AT90USB1287-AUR

Features • High performance, low power AVR® 8-bit Microcontroller • Advanced RISC architecture • • • • • • – 135 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 16MIPS throughput at 16MHz – On-chip 2-cycle multiplier Non-volatile program and data memories – 64/128Kbytes of in-system self-programmable flash • Endurance: 100,000 write/erase cycles – Optional Boot Code section with independent lock bits • USB boot loader programmed by default in the factory • In-system programming by on-chip boot program hardware activated after reset • True read-while-write operation • All supplied parts are pre-programed with a default USB bootloader – 2K/4K (64K/128K flash version) bytes EEPROM • Endurance: 100,000 write/erase cycles – 4K/8K (64K/128K flash version) bytes internal SRAM – Up to 64Kbytes optional external memory space – Programming lock for software security JTAG (IEEE std. 1149.1 compliant) interface – Boundary-scan capabilities according to the JTAG standard – Extensive on-chip debug support – Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface USB 2.0 full-speed/low-speed device and on-the-go module – Complies fully with: – Universal serial bus specification REV 2.0 – On-the-go supplement to the USB 2.0 specification rev 1.0 – Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s USB full-speed/low speed device module with interrupt on transfer completion – Endpoint 0 for control transfers: up to 64-bytes – Six programmable endpoints with in or out directions and with bulk, interrupt or isochronous transfers – Configurable endpoints size up to 256bytes in double bank mode – Fully independent 832bytes USB DPRAM for endpoint memory allocation – Suspend/resume interrupts – Power-on reset and USB bus reset – 48MHz PLL for full-speed bus operation – USB bus disconnection on microcontroller request USB OTG reduced host: – Supports host negotiation protocol (HNP) and session request protocol (SRP) for OTG dual-role devices – Provide status and control signals for software implementation of HNP and SRP – Provides programmable times required for HNP and SRP Peripheral features – Two 8-bit timer/counters with separate prescaler and compare mode – Two16-bit timer/counter with separate prescaler, compare- and capture mode 8-bit Atmel Microcontroller with 64/128Kbytes of ISP Flash and USB Controller AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 7593L–AVR–09/12 • • • • • 2 – Real time counter with separate oscillator – Four 8-bit PWM channels – Six PWM channels with programmable resolution from 2 to 16 bits – Output compare modulator – 8-channels, 10-bit ADC – Programmable serial USART – Master/slave SPI serial interface – Byte oriented 2-wire serial interface – Programmable watchdog timer with separate on-chip oscillator – On-chip analog comparator – Interrupt and wake-up on pin change Special microcontroller features – Power-on reset and programmable brown-out detection – Internal calibrated oscillator – External and internal interrupt sources – Six sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and packages – 48 programmable I/O lines – 64-lead TQFP and 64-lead QFN Operating voltages – 2.7 - 5.5V Operating temperature – Industrial (-40°C to +85°C) Maximum frequency – 8MHz at 2.7V - industrial range – 16MHz at 4.5V - industrial range AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 1. Pin configurations AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout Atmel AT90USB64/128-TQFP. 64 Figure 1-1. (INT.6/AIN.0) PE6 1 48 PA3 (AD3) (INT.7/AIN.1/UVcon) PE7 2 47 PA4 (AD4) 46 PA5 (AD5) INDEX CORNER UVcc 3 D- 4 45 PA6 (AD6) D+ 5 44 PA7 (AD7) UGnd 6 43 PE2 (ALE/HWB) UCap 7 42 PC7 (A15/IC.3/CLKO) VBus 8 41 PC6 (A14/OC.3A) 40 PC5 (A13/OC.3B) AT90USB90128/64 TQFP64 31 32 (T0) PD7 PE0 (WR) (T1) PD6 33 30 16 (XCK1) PD5 (PCINT6/OC.1B) PB6 29 PE1 (RD) (ICP1) PD4 34 28 15 (TXD1/INT3) PD3 (PCINT5/OC.1A) PB5 27 PC0 (A8) (RXD1/INT2) PD2 35 26 14 (OC2B/SDA/INT1) PD1 (PCINT4/OC.2A) PB4 25 PC1 (A9) (OC0B/SCL/INT0) PD0 36 24 13 XTAL1 (PDO/PCINT3/MISO) PB3 23 PC2 (A10) XTAL2 37 22 12 GND (PDI/PCINT2/MOSI) PB2 21 PC3 (A11/T.3) VCC 38 20 11 RESET (PCINT1/SCLK) PB1 19 PC4 (A12/OC.3C) (INT.5/TOSC2) PE5 39 18 10 (INT4/TOSC1) PE4 (SS/PCINT0) PB0 17 9 (PCINT7/OC.0A/OC.1C) PB7 (IUID) PE3 3 7593L–AVR–09/12 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout Atmel AT90USB64/128-QFN. 64 Figure 1-2. (INT.6/AIN.0) PE6 1 48 PA3 (AD3) (INT.7/AIN.1/UVcon) PE7 2 47 PA4 (AD4) 46 PA5 (AD5) 45 PA6 (AD6) UVcc 3 D- 4 D+ 5 44 PA7 (AD7) UGnd 6 43 PE2 (ALE/HWB) UCap 7 42 PC7 (A15/IC.3/CLKO) VBus 8 41 PC6 (A14/OC.3A) 40 PC5 (A13/OC.3B) 39 PC4 (A12/OC.3C) INDEX CORNER AT90USB128/64 (IUID) PE3 9 (SS/PCINT0) PB0 10 (PCINT1/SCLK) PB1 11 38 PC3 (A11/T.3) (PDI/PCINT2/MOSI) PB2 12 37 PC2 (A10) (PDO/PCINT3/MISO) PB3 13 36 PC1 (A9) (PCINT4/OC.2A) PB4 14 35 PC0 (A8) (PCINT5/OC.1A) PB5 15 34 PE1 (RD) (PCINT6/OC.1B) PB6 16 33 PE0 (WR) Note: 4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (PCINT7/OC.0A/OC.1C) PB7 (INT4/TOSC1) PE4 (INT.5/TOSC2) PE5 RESET VCC GND XTAL2 XTAL1 (OC0B/SCL/INT0) PD0 (OC2B/SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T0) PD7 (64-lead QFN top view) The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 2. Overview The Atmel® AVR® AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the Atmel® AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90USB64/128 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 5 7593L–AVR–09/12 Block diagram PF7 - PF0 VCC PC7 - PC0 PA7 - P A0 POR TA DRIVERS POR TF DRIVERS RESET Block diagram. XT AL2 Figure 2-1. XT AL1 2.1 POR TC DRIVERS GND DATA DIR. REG. PORT F DATA REGISTER PORT F DATA DIR. REG. PORT A DATA REGISTER PORT A DATA REGISTER PORT C DATA DIR. REG. PORT C 8-BIT DA TA BUS POR - BOD RESET AVCC INTERNAL OSCILLA TOR CALIB. OSC ADC AGND AREF JTAG TAP PROGRAM COUNTER ST ACK POINTER ON-CHIP DEBUG PROGRAM FLASH SRAM BOUNDARYSCAN INSTRUCTION REGISTER OSCILLA TOR WATCHDOG TIMER TIMING AND CONTROL MCU CONTROL REGISTER TIMER/ COUNTERS GENERAL PURPOSE REGISTERS X PROGRAMMING LOGIC INSTRUCTION DECODER CONTROL LINES Z INTERRUPT UNIT ALU EEPROM Y PLL ST ATUS REGISTER + - ANALOG COMP ARATOR USART1 USB SPI DATA DIR. REG. PORTE DATA REGISTER PORTE POR TE DRIVERS PE7 - PE0 DATA DIR. REG. PORTB DATA REGISTER PORTB POR TB DRIVERS PB7 - PB0 DATA REGISTER PORTD TWO-WIRE SERIAL INTERFACE DATA DIR. REG. PORTD POR TD DRIVERS PD7 - PD0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting 6 AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel AT90USB64/128 provides the following features: 64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 2K/4Kbytes EEPROM, 4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, one USART, a byte oriented 2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using the Atmel high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the AT90USB64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90USB64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 7 7593L–AVR–09/12 2.2 2.2.1 Pin descriptions VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 AVCC Analog supply voltage. 2.2.4 Port A (PA7..PA0) Port A is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the Atmel AT90USB64/128 as listed on page 78. 2.2.5 Port B (PB7..PB0) Port B is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the AT90USB64/128 as listed on page 79. 2.2.6 Port C (PC7..PC0) Port C is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the AT90USB64/128 as listed on page 82. 2.2.7 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90USB64/128 as listed on page 83. 8 AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 2.2.8 Port E (PE7..PE0) Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the AT90USB64/128 as listed on page 86. 2.2.9 Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bidirectional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.2.10 DUSB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB Dconnector pin with a serial 22Ω resistor. 2.2.11 D+ USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22Ω resistor. 2.2.12 UGND USB Pads Ground. 2.2.13 UVCC USB Pads Internal Regulator Input supply voltage. 2.2.14 UCAP USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF). 2.2.15 VBUS USB VBUS monitor and OTG negociations. 2.2.16 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page 58. Shorter pulses are not guaranteed to generate a reset. 2.2.17 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 9 7593L–AVR–09/12 2.2.18 XTAL2 Output from the inverting oscillator amplifier. 2.2.19 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.2.20 AREF This is the analog reference pin for the A/D Converter. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 10 AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 5. AVR CPU core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural overview Figure 5-1. Block diagram of the AVR architecture. Data bus 8-bit Flash program memory Program counter Status and control 32 x 8 general purpose registrers Control lines Direct addressing Instruction decoder Indirect addressing Instruction register Interrupt unit SPI unit Watchdog timer ALU Analog comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Re-programmable Flash memory. 11 7593L–AVR–09/12 The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel AT90USB64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction set summary” on page 423 for a detailed description. 12 AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 5.4 Status register The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR status register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 I T H S V N Z C Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction set summary” on page 423 for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction set summary” on page 423 for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction set summary” on page 423 for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction set summary” on page 423 for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction set summary” on page 423 for detailed information. 13 7593L–AVR–09/12 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction set summary” on page 423 for detailed information. 5.5 General purpose register file The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 5-2. AVR CPU general purpose working registers. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E purpose R15 0x0F working R16 0x10 registers R17 0x11 … R26 0x1A R27 0x1B X-register Low byte X-register High byte R28 0x1C Y-register Low byte R29 0x1D Y-register High byte R30 0x1E Z-register Low byte R31 0x1F Z-register High byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 5-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. 5.5.1 14 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-3. AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 Figure 5-3. The X-, Y-, and Z-registers. 15 XH XL 7 X-register 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 Stack pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit Read/write Initial value 15 14 13 12 11 10 9 SP15 SP14 SP13 SP12 SP11 SP10 SP9 8 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 15 7593L–AVR–09/12 5.6.1 RAMPZ - Extended Z-pointer register for ELPM/SPM Bit 7 6 5 4 3 2 1 0 RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 5-4. Note that LPM is not affected by the RAMPZ setting. Figure 5-4. Bit (individually) The Z-pointer used by ELPM and SPM. 7 0 7 RAMPZ Bit (Z-pointer) 23 0 7 ZH 16 0 ZL 15 8 7 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 5.7 Instruction execution timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 5-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5-5. The parallel instruction fetches and instruction executions. T1 T2 T3 T4 clkCPU 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch Figure 5-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. 16 AT90USB64/128 7593L–AVR–09/12 AT90USB64/128 Figure 5-6. Single cycle ALU operation. T1 T2 T3 T4 clkCPU Total execution time Register operands fetch ALU operation execute Result write back 5.8 Reset and interrupt handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory programming” on page 359 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 68. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 68 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory programming” on page 359. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. 17 7593L–AVR–09/12 Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly code example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C code example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1