AT91RM9200-EK Evaluation Board
..............................................................................................
User Guide
Table of Contents
Section 1
Overview ............................................................................................... 1-1
1.1
1.2
1.3
Scope ........................................................................................................1-1
Deliverables ..............................................................................................1-2
The AT91RM9200-EK Evaluation Board ..................................................1-3
Section 2
Setting Up the AT91RM9200-EK
Evaluation Board .................................................................................. 2-1
2.1
2.2
2.3
2.4
Electrostatic Warning ................................................................................2-1
Requirements............................................................................................2-1
Powering Up the Board .............................................................................2-1
Getting Started with the AT91RM9200 .....................................................2-1
Section 3
Board Description ................................................................................. 3-1
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
AT91RM9200 Processor...........................................................................3-1
Memory .....................................................................................................3-2
Memory Card ............................................................................................3-2
Clock Circuitry and Analog Functions .......................................................3-2
Reset Circuitry...........................................................................................3-2
Power Supply Circuitry..............................................................................3-2
Remote Communication............................................................................3-2
User Interface ...........................................................................................3-2
Expansion Slot ..........................................................................................3-3
Debug Interface ........................................................................................3-3
Wrapping User Area..................................................................................3-3
Section 4
Configuration Straps ............................................................................. 4-1
4.1
Configuration Straps and Jumper Settings ...............................................4-1
Section 5
Schematics ........................................................................................... 5-1
5.1
Schematics ...............................................................................................5-1
Section 6
Errata .................................................................................................... 6-1
6.1
Errata ........................................................................................................6-1
6.1.1
AT91RM9200-EK Evaluation Board User Guide
SD/MMC Card slot communication problem ......................................6-1
1
6103C–ATARM–05-Jan-06
Table of Contents
2
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Overview
Section 1
Overview
1.1
Scope
The AT91RM9200-EK Evaluation Board enables real-time code development and evaluation. It supports the AT91RM9200 ARM9™-based 32-bit RISC microcontroller.
This guide focuses on the AT91RM9200-EK Evaluation Board as an evaluation and
demonstration platform:
! Section 1 is this overview.
! Section 2 gives information on setting up the installation.
! Section 3 contains a description of the development board.
! Section 4 details the configuration straps.
! Section 5 shows board schematics.
! Section 6 contains errata.
AT91RM9200-EK Evaluation Board User Guide
1-1
6103C–ATARM–05-Jan-06
Overview
1.2
Deliverables
The development kit is delivered with:
! One AC adapter 100 - 240V ~ 1.2A, 12V, 50 - 60 Hz with adapters
! One modem RS232 cable
! One RJ45 Ethernet crossed cable
! One A/B-type USB cable
! One AT91 DVD-ROM containing summary and full datasheets, datasheets with
electrical and mechanical characteristics, application notes and getting started
documents for all development boards and AT91 microcontrollers. An AT91 software
package with C and assembly listings is also provided. This allows the user to begin
evaluating the AT91 ARM® Thumb® 32-bit microcontroller quickly.
! CD ROMs from third parties, providing solutions for operating system evaluation
! DataFlash® Cards to provide demonstrations of operating systems when inserted in
the bootable slot
Note:
To boot on a DataFlash Card:
- Ensure J15 (BMS) is set on position 1-2
- Insert the DataFlash Card in the J200 socket (bottom side)
- Reset the board
Further details are given on the AT91 DVD-ROM.
Note:
1-2
6103C–ATARM–05-Jan-06
These deliverables are subject to change without notice.
AT91RM9200-EK Evaluation Board User Guide
Overview
1.3
The
The board consists of an AT91RM9200 together with the following:
AT91RM9200-EK ! 8 Mbytes of parallel Flash memory
Evaluation Board
! Four banks of 2M x 32-bit SDRAM
! DataFlash® or SD/MMC memory expansion socket
! Additional DataFlash memory expansion socket
! Digital-to-Analog Converter (DAC) for a stereo audio signal
! Four communication ports (USB host and device, Ethernet, serial and DBGU)
! Graphic controller with output to a standard VGA monitor
! JTAG/ICE, ETM and code test port interface
! Expansion connector
! Onboard prototype area
AT91RM9200-EK Evaluation Board User Guide
1-3
6103C–ATARM–05-Jan-06
Overview
Figure 1-1. AT91RM9200-EK Evaluation Board Block Diagram
LCD Panel
Slot
LCD Panel
Slot
VGA Connector
16
Flash
Graphic Display
Controller
32
Expansion Slot
Clock
Controller
DataFlash Card
Socket
SDRAM
Ethernet
Port
Ethernet
PHY
LED LED LED
25
ICE Debug Port
EBI
USB Host
Port
SPI
EMAC
UHP
ETM
Trace Port
AT91RM9200
USB Device
Port
JTAG
DBGU
UDP
RS232 Driver
NRST
MCI or
SPI
Oscillator, PLL
and Reset
DataFlash Card/
SDCard
Socket
USART
TWI
Code Test Port
DC
Input
Power
Supply
RS232
Driver
Digital-to-Analog
Converter
Stereo Output
1-4
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Section 2
Setting Up the AT91RM9200-EK
Evaluation Board
2.1
Electrostatic
Warning
The AT91RM9200-EK Evaluation Board is shipped in protective anti-static packaging.
The board must not be subjected to high electrostatic potentials. A grounding strap or
similar protective device should be worn when handling the board. Avoid touching the
component pins or any other metallic element.
2.2
Requirements
In order to connect the AT91RM9200-EK Evaluation Board, the following element is
required:
! The AT91RM9200-EK Evaluation Board itself
2.3
Powering Up the
Board
DC power is supplied to the board via the 2.1 mm socket (J1). The polarity of the power
supply is not critical. The minimum voltage required is 7V.
The board has three voltage regulators providing 1.8V, 3.3V and 5V. The regulators
allow the input voltage range to be from 7V to 12V.
2.4
Getting Started
with the
AT91RM9200
The AT91RM9200-EK Evaluation Board is delivered with a DVD-ROM containing all
necessary information and step-by-step procedures for working with the most common
development tool chains. Please refer to this DVD-ROM, or to the AT91 web site,
http://www.atmel.com/products/AT91/ for the most up-to-date information on getting
started with the AT91RM9200.
AT91RM9200-EK Evaluation Board User Guide
2-1
Rev. 6103C–ATARM–05-Jan-06
Setting Up the AT91RM9200-EK Evaluation Board
2-2
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Section 3
Board Description
3.1
AT91RM9200
Processor
! Incorporates the ARM920T™ ARM® Thumb® Processor
– 200 MIPS at 180 MHz
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– Memory Management Unit
– In-circuit Emulator including Debug Communication Channel
– Mid-level Implementation Embedded Trace Macrocell™
! Additional Embedded Memories
– 16K Bytes of SRAM and 128K Bytes of ROM
! External Bus Interface (EBI)
– Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to
CompactFlash®, SmartMedia® and NAND Flash
! System Peripherals:
– Enhanced Clock Generator and Power Management Controller
– Two On-chip Oscillators with Two PLLs
– Very Slow Clock Operating Mode and Software Power Optimization
Capabilities
– Four Programmable External Clock Signals
– System Timer Including Periodic Interrupt, Watchdog and Second Counter
– Real-time Clock with Alarm Interrupt
– Debug Unit, Two-wire UART and Support for Debug Communication Channel
– Advanced Interrupt Controller with 8-level Priority, Individually Maskable
Vectored Interrupt Sources, Spurious Interrupt Protected
– Seven External Interrupt Sources and One Fast Interrupt Source
– Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input
Change Interrupt and Open-drain Capability on Each Line
– 20-channel Peripheral DMA Controller (PDC)
! Ethernet MAC 10/100 Base-T
! USB 2.0 Full Speed (12 M-bits per second) Host Double Port and Device Port
AT91RM9200-EK Evaluation Board User Guide
3-1
Rev. 6103C–ATARM–05-Jan-06
Board Description
! MultiMedia Card Interface (MCI)
! Three Synchronous Serial Controllers (SSC)
! Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
! Master/Slave Serial Peripheral Interface (SPI)
! Two 3-channel, 16-bit Timer/Counters (TC)
! Two-wire Interface (TWI)
! IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
3.2
Memory
! 8-Mbyte parallel Flash memory
! Four banks of 2M x 32-bit SDRAM
3.3
Memory Card
! SD Card/MMC
– Supports MultiMedia and SD Card
– Analog switches provide support for DataFlash® Card
! Additional DataFlash Card Socket
Clock Circuitry
and Analog
Functions
! 32.768 kHz standard crystal for the AT91RM9200
3.5
Reset Circuitry
! Reset Controller
3.6
Power Supply
Circuitry
! 5V DC/DC converter
3.4
! 18.432 MHz standard crystal for the AT91RM9200
! 50 MHz CMOS oscillator for the Display Controller and Ethernet PHY
! 3.3V DC/DC converter
! 1.8V Linear regulator
3.7
Remote
Communication
! Fast Ethernet Physical Layer Single Chip Transceiver
! Host Interface via RS-232 DB9 male socket
! Debug Port via RS-232 DB9 connector
! Host and Device USB socket
3.8
User Interface
! Graphic Display Controller
! TFT/SNT panel socket
3-2
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Board Description
! 15-pin standard socket for an external VGA monitor
! Three LEDs managed via general PIO lines
! Stereo Audio Jack connected to a DAC
3.9
Expansion Slot
! The expansion slot gives access to all the microcontroller’s signals.
3.10
Debug Interface
! 38-pin trace Port socket (ETM)
! 38-pin Code Test port socket
! 20-pin JTAG ICE interface connector
! Serial Debug Unit
3.11
Wrapping User
Area
! Onboard prototype area allowing the developer to fit additional components.
AT91RM9200-EK Evaluation Board User Guide
3-3
6103C–ATARM–05-Jan-06
Board Description
3-4
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Section 4
Configuration Straps
4.1
Configuration
Straps and
Jumper Settings
Table 4-1 gives details on configuration straps and jumper settings on the
AT91RM9200-EK Evaluation Board and their default settings.
Table 4-1. Configuration Straps and Jumper Settings
Designation
Default
Setting
Feature
J13
Closed
Available for measuring VDDCORE current.
1-2
The AT91RM9200 boots from internal ROM and can also boot
from external SPI DataFlash® connected on NPCS0.
2-3
The AT91RM9200 boots from Flash memory connected on NCS0.
J15
AT91RM9200-EK Evaluation Board User Guide
4-1
Rev. 6103C–ATARM–05-Jan-06
Configuration Straps
4-2
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Section 5
Schematics
5.1
Schematics
This section contains the following schematics:
! AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Top View
! AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Bottom View
! Power Supply
! AT91RM9200 Chip
! Debug
! SDRAM and Flash
! RMII Ethernet
! Stereo Audio DAC
! Serial Interfaces
! VGA Display
! Expansion Connector
AT91RM9200-EK Evaluation Board User Guide
5-1
Rev. 6103C–ATARM–05-Jan-06
Schematics
Figure 5-1. AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Top View
5-2
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Schematics
Figure 5-2. AT91RM9200-EK Board Layout, Rev. 63PC042262A01 - Bottom View
AT91RM9200-EK Evaluation Board User Guide
5-3
6103C–ATARM–05-Jan-06
8
D
7
6
5
4
2
1
D
TP10
12V DC INPUT
R248
0R100
3V3
I limit = 0.1V / R ... about 2.9A
CR1
1V8
F1
STPS340U
3
J1
MP179_2.1mm
1
2
3
C256
2.2µF
2A
R257
0R100
TP17
TP11
+ C18
470uF
25V
3V3
U4
5
V+
1
8
2
7
3
6
L3
22uH
3.8A
+
C22
220uF
16V
C12
100NF
3
SHDN
2
3/5
4
REF
8
CS
EXT
GND
OUT
7
4
3
4
VIN
VIN
1
2
GND
EN
5
+
Q201
IRF7425
1
+
CR8
3.3 V
+
CR7
STPS340U
MAX1626ESA
R35
1K
1%
C300
100NF
U12
6
VOUT
VOUT
6
5
RES/PG
8
FB/NC
7
NTRST
TPS77518D
R288
4K7
C255
2.2µF
C254
100NF
C25
220uF
16V
C
C24
220uF
16V
C
C23
220uF
16V
R244
0R100
I limit = 0.1V / R ... about 2.9A
R245
C221
2.2µF
0R100
U1
5
5V
V+
8
2
7
3
6
L1
22uH
3.8A
+
1
C2
220uF
16V
3
C3
100NF
SHDN
2
3/5
4
REF
8
GND
CS
6
EXT
7
OUT
4
TP3
5
+
1
Q200
IRF7425
+
+
C233
2.2µF
CR5
MAX1626ESA
STPS340U
C21
220uF
16V
C232
100NF
B
B
C20
220uF
16V
C19
220uF
16V
Z6
Z3 - Z5 are mounting holes.
The Z reference designators
are not listed on the actual
board.
Z9
Z8
Z10
GUARD RING
TP2
Z4
Z5
Z3
A
Z13
Z7
TM
1
1
TM
TM
1
1
TM
TM
1
Z11
Z2
Z12
TP18
Z1
TP1
A
Wednesday, February 23, 2005
R227
0R
TP5
B 101-3-05-106
A INIT EDIT
REV
AT91RM9200-EK
NORMALLY CLOSED
POWER SUPPLY
MODIF.
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MDZ
23/02/05
04/01/05
JPG
JPG
DES.
DATE
VER.
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REV.
SHEET
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This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
1
9
8
7
6
5
4
3
2
1
PB[0..29]
PB29
PB28
PB27
PB26
PB25
PB24
PB23
PB22
PB21
PB20
PB19
PB18
PB17
PB16
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC15
PC14
PC13
PC12
PC11
PC10
PC6
PC5
PC4
PC3
PC2
PC1
PC0
J6
J5
G6
G4
F4
F5
F3
C4
B4
A3
C5
B3
A4
F7
E7
D7
C7
C8
F9
B8
A8
D9
E9
C9
B9
A9
E10
D10
C10
B10
L13
M17
M13
N17
N16
L12
K15
K13
K14
L15
L14
M14
M15
D[0..31]
DDP
DDM
HDPA
HDMA
K1
K3
HDPA
HDMA
HDPB
HDMB
L2
L3
HDPB
HDMB
TDI
TMS
TCK
A1
C1
E5
TDI
TMS
TCK
TDO
NTRST
B1
E2
A2
TDO
NTRST
JTAGSEL
H13
VDDPLLB
H15
GNDPLLB
F17
PLLRCB
K17
XOUT
Y3
18.4320MHz
J17
XOUT32
J15
VDDPLLA
J16
GNDPLLA
R38
47K
1
PA31
BOOT MODE SELECT
1-2: BMS=Hight=Internal Boot
1-3: BMS=Low=External Boot from NCS0
J15
2
3
R39
470R
B
RAS
CAS
CR10
BAT54-7
SDWE
SDA10
SDCKE
SDCK
BFCS/NCS0
SDCS/NCS1
NCS2
SMCS/NCS3
CFOE/NOE/NRD
U6
M9
T6
R7
N9
BFCS_NCS0
SDCS
NCS2
SMCS_NCS3
CFOE_NOE_NRD
CFWE/NWE/NWR0
CFIOR/NBS1/NWR1
CFIOW/NBS3/NWR3
P8
T7
R8
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
NRST
E1
TST1
TST0
D1
E4
VDDIOP
VDDIOP
100NF
100NF
100NF
C315
C281
C296
H5
VDDIOP
100NF
C314
D3
VDDIOP
100NF
C305
D2
VDDIOP
A7
D5
100NF
C29
VDDIOP
VDDIOP
100NF
C311
D8
100NF
C290
VDDIOP
100NF B11
C38
VDDIOP
100NF A11
C294
VDDIOP
100NF A16
C32
VDDIOM
100NF H14
C282
VDDIOM
100NF R14
C310
VDDIOM
100NF R10
VDDIOM
C304
T5
100NF
VDDIOM
C316
R6
100NF
VDDIOM
VDDIOM
C37
P4
100NF
C306
M1
100NF
C307
VDDIOM
100NF K16
C39
VDDIOM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M12
P17
M16
J12
H16
C15
A14
C11
D11
B7
E8
E6
D4
E3
F2
G3
L1
L5
M2
R1
U2
R2
M7
U5
T9
N12
T13
VDDCORE
VDDCORE
VDDCORE
VDDCORE
T2
U1
100NF R17
VDDPLL
C43
0R
100NF P16
R289
C301
100NF
C30
VDDOSC
100NF T10
0R
C309
R290
100NF
C302
10 uF
10V
C303
CR9
STPS1L30U
2
100NF
J13
1
A
C308
PLLRCA
VDDCORE
L17
C284
680pF
1V8
N10
U8
3V3
3
C325
100NF
3V3
1K
1K
R300
1%
U10
1
GND
2
RESET
VCC
4
MR
3
RESET
MAX6390XS29D4-T
1%
R291
1K
R293
1%
3V3
NRST
3V3
A
Monday, March 21, 2005
C295
10 uF
10V
AT91RM9200-EK
AT91RM9200
A01101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
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JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
NRST
S1
F6
1K27
1%
XIN32
100NF
R284
GNDOSC
G17
VDDPLL
C285
100NF
C283
5.6NF
J13
H17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
D
C
T8
N6
P9
U7
Y4
32.768 kHz
4
C291
10PF
VDDOSC
100NF C14
1
C288
10PF
J14
N1
M4
M6
M3
N4
N2
L4
P1
N7
N3
M5
P5
P3
P2
N5
T1
U3
T3
R3
U4
R4
N8
P6
T4
R5
P7
A[0..25]
SDWE
SDA10
SDCKE
SDCK
XIN
VDDIOP
VDDOSC
C280
100NF
RAS
CAS
C286
C287
10PF
2
B
0R
1
R285
C273
10PF
VDDIOP
1K96
1%
U11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
L6
R286
C293
470pF
AT91RM9200
C279
C292
4.7NF
NBS0/A0
NWR2/NBS2/A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BA0/A16
BA1/A17
A18
A19
A20
A21
A22
PC7/A23
PC8/A24
CFRNW/PC9/A25
K4
VDDPLL
C31
100NF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
PC16/D16
PC17/D17
PC18/D18
PC19/D19
PC20/D20
PC21/D21
PC22/D22
PC23/D23
PC24/D24
PC25/D25
PC26/D26
PC27/D27
PC28/D28
PC29/D29
PC30/D30
PC31/D31
R9
P10
N11
U9
M11
P11
U10
U11
R11
T11
P12
U12
T12
R12
U13
P13
U14
R13
U15
T14
U16
T15
U17
T16
R15
T17
P14
P15
N13
R16
N15
N14
2
K5
K2
VDDCORE
0R
DDP
DDM
100NF L16
R292
PD0/ETX0
PD1/ETX1
PD2/ETX2
PD3/ETX3
PD4/ETXEN
PD5/ETXER
PD6/DTXD
PD7/PCK0/TSYNC
PD8/PCK1/TCLK
PD9/PCK2/TPS0
PD10/PCK3/TPS1
PD11/TPS2
PD12/TPK0
PD13/TPK1
PD14/TPK2
PD15/TD0/TPK3
PD16/TD1/TPK4
PD17/TD2/TPK5
PD18/NPCS1/TPK6
PD19/NPCS2/TPK7
PD20/NPCS3/TPK8
PD21/RTS0/TPK9
PD22/RTS1/TPK10
PD23/RTS2/TPK11
PD24/RTS3/TPK12
PD25/DTR1/TPK13
PD26/TPK14
PD27/TPK15
C289
C
E17
F15
F14
E16
D17
C17
D16
D6
A6
B6
C6
A5
B5
B2
C3
C2
F1
G2
G5
G1
H2
H4
H3
H1
J3
J1
J4
J2
HOLDA/PC15
HOLD/PC14
NCS7/PC13
CFCE2/NCS6/PC12
CFCE1/NCS5/PC11
CFCS/NCS4/PC10
NWAIT/PC6
BFWE/PC5
BFOE/PC4
SMWE/BFBAA/PC3
BFAVD/PC2
SMOE/BFRDY/PC1
BFCK/PC0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
IRQ0/PB29
FIQ/PB28
PCK0/PB27
RTS1/PB26
EF100/DSR1/PB25
CTS1/PB24
DCD1/PB23
SCK1/PB22
RXD1/PB21
TXD1/PB20
RXCK/DTR1/PB19
ECOL/RI1/PB18
ERXDV/RF2/PB17
ERX3/RK2/PB16
ERX2/RD2/PB15
ETXER/TD2/PB14
ETX3/TK2/PB13
ETX2/TF2/PB12
TIOB5/RF1/PB11
TIOA5/RK1/PB10
TIOB4/RD1/PB9
TIOA4/TD1/PB8
TIOB3/TK1/PB7
TIOA3/TF1/PB6
MCDA3/RF0/PB5
MCDA2/RK0/PB4
MCDA1/RD0/PB3
SCK3/TD0/PB2
CTS3/TK0/PB1
RTS3/TF0/PB0
D
RTS2/DTXD/PA31
CTS2/DRXD/PA30
TCLK5/MCDA0/PA29
TCLK4/MCCDA/PA28
TCLK3/MCCK/PA27
IRQ1/TWCK/PA26
IRQ2/TWD/PA25
PCK1/SCK2/PA24
IRQ3/TXD2/PA23
TIOB2/RXD2/PA22
TIOA2/RTS0/PA21
TIOB1/CTS0/PA20
TIOA1/SCK0/PA19
TIOB0/RXD0/PA18
TIOA0/TXD0/PA17
IRQ6/EMDIO/PA16
TCLK2/EMDC/PA15
TCLK1/ERXER/PA14
TCLK0/ERX1/PA13
MCDB3/ERX0/PA12
MCDB2/ERXDV/PA11
MCDB1/ETX1/PA10
MCDB0/ETX0/PA9
MCCDB/ETXEN/PA8
EXTCK/PCK2/PA7
RXD3/NPCS3/PA6
TXD3/NPCS2/PA5
PCK1/NPCS1/PA4
IRQ5/NPCS0/PA3
IRQ4/SPCK/PA2
PCK0/MOSI/PA1
PCK3/MISO/PA0
PD[0..27]
1
PA31
PA30
PA29
PA28
PA27
PA26
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PC[0..15]
A10
F11
E11
F12
G12
E12
E13
B12
A12
D12
D13
C12
A13
C13
B13
D14
B14
A15
A17
B16
B15
D15
E14
C16
B17
E15
F16
F13
G16
G15
G14
G13
PA[0..31]
7
6
5
4
3
2
1
23/02/05
06/01/05
2
9
8
7
6
5
PD[0..27]
4
3
2
1
PC[0..15]
D[0..31]
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D
D
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
CODETEST
PORT
J12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
NCS7
A1
A3
PC13
C
R294
0R
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CT_CLK
A2
A4
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
R295
0R
PD8
C
G1
G2
G3
G4
G5
A[0..25]
A1
A2
A3
A4
ETM
TRACE PORT
J16
B
10K
10K
10K
10K
3V3
R309
10K
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
R305
R306
R307
R308
J18
C323
100NF
3V3
R302
10K
NTRST
TDI
TMS
TCK
TDO
PD9
PD10
PD11
PD7
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
3V3
PIPESTAT[0]
PIPESTAT[1]
PIPESTAT[2]
TRACESYNC
TRACEPKT[0]
TRACEPKT[1]
TRACEPKT[2]
TRACEPKT[3]
TRACEPKT[4]
TRACEPKT[5]
TRACEPKT[6]
TRACEPKT[7]
VSUPPLY
EXTTRIG
NRST
PD8
R299
R310
0R
0R
C320
100NF
C319
100NF
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
TRACEPKT[8]
TRACEPKT[9]
TRACEPKT[10]
TRACEPKT[11]
TRACEPKT[12]
TRACEPKT[13]
TRACEPKT[14]
TRACEPKT[15]
NTRST
TDI
TMS
TCK
TDO
NSRST
DBGRQ
GND
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
B
SYSTEM RESET
R297
0R
NRST
R298
10K
G1
G2
G3
G4
G5
ICE INTERFACE
TRACECLK
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
A
A
Monday, March 21, 2005
AT91RM9200-EK
ETM - ICE - TEST
A01 101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
JPG
JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
3
9
8
7
6
5
4
3
2
1
EBI SDRAM INTERFACE
A[0..25]
D[0..31]
RAS
CAS
D
D
SDWE
SDA10
SDCKE
SDCK
16
19
C33
100NF
15
39
CAS
RAS
17
18
SDWE
16
19
C34
100NF
128 Mbits
28
41
54
6
12
46
52
100NF
NBS2
A1
CFIOW_NBS3_NWR3
C
100NF
38
100NF
37
SDCK
3V3
100NF
SDCKE
1
14
27
3
9
43
49
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
C45
SDWE
36
40
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
C313
17
18
20
21
A0
MT48LC8M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
N.C
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
C299
CAS
RAS
28
41
54
6
12
46
52
23
24
25
26
29
30
31
32
33
34
22
35
C278
15
39
100NF
NBS0
A0
CFIOR_NBS1_NWR1
100NF
38
C46
SDCK
BA0
BA1
A14
3V3
C44
37
A16
A17
100NF
SDCKE
C
1
14
27
3
9
43
49
SDA10
A13
100NF
36
40
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
C41
A14
20
21
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
C35
BA0
BA1
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
100NF
A16
A17
U200
A0
MT48LC8M16A2 DQ0
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
DQ8
A9
DQ9
A10
DQ10
A11
DQ11
DQ12
BA0
DQ13
BA1
DQ14
DQ15
N.C
N.C
VDD
VDD
CKE
VDD
VDDQ
CLK
VDDQ
VDDQ
DQML
VDDQ
DQMH
VSS
CAS
VSS
RAS
VSS
VSSQ
VSSQ
WE
VSSQ
CS
VSSQ
C40
SDA10
A13
23
24
25
26
29
30
31
32
33
34
22
35
100NF
U13
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDCS
C277
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
C312
100NF
C298
100NF
128 Mbits
D[0..31]
A[0..25]
U201
B
3V3
R32
47K
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
15
10
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
10K
12
11
13
14
26
28
RESET
WE
VPP
WP
CE
OE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
B
AT49BV6416-70TI
3V3
NRST
CFWE_NWE_NWR0
R33
BFCS_NCS0
CFOE_NOE_NRD
0R
3V3
3V3
R31
A
VCCQ
VCC
47
37
GND
GND
46
27
C28
100NF
C27
100NF
A
Monday, March 21, 2005
AT91RM9200-EK
SDRAM & FLASH
A01 101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
JPG
JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
4
9
8
7
6
5
4
3
2
1
3V3
3V3
Y1
R20
10K
1 OE
VDD 4
C13
100NF
50 MHz
2 VSS
OUT 3
SG-8002JC-50.0000M-PCB
D
R15
D
0R
L201
742792093
PA[0..31]
1
VCCA
2
C228
100NF
PC[0..15]
C227
100NF
L200
742792093
1
VCCA
REFCK
42
REF_CLK/XT2
PA10
PA9
PA8
ETX1
ETX0
ETXEN
17
18
19
20
21
22
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
PA13
PA12
R12
3V3
PA11
10K
ECRSDV
C
PA14
ERXER
R14
3V3
PA15
PA16
PC4
EMDC
EMDIO
IRQ
R10
R11
10K
0R
0R
R13
2K2
7
36
35
COL/RMII
CRS/ADR4
24
25
32
MDC
MDIO
MDINTR
DM9161E
3V3
R228
4
R229
2
AVDD
9
5
6
46
47
41
DVDD
39
DVDD
BGRESG
C226
100NF
30
DVDD
C229
100NF
23
DVDD
C225
49R9
1%
PWRDWN
BGRES
48
FDX/COLLED/OP0
SPEEDLED/OP1
LINK/ACTLED/OP2
CABLESTS/LINKSTS
11
12
13
14
SD
45
RESET
TX-
2
7 RD+
RX+
3
RX-
6
8 RD-
100NF
100V
C219
100NF
100V 4
C6
100NF
C5
100NF
C4
100NF
75
75
5
R207
10K
R212
10K
R213
10K
OP0
DS1
RECEIVE STATUS
SUPER YELLOW
270R
1
2
1
OP1
DISPLAY SPEED STATUS
GREEN = 100 Mb
OP2
DNP
NOT INSTALLED
R234
DNP
ACT LED
GREEN
R237
R214
270R
DS3
R211
270R
NOT INSTALLED
R232
DNP
R208
NOT INSTALLED
B
DNP
R242
10K
VCCA
OP2 OP1 OP0
C215
10 uF
10V
2
L203
742792093
VCCA
3V3
DNP
DNP
C230
100NF
7
8
R3
47K
VCCA
4
J0026D21
3V3
L202
742792093
75
75
DS5
3V3
C
5
1nF
3V3
R226
6K8
1%
DGND
DGND
DGND
2 TD-
VCCA
AVDD
100NF
49R9
1%
1
6 CT
AVDD
C224
40
3
TX+
3 CT
100NF
100V
8
1
AGND
AGND
AGND
10
1 TD+
C217
100NF
0R
R231
49R9
1%
J2
C223
NRST
B
TX+
16
38
15
33
44
R9
43
TXRXD3/ADR3
RXD2/ADR2
RXD1/ADR1
RXD0/ADR0
RX+
RX_EN
RX_CLK/SCRAMEN/10BTSER
RX_DV/TESTMODE
RXTX_ER/TXD4
RX_ER/RXD4/RPTR
26
27
28
29
31
34
37
ERX1
ERX0
XT1
2
C218
100NF
16
PA7
R230
49R9
1%
15
U3
R209
C220
10µF
R215
R210
NOT INSTALLED
C231
100NF
VCCA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Dual speed 100/10 HDX
Reserved
Reserved
Manually select 10TX HDX
Manually select 10TX FDX
Manually select 100TX HDX
Manually select 100TX FDX
Auto negociation enables all capabilities (default)
R243
0R
Triple Light pipe, 5mm.
Install if putting board
into case.
LP2
LPF-C031304S
NOT INSTALLED
A
A
Monday, March 21, 2005
AT91RM9200-EK
ETHERNET
A01 101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
JPG
JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
5
9
8
7
6
5
4
3
2
1
L2
742792093
2
3V3
D
C205
100NF
C204
100NF
C16
100NF
C9
100NF
10
U2
9
AVDD1
R204
R1
15K
R218
15K
R2
15K
15K
C202
330PF
C
DNP
TP6
DNP
TP12
DNP
TP13
DNP
TP15
PB[0..29]
PB6
PB8
PB7
R238
R240
R239
TF1
TD1
TK1
0R
0R
0R
NRST
LP1
3V3
Triple Light pipe, 10mm.
Install if putting board
into case.
10K
AVDD0
VDD
5
7
37
FOUTL
DEEMR
35
38
FOPL
DEEML
34
39
FINL
MCS2
20
R219
10K
MCS1
19
R220
10K
SDA
16
SCL
15
FOUTR
42
FOPR
43
FINR
DAC3550A
32
AUX1R
31
AUX1L
30
AUX2R
29
AUX2L
27
25
24
23
TESTEN
WSI
DAI
CLI
26
PORQ
R241
10K
XTI 12
XTI
R221
10K
XTO 13
XTO
AGNDC
44
3V3
OUT_L
OUT_R
41
1
AVSS1
2
AVSS0
3
J5
5
4
3
2
1
C11
150uF
16V
DEECTRL
VREF
3V3
LINE OUT
21
LPF-C031303S
NOT INSTALLED
B
D
C14
10 uF
10V
18
C1
330PF
R217
C15
100NF
+
C10
10µF
+
1
3V3
CLKOUT
14
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
4
6
8
11
22
28
33
36
40
TP4
DNP
TP7
DNP
TP8
DNP
TP9
DNP
C17
150uF
16V
R201
1K5
1%
R203
47R
R200
47R
ST-3081-5N
R202
1K5
1%
TWD
C
TWCK
TP14
DNP
B
VSS
17
3V3
C203
3.3µF
USER LED 1
USER LED 2
USER LED 3
PB[0..29]
DS2
GREEN
PB0
R236
DS4
SUPER YELLOW
DS6
RED
220R
R216
PB1
R235
0R
220R
GND AUDIO
PB2
A
R233
220R
A
Monday, March 21, 2005
AT91RM9200-EK
I2S STEREO DAC
A01 101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
JPG
JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
6
9
PA[0..31]
PB[0..29]
R304
CD1 SW
CD1 SW
MCI8
MCI7
MCDA1
3 NO1
MCI1
D
PA6
PB22
PA28
MMC_CS
MMC_TYPE
MMC_CMD
MCI2
PA1
MOSI
5V
C318
100NF
NC4
MISO
14
4 CO1
CO4 12
MCI7
2 NC1
NO4 13
MCDA0
MCI5
3V3
1 IN
MCI2
MCI1
MCIA9
MCDA2
12
11
10
8
7
6
5
4
3
2
1
9
C258
100NF
SPCK
7 CO2
CO3 9
MCI5
5 NC2
NO3 10
R259
PA31
4K7
16 V+
EN_B
C276
100NF
PB[0..29]
PA27
J200
CD1 SW
CD1 SW
PB10
MISO
PA2
SPCK
SPCK
3V3
PA1
PA3
MOSI
NPCS0
MOSI
NPCS0
15
V+
2
V-
6
C26
100NF
J10
C260
100NF
C259
100NF
SERIAL DEBUG PORT
1
6
2
7
3
8
4
9
5
RXD
14
TXD
7
T
R
13
9
R
8
R260
4K7
3V3
U14
28
C275
100NF
C
1
D
ADM3202ARN
SD CARD / MMC CARD OR
DATA FLASH INTERFACE
R303
4K7
8 GND
GND
12
R258
0R
15
16
T
10
PA30 DBGU_RXD
PI5A100Q
PA0
11
DBGU_TXD
C321
100NF
MMC_CLK
VCC
5 C2-
FPS009-2405-0
NO2
NC3 11
6
R311 10K
3 C14 C2+
PA[0..31]
2
3V3
U8
1 C1+
C257
100NF
J17
MCDA3
3
0R
U15
PB5
4
11
PA2
PA17
PA29
PA0
PB27
PB3
PB4
5
12
11
10
8
7
6
5
4
3
2
1
9
C1+
24
1
GND
C1C2+
V+
27
2
C2-
V-
3
T1OUT
9
T2OUT
10
RTS1
14
T1IN
PB20
TXD1
13
T2IN
12
T3IN
DTR1
PB23
DCD1
26
25
PB26
PB19
VCC
T
T
T3OUT
RIGHT ANGLE MALE SUBD
C42
100NF
J14
C274
100NF
RS232 COM PORT
DCD
DSR
RXD
RTS
TXD
CTS
DTR
RI
C297
100NF
1
6
2
7
3
8
4
9
5
C
11
T
21
R
20
R
19
R1OUT
R
R1IN
4
11
6
10
7
10
8
RIGHT ANGLE MALE SUBD
FPS009-2405-0
C317
100NF
DATA FLASH
INTERFACE ONLY
PB25
DSR1
18
R2OUT
PB21
RXD1
17
R3OUT
PB24
CTS1
16
R4OUT
PB18
RI1
15
R5OUT
4K7
23
EN
R
R
R2IN
5
R3IN
6
R4IN
7
R5IN
8
SHDN
22
R
3V3
F2
0.20A
R287
R
5V
MAX3241ECW
R37
10K
B
C216
100NF
C214
10NF
R223
0R
F3
0.20A
PD4
USB HOST INTERFACE
R4
22K
C210
100NF
R222
47K
27R
R18
27R
R225
15K
A1
A2
A3
A4
R224
15K
C213
47pF
C212
47pF
B1
B2
B3
B4
A
B
1 2
USB_DP_PUP
3 4
DDP
C208
15PF
HDMB
HDPB
R19
R7
1K5
1%
CR6
BAT54-7
3
NRST
DDM
A
Q1
MMBT2222ALT1
J3
CCUSBA-32002-30X
C207
33PF
J4
2
R17
3V3
C211
10NF
PD5
HDMA
HDPA
R5
15K
USB_CNX
5V
C8
10 uF
10V
B
PD[0..27]
1
C7
10 uF
10V
R6
27R
2
1
R8
27R
3
4
C206
15PF
5
C209
100NF
6
A
27R
R16
USB DEVICE INTERFACE
27R
R206
15K
Monday, March 21, 2005
R205
15K
C201
47pF
C200
47pF
AT91RM9200-EK
SERIAL INTERFACES
A01 101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
JPG
JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
7
9
6
5
4
C245
100NF
3
C244
100NF
2
DNP
J11
C243
100NF
L205
1
2
AVDDV
742792093
R256
4K7
R270
4K7
L206
742792093
2
A[0..25]
A21
CLK
17
R253
10R
6K8
1%
2
L204
742792093
CLK/2
16
R254
10R
C238
10µF
10
C237 VDDA
100NF
11 VSSA
12
OSC
FUNC
15
LOCK/REF
14
I2CADR
13
3V3
R269
3V3
R255
10R
ICS1523
47K
R271
R272
R273
R274
R275
R283
R282
R281
138
139
140
141
142
2
3
4
Generic Little Indian
114
110
AVDD
AVDD
AVDD
116
118
111
133
5
76
AVSS
AVSS
BUSCLK
CLKI
CLKI2
CLKI3
TEST
60
66
64
62
CNF7
CNF6
CNF5
CNF4
CNF3
CNF2
CNF1
CNF0
131
130
129
128
127
126
125
124
VMP7
VMP6
VMP5
VMP4
VMP3
VMP2
VMP1
VMP0
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
134
135
136
137
57
61
63
65
67
68
69
70
71
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
RED
GREEN
BLUE
HRTC
VRTC
IREF
112
115
117
119
120
113
1
3
CW
SDA
RH/VH
13
TWCK
5
SCL
RW/VW
12
RL/VL
14
A0
A2
A3
NC
NC
NC
NC
NC
WP
9
VCC
16
VSS
D
3V3
C251
NOT INSTALLED
DNP
8
NOT INSTALLED
DNP
J9
DNP
J8
1
3
5
R1
7
R3
9
R5
11
G0
13
G2
15
G4
17
19
B1
21
B3
23
B5
25
DATAEN
27
29
31
NOT INSTALLED
C222
DNP
DOTCLK
VSYNC
R0
R2
R4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
HSYNC
FDAT18
FDAT20
FDAT22
VMP0
VMP2
VMP4
VMP6
GPIO12
GPIO10
GPIO8
GPIO6
GPIO4
GPIO2
GPIO0
G1
G3
G5
B0
B2
B4
C235
NOT INSTALLED
DNP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
FDAT19
FDAT21
FDAT23
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
VMP1
VMP3
VMP5
VMP7
GPIO11
GPIO9
GPIO7
GPIO5
GPIO3
GPIO1
C
3V3
CR200
BAV99-7
CR201
BAV99-7
AVDDV
2
2
3
1
CR202
BAV99-7
2
3
1
3
J6
CA-15DHDSR-F-11
1
L4
6
1
7
2
8
3
9
4
10
5
R
L5
G
L6
B
R246
150R
1%
4.6mA
R247
150R
1%
R252
150R
1%
11
B
12
13
14
15
16
VDDQ
18
8
C262 EXTFIL
150pF
9 XFILRET
15K
VMP7
VMP6
VMP5
VMP4
VMP3
VMP2
VMP1
VMP0
6
1
2
3
7
15
VSYNC
HSYNC
DATAEN
DOTCLK
74
75
77
78
TWD
10
4
11
DVDD
3.3NF
R266
3V3
0R
DVDD
19
C266
100NF
NRST
CFIOR_NBS1_NWR1
CFWE_NWE_NWR0
CFOE_NOE_NRD
SMCS_NCS3
R267
38
VSSQ
PDEN
EXTFB
HSYNC
C267
10µF
IOVDD
21
20
WAIT
RESET
RD/WR
WE1
WE0
RD
BS
M/R
CS
IOVDD
CLK+
CLK-
39
35
34
33
32
31
30
29
28
123
SDA
SCL
3V3
109
23
22
3
4
CLK/2+
CLK/2-
IOVDD
VSSD
IOVDD
2
R265
47K
92
24
73
IREF
IOVDD
B
1
VDDD
U5
IOVDD
R263
3V3
1
5
6
7
3V3
C264
C265
100NF
U7
3V3
R261 10K
R262 10K
R264 10K
R280
2K2
C261
100NF
R30
R29
R28
R27
R26
R25
R24
R23
C263
10 uF
10V
FPFRAME
FPLINE
DRDY
FPSHIFT
FDAT23
FDAT22
FDAT21
FDAT20
FDAT19
FDAT18
R0
B0
B1
B2
G0
G1
G2
R1
R2
B3
B4
B5
G3
G4
G5
R3
R4
R5
107
106
105
104
103
102
101
100
98
97
96
95
94
93
91
90
87
86
85
84
83
82
81
80
DNP
VR1
NOT INSTALLED
20%
DNP
U6
C250
10 uF
10V
FDAT23
FDAT22
FDAT21
FDAT20
FDAT19
FDAT18
FDAT17
FDAT16
FDAT15
FDAT14
FDAT13
FDAT12
FDAT11
FDAT10
FDAT9
FDAT8
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
S1D13806
DISPLAY CONTROLLER
37
PC6
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VDDCORE
3V3
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
1
C
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TWD
TWCK
VDDCORE
R268
4K7
R279
0R
122
PA25
VDDCORE
PA26
89
R277
0R
27
PA[0..31]
R276
2K7
36
59
72
79
88
99
108
121
144
58
143
R278
2K7
AB20
AB19
AB18
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
RESERVED
3V3
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DTESEN
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DVSS
DVSS
PC[0..15]
TESTEN
56
D[0..31]
3V3
20% ..100%
132
D
1
C246
10µF
1
DNP
DNP
C252 C253
LUMINANCE
NOT INSTALLED
NOT INSTALLED
1
2
3
4
5V
5
6
17
7
2
8
3V3
C240
10 uF
10V
(Default)
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
C272
100NF
C234
100NF
C241
100NF
C271
100NF
C268
100NF
C247
100NF
C270
100NF
C248
100NF
C242
100NF
C269
100NF
C249
100NF
3V3
A
3V3
R21
10K
Y2
1 OE
R251
1K5
1%
3V3
VDD 4
50 MHz
2 VSS
AVDDV
A
Q202
MMBT2222ALT1
Monday, March 21, 2005
C239
100NF
R249
75R
1%
OUT 3
SG-8002JC-50.0000M-PCB
R250
1K
1%
C236
100NF
AT91RM9200-EK
R22
0R
VGA TFT/CRT DISPLAY
A01 101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
JPG
JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
8
9
8
7
PD[0..27]
PC[0..15]
PB[0..29]
6
5
4
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD6
PD5
PD4
PD3
PD2
PD1
PD0
C
D[0..31]
2
1
PA[0..31]
C324
100NF
D
3
PB29
PB28
PB27
PB26
PB25
PB24
PB23
PB22
PB21
PB20
PB19
PB18
PB17
PB16
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA31
PA30
PA29
PA28
PA27
PA26
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
3V3
P1C
P15
P1A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
TP16
A[0..25]
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
3V3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
A0
A1 NWR2
A2
A3
A4
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
1
P39
P2
P27
1
1
P40
P28
1
P41
P29
1
1
P42
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BFCS_NCS0
NCS2
SMCS_NCS3
NRST
CFOE_NOE_NRD
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
A
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
A5
A6
A7
A8
A9
A10
A11
A12
P30
P24
1
P43
P31
1
A13
A14
A15
A16
A17
A18
A19
A20
1
P32
A21
A22
A23
A24
A25
BFCS_NCS0
NCS2
SMCS_NCS3
NRST
CFOE_NOE_NRD
CFWE_NWE_NWR0
CFIOR_NBS1_NWR1
CFIOW_NBS3_NWR3
1
P45
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PC9
5V
P10
P33
1
C
1
1
P14
PC7
PC8
1
1
P26
1
P46
5V
P11
P34
1
1
1
P18
1
P47
5V
P12
P35
1
1
1
5V
P13
P36
1
1
1
P20
1
P49
5V
P8
P37
1
1
1
P21
1
P50
3V3
3V3
P7
1
PB24
PB25
PB26
PB27
PB28
PB29
1
1
P44
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
3V3
P6
P25
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
1
1
P48
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
3V3
P4
1
P1D
1
1
P23
1
P1B
3V3
P5
P19
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
P17
PB9
PB10
PB11
PB12
PB13
PB14
PB15
3V3
P3
1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
D
1
P16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
1
5V
P9
P38
1
1
1
P22
1
R301
1K
1%
WAIT
PC0
PC1
PC2
PC3
PC4
PC5
PC6_R
A23
A24
B
1
P51
PC6
R296
0R
A25
PC10
PC11
PC12
PC13
PC14
PC15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
5V
A
C322
100NF
Monday, March 21, 2005
AT91RM9200-EK
EXPANSION CONNECTORS
A01 101-3-05-106
A INIT EDIT
ELX
MDZ
23/02/05
04/01/05
JPG
JPG
REV MODIF.
DES.
DATE
VER.
DATE
REV.
SHEET
SCALE
1/1
63SC042261A01
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
1
23/02/05
06/01/05
9
9
Schematics
5-4
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Errata
Section 6
Errata
6.1
Errata
6.1.1
SD/MMC Card Slot
Communication
Problem
On the AT91RM9200-EK Board, revision 700-20226 REV X5, a communication problem
may occur on the SD/MMC interface.
This issue has been corrected on all boards of revision 63PC042262A by adding a 10
kOhm pull-up resistor between the pin connectors J17-2 and J17-4.
AT91RM9200-EK Evaluation Board User Guide
6-1
6103C–ATARM–05-Jan-06
Errata
6-2
6103C–ATARM–05-Jan-06
AT91RM9200-EK Evaluation Board User Guide
Revision History
Doc. Rev.
Date
Comments
6103A
24-Sep-04
First issue.
6103B
02-Mar-05
CSR 04-361,
CSR 05-028, CSR 05-246
19-Jul-05
Section 1.2, “Deliverables” on page 2; List simplified
Table 4-1, Boot information modified
New schematics added in Section 5.
07-Nov-05
Added Section 6, Errata.
CSR 05-478
6103C
Change Request Ref.
1
6103C–ATARM–05-Jan-06
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