AT91SAM ARM-based Embedded MPU
SAM9260
Features
• 180 MHz ARM926EJ-S™ ARM® Thumb® Processor
– 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU
• Memories
•
•
•
•
– 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories,
CompactFlash, SLC NAND Flash with ECC
– Two 4-kbyte internal SRAM, single-cycle access at system speed
– One 32-kbyte internal ROM, embedding bootstrap routine
Peripherals
– ITU-R BT. 601/656 Image Sensor Interface
– USB Device and USB Host with dedicated On-Chip Transceiver
– 10/100 Mbps Ethernet MAC Controller
– One High Speed Memory Card Host
– Two Master/Slave Serial Peripheral Interfaces
– Two Three-channel 32-bit Timer/Counters
– One Synchronous Serial Controller
– One Two-wire Interface
– Four USARTs
– Two UARTs
– 4-channel 10-bit ADC
System
– 90 MHz six 32-bit layer AHB Bus Matrix
– 22 Peripheral DMA Channels
– Boot from NAND Flash, DataFlash® or serial DataFlash
– Reset Controller with On-Chip Power-on Reset
– Selectable 32,768 Hz Low-Power and 3-20 MHz Main Oscillator
– Internal Low-Power 32 kHz RC Oscillator
– One PLL for the system and one PLL optimized for USB
– Two Programmable External Clock Signals
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real Time Timer
I/O
– Three 32-bit Parallel Input/Output Controllers
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
Package
– 217-ball BGA, 0.8 mm pitch
– 208-pin QFP, 0.5 mm pitch
This is a summary document.
The complete document is
available on the Atmel website
at www.atmel.com.
6221LS–ATARM–15-Oct-12
1.
Description
The SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide
range of peripherals.
The SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several
standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and
MultiMedia Card Interface.
The SAM9260 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also
features an External Bus Interface capable of interfacing with a wide range of memory devices.
2.
SAM9260 Block Diagram
The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-pin
PQFP package and the unavailable pins are highlighted in “Multiplexing on PIO Controller A” on page 31, “Multiplexing
on PIO Controller B” on page 32, “Multiplexing on PIO Controller C” on page 33. The USB Host Port B is not available in
the 208-pin package. Table 2-1 on page 2 defines all the multiplexed and not multiplexed pins not available in the 208PQFP package.
Table 2-1.
Unavailable Signals in 208-lead PQFP Package
PIO
Peripheral A
Peripheral B
-
HDPB
-
-
HDMB
-
PA30
SCK2
RXD4
PA31
SCK0
TXD4
PB12
TXD5
ISI_D10
PB13
RXD5
ISI_D11
PC2
AD2
PCK1
PC3
AD3
SPI1_NPCS3
PC12
IRQ0
NCS7
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
2
PIT
MCI
RSTC
SHDWC
RTT
4GPREG
PDC
POR
VDDCORE
NRST
POR
OSC
RC
WDT
OSC
PLLB
PLLA
PMC
PDC
DBGU
AIC
System
Controller
SHDN
WKUP
VDDBU
OSCSEL
XIN32
XOUT32
XIN
XOUT
PLLRCA
DRXD
DTXD
PCK0-PCK1
FIQ
IRQ0-IRQ2
TST
SLAVE
TWI
PIOC
PIOB
PIOA
PDC
USART0
USART1
USART2
USART3
USART4
USART5
APB
JT
AG
SE
L
NT
R
TD ST
TDI
TMO
TC S
RTK
CK
SPI0_, SPI1_
MMU
TC0
TC1
TC2
Fast SRAM
4 Kbytes
Bus Interface
PDC
SPI0
SPI1
ROM
32 Kbytes
I
ICache
8 Kbytes
D
TC3
TC4
TC5
Fast SRAM
4 Kbytes
DCache
8 Kbytes
ARM926EJ-S Processor
In-Circuit Emulator
JTAG Selection and Boundary Scan
S
PDC
BM
SSC
DMA
4-channel
10-bit ADC
PDC
Peripheral
Bridge
6-layer Matrix
FIFO
USB
Device
DPRAM
DMA
Image
Sensor
Interface
Transceiver
22-channel
Peripheral
DMA
FIFO
10/100 Ethernet
MAC
ET
ETXC
K
ECXE -E
N R
ERRS -E XC
T
ERXE -EC XE K
R O
ET X0 -E L R
- R
M X0 ER XD
D - X
M C ETX 3 V
D
3
F1 IO
00
G
NP
NPCS
NPCS3
NPCS2
C 1
SP S0
M CK
O
T
M SI
C
IS
L
O
TI K0
O -T
TI A0- CL
O T K
TC B0 IOA2
L -T 2
TI K3 IOB
O TI A3 TC 2
L
O
B3-TIOK5
-T A
IO 5
B5
TK
TF
TD
RD
RF
RK
AD
0A
A D3
D
TR
IG
A
D
VR
EF
VD
DA
NA
ND
AN
A
Filter
M
CD
B
0
-M
CD
M
M B3
C
C
D
A0 CD
M B
C
M DA
CC 3
D
M A
CC
K
T
CT TWWD
RTS0- CK
C
SC S0- TS
R 3
RX K0- TS
S 3
TXD0- CK
D0 RX 3
-T D5
X
DSD5
DCR0
D
R0
DT I0
R0
Transc.
ECC
Controller
Static
Memory
Controller
SDRAM
Controller
CompactFlash
NAND Flash
EBI
DMA
USB
OHCI
Transc.
I
S
I_
M
IS CK
I_
I PC
S
I_ K
IS DO
I_ -I
V
IS SY SI_
I_ N D7
H
SY C
NC
H
D
HD PA
M
A
HD
P
HD B
M
B
DD
DDM
P
MASTER
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15, A18-A20
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
A21/NANDALE
A22/NANDCLE
D16-D31
NWAIT
A23-A24
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
CFCE1-CFCE2
NCS2, NCS6, NCS7
NCS3/NANDCS
Figure 2-1. SAM9260 Block Diagram
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
3
3.
Signal Description
Table 3-1.
Signal Description List
Signal Name
Function
Type
Active
Level
Comments
Power Supplies
VDDIOM
EBI I/O Lines Power Supply
Power
1.65V to 1.95V or 3.0V to3.6V
VDDIOP0
Peripherals I/O Lines Power Supply
Power
3.0V to 3.6V
VDDIOP1
Peripherals I/O Lines Power Supply
Power
1.65V to 3.6V
VDDBU
Backup I/O Lines Power Supply
Power
1.65V to 1.95V
VDDANA
Analog Power Supply
Power
3.0V to 3.6V
VDDPLL
PLL Power Supply
Power
1.65V to 1.95V
VDDCORE
Core Chip Power Supply
Power
1.65V to 1.95V
GND
Ground
Ground
GNDPLL
PLL and Oscillator Ground
Ground
GNDANA
Analog Ground
Ground
GNDBU
Backup Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
OSCSEL
Slow Clock Oscillator Selection
Input
PLLRCA
PLL A Filter
Input
PCK0 - PCK1
Programmable Clock Output
Output
Input
Output
Accepts between 0V and
VDDBU.
Output
Shutdown, Wakeup Logic
SHDN
Shutdown Control
WKUP
Wake-up Input
Driven at 0V only. Do not tie over
VDDBU.
Output
Accepts between 0V and
VDDBU.
Input
ICE and JTAG
NTRST
Test Reset Signal
Input
Low
Pull-up resistor
TCK
Test Clock
Input
No pull-up resistor
TDI
Test Data In
Input
No pull-up resistor
TDO
Test Data Out
TMS
Test Mode Select
Input
No pull-up resistor
JTAGSEL
JTAG Selection
Input
Pull-down resistor. Accepts
between 0V and VDDBU.
RTCK
Return Test Clock
Output
Output
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
4
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
I/O
Low
Comments
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
Input
BMS
Boot Mode Select
Input
Pull-up resistor
Pull-down resistor. Accepts
between 0V and VDDBU.
No pull-up resistor
BMS = 0 when tied to GND
BMS = 1 when tied to VDDIOP0.
Debug Unit - DBGU
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
Advanced Interrupt Controller - AIC
IRQ0 - IRQ2
External Interrupt Inputs
Input
FIQ
Fast Interrupt Input
Input
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
Parallel IO Controller A
I/O
Pulled-up input at reset
PB0 - PB31
Parallel IO Controller B
I/O
Pulled-up input at reset
PC0 - PC31
Parallel IO Controller C
I/O
Pulled-up input at reset
External Bus Interface - EBI
D0 - D31
Data Bus
I/O
A0 - A25
Address Bus
NWAIT
External Wait Signal
Pulled-up input at reset
Output
Input
0 at reset
Low
Static Memory Controller - SMC
NCS0 - NCS7
Chip Select Lines
Output
Low
NWR0 - NWR3
Write Signal
Output
Low
NRD
Read Signal
Output
Low
NWE
Write Enable
Output
Low
NBS0 - NBS3
Byte Mask Signal
Output
Low
CompactFlash Support
CFCE1 - CFCE2
CompactFlash Chip Enable
Output
Low
CFOE
CompactFlash Output Enable
Output
Low
CFWE
CompactFlash Write Enable
Output
Low
CFIOR
CompactFlash IO Read
Output
Low
CFIOW
CompactFlash IO Write
Output
Low
CFRNW
CompactFlash Read Not Write
Output
CFCS0 - CFCS1
CompactFlash Chip Select Lines
Output
Low
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
5
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
NAND Flash Support
NANDCS
NAND Flash Chip Select
Output
Low
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
NANDALE
NAND Flash Address Latch Enable
Output
Low
NANDCLE
NAND Flash Command Latch Enable
Output
Low
SDRAM Controller
SDCK
SDRAM Clock
Output
SDCKE
SDRAM Clock Enable
Output
High
SDCS
SDRAM Controller Chip Select
Output
Low
BA0 - BA1
Bank Select
Output
SDWE
SDRAM Write Enable
Output
Low
RAS - CAS
Row and Column Signal
Output
Low
SDA10
SDRAM Address 10 Line
Output
Multimedia Card Interface MCI
MCCK
Multimedia Card Clock
Output
MCCDA
Multimedia Card Slot A Command
I/O
MCDA0 - MCDA3
Multimedia Card Slot A Data
I/O
MCCDB
Multimedia Card Slot B Command
I/O
MCDB0 - MCDB3
Multimedia Card Slot B Data
I/O
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
DTR0
USART0 Data Terminal Ready
DSR0
USART0 Data Set Ready
Input
DCD0
USART0 Data Carrier Detect
Input
RI0
USART0 Ring Indicator
Input
Output
Input
Output
Synchronous Serial Controller - SSC
TD
SSC Transmit Data
Output
RD
SSC Receive Data
Input
TK
SSC Transmit Clock
I/O
RK
SSC Receive Clock
I/O
TF
SSC Transmit Frame Sync
I/O
RF
SSC Receive Frame Sync
I/O
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
6
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
Timer/Counter - TCx
TCLKx
TC Channel x External Clock Input
Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Serial Peripheral Interface - SPIx_
SPIx_MISO
Master In Slave Out
I/O
SPIx_MOSI
Master Out Slave In
I/O
SPIx_SPCK
SPI Serial Clock
I/O
SPIx_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
SPIx_NPCS1-SPIx_NPCS3
SPI Peripheral Chip Select
Output
Low
Two-Wire Interface
TWD
Two-wire Serial Data
I/O
TWCK
Two-wire Serial Clock
I/O
USB Host Port
HDPA
USB Host Port A Data +
Analog
HDMA
USB Host Port A Data -
Analog
HDPB
USB Host Port B Data +
Analog
HDMB
USB Host Port B Data +
Analog
USB Device Port
DDM
USB Device Port Data -
Analog
DDP
USB Device Port Data +
Analog
Ethernet 10/100
ETXCK
Transmit Clock or Reference Clock
Input
MII only, REFCK in RMII
ERXCK
Receive Clock
Input
MII only
ETXEN
Transmit Enable
Output
ETX0-ETX3
Transmit Data
Output
ETX0-ETX1 only in RMII
ETXER
Transmit Coding Error
Output
MII only
ERXDV
Receive Data Valid
Input
RXDV in MII, CRSDV in RMII
ERX0-ERX3
Receive Data
Input
ERX0-ERX1 only in RMII
ERXER
Receive Error
Input
ECRS
Carrier Sense and Data Valid
Input
MII only
ECOL
Collision Detect
Input
MII only
EMDC
Management Data Clock
EMDIO
Management Data Input/Output
EF100
Force 100Mbit/sec.
Output
I/O
Output
High
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
7
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
Image Sensor Interface
ISI_D0-ISI_D11
Image Sensor Data
Input
ISI_MCK
Image Sensor Reference Clock
ISI_HSYNC
Image Sensor Horizontal Synchro
Input
ISI_VSYNC
Image Sensor Vertical Synchro
Input
ISI_PCK
Image Sensor Data clock
Input
Output
Provided by PCK1.
Analog to Digital Converter
AD0-AD3
Analog Inputs
Analog
ADVREF
Analog Positive Reference
Analog
ADTRG
ADC Trigger
Digital pulled-up inputs at reset
Input
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
8
4.
Package and Pinout
The SAM9260 is available in two packages:
z
208-pin PQFP Green package (0.5mm pitch).
z
217-ball LFBGA Green package (0.8 mm ball pitch).
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
9
4.1
208-pin PQFP Package
Figure 11-3 shows the orientation of the 208-pin PQFP package. A detailed mechanical description is given in the section
“SAM9260 Mechanical Characteristics” of the datasheet.
4.2
208-pin PQFP Pinout
Table 4-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Pinout for 208-pin PQFP Package
Signal Name
PA24
PA25
PA26
PA27
VDDIOP0
GND
PA28
PA29
PB0
PB1
PB2
PB3
VDDIOP0
GND
PB4
PB5
PB6
PB7
PB8
PB9
PB14
PB15
PB16
VDDIOP0
GND
PB17
PB18
PB19
TDO
TDI
TMS
VDDIOP0
GND
TCK
NTRST
NRST
RTCK
VDDCORE
GND
BMS
OSCSEL
TST
JTAGSEL
GNDBU
XOUT32
XIN32
VDDBU
WKUP
SHDN
HDMA
HDPA
VDDIOP0
Pin
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Signal Name
GND
DDM
DDP
PC13
PC11
PC10
PC14
PC9
PC8
PC4
PC6
PC7
VDDIOM
GND
PC5
NCS0
CFOE/NRD
CFWE/NWE/NWR0
NANDOE
NANDWE
A22
A21
A20
A19
VDDCORE
GND
A18
BA1/A17
BA0/A16
A15
A14
A13
A12
A11
A10
A9
A8
VDDIOM
GND
A7
A6
A5
A4
A3
A2
NWR2/NBS2/A1
NBS0/A0
SDA10
CFIOW/NBS3/NWR3
CFIOR/NBS1/NWR1
SDCS/NCS1
CAS
Pin
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Signal Name
RAS
D0
D1
D2
D3
D4
D5
D6
GND
VDDIOM
SDCK
SDWE
SDCKE
D7
D8
D9
D10
D11
D12
D13
D14
D15
PC15
PC16
PC17
PC18
PC19
VDDIOM
GND
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
GND
VDDCORE
VDDPLL
XIN
XOUT
GNDPLL
NC
GNDPLL
PLLRCA
VDDPLL
GNDANA
Pin
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal Name
ADVREF
PC0
PC1
VDDANA
PB10
PB11
PB20
PB21
PB22
PB23
PB24
PB25
VDDIOP1
GND
PB26
PB27
GND
VDDCORE
PB28
PB29
PB30
PB31
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
VDDIOP0
GND
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
VDDIOP0
GND
PA18
PA19
VDDCORE
GND
PA20
PA21
PA22
PA23
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
10
4.3
217-ball LFBGA Package
Figure 11-1 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in the
section “SAM9260 Mechanical Characteristics” of the datasheet.
4.4
217-ball LFBGA Pinout
Table 4-2.
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
D1
D2
D3
D4
Pinout for 217-ball LFBGA Package
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
CFIOW/NBS3/NWR3
NBS0/A0
NWR2/NBS2/A1
A6
A8
A11
A13
BA0/A16
A18
A21
A22
CFWE/NWE/NWR0
CFOE/NRD
NCS0
PC5
PC6
PC4
SDCK
CFIOR/NBS1/NWR1
SDCS/NCS1
SDA10
A3
A7
A12
A15
A20
NANDWE
PC7
PC10
PC13
PC11
PC14
PC8
WKUP
D8
D1
CAS
A2
A4
A9
A14
BA1/A17
A19
NANDOE
PC9
PC12
DDP
HDMB
NC
VDDIOP0
SHDN
D9
D2
RAS
D0
J14
J15
J16
J17
K1
K2
K3
K4
K8
K9
K10
K14
K15
K16
K17
L1
L2
L3
L4
L14
L15
L16
L17
M1
M2
M3
M4
M14
M15
M16
M17
N1
N2
N3
N4
N14
N15
N16
N17
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
TDO
PB19
TDI
PB16
PC24
PC20
D15
PC21
GND
GND
GND
PB4
PB17
GND
PB15
GND
PC26
PC25
VDDIOP0
PA28
PB9
PB8
PB14
VDDCORE
PC31
GND
PC22
PB1
PB2
PB3
PB7
XIN
VDDPLL
PC23
PC27
PA31
PA30
PB0
PB6
XOUT
VDDPLL
PC30
PC28
PB11
PB13
PB24
VDDIOP1
PB30
PB31
PA1
PA3
PA7
PA9
PA26
PA25
P17
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
PB5
NC
GNDANA
PC29
VDDANA
PB12
PB23
GND
PB26
PB28
PA0
PA4
PA5
PA10
PA21
PA23
PA24
PA29
PLLRCA
GNDPLL
PC0
PC1
PB10
PB22
GND
PB29
PA2
PA6
PA8
PA11
VDDCORE
PA20
GND
PA22
PA27
GNDPLL
ADVREF
PC2
PC3
PB20
PB21
PB25
PB27
PA12
PA13
PA14
PA15
PA19
PA17
PA16
PA18
VDDIOP0
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
E1
E2
E3
E4
E14
E15
E16
E17
F1
F2
F3
F4
F14
F15
F16
F17
G1
G2
G3
G4
G14
G15
G16
G17
H1
H2
H3
H4
H8
H9
H10
H14
H15
H16
H17
J1
J2
J3
J4
J8
J9
J10
A5
GND
A10
GND
VDDCORE
GND
VDDIOM
GND
DDM
HDPB
NC
VDDBU
XIN32
D10
D5
D3
D4
HDPA
HDMA
GNDBU
XOUT32
D13
SDWE
D6
GND
OSCSEL
BMS
JTAGSEL
TST
PC15
D7
SDCKE
VDDIOM
GND
NRST
RTCK
TMS
PC18
D14
D12
D11
GND
GND
GND
VDDCORE
TCK
NTRST
PB18
PC19
PC17
VDDIOM
PC16
GND
GND
GND
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
11
5.
Power Considerations
5.1
Power Supplies
The SAM9260 has several types of power supply pins:
z
VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage
ranges from 1.65V and 1.95V, 1.8V nominal.
z
VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical)
or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is selectable by software.
z
VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 3.0V and 3.6V, 3V
or 3.3V nominal.
z
VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V
and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
z
VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.65V to
1.95V, 1.8V nominal.
z
VDDPLL pin: Powers the Main Oscillator and PLL cells; voltage ranges from 1.65V and 1.95V, 1.8V nominal.
z
VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the multiplexing tables.
These supplies enable the user to power the device differently for interfacing with memories and for interfacing with
peripherals.
Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power supplies. Separated
ground pins are provided for VDDBU, VDDPLL and VDDANA. These ground pins are respectively GNDBU, GNDPLL
and GNDANA.
5.2
Power Consumption
The SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static current rises up to 5 mA if the
temperature increases to 85°C.
On VDDBU, the current does not exceed 10 µA in worst case conditions.
For dynamic power consumption, the SAM9260 consumes a maximum of 100 mA on VDDCORE at maximum conditions
(1.8V, 25°C, processor running full-performance algorithm out of high speed memories).
5.3
Programmable I/O Lines Power Supplies
The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either
out of 1.8V or 3.3V external memories.
The target maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power supply at 1.8V and
50 pF for power supply at 3.3V. The other signals (control, address and data signals) do not exceed 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix
User Interface.
At reset, the selected voltage defaults to 3.3V nominal, and power supply pins can accept either 1.8V or 3.3V. Obviously,
the device cannot reach its maximum speed if the voltage supplied to the pins is 1.8V only. The user must program the
EBI voltage range before getting the device out of its Slow Clock Mode.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
12
6.
I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates
a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.
The NTRST signal is described in Section 6.3.
All the JTAG signals are supplied with VDDIOP0.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of
about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to
unpredictable results.
This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is a bidirectional with an open-drain output integrating a non-programmable pull-up resistor. It can be driven with
voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and
NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table
“DC Characteristics” in the section “SAM9260 Electrical Characteristics” in the product datasheet.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section on DC
Characteristics in “SAM9260 Electrical Characteristics” for more information. Programming of this pull-up resistor is
performed independently for each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the
External Bus Interface signals and that must be enabled as Peripheral at reset. This is explicitly indicated in the column
“Reset State” of the PIO Controller multiplexing tables.
6.5
I/O Line Drive Levels
The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently except PC4 to
PC31 that are VDDIOM powered.
6.6
Shutdown Logic Pins
The SHDN pin is a tri-state output pin, which is driven by the Shutdown Controller. There is no internal pull-up. An
external pull-up tied to VDDBU is needed and its value must be higher than 1 MΩ. The resistor value is calculated
according to the regulator enable implementation and the SHDN level.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
13
6.7
Slow Clock Selection
The SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator.
Table 6-1 defines the states for OSCSEL signal.
Table 6-1.
Slow Clock Selection
OSCSEL
Slow Clock
Startup Time
0
Internal RC
240 µs
1
External 32768 Hz
1200 ms
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The 32,768 Hz startup delay is
1200 ms whereas it is 240 µs for the internal RC oscillator (refer to Table 6-1). The pin OSCSEL must be tied either to
GND or VDDBU for correct operation of the device.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
14
7.
Processor and Architecture
7.1
ARM926EJ-S Processor
z
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
z
Two Instruction Sets
ARM High-performance 32-bit Instruction Set
z
Thumb High Code Density 16-bit Instruction Set
z
DSP Instruction Extensions
z
5-Stage Pipeline Architecture:
z
z
z
z
7.2
z
z
Instruction Fetch (F)
z
Instruction Decode (D)
z
Execute (E)
z
Data Memory (M)
z
Register Write (W)
8-Kbyte Data Cache, 8-Kbyte Instruction Cache
z
Virtually-addressed 4-way Associative Cache
z
Eight words per line
z
Write-through and Write-back Operation
z
Pseudo-random or Round-robin Replacement
Write Buffer
z
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
z
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
z
Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
z
Access Permission for Sections
z
Access Permission for large pages and small pages can be specified separately for each quarter of the
page
z
16 embedded domains
Bus Interface Unit (BIU)
z
Arbitrates and Schedules AHB Requests
z
Separate Masters for both instruction and data access providing complete Matrix system flexibility
z
Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
z
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
Bus Matrix
z
6-layer Matrix, handling requests from 6 masters
z
Programmable Arbitration strategy
z
z
z
Fixed-priority Arbitration
z
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
Burst Management
z
Breaking with Slot Cycle Limit Support
z
Undefined Burst Length Support
One Address Decoder provided per Master
z
Three different slaves may be assigned to each decoded memory area: one for internal boot, one for
external boot, one after remap
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
15
z
z
7.2.1
Boot Mode Select
z
Non-volatile Boot Memory can be internal or external
z
Selection is made by BMS pin sampled at reset
Remap Command
z
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
z
Allows Handling of Dynamic Exception Vectors
Matrix Masters
The Bus Matrix of the SAM9260 manages six Masters, which means that each master can perform an access
concurrently with others, according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all
the masters have the same decodings.
Table 7-1.
7.2.2
List of Bus Matrix Masters
Master 0
ARM926™ Instruction
Master 1
ARM926 Data
Master 2
PDC
Master 3
USB Host DMA
Master 4
ISI Controller
Master 5
Ethernet MAC
Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.
List of Bus Matrix Slaves
Slave 0
Internal SRAM0 4 KBytes
Slave 1
Internal SRAM1 4 KBytes
Internal ROM
Slave 2
7.2.3
USB Host User Interface
Slave 3
External Bus Interface
Slave 4
Internal Peripherals
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access
from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown “-” in
the following table.
Table 7-3.
SAM9260 Masters to Slaves Access
Master
0&1
2
3
4
5
Slave
ARM926
Instruction &
Data
Peripheral
DMA
Controller
USB Host
Controller
ISI
Controller
Ethernet
MAC
0
Internal SRAM
4 KBytes
X
X
X
X
X
1
Internal SRAM
4 KBytes
X
X
X
X
X
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
16
Table 7-3.
Internal ROM
X
X
X
-
-
UHP User Interface
X
-
-
-
-
3
External Bus Interface
X
X
X
X
X
4
Internal Peripherals
X
X
X
-
-
2
7.3
SAM9260 Masters to Slaves Access (Continued)
Peripheral DMA Controller
z
Acting as one Matrix Master
z
Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.
z
Next Pointer Support, forbids strong real-time constraints on buffer management.
z
Twenty-two channels
z
Two for each USART
z
Two for the Debug Unit
z
Two for each Serial Synchronous Controller
z
Two for each Serial Peripheral Interface
z
One for Multimedia Card Interface
z
One for Analog-to-Digital Converter
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to
High priorities):
z
DBGU Transmit Channel
z
USART5 Transmit Channel
z
USART4 Transmit Channel
z
USART3 Transmit Channel
z
USART2 Transmit Channel
z
USART1 Transmit Channel
z
USART0 Transmit Channel
z
SPI1 Transmit Channel
z
SPI0 Transmit Channel
z
SSC Transmit Channel
z
DBGU Receive Channel
z
USART5 Receive Channel
z
USART4 Receive Channel
z
USART3 Receive Channel
z
USART2 Receive Channel
z
USART1 Receive Channel
z
USART0 Receive Channel
z
ADC Receive Channel
z
SPI1 Receive Channel
z
SPI0 Receive Channel
z
SSC Receive Channel
z
MCI Transmit/Receive Channel
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
17
7.4
Debug and Test Features
z
z
z
ARM926 Real-time In-circuit Emulator
z
Two real-time Watchpoint Units
z
Two Independent Registers: Debug Control Register and Debug Status Register
z
Test Access Port Accessible through JTAG Protocol
z
Debug Communications Channel
Debug Unit
z
Two-pin UART
z
Debug Communication Channel Interrupt Handling
z
Chip ID Register
IEEE1149.1 JTAG Boundary-scan on All Digital Pins
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
18
8.
Memories
Figure 8-1. SAM9260 Memory Mapping
Address Memory Space
Internal Memory Mapping
0x0000 0000
Notes :
(1) Can be ROM, EBI_NCS0 or SRAM
depending on BMS and REMAP
0x0000 0000
Boot Memory (1)
Internal Memories
256M Bytes
0x10 0000
ROM
0x0FFF FFFF
EBI
Chip Select 0
Reserved
256M Bytes
0x20 0000
SRAM0
4K Bytes
0x20 1000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
32K Bytes
0x10 8000
0x1000 0000
Reserved
EBI
Chip Select 1/
SDRAMC
256M Bytes
0x30 0000
SRAM1
4K Bytes
0x30 1000
Reserved
0x3000 0000
0x50 0000
EBI
Chip Select 2
UHP
256M Bytes
0x50 4000
EBI
Chip Select 3/
NANDFlash
256M Bytes
0x0FFF FFFF
EBI
Chip Select 4/
Compact Flash
Slot 0
256M Bytes
EBI
Chip Select 5/
Compact Flash
Slot 1
256M Bytes
16K Bytes
0x3FFF FFFF
0x4000 0000
Reserved
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
Peripheral Mapping
0xF000 0000
System Controller Mapping
Reserved
0x7000 0000
0xFFFA 0000
EBI
Chip Select 6
256M Bytes
0x7FFF FFFF
0x8000 0000
TCO, TC1, TC2
16K Bytes
0xFFFF C000
UDP
16K Bytes
0xFFFF E800
MCI
16K Bytes
0xFFFF EA00
TWI
16K Bytes
Reserved
0xFFFA 4000
0xFFFA 8000
EBI
Chip Select 7
256M Bytes
0xFFFA C000
0x8FFF FFFF
0x9000 0000
ECC
512 Bytes
SDRAMC
512 Bytes
SMC
512 Bytes
0xFFFF EC00
0xFFFB 0000
USART0
16K Bytes
0xFFFB 4000
0xFFFF EE00
USART1
16K Bytes
0xFFFB 8000
USART2
16K Bytes
SSC
16K Bytes
ISI
16K Bytes
EMAC
16K Bytes
MATRIX
0xFFFF EF10
0xFFFF F000
0xFFFB C000
512 Bytes
CCFG
AIC
512 Bytes
0xFFFF F200
0xFFFC 0000
0xFFFC 4000
1,518M Bytes
SPI0
16K Bytes
0xFFFC C000
SPI1
16K Bytes
USART3
PIOB
16K Bytes
0xFFFD 8000
USART5
0xFFFF FC00
16K Bytes
0xFFFF FD00
TC3, TC4, TC5
16K Bytes
ADC
16K Bytes
256 Bytes
16 Bytes
SHDWC
0xFFFF FD20
16 Bytes
0xFFFF FD30
RTTC
16 Bytes
PITC
16 Bytes
WDTC
16 Bytes
GPBR
16 Bytes
0xFFFF FD40
0xFFFE 4000
0xFFFF FD50
0xFFFF FD60
Reserved
0xFFFF C000
SYSC
0xFFFF FFFF
PMC
RSTC
0xFFFF FD10
0xFFFE 0000
0xFFFF FFFF
512 bytes
0xFFFF FA00
16K Bytes
0xFFFD C000
256M Bytes
512 bytes
Reserved
USART4
Internal Peripherals
512 Bytes
0xFFFF F800
0xFFFD 4000
0xEFFF FFFF
PIOA
PIOC
0xFFFD 0000
0xF000 0000
512 Bytes
0xFFFF F600
0xFFFC 8000
Undefined
(Abort)
DBGU
0xFFFF F400
16K Bytes
Reserved
0xFFFF FFFF
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
19
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High
Performance Bus (AHB) for its Master and Slave interfaces with additional features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI
that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing
of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved
for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master requesting such an
access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in
order to simplify the mappings, all the masters have a similar address decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory
space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-1, “Internal
Memory Mapping,” on page 20 for details.
A complete memory map is presented in Figure 8-1 on page 19.
8.1
Embedded Memories
z
32 KB ROM
z
z
Two 4 KB Fast SRAM
z
8.1.1
Single Cycle Access at full matrix speed
Single Cycle Access at full matrix speed
Boot Strategies
Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS
state at reset.
Table 8-1.
Internal Memory Mapping
Address
0x0000 0000
REMAP = 0
REMAP = 1
BMS = 1
BMS = 0
ROM
EBI_NCS0
SRAM0 4K
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can
be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software
once the system has booted. Refer to the Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is
done via hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in Figure 8-1 on page 19.
The SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory
area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.
8.1.1.1 BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
z
Boot on slow clock (On-chip RC or 32,768 Hz)
z
Auto baudrate detection
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
20
z
Downloads and runs an application from external storage media into internal SRAM
z
Downloaded code size depends on embedded SRAM size
z
Automatic detection of valid application
z
Bootloader on a non-volatile memory
z
z
SPI DataFlash® connected on NPCS0 and NPCS1 of the SPI0
z
8-bit and/or 16-bit NAND Flash
SAM-BA® Monitor in case no valid program is detected in external NVM, supporting
z
Serial communication on a DBGU
z
USB Device Port
8.1.1.2 BMS = 0, Boot on External Memory
z
Boot on slow clock (On-chip RC or 32,768 Hz)
z
Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write
controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps:
8.2
1.
Program the PMC (main oscillator enable or bypass mode).
2.
Program and start the PLL.
3.
Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock.
4.
Switch the main clock to the new value.
External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256-Mbyte
memory area assigned.
Refer to the memory map in Figure 8-1 on page 19.
8.2.1
External Bus Interface
z
8.2.2
Integrates three External Memory Controllers
z
Static Memory Controller
z
SDRAM Controller
z
ECC Controller
z
Additional logic for NAND Flash
z
Full 32-bit External Data Bus
z
Up to 26-bit Address Bus (up to 64MBytes linear)
z
Up to 8 chip selects, Configurable Assignment:
z
Static Memory Controller on NCS0
z
SDRAM Controller or Static Memory Controller on NCS1
z
Static Memory Controller on NCS2
z
Static Memory Controller on NCS3, Optional NAND Flash support
z
Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
z
Static Memory Controller on NCS6-NCS7
Static Memory Controller
z
8-, 16- or 32-bit Data Bus
z
Multiple Access Modes supported
z
Byte Write or Byte Select Lines
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
21
z
z
z
z
8.2.3
Multiple device adaptability
z
Compliant with LCD Module
z
Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
z
Programmable Wait State Generation
z
External Wait Request
z
Programmable Data Float Time
Slow Clock mode supported
SDRAM Controller
z
Supported devices
z
Numerous configurations supported
z
z
z
Standard and Low-power SDRAM (Mobile SDRAM)
z
2K, 4K, 8K Row Address Memory Parts
z
SDRAM with two or four Internal Banks
z
SDRAM with 16- or 32-bit Datapath
Programming facilities
z
Word, half-word, byte access
z
Automatic page break when Memory Boundary has been reached
z
Multibank Ping-pong Access
z
Timing parameters specified by software
z
Automatic refresh operation, refresh rate is programmable
Energy-saving capabilities
z
Self-refresh, power down and deep power down modes supported
z
Error detection
z
SDRAM Power-up Initialization by software
z
CAS Latency of 1, 2 and 3 supported
z
Auto Precharge Command not used
z
8.2.4
Asynchronous read in Page Mode supported (4- up to 32-byte page size)
Refresh Error Interrupt
Error Corrected Code Controller
z
Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
z
Single bit error correction and 2-bit Random detection
z
Automatic Hamming Code Calculation while writing
z
Automatic Hamming Code Calculation while reading
z
ECC value available in a register
z
Error Report, including error flag, correctable error flag and word address being detected erroneous
z
Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
22
9.
System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets,
clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the
chip configuration. The chip configuration registers configure EBI chip select assignment and voltage range for external
memories
The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between addresses
0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All the registers of the
System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store
instruction has an indexing mode of ±4 Kbytes.
Figure 9-1 on page 24 shows the System Controller block diagram.
Figure 8-1 on page 19 shows the mapping of the User Interfaces of the System Controller peripherals.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
23
9.1
System Controller Block Diagram
Figure 9-1. SAM9260 System Controller Block Diagram
System Controller
VDDCORE Powered
irq0-irq2
fiq
periph_irq[2..24]
nirq
nfiq
Advanced
Interrupt
Controller
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
int
MCK
periph_nreset
Debug
Unit
dbgu_irq
dbgu_txd
dbgu_rxd
MCK
debug
periph_nreset
Periodic
Interval
Timer
pit_irq
Watchdog
Timer
wdt_irq
periph_nreset
Bus Matrix
rstc_irq
por_ntrst
jtag_nreset
VDDCORE
POR
Reset
Controller
periph_nreset
proc_nreset
backup_nreset
VDDBU
VDDBU
POR
VDDBU Powered
UHPCK
periph_clk[20]
periph_nreset
Real-time
Timer
rtt_irq
rtt_alarm
UDPCK
SLCK
SHDN
periph_clk[10]
WKUP
RC
OSC
USB Host
Port
periph_irq[20]
SLCK
SLCK
backup_nreset
backup_nreset
Shutdown
Controller
periph_nreset
USB
Device
Port
periph_irq[10]
rtt0_alarm
SLOW
CLOCK
OSC
4 General-purpose
Backup Registers
SLCK
XIN
Boundary Scan
TAP Controller
MCK
NRST
XIN32
PCK
debug
wdt_fault
WDRPROC
XOUT32
ARM926EJ-S
proc_nreset
jtag_nreset
SLCK
debug
idle
proc_nreset
OSC_SEL
ntrst
por_ntrst
periph_clk[2..27]
pck[0-1]
int
MAIN
OSC
MAINCK
XOUT
PLLRCA
PLLA
PLLACK
PLLB
PCK
Power
Management
Controller
UDPCK
UHPCK
MCK
PLLBCK
pmc_irq
periph_nreset
periph_clk[6..24]
idle
periph_nreset
periph_nreset
periph_clk[2..4]
dbgu_rxd
PA0-PA31
PB0-PB31
PC0-PC31
PIO
Controllers
periph_irq[2..4]
irq0-irq2
fiq
dbgu_txd
Embedded
Peripherals
periph_irq[6..24]
in
out
enable
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
24
9.2
Reset Controller
z
Based on two Power-on-reset cells
z
z
Status of the last reset
z
z
Allows shaping a reset signal for the external devices
Shutdown Controller
z
9.4
Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or
watchdog reset
Controls the internal resets and the NRST pin output
z
9.3
One on VDDBU and one on VDDCORE
Shutdown and Wake-up logic
z
Software programmable assertion of the SHDN pin
z
Deassertion Programmable on a WKUP pin level change or on alarm
Clock Generator
z
Embeds a Low-power 32,768 Hz Slow Clock Oscillator and a Low-power RC oscillator selectable with OSCSEL
signal
z
z
z
Provides the permanent Slow Clock SLCK to the system
Embeds the Main Oscillator
z
Oscillator bypass feature
z
Supports 3 to 20 MHz crystals
Embeds 2 PLLs
z
PLLA outputs 80 to 240 MHz clock
z
PLLB outputs 70 to 130 MHz clock
z
Both integrate an input divider to increase output accuracy
z
PLLB embeds its own filter
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
25
Figure 9-2. Clock Generator Block Diagram
Clock Generator
OSC_SEL
On Chip
RC OSC
XIN32
Slow Clock
SLCK
Slow Clock
Oscillator
XOUT32
XIN
Main
Oscillator
Main Clock
MAINCK
PLL and
Divider A
PLLA Clock
PLLACK
PLL and
Divider B
PLLB Clock
PLLBCK
XOUT
PLLRCA
Status
Control
Power
Management
Controller
9.5
Power Management Controller
z
z
Provides:
z
the Processor Clock PCK
z
the Master Clock MCK, in particular to the Matrix and the memory interfaces
z
the USB Device Clock UDPCK
z
independent peripheral clocks, typically at the frequency of MCK
z
2 programmable clock outputs: PCK0, PCK1
Five flexible operating modes:
z
Normal Mode, processor and peripherals running at a programmable frequency
z
Idle Mode, processor stopped waiting for an interrupt
z
Slow Clock Mode, processor and peripherals running at low frequency
z
Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped
waiting for an interrupt
z
Backup Mode, Main Power Supplies off, VDDBU powered by a battery
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
26
Figure 9-3. SAM9260 Power Management Controller Block Diagram
Processor
Clock
Controller
int
Master Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
PCK
Idle Mode
Divider
/1,/2,/4
Prescaler
/1,/2,/4,...,/64
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
USB Clock Controller
ON/OFF
PLLBCK
9.6
9.7
9.8
9.9
Periodic Interval Timer
z
Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
z
Includes a 12-bit Interval Overlay Counter
z
Real Time OS or Linux®/Windows CE® compliant tick generator
Watchdog Timer
z
16-bit key-protected only-once-Programmable Counter
z
Windowed, prevents the processor being in a dead-lock on the watchdog access
Real-time Timer
z
Real-time Timer 32-bit free-running back-up Counter
z
Integrates a 16-bit programmable prescaler running on slow clock
z
Alarm Register capable of generating a wake-up of the system through the Shutdown Controller
General-purpose Back-up Registers
z
9.10
UDPCK
UHPCK
Divider
/1,/2,/4
Four 32-bit backup general-purpose registers
Advanced Interrupt Controller
z
Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
z
Thirty-two individually maskable and vectored interrupt sources
z
z
Source 0 is reserved for the Fast Interrupt Input (FIQ)
z
Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
z
Programmable Edge-triggered or Level-sensitive Internal Sources
z
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
Three External Sources plus the Fast Interrupt signal
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
27
z
z
8-level Priority Controller
z
Drives the Normal Interrupt of the processor
z
Handles priority of the interrupt sources 1 to 31
z
Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
z
Optimizes Interrupt Service Routine Branch and Execution
z
One 32-bit Vector Register per interrupt source
z
Interrupt Vector Register reads the corresponding current Interrupt Vector
z
Protect Mode
z
Fast Forcing
z
z
9.11
Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
Debug Unit
z
z
z
Composed of two functions:
z
Two-pin UART
z
Debug Communication Channel (DCC) support
Two-pin UART
z
Implemented features are 100% compatible with the standard Atmel ® USART
z
Independent receiver and transmitter with a common programmable Baud Rate Generator
z
Even, Odd, Mark or Space Parity Generation
z
Parity, Framing and Overrun Error Detection
z
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
z
Support for two PDC channels with connection to receiver and transmitter
Debug Communication Channel Support
z
9.12
Easy debugging by preventing automatic operations when protect models are enabled
Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE
Interface
Chip Identification
z
Chip ID: 0x019803A2
z
JTAG ID: 0x05B1303F
z
ARM926 TAP ID: 0x0792603F
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
28
10.
Peripherals
10.1
User Interface
The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and
0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in
Figure 8-1 on page 19.
10.2
Identifiers
Table 10-1 defines the Peripheral Identifiers of the SAM9260. A peripheral identifier is required for the control of the
peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power
Management Controller.
Table 10-1. SAM9260 Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
Peripheral Name
External Interrupt
0
AIC
Advanced Interrupt Controller
FIQ
1
SYSC
System Controller Interrupt
2
PIOA
Parallel I/O Controller A
3
PIOB
Parallel I/O Controller B
4
PIOC
Parallel I/O Controller C
5
ADC
Analog to Digital Converter
6
US0
USART 0
7
US1
USART 1
8
US2
USART 2
9
MCI
Multimedia Card Interface
10
UDP
USB Device Port
11
TWI
Two-wire Interface
12
SPI0
Serial Peripheral Interface 0
13
SPI1
Serial Peripheral Interface 1
14
SSC
Synchronous Serial Controller
15
-
Reserved
16
-
Reserved
17
TC0
Timer/Counter 0
18
TC1
Timer/Counter 1
19
TC2
Timer/Counter 2
20
UHP
USB Host Port
21
EMAC
Ethernet MAC
22
ISI
Image Sensor Interface
23
US3
USART 3
24
US4
USART 4
25
US5
USART 5
26
TC3
Timer/Counter 3
27
TC4
Timer/Counter 4
28
TC5
Timer/Counter 5
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
29
Table 10-1. SAM9260 Peripheral Identifiers (Continued)
Peripheral ID
Peripheral Mnemonic
Peripheral Name
External Interrupt
29
AIC
Advanced Interrupt Controller
IRQ0
30
AIC
Advanced Interrupt Controller
IRQ1
31
AIC
Advanced Interrupt Controller
IRQ2
Note:
Setting AIC, SYSC, UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect.
10.2.1 Peripheral Interrupts and Clock Control
10.2.1.1 System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
z
the SDRAM Controller
z
the Debug Unit
z
the Periodic Interval Timer
z
the Real-time Timer
z
the Watchdog Timer
z
the Reset Controller
z
the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt
Controller.
10.2.1.2 External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated
Peripheral ID. However, there is no clock control associated with these peripheral IDs.
10.3
Peripheral Signal Multiplexing on I/O Lines
The SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Table
10-2 on page 31, Table 10-3 on page 32 and Table 10-4 on page 33 define how the I/O lines of the peripherals A and B
are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for
the user’s own comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only might be duplicated within both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O appears, the
PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is
released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets
low.
If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit
in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the
pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
30
10.3.1 PIO Controller A Multiplexing
Table 10-2. Multiplexing on PIO Controller A
PIO Controller A
I/O Line
Peripheral A
Peripheral B
PA0
SPI0_MISO
PA1
SPI0_MOSI
PA2
SPI0_SPCK
PA3
SPI0_NPCS0
PA4
Application Usage
Reset State
Power
Supply
MCDB0
I/O
VDDIOP0
MCCDB
I/O
VDDIOP0
I/O
VDDIOP0
MCDB3
I/O
VDDIOP0
RTS2
MCDB2
I/O
VDDIOP0
PA5
CTS2
MCDB1
I/O
VDDIOP0
PA6
MCDA0
I/O
VDDIOP0
PA7
MCCDA
I/O
VDDIOP0
PA8
MCCK
I/O
VDDIOP0
PA9
MCDA1
I/O
VDDIOP0
PA10
MCDA2
ETX2
I/O
VDDIOP0
PA11
MCDA3
ETX3
I/O
VDDIOP0
PA12
ETX0
I/O
VDDIOP0
PA13
ETX1
I/O
VDDIOP0
PA14
ERX0
I/O
VDDIOP0
PA15
ERX1
I/O
VDDIOP0
PA16
ETXEN
I/O
VDDIOP0
PA17
ERXDV
I/O
VDDIOP0
PA18
ERXER
I/O
VDDIOP0
PA19
ETXCK
I/O
VDDIOP0
PA20
EMDC
I/O
VDDIOP0
PA21
EMDIO
I/O
VDDIOP0
PA22
ADTRG
ETXER
I/O
VDDIOP0
PA23
TWD
ETX2
I/O
VDDIOP0
PA24
TWCK
ETX3
I/O
VDDIOP0
PA25
TCLK0
ERX2
I/O
VDDIOP0
PA26
TIOA0
ERX3
I/O
VDDIOP0
PA27
TIOA1
ERXCK
I/O
VDDIOP0
PA28
TIOA2
ECRS
I/O
VDDIOP0
PA29
SCK1
ECOL
I/O
VDDIOP0
PA30(1)
SCK2
RXD4
I/O
VDDIOP0
(1)
SCK0
TXD4
I/O
VDDIOP0
PA31
Note:
Comments
Function
Comments
1. Not available in the 208-lead PQFP package.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
31
10.3.2 PIO Controller B Multiplexing
Table 10-3. Multiplexing on PIO Controller B
PIO Controller B
I/O Line
Peripheral A
Peripheral B
PB0
SPI1_MISO
PB1
Application Usage
Comments
Reset State
Power
Supply
TIOA3
I/O
VDDIOP0
SPI1_MOSI
TIOB3
I/O
VDDIOP0
PB2
SPI1_SPCK
TIOA4
I/O
VDDIOP0
PB3
SPI1_NPCS0
TIOA5
I/O
VDDIOP0
PB4
TXD0
I/O
VDDIOP0
PB5
RXD0
I/O
VDDIOP0
PB6
TXD1
TCLK1
I/O
VDDIOP0
PB7
RXD1
TCLK2
I/O
VDDIOP0
PB8
TXD2
I/O
VDDIOP0
PB9
RXD2
I/O
VDDIOP0
PB10
TXD3
ISI_D8
I/O
VDDIOP1
PB11
RXD3
ISI_D9
I/O
VDDIOP1
(1)
TXD5
ISI_D10
I/O
VDDIOP1
(1)
PB13
RXD5
ISI_D11
I/O
VDDIOP1
PB14
DRXD
I/O
VDDIOP0
PB15
DTXD
I/O
VDDIOP0
PB16
TK0
TCLK3
I/O
VDDIOP0
PB17
TF0
TCLK4
I/O
VDDIOP0
PB18
TD0
TIOB4
I/O
VDDIOP0
PB19
RD0
TIOB5
I/O
VDDIOP0
PB20
RK0
ISI_D0
I/O
VDDIOP1
PB21
RF0
ISI_D1
I/O
VDDIOP1
PB22
DSR0
ISI_D2
I/O
VDDIOP1
PB23
DCD0
ISI_D3
I/O
VDDIOP1
PB24
DTR0
ISI_D4
I/O
VDDIOP1
PB25
RI0
ISI_D5
I/O
VDDIOP1
PB26
RTS0
ISI_D6
I/O
VDDIOP1
PB27
CTS0
ISI_D7
I/O
VDDIOP1
PB28
RTS1
ISI_PCK
I/O
VDDIOP1
PB29
CTS1
ISI_VSYNC
I/O
VDDIOP1
PB30
PCK0
ISI_HSYNC
I/O
VDDIOP1
PB31
PCK1
I/O
VDDIOP1
PB12
Note:
Function
Comments
1. Not available in the 208-lead PQFP package.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
32
10.3.3 PIO Controller C Multiplexing
Table 10-4. Multiplexing on PIO Controller C
PIO Controller C
I/O Line
Peripheral A
Application Usage
Peripheral B
Comments
Reset State
Power
Supply
PC0
SCK3
AD0
I/O
VDDANA
PC1
PCK0
AD1
I/O
VDDANA
PC2(1)
PCK1
AD2
I/O
VDDANA
SPI1_NPCS3
AD3
I/O
VDDANA
(1)
PC3
PC4
A23
SPI1_NPCS2
A23
VDDIOM
PC5
A24
SPI1_NPCS1
A24
VDDIOM
PC6
TIOB2
CFCE1
I/O
VDDIOM
PC7
TIOB1
CFCE2
I/O
VDDIOM
PC8
NCS4/CFCS0
RTS3
I/O
VDDIOM
PC9
NCS5/CFCS1
TIOB0
I/O
VDDIOM
PC10
A25/CFRNW
CTS3
A25
VDDIOM
NCS2
SPI0_NPCS1
I/O
VDDIOM
IRQ0
NCS7
I/O
VDDIOM
PC13
FIQ
NCS6
I/O
VDDIOM
PC14
NCS3/NANDCS
IRQ2
I/O
VDDIOM
PC15
NWAIT
IRQ1
I/O
VDDIOM
PC16
D16
SPI0_NPCS2
I/O
VDDIOM
PC17
D17
SPI0_NPCS3
I/O
VDDIOM
PC18
D18
SPI1_NPCS1
I/O
VDDIOM
PC19
D19
SPI1_NPCS2
I/O
VDDIOM
PC20
D20
SPI1_NPCS3
I/O
VDDIOM
PC21
D21
EF100
I/O
VDDIOM
PC22
D22
TCLK5
I/O
VDDIOM
PC23
D23
I/O
VDDIOM
PC24
D24
I/O
VDDIOM
PC25
D25
I/O
VDDIOM
PC26
D26
I/O
VDDIOM
PC27
D27
I/O
VDDIOM
PC28
D28
I/O
VDDIOM
PC29
D29
I/O
VDDIOM
PC30
D30
I/O
VDDIOM
PC31
D31
I/O
VDDIOM
PC11
PC12
Note:
(1)
Function
Comments
1. Not available in the 208-lead PQFP package.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
33
10.4
Embedded Peripherals
10.4.1 Serial Peripheral Interface
z
z
z
Supports communication with serial external devices
z
Four chip selects with external decoder support allow communication with up to 15 peripherals
z
Serial memories, such as DataFlash and 3-wire EEPROMs
z
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
z
External co-processors
Master or slave serial peripheral bus interface
z
8- to 16-bit programmable data length per chip select
z
Programmable phase and polarity per chip select
z
Programmable transfer delays between consecutive transfers and between clock and data per chip select
z
Programmable delay between consecutive transfers
z
Selectable mode fault detection
Very fast transfers supported
z
Transfers with baud rates up to MCK
z
The chip select line may be left active to speed up transfers on the same device
10.4.2 Two-wire Interface
z
Master, MultiMaster and Slave modes supported
z
General Call supported in Slave mode
10.4.3 USART
z
Programmable Baud Rate Generator
z
5- to 9-bit full-duplex synchronous or asynchronous serial communications
z
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
z
Parity generation and error detection
z
Framing error detection, overrun error detection
z
MSB- or LSB-first
z
Optional break generation and detection
z
By 8 or by-16 over-sampling receiver frequency
z
Hardware handshaking RTS-CTS
z
Optional modem signal management DTR-DSR-DCD-RI
z
Receiver time-out and transmitter timeguard
z
Optional Multi-drop Mode with address generation and detection
z
RS485 with driver control signal
z
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
z
IrDA modulation and demodulation
z
z
z
NACK handling, error counter with repetition and iteration limit
Communication at up to 115.2 Kbps
Test Modes
z
Remote Loopback, Local Loopback, Automatic Echo
The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the SAM9260,
only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0.
The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and
CTS2, respectively) are implemented in these USARTs for other features.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
34
Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these
USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem
signals are never activated.
10.4.4 Serial Synchronous Controller
z
Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master
or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
z
Contains an independent receiver and transmitter and a common clock divider
z
Offers a configurable frame sync and data length
z
Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame
sync signal
z
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
10.4.5 Timer Counter
z
Two blocks of three 16-bit Timer Counter channels
z
Each channel can be individually programmed to perform a wide range of functions including:
z
z
Note:
z
Frequency Measurement
z
Event Counting
z
Interval Measurement
z
Pulse Generation
z
Delay Timing
z
Pulse Width Modulation
z
Up/down Capabilities
Each channel is user-configurable and contains:
z
Three external clock inputs
z
Five internal clock inputs
z
Two multi-purpose input/output signals
Each block contains two global registers that act on all three TC Channels
TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See Figure 8-1,
“SAM9260 Memory Mapping,” on page 19 for TC Block 0 and TC Block 1 base addresses.
10.4.6 Multimedia Card Interface
z
One double-channel MultiMedia Card Interface
z
Compatibility with MultiMedia Card Specification Version 3.11
z
Compatibility with SD Memory Card Specification Version 1.1
z
Compatibility with SDIO Specification Version V1.0.
z
Card clock rate up to Master Clock divided by 2
z
Embedded power management to slow down clock rate when not used
z
MCI has two slots, each supporting
z
z
One slot for one MultiMediaCard bus (up to 30 cards) or
z
One SD Memory Card
Support for stream, block and multi-block data read and write
10.4.7 USB Host Port
z
Compliance with Open HCI Rev 1.0 Specification
z
Compliance with USB V2.0 Full-speed and Low-speed Specification
z
Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
35
z
Root hub integrated with two downstream USB ports in the 217-LFBGA package
z
Two embedded USB transceivers
z
Supports power management
z
Operates as a master on the Matrix
10.4.8 USB Device Port
z
USB V2.0 full-speed compliant, 12 MBits per second
z
Embedded USB V2.0 full-speed transceiver
z
Embedded 2,432-byte dual-port RAM for endpoints
z
Suspend/Resume logic
z
Ping-pong mode (two memory banks) for isochronous and bulk endpoints
z
Six general-purpose endpoints
z
z
Endpoint 0 and 3: 64 bytes, no ping-pong mode
z
Endpoint 1 and 2: 64 bytes, ping-pong mode
z
Endpoint 4 and 5: 512 bytes, ping-pong mode
Embedded pad pull-up
10.4.9 Ethernet 10/100 MAC
z
Compatibility with IEEE Standard 802.3
z
10 and 100 MBits per second data throughput capability
z
Full- and half-duplex operations
z
MII or RMII interface to the physical layer
z
Register Interface to address, data, status and control registers
z
DMA Interface, operating as a master on the Memory Controller
z
Interrupt generation to signal receive and transmit completion
z
28-byte transmit and 28-byte receive FIFOs
z
Automatic pad and CRC generation on transmitted frames
z
Address checking logic to recognize four 48-bit addresses
z
Support promiscuous mode where all valid frames are copied to memory
z
Support physical layer management through MDIO interface
10.4.10 Image Sensor Interface
z
ITU-R BT. 601/656 8-bit mode external interface support
z
Support for ITU-R BT.656-4 SAV and EAV synchronization
z
Vertical and horizontal resolutions up to 2048 x 2048
z
Preview Path up to 640*480
z
Support for packed data formatting for YCbCr 4:2:2 formats
z
Preview scaler to generate smaller size image
z
Programmable frame capture rate
10.4.11 Analog-to-Digital Converter
z
4-channel ADC
z
10-bit 312K samples/sec. Successive Approximation Register ADC
z
-2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
z
Individual enable and disable of each channel
z
External voltage reference for better accuracy on low voltage inputs
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
36
z
Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0
to TIOA2 trigger
z
Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions
of all enabled channels
z
Four analog inputs shared with digital signals
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
37
11.
SAM9260 Mechanical Characteristics
11.1
Package Drawings
Figure 11-1. 217-ball LFBGA: Ball A1 Position
One or two ink (or laser) dots may be present on top of the package.
Optional. Atmel internal use Only.
Figure 11-2. 217-ball LFBGA Package Drawing
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
38
Table 11-1. 217-ball LFBGA Soldering Information
Ball Land
0.43 mm +/- 0.05
Soldering Mask Opening
0.30 mm +/- 0.05
Table 11-2. Device and 217-ball LFBGA Package Maximum Weight
450
mg
Table 11-3. 217-ball LFBGA Package Characteristics
Moisture Sensitivity Level
3
Table 11-4. Package Reference
JEDEC Drawing Reference
MO-205
JESD97 Classification
e1
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
39
Figure 11-3. 208-lead PQFP: Pin 1 Position
One or two ink (or laser) dots may be present on top of the package.
Optional, Atmel internal use Only.
Figure 11-4. 208-lead PQFP Package Drawing
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
40
Table 11-5. Device and 208-lead PQFP Package Maximum Weight
5.5
g
Table 11-6. 208-lead PQFP Package Characteristics
Moisture Sensitivity Level
3
Table 11-7. Package Reference
JEDEC Drawing Reference
MS-022
JESD97 Classification
e3
11.2
Soldering Profile
Table 11-8 gives the recommended soldering profile from J-STD-20.
Table 11-8. Soldering Profile
Profile Feature
PQFP208 Green Package
BGA217 Green Package
Average Ramp-up Rate (217°C to Peak)
3⋅ C/sec. max.
3⋅ C/sec. max.
Preheat Temperature 175°C ±25°C
180 sec. max.
180 sec. max.
Temperature Maintained Above 217°C
60 sec. to 150 sec.
60 sec. to 150 sec.
Time within 5⋅ C of Actual Peak Temperature
20 sec. to 40 sec.
20 sec. to 40 sec.
Peak Temperature Range
260 +0 ⋅ C
260 +0 ⋅ C
Ramp-down Rate
6⋅ C/sec. max.
6⋅ C/sec. max.
Time 25⋅ C to Peak Temperature
8 min. max.
8 min. max.
Note:
It is recommended to apply a soldering temperature higher than 250°C
A maximum of three reflow passes is allowed per component.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
41
12.
SAM9260 Ordering Information
Table 12-1. SAM9260 Ordering Information
Marketing Revision Level A
Ordering Code
Marketing Revision Level B
Ordering Code
Package
Package Type
AT91SAM9260-QU
AT91SAM9260B-QU
PQFP208
Green
AT91SAM9260-CU
AT91SAM9260B-CU
BGA217
Green
Temperature
Operating Range
Industrial
-40°C to 85°C
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
42
13.
Revision History
Table 13-1. Revision History - current version appears first
Revision
Comments
Change
Req. Ref.
6221LS
Removed: 208-pin Package and 217-ball package outlines: Formerly Figure 4-1 and Figure 4-2.
Added: Figure 11-1 ”217-ball LFBGA: Ball A1 Position” and Figure 11-3 ”208-lead PQFP: Pin 1
Position”.
8450
Changed document format: pagination has changed.
6221KS
6221JS
6221IS
Document title and name of product updated to conform to AT91SAM Marketing standards:
AT91SAM ARM-based MPU. AT91SAM9260 now referenced in text as SAM9260.
”Features”, removed SDCard from System list, boot possibilities.
7142
Line added to Debug Unit
5846
Note edited after Table 10-1, “SAM9260 Peripheral Identifiers” on page 29
5854
‘Manchester Encoding/Decoding’ removed from USART
5933
Section 6.6 “Shutdown Logic Pins” on page 13 edited
6030
Features list shortened and reorganized, from new structure in Datasheet AT91SAM9G45
RFO
Section 12. “SAM9260 Ordering Information” on page 42, New Ordering codes for Version B
added.
5686
Table 3-1, “Signal Description List”, Image Sensor Interface, ISI_MCK line, added comments.
5330
Table 10-3, “Multiplexing on PIO Controller B”, PB31 line, removed ISI_MCK.
Table 3-1, “Signal Description List”, Reset/Test, BMS line, added comments.
5422
6221HS
”Power Considerations”,in Section 5.1 ”Power Supplies”, VDDCORE and VDDBU startup
voltage restraints removed.
5229
6221GS
Updated all references to 217-ball LFBGA to Green package.
Review
In Section 5.1 “Power Supplies” on page 12, VDDCORE and VDDBU, added information on
supply voltage during startup.
Review
In Section 6.5 “I/O Line Drive Levels” on page 13, added information on PC4 to PC31.
Review
In Section 6.7 “Slow Clock Selection” on page 14, corrected startup delay for internal RC
oscillator.
Review
In Section 10.4.6 “Multimedia Card Interface” on page 35, corrected specification version
compatibility.
4944
In Section 8.1.1 “Boot Strategies” on page 20, removed sentence “When REMAP = 1, BMS is
ignored.”
5026
Changed divider value for Master Clock Controller in Figure 9-3, “SAM9260 Power
Management Controller Block Diagram,” on page 27.
4833
Corrected package reference to PQFP in Figure 11-4, “208-lead PQFP Package Drawing,” on
page 40.
4740
Updated BGA ordering code in Section 12. “SAM9260 Ordering Information” on page 42.
4768
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
43
Table 13-1. Revision History - current version appears first
Revision
Comments
6221FS
All new information in Section 7.2.1 ”Matrix Masters”, Table 7-1, “List of Bus Matrix Masters,”
on page 16 and Section 7.2.3 ”Master to Slave Access”, Table 7-3, “SAM9260 Masters to
Slaves Access,” on page 16.
4457
In Figure 2-1 ”SAM9260 Block Diagram” on page 3, updated EBI signals NRD, NWR0, NWR1,
NWR3.
4431
Added details on Timer/Counter blocks in Section 10.4.5 “Timer Counter” on page 35.
4369
Updated Chip ID in Section 9.12 “Chip Identification” on page 28.
4582
Updated information on programmable pull-up resistor in Section 6.4 “PIO Controllers” on page
13.
3972
6221ES
Change
Req. Ref.
Updated Section 6.7 “Slow Clock Selection” on page 14.
6221DS
6221CS
6221BS
In Table 10-1, “SAM9260 Peripheral Identifiers,” on page 29, added Note on clocking and
corrected Peripheral Name for PID12, PID13 and PID14.
3504 and
3543
Placed comment on RDY/BUSY with PC13 in Table 10-4, “Multiplexing on PIO Controller C,”
on page 33.
3406
Removed references to VDDOSC in “Features” , in Table 3-1, “Signal Description List”, and in
Section 5.1 “Power Supplies” on page 12. Corrected VDDPLLA and VDDPLLB with VDDPLL
and GNDPLLA and GNDPLLB with GNDPLL in Table 4-1, “Pinout for 208-pin PQFP Package,”
on page 10 and in Table 4-2, “Pinout for 217-ball LFBGA Package,” on page 11.
3183
In Figure 2-1 on page 3, corrected range for SCKx pins; label change on matrix block.
3235,
3071
In Figure 2-1 on page 3 and Section 7.3 “Peripheral DMA Controller” on page 17, removed TWI
PDC channels.
3066
In Section 6.3 “Reset Pins” on page 13, added NRST as bidirectional.
3236
In Figure 9-3 on page 27, added UHPCK as USB Clock Controller output.
3237
In Section 10.4.3 “USART” on page 34, added information on modem signals.
3245
For VDDIOP1, added supported voltage levels in Table 3-1, “Signal Description List,” on
page 4 and corrected supported voltage levels in Section 5.2 “Power Consumption” on page
12.
2874
Removed package marking and updated package outline information in Section 4. “Package
and Pinout” on page 9.
2922
Change to signal name for pin 147 in Section 4-1 “Pinout for 208-pin PQFP Package” on page
10.
2907
Inserted new voltage information for JTAGSEL signal in Table 3-1, “Signal Description List”
and in Section 6.1 “JTAG Port Pins” on page 13.
2947
In Table 3-1, “Signal Description List,” on page 4, added new voltage information for OSCSEL
and TST pins.
2979
In Section 6.3 “Reset Pins” on page 13, new information on NRST and NRTST pins.
3003
Corrected ADC features in Section 10.4.11 “Analog-to-Digital Converter” on page 36.
2923
Power consumption figures updated with current values in Section 5.2 “Power Consumption”
on page 12.
Change to signal name for pin 47 in Section 4-1 “Pinout for 208-pin PQFP Package” on page
10.
6221AS
2843
First issue.
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
44
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