AT91SAM9G20B-CFU

32-BIT ARM-BASED MICROPROCESSORS SAM9G20 Description The SAM9G20 embedded microprocessor unit is based on the integration of an Arm926EJ-S™ processor with fast ROM and RAM memories and a wide range of peripherals. The SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a dual port USB Host controller with on-chip USB transceivers. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The SAM9G20 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. The SAM9G20 is an enhancement of the SAM9260 with the same peripheral features. It is pin-to-pin compatible with the exception of power supply pins. Speed is increased to reach 400 MHz on the Arm core and 133 MHz on the system bus and EBI. Features • Incorporates the Arm926EJ-S Arm® Thumb® Processor - DSP Instruction Extensions, Arm Jazelle® Technology for Java® Acceleration - 32-Kbyte Data Cache, 32-Kbyte Instruction Cache, Write Buffer - CPU Frequency 400 MHz - Memory Management Unit - EmbeddedICE, Debug Communication Channel Support • Additional Embedded Memories - One 64-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed - Two 16-Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed • External Bus Interface (EBI) - Supports SDRAM, Static Memory, ECC-enabled SLC NAND Flash and CompactFlash® • USB 2.0 Full Speed (12 Mbit/s) Device Port - On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM • USB 2.0 Full Speed (12 Mbit/s) Host and Dual Port - Single or Dual On-chip Transceivers - Integrated FIFOs and Dedicated DMA Channels • Ethernet MAC 10/100 Base T - Media Independent Interface or Reduced Media Independent Interface - 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit • Image Sensor Interface - ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate - 12-bit Data Interface for Support of High Sensibility Sensors - SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format • Bus Matrix - Six 32-bit-layer Matrix - Boot Mode Select Option, Remap Command • Fully-featured System Controller, including - Reset Controller, Shutdown Controller - 128-bit (4 x 32-bit) General Purpose Backup Registers - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit  2017 Microchip Technology Inc. DS60001516A-page 1 SAM9G20 - Periodic Interval Timer, Watchdog Timer and Real-time Timer • Reset Controller (RSTC) - Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control • Clock Generator (CKGR) - Selectable 32768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 3 to 20 MHz On-chip Oscillator, One up to 800 MHz PLL and One up to 100 MHz PLL • Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Two Programmable External Clock Signals • Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected • Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention - Mode for General Purpose 2-wire UART Serial Communication • Periodic Interval Timer (PIT) - 20-bit Interval Timer plus 12-bit Interval Counter • Watchdog Timer (WDT) - Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock • Real-time Timer (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler • One 4-channel 10-bit Analog-to-Digital Converter • Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) - 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output - All I/O Lines are Schmitt Trigger Inputs • Peripheral DMA Controller Channels (PDC) • One Two-slot MultiMedia Card Interface (MCI) - SDCard/SDIO and MultiMediaCard™ Compliant - Automatic Protocol Control and Fast Automatic Data Transfers with PDC • One Synchronous Serial Controller (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - I²S Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer • Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support - Full Modem Signal Control on USART0 • Two 2-wire UARTs • Two Master/Slave Serial Peripheral Interfaces (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects - Synchronous Communications • Two Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability - High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2 • One Two-wire Interface (TWI) - Compatible with Standard Two-wire Serial Memories - One, Two or Three Bytes for Slave Address - Sequential Read/Write Operations - Master, Multi-master and Slave Mode Operation - Bit Rate: Up to 400 Kbit/s - General Call Supported in Slave Mode DS60001516A-page 2  2017 Microchip Technology Inc. SAM9G20 - Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode • IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies - 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL - 1.65 to 3.6V for VDDOSC - 1.65V to 3.6V for VDDIOP (Peripheral I/Os) - 3.0V to 3.6V for VDDUSB - 3.0V to 3.6V VDDANA (Analog-to-Digital Converter) - Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in 217-ball LFBGA and 247-ball TFBGA Green-compliant Packages  2017 Microchip Technology Inc. DS60001516A-page 3 Block Diagram FIQ IRQ0–IRQ2 AIC DRXD DTXD PCK0–PCK1 DBGU In-Circuit Emulator Filter Filter M CK IS PC I_ K IS D0 I_ –I V IS SY SI_ I_ N D7 HS C YN C HD P HD A M A HD PB HD M B I_ I_ 10/100 Ethernet MAC Arm926EJ-S Processor ICache 32 Kbytes DCache 32 Kbytes MMU FIFO I PMC Image Sensor Interface USB OHCI DMA DMA D PLLB Main Oscillator WDT PIT RC Osc. OSCSEL XIN32 XOUT32 6-layer Matrix 128-bit GPBR Slow Clock Oscillator SHDN WKUP VDDBU POR VDDCORE POR RTT PIOA ROM 64 Kbytes PIOB SHDWC Fast SRAM 16 Kbytes Fast SRAM 16 Kbytes EBI 24-channel Peripheral DMA Peripheral Bridge PIOC CompactFlash NAND Flash RSTC NRST APB SDRAM Controller PDC MCI PDC TWI PDC USART0 USART1 USART2 USART3 USART4 USART5 PDC SPI0 SPI1 PDC TC0 TC1 TC2 TC3 TC4 TC5 SSC DPRAM PDC 4-channel 10-bit ADC USB Device DD DDM P A AN ND EF NA G VR DA AD VD NP NPCS NPCS3 NPCS2 C 1 SP S0 M CK O TC M SI IS L O TI K0 O –T TI A0 C O – LK TC B0–TIO 2 L T A TI K3 IOB2 O – TI A3 TC 2 O – LK B3 TI 5 –T OA IO 5 B5 TK TF TD RD RF R AD K 0– A AD D3 TR IG –M CD A0 MC B3 –M CD C B M DA CC 3 M DA CC K TW CT TW D RTS0 CK – SC S0 CT RX K0 –RTS3 – S TXD0– SC 3 D0 RX K3 –T D 5 DSXD5 DCR0 D0 R DT I0 R0 B0 CD M SPI0_, SPI1_ D0–D15 A0/NBS0 A1/NBS2/NWR2 A2–A15, A18–A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE, A22/NANDCLE D16–D31 NWAIT A23–A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1–CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS SAM9G20 DS60001516A-page 4 CD Static Memory Controller ECC Controller Transceiver M Transc. FIFO DMA Bus Interface PLLA IS Transc. PDC XIN XOUT S JTAG Selection and Boundary Scan System Controller TST IS SLAVE L MASTER ET ETXC K ECXE -E N R ERRS -E XC T ERXE -EC XE K R O ET X0 -E L R – R M X0 ER XD D – M C ET X3 V DI X3 F1 O 00 SAM9G20 Block Diagram BM Figure 1-1: TD TDI TMO TC S RTK CK JT AG SE  2017 Microchip Technology Inc. 1. SAM9G20 2. Signal Description Table 2-1: Signal Description List Signal Name Function Type Active Level Comments Power Supplies VDDIOM EBI I/O Lines Power Supply Power – 1.65–1.95 V or 3.0–3.6 V VDDIOP Peripherals I/O Lines Power Supply Power – 1.65–3.6 V VDDBU Backup I/O Lines Power Supply Power – 0.9–1.1 V VDDANA Analog Power Supply Power – 3.0–3.6 V VDDPLL PLL Power Supply Power – 0.9–1.1 V VDDOSC Oscillator Power Supply Power – 1.65–3.6 V VDDCORE Core Chip Power Supply Power – 0.9–1.1 V VDDUSB USB Power Supply Power – 1.65–3.6 V GND Ground Ground – GNDANA Analog Ground Ground – GNDBU Backup Ground Ground – GNDUSB USB Ground Ground – GNDPLL PLL Ground Ground – Clocks, Oscillators and PLLs XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output OSCSEL Slow Clock Oscillator Selection PCK0–PCK1 Programmable Clock Output Input – Output – Input – Output – Input – Output – Accepts between 0V and VDDBU Shutdown, Wakeup Logic SHDN Shutdown Control WKUP Wake-up Input Output – Input – Accepts between 0V and VDDBU ICE and JTAG NTRST Test Reset Signal Input Low TCK Test Clock Input – No pull-up resistor TDI Test Data In Input – No pull-up resistor TDO Test Data Out Output – TMS Test Mode Select Input – No pull-up resistor JTAGSEL JTAG Selection Input – Pull-down resistor. Accepts between 0V and VDDBU. RTCK Return Test Clock Output –  2017 Microchip Technology Inc. Pull-up resistor DS60001516A-page 5 SAM9G20 Table 2-1: Signal Description List Signal Name Function Type Active Level I/O Low Input – Comments Reset/Test NRST Microprocessor Reset TST Test Mode Select Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor BMS Boot Mode Select Input – BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP Debug Unit - DBGU DRXD Debug Receive Data Input – DTXD Debug Transmit Data Output – Advanced Interrupt Controller - AIC IRQ0–IRQ2 External Interrupt Inputs Input – FIQ Fast Interrupt Input Input – PIO Controller - PIOA / PIOB / PIOC PA0–PA31 Parallel IO Controller A I/O – Pulled-up input at reset PB0–PB31 Parallel IO Controller B I/O – Pulled-up input at reset PC0–PC31 Parallel IO Controller C I/O – Pulled-up input at reset I/O – Pulled-up input at reset Output – 0 at reset Input Low External Bus Interface - EBI D0–D31 Data Bus A0–A25 Address Bus NWAIT External Wait Signal Static Memory Controller - SMC NCS0–NCS7 Chip Select Lines Output Low NWR0–NWR3 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS3 Byte Mask Signal Output Low CompactFlash Support CFCE1–CFCE2 CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash IO Read Output Low CFIOW CompactFlash IO Write Output Low CFRNW CompactFlash Read Not Write Output – CFCS0–CFCS1 CompactFlash Chip Select Lines Output Low DS60001516A-page 6  2017 Microchip Technology Inc. SAM9G20 Table 2-1: Signal Description List Signal Name Function Type Active Level Comments NAND Flash Support NANDCS NAND Flash Chip Select Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDALE NAND Flash Address Latch Enable Output Low NANDCLE NAND Flash Command Latch Enable Output Low SDRAM Controller - SDRAMC SDCK SDRAM Clock Output – SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low BA0–BA1 Bank Select Output – SDWE SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output – Multimedia Card Interface - MCI MCCK Multimedia Card Clock Output – MCCDA Multimedia Card Slot A Command I/O – MCDA0–MCDA3 Multimedia Card Slot A Data I/O – MCCDB Multimedia Card Slot B Command I/O – MCDB0–MCDB3 Multimedia Card Slot B Data I/O – Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock I/O – TXDx USARTx Transmit Data I/O – RXDx USARTx Receive Data Input – RTSx USARTx Request To Send Output – CTSx USARTx Clear To Send Input – DTR0 USART0 Data Terminal Ready Output – DSR0 USART0 Data Set Ready Input – DCD0 USART0 Data Carrier Detect Input – RI0 USART0 Ring Indicator Input – Synchronous Serial Controller - SSC TD SSC Transmit Data Output – RD SSC Receive Data Input – TK SSC Transmit Clock I/O – RK SSC Receive Clock I/O – TF SSC Transmit Frame Sync I/O –  2017 Microchip Technology Inc. DS60001516A-page 7 SAM9G20 Table 2-1: Signal Description List Signal Name Function RF SSC Receive Frame Sync Type Active Level I/O – Comments Timer/Counter - TCx TCLKx TC Channel x External Clock Input Input – TIOAx TC Channel x I/O Line A I/O – TIOBx TC Channel x I/O Line B I/O – Serial Peripheral Interface - SPIx SPIx_MISO Master In Slave Out I/O – SPIx_MOSI Master Out Slave In I/O – SPIx_SPCK SPI Serial Clock I/O – SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS1–SPIx_NPCS3 SPI Peripheral Chip Select Output Low Two-Wire Interface - TWI TWD Two-wire Serial Data I/O – TWCK Two-wire Serial Clock I/O – USB Host Port - UHP HDPA USB Host Port A Data + Analog – HDMA USB Host Port A Data - Analog – HDPB USB Host Port B Data + Analog – HDMB USB Host Port B Data - Analog – USB Device Port - UDP DDM USB Device Port Data - Analog – DDP USB Device Port Data + Analog – Ethernet MAC 10/100 - EMAC ETXCK Transmit Clock or Reference Clock Input – MII only, REFCK in RMII ERXCK Receive Clock Input – MII only ETXEN Transmit Enable Output – ETX0–ETX3 Transmit Data Output – ETX0–ETX1 only in RMII ETXER Transmit Coding Error Output – MII only ERXDV Receive Data Valid Input – RXDV in MII, CRSDV in RMII ERX0–ERX3 Receive Data Input – ERX0–ERX1 only in RMII ERXER Receive Error Input – ECRS Carrier Sense and Data Valid Input – MII only ECOL Collision Detect Input – MII only EMDC Management Data Clock Output – EMDIO Management Data Input/Output I/O – DS60001516A-page 8  2017 Microchip Technology Inc. SAM9G20 Table 2-1: Signal Description List Signal Name Function Type Active Level Comments Image Sensor Interface - ISI ISI_D0-ISI_D11 Image Sensor Data Input – ISI_MCK Image Sensor Reference Clock Output – ISI_HSYNC Image Sensor Horizontal Synchro Input – ISI_VSYNC Image Sensor Vertical Synchro Input – ISI_PCK Image Sensor Data clock Input – Analog-to-Digital Converter - ADC AD0-AD3 Analog Inputs Analog – ADVREF Analog Positive Reference Analog – ADTRG ADC Trigger Input –  2017 Microchip Technology Inc. Digital pulled-up inputs at reset DS60001516A-page 9 SAM9G20 3. Package and Pinout The SAM9G20 is available in the following Green-compliant packages: • 217-ball LFBGA, 15 x 15 mm x 1.4 mm (0.8 mm pitch) • 247-ball TFBGA, 10 x 10 x 1.1 mm (0.5 mm pitch) 3.1 217-ball LFBGA Package Outline Figure 3-1 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in Section 41.1 “217-ball LFBGA Package Drawing”. Figure 3-1: 217-ball LFBGA Package (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U Ball A1 3.2 217-ball LFBGA Pinout Table 3-1: Pinout for 217-ball LFBGA Package Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 CFIOW/NBS3/NWR3 D5 A5 J14 TDO P17 PB5 A2 NBS0/A0 D6 GND J15 PB19 R1 NC A3 NWR2/NBS2/A1 D7 A10 J16 TDI R2 GNDANA A4 A6 D8 GND J17 PB16 R3 PC29 A5 A8 D9 VDDCORE K1 PC24 R4 VDDANA A6 A11 D10 GNDUSB K2 PC20 R5 PB12 A7 A13 D11 VDDIOM K3 D15 R6 PB23 A8 BA0/A16 D12 GNDUSB K4 PC21 R7 GND A9 A18 D13 DDM K8 GND R8 PB26 A10 A21 D14 HDPB K9 GND R9 PB28 A11 A22 D15 NC K10 GND R10 PA0 A12 CFWE/NWE/NWR0 D16 VDDBU K14 PB4 R11 PA4 A13 CFOE/NRD D17 XIN32 K15 PB17 R12 PA5 A14 NCS0 E1 D10 K16 GND R13 PA10 DS60001516A-page 10  2017 Microchip Technology Inc. SAM9G20 Table 3-1: Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A15 PC5 E2 D5 K17 PB15 R14 PA21 A16 PC6 E3 D3 L1 GND R15 PA23 A17 PC4 E4 D4 L2 PC26 R16 PA24 B1 SDCK E14 HDPA L3 PC25 R17 PA29 B2 CFIOR/NBS1/NWR1 E15 HDMA L4 VDDOSC T1 NC B3 SDCS/NCS1 E16 GNDBU L14 PA28 T2 GNDPLL B4 SDA10 E17 XOUT32 L15 PB9 T3 PC0 B5 A3 F1 D13 L16 PB8 T4 PC1 B6 A7 F2 SDWE L17 PB14 T5 PB10 B7 A12 F3 D6 M1 VDDCORE T6 PB22 B8 A15 F4 GND M2 PC31 T7 GND B9 A20 F14 OSCSEL M3 GND T8 PB29 B10 NANDWE F15 BMS M4 PC22 T9 PA2 B11 PC7 F16 JTAGSEL M14 PB1 T10 PA6 B12 PC10 F17 TST M15 PB2 T11 PA8 B13 PC13 G1 PC15 M16 PB3 T12 PA11 B14 PC11 G2 D7 M17 PB7 T13 VDDCORE B15 PC14 G3 SDCKE N1 XIN T14 PA20 B16 PC8 G4 VDDIOM N2 VDDPLL T15 GND B17 WKUP G14 GND N3 PC23 T16 PA22 C1 D8 G15 NRST N4 PC27 T17 PA27 C2 D1 G16 RTCK N14 PA31 U1 GNDPLL C3 CAS G17 TMS N15 PA30 U2 ADVREF C4 A2 H1 PC18 N16 PB0 U3 PC2 C5 A4 H2 D14 N17 PB6 U4 PC3 C6 A9 H3 D12 P1 XOUT U5 PB20 C7 A14 H4 D11 P2 VDDPLL U6 PB21 C8 BA1/A17 H8 GND P3 PC30 U7 PB25 C9 A19 H9 GND P4 PC28 U8 PB27 C10 NANDOE H10 GND P5 PB11 U9 PA12 C11 PC9 H14 VDDCORE P6 PB13 U10 PA13 C12 PC12 H15 TCK P7 PB24 U11 PA14 C13 DDP H16 NTRST P8 VDDIOP U12 PA15 C14 HDMB H17 PB18 P9 PB30 U13 PA19 C15 NC J1 PC19 P10 PB31 U14 PA17 C16 VDDUSB J2 PC17 P11 PA1 U15 PA16  2017 Microchip Technology Inc. DS60001516A-page 11 SAM9G20 Table 3-1: Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name C17 SHDN J3 VDDIOM P12 PA3 U16 PA18 D1 D9 J4 PC16 P13 PA7 U17 VDDIOP D2 D2 J8 GND P14 PA9 D3 RAS J9 GND P15 PA26 D4 D0 J10 GND P16 PA25 3.3 247-ball TFBGA Package Outline Figure 3-2 shows the orientation of the 247-ball TFBGA package. A detailed mechanical description is given in Section 41.2 “247-ball TFBGA Package Drawing”. Figure 3-2: 247-ball TFBGA Package (Top View) Ball A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J K L M N P R T U V W 3.4 247-ball TFBGA Package Pinout Table 3-2: Pinout for 247-ball TFBGA Package Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 D13 F7 CFIOR/NBS1/NWR1 K10 GND P17 RTCK A2 D12 F8 SDA10 K11 VDDIOM P18 PB16 A12 A9 F9 NBS0/A0 K12 GND R2 GND A14 A13 F10 A6 K13 GND R3 PB29 A16 A20 F11 A12 K14 XOUT32 R5 PB26 A18 A22 F12 A15 K15 XIN32 R6 PB27 A19 NANDOE F13 BA1/A17 K17 HDPA R7 PA5 B1 D15 F14 PC10 K18 HDMA R8 GND B2 D14 F15 PC14 L2 NC R9 PA12 B3 D10 F16 VDDUSB L3 NC R10 GND DS60001516A-page 12  2017 Microchip Technology Inc. SAM9G20 Table 3-2: Pinout for 247-ball TFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name B4 D9 F17 PC9 L5 ADVREF R11 PA19 B5 D7 F18 PC12 L6 PC2 R12 PA26 B6 D3 G2 PC26 L7 GND R13 PB1 B7 D2 G3 PC25 L8 GND R14 GND B8 RAS G5 PC24 L9 GND R15 PB7 B9 CAS G6 PC21 L10 GND R17 PB14 B10 NWR2/NBS2/A1 G8 VDDCORE L11 VDDCORE R18 PB9 B11 A3 G9 A5 L12 GND T2 PA1 B13 A10 G10 VDDCORE L13 OSCSEL T3 PB10 B15 A18 G11 VDDCORE L14 GNDBU T17 PB19 B17 A21 G12 VDDCORE L15 GND T18 PB17 B19 VDDUSB G14 PC13 L17 NRST U2 GNDANA C2 PC15 G15 GND L18 TCK U3 PB21 C3 D11 G17 GNDUSB M2 PC0 U4 PB28 C4 D8 G18 PC11 M3 PC1 U5 PB31 C5 SDCKE H2 PC31 M5 PC3 U6 PA4 C6 SDWE H3 PC30 M6 NTRST U7 PA3 C7 SDCK H5 PC28 M7 GND U8 PA9 C8 D1 H6 PC27 M8 GND U9 GND C9 SDCS/NCS1 H7 PC29 M9 GND U10 PA15 C10 A2 H8 GND M10 PA16 U11 PA21 C11 A7 H9 GND M11 VDDCORE U12 PA25 C12 A11 H10 VDDIOM M12 GND U13 PA29 C14 A19 H11 VDDIOM M13 VDDIOP U14 PA27 C16 GNDUSB H12 GND M14 TST U15 PA31 C18 CFWE/NWE/NWR0 H13 VDDCORE M15 JTAGSEL U16 GND D2 PC17 H14 SHDW M17 PB18 U17 PB2 D3 PC16 H15 VDDBU M18 TMS U18 GND D13 A14 H17 HDPB N2 PB20 V1 PB12 D15 NANDWE H18 HDMB N3 PB13 V2 PB23 D17 CFOE/NRD J2 VDDOSC N5 PB11 V3 PB30 D19 NCS0 J3 VDDPLL N6 BMS V4 PA2 E2 PC18 J5 XOUT N8 GND V5 PA8 E3 PC19 J6 XIN N11 PA17 V6 PA10 E5 D6 J7 VDDPLL N12 PA23 V7 PA13 E6 D5 J8 GND N14 GND V8 VDDIOP  2017 Microchip Technology Inc. DS60001516A-page 13 SAM9G20 Table 3-2: Pinout for 247-ball TFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name E7 D0 J9 VDDIOM N15 VDDIOP V9 PA14 E8 CFIOW/NBS3/NWR3 J10 VDDIOM N17 TDO V10 VDDIOP E9 GND J11 VDDIOM N18 TDI V11 PA20 E10 A4 J12 GND P2 PB24 V12 PA22 E11 A8 J13 GND P3 PB22 V13 VDDIOP E12 VDDIOM J14 WKUP P5 GND V14 PA30 E13 BA0/A16 J15 DDP P6 GND V15 PB0 E14 PC8 J17 DDM P7 PA6 V16 GND E15 PC4 J18 VDDIOP P8 PA7 V17 PB4 E16 PC5 K2 GNDPLL P9 PA11 V18 GND E18 PC7 K3 GND P10 GND V19 PB6 E19 PC6 K5 NC P11 PA18 W1 PB25 F2 PC22 K6 GNDPLL P12 PA24 W2 PA0 F3 PC23 K7 VDDANA P13 PA28 W18 PB8 F5 PC20 K8 GND P14 PB3 W19 PB15 F6 D4 K9 GND P15 PB5 DS60001516A-page 14  2017 Microchip Technology Inc. SAM9G20 4. Power Considerations 4.1 Power Supplies The SAM9G20 has several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have separate grounds. See Table 4-1. Table 4-1: SAM9G20 Power Supply Pins Pin(s) Item(s) powered Range Nominal VDDCORE Core, including the processor Embedded memories Peripherals 0.9–1.1 V 1.0V 1.65–1.95 V 1.8V VDDIOM External Bus Interface I/O lines 3.0–3.6 V 3.3V 1.65–3.6 V – 1.65–1.95 V 1.8V 3.0–3.6 V 3.3V VDDOSC Main Oscillator cells VDDIOP Peripherals I/O lines Ground GND VDDBU Slow Clock oscillator Internal RC oscillator Part of the System Controller 0.9–1.1 V 1.0V GNDBU VDDPLL PLL cells 0.9–1.1 V 1.0V GNDPLL VDDUSB USB transceiver 3.0–3.6 V 3.3V GNDUSB VDDANA Analog-to-Digital Converter 3.0–3.6 V 3.3V GNDANA 4.2 Programmable I/O Lines The power supply pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The maximum speed is 133 MHz on the pin SDCK (SDRAM Clock) loaded with 10 pF. The other signals (control, address and data signals) do not go over 66 MHz, loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The EBI I/Os accept two slew rate modes, Fast and Slow. This allows to adapt the rising and falling time on SDRAM clock, control and data to the bus load. The voltage ranges and the slew rates are determined by programming VDDIOMSEL and IOSR bits in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock mode. At reset, the selected slew rates defaults are Fast. 4.3 Power Sequence Requirements The SAM9G20 board design must comply with the power-up and power-down sequence guidelines described in the following sections to guarantee reliable operation of the device. Any deviation from these sequences may lead to the following situations: • Excessive current consumption during the power-up phase which, in the worst case, can result in irreversible damage to the device. • Prevent the device from booting. 4.3.1 Power-up Sequence The power sequence described below is applicable to all the SAM9G20 revisions. However, the power sequence can be simplified for the revision B device. In this revision, the over consumption during the power-up phase has been limited to less than 200 mA. This current can not damage the device and if it is acceptable for the final application, the power sequence becomes VDDIO followed by VDDCORE. VDDIO must be established first (> 0.7V) to ensure a correct sampling of the BMS signal and also to guarantee the correct voltage level when accessing an external memory.  2017 Microchip Technology Inc. DS60001516A-page 15 SAM9G20 Figure 4-1: VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > VOH VOH(2.6V) VDDCORE VDDCOREtyp 0.7V VT+ (0.5V) t < t2 >< t3 > Core Supply POR output SLCK VDDCORE and VDDBU are controlled by Power-on-Reset (POR) to guarantee that these power sources reach their target values prior to the release of POR. (See Figure 4-1.) • VDDIOM and VDDIOP must NOT be powered until VDDCORE has reached a level superior or equal to VT+ (0.5V). • VDDIOP must be ≥ VIH (refer to Table 40-2 ”DC Characteristics” for more details), (tRST + t1) at the latest, after VDDCORE has reached VT+. • VDDIOM must reach VOH (refer to Table 40-2 ”DC Characteristics” for more details), (tRST + t1 + t2) at the latest, after VDDCORE has reached VT+. • t2 = tRST = 30 µs • t3 = 3 × tSLCK • t4 = 14 × tSLCK The tSLCK min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz). This gives: • • • t2 = tRST = 30 µs t3 = 66 µs t4 = 308 µs Figure 4-2 shows an example of the implementation on the evaluation kit AT91SAM9G20-EK Rev.C. DS60001516A-page 16  2017 Microchip Technology Inc. SAM9G20 Figure 4-2: Power-up Sequence Implementation Example on AT91SAM9G20-EK Rev.C 10 SQUARE CM COPPER AREA FOR HEAT SINKING WITH NO SOLDER MASK R168 MN1 LT1963AEQ-3.3 J1 5V C2 10μF 10V 2 R3 100K 1 2 + 3 C1 330μF CR1 5V NOT POPULATED 3V3 CURRENT MEASURE 6 GND VIN VOUT SD GND FB 1 3 5 3V3 IRLML6402 J2 Q3 3 2 4 C3 10μF C4 10μF 1 REGULATED 5V ONLY R163 10K 5V R161 82K R164 1K 8 MN15B 7 5 + 6 Q2 6 Si1563EDH 5 4 5V LM293 4 R162 15K C147 100NF J3 FORCE POWER ON 1 C14 15PF 2 3 R9 10K R10 10K R169 NOT POPULATED C5 1μF C6 1μF SHDN 8 5V C1M 5 5V 6 3 4 C1P C2M VIN 1V0 C11 R7 22μF 30K C2P VOUT 7 C12 10PF 5V R167 10K R165 15K TPS60500 1 2 - 3 + R166 10K C15 4.7μF MN15A 1 EN MN3 GND FB 10 PG 2 R11 120K 9 LM293 D1 MMSD4148 4.3.2 Power-down Sequence Switch off the VDDIOM and VDDIOP power supplies prior to, or at the same time, as VDDCORE. No power-up or power-down restrictions apply to VDDBU, VDDPL, VDDANA and VDDUSB.  2017 Microchip Technology Inc. DS60001516A-page 17 SAM9G20 5. I/O Line Considerations 5.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 5.3 “Reset Pins”. All the JTAG signals are supplied with VDDIOP. 5.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 5.3 Reset Pins NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 kΩ minimum to VDDIOP. The NRST signal is inserted in the Boundary Scan. 5.4 PIO Controllers All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers integrate a programmable pull-up resistor of 75 kΩ typical with the exception of P4–P31. For details, refer to Section 40. “Electrical Characteristics”. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. 5.5 I/O Line Drive Levels The PIO lines drive current capability is described in Section 40.2 “DC Characteristics”. 5.6 Shutdown Logic Pins The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1 MΩ.. The resistor value is calculated according to the regulator enable implementation and the SHDN level. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. DS60001516A-page 18  2017 Microchip Technology Inc. SAM9G20 6. Processor and Architecture 6.1 Arm926EJ-S Processor • RISC Processor Based on Arm v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets - Arm High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set • DSP Instruction Extensions • 5-Stage Pipeline Architecture: - Instruction Fetch (F) - Instruction Decode (D) - Execute (E) - Data Memory (M) - Register Write (W) • 32-Kbyte Data Cache, 32-Kbyte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement • Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain • Standard Arm v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains • Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete Matrix system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) 6.2 Bus Matrix • 6-layer Matrix, handling requests from 6 masters • Programmable Arbitration strategy - Fixed-priority Arbitration - Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master • Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support • One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap • Boot Mode Select - Non-volatile Boot Memory can be internal or external - Selection is made by BMS pin sampled at reset • Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory • Allows Handling of Dynamic Exception Vectors  2017 Microchip Technology Inc. DS60001516A-page 19 SAM9G20 6.2.1 Matrix Masters The Bus Matrix of the SAM9G20 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 6-1: List of Bus Matrix Masters Master 0 Arm926™ Instruction Master 1 Arm926 Data Master 2 PDC Master 3 ISI Controller Master 4 Ethernet MAC Master 5 USB Host DMA 6.2.2 Matrix Slaves Each Slave has its own arbiter, thus allowing to program a different arbitration per Slave. Table 6-2: List of Bus Matrix Slaves Slave 0 Internal SRAM0 16 Kbytes Slave 1 Internal SRAM1 16 Kbytes Internal ROM Slave 2 USB Host User Interface Slave 3 External Bus Interface Slave 4 Internal Peripherals 6.2.3 Masters to Slaves Access All the Masters can normally access all the Slaves. However, some paths do not make sense, like as example allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown “–” in Table 6-3. Table 6-3: SAM9G20 Masters to Slaves Access Master Slave 0&1 2 3 4 5 Arm926 Instruction & Data Peripheral DMA Controller ISI Controller Ethernet MAC USB Host Controller 0 Internal SRAM 16 Kbytes X X X X X 1 Internal SRAM 16 Kbytes X X X X X Internal ROM X X – – – UHP User Interface X X – – – 3 External Bus Interface X X X X X 4 Internal Peripherals X X – – – 2 DS60001516A-page 20  2017 Microchip Technology Inc. SAM9G20 6.3 • • • • Peripheral DMA Controller Acting as one Matrix Master Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. Next Pointer Support, forbids strong real-time constraints on buffer management. Twenty-four channels - Two for each USART - Two for the Debug Unit - Two for the Serial Synchronous Controller - Two for each Serial Peripheral Interface - One for Multimedia Card Interface - One for Analog-to-Digital Converter - Two for the Two-wire Interface The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): - 6.4 TWI Transmit Channel DBGU Transmit Channel USART5 Transmit Channel USART4 Transmit Channel USART3 Transmit Channel USART2 Transmit Channel USART1 Transmit Channel USART0 Transmit Channel SPI1 Transmit Channel SPI0 Transmit Channel SSC Transmit Channel TWI Receive Channel DBGU Receive Channel USART5 Receive Channel USART4 Receive Channel USART3 Receive Channel USART2 Receive Channel USART1 Receive Channel USART0 Receive Channel ADC Receive Channel SPI1 Receive Channel SPI0 Receive Channel SSC Receive Channel MCI Transmit/Receive Channel Debug and Test Features • Arm926 Real-time In-circuit Emulator - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel • Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins  2017 Microchip Technology Inc. DS60001516A-page 21 SAM9G20 7. Memories Figure 7-1: SAM9G20 Memory Mapping Internal Memory Mapping Address Memory Space 0x0000 0000 Notes : (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP 0x0000 0000 Boot Memory (1) Internal Memories 256 Mbytes Reserved 256 Mbytes 0x1FFF FFFF 0x2000 0000 0x3FFF FFFF 0x4000 0000 0x4FFF FFFF 0x5000 0000 0x5FFF FFFF 0x6000 0000 0x6FFF FFFF 0x7000 0000 32 Kbytes 0x10 8000 EBI Chip Select 0 0x2FFF FFFF 0x3000 0000 0x10 0000 ROM 0x0FFF FFFF 0x1000 0000 0x20 0000 SRAM0 16 Kbytes 0x20 4000 Reserved EBI Chip Select 1/ SDRAMC 256 Mbytes 0x30 0000 SRAM1 16 Kbytes 0x30 4000 Reserved 0x50 0000 EBI Chip Select 2 256 Mbytes 0x50 4000 EBI Chip Select 3/ NANDFlash 256 Mbytes 0x0FFF FFFF EBI Chip Select 4/ Compact Flash Slot 0 256 Mbytes EBI Chip Select 5/ Compact Flash Slot 1 256 Mbytes UHP 16 Kbytes Reserved Peripheral Mapping 0xF000 0000 System Controller Mapping Reserved 0xFFFA 0000 EBI Chip Select 6 256 Mbytes 0x7FFF FFFF 0x8000 0000 TCO, TC1, TC2 16 Kbytes 0xFFFF C000 UDP 16 Kbytes 0xFFFF E800 MCI 16 Kbytes 0xFFFF EA00 TWI 16 Kbytes Reserved 0xFFFA 4000 0xFFFA 8000 EBI Chip Select 7 256 Mbytes 0xFFFA C000 0x8FFF FFFF 0x9000 0000 ECC 512 bytes SDRAMC 512 bytes SMC 512 bytes MATRIX 512 bytes 0xFFFF EC00 0xFFFB 0000 USART0 16 Kbytes 0xFFFB 4000 0xFFFF EE00 USART1 16 Kbytes 0xFFFB 8000 USART2 16 Kbytes SSC 16 Kbytes ISI 16 Kbytes EMAC 16 Kbytes 0xFFFF F000 0xFFFB C000 AIC 512 bytes 0xFFFF F200 0xFFFC 0000 0xFFFC 4000 1,518 Mbytes SPI0 16 Kbytes 0xFFFC C000 SPI1 16 Kbytes USART3 PIOB 16 Kbytes 0xFFFD 8000 USART5 0xFFFF FC00 16 Kbytes 0xFFFF FD00 16 Kbytes ADC 16 Kbytes 256 bytes 16 bytes SHDWC 0xFFFF FD20 16 bytes 0xFFFF FD30 RTT 16 bytes PIT 16 bytes WDT 16 bytes GPBR 16 bytes 0xFFFF FD40 0xFFFE 4000 0xFFFF FD50 0xFFFF FD60 Reserved DS60001516A-page 22 PMC RSTC 0xFFFF FD10 TC3, TC4, TC5 0xFFFE 0000 0xFFFF C000 SYSC 0xFFFF FFFF 512 bytes 0xFFFF FA00 16 Kbytes 0xFFFD C000 0xFFFF FFFF 512 bytes Reserved USART4 256 Mbytes 512 bytes 0xFFFF F800 0xFFFD 4000 Internal Peripherals PIOA PIOC 0xFFFD 0000 0xEFFF FFFF 0xF000 0000 512 bytes 0xFFFF F600 0xFFFC 8000 Undefined (Abort) DBGU 0xFFFF F400 16 Kbytes Reserved 0xFFFF FFFF  2017 Microchip Technology Inc. SAM9G20 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (Arm926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 7-1 ”Internal Memory Mapping” for details. 7.1 Embedded Memories • 64 Kbyte ROM - Single Cycle Access at full matrix speed • Two 16 Kbyte Fast SRAM - Single Cycle Access at full matrix speed 7.1.1 Boot Strategies Table 7-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Table 7-1: Internal Memory Mapping REMAP = 0 Address BMS = 1 BMS = 0 REMAP = 1 0x0000 0000 ROM EBI_NCS0 SRAM0 16 KB 0x0010 0000 ROM 0x0020 0000 SRAM0 16 KB 0x0030 0000 SRAM1 16 KB 0x0050 0000 USB Host User Interface The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. When REMAP = 1, BMS is ignored. Refer to Section 18. “SAM9G20 Bus Matrix” for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 7-1. The SAM9G20 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 7.1.1.1 BMS = 1, Boot on Embedded ROM The system boots using the Boot Program. • • • • Boot on slow clock (On-chip RC or 32768 Hz) Auto baudrate detection Downloads and runs an application from external storage media into internal SRAM Downloaded code size depends on embedded SRAM size  2017 Microchip Technology Inc. DS60001516A-page 23 SAM9G20 • Automatic detection of valid application • Bootloader on a non-volatile memory - SDCard (boot ROM does not support high capacity SDCards.) - NAND Flash - SPI DataFlash and Serial Flash connected on NPCS0 and NPCS1 of the SPI0 - EEPROM on TWI • SAM-BA® Boot in case no valid program is detected in external NVM, supporting - Serial communication on a DBGU - USB Device HS Port 7.1.1.2 BMS = 0, Boot on External Memory • Boot on slow clock (On-chip RC or 32768 Hz) • Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS = 0), the user must take the following steps: 1. 2. 3. 4. Program the PMC (main oscillator enable or bypass mode). Program and start the PLL. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock. Switch the main clock to the new value. 7.2 External Memories The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256-Mbyte memory area assigned. Refer to the memory map in Figure 7-1. 7.2.1 External Bus Interface • Integrates three External Memory Controllers - Static Memory Controller - SDRAM Controller - ECC Controller • Additional logic for NAND Flash • Full 32-bit External Data Bus • Up to 26-bit Address Bus (up to 64 Mbytes linear) • Up to 8 chip selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash support - Static Memory Controller on NCS4–NCS5, Optional CompactFlash support - Static Memory Controller on NCS6–NCS7 7.2.2 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability - Compliant with LCD Module - Control signals programmable setup, pulse and hold time for each Memory Bank DS60001516A-page 24  2017 Microchip Technology Inc. SAM9G20 • Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time • Slow Clock mode supported 7.2.3 SDRAM Controller • Supported devices - Standard and Low-power SDRAM (Mobile SDRAM) • Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Datapath • Programming facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Multibank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities - Self-refresh, power down and deep power down modes supported • Error detection - Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency of 1, 2 and 3 supported • Auto Precharge Command not used 7.2.4 Error Correction Code Controller • Hardware Error Correction Code (ECC) Generation - Detection and Correction by Software • Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path. • Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software • Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data Path • Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path • Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path  2017 Microchip Technology Inc. DS60001516A-page 25 SAM9G20 8. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing to configure the Matrix and a set of registers for the chip configuration. The chip configuration registers allows configuring: - EBI chip select assignment and Voltage range for external memories The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF E800 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard Arm instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 8-1 shows the System Controller block diagram. Figure 7-1 shows the mapping of the User Interfaces of the System Controller peripherals. DS60001516A-page 26  2017 Microchip Technology Inc. SAM9G20 8.1 System Controller Block Diagram Figure 8-1: SAM9G20 System Controller Block Diagram System Controller VDDCORE Powered nirq nfiq irq0–irq2 fiq periph_irq[2..24] Advanced Interrupt Controller pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq int MCK periph_nreset dbgu_irq Debug Unit dbgu_rxd dbgu_txd Arm926EJ-S proc_nreset PCK debug MCK debug periph_nreset Periodic Interval Timer pit_irq Watchdog Timer wdt_irq jtag_nreset SLCK debug idle proc_nreset Boundary Scan TAP Controller MCK wdt_fault WDRPROC NRST periph_nreset Bus Matrix rstc_irq por_ntrst jtag_nreset VDDCORE POR periph_nreset proc_nreset Reset Controller backup_nreset VDDBU VDDBU POR VDDBU Powered UHPCK periph_clk[20] periph_nreset USB Host Port periph_irq[20] SLCK SLCK backup_nreset Real-time Timer rtt_irq rtt_alarm UDPCK SLCK SHDN periph_clk[10] WKUP RC Oscillator OSCSEL XIN32 ntrst por_ntrst backup_nreset Shutdown Controller Four 32-bit General-Purpose Backup Registers Slow Clock Oscillator SLCK XOUT periph_clk[2..27] pck[0–1] int Main Oscillator MAINCK PLLA PLLACK PLLB PLLBCK USB Device Port periph_irq[10] rtt0_alarm XOUT32 XIN periph_nreset PCK UDPCK Power Management Controller UHPCK MCK pmc_irq periph_nreset periph_clk[6..24] idle periph_nreset periph_nreset periph_clk[2..4] dbgu_rxd PA0–PA31 PB0–PB31 PC0–PC31  2017 Microchip Technology Inc. PIO Controllers periph_irq[2..4] irq0–irq2 fiq dbgu_txd periph_irq[6..24] Embedded Peripherals in out enable DS60001516A-page 27 SAM9G20 8.2 Reset Controller • Based on two Power-on-Reset cells - one on VDDBU and one on VDDCORE • Status of the last reset - Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • Controls the internal resets and the NRST pin output - Allows shaping a reset signal for the external devices 8.3 Shutdown Controller • Shutdown and Wake-Up logic - Software programmable assertion of the SHDN pin - Deassertion Programmable on a WKUP pin level change or on alarm 8.4 Clock Generator • Embeds a Low power 32768 Hz Slow Clock Oscillator and a Low power RC oscillator selectable with OSCSEL signal - Provides the permanent Slow Clock SLCK to the system • Embeds the Main Oscillator - Oscillator bypass feature - Supports 3 to 20 MHz crystals • Embeds two PLLs - The PLL A outputs 400–800 MHz clock - The PLL B outputs 100 MHz clock - Both integrate an input divider to increase output accuracy - PLL A and PLL B embed their own filters Figure 8-2: Clock Generator Block Diagram Clock Generator OSCSEL On Chip RC OSC XIN32 Slow Clock SLCK Slow Clock Oscillator XOUT32 XIN Main Oscillator Main Clock MAINCK PLL and Divider A PLLA Clock PLLACK PLL and Divider B PLLB Clock PLLBCK XOUT Status Control Power Management Controller DS60001516A-page 28  2017 Microchip Technology Inc. SAM9G20 8.5 Power Management Controller • Provides: - the Processor Clock PCK - the Master Clock MCK, in particular to the Matrix and the memory interfaces.The MCK divider can be 1,2,4,6 - the USB Device Clock UDPCK - independent peripheral clocks, typically at the frequency of MCK - 2 programmable clock outputs: PCK0, PCK1 • Five flexible operating modes: - Normal Mode, processor and peripherals running at a programmable frequency - Idle Mode, processor stopped waiting for an interrupt - Slow Clock Mode, processor and peripherals running at low frequency - Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt - Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 8-3: SAM9G20 Power Management Controller Block Diagram Processor Clock Controller Divider /1,/2 PCK int Idle Mode Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,.../64 Divider /1,/2,/4,/6 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] USB Clock Controller PLLBCK 8.6 Divider /1,/2,/4 ON/OFF UDPCK Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux®/Windows CE® compliant tick generator 8.7 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • Windowed, prevents the processor being in a dead-lock on the watchdog access  2017 Microchip Technology Inc. DS60001516A-page 29 SAM9G20 8.8 Real-time Timer • Real-time Timer 32-bit free-running back-up Counter • Integrates a 16-bit programmable prescaler running on slow clock • Alarm Register capable of generating a wake-up of the system through the Shutdown Controller 8.9 General-purpose Backup Registers • Four 32-bit general-purpose backup registers 8.10 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the Arm Processor • Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive • Three External Sources plus the Fast Interrupt signal • 8-level Priority Controller - Drives the Normal Interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt • Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode - Easy debugging by preventing automatic operations when protect models are enabled • Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 8.11 Debug Unit • Composed of two functions: - Two-pin UART - Debug Communication Channel (DCC) support • Two-pin UART - Implemented features are 100% compatible with the standard Microchip USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support - Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the Arm Processor’s ICE Interface 8.12 Chip Identification • Chip ID:0x019905A1 • JTAG ID: 0x05B2403F • Arm926 TAP ID:0x0792603F DS60001516A-page 30  2017 Microchip Technology Inc. SAM9G20 9. Peripherals 9.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 7-1. 9.2 Peripheral Identifiers Table 9-1 defines the Peripheral Identifiers of the SAM9G20. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 9-1: Peripheral Identifiers Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 0 AIC Advanced Interrupt Controller FIQ 1 SYSC System Controller Interrupt – 2 PIOA Parallel I/O Controller A – 3 PIOB Parallel I/O Controller B – 4 PIOC Parallel I/O Controller C – 5 ADC Analog to Digital Converter – 6 US0 USART 0 – 7 US1 USART 1 – 8 US2 USART 2 – 9 MCI Multimedia Card Interface – 10 UDP USB Device Port – 11 TWI Two-wire Interface – 12 SPI0 Serial Peripheral Interface 0 – 13 SPI1 Serial Peripheral Interface 1 – 14 SSC Synchronous Serial Controller – 15 – Reserved – 16 – Reserved – 17 TC0 Timer/Counter 0 – 18 TC1 Timer/Counter 1 – 19 TC2 Timer/Counter 2 – 20 UHP USB Host Port – 21 EMAC Ethernet MAC – 22 ISI Image Sensor Interface – 23 US3 USART 3 – 24 US4 USART 4 – 25 US5 USART 5 – 26 TC3 Timer/Counter 3 – 27 TC4 Timer/Counter 4 – 28 TC5 Timer/Counter 5 –  2017 Microchip Technology Inc. DS60001516A-page 31 SAM9G20 Table 9-1: Peripheral Identifiers (Continued) Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 29 AIC Advanced Interrupt Controller IRQ0 30 AIC Advanced Interrupt Controller IRQ1 31 AIC Advanced Interrupt Controller IRQ2 Note: 9.2.1 9.2.1.1 Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion. Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • • • • • • • the SDRAM Controller the Debug Unit the Periodic Interval Timer the Real-time Timer the Watchdog Timer the Reset Controller the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 9.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 9.3 Peripheral Signal Multiplexing on I/O Lines The SAM9G20 features three PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Table 9-2, Table 9-3 and Table 9-4 define how the I/O lines of the peripherals A and B are multiplexed on the PIO controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only might be duplicated within both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O appears, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the PIO Controller PIO Status Register (PIO_PSR) resets low. If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. DS60001516A-page 32  2017 Microchip Technology Inc. SAM9G20 9.3.1 Table 9-2: PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A Peripheral B PA0 SPI0_MISO PA1 Application Usage Reset State Power Supply Function MCDB0 I/O VDDIOP – SPI0_MOSI MCCDB I/O VDDIOP – PA2 SPI0_SPCK – I/O VDDIOP – PA3 SPI0_NPCS0 MCDB3 I/O VDDIOP – PA4 RTS2 MCDB2 I/O VDDIOP – PA5 CTS2 MCDB1 I/O VDDIOP – PA6 MCDA0 – I/O VDDIOP – PA7 MCCDA – I/O VDDIOP – PA8 MCCK – I/O VDDIOP – PA9 MCDA1 – I/O VDDIOP – PA10 MCDA2 ETX2 I/O VDDIOP – PA11 MCDA3 ETX3 I/O VDDIOP – PA12 ETX0 – I/O VDDIOP – PA13 ETX1 – I/O VDDIOP – PA14 ERX0 – I/O VDDIOP – PA15 ERX1 – I/O VDDIOP – PA16 ETXEN – I/O VDDIOP – PA17 ERXDV – I/O VDDIOP – PA18 ERXER – I/O VDDIOP – PA19 ETXCK – I/O VDDIOP – PA20 EMDC – I/O VDDIOP – PA21 EMDIO – I/O VDDIOP – PA22 ADTRG ETXER I/O VDDIOP – PA23 TWD ETX2 I/O VDDIOP – PA24 TWCK ETX3 I/O VDDIOP – PA25 TCLK0 ERX2 I/O VDDIOP – PA26 TIOA0 ERX3 I/O VDDIOP – PA27 TIOA1 ERXCK I/O VDDIOP – PA28 TIOA2 ECRS I/O VDDIOP – PA29 SCK1 ECOL I/O VDDIOP – PA30 SCK2 RXD4 I/O VDDIOP – PA31 SCK0 TXD4 I/O VDDIOP –  2017 Microchip Technology Inc. Comments Comments DS60001516A-page 33 SAM9G20 9.3.2 PIO Controller B Multiplexing Table 9-3: Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 SPI1_MISO PB1 Application Usage Reset State Power Supply Function TIOA3 I/O VDDIOP – SPI1_MOSI TIOB3 I/O VDDIOP – PB2 SPI1_SPCK TIOA4 I/O VDDIOP – PB3 SPI1_NPCS0 TIOA5 I/O VDDIOP – PB4 TXD0 – I/O VDDIOP – PB5 RXD0 – I/O VDDIOP – PB6 TXD1 TCLK1 I/O VDDIOP – PB7 RXD1 TCLK2 I/O VDDIOP – PB8 TXD2 – I/O VDDIOP – PB9 RXD2 – I/O VDDIOP – PB10 TXD3 ISI_D8 I/O VDDIOP – PB11 RXD3 ISI_D9 I/O VDDIOP – PB12 TXD5 ISI_D10 I/O VDDIOP – PB13 RXD5 ISI_D11 I/O VDDIOP – PB14 DRXD – I/O VDDIOP – PB15 DTXD – I/O VDDIOP – PB16 TK0 TCLK3 I/O VDDIOP – PB17 TF0 TCLK4 I/O VDDIOP – PB18 TD0 TIOB4 I/O VDDIOP – PB19 RD0 TIOB5 I/O VDDIOP – PB20 RK0 ISI_D0 I/O VDDIOP – PB21 RF0 ISI_D1 I/O VDDIOP – PB22 DSR0 ISI_D2 I/O VDDIOP – PB23 DCD0 ISI_D3 I/O VDDIOP – PB24 DTR0 ISI_D4 I/O VDDIOP – PB25 RI0 ISI_D5 I/O VDDIOP – PB26 RTS0 ISI_D6 I/O VDDIOP – PB27 CTS0 ISI_D7 I/O VDDIOP – PB28 RTS1 ISI_PCK I/O VDDIOP – PB29 CTS1 ISI_VSYNC I/O VDDIOP – PB30 PCK0 ISI_HSYNC I/O VDDIOP – PB31 PCK1 ISI_MCK I/O VDDIOP – DS60001516A-page 34 Comments Comments  2017 Microchip Technology Inc. SAM9G20 9.3.3 PIO Controller C Multiplexing Table 9-4: Multiplexing on PIO Controller C PIO Controller C Application Usage I/O Line Peripheral A Peripheral B Comments Reset State Power Supply Function PC0 – SCK3 AD0 I/O VDDANA – PC1 – PCK0 AD1 I/O VDDANA – PC2 – PCK1 AD2 I/O VDDANA – PC3 – SPI1_NPCS3 AD3 I/O VDDANA – PC4 A23 SPI1_NPCS2 A23 VDDIOM – PC5 A24 SPI1_NPCS1 A24 VDDIOM – PC6 TIOB2 CFCE1 I/O VDDIOM – PC7 TIOB1 CFCE2 I/O VDDIOM – PC8 NCS4/CFCS0 RTS3 I/O VDDIOM – PC9 NCS5/CFCS1 TIOB0 I/O VDDIOM – PC10 A25/CFRNW CTS3 A25 VDDIOM – PC11 NCS2 SPI0_NPCS1 I/O VDDIOM – PC12 IRQ0 NCS7 I/O VDDIOM – PC13 FIQ NCS6 I/O VDDIOM – PC14 NCS3/NANDCS IRQ2 I/O VDDIOM – PC15 NWAIT IRQ1 I/O VDDIOM – PC16 D16 SPI0_NPCS2 I/O VDDIOM – PC17 D17 SPI0_NPCS3 I/O VDDIOM – PC18 D18 SPI1_NPCS1 I/O VDDIOM – PC19 D19 SPI1_NPCS2 I/O VDDIOM – PC20 D20 SPI1_NPCS3 I/O VDDIOM – PC21 D21 – I/O VDDIOM – PC22 D22 TCLK5 I/O VDDIOM – PC23 D23 – I/O VDDIOM – PC24 D24 – I/O VDDIOM – PC25 D25 – I/O VDDIOM – PC26 D26 – I/O VDDIOM – PC27 D27 – I/O VDDIOM – PC28 D28 – I/O VDDIOM – PC29 D29 – I/O VDDIOM – PC30 D30 – I/O VDDIOM – PC31 D31 – I/O VDDIOM –  2017 Microchip Technology Inc. Comments DS60001516A-page 35 SAM9G20 9.4 9.4.1 Embedded Peripherals Serial Peripheral Interface • Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors • Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection • Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device 9.4.2 • • • • • • • • • Two-wire Interface Compatibility with standard two-wire serial memory One, two or three bytes for slave address Sequential read/write operations Supports either master or slave modes Compatible with standard two-wire serial memories Master, multi-master and slave mode operation Bit rate: up to 400 Kbits General Call supported in slave mode Connection to Peripheral DMA Controller (PDC) capabilities optimizes data transfers in master mode only - One channel for the receiver, one channel for the transmitter - Next buffer support 9.4.3 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Optional modem signal management DTR-DSR-DCD-RI - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation - Communication at up to 115.2 Kbps • Test Modes - Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the SAM9G20, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. DS60001516A-page 36  2017 Microchip Technology Inc. SAM9G20 The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features. Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 9.4.4 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 9.4.5 Timer Counter • Two blocks of three 16-bit Timer Counter channels • Each channel can be individually programmed to perform a wide range of functions including: - Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities • Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals • Each block contains two global registers that act on all three TC Channels Note: 9.4.6 TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See Figure 7-1 for TC Block 0 and TC Block 1 base addresses. Multimedia Card Interface • • • • • • • One double-channel MultiMedia Card Interface Compatibility with MultiMedia Card Specification Version 3.11 Compatibility with SD Memory Card Specification Version 1.1 Compatibility with SDIO Specification Version V1.0. Card clock rate up to Master Clock divided by 2 Embedded power management to slow down clock rate when not used MCI has two slots, each supporting - One slot for one MultiMediaCard bus (up to 30 cards) or - One SD Memory Card • Support for stream, block and multi-block data read and write 9.4.7 • • • • • • • USB Host Port Compliance with Open HCI Rev 1.0 Specification Compliance with USB V2.0 Full-speed and Low-speed Specification Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices Root hub integrated with two downstream USB ports in the 217-LFBGA package Two embedded USB transceivers Supports power management Operates as a master on the Matrix  2017 Microchip Technology Inc. DS60001516A-page 37 SAM9G20 9.4.8 USB Device Port • • • • • • USB V2.0 full-speed compliant, 12 MBits per second Embedded USB V2.0 full-speed transceiver Embedded 2,432-byte dual-port RAM for endpoints Suspend/Resume logic Ping-pong mode (two memory banks) for isochronous and bulk endpoints Six general-purpose endpoints - Endpoint 0 and 3: 64 bytes, no ping-pong mode - Endpoint 1 and 2: 64 bytes, ping-pong mode - Endpoint 4 and 5: 512 bytes, ping-pong mode • Embedded pad pull-up 9.4.9 • • • • • • • • • • • • Compatibility with IEEE Standard 802.3 10 and 100 MBits per second data throughput capability Full- and half-duplex operations MII or RMII interface to the physical layer Register Interface to address, data, status and control registers DMA Interface, operating as a master on the Memory Controller Interrupt generation to signal receive and transmit completion 28-byte transmit and 28-byte receive FIFOs Automatic pad and CRC generation on transmitted frames Address checking logic to recognize four 48-bit addresses Supports promiscuous mode where all valid frames are copied to memory Supports physical layer management through MDIO interface 9.4.10 • • • • • • • Ethernet MAC 10/100 Image Sensor Interface ITU-R BT. 601/656 8-bit mode external interface support Support for ITU-R BT.656-4 SAV and EAV synchronization Vertical and horizontal resolutions up to 2048 x 2048 Preview Path up to 640 x 480 in RGMB mode, 2048 x2048 in grayscale mode Support for packed data formatting for YCbCr 4:2:2 formats Preview scaler to generate smaller size image Programmable frame capture rate 9.4.11 Analog-to-Digital Converter • • • • • • • 4-channel ADC 10-bit 312K samples/sec. Successive Approximation Register ADC -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity Individual enable and disable of each channel External voltage reference for better accuracy on low voltage inputs Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals DS60001516A-page 38  2017 Microchip Technology Inc. SAM9G20 10. Arm926EJ-S Processor Overview 10.1 Overview The Arm926EJ-S processor is a member of the Arm9™ family of general-purpose microprocessors. The Arm926EJ-S implements Arm architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The Arm926EJ-S processor supports the 32-bit Arm and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The Arm926EJ-S processor supports the Arm debug architecture and includes logic to assist in both hardware and software debug. The Arm926EJ-S provides a complete high performance processor subsystem, including: • • • • an Arm9EJ-S integer core a Memory Management Unit (MMU) separate instruction and data AMBA AHB bus interfaces separate instruction and data TCM interfaces  2017 Microchip Technology Inc. DS60001516A-page 39 SAM9G20 10.2 Block Diagram Figure 10-1: Arm926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor External Coprocessors ETM9 External Coprocessor Interface Trace Port Interface Write Data Arm9EJ-S Processor Core Instruction Fetches Read Data Data Address Instruction Address MMU DTCM Interface Data TLB Instruction TLB ITCM Interface Data TCM Instruction TCM Instruction Address Data Address Data Cache AHB Interface and Write Buffer Instruction Cache AMBA AHB DS60001516A-page 40  2017 Microchip Technology Inc. SAM9G20 10.3 10.3.1 Arm9EJ-S Processor Arm9EJ-S Operating States The Arm9EJ-S processor can operate in three different states, each with a specific instruction set: • Arm state: 32-bit, word-aligned Arm instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 10.3.2 Switching State The operating state of the Arm9EJ-S core can be switched between: • Arm state and THUMB state using the BX and BLX instructions, and loads to the PC • Arm state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in Arm state. If an exception occurs in Thumb or Jazelle states, the processor reverts to Arm state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 10.3.3 Instruction Pipelines The Arm9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for Arm and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 10.3.4 Memory Access The Arm9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, halfwords must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The Arm9EJ-S control logic automatically detects these cases and stalls the core or forward data. 10.3.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on Arm processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of Arm9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing Arm or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in Arm9EJ-S decodes 95% of executed byte codes and turns them into Arm instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of Arm instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing Arm registers are re-used in Jazelle state and all registers then have particular functions in this mode. Minimum interrupt latency is maintained across both Arm state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to Arm state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 10.3.6 Arm9EJ-S Operating Modes In all states, there are seven operation modes: • • • • • • • User mode is the usual Arm program execution state. It is used for executing most application programs Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process Interrupt (IRQ) mode is used for general-purpose interrupt handling Supervisor mode is a protected mode for the operating system Abort mode is entered after a data or instruction prefetch abort System mode is a privileged user mode for the operating system Undefined mode is entered when an undefined instruction exception occurs  2017 Microchip Technology Inc. DS60001516A-page 41 SAM9G20 Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 10.3.7 Arm9EJ-S Registers The Arm9EJ-S core has a total of 37 registers: • 31 general-purpose 32-bit registers • Six 32-bit status registers Table 10-1 shows all the registers in all modes. Table 10-1: Arm9TDMI Modes and Registers Layout User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ Mode-specific banked registers The Arm state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. DS60001516A-page 42  2017 Microchip Technology Inc. SAM9G20 In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey Arm Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return For more details, refer to Arm Software Development Kit. The Thumb state register set is a subset of the Arm state set. The programmer has direct access to: • • • • • Eight general-purpose registers r0–r7 Stack pointer, SP Link register, LR (Arm r14) PC CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the Arm9EJ-S Technical Reference Manual, revision r1p2 page 2-12). 10.3.7.1 Status Registers The Arm9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode Figure 10-2: Status Register Format 31 30 29 28 27 24 N Z C V Q J 7 6 5 Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than I F T 0 Mode Mode bits Thumb state bit FIQ disable IRQ disable Figure 10-2 shows the status register format, where: • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. • The J bit in the CPSR indicates when the Arm9EJ-S core is in Jazelle state, where: - J = 0: The processor is in Arm or Thumb state, depending on the T bit - J = 1: The processor is in Jazelle state. • Mode: five bits to encode the current processor mode 10.3.7.2 Exceptions Exception Types and Priorities The Arm9EJ-S supports five types of exceptions. Each type drives the Arm9EJ-S in a privileged mode. The types of exceptions are: • • • • • Fast interrupt (FIQ) Normal interrupt (IRQ) Data and Prefetched aborts (Abort) Undefined instruction (Undefined) Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.  2017 Microchip Technology Inc. DS60001516A-page 43 SAM9G20 More than one exception can happen at a time, therefore the Arm9EJ-S takes the arisen exceptions according to the following priority order: • • • • • • Reset (highest priority) Data Abort FIQ IRQ Prefetch Abort BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the Arm9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an Arm exception, the Arm9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: - Arm and Jazelle states, the Arm9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). - THUMB state, the Arm9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The Arm9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the Arm9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of Arm9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the Arm9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 10.3.8 Arm Instruction Set Overview The Arm instruction set is divided into: • • • • • • Branch instructions Data processing instructions Status register transfer instructions Load and Store instructions Coprocessor instructions Exception-generating instructions Arm instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the Arm Technical Reference Manual, Arm ref. DDI0198B. DS60001516A-page 44  2017 Microchip Technology Inc. SAM9G20 Table 10-2 gives the Arm instruction mnemonic list. Table 10-2: Mnemonic Arm Instruction Mnemonic List Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry RSB Reverse Subtract RSC Reverse Subtract with Carry CMP Compare CMN Compare Negated TST Test TEQ Test Equivalence AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR MUL Multiply MLA Multiply Accumulate SMULL Sign Long Multiply UMULL Unsigned Long Multiply SMLAL Signed Long Multiply Accumulate UMLAL Unsigned Long Multiply Accumulate MSR B BX LDR Move to Status Register Branch MRS BL Move From Status Register Branch and Link Branch and Exchange SWI Software Interrupt Load Word STR Store Word LDRSH Load Signed Halfword LDRSB Load Signed Byte LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRBT Load Register Byte with Translation STRBT Store Register Byte with Translation LDRT Load Register with Translation STRT Store Register with Translation LDM Load Multiple STM Store Multiple SWP Swap Word MCR Move To Coprocessor MRC Move From Coprocessor LDC Load To Coprocessor STC Store From Coprocessor CDP Coprocessor Data Processing  2017 Microchip Technology Inc. SWPB Swap Byte DS60001516A-page 45 SAM9G20 10.3.9 New Arm Instruction Set Table 10-3: Mnemonic BXJ New Arm Instruction Mnemonic List Operation Mnemonic Operation Branch and exchange to Java MRRC Move double from coprocessor BLX (1) Branch, Link and exchange MCR2 Alternative move of Arm reg to coprocessor SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint SMULxy Signed Multiply 16 * 16 bit PLD SMULWy Signed Multiply 32 * 16 bit STRD Store Double Saturated Add STC2 Alternative Store from Coprocessor Saturated Add with Double LDRD Load Double Saturated subtract LDC2 Alternative Load to Coprocessor QADD QDADD QSUB QDSUB Saturated Subtract with double Soft Preload, Memory prepare to load from address CLZ Count Leading Zeroes Note 1: A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 10.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the Arm instruction set. The Thumb instruction set is divided into: • • • • • Branch instructions Data processing instructions Load and Store instructions Load and Store multiple instructions Exception-generating instruction For further details, see the Arm Technical Reference Manual, Arm ref. DDI0198B. Table 10-4 gives the Thumb instruction mnemonic list. Table 10-4: Mnemonic Thumb Instruction Mnemonic List Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry CMP Compare CMN Compare Negated TST Test NEG Negate AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR LSL Logical Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right MUL Multiply BLX Branch, Link, and Exchange B Branch BL BX Branch and Exchange DS60001516A-page 46 SWI Branch and Link Software Interrupt  2017 Microchip Technology Inc. SAM9G20 Table 10-4: Thumb Instruction Mnemonic List (Continued) Mnemonic Operation Mnemonic Operation LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH Push Register to stack POP Pop Register from stack Conditional Branch BKPT Breakpoint BCC 10.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • • • • • Arm9EJ-S Caches (ICache, DCache and write buffer) TCM MMU Other system options To control these features, CP15 provides 16 additional registers. See Table 10-5. Table 10-5: Register 0 CP15 Registers Name Read/Write (1) Read/Unpredictable ID Code 0 Cache type (1) Read/Unpredictable 0 TCM status(1) Read/Unpredictable 1 Control Read/Write 2 Translation Table Base Read/Write 3 Domain Access Control Read/Write 4 Reserved None 5 Data fault Status (1) status(1) Read/Write 5 Instruction fault 6 Fault Address Read/Write 7 Cache Operations Read/Write 8 TLB operations Unpredictable/Write (2) Read/Write 9 cache lockdown Read/Write 9 TCM region Read/Write 10 TLB lockdown Read/Write 11 Reserved None 12 Reserved 13 None (1) FCSE PID  2017 Microchip Technology Inc. Read/Write DS60001516A-page 47 SAM9G20 Table 10-5: CP15 Registers (Continued) Register Name Read/Write (1) 13 Context ID Read/Write 14 Reserved None 15 Test configuration Read/Write Note 1: Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2: Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 10.4.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from Arm Register) instruction is used to write an Arm register to CP15. • MRC (Move to Arm Register from Coprocessor) instruction is used to read the value of CP15 to an Arm register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 cond 23 22 21 opcode_1 15 20 26 25 24 1 1 1 0 19 18 17 16 L 14 13 12 Rd 7 27 6 5 opcode_2 4 1 CRn 11 10 9 8 1 1 1 1 3 2 1 0 CRm CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. Rd[15:12]: Arm Register Defines the Arm register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. L: Instruction Bit 0: MCR instruction 1: MRC instruction opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. cond [31:28]: Condition For more details, see Chapter 2 in Arm926EJ-S TRM. DS60001516A-page 48  2017 Microchip Technology Inc. SAM9G20 10.5 Memory Management Unit (MMU) The Arm926EJ-S processor implements an enhanced Arm architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, twolevel page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 7 shows the different attributes of each page in the physical memory. Table 10-6: Mapping Details Mapping Name Mapping Size Access Permission By Subpage Size Section 1 Mbyte Section – Large Page 64 Kbytes 4 separated subpages 16 Kbytes Small Page 4 Kbytes 4 separated subpages 1 Kbyte Tiny Page 1 Kbyte Tiny Page – The MMU consists of: • Access control logic • Translation Look-aside Buffer (TLB) • Translation table walk hardware 10.5.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 10.5.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 10.5.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access.  2017 Microchip Technology Inc. DS60001516A-page 49 SAM9G20 There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, refer to chapter 3 in Arm926EJ-S Technical Reference Manual. 10.5.4 MMU Faults The MMU generates an abort on the following types of faults: • • • • Alignment faults (for data accesses only) Translation faults Domain faults Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, refer to chapter 3 in Arm926EJ-S Technical Reference Manual. 10.6 Caches and Write Buffer The Arm926EJ-S contains a 32 KB Instruction Cache (ICache), a 32 KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by Arm926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 10.6.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in Arm926EJS TRM). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 10.6.2 Data Cache (DCache) and Write Buffer Arm926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. 10.6.2.1 DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. DS60001516A-page 50  2017 Microchip Technology Inc. SAM9G20 Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in Arm926EJS TRM). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 10.6.2.2 Write Buffer The Arm926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the Arm9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. 10.6.2.3 Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 10.6.2.4 Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 10.7 Bus Interface Unit The Arm926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. • Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 10.7.1 Supported Transfers The Arm926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any Arm9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Microchip bus is AHB-Lite protocol compliant, hence it does not support split and retry requests.  2017 Microchip Technology Inc. DS60001516A-page 51 SAM9G20 The following table gives an overview of the supported transfers and different kinds of transactions they are used for. Table 10-7: HBurst[2:0] Supported Transfers Description Single transfer of word, half word, or byte: • • • • data write (NCNB, NCB, WT, or WB that has missed in DCache) data read (NCNB or NCB) NC instruction fetch (prefetched and non-prefetched) page table walk read SINGLE Single transfer INCR4 Four-word incrementing burst Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. INCR8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. WRAP8 Eight-word wrapping burst Cache linefill 10.7.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of Arm9EJ-S core, are made as 32-bit accesses on the AHB. If the Arm9EJ-S is in Thumb state, then two instructions can be fetched at a time. 10.7.3 Address Alignment The Arm926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. DS60001516A-page 52  2017 Microchip Technology Inc. SAM9G20 11. Debug and Test 11.1 Overview The SAM9G20 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.  2017 Microchip Technology Inc. DS60001516A-page 53 SAM9G20 11.2 Block Diagram Figure 11-1: Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset and Test Arm9EJ-S TST ICE-RT PDC DBGU PIO Arm926EJ-S DTXD DRXD TAP: Test Access Port DS60001516A-page 54  2017 Microchip Technology Inc. SAM9G20 11.3 11.3.1 Application Examples Debug Environment Figure 11-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 11-2: Application Debug and Trace Environment Example Host Debugger PC ICE/JTAG Interface ICE/JTAG Connector SAM9G20 RS232 Connector Terminal SAM9G20-based Application Board 11.3.2 Test Environment The figure below shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 11-3: Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector SAM9G20 Chip n Chip 2 Chip 1 SAM9G20-based Application Board In Test  2017 Microchip Technology Inc. DS60001516A-page 55 SAM9G20 11.4 Debug and Test Pin Description Table 11-1: Debug and Test Pin List Pin Name Function Type Active Level Input/Output Low Input High Reset/Test NRST Microprocessor Reset TST Test Mode Select ICE and JTAG NTRST Test Reset Signal Input Low TCK Test Clock Input – TDI Test Data In Input – TDO Test Data Out Output – TMS Test Mode Select Input – RTCK Returned Test Clock Output – JTAGSEL JTAG Selection Input – Debug Unit DRXD Debug Receive Data Input – DTXD Debug Transmit Data Output – 11.5 11.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 11.5.2 EmbeddedICE The Arm9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an Arm9EJ-S core embedded within the Arm926EJ-S. The internal state of the Arm926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the Arm9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the Arm9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the Arm document: Arm9EJ-S Technical Reference Manual (DDI 0222A). 11.5.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. DS60001516A-page 56  2017 Microchip Technology Inc. SAM9G20 NTRST (optional in IEEE Standard 1149.1) is a Test-Reset input which is mandatory in Arm cores and used to reset the debug logic. On Microchip Arm926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on Arm926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an Arm9E™ running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 11.5.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM9G20 Debug Unit Chip ID value is 0x0199 05A1 on 32-bit width. For further details on the Debug Unit, see Section 27. “Debug Unit (DBGU)”. 11.5.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the Arm processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 11.5.5.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 308 bits that correspond to active pins and associated control signals. Each SAM9G20 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 11-2: SAM9G20 JTAG Boundary Scan Register Bit Number Pin Name Pin Type A0 IN/OUT 307 CONTROL 306 INPUT/OUTPUT 305 CONTROL A1 IN/OUT 304 INPUT/OUTPUT 303 CONTROL A10 IN/OUT 302 INPUT/OUTPUT 301 CONTROL A11 IN/OUT 300 INPUT/OUTPUT 299 CONTROL A12 IN/OUT 298 INPUT/OUTPUT 297 CONTROL A13 296  2017 Microchip Technology Inc. Associated BSR Cells IN/OUT INPUT/OUTPUT DS60001516A-page 57 SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type A14 IN/OUT 295 CONTROL 294 INPUT/OUTPUT 293 CONTROL A15 IN/OUT 292 INPUT/OUTPUT 291 CONTROL A16 IN/OUT 290 INPUT/OUTPUT 289 CONTROL A17 IN/OUT 288 INPUT/OUTPUT 287 CONTROL A18 IN/OUT 286 INPUT/OUTPUT 285 CONTROL A19 IN/OUT 284 INPUT/OUTPUT 283 CONTROL A2 IN/OUT 282 INPUT/OUTPUT 281 CONTROL A20 IN/OUT 280 INPUT/OUTPUT 279 CONTROL A21 IN/OUT 278 INPUT/OUTPUT 277 CONTROL A22 IN/OUT 276 INPUT/OUTPUT 275 CONTROL A3 IN/OUT 274 INPUT/OUTPUT 273 CONTROL A4 IN/OUT 272 INPUT/OUTPUT 271 CONTROL A5 IN/OUT 270 INPUT/OUTPUT 269 CONTROL A6 IN/OUT 268 INPUT/OUTPUT 267 CONTROL A7 IN/OUT 266 INPUT/OUTPUT 265 CONTROL A8 IN/OUT 264 INPUT/OUTPUT 263 CONTROL A9 IN/OUT 262 261 DS60001516A-page 58 Associated BSR Cells INPUT/OUTPUT BMS INPUT INPUT  2017 Microchip Technology Inc. SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type CAS IN/OUT 260 CONTROL 259 INPUT/OUTPUT 258 CONTROL D0 IN/OUT 257 INPUT/OUTPUT 256 CONTROL D1 IN/OUT 255 INPUT/OUTPUT 254 CONTROL D10 IN/OUT 253 INPUT/OUTPUT 252 CONTROL D11 IN/OUT 251 INPUT/OUTPUT 250 CONTROL D12 IN/OUT 249 INPUT/OUTPUT 248 CONTROL D13 IN/OUT 247 INPUT/OUTPUT 246 CONTROL D14 IN/OUT 245 INPUT/OUTPUT 244 CONTROL D15 IN/OUT 243 INPUT/OUTPUT 242 CONTROL D2 IN/OUT 241 INPUT/OUTPUT 240 CONTROL D3 IN/OUT 239 INPUT/OUTPUT 238 CONTROL D4 IN/OUT 237 INPUT/OUTPUT 236 CONTROL D5 IN/OUT 235 INPUT/OUTPUT 234 CONTROL D6 IN/OUT 233 INPUT/OUTPUT 232 CONTROL D7 IN/OUT 231 INPUT/OUTPUT 230 CONTROL D8 IN/OUT 229 INPUT/OUTPUT 228 CONTROL D9 IN/OUT 227 INPUT/OUTPUT 226 CONTROL NANDOE 225  2017 Microchip Technology Inc. Associated BSR Cells IN/OUT INPUT/OUTPUT DS60001516A-page 59 SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type NANDWE IN/OUT 224 CONTROL 223 INPUT/OUTPUT 222 CONTROL NCS0 IN/OUT 221 INPUT/OUTPUT 220 CONTROL NCS1 IN/OUT 219 INPUT/OUTPUT 218 CONTROL NRD IN/OUT 217 INPUT/OUTPUT 216 CONTROL NRST IN/OUT 215 INPUT/OUTPUT 214 CONTROL NWR0 IN/OUT 213 INPUT/OUTPUT 212 CONTROL NWR1 IN/OUT 211 INPUT/OUTPUT 210 CONTROL NWR3 IN/OUT 209 208 INPUT/OUTPUT OSCSEL INPUT PA0 IN/OUT 207 INPUT/OUTPUT 205 CONTROL PA1 IN/OUT 204 INPUT/OUTPUT 203 CONTROL PA10 IN/OUT 202 INPUT/OUTPUT 201 CONTROL PA11 IN/OUT 200 INPUT/OUTPUT 199 CONTROL PA12 IN/OUT 198 INPUT/OUTPUT 197 CONTROL PA13 IN/OUT 196 INPUT/OUTPUT 195 CONTROL PA14 IN/OUT 194 INPUT/OUTPUT 193 CONTROL PA15 IN/OUT 192 INPUT/OUTPUT 191 CONTROL PA16 DS60001516A-page 60 INPUT CONTROL 206 190 Associated BSR Cells IN/OUT INPUT/OUTPUT  2017 Microchip Technology Inc. SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PA17 IN/OUT 189 Associated BSR Cells CONTROL 188 INPUT/OUTPUT 187 CONTROL PA18 IN/OUT 186 INPUT/OUTPUT 185 CONTROL PA19 IN/OUT 184 INPUT/OUTPUT 183 CONTROL PA2 IN/OUT 182 INPUT/OUTPUT 181 CONTROL PA20 IN/OUT 180 INPUT/OUTPUT 179 CONTROL PA21 IN/OUT 178 INPUT/OUTPUT 177 CONTROL PA22 IN/OUT 176 INPUT/OUTPUT 175 CONTROL PA23 IN/OUT 174 INPUT/OUTPUT 173 CONTROL PA24 IN/OUT 172 INPUT/OUTPUT 171 CONTROL PA25 IN/OUT 170 INPUT/OUTPUT 169 CONTROL PA26 IN/OUT 168 INPUT/OUTPUT 167 CONTROL PA27 IN/OUT 166 INPUT/OUTPUT 165 CONTROL PA28 IN/OUT 164 INPUT/OUTPUT 163 CONTROL PA29 IN/OUT 162 INPUT/OUTPUT 161 CONTROL PA3 IN/OUT 160 INPUT/OUTPUT 159 – internal – 158 – internal – 157 – internal – 156 – internal – PA4 IN/OUT 155 154  2017 Microchip Technology Inc. CONTROL INPUT/OUTPUT DS60001516A-page 61 SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PA5 IN/OUT 153 Associated BSR Cells CONTROL 152 INPUT/OUTPUT 151 CONTROL PA6 IN/OUT 150 INPUT/OUTPUT 149 CONTROL PA7 IN/OUT 148 INPUT/OUTPUT 147 CONTROL PA8 IN/OUT 146 INPUT/OUTPUT 145 CONTROL PA9 IN/OUT 144 INPUT/OUTPUT 143 CONTROL PB0 IN/OUT 142 INPUT/OUTPUT 141 CONTROL PB1 IN/OUT 140 INPUT/OUTPUT 139 CONTROL PB10 IN/OUT 138 INPUT/OUTPUT 137 CONTROL PB11 IN/OUT 136 INPUT/OUTPUT 135 – internal – 134 – internal – 133 – internal – 132 – internal – PB14 IN/OUT 131 CONTROL 130 INPUT/OUTPUT 129 CONTROL PB15 IN/OUT 128 INPUT/OUTPUT 127 CONTROL PB16 IN/OUT 126 INPUT/OUTPUT 125 CONTROL PB17 IN/OUT 124 INPUT/OUTPUT 123 CONTROL PB18 IN/OUT 122 INPUT/OUTPUT 121 CONTROL PB19 IN/OUT 120 INPUT/OUTPUT 119 CONTROL PB2 118 DS60001516A-page 62 IN/OUT INPUT/OUTPUT  2017 Microchip Technology Inc. SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PB20 IN/OUT 117 CONTROL 116 INPUT/OUTPUT 115 CONTROL PB21 IN/OUT 114 INPUT/OUTPUT 113 CONTROL PB22 IN/OUT 112 INPUT/OUTPUT 111 CONTROL PB23 IN/OUT 110 INPUT/OUTPUT 109 CONTROL PB24 IN/OUT 108 INPUT/OUTPUT 107 CONTROL PB25 IN/OUT 106 INPUT/OUTPUT 105 CONTROL PB26 IN/OUT 104 INPUT/OUTPUT 103 CONTROL PB27 IN/OUT 102 INPUT/OUTPUT 101 CONTROL PB28 IN/OUT 100 INPUT/OUTPUT 99 CONTROL PB29 IN/OUT 98 INPUT/OUTPUT 97 CONTROL PB3 IN/OUT 96 INPUT/OUTPUT 95 CONTROL PB30 IN/OUT 94 INPUT/OUTPUT 93 CONTROL PB31 IN/OUT 92 INPUT/OUTPUT 91 CONTROL PB4 IN/OUT 90 INPUT/OUTPUT 89 CONTROL PB5 IN/OUT 88 INPUT/OUTPUT 87 CONTROL PB6 IN/OUT 86 INPUT/OUTPUT 85 CONTROL PB7 IN/OUT 84 INPUT/OUTPUT 83 CONTROL PB8 82  2017 Microchip Technology Inc. Associated BSR Cells IN/OUT INPUT/OUTPUT DS60001516A-page 63 SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PB9 IN/OUT 81 Associated BSR Cells CONTROL 80 INPUT/OUTPUT 79 CONTROL PC0 IN/OUT 78 INPUT/OUTPUT 77 CONTROL PC1 IN/OUT 76 INPUT/OUTPUT 75 CONTROL PC10 IN/OUT 74 INPUT/OUTPUT 73 CONTROL PC11 IN/OUT 72 INPUT/OUTPUT 71 – internal – 70 – internal – PC13 IN/OUT 69 CONTROL 68 INPUT/OUTPUT 67 CONTROL PC14 IN/OUT 66 INPUT/OUTPUT 65 CONTROL PC15 IN/OUT 64 INPUT/OUTPUT 63 CONTROL PC16 IN/OUT 62 INPUT/OUTPUT 61 CONTROL PC17 IN/OUT 60 INPUT/OUTPUT 59 CONTROL PC18 IN/OUT 58 INPUT/OUTPUT 57 CONTROL PC19 IN/OUT 56 INPUT/OUTPUT 55 – internal – 54 – internal – PC20 IN/OUT 53 CONTROL 52 INPUT/OUTPUT 51 CONTROL PC21 IN/OUT 50 INPUT/OUTPUT 49 CONTROL PC22 IN/OUT 48 INPUT/OUTPUT 47 CONTROL PC23 46 DS60001516A-page 64 IN/OUT INPUT/OUTPUT  2017 Microchip Technology Inc. SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PC24 IN/OUT 45 Associated BSR Cells CONTROL 44 INPUT/OUTPUT 43 CONTROL PC25 IN/OUT 42 INPUT/OUTPUT 41 CONTROL PC26 IN/OUT 40 INPUT/OUTPUT 39 CONTROL PC27 IN/OUT 38 INPUT/OUTPUT 37 CONTROL PC28 IN/OUT 36 INPUT/OUTPUT 35 CONTROL PC29 IN/OUT 34 INPUT/OUTPUT 33 – internal – 32 – internal – PC30 IN/OUT 31 CONTROL 30 INPUT/OUTPUT 29 CONTROL PC31 IN/OUT 28 INPUT/OUTPUT 27 CONTROL PC4 IN/OUT 26 INPUT/OUTPUT 25 CONTROL PC5 IN/OUT 24 INPUT/OUTPUT 23 CONTROL PC6 IN/OUT 22 INPUT/OUTPUT 21 CONTROL PC7 IN/OUT 20 INPUT/OUTPUT 19 CONTROL PC8 IN/OUT 18 INPUT/OUTPUT 17 CONTROL PC9 IN/OUT 16 INPUT/OUTPUT 15 CONTROL RAS IN/OUT 14 INPUT/OUTPUT 13 CONTROL RTCK OUT 12 OUTPUT 11 CONTROL SDA10 10  2017 Microchip Technology Inc. IN/OUT INPUT/OUTPUT DS60001516A-page 65 SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type SDCK IN/OUT 09 Associated BSR Cells CONTROL 08 INPUT/OUTPUT 07 CONTROL SDCKE IN/OUT 06 INPUT/OUTPUT 05 CONTROL SDWE IN/OUT 04 INPUT/OUTPUT 03 CONTROL SHDN OUT 02 OUTPUT 01 TST INPUT INPUT 00 WKUP INPUT INPUT DS60001516A-page 66  2017 Microchip Technology Inc. SAM9G20 11.5.6 JID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 MANUFACTURER IDENTITY 3 2 1 0 1 VERSION[31:28]: Product Version Number Set to 0x0. PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B24 MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_403F.  2017 Microchip Technology Inc. DS60001516A-page 67 SAM9G20 12. Boot Program 12.1 Overview The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial Flash Boot program and DataFlash Boot program are executed. It looks for a sequence of seven valid Arm exception vectors in a Serial Flash or DataFlash connected to the SPI. All these vectors must be Bbranch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid Arm vector sequence is found, NAND Flash Boot program is then executed. The NAND Flash Boot program looks for a sequence of seven valid Arm exception vectors. If such a sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid Arm exception vector is found, the SDCard Boot program is then executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SDCard on Slot A. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If the SDCard is not formatted or if boot.bin file is not found, TWI Boot program is then executed. The TWI Boot program searches for a valid application in an EEPROM memory. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid application is found, SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 12.2 Flow Diagram The Boot Program implements the algorithm in Figure 12-1. DS60001516A-page 68  2017 Microchip Technology Inc. SAM9G20 Figure 12-1: Boot Program Algorithm Flow Diagram Device Setup SPI Serialflash Boot NPCS0 No Yes Download from Serial flash NPCS1 Run Yes Download from Dataflash NPCS1 Run Yes Download from NandFlash Run NandFlash Boot Yes Download from SDCARD Run SD Card Boot Yes Download from EEPROM Run TWI/EEPROM Boot DataFlash Boot NPCS0 DataFlash Boot NPCS1 Timeout 50ms. Character(s) received on DBGU Run SAM-BA Boot OR SAM-BA Boot USB Enumeration Successful  2017 Microchip Technology Inc. Serial Flash Boot NPCS1 Timeout < 50ms EEPROMBoot No Run Timeout < 50ms SD Card Boot No Download from Dataflash NPCS0 Timeout < 25 ms NandFlash Boot No Yes Serial Flash Boot NPCS0 Timeout < 25 ms SPI Dataflash Boot NPCS1 No Run Timeout < 25 ms SPI Serialflash Boot NPCS1 No Download from Serial flash NPCS0 Timeout < 25 ms SPI Dataflash Boot NPCS0 No Yes Run SAM-BA Boot DS60001516A-page 69 SAM9G20 12.3 Device Initialization Initialization follows the steps described below: 1. 2. 3. 4. Stack setup for Arm supervisor mode Main Oscillator Frequency Detection C variable initialization PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. - If internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is active, TTable 12-1 defines the crystals supported by the Boot Program when using the internal RC oscillator. also supported by the Boot Program. Table 12-1: Crystals Supported by Software Auto-Detection (MHz) 3.0 8.0 18.432 Other Boot in DBGU Yes Yes Yes Yes Boot on USB Yes Yes Yes No Note: Any other crystal can be used but it prevents using the USB. - If internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is bypassed, Table 12-2 defines the frequencies supported by the Boot Program when bypassing the main oscillator. Table 12-2: Crystals Supported by Software Auto-Detection (MHz) 3.0 8.0 20 50 Other Boot in DBGU Yes Yes Yes Yes Yes Boot on USB Yes Yes Yes Yes No Note: Any other crystal can be used but it prevents using the USB. - If an external 32768 Hz Oscillator is used (OSCSEL = 1), defines the crystals supported by the Boot Program. Table 12-3 defines the crystals supported by the Boot Program. Table 12-3: Crystals Supported by Software Auto-Detection (MHz) 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.608 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 17.734470 18.432 20.0 Note: Booting either on USB or on DBGU is possible with any of these input frequencies. - If an external 32768 Hz Oscillator is used (OSCSEL = 1) and Main Oscillator is bypassed. Table 12-4 defines the crystals supported by the Boot Program. Table 12-4: Input Frequencies Supported (OSCEL = 1) 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.608 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 DS60001516A-page 70  2017 Microchip Technology Inc. SAM9G20 Table 12-4: Input Frequencies Supported (OSCEL = 1) 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 17.734470 18.432 20.0 24.0 24.576 25.0 28.224 32.0 33.0 40.0 48.0 50 Note: 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Booting either on USB or on DBGU is possible with any of these input frequencies. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) Jump to Serial Flash Boot sequence through NPCS0. If Serial Flash Boot succeeds, perform a remap and jump to 0x0. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, perform a remap and jump to 0x0. Jump to Serial Flash Boot sequence through NPCS1. If Serial Flash Boot succeeds, perform a remap and jump to 0x0. Jump to DataFlash Boot sequence through NPCS1. If DataFlash Boot succeeds, perform a remap and jump to 0x0. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. Jump to SDCard Boot sequence. If SDCard Boot succeeds, perform a remap and jump to 0x0. Jump to EEPROM Boot sequence. If EEPROM Boot succeeds, perform a remap and jump to 0x0. Activation of the Instruction Cache Jump to SAM-BA Boot sequence Disable the WatchDog Initialization of the USB Device Port Figure 12-2: Remap Action after Download Completion 0x0000_0000 0x0000_0000 Internal ROM Internal SRAM REMAP 0x0020_0000 0x0010_0000 Internal SRAM 12.4 Internal ROM Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corresponding to the Arm exception vectors. These bytes must implement Arm instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his/her own vector (see “Structure of Arm Vector 6”). 12.4.1 Valid Arm exception vectors Figure 12-3: LDR Opcode 31 1 28 27 1 1 0  2017 Microchip Technology Inc. 0 24 23 1 I P U 20 19 0 W 1 16 15 Rn 12 11 0 Rd DS60001516A-page 71 SAM9G20 Figure 12-4: B Opcode 31 1 28 27 1 1 0 1 24 23 0 1 0 0 Offset (24 bits) Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: - Rn = Rd = PC = 0xF I==0 P==1 U offset added (U==1) or subtracted (U==0) W==1 12.4.2 Structure of Arm Vector 6 The Arm exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below. Figure 12-5: Structure of the Arm Vector 6 31 0 Size of the code to download in bytes 12.4.2.1 Example An example of valid vectors follows: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 ’. • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. - Address: Address in hexadecimal - Output: The byte, halfword or word read in hexadecimal following by ‘>’ • Send a file (S): Send a file to a specified address - Address: Address in hexadecimal - Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address - Address: Address in hexadecimal - NbOfBytes: Number of bytes in hexadecimal to receive - Output: ‘>’  2017 Microchip Technology Inc. DS60001516A-page 75 SAM9G20 • Go (G): Jump to a specified address and execute the code - Address: Address to jump in hexadecimal - Output: ‘>’ • Get Version (V): Return the SAM-BA boot version - Output: ‘>’ 12.10.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 12.10.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: - = 01 hex = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) = 1’s complement of the blk#. = 2 bytes CRC16 Figure 12-8 shows a transmission using this protocol. Figure 12-8: Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 12.10.3 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, beginning with Windows 98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Microchip’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. DS60001516A-page 76  2017 Microchip Technology Inc. SAM9G20 Microchip provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 12.10.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 12-6: Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value SET_ADDRESS Sets the device address for all future device access SET_CONFIGURATION Sets the device configuration GET_CONFIGURATION Returns the current device configuration value GET_STATUS Returns status for the specified recipient SET_FEATURE Used to set or enable a specific feature CLEAR_FEATURE Used to clear or disable a specific feature The device also handles some class requests defined in the CDC class. Table 12-7: Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present Unhandled requests are STALLed. 12.10.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response.  2017 Microchip Technology Inc. DS60001516A-page 77 SAM9G20 12.11 Hardware and Software Constraints • The DataFlash, Serial Flash, NAND Flash, SDCard(1), and EEPROM downloaded code size must be inferior to 16K bytes. • The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). • The downloaded code must be position-independent or linked at address 0x0000_0000. • The DataFlash must be connected to NPCS0 of the SPI. Note 1: Boot ROM does not support high capacity SDCards. The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 12-8 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 12-8: Pins Driven during Boot Program Execution Peripheral Pin PIO Line SPI0 MOSI PIOA1 SPI0 MISO PIOA0 SPI0 SPCK PIOA2 SPI0 NPCS0 PIOA3 SPI0 NPCS1 PIOC11 PIOC NANDCS PIOC14 Address Bus NAND CLE A22 Address Bus NAND ALE A21 MCI0 MCDA0 PIOA6 MCI0 MCCDA PIOA7 MCI0 MCCK PIOA8 MCI0 MCDA1 PIOA9 MCI0 MCDA2 PIOA10 MCI0 MCDA3 PIOA11 TWI TWCK PIOA24 TWI TWD PIOA23 DBGU DRXD PIOB14 DBGU DTXD PIOB15 DS60001516A-page 78  2017 Microchip Technology Inc. SAM9G20 13. Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 13.2 Block Diagram Figure 13-1: Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR rstc_irq Startup Counter Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager periph_nreset exter_nreset backup_neset WDRPROC wd_fault SLCK 13.3 13.3.1 Functional Description Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • • • • proc_nreset: Processor reset line. It also resets the Watchdog Timer. backup_nreset: Affects all the peripherals powered by VDDBU. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in Section 40.5 Crystal Oscillator Characteristics. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.  2017 Microchip Technology Inc. DS60001516A-page 79 SAM9G20 13.3.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager. Figure 13-2: NRST Manager RSTC_MR URSTIEN RSTC_SR URSTS NRSTL rstc_irq RSTC_MR URSTEN Other interrupt sources user_reset NRST RSTC_MR ERSTL nrst_out 13.3.2.1 External Reset Timer exter_nreset NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 13.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 13.3.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. DS60001516A-page 80  2017 Microchip Technology Inc. SAM9G20 Figure 13-3: BMS Sampling SLCK Core Supply POR output BMS Signal XXX H or L BMS sampling delay = 3 cycles proc_nreset 13.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.3.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 13-4 shows how the General Reset affects the reset signals.  2017 Microchip Technology Inc. DS60001516A-page 81 SAM9G20 Figure 13-4: General Reset State SLCK Any Freq. MCK Backup Supply POR output Startup Time Main Supply POR output backup_nreset Processor Startup = 3 cycles proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) BMS Sampling EXTERNAL RESET LENGTH = 2 cycles 13.3.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the Arm processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. DS60001516A-page 82  2017 Microchip Technology Inc. SAM9G20 Figure 13-5: Wake-up State SLCK Any Freq. MCK Main Supply POR output backup_nreset Resynch. 2 cycles proc_nreset RSTTYP Processor Startup = 3 cycles XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 13.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.  2017 Microchip Technology Inc. DS60001516A-page 83 SAM9G20 Figure 13-6: User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 13.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. DS60001516A-page 84  2017 Microchip Technology Inc. SAM9G20 Figure 13-7: Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 13.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.  2017 Microchip Technology Inc. DS60001516A-page 85 SAM9G20 Figure 13-8: Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 13.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • • • • • Backup Reset Wake-up Reset Watchdog Reset Software Reset User Reset Particular cases are listed below: • When in User Reset: - A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. - A software reset is impossible, since the processor reset is being activated. • When in Software Reset: - A watchdog event has priority over the current state. - The NRST has no effect. • When in Watchdog Reset: - The processor reset is active and so a Software Reset cannot be programmed. - A User Reset cannot be entered. 13.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. DS60001516A-page 86  2017 Microchip Technology Inc. SAM9G20 Figure 13-9: Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1)  2017 Microchip Technology Inc. DS60001516A-page 87 SAM9G20 13.4 Reset Controller (RSTC) User Interface Table 13-1: Register Mapping Offset Register Name Access Reset Value Backup Reset Value 0x00 Control Register RSTC_CR Write-only – – 0x04 Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 0x08 Mode Register RSTC_MR Read/Write – 0x0000_0000 Note 1: The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. DS60001516A-page 88  2017 Microchip Technology Inc. SAM9G20 13.4.1 Reset Controller Control Register Name:RSTC_CR Access:Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. EXTRST: External Reset 0: No effect. 1: If KEY is correct, asserts the NRST pin. KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.  2017 Microchip Technology Inc. DS60001516A-page 89 SAM9G20 13.4.2 Reset Controller Status Register Name:RSTC_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP Reset Type Comments 0 0 0 General Reset Both VDDCORE and VDDBU rising 0 0 1 Wake Up Reset VDDCORE rising 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor reset required by the software 1 0 0 User Reset NRST pin detected low NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). SRCMP: Software Reset Command in Progress 0: No software command is being performed by the reset controller. The reset controller is ready for a software command. 1: A software reset command is being performed by the reset controller. The reset controller is busy. DS60001516A-page 90  2017 Microchip Technology Inc. SAM9G20 13.4.3 Reset Controller Mode Register Name:RSTC_MR Access:Read/Write 31 30 29 28 27 26 25 24 17 – 16 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset. URSTIEN: User Reset Interrupt Enable 0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.  2017 Microchip Technology Inc. DS60001516A-page 91 SAM9G20 14. Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1: RTT_MR RTTRST Real-time Timer RTT_MR RTPRES RTT_MR SLCK RTTINCIEN reload 16-bit Divider set 0 RTT_MR RTTRST RTT_SR 1 RTTINC reset 0 rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set rtt_alarm = RTT_AR 14.3 ALMV Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. DS60001516A-page 92  2017 Microchip Technology Inc. SAM9G20 Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). Figure 14-2: RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR  2017 Microchip Technology Inc. DS60001516A-page 93 SAM9G20 14.4 Real-time Timer (RTT) User Interface Table 14-1: Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read/Write 0x0000_8000 0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 DS60001516A-page 94  2017 Microchip Technology Inc. SAM9G20 14.4.1 Real-time Timer Mode Register Name:RTT_MR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES ≠ 0: The prescaler period is equal to RTPRES. ALMIEN: Alarm Interrupt Enable 0: The bit ALMS in RTT_SR has no effect on interrupt. 1: The bit ALMS in RTT_SR asserts interrupt. RTTINCIEN: Real-time Timer Increment Interrupt Enable 0: The bit RTTINC in RTT_SR has no effect on interrupt. 1: The bit RTTINC in RTT_SR asserts interrupt. RTTRST: Real-time Timer Restart 1: Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.  2017 Microchip Technology Inc. DS60001516A-page 95 SAM9G20 14.4.2 Real-time Timer Alarm Register Name:RTT_AR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. DS60001516A-page 96  2017 Microchip Technology Inc. SAM9G20 14.4.3 Real-time Timer Value Register Name:RTT_VR Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV CRTV: Current Real-time Value Returns the current value of the Real-time Timer.  2017 Microchip Technology Inc. DS60001516A-page 97 SAM9G20 14.4.4 Real-time Timer Status Register Name:RTT_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR. RTTINC: Real-time Timer Increment 0: The Real-time Timer has not been incremented since the last read of the RTT_SR. 1: The Real-time Timer has been incremented since the last read of the RTT_SR. DS60001516A-page 98  2017 Microchip Technology Inc. SAM9G20 15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1: Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR pit_irq PITS reset 0 MCK Prescaler 15.3 0 0 1 12-bit Adder 1 read PIT_PIVR 20-bit Counter MCK/16 CPIV PIT_PIVR CPIV PIT_PIIR PICNT PICNT Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN = 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.  2017 Microchip Technology Inc. DS60001516A-page 99 SAM9G20 The PIT is stopped when the core enters debug state. Figure 15-2: Enabling/Disabling PIT with PITEN APB cycle APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN CPIV PICNT 0 1 PIV - 1 0 PIV 1 0 1 0 PITS (PIT_SR) APB Interface read PIT_PIVR DS60001516A-page 100  2017 Microchip Technology Inc. SAM9G20 15.4 Periodic Interval Timer (PIT) User Interface Table 15-1: Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read/Write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000  2017 Microchip Technology Inc. DS60001516A-page 101 SAM9G20 15.4.1 Periodic Interval Timer Mode Register Name:PIT_MR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). PITEN: Period Interval Timer Enabled 0: The Periodic Interval Timer is disabled when the PIV value is reached. 1: The Periodic Interval Timer is enabled. PITIEN: Periodic Interval Timer Interrupt Enable 0: The bit PITS in PIT_SR has no effect on interrupt. 1: The bit PITS in PIT_SR asserts interrupt. DS60001516A-page 102  2017 Microchip Technology Inc. SAM9G20 15.4.2 Periodic Interval Timer Status Register Name:PIT_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.  2017 Microchip Technology Inc. DS60001516A-page 103 SAM9G20 15.4.3 Periodic Interval Timer Value Register Name:PIT_PIVR Access:Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. DS60001516A-page 104  2017 Microchip Technology Inc. SAM9G20 15.4.4 Periodic Interval Timer Image Register Name:PIT_PIIR Access:Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.  2017 Microchip Technology Inc. DS60001516A-page 105 SAM9G20 16. Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 Block Diagram Figure 16-1: Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR WDD reload Current Value 1/128 SLCK 1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 27.4.2 27.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 27.4.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Figure 27-4: Start Bit Detection Sampling Clock DRXD True Start Detection D0 Baud Rate Clock DS60001516A-page 326  2017 Microchip Technology Inc. SAM9G20 Figure 27-5: Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling 27.4.2.3 D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 27-6: Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 27.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 27-7: Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 27.4.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 27-8: Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit  2017 Microchip Technology Inc. RSTSTA DS60001516A-page 327 SAM9G20 27.4.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 27-9: Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 27.4.3 27.4.3.1 RSTSTA Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 27.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 27-10: Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit 27.4.3.3 D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. DS60001516A-page 328  2017 Microchip Technology Inc. SAM9G20 Figure 27-11: Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 Data 0 S Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR 27.4.4 Write Data 1 in DBGU_THR Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. 27.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.  2017 Microchip Technology Inc. DS60001516A-page 329 SAM9G20 Figure 27-12: Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter 27.4.6 TXD VDD Disabled Disabled RXD TXD Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the Arm Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the Arm Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. DS60001516A-page 330  2017 Microchip Technology Inc. SAM9G20 27.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: • • • • • • EXT - shows the use of the extension identifier register NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size ARCH - identifies the set of embedded peripherals SRAMSIZ - indicates the size of the embedded SRAM EPROC - indicates the embedded Arm processor VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 27.4.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the Arm processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.  2017 Microchip Technology Inc. DS60001516A-page 331 SAM9G20 27.5 Debug Unit (DBGU) User Interface Table 27-2: Register Mapping Offset Register Name Access Reset 0x0000 Control Register DBGU_CR Write-only – 0x0004 Mode Register DBGU_MR Read/Write 0x0 0x0008 Interrupt Enable Register DBGU_IER Write-only – 0x000C Interrupt Disable Register DBGU_IDR Write-only – 0x0010 Interrupt Mask Register DBGU_IMR Read-only 0x0 0x0014 Status Register DBGU_SR Read-only – 0x0018 Receive Holding Register DBGU_RHR Read-only 0x0 0x001C Transmit Holding Register DBGU_THR Write-only – 0x0020 Baud Rate Generator Register DBGU_BRGR Read/Write 0x0 Reserved – – – 0x0040 Chip ID Register DBGU_CIDR Read-only – 0x0044 Chip ID Extension Register DBGU_EXID Read-only – 0x0048 Force NTRST Register DBGU_FNR Read/Write 0x0 0x004C–0x00FC Reserved – – – 0x0100–0x0124 PDC Area – – – 0x0024–0x003C DS60001516A-page 332  2017 Microchip Technology Inc. SAM9G20 27.5.1 Debug Unit Control Register Name:DBGU_CR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted. RSTTX: Reset Transmitter 0: No effect. 1: The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. RXEN: Receiver Enable 0: No effect. 1: The receiver is enabled if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. TXEN: Transmitter Enable 0: No effect. 1: The transmitter is enabled if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.  2017 Microchip Technology Inc. DS60001516A-page 333 SAM9G20 27.5.2 Debug Unit Mode Register Name:DBGU_MR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 14 13 12 11 10 9 – – 15 CHMODE PAR 8 – 7 6 5 4 3 2 1 0 – – – – – – – – PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Space: parity forced to 0 0 1 1 Mark: parity forced to 1 1 x x No parity CHMODE: Channel Mode CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo 1 0 Local Loopback 1 1 Remote Loopback DS60001516A-page 334  2017 Microchip Technology Inc. SAM9G20 27.5.3 Debug Unit Interrupt Enable Register Name:DBGU_IER Access:Write-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY RXRDY: Enable RXRDY Interrupt TXRDY: Enable TXRDY Interrupt ENDRX: Enable End of Receive Transfer Interrupt ENDTX: Enable End of Transmit Interrupt OVRE: Enable Overrun Error Interrupt FRAME: Enable Framing Error Interrupt PARE: Enable Parity Error Interrupt TXEMPTY: Enable TXEMPTY Interrupt TXBUFE: Enable Buffer Empty Interrupt RXBUFF: Enable Buffer Full Interrupt COMMTX: Enable COMMTX (from Arm) Interrupt COMMRX: Enable COMMRX (from Arm) Interrupt 0: No effect. 1: Enables the corresponding interrupt.  2017 Microchip Technology Inc. DS60001516A-page 335 SAM9G20 27.5.4 Debug Unit Interrupt Disable Register Name:DBGU_IDR Access:Write-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY RXRDY: Disable RXRDY Interrupt TXRDY: Disable TXRDY Interrupt ENDRX: Disable End of Receive Transfer Interrupt ENDTX: Disable End of Transmit Interrupt OVRE: Disable Overrun Error Interrupt FRAME: Disable Framing Error Interrupt PARE: Disable Parity Error Interrupt TXEMPTY: Disable TXEMPTY Interrupt TXBUFE: Disable Buffer Empty Interrupt RXBUFF: Disable Buffer Full Interrupt COMMTX: Disable COMMTX (from Arm) Interrupt COMMRX: Disable COMMRX (from Arm) Interrupt 0: No effect. 1: Disables the corresponding interrupt. DS60001516A-page 336  2017 Microchip Technology Inc. SAM9G20 27.5.5 Debug Unit Interrupt Mask Register Name:DBGU_IMR Access:Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY RXRDY: Mask RXRDY Interrupt TXRDY: Disable TXRDY Interrupt ENDRX: Mask End of Receive Transfer Interrupt ENDTX: Mask End of Transmit Interrupt OVRE: Mask Overrun Error Interrupt FRAME: Mask Framing Error Interrupt PARE: Mask Parity Error Interrupt TXEMPTY: Mask TXEMPTY Interrupt TXBUFE: Mask TXBUFE Interrupt RXBUFF: Mask RXBUFF Interrupt COMMTX: Mask COMMTX Interrupt COMMRX: Mask COMMRX Interrupt 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.  2017 Microchip Technology Inc. DS60001516A-page 337 SAM9G20 27.5.6 Debug Unit Status Register Name:DBGU_SR Access:Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY RXRDY: Receiver Ready 0: No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1: At least one complete character has been received, transferred to DBGU_RHR and not yet read. TXRDY: Transmitter Ready 0: A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1: There is no character written to DBGU_THR not yet transferred to the Shift Register. ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1: The End of Transfer signal from the receiver Peripheral Data Controller channel is active. ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1: The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. FRAME: Framing Error 0: No framing error has occurred since the last RSTSTA. 1: At least one framing error has occurred since the last RSTSTA. PARE: Parity Error 0: No parity error has occurred since the last RSTSTA. 1: At least one parity error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty 0: There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1: There are no characters in DBGU_THR and there are no characters being processed by the transmitter. TXBUFE: Transmission Buffer Empty 0: The buffer empty signal from the transmitter PDC channel is inactive. 1: The buffer empty signal from the transmitter PDC channel is active. DS60001516A-page 338  2017 Microchip Technology Inc. SAM9G20 RXBUFF: Receive Buffer Full 0: The buffer full signal from the receiver PDC channel is inactive. 1: The buffer full signal from the receiver PDC channel is active. COMMTX: Debug Communication Channel Write Status 0: COMMTX from the Arm processor is inactive. 1: COMMTX from the Arm processor is active. COMMRX: Debug Communication Channel Read Status 0: COMMRX from the Arm processor is inactive. 1: COMMRX from the Arm processor is active.  2017 Microchip Technology Inc. DS60001516A-page 339 SAM9G20 27.5.7 Debug Unit Receiver Holding Register Name:DBGU_RHR Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last received character if RXRDY is set. DS60001516A-page 340  2017 Microchip Technology Inc. SAM9G20 27.5.8 Debug Unit Transmit Holding Register Name:DBGU_THR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.  2017 Microchip Technology Inc. DS60001516A-page 341 SAM9G20 27.5.9 Debug Unit Baud Rate Generator Register Name:DBGU_BRGR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD CD: Clock Divisor CD Baud Rate Clock 0 Disabled 1 MCK 2–65535 DS60001516A-page 342 MCK / (CD x 16)  2017 Microchip Technology Inc. SAM9G20 27.5.10 Debug Unit Chip ID Register Name:DBGU_CIDR Access:Read-only 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 3 EPROC 2 VERSION VERSION: Version of the Device Current version of the device. EPROC: Embedded Processor EPROC Processor 0 0 1 Arm946ES 0 1 0 Arm7TDMI 1 0 0 Arm920T 1 0 1 Arm926EJS NVPSIZ: Nonvolatile Program Memory Size NVPSIZ Size 0 0 0 0 None 0 0 0 1 8K bytes 0 0 1 0 16K bytes 0 0 1 1 32K bytes 0 1 0 0 Reserved 0 1 0 1 64K bytes 0 1 1 0 Reserved 0 1 1 1 128K bytes 1 0 0 0 Reserved 1 0 0 1 256K bytes 1 0 1 0 512K bytes 1 0 1 1 Reserved 1 1 0 0 1024K bytes 1 1 0 1 Reserved 1 1 1 0 2048K bytes 1 1 1 1 Reserved  2017 Microchip Technology Inc. DS60001516A-page 343 SAM9G20 NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 Size 0 0 0 0 None 0 0 0 1 8K bytes 0 0 1 0 16K bytes 0 0 1 1 32K bytes 0 1 0 0 Reserved 0 1 0 1 64K bytes 0 1 1 0 Reserved 0 1 1 1 128K bytes 1 0 0 0 Reserved 1 0 0 1 256K bytes 1 0 1 0 512K bytes 1 0 1 1 Reserved 1 1 0 0 1024K bytes 1 1 0 1 Reserved 1 1 1 0 2048K bytes 1 1 1 1 Reserved SRAMSIZ: Internal SRAM Size SRAMSIZ Size 0 0 0 0 Reserved 0 0 0 1 1K bytes 0 0 1 0 2K bytes 0 0 1 1 6K bytes 0 1 0 0 112K bytes 0 1 0 1 4K bytes 0 1 1 0 80K bytes 0 1 1 1 160K bytes 1 0 0 0 8K bytes 1 0 0 1 16K bytes 1 0 1 0 32K bytes 1 0 1 1 64K bytes 1 1 0 0 128K bytes 1 1 0 1 256K bytes 1 1 1 0 96K bytes 1 1 1 1 512K bytes DS60001516A-page 344  2017 Microchip Technology Inc. SAM9G20 ARCH: Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 0111 0001 AT91SAM7XCxx Series 0x72 0111 0010 AT91SAM7SExx Series 0x73 0111 0011 AT91SAM7Lxx Series 0x75 0111 0101 AT91SAM7Xxx Series 0x92 1001 0010 AT91x92 Series 0xF0 1111 0000 AT75Cxx Series NVPTYP: Nonvolatile Program Memory Type NVPTYP Memory 0 0 0 ROM 0 0 1 ROMless or on-chip Flash 1 0 0 SRAM emulating ROM 0 1 0 Embedded Flash Memory 0 1 1 ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size EXT: Extension Flag 0: Chip ID has a single register definition without extension 1: An extended Chip ID exists.  2017 Microchip Technology Inc. DS60001516A-page 345 SAM9G20 27.5.11 Debug Unit Chip ID Extension Register Name:DBGU_EXID Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. DS60001516A-page 346  2017 Microchip Technology Inc. SAM9G20 27.5.12 Debug Unit Force NTRST Register Name: DBGU_FNR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST FNTRST: Force NTRST 0: NTRST of the Arm processor’s TAP controller is driven by the power_on_reset signal. 1: NTRST of the Arm processor’s TAP controller is held low.  2017 Microchip Technology Inc. DS60001516A-page 347 SAM9G20 28. Parallel Input Output Controller (PIO) 28.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: • • • • • An input change interrupt enabling level change detection on any I/O line. A glitch filter providing rejection of pulses lower than one-half of clock cycle. Multi-drive capability similar to an open drain I/O line. Control of the pull-up of the I/O line. Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 28.2 Block Diagram Figure 28-1: Block Diagram PIO Controller AIC PMC PIO Interrupt PIO Clock Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB DS60001516A-page 348  2017 Microchip Technology Inc. SAM9G20 Figure 28-2: Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver 28.3 28.3.1 General Purpose I/Os External Devices Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. 28.3.2 External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. 28.3.3 Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 28.3.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.  2017 Microchip Technology Inc. DS60001516A-page 349 SAM9G20 28.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 28-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 28-3: I/O Line Control Logic PIO_OER[0] PIO_OSR[0] PIO_PUER[0] PIO_ODR[0] PIO_PUSR[0] PIO_PUDR[0] 1 Peripheral A Output Enable 0 0 Peripheral B Output Enable 0 1 PIO_PER[0] PIO_ASR[0] 1 PIO_PSR[0] PIO_ABSR[0] PIO_PDR[0] PIO_BSR[0] Peripheral A Output 0 Peripheral B Output 1 PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 0 0 PIO_SODR[0] PIO_ODSR[0] 1 Pad PIO_CODR[0] 1 Peripheral A Input PIO_PDSR[0] PIO_ISR[0] 0 Edge Detector Glitch Filter Peripheral B Input (Up to 32 possible inputs) PIO Interrupt 1 PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] DS60001516A-page 350  2017 Microchip Technology Inc. SAM9G20 28.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 28.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 28.4.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 28.4.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/ O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 28.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.  2017 Microchip Technology Inc. DS60001516A-page 351 SAM9G20 28.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multidriver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 28.4.7 Output Line Timings Figure 28-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 28-4 also shows when the feedback in PIO_PDSR is available. Figure 28-4: Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 28.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/ O line at the time the clock was disabled. 28.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 28-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. DS60001516A-page 352  2017 Microchip Technology Inc. SAM9G20 Figure 28-5: Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles up to 2.5 cycles PIO_PDSR if PIO_IFSR = 1 28.4.10 1 cycle up to 2 cycles Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 28-6: Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR 28.5 APB Access APB Access I/O Lines Programming Example The programing example as shown in Table 28-1 below is used to define the following configuration. • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor • Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor • Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts • Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter  2017 Microchip Technology Inc. DS60001516A-page 353 SAM9G20 • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor • I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor • I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 28-1: Programming Example Register Value to be Written PIO_PER 0x0000 FFFF PIO_PDR 0x0FFF 0000 PIO_OER 0x0000 00FF PIO_ODR 0x0FFF FF00 PIO_IFER 0x0000 0F00 PIO_IFDR 0x0FFF F0FF PIO_SODR 0x0000 0000 PIO_CODR 0x0FFF FFFF PIO_IER 0x0F00 0F00 PIO_IDR 0x00FF F0FF PIO_MDER 0x0000 000F PIO_MDDR 0x0FFF FFF0 PIO_PUDR 0x00F0 00F0 PIO_PUER 0x0F0F FF0F PIO_ASR 0x0F0F 0000 PIO_BSR 0x00F0 0000 PIO_OWER 0x0000 000F PIO_OWDR 0x0FFF FFF0 DS60001516A-page 354  2017 Microchip Technology Inc. SAM9G20 28.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 28-2: Register Mapping Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only – 0x0004 PIO Disable Register PIO_PDR Write-only – PIO_PSR Read-only (1) 0x0008 PIO Status Register 0x000C Reserved 0x0010 Output Enable Register PIO_OER Write-only – 0x0014 Output Disable Register PIO_ODR Write-only – 0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000 0x001C Reserved 0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only – 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only – 0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000 0x002C Reserved 0x0030 Set Output Data Register PIO_SODR Write-only – 0x0034 Clear Output Data Register PIO_CODR Write-only 0x0038 Output Data Status Register PIO_ODSR Read-only or(2) Read/Write – 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only – 0x0044 Interrupt Disable Register PIO_IDR Write-only – 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 (4) 0x004C Interrupt Status Register PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only – 0x0054 Multi-driver Disable Register PIO_MDDR Write-only – 0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000 0x005C Reserved 0x0060 Pull-up Disable Register PIO_PUDR Write-only – 0x0064 Pull-up Enable Register PIO_PUER Write-only – 0x0068 Pad Pull-up Status Register PIO_PUSR Read-only 0x00000000 0x006C Reserved 0x0070 Peripheral A Select Register(5) PIO_ASR Write-only – 0x0074 Peripheral B Select Register (5) PIO_BSR Write-only – 0x0078 AB Status Register(5) PIO_ABSR Read-only 0x00000000  2017 Microchip Technology Inc. DS60001516A-page 355 SAM9G20 Table 28-2: Register Mapping (Continued) Offset Register 0x007C to 0x009C Reserved 0x00A0 Output Write Enable 0x00A4 Name Access Reset PIO_OWER Write-only – Output Write Disable PIO_OWDR Write-only – 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved Note 1: Reset value of PIO_PSR depends on the product implementation. 2: PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3: Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4: PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5: Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register. DS60001516A-page 356  2017 Microchip Technology Inc. SAM9G20 28.6.1 PIO Controller PIO Enable Register Name:PIO_PER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).  2017 Microchip Technology Inc. DS60001516A-page 357 SAM9G20 28.6.2 PIO Controller PIO Disable Register Name:PIO_PDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). DS60001516A-page 358  2017 Microchip Technology Inc. SAM9G20 28.6.3 PIO Controller PIO Status Register Name:PIO_PSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active). 1: PIO is active on the corresponding I/O line (peripheral is inactive).  2017 Microchip Technology Inc. DS60001516A-page 359 SAM9G20 28.6.4 PIO Controller Output Enable Register Name:PIO_OER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. DS60001516A-page 360  2017 Microchip Technology Inc. SAM9G20 28.6.5 PIO Controller Output Disable Register Name:PIO_ODR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Disable 0: No effect. 1: Disables the output on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 361 SAM9G20 28.6.6 PIO Controller Output Status Register Name:PIO_OSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. DS60001516A-page 362  2017 Microchip Technology Inc. SAM9G20 28.6.7 PIO Controller Input Filter Enable Register Name:PIO_IFER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 363 SAM9G20 28.6.8 PIO Controller Input Filter Disable Register Name:PIO_IFDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line. DS60001516A-page 364  2017 Microchip Technology Inc. SAM9G20 28.6.9 PIO Controller Input Filter Status Register Name:PIO_IFSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 365 SAM9G20 28.6.10 PIO Controller Set Output Data Register Name:PIO_SODR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. DS60001516A-page 366  2017 Microchip Technology Inc. SAM9G20 28.6.11 PIO Controller Clear Output Data Register Name:PIO_CODR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Set Output Data 0: No effect. 1: Clears the data to be driven on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 367 SAM9G20 28.6.12 PIO Controller Output Data Status Register Name:PIO_ODSR Access:Read-only or Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1. DS60001516A-page 368  2017 Microchip Technology Inc. SAM9G20 28.6.13 PIO Controller Pin Data Status Register Name:PIO_PDSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1.  2017 Microchip Technology Inc. DS60001516A-page 369 SAM9G20 28.6.14 PIO Controller Interrupt Enable Register Name:PIO_IER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Enable 0: No effect. 1: Enables the Input Change Interrupt on the I/O line. DS60001516A-page 370  2017 Microchip Technology Inc. SAM9G20 28.6.15 PIO Controller Interrupt Disable Register Name:PIO_IDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Disable 0: No effect. 1: Disables the Input Change Interrupt on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 371 SAM9G20 28.6.16 PIO Controller Interrupt Mask Register Name:PIO_IMR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Mask 0: Input Change Interrupt is disabled on the I/O line. 1: Input Change Interrupt is enabled on the I/O line. DS60001516A-page 372  2017 Microchip Technology Inc. SAM9G20 28.6.17 PIO Controller Interrupt Status Register Name:PIO_ISR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Status 0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.  2017 Microchip Technology Inc. DS60001516A-page 373 SAM9G20 28.6.18 PIO Multi-driver Enable Register Name:PIO_MDER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Multi Drive Enable 0: No effect. 1: Enables Multi Drive on the I/O line. DS60001516A-page 374  2017 Microchip Technology Inc. SAM9G20 28.6.19 PIO Multi-driver Disable Register Name:PIO_MDDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Multi Drive Disable 0: No effect. 1: Disables Multi Drive on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 375 SAM9G20 28.6.20 PIO Multi-driver Status Register Name:PIO_MDSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Multi Drive Status 0: The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1: The Multi Drive is enabled on the I/O line. The pin is driven at low level only. DS60001516A-page 376  2017 Microchip Technology Inc. SAM9G20 28.6.21 PIO Pull Up Disable Register Name:PIO_PUDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Pull Up Disable 0: No effect. 1: Disables the pull up resistor on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 377 SAM9G20 28.6.22 PIO Pull Up Enable Register Name:PIO_PUER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Pull Up Enable 0: No effect. 1: Enables the pull up resistor on the I/O line. DS60001516A-page 378  2017 Microchip Technology Inc. SAM9G20 28.6.23 PIO Pull Up Status Register Name:PIO_PUSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Pull Up Status 0: Pull Up resistor is enabled on the I/O line. 1: Pull Up resistor is disabled on the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 379 SAM9G20 28.6.24 PIO Peripheral A Select Register Name:PIO_ASR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Peripheral A Select 0: No effect. 1: Assigns the I/O line to the Peripheral A function. DS60001516A-page 380  2017 Microchip Technology Inc. SAM9G20 28.6.25 PIO Peripheral B Select Register Name:PIO_BSR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Peripheral B Select 0: No effect. 1: Assigns the I/O line to the peripheral B function.  2017 Microchip Technology Inc. DS60001516A-page 381 SAM9G20 28.6.26 PIO Peripheral A B Status Register Name:PIO_ABSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Peripheral A B Status 0: The I/O line is assigned to the Peripheral A. 1: The I/O line is assigned to the Peripheral B. DS60001516A-page 382  2017 Microchip Technology Inc. SAM9G20 28.6.27 PIO Output Write Enable Register Name:PIO_OWER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Write Enable 0: No effect. 1: Enables writing PIO_ODSR for the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 383 SAM9G20 28.6.28 PIO Output Write Disable Register Name:PIO_OWDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Write Disable 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. DS60001516A-page 384  2017 Microchip Technology Inc. SAM9G20 28.6.29 PIO Output Write Status Register Name:PIO_OWSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line.  2017 Microchip Technology Inc. DS60001516A-page 385 SAM9G20 29. Serial Peripheral Interface (SPI) 29.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. • Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. 29.2 Block Diagram Figure 29-1: Block Diagram PDC APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt DS60001516A-page 386  2017 Microchip Technology Inc. SAM9G20 29.3 Application Block Diagram Figure 29-2: Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 NC NPCS3 MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 29.4 Signal Description Table 29-1: Signal Description Type Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1–NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 29.5 29.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. 29.5.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. 29.5.3 Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI.  2017 Microchip Technology Inc. DS60001516A-page 387 SAM9G20 29.6 Functional Description 29.6.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode. 29.6.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 29-2 shows the four modes and corresponding parameter settings. Table 29-2: SPI Bus Protocol Mode SPI Mode CPOL NCPHA 0 0 1 1 0 0 2 1 1 3 1 0 Figure 29-3 and Figure 29-4 show examples of data transfers. Figure 29-3: SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. DS60001516A-page 388  2017 Microchip Technology Inc. SAM9G20 Figure 29-4: SPI Transfer Format (NCPHA = 0, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 5 8 7 6 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 29.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 29-5 shows a block diagram of the SPI when operating in Master Mode. Figure 29-6 shows a flow chart describing how transfers are handled.  2017 Microchip Technology Inc. DS60001516A-page 389 SAM9G20 29.6.3.1 Master Mode Block Diagram Figure 29-5: Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..3 SPI_RDR CSAAT PCS PS NPCS3 PCSDEC SPI_MR PCS 0 NPCS2 Current Peripheral NPCS1 SPI_TDR NPCS0 PCS 1 MSTR MODF NPCS0 MODFDIS DS60001516A-page 390  2017 Microchip Technology Inc. SAM9G20 29.6.3.2 Master Mode Flow Diagram Figure 29-6: Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 CSAAT ? PS ? 1 0 0 Fixed peripheral PS ? 1 Fixed peripheral 0 1 Variable peripheral Variable peripheral SPI_TDR(PCS) = NPCS ? no NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS) yes SPI_MR(PCS) = NPCS ? no NPCS = 0xF NPCS = 0xF Delay DLYBCS Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS), SPI_TDR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS  2017 Microchip Technology Inc. DS60001516A-page 391 SAM9G20 29.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 29.6.3.4 Transfer Delays Figure 29-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: • The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. • The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. • The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 29-7: Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS 29.6.3.5 DLYBS DLYBCT DLYBCT Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. DS60001516A-page 392  2017 Microchip Technology Inc. SAM9G20 29.6.3.6 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 29.6.3.7 Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. Figure 29-8: Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..3] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write SPI_TDR TDRE NPCS[0..3] DLYBCT DLYBCT B A B A DLYBCS PCS = B DLYBCS PCS = B Write SPI_TDR  2017 Microchip Technology Inc. DS60001516A-page 393 SAM9G20 29.6.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO controller, so that external pull up resistors are needed to guarantee high level. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until reenabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 29.6.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 29-9 shows a block diagram of the SPI when operating in Slave Mode. Figure 29-9: Slave Mode Functional Block Diagram SPCK NSS SPI Clock SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RDRF OVRES RD MSB Shift Register MISO SPI_TDR TD DS60001516A-page 394 TDRE  2017 Microchip Technology Inc. SAM9G20 29.7 Serial Peripheral Interface (SPI) User Interface Table 29-3: Register Mapping Offset Register Name Access Reset 0x00 Control Register SPI_CR Write-only --- 0x04 Mode Register SPI_MR Read/Write 0x0 0x08 Receive Data Register SPI_RDR Read-only 0x0 0x0C Transmit Data Register SPI_TDR Write-only --- 0x10 Status Register SPI_SR Read-only 0x000000F0 0x14 Interrupt Enable Register SPI_IER Write-only --- 0x18 Interrupt Disable Register SPI_IDR Write-only --- 0x1C Interrupt Mask Register SPI_IMR Read-only 0x0 Reserved – – – 0x30 Chip Select Register 0 SPI_CSR0 Read/Write 0x0 0x34 Chip Select Register 1 SPI_CSR1 Read/Write 0x0 0x38 Chip Select Register 2 SPI_CSR2 Read/Write 0x0 0x3C Chip Select Register 3 SPI_CSR3 Read/Write 0x0 Reserved – – – Reserved for the PDC – – – 0x20–0x2C 0x004C–0x00F8 0x100–0x124  2017 Microchip Technology Inc. DS60001516A-page 395 SAM9G20 29.7.1 SPI Control Register Name: SPI_CR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. SWRST: SPI Software Reset 0: No effect. 1: Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. PDC channels are not affected by software reset. LASTXFER: Last Transfer 0: No effect. 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. DS60001516A-page 396  2017 Microchip Technology Inc. SAM9G20 29.7.2 SPI Mode Register Name: SPI_MR Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 3 7 6 5 4 LLB – – MODFDIS PCS 2 1 0 PCSDEC PS MSTR MSTR: Master/Slave Mode 0: SPI is in Slave mode. 1: SPI is in Master mode. PS: Peripheral Select 0: Fixed Peripheral Select. 1: Variable Peripheral Select. PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14. MODFDIS: Mode Fault Detection 0: Mode fault detection is enabled. 1: Mode fault detection is disabled. LLB: Local Loopback Enable 0: Local loopback path disabled. 1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.)  2017 Microchip Technology Inc. DS60001516A-page 397 SAM9G20 PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: DLYBCS Delay Between Chip Selects = ----------------------MCK DS60001516A-page 398  2017 Microchip Technology Inc. SAM9G20 29.7.3 SPI Receive Data Register Name: SPI_RDR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.  2017 Microchip Technology Inc. DS60001516A-page 399 SAM9G20 29.7.4 SPI Transmit Data Register Name: SPI_TDR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS LASTXFER: Last Transfer 0: No effect. 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). DS60001516A-page 400  2017 Microchip Technology Inc. SAM9G20 29.7.5 SPI Status Register Name: SPI_SR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – SPIENS 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF RDRF: Receive Data Register Full 0: No data has been received since the last read of SPI_RDR 1: Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. TDRE: Transmit Data Register Empty 0: Data has been written to SPI_TDR and not yet transferred to the serializer. 1: The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. MODF: Mode Fault Error 0: No Mode Fault has been detected since the last read of SPI_SR. 1: A Mode Fault occurred since the last read of the SPI_SR. OVRES: Overrun Error Status 0: No overrun has been detected since the last read of SPI_SR. 1: An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. ENDRX: End of RX buffer 0: The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1: The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). ENDTX: End of TX buffer 0: The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1: The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). RXBUFF: RX Buffer Full 0: SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1: Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. TXBUFE: TX Buffer Empty 0: SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1: Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. NSSR: NSS Rising 0: No rising edge detected on NSS pin since last read. 1: A rising edge occurred on NSS pin since last read.  2017 Microchip Technology Inc. DS60001516A-page 401 SAM9G20 TXEMPTY: Transmission Registers Empty 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. SPIENS: SPI Enable Status 0: SPI is disabled. 1: SPI is enabled. Note 1: SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC. DS60001516A-page 402  2017 Microchip Technology Inc. SAM9G20 29.7.6 SPI Interrupt Enable Register Name: SPI_IER Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF RDRF: Receive Data Register Full Interrupt Enable TDRE: SPI Transmit Data Register Empty Interrupt Enable MODF: Mode Fault Error Interrupt Enable OVRES: Overrun Error Interrupt Enable ENDRX: End of Receive Buffer Interrupt Enable ENDTX: End of Transmit Buffer Interrupt Enable RXBUFF: Receive Buffer Full Interrupt Enable TXBUFE: Transmit Buffer Empty Interrupt Enable NSSR: NSS Rising Interrupt Enable TXEMPTY: Transmission Registers Empty Enable 0: No effect. 1: Enables the corresponding interrupt.  2017 Microchip Technology Inc. DS60001516A-page 403 SAM9G20 29.7.7 SPI Interrupt Disable Register Name: SPI_IDR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF RDRF: Receive Data Register Full Interrupt Disable TDRE: SPI Transmit Data Register Empty Interrupt Disable MODF: Mode Fault Error Interrupt Disable OVRES: Overrun Error Interrupt Disable ENDRX: End of Receive Buffer Interrupt Disable ENDTX: End of Transmit Buffer Interrupt Disable RXBUFF: Receive Buffer Full Interrupt Disable TXBUFE: Transmit Buffer Empty Interrupt Disable NSSR: NSS Rising Interrupt Disable TXEMPTY: Transmission Registers Empty Disable 0: No effect. 1: Disables the corresponding interrupt. DS60001516A-page 404  2017 Microchip Technology Inc. SAM9G20 29.7.8 SPI Interrupt Mask Register Name: SPI_IMR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 – – – – – 9 8 TXEMPTY NSSR 7 6 5 4 3 2 1 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF RDRF: Receive Data Register Full Interrupt Mask TDRE: SPI Transmit Data Register Empty Interrupt Mask MODF: Mode Fault Error Interrupt Mask OVRES: Overrun Error Interrupt Mask ENDRX: End of Receive Buffer Interrupt Mask ENDTX: End of Transmit Buffer Interrupt Mask RXBUFF: Receive Buffer Full Interrupt Mask TXBUFE: Transmit Buffer Empty Interrupt Mask NSSR: NSS Rising Interrupt Mask TXEMPTY: Transmission Registers Empty Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.  2017 Microchip Technology Inc. DS60001516A-page 405 SAM9G20 29.7.9 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 3 2 1 0 CSAAT – NCPHA CPOL CPOL: Clock Polarity 0: The inactive state value of SPCK is logic level zero. 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. NCPHA: Clock Phase 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. CSAAT: Chip Select Active After Transfer 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. DS60001516A-page 406 BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved  2017 Microchip Technology Inc. SAM9G20 BITS Bits Per Transfer 1101 Reserved 1110 Reserved 1111 Reserved SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = --------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBS Delay Before SPCK = ------------------MCK DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = -----------------------------------MCK  2017 Microchip Technology Inc. DS60001516A-page 407 SAM9G20 30. Two-wire Interface (TWI) 30.1 Overview The Microchip Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Microchip Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. The table below lists the compatibility level of the Microchip Two-wire Interface in Master Mode and a full I2C compatible device. Table 30-1: Microchip TWI compatibility with i2C Standard I2C Standard Microchip TWI Standard Mode Speed (100 kHz) Supported Fast Mode Speed (400 kHz) Supported 7 or 10 bits Slave Addressing Supported START BYTE(1) Not Supported Repeated Start (Sr) Condition Supported ACK and NACK Management Supported Slope control and input filtering (Fast mode) Not Supported Clock stretching Supported Note 1: START + b000000001 + Ack + SrQ 30.2 List of Abbreviations Table 30-2: Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write DS60001516A-page 408  2017 Microchip Technology Inc. SAM9G20 30.3 Block Diagram Figure 30-1: Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI Interrupt 30.4 AIC Application Block Diagram Figure 30-2: Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Microchip TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.4.1 I/O Lines Description Table 30-3: I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output  2017 Microchip Technology Inc. Type DS60001516A-page 409 SAM9G20 30.5 30.5.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 302). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: • Program the PIO controller to: - Dedicate TWD and TWCK as peripheral lines. - Define TWD and TWCK as open-drain. 30.5.2 Power Management • Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 30.5.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. 30.6 30.6.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 30-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 30-3). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 30-3: START and STOP Conditions TWD TWCK Start Figure 30-4: Stop Transfer Format TWD TWCK Start 30.6.2 Address R/W Ack Data Ack Data Ack Stop Modes of Operation The TWI has six modes of operations: • Master transmitter mode • Master receiver mode • Multi-master transmitter mode DS60001516A-page 410  2017 Microchip Technology Inc. SAM9G20 • Multi-master receiver mode • Slave transmitter mode • Slave receiver mode These modes are described in the following sections. 30.6.3 Master Mode 30.6.3.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 30.6.3.2 Application Block Diagram Figure 30-5: Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Microchip TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.6.3.3 Programming Master Mode The following registers have to be programmed before entering Master mode: 1. 2. 3. 4. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode. CKDIV + CHDIV + CLDIV: Clock Waveform. SVDIS: Disable the slave mode. MSEN: Enable the master mode. 30.6.3.4 Master Transmitter Mode After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR. When no more data is written into the TWI_THR, the master generates a stop condition to end the transfer. The end of the complete transfer is marked by the TWI_TXCOMP bit set to one. See Figure 30-6, Figure 30-7, and Figure 30-8. TXRDY is used as Transmit Ready for the PDC transmit channel.  2017 Microchip Technology Inc. DS60001516A-page 411 SAM9G20 Figure 30-6: Master Write with On Data Byte S TWD DADR W A DATA A P TXCOMP TXRDY STOP sent automaticaly (ACK received and TXRDY = 1) Write THR (DATA) Figure 30-7: Master Write with Multiple Data Byte S TWD DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Figure 30-8: TWD S Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) Master Write with One Byte Internal Address and Multiple Data Bytes DADR W A IADR(7:0) A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) 30.6.3.5 Write THR (Data n+1) Write THR (Data n+x) STOP sent automaticaly Last data sent (ACK received and TXRDY = 1) Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 309. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 30-9. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-to-last data received. See Figure 30-10. For Internal Address usage see Section 30.6.3.6 Internal Address. DS60001516A-page 412  2017 Microchip Technology Inc. SAM9G20 Figure 30-9: Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 30-10: TWD S Master Read with Multiple Data Bytes DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 30.6.3.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. • 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 30-12. See Figure 30-11 and Figure 30-13 for Master Write operation with internal address. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e., no internal address, IADRSZ must be set to 0. In the figures below the following abbreviations are used:  S Start  Sr Repeated Start  P Stop  W Write  R Read  A Acknowledge  N Not Acknowledge  DADR Device Address  IADR Internal Address  2017 Microchip Technology Inc. DS60001516A-page 413 SAM9G20 Figure 30-11: Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address S TWD DADR P One byte internal address S TWD DADR Figure 30-12: P Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR A W IADR(23:16) A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA N P Two bytes internal address S TWD DADR W A IADR(15:8) A IADR(7:0) A Sr W A IADR(7:0) A Sr R A DADR R A DATA N P One byte internal address TWD S DADR DADR DATA N P • 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. 2. 3. Program IADRSZ = 1, Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 30-13 below shows a byte write to a Microchip AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 30-13: Internal Address Usage S T A R T Device Address W R I T E FIRST WORD ADDRESS SECOND WORD ADDRESS S T O P DATA 0 M S B 30.6.3.7 LR A S / C BW K M S B A C K LA SC BK A C K Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences: • Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, size, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC end TX flag. 5. Disable the PDC by setting the PDC TXDIS bit. DS60001516A-page 414  2017 Microchip Technology Inc. SAM9G20 • Data Receive with the PDC 1. Initialize the receive PDC (memory pointers, size - 1, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC RXTEN bit. 4. Wait for the PDC end RX flag. 5. Disable the PDC by setting the PDC RXDIS bit. 30.6.3.8 Read/Write Flowcharts The flowcharts in the following figures provide examples of read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 30-14: TWI Write Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished  2017 Microchip Technology Inc. DS60001516A-page 415 SAM9G20 Figure 30-15: TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished DS60001516A-page 416  2017 Microchip Technology Inc. SAM9G20 Figure 30-16: TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send No TXRDY = 1? Yes Data to send? Yes Read Status register Yes No TXCOMP = 1? END  2017 Microchip Technology Inc. DS60001516A-page 417 SAM9G20 Figure 30-17: TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? No Yes Read Receive Holding Register Read Status register No TXCOMP = 1? Yes END DS60001516A-page 418  2017 Microchip Technology Inc. SAM9G20 Figure 30-18: TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END  2017 Microchip Technology Inc. DS60001516A-page 419 SAM9G20 Figure 30-19: TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? No Yes Read Receive Holding register (TWI_RHR) No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? No Yes END DS60001516A-page 420  2017 Microchip Technology Inc. SAM9G20 30.6.4 30.6.4.1 Multi-master Mode Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 30-21. 30.6.4.2 Different Multi-master Modes Two multi-master modes may be distinguished: 1. 2. TWI is considered as a Master only and will never be addressed. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported. • TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 30-20). Note: The state of the bus (busy or free) is not indicated in the user interface. • TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. 2. 3. 4. 5. 6. 7. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR.  2017 Microchip Technology Inc. DS60001516A-page 421 SAM9G20 Figure 30-20: Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Figure 30-21: Bus is considered as free Transfer is initiated Arbitration Cases TWCK TWD TWCK Data from a Master S 1 0 0 1 1 Data from TWI S 1 0 TWD S 1 0 0 1 P Arbitration is lost TWI stops sending data 1 1 Data from the master P Arbitration is lost S 1 0 1 S 1 0 0 1 1 S 1 0 0 1 1 The master stops sending data Data from the TWI ARBLST Bus is busy Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is free Transfer is stopped Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 30-22 gives an example of read and write operations in Multi-master mode. DS60001516A-page 422  2017 Microchip Technology Inc. SAM9G20 Figure 30-22: Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? Yes GACC = 1 ? No No SVREAD = 0 ? No No EOSACC = 1 ? TXRDY= 1 ? Yes Yes Yes No Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? Yes No No No Yes Read TWI_RHR Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence Prog seq OK ? No Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register Yes No ARBLST = 1 ? Yes Yes MREAD = 1 ? RXRDY= 0 ? No TXRDY= 0 ? No Read TWI_RHR Yes Yes No Data to read? Data to send ? No Yes Write in TWI_THR No Stop transfer Read Status Register Yes  2017 Microchip Technology Inc. TXCOMP = 0 ? No DS60001516A-page 423 SAM9G20 30.6.5 Slave Mode 30.6.5.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 30.6.5.2 Application Block Diagram Figure 30-23: Slave Mode Typical Application Block Diagram VDD R Master Host with TWI Interface 30.6.5.3 R TWD TWCK Host with TWI Interface Host with TWI Interface LCD Controller Slave 1 Slave 2 Slave 3 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. 2. 3. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. MSDIS (TWI_CR): Disable the master mode. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account. 30.6.5.4 Receiving Data After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set. • Read Sequence In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. Note that a STOP or a repeated START always follows a NACK. See Figure 30-24. • Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 30-25. • Clock Synchronization Sequence In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. DS60001516A-page 424  2017 Microchip Technology Inc. SAM9G20 Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 30-27 and Figure 30-28. • General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 30-26. 30.6.5.5 PDC As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in SLAVE mode. 30.6.5.6 Data Transfer • Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 30-24 describes the write operation. Figure 30-24: Read Access Ordered by a MASTER SADR matches, TWI answers with an ACK SADR does not match, TWI answers with a NACK TWD S ADR R NA DATA NA P/S/Sr SADR R A DATA A ACK/NACK from the Master A DATA NA S/Sr TXRDY NACK Read RHR Write THR SVACC SVREAD SVREAD has to be taken into account only while SVACC is active EOSVACC Note 1: When SVACC is low, the state of SVREAD becomes irrelevant. 2: TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. • Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 30-25 describes the Write operation.  2017 Microchip Technology Inc. DS60001516A-page 425 SAM9G20 Figure 30-25: Write Access Ordered by a Master SADR does not match, TWI answers with a NACK S TWD ADR W NA DATA NA SADR matches, TWI answers with an ACK P/S/Sr SADR W A DATA Read RHR A A DATA NA S/Sr RXRDY SVACC SVREAD has to be taken into account only while SVACC is active SVREAD EOSVACC Note 1: When SVACC is low, the state of SVREAD becomes irrelevant. 2: RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. • General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 30-26 describes the General Call access. Figure 30-26: Master Performs a General Call 0000000 + W TXD S GENERAL CALL RESET command = 00000110X WRITE command = 00000100X A Reset or write DADD A DATA1 A DATA2 A New SADR A P New SADR Programming sequence GCACC Reset after read SVACC Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. • Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 30-27 describes the clock synchronization in Read mode. DS60001516A-page 426  2017 Microchip Technology Inc. SAM9G20 Figure 30-27: Clock Synchronization in Read Mode TWI_THR S SADR DATA1 1 DATA0 R A DATA0 A DATA1 DATA2 A DATA2 XXXXXXX NA S 2 TWCK CLOCK is tied low by the TWI as long as THR is empty Write THR SCLWS TXRDY SVACC SVREAD As soon as a START is detected TXCOMP Ack or Nack from the master TWI_THR is transmitted to the shift register 1 The data is memorized in TWI_THR until a new value is written 2 The clock is stretched after the ACK, the state of TWD is undefined during clock stretching Note 1: TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 2: At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3: SCLWS is automatically set when the clock synchronization mechanism is started. Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 30-28 describes the clock synchronization in Read mode. Figure 30-28: Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 TWI_RHR A DATA1 A DATA0 is not read in the RHR DATA2 DATA1 NA S ADR DATA2 SCLWS SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD TXCOMP As soon as a START is detected Note 1: At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR.  2017 Microchip Technology Inc. DS60001516A-page 427 SAM9G20 2: SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. • Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 30-29 describes the repeated start + reversal from Read to Write mode. Figure 30-29: Repeated Start + Reversal from Read to Write Mode TWI_THR TWD DATA0 S SADR R A DATA0 DATA1 A DATA1 NA Sr SADR W A DATA2 TWI_RHR A DATA3 DATA2 A P DATA3 SVACC SVREAD TXRDY RXRDY EOSACC Cleared after read As soon as a START is detected TXCOMP Note 1: TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command.Figure 30-30 describes the repeated start + reversal from Write to Read mode. Figure 30-30: Repeated Start + Reversal from Write to Read Mode DATA2 TWI_THR TWD S SADR W A DATA0 TWI_RHR A DATA1 DATA0 A Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY Read TWI_RHR EOSACC TXCOMP Cleared after read As soon as a START is detected Note 1: In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2: TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. DS60001516A-page 428  2017 Microchip Technology Inc. SAM9G20 30.6.5.7 Read/Write Flowcharts The flowchart shown in Figure 30-31 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 30-31: Read/Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No EOSACC = 1 ? GACC = 1 ? No SVREAD = 0 ? No TXRDY= 1 ? No Write in TWI_THR No TXCOMP = 1 ? RXRDY= 0 ? No END Read TWI_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR  2017 Microchip Technology Inc. DS60001516A-page 429 SAM9G20 30.7 Two-wire Interface (TWI) User Interface Table 30-4: Register Mapping Offset Register Name Access Reset 0x00 Control Register TWI_CR Write-only – 0x04 Master Mode Register TWI_MMR Read/Write 0x00000000 0x08 Slave Mode Register TWI_SMR Read/Write 0x00000000 0x0C Internal Address Register TWI_IADR Read/Write 0x00000000 0x10 Clock Waveform Generator Register TWI_CWGR Read/Write 0x00000000 0x20 Status Register TWI_SR Read-only 0x0000F009 0x24 Interrupt Enable Register TWI_IER Write-only – 0x28 Interrupt Disable Register TWI_IDR Write-only – 0x2C Interrupt Mask Register TWI_IMR Read-only 0x00000000 0x30 Receive Holding Register TWI_RHR Read-only 0x00000000 0x34 Transmit Holding Register TWI_THR Write-only – 0x38–0xFC Reserved – – – 0x100–0x124 Reserved for the PDC – – – DS60001516A-page 430  2017 Microchip Technology Inc. SAM9G20 30.7.1 TWI Control Register Name: TWI_CR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). STOP: Send a STOP Condition 0: No effect. 1: STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. MSEN: TWI Master Mode Enabled 0: No effect. 1: If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. MSDIS: TWI Master Mode Disabled 0: No effect. 1: The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. SVEN: TWI Slave Mode Enabled 0: No effect. 1: If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling.  2017 Microchip Technology Inc. DS60001516A-page 431 SAM9G20 SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset. DS60001516A-page 432  2017 Microchip Technology Inc. SAM9G20 30.7.2 TWI Master Mode Register Name: TWI_MMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 DADR 18 17 16 15 – 14 – 13 – 12 MREAD 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 – 8 IADRSZ 0 – IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 No internal device address 0 1 One-byte internal device address 1 0 Two-byte internal device address 1 1 Three-byte internal device address MREAD: Master Read Direction 0: Master write direction. 1: Master read direction. DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.  2017 Microchip Technology Inc. DS60001516A-page 433 SAM9G20 30.7.3 TWI Slave Mode Register Name: TWI_SMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. DS60001516A-page 434  2017 Microchip Technology Inc. SAM9G20 30.7.4 TWI Internal Address Register Name: TWI_IADR Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.  2017 Microchip Technology Inc. DS60001516A-page 435 SAM9G20 30.7.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode. CLDIV: Clock Low Divider The SCL low period is defined as follows: T low = ( ( CLDIV × 2 CKDIV ) + 4 ) × T MCK CHDIV: Clock High Divider The SCL high period is defined as follows: T high = ( ( CHDIV × 2 CKDIV ) + 4 ) × T MCK CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. DS60001516A-page 436  2017 Microchip Technology Inc. SAM9G20 30.7.6 TWI Status Register Name: TWI_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame. 1: When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 30-7 and in Figure 30-10. TXCOMP used in Slave mode: 0: As soon as a Start is detected. 1: After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 30-27, Figure 30-28, Figure 30-29 and Figure 30-30. RXRDY: Receive Holding Register Ready (automatically set / reset) 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 30-10. RXRDY behavior in Slave mode can be seen in Figure 30-25, Figure 30-28, Figure 30-29 and Figure 30-30. TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR. 1: As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 30-8. TXRDY used in Slave mode: 0: As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 30-24, Figure 30-27, Figure 30-29 and Figure 30-30.  2017 Microchip Technology Inc. DS60001516A-page 437 SAM9G20 SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 30-24, Figure 30-25, Figure 30-29 and Figure 30-30. SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0: TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 30-24, Figure 30-25, Figure 30-29 and Figure 30-30. GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0: No General Call has been detected. 1: A General Call has been detected. After the detection of General Call, the programmer decoded the commands that follow and the programming sequence. GACC behavior can be seen in Figure 30-26. OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0: TWI_RHR has not been loaded while RXRDY was set 1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0: Each data byte has been correctly received by the far-end side TWI slave component. 1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. NACK used in Slave Read mode: 0: Each data byte has been correctly received by the Master. 1: In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 30-27 and Figure 30-28. DS60001516A-page 438  2017 Microchip Technology Inc. SAM9G20 EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0: A slave access is being performing. 1: The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 30-29 and Figure 30-30. ENDRX: End of RX buffer This bit is only used in Master mode. 0: The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR. 1: The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR. ENDTX: End of TX buffer This bit is only used in Master mode. 0: The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR. 1: The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR. RXBUFF: RX Buffer Full This bit is only used in Master mode. 0: TWI_RCR or TWI_RNCR have a value other than 0. 1: Both TWI_RCR and TWI_RNCR have a value of 0. TXBUFE: TX Buffer Empty This bit is only used in Master mode. 0: TWI_TCR or TWI_TNCR have a value other than 0. 1: Both TWI_TCR and TWI_TNCR have a value of 0.  2017 Microchip Technology Inc. DS60001516A-page 439 SAM9G20 30.7.7 TWI Interrupt Enable Register Name: TWI_IER Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP TXCOMP: Transmission Completed Interrupt Enable RXRDY: Receive Holding Register Ready Interrupt Enable TXRDY: Transmit Holding Register Ready Interrupt Enable SVACC: Slave Access Interrupt Enable GACC: General Call Access Interrupt Enable OVRE: Overrun Error Interrupt Enable NACK: Not Acknowledge Interrupt Enable ARBLST: Arbitration Lost Interrupt Enable SCL_WS: Clock Wait State Interrupt Enable EOSACC: End Of Slave Access Interrupt Enable ENDRX: End of Receive Buffer Interrupt Enable ENDTX: End of Transmit Buffer Interrupt Enable RXBUFF: Receive Buffer Full Interrupt Enable TXBUFE: Transmit Buffer Empty Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. DS60001516A-page 440  2017 Microchip Technology Inc. SAM9G20 30.7.8 TWI Interrupt Disable Register Name: TWI_IDR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP TXCOMP: Transmission Completed Interrupt Disable RXRDY: Receive Holding Register Ready Interrupt Disable TXRDY: Transmit Holding Register Ready Interrupt Disable SVACC: Slave Access Interrupt Disable GACC: General Call Access Interrupt Disable OVRE: Overrun Error Interrupt Disable NACK: Not Acknowledge Interrupt Disable ARBLST: Arbitration Lost Interrupt Disable SCL_WS: Clock Wait State Interrupt Disable EOSACC: End Of Slave Access Interrupt Disable ENDRX: End of Receive Buffer Interrupt Disable ENDTX: End of Transmit Buffer Interrupt Disable RXBUFF: Receive Buffer Full Interrupt Disable TXBUFE: Transmit Buffer Empty Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.  2017 Microchip Technology Inc. DS60001516A-page 441 SAM9G20 30.7.9 TWI Interrupt Mask Register Name: TWI_IMR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP TXCOMP: Transmission Completed Interrupt Mask RXRDY: Receive Holding Register Ready Interrupt Mask TXRDY: Transmit Holding Register Ready Interrupt Mask SVACC: Slave Access Interrupt Mask GACC: General Call Access Interrupt Mask OVRE: Overrun Error Interrupt Mask NACK: Not Acknowledge Interrupt Mask ARBLST: Arbitration Lost Interrupt Mask SCL_WS: Clock Wait State Interrupt Mask EOSACC: End Of Slave Access Interrupt Mask ENDRX: End of Receive Buffer Interrupt Mask ENDTX: End of Transmit Buffer Interrupt Mask RXBUFF: Receive Buffer Full Interrupt Mask TXBUFE: Transmit Buffer Empty Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. DS60001516A-page 442  2017 Microchip Technology Inc. SAM9G20 30.7.10 TWI Receive Holding Register Name: TWI_RHR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA RXDATA: Master or Slave Receive Holding Data  2017 Microchip Technology Inc. DS60001516A-page 443 SAM9G20 30.7.11 TWI Transmit Holding Register Name: TWI_THR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TXDATA TXDATA: Master or Slave Transmit Holding Data DS60001516A-page 444  2017 Microchip Technology Inc. SAM9G20 31. Universal Synchronous Asynchronous Receiver Transmitter (USART) 31.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 31.2 Block Diagram Figure 31-1: USART Block Diagram Peripheral DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC Modem Signals Control MCK DIV DSR DCD MCK/DIV RI SLCK Baud Rate Generator SCK User Interface APB  2017 Microchip Technology Inc. DS60001516A-page 445 SAM9G20 31.3 Application Block Diagram Figure 31-2: Application Block Diagram IrLAP PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrDA Driver USART RS232 Drivers RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers Modem PSTN 31.4 I/O Lines Description Table 31-1: I/O Line Description Name Description Type SCK Serial Clock I/O TXD Transmit Serial Data I/O RXD Receive Serial Data Input RI Ring Indicator Input Low DSR Data Set Ready Input Low DCD Data Carrier Detect Input Low DTR Data Terminal Ready Output Low CTS Clear to Send Input Low RTS Request to Send Output Low DS60001516A-page 446 Active Level  2017 Microchip Technology Inc. SAM9G20 31.5 31.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. All the pins of the modems may or may not be implemented on the USART. Only USART0 is fully equipped with all the modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART. 31.5.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 31.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.  2017 Microchip Technology Inc. DS60001516A-page 447 SAM9G20 31.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication - MSB- or LSB-first - 1, 1.5 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling receiver frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication • High-speed 5- to 9-bit full-duplex synchronous serial communication - MSB- or LSB-first - 1 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication • RS485 with driver control signal • ISO7816, T0 or T1 protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit • InfraRed IrDA Modulation and Demodulation • Test modes - Remote loopback, local loopback, automatic echo 31.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: • the Master Clock MCK • a division of the Master Clock, the divider being product dependent, but generally set to 8 • the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. DS60001516A-page 448  2017 Microchip Technology Inc. SAM9G20 Figure 31-3: Baud Rate Generator USCLKS CD MCK SCK 0 MCK/DIV SCK CD 1 Reserved 16-bit Counter 2 FIDI >1 3 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 31.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over )CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. 31.6.1.2 Baud Rate Calculation Example Table 31-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 31-2: Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00%  2017 Microchip Technology Inc. DS60001516A-page 449 SAM9G20 Table 31-2: Baud Rate Example (OVER = 0) (Continued) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% The baud rate is calculated with the following formula: BaudRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 –  ---------------------------------------------------  ActualBaudRate  31.6.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 – Over )  CD + FP -------    8  The modified architecture is presented in Figure 31-4. Figure 31-4: Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 2 3 16-bit Counter glitch-free logic 1 0 FIDI >1 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 DS60001516A-page 450 Sampling Clock  2017 Microchip Technology Inc. SAM9G20 31.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. SelectedClock BaudRate = -------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 31.6.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where: • • • • B is the bit rate Di is the bit-rate adjustment factor Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 31-3. Table 31-3: Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 31-4. Table 31-4: Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 31-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 31-5: Possible Values for the Fi/Di Ratio Fi/Di 372 558 744 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR.  2017 Microchip Technology Inc. DS60001516A-page 451 SAM9G20 This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 31-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 31-5: Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 31.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. 31.6.3 31.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. DS60001516A-page 452  2017 Microchip Technology Inc. SAM9G20 Figure 31-6: Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 31-7: Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 31.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 31-8 illustrates this coding scheme. Figure 31-8: NRZ to Manchester Encoding NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1 Txd The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 31-9 illustrates and defines the valid patterns. To improve flexi-  2017 Microchip Technology Inc. DS60001516A-page 453 SAM9G20 bility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. Figure 31-9: Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 31-10 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the US_MR is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR. The USART character format is modified and includes sync information. DS60001516A-page 454  2017 Microchip Technology Inc. SAM9G20 Figure 31-10: Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter 31.6.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. Figure 31-11: Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error 31.6.3.4 Synchro. Jump Tolerance Sync Jump Synchro. Error Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.  2017 Microchip Technology Inc. DS60001516A-page 455 SAM9G20 The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 31-12 and Figure 31-13 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 31-12: Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 Figure 31-13: 2 3 4 5 6 7 0 1 Start Rejection Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 31.6.3.5 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Manchester Decoder When the MAN field in US_MR is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 31-9 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 31-14.. The sample pulse rejection mechanism applies. DS60001516A-page 456  2017 Microchip Technology Inc. SAM9G20 Figure 31-14: Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 31-15 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANERR flag in US_CSR is raised. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 31-16 for an example of Manchester error detection during data phase. Figure 31-15: Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Manchester encoded data Preamble Mismatch invalid pattern SFD Txd DATA Preamble Length is set to 8 Figure 31-16: Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-to-one transition.  2017 Microchip Technology Inc. DS60001516A-page 457 SAM9G20 31.6.3.6 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 31-17. Figure 31-17: Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line Manchester decoder USART Receiver Manchester encoder USART Emitter ASK/FSK downstream transmitter Downstream Receiver PA RF filter Mod VCO control The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 31-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 31-19. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 31-18: ASK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 DS60001516A-page 458  2017 Microchip Technology Inc. SAM9G20 Figure 31-19: FSK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 31.6.3.7 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 31-20 illustrates a character reception in synchronous mode. Figure 31-20: Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 31.6.3.8 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.  2017 Microchip Technology Inc. DS60001516A-page 459 SAM9G20 Figure 31-21: Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 31.6.3.9 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see Section 31.6.3.10 Multidrop Mode. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 31-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 31-6: Parity Bit Examples Character Hexa Binary Parity Bit Parity Mode A 0x41 0100 0001 1 Odd A 0x41 0100 0001 0 Even A 0x41 0100 0001 1 Mark A 0x41 0100 0001 0 Space A 0x41 0100 0001 None None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 31-22 illustrates the parity bit status setting and clearing. DS60001516A-page 460  2017 Microchip Technology Inc. SAM9G20 Figure 31-22: Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 31.6.3.10 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 31.6.3.11 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 31-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted.  2017 Microchip Technology Inc. DS60001516A-page 461 SAM9G20 Figure 31-23: Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 31-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. Table 31-7: 31.6.3.12 Maximum Timeguard Length Depending on Baud Rate Baud Rate (bit/s) Bit Time (µs) Timeguard (ms) 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. DS60001516A-page 462  2017 Microchip Technology Inc. SAM9G20 If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 31-24 shows the block diagram of the Receiver Time-out feature. Figure 31-24: Receiver Time-out Block Diagram TO Baud Rate Clock 1 D Q Clock 16-bit Time-out Counter 16-bit Value = STTTO Character Received Load Clear TIMEOUT 0 RETTO Table 31-8 gives the maximum time-out period for some standard baud rates. Table 31-8: 31.6.3.13 Maximum Time-out Period Baud Rate (bit/s) Bit Time (µs) Time-out (ms) 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.  2017 Microchip Technology Inc. DS60001516A-page 463 SAM9G20 Figure 31-25: Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 31.6.3.14 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 31-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 31-26: Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 STTBRK = 1 D6 D7 Parity Stop Bit Bit Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY DS60001516A-page 464  2017 Microchip Technology Inc. SAM9G20 31.6.3.15 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 31.6.3.16 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 31-27. Figure 31-27: Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 31-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 31-28: Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 31-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 31-29: Transmitter Behavior when Operating with Hardware Handshaking CTS TXD  2017 Microchip Technology Inc. DS60001516A-page 465 SAM9G20 31.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 31.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see Section 31.6.1 Baud Rate Generator). The USART connects to a smart card as shown in Figure 31-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 31-30: Connection of a Smart Card to the USART USART CLK SCK I/O TXD Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to Section 31.7.2 USART Mode Register and Section PAR: Parity Type. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 31.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 31-31. If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 31-32. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 31-31: T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit DS60001516A-page 466 D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit  2017 Microchip Technology Inc. SAM9G20 Figure 31-32: T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 31.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. 31.6.4.4 Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 31.6.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. 31.6.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. 31.6.4.7 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). 31.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 31-33. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated.  2017 Microchip Technology Inc. DS60001516A-page 467 SAM9G20 Figure 31-33: Connection to IrDA Transceivers USART IrDA Transceivers Receiver Demodulator RXD Transmitter Modulator TXD RX TX The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX • Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). • Receive data 31.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 31-9. Table 31-9: IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 µs 9.6 Kb/s 19.53 µs 19.2 Kb/s 9.77 µs 38.4 Kb/s 4.88 µs 57.6 Kb/s 3.26 µs 115.2 Kb/s 1.63 µs Figure 31-34 shows an example of character transmission. Figure 31-34: IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 1 0 1 0 0 1 1 0 1 TXD Bit Period DS60001516A-page 468 3 16 Bit Period  2017 Microchip Technology Inc. SAM9G20 31.6.5.2 IrDA Baud Rate Table 31-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 31-10: IrDA Baud Rate Error Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 31.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 31-35 illustrates the operations of the IrDA demodulator.  2017 Microchip Technology Inc. DS60001516A-page 469 SAM9G20 Figure 31-35: IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 5 4 3 Pulse Rejected 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 31.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 31-36. Figure 31-36: Typical Connection to a RS485 Bus USART RXD TXD Differential Bus RTS The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 31-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. DS60001516A-page 470  2017 Microchip Technology Inc. SAM9G20 Figure 31-37: Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 31.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 31-11 gives the correspondence of the USART signals with modem connection standards. Table 31-11: Circuit References USART Pin V24 CCITT Direction TXD 2 103 From terminal to modem RTS 4 105 From terminal to modem DTR 20 108.2 From terminal to modem RXD 3 104 From modem to terminal CTS 5 106 From terminal to modem DSR 6 107 From terminal to modem DCD 8 109 From terminal to modem RI 22 125 From terminal to modem The control of the DTR output pin is performed by writing the Control Register (US_CR) with the DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode. The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled.  2017 Microchip Technology Inc. DS60001516A-page 471 SAM9G20 31.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 31.6.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 31-38: Normal Mode Configuration RXD Receiver TXD Transmitter 31.6.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 31-39. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 31-39: Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 31.6.8.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 31-40. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 31-40: Local Loopback Mode Configuration RXD Receiver Transmitter 31.6.8.4 1 TXD Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 31-41. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. DS60001516A-page 472  2017 Microchip Technology Inc. SAM9G20 Figure 31-41: Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter  2017 Microchip Technology Inc. DS60001516A-page 473 SAM9G20 31.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 31-12: Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read/Write – 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only – 0x0010 Interrupt Mask Register US_IMR Read-only 0x0 0x0014 Channel Status Register US_CSR Read-only – 0x0018 Receiver Holding Register US_RHR Read-only 0x0 0x001C Transmitter Holding Register US_THR Write-only – 0x0020 Baud Rate Generator Register US_BRGR Read/Write 0x0 0x0024 Receiver Time-out Register US_RTOR Read/Write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read/Write 0x0 Reserved – – – 0x0040 FI DI Ratio Register US_FIDI Read/Write 0x174 0x0044 Number of Errors Register US_NER Read-only – 0x0048 Reserved – – – 0x004C IrDA Filter Register US_IF Read/Write 0x0 0x0050 Manchester Encoder Decoder Register US_MAN Read/Write 0x30011004 Reserved – – – Reserved for PDC Registers – – – 0x2C–0x3C 0x5C–0xFC 0x100–0x128 DS60001516A-page 474  2017 Microchip Technology Inc. SAM9G20 31.7.1 USART Control Register Name:US_CR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.  2017 Microchip Technology Inc. DS60001516A-page 475 SAM9G20 STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. RETTO: Rearm Time-out 0: No effect 1: Restart Time-out DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. DS60001516A-page 476  2017 Microchip Technology Inc. SAM9G20 31.7.2 USART Mode Register Name:US_MR Access:Read/Write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 – 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 15 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE USART_MODE USART_MODE Mode of the USART 0 0 0 0 Normal 0 0 0 1 RS485 0 0 1 0 Hardware Handshaking 0 0 1 1 Modem 0 1 0 0 IS07816 Protocol: T = 0 0 1 1 0 IS07816 Protocol: T = 1 1 0 0 0 IrDA Others Reserved USCLKS: Clock Selection USCLKS Selected Clock 0 0 MCK 0 1 MCK/DIV (DIV = 8) 1 0 Reserved 1 1 SCK CHRL: Character Length. CHRL Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode.  2017 Microchip Technology Inc. DS60001516A-page 477 SAM9G20 PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode NBSTOP: Number of Stop Bits NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved CHMODE: Channel Mode CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo. Receiver input is connected to the TXD pin. 1 0 Local Loopback. Transmitter output is connected to the Receiver Input.. 1 1 Remote Loopback. RXD pin is internally connected to the TXD pin. MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. DS60001516A-page 478  2017 Microchip Technology Inc. SAM9G20 DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into US_THR. MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T = 0. FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit.  2017 Microchip Technology Inc. DS60001516A-page 479 SAM9G20 31.7.3 USART Interrupt Enable Register Name: US_IER Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY RXRDY: RXRDY Interrupt Enable TXRDY: TXRDY Interrupt Enable RXBRK: Receiver Break Interrupt Enable ENDRX: End of Receive Transfer Interrupt Enable ENDTX: End of Transmit Interrupt Enable OVRE: Overrun Error Interrupt Enable FRAME: Framing Error Interrupt Enable PARE: Parity Error Interrupt Enable TIMEOUT: Time-out Interrupt Enable TXEMPTY: TXEMPTY Interrupt Enable ITER: Iteration Interrupt Enable TXBUFE: Buffer Empty Interrupt Enable RXBUFF: Buffer Full Interrupt Enable NACK: Non Acknowledge Interrupt Enable RIIC: Ring Indicator Input Change Enable DSRIC: Data Set Ready Input Change Enable DCDIC: Data Carrier Detect Input Change Interrupt Enable CTSIC: Clear to Send Input Change Interrupt Enable MANE: Manchester Error Interrupt Enable DS60001516A-page 480  2017 Microchip Technology Inc. SAM9G20 31.7.4 USART Interrupt Disable Register Name:US_IDR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY RXRDY: RXRDY Interrupt Disable TXRDY: TXRDY Interrupt Disable RXBRK: Receiver Break Interrupt Disable ENDRX: End of Receive Transfer Interrupt Disable ENDTX: End of Transmit Interrupt Disable OVRE: Overrun Error Interrupt Disable FRAME: Framing Error Interrupt Disable PARE: Parity Error Interrupt Disable TIMEOUT: Time-out Interrupt Disable TXEMPTY: TXEMPTY Interrupt Disable ITER: Iteration Interrupt Enable TXBUFE: Buffer Empty Interrupt Disable RXBUFF: Buffer Full Interrupt Disable NACK: Non Acknowledge Interrupt Disable RIIC: Ring Indicator Input Change Disable DSRIC: Data Set Ready Input Change Disable DCDIC: Data Carrier Detect Input Change Interrupt Disable CTSIC: Clear to Send Input Change Interrupt Disable MANE: Manchester Error Interrupt Disable  2017 Microchip Technology Inc. DS60001516A-page 481 SAM9G20 31.7.5 USART Interrupt Mask Register Name:US_IMR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 MANE 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY RXRDY: RXRDY Interrupt Mask TXRDY: TXRDY Interrupt Mask RXBRK: Receiver Break Interrupt Mask ENDRX: End of Receive Transfer Interrupt Mask ENDTX: End of Transmit Interrupt Mask OVRE: Overrun Error Interrupt Mask FRAME: Framing Error Interrupt Mask PARE: Parity Error Interrupt Mask TIMEOUT: Time-out Interrupt Mask TXEMPTY: TXEMPTY Interrupt Mask ITER: Iteration Interrupt Enable TXBUFE: Buffer Empty Interrupt Mask RXBUFF: Buffer Full Interrupt Mask NACK: Non Acknowledge Interrupt Mask RIIC: Ring Indicator Input Change Mask DSRIC: Data Set Ready Input Change Mask DCDIC: Data Carrier Detect Input Change Interrupt Mask CTSIC: Clear to Send Input Change Interrupt Mask MANE: Manchester Error Interrupt Mask DS60001516A-page 482  2017 Microchip Technology Inc. SAM9G20 31.7.6 USART Channel Status Register Name:US_CSR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).  2017 Microchip Technology Inc. DS60001516A-page 483 SAM9G20 TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. DS60001516A-page 484  2017 Microchip Technology Inc. SAM9G20 MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA.  2017 Microchip Technology Inc. DS60001516A-page 485 SAM9G20 31.7.7 USART Receive Holding Register Name:US_RHR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last character received if RXRDY is set. RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. DS60001516A-page 486  2017 Microchip Technology Inc. SAM9G20 31.7.8 USART Transmit Holding Register Name:US_THR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.  2017 Microchip Technology Inc. DS60001516A-page 487 SAM9G20 31.7.9 USART Baud Rate Generator Register Name:US_BRGR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 OVER = 0 CD SYNC = 1 OVER = 1 0 1–65535 USART_MODE = ISO7816 Baud Rate Clock Disabled Baud Rate = Baud Rate = Baud Rate = Selected Clock/16/CD Selected Clock/8/CD Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO FP: Fractional Part 0: Fractional divider is disabled. 1–7: Baudrate resolution, defined by FP x 1/8. DS60001516A-page 488  2017 Microchip Technology Inc. SAM9G20 31.7.10 USART Receiver Time-out Register Name:US_RTOR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO TO: Time-out Value 0: The Receiver Time-out is disabled. 1–65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.  2017 Microchip Technology Inc. DS60001516A-page 489 SAM9G20 31.7.11 USART Transmitter Timeguard Register Name:US_TTGR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1–255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. DS60001516A-page 490  2017 Microchip Technology Inc. SAM9G20 31.7.12 USART FI DI RATIO Register Name:US_FIDI Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1–2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.  2017 Microchip Technology Inc. DS60001516A-page 491 SAM9G20 31.7.13 USART Number of Errors Register Name:US_NER Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. DS60001516A-page 492  2017 Microchip Technology Inc. SAM9G20 31.7.14 USART IrDA FILTER Register Name:US_IF Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.  2017 Microchip Technology Inc. DS60001516A-page 493 SAM9G20 31.7.15 USART Manchester Configuration Register Name:US_MAN Access:Read/Write 31 – 30 DRIFT 29 1 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 17 16 RX_PL 8 TX_PP 0 TX_PL TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1–15: The Preamble Length is TX_PL x Bit Period TX_PP: Transmitter Preamble Pattern TX_PP Preamble Pattern default polarity assumed (TX_MPOL field not set) 0 0 ALL_ONE 0 1 ALL_ZERO 1 0 ZERO_ONE 1 1 ONE_ZERO TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1–15: The detected preamble length is RX_PL x Bit Period RX_PP: Receiver Preamble Pattern detected RX_PP Preamble Pattern default polarity assumed (RX_MPOL field not set) 0 0 ALL_ONE 0 1 ALL_ZERO 1 0 ZERO_ONE 1 1 ONE_ZERO RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. DS60001516A-page 494  2017 Microchip Technology Inc. SAM9G20 DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.  2017 Microchip Technology Inc. DS60001516A-page 495 SAM9G20 32. Synchronous Serial Controller (SSC) 32.1 Overview The Microchip Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: • CODECs in master or slave mode • DAC through dedicated serial interface, particularly I2S • Magnetic card reader 32.2 Block Diagram Figure 32-1: Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK PMC TD MCK SSC Interface PIO RF RK Interrupt Control RD SSC Interrupt DS60001516A-page 496  2017 Microchip Technology Inc. SAM9G20 32.3 Application Block Diagram Figure 32-2: Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 32.4 Codec Time Slot Management Frame Management Line Interface Pin Name List Table 32-1: I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 32.5 32.5.1 Type Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. 32.5.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. 32.5.3 Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. 32.6 Functional Description This section contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2.  2017 Microchip Technology Inc. DS60001516A-page 497 SAM9G20 Figure 32-3: SSC Functional Block Diagram Transmitter MCK TK Input Clock Divider Transmit Clock Controller RX clock TF RF Start Selector TX clock Clock Output Controller TK Frame Sync Controller TF Transmit Shift Register TX PDC Transmit Holding Register APB TD Transmit Sync Holding Register Load Shift User Interface Receiver RK Input Receive Clock RX Clock Controller TX Clock RF TF Start Selector Interrupt Control RK Frame Sync Controller RF Receive Shift Register RX PDC PDC Clock Output Controller Receive Holding Register RD Receive Sync Holding Register Load Shift AIC 32.6.1 Clock Management The transmitter clock can be generated by: • an external clock received on the TK I/O pad • the receiver clock • the internal clock divider The receiver clock can be generated by: • an external clock received on the RK I/O pad • the transmitter clock • the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. DS60001516A-page 498  2017 Microchip Technology Inc. SAM9G20 32.6.1.1 Clock Divider Figure 32-4: Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 32-5: Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 32.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results.  2017 Microchip Technology Inc. DS60001516A-page 499 SAM9G20 Figure 32-6: Transmitter Clock Management TK (pin) Clock Output Tri-state Controller MUX Receiver Clock Divider Clock Data Transfer CKO CKS 32.6.1.3 INV MUX Tri-state Controller CKI CKG Transmitter Clock Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. Figure 32-7: Receiver Clock Management RK (pin) Tri-state Controller MUX Clock Output Transmitter Clock Divider Clock Data Transfer CKO CKS 32.6.1.4 INV MUX Tri-state Controller CKI CKG Receiver Clock Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: - Master Clock divided by 2 if Receiver Frame Synchro is input - Master Clock divided by 3 if Receiver Frame Synchro is output DS60001516A-page 500  2017 Microchip Technology Inc. SAM9G20 In addition, the maximum clock speed allowed on the TK pin is: - Master Clock divided by 6 if Transmit Frame Synchro is input - Master Clock divided by 2 if Transmit Frame Synchro is output 32.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See Section 32.6.4 Start. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See Section 32.6.5 Frame Sync. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 32-8: Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN 32.6.3 TD 0 SSC_TFMR.MSBF Start Selector SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB 0 SSC_THR 1 SSC_TSHR SSC_TFMR.FSLEN Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See Section 32.6.4 Start. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See Section 32.6.5 Frame Sync. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR.  2017 Microchip Technology Inc. DS60001516A-page 501 SAM9G20 Figure 32-9: Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF Start Selector SSC_RFMR.MSBF SSC_RFMR.DATNB Receive Shift Register SSC_RSHR SSC_RHR SSC_RFMR.FSLEN SSC_RFMR.DATLEN RD SSC_RCMR.STTDLY 32.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. • Synchronously with the transmitter/receiver • On detection of a falling/rising edge on TF/RF • On detection of a low level/high level on TF/RF • On detection of a level change or an edge on TF/RF A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). DS60001516A-page 502  2017 Microchip Technology Inc. SAM9G20 Figure 32-10: Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO B1 STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) BO X B1 BO B1 STTDLY TD (Output) X B1 BO BO B1 STTDLY Figure 32-11: Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF Start = Falling Edge on RF Start = High Level on RF Start = Rising Edge on RF Start = Level Change on RF Start = Any Edge on RF RD (Input) RD (Input) X BO STTDLY BO X B1 STTDLY BO X RD (Input) B1 STTDLY RD (Input) BO X B1 STTDLY RD (Input) RD (Input) B1 BO X B1 BO B1 STTDLY X BO B1 BO B1 STTDLY  2017 Microchip Technology Inc. DS60001516A-page 503 SAM9G20 32.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 256 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 32.6.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 32.6.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). 32.6.6 Receive Compare Modes Figure 32-12: Receive Compare Modes RK RD (Input) CMP0 CMP1 CMP2 CMP3 Ignored B0 B1 B2 Start FSLEN Up to 16 Bits (4 in This Example) 32.6.6.1 STDLY DATLEN Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. DS60001516A-page 504  2017 Microchip Technology Inc. SAM9G20 32.6.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: • • • • • • the event that starts the data transfer (START) the delay in number of bit periods between the start event and the first data bit (STTDLY) the length of the data (DATLEN) the number of data to be transferred for each start event (DATNB). the length of synchronization transferred for each start event (FSLEN) the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. Table 32-2: Data Frame Registers Transmitter Receiver Field Length Comment SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame SSC_TFMR SSC_RFMR MSBF SSC_TFMR SSC_RFMR FSLEN Up to 16 Size of Synchro data register SSC_TFMR DATDEF 0 or 1 Data default value ended SSC_TFMR FSDEN Most significant bit first Enable send SSC_TSHR SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit start delay Figure 32-13: Transmit and Receive Frame Format in Edge/Pulse Start Modes Start Start PERIOD TF/RF (1) FSLEN TD (If FSDEN = 1) Sync Data Default From SSC_TSHR FromDATDEF TD (If FSDEN = 0) RD Default Data From SSC_THR Ignored To SSC_RSHR STTDLY From SSC_THR Default From SSC_THR Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN Sync Data FromDATDEF Data Data From DATDEF Sync Data Data From SSC_THR Default From DATDEF Ignored Sync Data DATNB Note 1: Example of input on falling edge of TF/RF.  2017 Microchip Technology Inc. DS60001516A-page 505 SAM9G20 Figure 32-14: Transmit Frame Format in Continuous Mode Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note 1: STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 32-15: Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN Note 1: STTDLY is set to 0. 32.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 32.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. DS60001516A-page 506  2017 Microchip Technology Inc. SAM9G20 Figure 32-16: Interrupt Block Diagram SSC_IMR SSC_IER PDC SSC_IDR Set Clear TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC Interrupt Control RXBUFF ENDRX SSC Interrupt Receiver RXRDY OVRUN RXSYNC 32.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 32-17: Audio Application Block Diagram Clock SCK TK Word Select WS TF I2S RECEIVER Data SD SSC TD RD Clock SCK RF Word Select WS RK Data SD MSB LSB Left Channel  2017 Microchip Technology Inc. MSB Right Channel DS60001516A-page 507 SAM9G20 Figure 32-18: Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF CODEC Serial Data Out TD SSC Serial Data In RD RF RK Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Dend Serial Data Out Serial Data In Figure 32-19: Time Slot Application Block Diagram SCLK TK FSYNC TF CODEC First Time Slot Data Out TD SSC RD Data in RF RK CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Second Time Slot Dend Serial Data Out Serial Data in DS60001516A-page 508  2017 Microchip Technology Inc. SAM9G20 32.8 Syncrhronous Serial Controller (SSC) User Interface Table 32-3: Register Mapping Offset Register Name Access Reset 0x0 Control Register SSC_CR Write – 0x4 Clock Mode Register SSC_CMR Read/Write 0x0 0x8 Reserved – – – 0xC Reserved – – – 0x10 Receive Clock Mode Register SSC_RCMR Read/Write 0x0 0x14 Receive Frame Mode Register SSC_RFMR Read/Write 0x0 0x18 Transmit Clock Mode Register SSC_TCMR Read/Write 0x0 0x1C Transmit Frame Mode Register SSC_TFMR Read/Write 0x0 0x20 Receive Holding Register SSC_RHR Read 0x0 0x24 Transmit Holding Register SSC_THR Write – 0x28 Reserved – – – 0x2C Reserved – – – 0x30 Receive Sync. Holding Register SSC_RSHR Read 0x0 0x34 Transmit Sync. Holding Register SSC_TSHR Read/Write 0x0 0x38 Receive Compare 0 Register SSC_RC0R Read/Write 0x0 0x3C Receive Compare 1 Register SSC_RC1R Read/Write 0x0 0x40 Status Register SSC_SR Read 0x000000CC 0x44 Interrupt Enable Register SSC_IER Write – 0x48 Interrupt Disable Register SSC_IDR Write – 0x4C Interrupt Mask Register SSC_IMR Read 0x0 0x50–0xFC Reserved – – – 0x100–0x124 Reserved for Peripheral Data Controller (PDC) – – –  2017 Microchip Technology Inc. DS60001516A-page 509 SAM9G20 32.8.1 SSC Control Register Name:SSC_CR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception. TXEN: Transmit Enable 0: No effect. 1: Enables Transmit if TXDIS is not set. TXDIS: Transmit Disable 0: No effect. 1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR. DS60001516A-page 510  2017 Microchip Technology Inc. SAM9G20 32.8.2 SSC Clock Mode Register Name:SSC_CMR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.  2017 Microchip Technology Inc. DS60001516A-page 511 SAM9G20 32.8.3 SSC Receive Clock Mode Register Name:SSC_RCMR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 STOP 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS CKS: Receive Clock Selection CKS Selected Receive Clock 0x0 Divided Clock 0x1 TK Clock signal 0x2 RK pin 0x3 Reserved CKO: Receive Clock Output Mode Selection CKO Receive Clock Output Mode 0x0 None 0x1 Continuous Receive Clock Output 0x2 Receive Clock only during data transfers Output 0x3–0x7 RK pin Input-only Reserved CKI: Receive Clock Inversion 0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. CKG: Receive Clock Gating Selection CKG Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved DS60001516A-page 512  2017 Microchip Technology Inc. SAM9G20 START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 Transmit start 0x2 Detection of a low level on RF signal 0x3 Detection of a high level on RF signal 0x4 Detection of a falling edge on RF signal 0x5 Detection of a rising edge on RF signal 0x6 Detection of any level change on RF signal 0x7 Detection of any edge on RF signal 0x8 Compare 0 0x9–0xF Reserved STOP: Receive Stop Selection 0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.  2017 Microchip Technology Inc. DS60001516A-page 513 SAM9G20 32.8.4 SSC Receive Frame Mode Register Name:SSC_RFMR Access:Read/Write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT 28 FSLEN_EXT 27 – 26 – 23 – 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods. FSOS: Receive Frame Sync Output Selection FSOS Selected Receive Frame Sync Signal RF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 DS60001516A-page 514 Reserved Input-only Undefined  2017 Microchip Technology Inc. SAM9G20 FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSEDGE Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description above.  2017 Microchip Technology Inc. DS60001516A-page 515 SAM9G20 32.8.5 SSC Transmit Clock Mode Register Name:SSC_TCMR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 1 0 PERIOD 23 22 21 20 STTDLY 15 – 14 – 13 – 12 – 11 7 6 5 CKI 4 3 CKO CKG START 2 CKS CKS: Transmit Clock Selection CKS Selected Transmit Clock 0x0 Divided Clock 0x1 RK Clock signal 0x2 TK Pin 0x3 Reserved CKO: Transmit Clock Output Mode Selection CKO Transmit Clock Output Mode TK pin 0x0 None 0x1 Continuous Transmit Clock Output 0x2 Transmit Clock only during data transfers Output 0x3–0x7 Input-only Reserved CKI: Transmit Clock Inversion 0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. CKG: Transmit Clock Gating Selection CKG Transmit Clock Gating 0x0 None, continuous clock 0x1 Transmit Clock enabled only if TF Low 0x2 Transmit Clock enabled only if TF High 0x3 Reserved DS60001516A-page 516  2017 Microchip Technology Inc. SAM9G20 START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 Receive start 0x2 Detection of a low level on TF signal 0x3 Detection of a high level on TF signal 0x4 Detection of a falling edge on TF signal 0x5 Detection of a rising edge on TF signal 0x6 Detection of any level change on TF signal 0x7 Detection of any edge on TF signal 0x8–0xF Reserved STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.  2017 Microchip Technology Inc. DS60001516A-page 517 SAM9G20 32.8.6 SSC Transmit Frame Mode Register Name:SSC_TFMR Access:Read/Write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT 28 FSLEN_EXT 27 – 26 – 23 FSDEN 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock periods. DS60001516A-page 518  2017 Microchip Technology Inc. SAM9G20 FSOS: Transmit Frame Sync Output Selection FSOS Selected Transmit Frame Sync Signal TF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 Reserved Input-only Undefined FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). FSEDGE Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description above.  2017 Microchip Technology Inc. DS60001516A-page 519 SAM9G20 32.8.7 SSC Receive Holding Register Name:SSC_RHR Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. DS60001516A-page 520  2017 Microchip Technology Inc. SAM9G20 32.8.8 SSC Transmit Holding Register Name:SSC_THR Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.  2017 Microchip Technology Inc. DS60001516A-page 521 SAM9G20 32.8.9 SSC Receive Synchronization Holding Register Name:SSC_RSHR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT RSDAT: Receive Synchronization Data DS60001516A-page 522  2017 Microchip Technology Inc. SAM9G20 32.8.10 SSC Transmit Synchronization Holding Register Name:SSC_TSHR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TSDAT 7 6 5 4 TSDAT TSDAT: Transmit Synchronization Data  2017 Microchip Technology Inc. DS60001516A-page 523 SAM9G20 32.8.11 SSC Receive Compare 0 Register Name:SSC_RC0R Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 CP0: Receive Compare Data 0 DS60001516A-page 524  2017 Microchip Technology Inc. SAM9G20 32.8.12 SSC Receive Compare 1 Register Name:SSC_RC1R Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP1 7 6 5 4 CP1 CP1: Receive Compare Data 1  2017 Microchip Technology Inc. DS60001516A-page 525 SAM9G20 32.8.13 SSC Status Register Name:SSC_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty. TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from TSR. 1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. DS60001516A-page 526  2017 Microchip Technology Inc. SAM9G20 CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register. TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled. RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled.  2017 Microchip Technology Inc. DS60001516A-page 527 SAM9G20 32.8.14 SSC Interrupt Enable Register Name:SSC_IER Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt. ENDTX: End of Transmission Interrupt Enable 0: No effect. 1: Enables the End of Transmission Interrupt. TXBUFE: Transmit Buffer Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Buffer Empty Interrupt RXRDY: Receive Ready Interrupt Enable 0: No effect. 1: Enables the Receive Ready Interrupt. OVRUN: Receive Overrun Interrupt Enable 0: No effect. 1: Enables the Receive Overrun Interrupt. ENDRX: End of Reception Interrupt Enable 0: No effect. 1: Enables the End of Reception Interrupt. RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 1: Enables the Receive Buffer Full Interrupt. CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. DS60001516A-page 528  2017 Microchip Technology Inc. SAM9G20 CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.  2017 Microchip Technology Inc. DS60001516A-page 529 SAM9G20 32.8.15 SSC Interrupt Disable Register Name:SSC_IDR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt. ENDTX: End of Transmission Interrupt Disable 0: No effect. 1: Disables the End of Transmission Interrupt. TXBUFE: Transmit Buffer Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Buffer Empty Interrupt. RXRDY: Receive Ready Interrupt Disable 0: No effect. 1: Disables the Receive Ready Interrupt. OVRUN: Receive Overrun Interrupt Disable 0: No effect. 1: Disables the Receive Overrun Interrupt. ENDRX: End of Reception Interrupt Disable 0: No effect. 1: Disables the End of Reception Interrupt. RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 1: Disables the Receive Buffer Full Interrupt. CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. DS60001516A-page 530  2017 Microchip Technology Inc. SAM9G20 CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.  2017 Microchip Technology Inc. DS60001516A-page 531 SAM9G20 32.8.16 SSC Interrupt Mask Register Name:SSC_IMR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled. TXEMPTY: Transmit Empty Interrupt Mask 0: The Transmit Empty Interrupt is disabled. 1: The Transmit Empty Interrupt is enabled. ENDTX: End of Transmission Interrupt Mask 0: The End of Transmission Interrupt is disabled. 1: The End of Transmission Interrupt is enabled. TXBUFE: Transmit Buffer Empty Interrupt Mask 0: The Transmit Buffer Empty Interrupt is disabled. 1: The Transmit Buffer Empty Interrupt is enabled. RXRDY: Receive Ready Interrupt Mask 0: The Receive Ready Interrupt is disabled. 1: The Receive Ready Interrupt is enabled. OVRUN: Receive Overrun Interrupt Mask 0: The Receive Overrun Interrupt is disabled. 1: The Receive Overrun Interrupt is enabled. ENDRX: End of Reception Interrupt Mask 0: The End of Reception Interrupt is disabled. 1: The End of Reception Interrupt is enabled. RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 1: The Receive Buffer Full Interrupt is enabled. CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. DS60001516A-page 532  2017 Microchip Technology Inc. SAM9G20 CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled.  2017 Microchip Technology Inc. DS60001516A-page 533 SAM9G20 33. Timer Counter (TC) 33.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 33-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2. Table 33-1: Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 SLCK DS60001516A-page 534  2017 Microchip Technology Inc. SAM9G20 33.2 Block Diagram Figure 33-1: Timer Counter Block Diagram Parallel I/O Controller TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIOA1 TIOA2 TIMER_CLOCK3 XC0 TCLK1 TIMER_CLOCK4 XC1 Timer/Counter Channel 0 TIOA TIOA0 TIOB0 TIOA0 TIOB TCLK2 TIOB0 XC2 TIMER_CLOCK5 TC0XC0S SYNC TCLK0 TCLK1 TCLK2 INT0 TCLK0 TCLK1 XC0 TIOA0 XC1 TIOA2 XC2 Timer/Counter Channel 1 TIOA TIOA1 TIOB1 TIOA1 TIOB TCLK2 TC1XC1S TCLK0 XC0 TCLK1 XC1 TCLK2 XC2 TIOB1 SYNC Timer/Counter Channel 2 INT1 TIOA TIOA2 TIOB2 TIOA2 TIOB TIOA0 TIOA1 TC2XC2S TIOB2 SYNC INT2 Timer Counter Advanced Interrupt Controller Table 33-2: Signal Name Description Block/Channel Signal Name XC0, XC1, XC2 Channel Signal External Clock Inputs TIOA Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT SYNC  2017 Microchip Technology Inc. Description Interrupt Signal Output Synchronization Input Signal DS60001516A-page 535 SAM9G20 33.3 Pin Name List Table 33-3: TC pin list Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O 33.4 33.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 33.4.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. 33.4.3 Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. 33.5 33.5.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 33-4. 33.5.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 33.5.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 33-2. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 • External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 33-3. Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock DS60001516A-page 536  2017 Microchip Technology Inc. SAM9G20 Figure 33-2: Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 33-3: Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 CLKI TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Selected Clock XC0 XC1 XC2 BURST 1  2017 Microchip Technology Inc. DS60001516A-page 537 SAM9G20 33.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 33-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 33-4: Clock Control Selected Clock Trigger CLKSTA Q Q S CLKEN CLKDIS S R R Counter Clock 33.5.5 Stop Event Disable Event TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 33.5.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. DS60001516A-page 538  2017 Microchip Technology Inc. SAM9G20 Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 33.5.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 33-5 shows the configuration of the TC channel when programmed in Capture Mode. 33.5.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 33.5.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.  2017 Microchip Technology Inc. DS60001516A-page 539 DS60001516A-page 540 MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 CLKI Compare RC = Register C COVFS INT Figure 33-5: TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS SAM9G20 Capture Mode CPCS LOVRS LDRBS ETRGS LDRAS TC1_IMR  2017 Microchip Technology Inc. SAM9G20 33.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 33-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 33.5.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.  2017 Microchip Technology Inc. DS60001516A-page 541 DS60001516A-page 542 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC TIOB MTIOB TIOA MTIOA Figure 33-6: Output Controller Output Controller TCCLKS SAM9G20 Waveform Mode CPCS CPBS COVFS TC1_SR ETRGS TC1_IMR  2017 Microchip Technology Inc. SAM9G20 33.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 33-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 33-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 33-7: WAVSEL = 00 without trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 33-8: WAVSEL = 00 with trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA  2017 Microchip Technology Inc. DS60001516A-page 543 SAM9G20 33.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 33-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 33-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 33-9: WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 33-10: WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA DS60001516A-page 544  2017 Microchip Technology Inc. SAM9G20 33.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 33-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 33-11: WAVSEL = 01 Without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 33-12: WAVSEL = 01 With Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Waveform Examples Time TIOB TIOA  2017 Microchip Technology Inc. DS60001516A-page 545 SAM9G20 33.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 33-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 33-13: WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 33-14: WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples Time TIOB TIOA DS60001516A-page 546  2017 Microchip Technology Inc. SAM9G20 33.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 33.5.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR.  2017 Microchip Technology Inc. DS60001516A-page 547 SAM9G20 33.6 Timer Counter (TC) User Interface Table 33-4: Register Mapping Offset(1) Register Name 0x00 + channel * 0x40 + 0x00 Channel Control Register 0x00 + channel * 0x40 + 0x04 Channel Mode Register 0x00 + channel * 0x40 + 0x08 Reserved 0x00 + channel * 0x40 + 0x0C Reserved 0x00 + channel * 0x40 + 0x10 Counter Value 0x00 + channel * 0x40 + 0x14 Register A Access Reset TC_CCR Write-only – TC_CMR Read/Write 0 TC_CV Read-only 0 TC_RA (2) Read/Write 0 0 0x00 + channel * 0x40 + 0x18 Register B TC_RB Read/Write(2) 0x00 + channel * 0x40 + 0x1C Register C TC_RC Read/Write 0 0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0 0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only – 0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only – 0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0 0xC0 Block Control Register TC_BCR Write-only – 0xC4 Block Mode Register TC_BMR Read/Write 0 0xFC Reserved – – – Note 1: Channel index ranges from 0 to 2. 2: Read-only if WAVE = 0 DS60001516A-page 548  2017 Microchip Technology Inc. SAM9G20 33.6.1 TC Block Control Register Name:TC_BCR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.  2017 Microchip Technology Inc. DS60001516A-page 549 SAM9G20 33.6.2 TC Block Mode Register Name:TC_BMR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 – – TC2XC2S TC1XC1S 0 TC0XC0S TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 0 TCLK0 0 1 none 1 0 TIOA1 1 1 TIOA2 TC1XC1S: External Clock Signal 1 Selection TC1XC1S Signal Connected to XC1 0 0 TCLK1 0 1 none 1 0 TIOA0 1 1 TIOA2 TC2XC2S: External Clock Signal 2 Selection TC2XC2S Signal Connected to XC2 0 0 TCLK2 0 1 none 1 0 TIOA0 1 1 TIOA1 DS60001516A-page 550  2017 Microchip Technology Inc. SAM9G20 33.6.3 TC Channel Control Register Name:TC_CCRx [x=0..2] Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1. CLKDIS: Counter Clock Disable Command 0: No effect. 1: Disables the clock. SWTRG: Software Trigger Command 0: No effect. 1: A software trigger is performed: the counter is reset and the clock is started.  2017 Microchip Technology Inc. DS60001516A-page 551 SAM9G20 33.6.4 TC Channel Mode Register: Capture Mode Name:TC_CMRx [x=0..2] (WAVE = 0) Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – 15 14 13 12 11 10 WAVE CPCTRG – – – ABETRG 7 6 5 3 2 LDBDIS LDBSTOP 16 LDRB 4 BURST CLKI LDRA 9 8 ETRGEDG 1 0 TCCLKS TCCLKS: Clock Selection TCCLKS Clock Selected 0 0 0 TIMER_CLOCK1 0 0 1 TIMER_CLOCK2 0 1 0 TIMER_CLOCK3 0 1 1 TIMER_CLOCK4 1 0 0 TIMER_CLOCK5 1 0 1 XC0 1 1 0 XC1 1 1 1 XC2 CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. BURST: Burst Signal Selection BURST 0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock. LDBSTOP: Counter Clock Stopped with RB Loading 0: Counter clock is not stopped when RB loading occurs. 1: Counter clock is stopped when RB loading occurs. LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. DS60001516A-page 552  2017 Microchip Technology Inc. SAM9G20 ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. WAVE 0: Capture Mode is enabled. 1: Capture Mode is disabled (Waveform Mode is enabled). LDRA: RA Loading Selection LDRA Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA LDRB: RB Loading Selection LDRB Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA  2017 Microchip Technology Inc. DS60001516A-page 553 SAM9G20 33.6.5 TC Channel Mode Register: Waveform Mode Name:TC_CMRx [x=0..2] (WAVE = 1) Access:Read/Write 31 30 29 BSWTRG 23 22 27 20 19 AEEVT 14 12 WAVSEL 7 6 CPCDIS CPCSTOP 25 24 BCPB 18 17 16 ACPC 13 WAVE 26 BCPC 21 ASWTRG 15 28 BEEVT 11 ENETRG 5 ACPA 10 9 EEVT 4 3 BURST CLKI 8 EEVTEDG 2 1 0 TCCLKS TCCLKS: Clock Selection TCCLKS Clock Selected 0 0 0 TIMER_CLOCK1 0 0 1 TIMER_CLOCK2 0 1 0 TIMER_CLOCK3 0 1 1 TIMER_CLOCK4 1 0 0 TIMER_CLOCK5 1 0 1 XC0 1 1 0 XC1 1 1 1 XC2 CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. BURST: Burst Signal Selection BURST 0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock. CPCSTOP: Counter Clock Stopped with RC Compare 0: Counter clock is not stopped when counter reaches RC. 1: Counter clock is stopped when counter reaches RC. CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. DS60001516A-page 554  2017 Microchip Technology Inc. SAM9G20 EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge EEVT: External Event Selection EEVT Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note 1: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. ENETRG: External Event Trigger Enable 0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1: The external event resets the counter and starts the counter clock. WAVSEL: Waveform Selection WAVSEL Effect 0 0 UP mode without automatic trigger on RC Compare 1 0 UP mode with automatic trigger on RC Compare 0 1 UPDOWN mode without automatic trigger on RC Compare 1 1 UPDOWN mode with automatic trigger on RC Compare WAVE 0: Waveform Mode is disabled (Capture Mode is enabled). 1: Waveform Mode is enabled. ACPA: RA Compare Effect on TIOA ACPA Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle  2017 Microchip Technology Inc. DS60001516A-page 555 SAM9G20 AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BCPB: RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BCPC: RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle DS60001516A-page 556  2017 Microchip Technology Inc. SAM9G20 33.6.6 TC Counter Value Register Name:TC_CVx [x=0..2] Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV CV: Counter Value CV contains the counter value in real time.  2017 Microchip Technology Inc. DS60001516A-page 557 SAM9G20 33.6.7 TC Register A Name:TC_RAx [x=0..2] Access:Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA RA: Register A RA contains the Register A value in real time. DS60001516A-page 558  2017 Microchip Technology Inc. SAM9G20 33.6.8 TC Register B Name:TC_RBx [x=0..2] Access:Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB RB: Register B RB contains the Register B value in real time.  2017 Microchip Technology Inc. DS60001516A-page 559 SAM9G20 33.6.9 TC Register C Name:TC_RCx [x=0..2] Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC RC: Register C RC contains the Register C value in real time. DS60001516A-page 560  2017 Microchip Technology Inc. SAM9G20 33.6.10 TC Status Register Name:TC_SRx [x=0..2] Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow Status 0: No counter overflow has occurred since the last read of the Status Register. 1: A counter overflow has occurred since the last read of the Status Register. LOVRS: Load Overrun Status 0: Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. CPAS: RA Compare Status 0: RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1: RA Compare has occurred since the last read of the Status Register, if WAVE = 1. CPBS: RB Compare Status 0: RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1: RB Compare has occurred since the last read of the Status Register, if WAVE = 1. CPCS: RC Compare Status 0: RC Compare has not occurred since the last read of the Status Register. 1: RC Compare has occurred since the last read of the Status Register. LDRAS: RA Loading Status 0: RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1: RA Load has occurred since the last read of the Status Register, if WAVE = 0. LDRBS: RB Loading Status 0: RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1: RB Load has occurred since the last read of the Status Register, if WAVE = 0. ETRGS: External Trigger Status 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled.  2017 Microchip Technology Inc. DS60001516A-page 561 SAM9G20 MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. MTIOB: TIOB Mirror 0: TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1: TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. DS60001516A-page 562  2017 Microchip Technology Inc. SAM9G20 33.6.11 TC Interrupt Enable Register Name:TC_IERx [x=0..2] Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt. LOVRS: Load Overrun 0: No effect. 1: Enables the Load Overrun Interrupt. CPAS: RA Compare 0: No effect. 1: Enables the RA Compare Interrupt. CPBS: RB Compare 0: No effect. 1: Enables the RB Compare Interrupt. CPCS: RC Compare 0: No effect. 1: Enables the RC Compare Interrupt. LDRAS: RA Loading 0: No effect. 1: Enables the RA Load Interrupt. LDRBS: RB Loading 0: No effect. 1: Enables the RB Load Interrupt. ETRGS: External Trigger 0: No effect. 1: Enables the External Trigger Interrupt.  2017 Microchip Technology Inc. DS60001516A-page 563 SAM9G20 33.6.12 TC Interrupt Disable Register Name:TC_IDRx [x=0..2] Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt. LOVRS: Load Overrun 0: No effect. 1: Disables the Load Overrun Interrupt (if WAVE = 0). CPAS: RA Compare 0: No effect. 1: Disables the RA Compare Interrupt (if WAVE = 1). CPBS: RB Compare 0: No effect. 1: Disables the RB Compare Interrupt (if WAVE = 1). CPCS: RC Compare 0: No effect. 1: Disables the RC Compare Interrupt. LDRAS: RA Loading 0: No effect. 1: Disables the RA Load Interrupt (if WAVE = 0). LDRBS: RB Loading 0: No effect. 1: Disables the RB Load Interrupt (if WAVE = 0). ETRGS: External Trigger 0: No effect. 1: Disables the External Trigger Interrupt. DS60001516A-page 564  2017 Microchip Technology Inc. SAM9G20 33.6.13 TC Interrupt Mask Register Name:TC_IMRx [x=0..2] Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled. LOVRS: Load Overrun 0: The Load Overrun Interrupt is disabled. 1: The Load Overrun Interrupt is enabled. CPAS: RA Compare 0: The RA Compare Interrupt is disabled. 1: The RA Compare Interrupt is enabled. CPBS: RB Compare 0: The RB Compare Interrupt is disabled. 1: The RB Compare Interrupt is enabled. CPCS: RC Compare 0: The RC Compare Interrupt is disabled. 1: The RC Compare Interrupt is enabled. LDRAS: RA Loading 0: The Load RA Interrupt is disabled. 1: The Load RA Interrupt is enabled. LDRBS: RB Loading 0: The Load RB Interrupt is disabled. 1: The Load RB Interrupt is enabled. ETRGS: External Trigger 0: The External Trigger Interrupt is disabled. 1: The External Trigger Interrupt is enabled.  2017 Microchip Technology Inc. DS60001516A-page 565 SAM9G20 34. MultiMedia Card Interface (MCI) 34.1 Overview The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 34.2 Block Diagram Figure 34-1: Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1) MCI Interrupt Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. DS60001516A-page 566  2017 Microchip Technology Inc. SAM9G20 34.3 Application Block Diagram Figure 34-2: Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 9 SDCard MMC 34.4 Pin Name List Table 34-1: I/O Lines Description Pin Name(2) Pin Description Type(1) Comments MCCDA/MCCDB Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP MCDB0–MCDB3 Data 0..3 of Slot B I/O/PP DAT0 of an MMC DAT[0..3] of an SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO Note 1: I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 34.5 34.5.1 Product Dependencies I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. 34.5.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock.  2017 Microchip Technology Inc. DS60001516A-page 567 SAM9G20 34.5.3 Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. 34.6 Bus Topology Figure 34-3: Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 34-2: Bus Topology Name Type(1) Description MCI Pin Name(2) (Slot z) 1 RSV NC Not connected - 2 CMD I/O/PP/OD Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data 0 MCDz0 Pin Number Note 1: I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. Figure 34-4: MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK Note: 1234567 1234567 1234567 MMC1 MMC2 MMC3 When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. DS60001516A-page 568  2017 Microchip Technology Inc. SAM9G20 Figure 34-5: SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 34-3. Table 34-3: SD Memory Card Bus Signals Pin Number Name Type(1) Description MCI Pin Name(2) (Slot z) 1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 MCDz3 2 CMD PP Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data line Bit 0 MCDz0 8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1 9 DAT[2] I/O/PP Data line Bit 2 MCDz2 Note 1: I: input, O: output, PP: Push Pull, OD: Open Drain. 2: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 34-6: Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy.  2017 Microchip Technology Inc. DS60001516A-page 569 SAM9G20 SD Card Bus Connections with Two Slots 1 2 3 4 5 6 78 Figure 34-7: MCDA0 - MCDA3 MCCK 1 2 3 4 5 6 78 9 MCCDA SD CARD 1 MCDB0 - MCDB3 9 MCCDB SD CARD 2 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. Figure 34-8: Mixing MultiMedia and SD Memory Cards with Two Slots MCDA0 MCCDA MCCK 1234567 MMC2 MMC3 SD CARD 9 MCCDB 1234567 MMC1 1 2 3 4 5 6 78 MCDB0 - MCDB3 1234567 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. DS60001516A-page 570  2017 Microchip Technology Inc. SAM9G20 34.7 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. • Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 34-4. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (see Section 34.7.2 Data Transfer Operation). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 34.7.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: NID Cycles Host Command CMD S T Content CRC E Z ****** CID Z S T Content Z Z Z The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 34-4 and Table 34-5.  2017 Microchip Technology Inc. DS60001516A-page 571 SAM9G20 Table 34-4: ALL_SEND_CID Command Description CMD Index Type Argument Resp Abbreviation Command Description CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: bcr means broadcast command with response. Table 34-5: Fields and Values for MCI_CMDR Command Register Field Value CMDNB (command number) 2 (CMD2) RSPTYP (response type) 2 (R2: 136 bits response) SPCMD (special command) 0 (not a special command) OPCMD (open drain command) 1 MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles) TRCMD (transfer command) 0 (No transfer) TRDIR (transfer direction) X (available only in transfer command) TRTYP (transfer type) X (available only in transfer command) IOSPCMD (SDIO special command) 0 (not a special command) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (MCI_ARGR) with the command argument. • Set the command register (MCI_CMDR) (see Table 34-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. DS60001516A-page 572  2017 Microchip Technology Inc. SAM9G20 Figure 34-9: Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note 1: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 34.7.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block. Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write):  2017 Microchip Technology Inc. DS60001516A-page 573 SAM9G20 The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 34.7.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 34-10), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. DS60001516A-page 574  2017 Microchip Technology Inc. SAM9G20 Figure 34-10: Read Functional Flow Diagram Send SELECT/DESELECT_CARD (1) command to select the card Send SET_BLOCKLEN command(1) No Yes Read with PDC Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght