AT91SAM9N12-CUR

32-BIT ARM-BASED MICROPROCESSORS SAM9N12/SAM9CN11/SAM9CN12 Description The SAM9N and SAM9CN Arm926EJ-S™-based embedded MPUs offer the frequently-requested combination of user interface functionality and high data rate connectivity, with LCD controller, resistive touchscreen, multiple UARTs, SPI, I2C, full-speed USB Host and Device and SDIO. These eMPUs support the latest generation of LPDDR/DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with eight DMA channels and distributed memory—including a 32-Kbyte SRAM—sustains the high bandwidth required by the processor and the high-speed peripherals. The SAM9CN devices offer on-chip hardware accelerators with DMA support that enable high-speed data encryption and authentication of transferred data or applications. Supported standards are up to 256-bit AES, and FIPS Publication 180-2 compliant SHA1 and SHA256. A True Random Number Generator is embedded for key generation and exchange protocols. The devices also feature fuse bits for crypto key (SAM9CN12), user configuration (SAM9N12 and SAM9CN11) and device configuration (all). The SAM9CN12 includes a secure Boot ROM; the SAM9N12 and SAM9CN11 include a standard Boot ROM. The I/Os support 1.8V or 3.3V operation and are independently configurable for the memory interface and peripheral I/ Os. This feature eliminates the need for any external level shifters, while 0.8mm ball pitch packages lower PCB cost and complexity. The SAM9N and SAM9CN power management controllers feature efficient clock gating and a battery backup section that minimizes power consumption in active and standby modes. The following table presents the embedded features of each device. • Device Configuration Feature SAM9N12 SAM9CN11 (for evaluation only) SAM9CN12 Standard Boot with BSC   – Secure Boot – –  TRNG    AES –   SHA –   JTAG Access   – Features • Core - Arm926EJ-S Arm® Thumb® Processor running up to 400 MHz - 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit • Memories - One 128-Kbyte internal ROM embedding standard or secure bootstrap routine - One 32-Kbyte internal SRAM, single-cycle access at system speed - 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories - MLC/SLC NAND Controller, with up to 24-bit Programmable Multibit Error Correction Code (PMECC)  2017 Microchip Technology Inc. DS60001517A-page 1 SAM9N12/SAM9CN11/SAM9CN12 • System running up to 133 MHz - Power-on Reset, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer and Real Time Clock - Boot Mode Select Option, Remap Command - Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators - Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL optimized for USB - Six 32-bit-layer AHB Bus Matrix - Dual Peripheral Bridge with dedicated programmable clock - One dual port 8-channel DMA Controller - Advanced Interrupt Controller (AIC) - Two Programmable External Clock Signals • Low-power Mode - Shutdown Controller with four 32-bit General-purpose Backup Registers - Clock Generator and Power Management Controller - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities • Peripherals - LCD Controller - USB Device Full Speed with dedicated On-chip Transceiver - USB Host Full Speed with dedicated On-chip Transceiver - One High speed SD card and SDIO Host Controller - Two Master/Slave Serial Peripheral Interfaces (SPI) - Two 3-channel 32-bit Timer/Counters (TC) - One Synchronous Serial Controller (SSC) - One 4-channel 16-bit PWM Controller - Two 2-wire Interfaces (TWI) - Four Universal Synchronous Asynchronous Receiver Transmitters (USART) - Two Universal Asynchronous Receiver Transmitters (UART) - One Debug Unit (DBGU) - One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touchscreen support • Safety - Crystal Failure Detection - Independent Watchdog - Power-on Reset Cells - Register Write Protection - SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2 (SAM9CN11/SAM9CN12 devices) • Cryptography - True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 - AES 256-, 192-, 128-bit Key Algorithm compliant with FIPS Publication 197 (SAM9CN11/SAM9CN12 devices) - 256 Fuse bits for crypto key and 64 Fuse bits for device configuration, including JTAG disable and forced boot from the on-chip ROM • I/O - Four 32-bit Parallel Input/Output Controllers - 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input - Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output • Packages - 217-ball BGA, pitch 0.8 mm - 247-ball BGA, pitch 0.5 mm DS60001517A-page 2  2017 Microchip Technology Inc. Block Diagram SAM9N12/CN11/CN12 Block Diagram System Controller HD P HD M S JTAG / Boundary Scan PIO D0–D15 A0/NBS0 A1/NBS2/NWR2/DQM2 A2–A15, A19 A16/BA0 A17/BA1 A18/BA2 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3/DQM3 SDCK, #SDCK, SDCKE RAS, CAS SDWE, SDA10 DQM[0..1] DQS[0..1] Transceiver MMU PIO PLLA 12 MHz RC Osc. PIT WDT LCD DCache 16 Kbytes I 8-ch DMA DDR2/LPDDR SDR/LPSDR Controller DMA DMA Bus Interface PMC 16 MHz XTAL Osc. USB FS OHCI Arm926EJ-S DBGU PLLB EBI In-Circuit Emulator AIC ICache 16 Kbytes XIN XOUT AG JT Fuse Box PCK0–PCK1 FIQ IRQ DRXD DTXD NC 23 SY AT DH M D C PW CD , L CD –L NC L 0 P AT SY CK N, IS DD DV DP DE DD LC LC LC LD LC L SE CK RT BM RS T TD TDI TMO TC S K Figure 1-1: NT  2017 Microchip Technology Inc. 1. D ROM 128 Kbytes Static Memory Controller Backup Section VDDBU NRST POR VDDCORE POR SHDWC 128-bit GPBR Multi-Layer AHB Matrix RC Osc. RTC PIO 32 kHz XTAL Osc RSTC * Except SAM9N12 DMA DMA PIOA PIOD PIOB PIOC AES * Peripheral Bridge SHA * SRAM 32 Kbytes Peripheral Bridge NAND Flash Controller PMECC PMERRLOC TRNG APB SPI0 SPI1 FIFO DMA DMA SSC HSMCI0 SD/SDIO DMA TWI0 TWI1 DMA PWM USART0 USART1 USART2 USART3 DMA UART0 UART1 TC0 TC1 TC2 TC3 TC4 TC5 DMA 12-channel 10-bit ADC Touchscreen CI M T TW W D CK 0– 0– TW TW D CK1 PW 1 M 0– PW M 3 I0 C M M C –M A0 _D 0_ C CI DA 0_ CK NP NPCS C 3 NP S2 NPCS C 1 SP S0 M CK O M SI IS O TK TF TD RD RF RK DS60001517A-page 3 A3 _D I0 CT RTS0– SCS0–3 RDK0 3 –3 TX X0– UR D0 3 D –3 UT X0 XD –U 0– RD UT X1 TC XD L TI K0 1 O – TI A0 TC O –T LK B0 IO 5 –T A 5 TS IOB AD 5 AD T AD 0/ RG X AD 1/X P/ 3/ AD M/ UL YM 2/ U /SYP/ R G PA E LL D5 AD NS –G 4/L E P R AD AD 1 VD VR 1 D E G ANF ND A AN A PIO DPRAM USB FS Device Transceiver DD M DD P DMA NWAIT A20–A25 D16–D31 NCS2, NCS3, NCS4, NCS5 NANDOE, NANDWE NANDALE, NANDCLE NANDCS SAM9N12/SAM9CN11/SAM9CN12 XIN32 XOUT32 SHDN WKUP SAM9N12/SAM9CN11/SAM9CN12 2. Signal Description Table 2-1 gives details on the signal names classified by peripheral. Table 2-1: Signal Description List Signal Name Function Type Active Level Clocks, Oscillators and PLLs XIN Main Oscillator Input Input – XOUT Main Oscillator Output Output – XIN32 Slow Clock Oscillator Input Input – XOUT32 Slow Clock Oscillator Output Output – PCK0–PCK1 Programmable Clock Output Output – Shutdown, Wakeup Logic SHDN Shut-Down Control Output – WKUP Wake-Up Input Input – ICE and JTAG TCK Test Clock Input – TDI Test Data In Input – TDO Test Data Out Output – TMS Test Mode Select Input – JTAGSEL JTAG Selection Input – RTCK Return Test Clock Output – Reset/Test NRST Microcontroller Reset I/O Low NTRST Test Reset Signal Input – BMS Boot Mode Select Input – Debug Unit - DBGU DRXD Debug Receive Data Input – DTXD Debug Transmit Data Output – Advanced Interrupt Controller - AIC IRQ External Interrupt Input Input – FIQ Fast Interrupt Input Input – PIO Controller - PIOA / PIOB / PIOC / PIOD PA0–PA31 Parallel IO Controller A I/O – PB0–PB18 Parallel IO Controller B I/O – PC0–PC31 Parallel IO Controller C I/O – PD0–PD21 Parallel IO Controller D I/O – DS60001517A-page 4  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 2-1: Signal Description List (Continued) Signal Name Function Type Active Level External Bus Interface - EBI D0–D15 Data Bus I/O – D16–D31 Data Bus I/O – A0–A25 Address Bus Output – NWAIT External Wait Signal Input Low Static Memory Controller - SMC NCS0–NCS5 Chip Select Lines Output Low NWR0–NWR3 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS3 Byte Mask Signal Output Low NAND Flash Support NFD0–NFD15 NAND Flash I/O I/O – NANDCS NAND Flash Chip Select Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low DDR2/SDRAM/LPDDR Controller SDCK,#SDCK DDR2/SDRAM differential clock Output – SDCKE DDR2/SDRAM Clock Enable Output High SDCS DDR2/SDRAM Controller Chip Select Output Low BA[0..2] Bank Select Output Low SDWE DDR2/SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output – DQS[0..1] Data Strobe I/O – DQM[0..3] Write Data Mask Output – High Speed Multimedia Card Interface - HSMCI MCI_CK Multimedia Card Clock I/O – MCI_CDA Multimedia Card Slot Command I/O – MCI_DA0–MCI_DA7 Multimedia Card Slot Data I/O – Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock I/O – TXDx USARTx Transmit Data Output – RXDx USARTx Receive Data Input – RTSx USARTx Request To Send Output – CTSx USARTx Clear To Send Input –  2017 Microchip Technology Inc. DS60001517A-page 5 SAM9N12/SAM9CN11/SAM9CN12 Table 2-1: Signal Description List (Continued) Signal Name Function Type Active Level Universal Asynchronous Receiver Transmitter - UARTx UTXDx UARTx Transmit Data Output – URXDx UARTx Receive Data Input – Synchronous Serial Controller - SSC TD SSC Transmit Data Output – RD SSC Receive Data Input – TK SSC Transmit Clock I/O – RK SSC Receive Clock I/O – TF SSC Transmit Frame Sync I/O – RF SSC Receive Frame Sync I/O – Timer Counter - TCx (x=0..5) TCLKx TC Channel x External Clock Input Input – TIOAx TC Channel x I/O Line A I/O – TIOBx TC Channel x I/O Line B I/O – Serial Peripheral Interface - SPIx SPIx_MISO Master In Slave Out I/O – SPIx_MOSI Master Out Slave In I/O – SPIx_SPCK SPI Serial Clock I/O – SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS1–SPIx_NPCS3 SPI Peripheral Chip Select Output Low Two-wire Interface - TWIx TWDx Two-wire Serial Data I/O – TWCKx Two-wire Serial Clock I/O – Output – Pulse Width Modulation Controller - PWM PWM0–PWM3 Pulse Width Modulation Output USB Device Full Speed Port - UDP DDP USB Device Data + Analog – DDM USB Device Data - Analog – USB Host Full Speed Port - UHP HDP USB Host Data + Analog – HDM USB Host Data - Analog – DS60001517A-page 6  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 2-1: Signal Description List (Continued) Signal Name Function Type Active Level LCD Controller - LCDC LCDDAT 0–23 LCD Data Bus Output – LCDVSYNC LCD Vertical Synchronization Output – LCDHSYNC LCD Horizontal Synchronization Output – LCDPCK LCD Pixel Clock Output – LCDDEN LCD Data Enable Output – LCDPWM LCD Contrast Control Output – LCDDISP LCD Display Enable Output – Analog-to-Digital Converter - ADC AD0/XP/UL Top/Upper Left Channel Analog – AD1/XM/UR Bottom/Upper Right Channel Analog – AD2/YP/LL Right/Lower Left Channel Analog – AD3/YM/SENSE Left/Sense Channel Analog – AD4/LR Lower Right Channel Analog – AD5–AD11 7 Analog Inputs Analog – ADTRG ADC Trigger Input – ADVREF ADC Reference Analog – Table 2-2: SAM9N12/CN11/CN12 I/O Type Description Pull-up(1) Pull-up Value (Ohm) Pulldown(1) Pull-down Value (Ohm) Schmitt Trigger(1) – Switchable 50–100K Switchable 50–100K Switchable 1.65–3.6V – Switchable 50–100K Switchable 50–100K Switchable LCDDOTCK 1.65–3.6V – Switchable 50–100K Switchable 50–100K Switchable ADx, GPADx 3.0–3.6V I Switchable 50–100K EBI All data lines (input/output) except the lines indicated further on in this table 1.65–1.95V, 3.0–3.6V – Switchable 50–100K Switchable 50–100K – EBI_O All address and control lines (output only) except the lines indicated further on in this table 1.65–1.95V, 3.0–3.6V – Reset State 50–100K Reset State 50–100K – Voltage Range Analog All PIO lines except the lines indicated further on in this table 1.65–3.6V GPIO_CLK MCICK, SPI0SPCK, SPI1SPCK GPIO_CLK2 GPIO_ANA I/O Type GPIO Signal Name  2017 Microchip Technology Inc. Switchable DS60001517A-page 7 SAM9N12/SAM9CN11/SAM9CN12 Table 2-2: SAM9N12/CN11/CN12 I/O Type Description (Continued) Analog Pull-up(1) Pull-up Value (Ohm) 1.65–1.95V, 3.0–3.6V – – – – – – NRST, NTRST, BMS, TCK, TDI, TMS, TDO, RTCK 3.0–3.6V – Reset State 100K Reset State 100K Reset State WKUP, SHDN, JTAGSEL 1.65–3.6V – Reset State 100k Reset State 15K Reset State USBFS HDP, HDM, DDP, DDM 3.0–3.6V I/O – – – – – CLOCK XIN, XOUT, XIN32, XOUT32 1.65–3.6V I/O – – – – – I/O Type Signal Name EBI_CLK SDCK, #SDCK RSTJTAG SYSC Voltage Range Pulldown(1) Pull-down Value (Ohm) Schmitt Trigger(1) Note 1: When “Reset State” is stated, the configuration is defined by the “Reset State” column of the Pin Description table. DS60001517A-page 8  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 3. Package and Pinout The SAM9N12/SAM9CN11/SAM9CN12 is available in the following Green-compliant packages: • 217-ball BGA, pitch 0.8 mm • 247-ball BGA, pitch 0.5 mm 3.1 217-ball BGA Package Outline Figure 3-1 shows the orientation of the 217-ball BGA package. Figure 3-1: Orientation of the 217-ball BGA Package TOP VIEW 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U BALL A1 3.2 247-ball BGA Package Outline Figure 3-2 shows the orientation of the 247-ball BGA package. Figure 3-2: Orientation of the 247-ball BGA Package BOTTOM VIEW BALL A1  2017 Microchip Technology Inc. DS60001517A-page 9 SAM9N12/SAM9CN11/SAM9CN12 3.3 217-ball BGA Package Pinout Table 3-1: BGA217 Pin Description Primary Ball Power Rail I/O Type Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST T3 VDDIOP0 GPIO PA0 I/O – – TXD0 O SPI1_NPCS1 O – – PIO, I, PU, ST U2 VDDIOP0 GPIO PA1 I/O – – RXD0 I SPI0_NPCS2 O – – PIO, I, PU, ST U3 VDDIOP0 GPIO PA2 I/O – – RTS0 O – – – – PIO, I, PU, ST P4 VDDIOP0 GPIO PA3 I/O – – CTS0 I – – – – PIO, I, PU, ST T4 VDDIOP0 GPIO PA4 I/O – – SCK0 I/O – – – – PIO, I, PU, ST U4 VDDIOP0 GPIO PA5 I/O – – TXD1 O – – – – PIO, I, PU, ST P5 VDDIOP0 GPIO PA6 I/O – – RXD1 I – – – – PIO, I, PU, ST R4 VDDIOP0 GPIO PA7 I/O – – TXD2 O SPI0_NPCS1 O – – PIO, I, PU, ST U6 VDDIOP0 GPIO PA8 I/O – – RXD2 I SPI1_NPCS0 I/O – – PIO, I, PU, ST R5 VDDIOP0 GPIO PA9 I/O – – DRXD I – – – – PIO, I, PU, ST R6 VDDIOP0 GPIO PA10 I/O – – DTXD O – – – – PIO, I, PU, ST T5 VDDIOP0 GPIO PA11 I/O – – SPI0_MISO I/O MCDA4 I/O – – PIO, I, PU, ST T6 VDDIOP0 GPIO PA12 I/O – – SPI0_MOSI I/O MCDA5 I/O – – PIO, I, PU, ST U5 VDDIOP0 GPIO_CLK PA13 I/O – – SPI0_SPCK I/O MCDA6 I/O – – PIO, I, PU, ST U7 VDDIOP0 GPIO PA14 I/O – – SPI0_NPCS0 I/O MCDA7 I/O – – PIO, I, PU, ST T7 VDDIOP0 GPIO PA15 I/O – – MCDA0 I/O – – – – PIO, I, PU, ST R7 VDDIOP0 GPIO PA16 I/O – – MCCDA I/O – – – – PIO, I, PU, ST U8 VDDIOP0 GPIO_CLK PA17 I/O – – MCCK I/O – – – – PIO, I, PU, ST P8 VDDIOP0 GPIO PA18 I/O – – MCDA1 I/O – – – – PIO, I, PU, ST T8 VDDIOP0 GPIO PA19 I/O – – MCDA2 I/O – – – – PIO, I, PU, ST R8 VDDIOP0 GPIO PA20 I/O – – MCDA3 I/O – – – – PIO, I, PU, ST U9 VDDIOP0 GPIO PA21 I/O – – TIOA0 I/O SPI1_MISO I/O – – PIO, I, PU, ST U10 VDDIOP0 GPIO PA22 I/O – – TIOA1 I/O SPI1_MOSI I/O – – PIO, I, PU, ST T9 VDDIOP0 GPIO_CLK PA23 I/O – – TIOA2 I/O SPI1_SPCK I/O – – PIO, I, PU, ST U11 VDDIOP0 GPIO PA24 I/O – – TCLK0 I TK I/O – – PIO, I, PU, ST T10 VDDIOP0 GPIO PA25 I/O – – TCLK1 I TF I/O – – PIO, I, PU, ST R9 VDDIOP0 GPIO PA26 I/O – – TCLK2 I TD O – – PIO, I, PU, ST U12 VDDIOP0 GPIO PA27 I/O – – TIOB0 I/O RD I – – PIO, I, PU, ST T11 VDDIOP0 GPIO PA28 I/O – – TIOB1 I/O RK I/O – – PIO, I, PU, ST U13 VDDIOP0 GPIO PA29 I/O – – TIOB2 I/O RF I/O – – PIO, I, PU, ST R10 VDDIOP0 GPIO PA30 I/O – – TWD0 I/O SPI1_NPCS3 O – – PIO, I, PU, ST T12 VDDIOP0 GPIO PA31 I/O – – TWCK0 O SPI1_NPCS2 O – – PIO, I, PU, ST E4 VDDANA GPIO PB0 I/O – – – – RTS2 O – – PIO, I, PU, ST F3 VDDANA GPIO PB1 I/O – – – – CTS2 I – – PIO, I, PU, ST F4 VDDANA GPIO PB2 I/O – – – – SCK2 I/O – – PIO, I, PU, ST F2 VDDANA GPIO PB3 I/O – – – – SPI0_NPCS3 O – – PIO, I, PU, ST G4 VDDANA GPIO_CLK PB4 I/O – – – – – – – – PIO, I, PU, ST G3 VDDANA GPIO PB5 I/O – – – – – – – – PIO, I, PU, ST DS60001517A-page 10  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 3-1: BGA217 Pin Description (Continued) Primary Ball Power Rail I/O Type Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST D2 VDDANA GPIO_ANA PB6 I/O AD7 I – – – – – – PIO, I, PU, ST E2 VDDANA GPIO_ANA PB7 I/O AD8 I – – – – – – PIO, I, PU, ST D1 VDDANA GPIO_ANA PB8 I/O AD9 I – – – – – – PIO, I, PU, ST F1 VDDANA GPIO_ANA PB9 I/O AD10 I – – PCK1 O – – PIO, I, PU, ST E1 VDDANA GPIO_ANA PB10 I/O AD11 I – – PCK0 O – – PIO, I, PU, ST A1 VDDANA GPIO_ANA PB11 I/O AD0 I – – PWM0 O – – PIO, I, PU, ST C3 VDDANA GPIO_ANA PB12 I/O AD1 I – – PWM1 O – – PIO, I, PU, ST B1 VDDANA GPIO_ANA PB13 I/O AD2 I – – PWM2 O – – PIO, I, PU, ST C2 VDDANA GPIO_ANA PB14 I/O AD3 I – – PWM3 O – – PIO, I, PU, ST D3 VDDANA GPIO_ANA PB15 I/O AD4 I – – – – – – PIO, I, PU, ST C1 VDDANA GPIO_ANA PB16 I/O AD5 I – – – – – – PIO, I, PU, ST E3 VDDANA GPIO_ANA PB17 I/O AD6 I – – – – – – PIO, I, PU, ST D4 VDDANA GPIO PB18 I/O – – IRQ I ADTRG I – – PIO, I, PU, ST G2 VDDIOP1 GPIO PC0 I/O – – LCDDAT0 O – – TWD1 I/O PIO, I, PU, ST G1 VDDIOP1 GPIO PC1 I/O – – LCDDAT1 O – – TWCK1 O PIO, I, PU, ST H4 VDDIOP1 GPIO PC2 I/O – – LCDDAT2 O – – TIOA3 I/O PIO, I, PU, ST J1 VDDIOP1 GPIO PC3 I/O – – LCDDAT3 O – – TIOB3 I/O PIO, I, PU, ST H3 VDDIOP1 GPIO PC4 I/O – – LCDDAT4 O – – TCLK3 I PIO, I, PU, ST J3 VDDIOP1 GPIO PC5 I/O – – LCDDAT5 O – – TIOA4 I/O PIO, I, PU, ST H2 VDDIOP1 GPIO PC6 I/O – – LCDDAT6 O – – TIOB4 I/O PIO, I, PU, ST H1 VDDIOP1 GPIO PC7 I/O – – LCDDAT7 O – – TCLK4 I PIO, I, PU, ST K2 VDDIOP1 GPIO PC8 I/O – – LCDDAT8 O – – UTXD0 O PIO, I, PU, ST J2 VDDIOP1 GPIO PC9 I/O – – LCDDAT9 O – – URXD0 I PIO, I, PU, ST L1 VDDIOP1 GPIO PC10 I/O – – LCDDAT10 O – – PWM0 O PIO, I, PU, ST K1 VDDIOP1 GPIO PC11 I/O – – LCDDAT11 O – – PWM1 O PIO, I, PU, ST L2 VDDIOP1 GPIO PC12 I/O – – LCDDAT12 O – – TIOA5 I/O PIO, I, PU, ST K3 VDDIOP1 GPIO PC13 I/O – – LCDDAT13 O – – TIOB5 I/O PIO, I, PU, ST M1 VDDIOP1 GPIO PC14 I/O – – LCDDAT14 O – – TCLK5 I PIO, I, PU, ST M2 VDDIOP1 GPIO_CLK PC15 I/O – – LCDDAT15 O – – PCK0 O PIO, I, PU, ST K4 VDDIOP1 GPIO PC16 I/O – – LCDDAT16 O – – UTXD1 O PIO, I, PU, ST M3 VDDIOP1 GPIO PC17 I/O – – LCDDAT17 O – – URXD1 I PIO, I, PU, ST N1 VDDIOP1 GPIO PC18 I/O – – LCDDAT18 O – – PWM0 O PIO, I, PU, ST N2 VDDIOP1 GPIO PC19 I/O – – LCDDAT19 O – – PWM1 O PIO, I, PU, ST N3 VDDIOP1 GPIO PC20 I/O – – LCDDAT20 O – – PWM2 O PIO, I, PU, ST P1 VDDIOP1 GPIO PC21 I/O – – LCDDAT21 O – – PWM3 O PIO, I, PU, ST P2 VDDIOP1 GPIO PC22 I/O – – LCDDAT22 O TXD3 O – – PIO, I, PU, ST P3 VDDIOP1 GPIO PC23 I/O – – LCDDAT23 O RXD3 I – – PIO, I, PU, ST R1 VDDIOP1 GPIO PC24 I/O – – LCDDISP O RTS3 O – – PIO, I, PU, ST R3 VDDIOP1 GPIO PC25 I/O – – – CTS3 I – – PIO, I, PU, ST R2 VDDIOP1 GPIO PC26 I/O – – LCDPWM SCK3 I/O  2017 Microchip Technology Inc. O PIO, I, PU, ST DS60001517A-page 11 SAM9N12/SAM9CN11/SAM9CN12 Table 3-1: BGA217 Pin Description (Continued) Primary Ball Power Rail I/O Type Alternate PIO Peripheral A Signal Dir Signal Dir Signal PIO Peripheral B Dir Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, ST T1 VDDIOP1 GPIO PC27 I/O – – LCDVSYNC O – – RTS1 O PIO, I, PU, ST M4 VDDIOP1 GPIO PC28 I/O – – LCDHSYNC O – – CTS1 I PIO, I, PU, ST N4 VDDIOP1 GPIO_CLK PC29 I/O – – LCDDEN O – – SCK1 I/O PIO, I, PU, ST T2 VDDIOP1 GPIO_CLK2 PC30 I/O – – LCDPCK O – – – – PIO, I, PU, ST U1 VDDIOP1 GPIO PC31 I/O – – FIQ I – – PCK1 O PIO, I, PU, ST P15 VDDNF EBI PD0 I/O – – NANDOE O – – – – PIO, I, PU N14 VDDNF EBI PD1 I/O – – NANDWE O – – – – PIO, I, PU M15 VDDNF EBI PD2 I/O – – A21/NANDALE O – – – – A21,O, PD M14 VDDNF EBI PD3 I/O – – A22/NANDCLE O – – – – A22,O, PD P16 VDDNF EBI PD4 I/O – – NCS3 O – – – – PIO, I, PU M17 VDDNF EBI PD5 I/O – – NWAIT I – – – – PIO, I, PU L15 VDDNF EBI PD6 I/O – – D16 O – – – – PIO, I, PU L16 VDDNF EBI PD7 I/O – – D17 O – – – – PIO, I, PU L17 VDDNF EBI PD8 I/O – – D18 O – – – – PIO, I, PU K17 VDDNF EBI PD9 I/O – – D19 O – – – – PIO, I, PU K16 VDDNF EBI PD10 I/O – – D20 O – – – – PIO, I, PU K15 VDDNF EBI PD11 I/O – – D21 O – – – – PIO, I, PU J17 VDDNF EBI PD12 I/O – – D22 O – – – – PIO, I, PU J16 VDDNF EBI PD13 I/O – – D23 O – – – – PIO, I, PU H17 VDDNF EBI PD14 I/O – – D24 O – – – – PIO, I, PU J15 VDDNF EBI PD15 I/O – – D25 O A20 O – – A20, O, PD G17 VDDNF EBI PD16 I/O – – D26 O A23 O – – A23, O, PD H16 VDDNF EBI PD17 I/O – – D27 O A24 O – – A24, O, PD H15 VDDNF EBI PD18 I/O – – D28 O A25 O – – A25, O, PD F17 VDDNF EBI PD19 I/O – – D29 O NCS2 O – – PIO, I, PU G16 VDDNF EBI PD20 I/O – – D30 O NCS4 O – – PIO, I, PU E17 VDDNF EBI PD21 I/O – – D31 O NCS5 O – – PIO, I, PU H8 H9 H10 VDDIOM POWER VDDIOM I – – – – – – – – I J14 K14 L14 VDDNF POWER VDDNF I – – – – – – – – I J8 J9 J10 K9 K10 GNDIOM GND GNDIOM I – – – – – – – – I P9 P12 VDDIOP0 POWER VDDIOP0 I – – – – – – – – I L3 L4 VDDIOP1 POWER VDDIOP1 I – – – – – – – – I P6 P7 P13 GNDIOP GND GNDIOP I – – – – – – – – I DS60001517A-page 12  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 3-1: BGA217 Pin Description (Continued) Primary Ball Power Rail I/O Type Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST D6 VDDBU POWER VDDBU I – – – – – – – – I D5 B3 GNDBU GND GNDBU I – – – – – – – – I C4 VDDANA POWER VDDANA I – – – – – – – – I B2 GNDANA GND GNDANA I – – – – – – – – I T16 VDDPLL POWER VDDPLL I – – – – – – – – I P14 GNDPLL GND GNDPLL I – – – – – – – – I R14 VDDOSC POWER VDDOSC I – – – – – – – – I R15 VDDUSB POWER VDDUSB I – – – – – – – – I N16 VDDFUSE POWER VDDFUSE I – – – – – – – – I M16 GNDFUSE GND GNDFUSE I – – – – – – – – I T17 GNDUSB GND GNDUSB I – – – – – – – – I C8 G15 J4 P10 VDDCORE POWER VDDCORE I – – – – – – – – I D8 H14 K8 P11 GNDCORE GND GNDCORE I – – – – – – – – I B14 VDDIOM EBI D0 I/O – – – – – – – – O, PD A14 VDDIOM EBI D1 I/O – – – – – – – – O, PD C14 VDDIOM EBI D2 I/O – – – – – – – – O, PD D13 VDDIOM EBI D3 I/O – – – – – – – – O, PD C13 VDDIOM EBI D4 I/O – – – – – – – – O, PD B13 VDDIOM EBI D5 I/O – – – – – – – – O, PD A13 VDDIOM EBI D6 I/O – – – – – – – – O, PD C12 VDDIOM EBI D7 I/O – – – – – – – – O, PD D12 VDDIOM EBI D8 I/O – – – – – – – – O, PD B12 VDDIOM EBI D9 I/O – – – – – – – – O, PD C11 VDDIOM EBI D10 I/O – – – – – – – – O, PD D11 VDDIOM EBI D11 I/O – – – – – – – – O, PD A12 VDDIOM EBI D12 I/O – – – – – – – – O, PD B11 VDDIOM EBI D13 I/O – – – – – – – – O, PD A11 VDDIOM EBI D14 I/O – – – – – – – – O, PD C10 VDDIOM EBI D15 I/O – – – – – – – – O, PD D17 VDDIOM EBI_O A0 O NBS0 O – – – – – – O, PD C17 VDDIOM EBI_O A1 O NBS2/ DQM2/ NWR2 O – – – – – – O, PD F16 VDDIOM EBI_O A2 O – – – – – – – – O, PD B17 VDDIOM EBI_O A3 O – – – – – – – – O, PD A17 VDDIOM EBI_O A4 O – – – – – – – – O, PD  2017 Microchip Technology Inc. DS60001517A-page 13 SAM9N12/SAM9CN11/SAM9CN12 Table 3-1: BGA217 Pin Description (Continued) Primary Ball Power Rail I/O Type Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST F15 VDDIOM EBI_O A5 O – – – – – – – – O, PD E16 VDDIOM EBI_O A6 O – – – – – – – – O, PD D16 VDDIOM EBI_O A7 O – – – – – – – – O, PD E15 VDDIOM EBI_O A8 O – – – – – – – – O, PD G14 VDDIOM EBI_O A9 O – – – – – – – – O, PD C16 VDDIOM EBI_O A10 O – – – – – – – – O, PD F14 VDDIOM EBI_O A11 O – – – – – – – – O, PD B16 VDDIOM EBI_O A12 O – – – – – – – – O, PD A16 VDDIOM EBI_O A13 O – – – – – – – – O, PD C15 VDDIOM EBI_O A14 O – – – – – – – – O, PD D15 VDDIOM EBI_O A15 O – – – – – – – – O, PD B15 VDDIOM EBI_O A16 O BA0 O – – – – – – O, PD E14 VDDIOM EBI_O A17 O BA1 O – – – – – – O, PD A15 VDDIOM EBI_O A18 O BA2 O – – – – – – O, PD D14 VDDIOM EBI_O A19 O – – – – – – – – O, PD B7 VDDIOM EBI_O NCS0 O – – – – – – – – O, PU C5 VDDIOM EBI_O NCS1 O SDCS O – – – – – – O, PU C7 VDDIOM EBI_O NRD O – – – – – – – – O, PU A6 VDDIOM EBI_O NWR0 O NWRE O – – – – – – O, PU C6 VDDIOM EBI_O NWR1 O NBS1 O – – – – – – O, PU D7 VDDIOM EBI_O NWR3 O NBS3/ DQM3 O – – – – – – O, PU A10 VDDIOM EBI_CLK SDCK O – – – – – – – – O A9 VDDIOM EBI_CLK #SDCK O – – – – – – – – O D10 VDDIOM EBI_O SDCKE O – – – – – – – – O, PU B9 VDDIOM EBI_O RAS O – – – – – – – – O, PU D9 VDDIOM EBI_O CAS O – – – – – – – – O, PU B10 VDDIOM EBI_O SDWE O – – – – – – – – O, PU B6 VDDIOM EBI_O SDA10 O – – – – – – – – O, PU C9 VDDIOM EBI_O DQM0 O – – – – – – – – O, PU A8 VDDIOM EBI_O DQM1 O – – – – – – – – O, PU B8 VDDIOM EBI DQS0 I/O – – – – – – – – O, PD A7 VDDIOM EBI DQS1 I/O – – – – – – – – O, PD A2 VDDANA POWER ADVREF I – – – – – – – – I P17 VDDUSB USBFS HDP I/O – – – – – – – – O, PD N17 VDDUSB USBFS HDM I/O – – – – – – – – O, PD R17 VDDUSB USBFS DDP I/O – – – – – – – – O, PD R16 VDDUSB USBFS DDM I/O – – – – – – – – O, PD A5 VDDBU SYSC WKUP I – – – – – – – – I, ST B5 VDDBU SYSC SHDN O – – – – – – – – O, PU DS60001517A-page 14  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 3-1: BGA217 Pin Description (Continued) Primary Ball Power Rail I/O Type Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST U15 VDDIOP0 RSTJTAG BMS I – – – – – – – – I, PU, ST B4 VDDBU SYSC JTAGSEL I – – – – – – – – I, PD R12 VDDIOP0 RSTJTAG TCK I – – – – – – – – I, ST R11 VDDIOP0 RSTJTAG TDI I – – – – – – – – I, ST U14 VDDIOP0 RSTJTAG TDO O – – – – – – – – O T13 VDDIOP0 RSTJTAG TMS I – – – – – – – – I, ST T14 VDDIOP0 RSTJTAG RTCK O – – – – – – – – O R13 VDDIOP0 RSTJTAG NRST I/O – – – – – – – – I, PU, ST T15 VDDIOP0 RSTJTAG NTRST I – – – – – – – – I, PU, ST A4 VDDBU CLOCK XIN32 I – – – – – – – – I A3 VDDBU CLOCK XOUT32 O – – – – – – – – O U17 VDDIOP0 CLOCK XIN I – – – – – – – – I U16 VDDIOP0 CLOCK XOUT O – – – – – – – – O N15 NC – – – – – – – – – – – –  2017 Microchip Technology Inc. DS60001517A-page 15 SAM9N12/SAM9CN11/SAM9CN12 3.4 247-ball BGA Package Pinout Table 3-2: BGA247 Pin Description Primary Ball Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST P3 VDDIOP0 GPIO PA0 I/O – – TXD0 O SPI1_NPCS1 O – – PIO, I, PU, ST R2 VDDIOP0 GPIO PA1 I/O – – RXD0 I SPI0_NPCS2 O – – PIO, I, PU, ST R9 VDDIOP0 GPIO PA2 I/O – – RTS0 O – – – – PIO, I, PU, ST N5 VDDIOP0 GPIO PA3 I/O – – CTS0 I – – – – PIO, I, PU, ST P10 VDDIOP0 GPIO PA4 I/O – – SCK0 I/O – – – – PIO, I, PU, ST R3 VDDIOP0 GPIO PA5 I/O – – TXD1 O – – – – PIO, I, PU, ST R10 VDDIOP0 GPIO PA6 I/O – – RXD1 I – – – – PIO, I, PU, ST T2 VDDIOP0 GPIO PA7 I/O – – TXD2 O SPI0_NPCS1 O – – PIO, I, PU, ST P6 VDDIOP0 GPIO PA8 I/O – – RXD2 I SPI1_NPCS0 I/O – – PIO, I, PU, ST T3 VDDIOP0 GPIO PA9 I/O – – DRXD I – – – – PIO, I, PU, ST U2 VDDIOP0 GPIO PA10 I/O – – DTXD O – – – – PIO, I, PU, ST P5 VDDIOP0 GPIO PA11 I/O – – SPI0_MISO I/O MCDA4 I/O – – PIO, I, PU, ST V2 VDDIOP0 GPIO PA12 I/O – – SPI0_MOSI I/O MCDA5 I/O – – PIO, I, PU, ST V1 VDDIOP0 GPIO_CLK PA13 I/O – – SPI0_SPCK I/O MCDA6 I/O – – PIO, I, PU, ST W2 VDDIOP0 GPIO PA14 I/O – – SPI0_NPCS0 I/O MCDA7 I/O – – PIO, I, PU, ST W1 VDDIOP0 GPIO PA15 I/O – – MCDA0 I/O – – – – PIO, I, PU, ST V3 VDDIOP0 GPIO PA16 I/O – – MCCDA I/O – – – – PIO, I, PU, ST R5 VDDIOP0 GPIO_CLK PA17 I/O – – MCCK I/O – – – – PIO, I, PU, ST U3 VDDIOP0 GPIO PA18 I/O – – MCDA1 I/O – – – – PIO, I, PU, ST V4 VDDIOP0 GPIO PA19 I/O – – MCDA2 I/O – – – – PIO, I, PU, ST U4 VDDIOP0 GPIO PA20 I/O – – MCDA3 I/O – – – – PIO, I, PU, ST V5 VDDIOP0 GPIO PA21 I/O – – TIOA0 I/O SPI1_MISO I/O – – PIO, I, PU, ST U5 VDDIOP0 GPIO PA22 I/O – – TIOA1 I/O SPI1_MOSI I/O – – PIO, I, PU, ST R6 VDDIOP0 GPIO_CLK PA23 I/O – – TIOA2 I/O SPI1_SPCK I/O – – PIO, I, PU, ST R7 VDDIOP0 GPIO PA24 I/O – – TCLK0 I TK I/O – – PIO, I, PU, ST U6 VDDIOP0 GPIO PA25 I/O – – TCLK1 I TF I/O – – PIO, I, PU, ST V6 VDDIOP0 GPIO PA26 I/O – – TCLK2 I TD O – – PIO, I, PU, ST R8 VDDIOP0 GPIO PA27 I/O – – TIOB0 I/O RD I – – PIO, I, PU, ST U7 VDDIOP0 GPIO PA28 I/O – – TIOB1 I/O RK I/O – – PIO, I, PU, ST P11 VDDIOP0 GPIO PA29 I/O – – TIOB2 I/O RF I/O – – PIO, I, PU, ST V7 VDDIOP0 GPIO PA30 I/O – – TWD0 I/O SPI1_NPCS3 O – – PIO, I, PU, ST N12 VDDIOP0 GPIO PA31 I/O – – TWCK0 O SPI1_NPCS2 O – – PIO, I, PU, ST G6 VDDANA GPIO PB0 I/O – – – – RTS2 O – – PIO, I, PU, ST E3 VDDANA GPIO PB1 I/O – – – – CTS2 I – – PIO, I, PU, ST G5 VDDANA GPIO PB2 I/O – – – – SCK2 I/O – – PIO, I, PU, ST F2 VDDANA GPIO PB3 I/O – – – – SPI0_NPCS3 O – – PIO, I, PU, ST E2 VDDANA GPIO_CLK PB4 I/O – – – – – – – – PIO, I, PU, ST E5 VDDANA GPIO PB5 I/O – – – – – – PIO, I, PU, ST DS60001517A-page 16  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 3-2: BGA247 Pin Description (Continued) Primary Ball Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST C2 VDDANA GPIO_ANA PB6 I/O AD7 I – – – – – – PIO, I, PU, ST B2 VDDANA GPIO_ANA PB7 I/O AD8 I – – – – – – PIO, I, PU, ST A2 VDDANA GPIO_ANA PB8 I/O AD9 I – – – – – – PIO, I, PU, ST B1 VDDANA GPIO_ANA PB9 I/O AD10 I – – PCK1 O – – PIO, I, PU, ST A1 VDDANA GPIO_ANA PB10 I/O AD11 I – – PCK0 O – – PIO, I, PU, ST C7 VDDANA GPIO_ANA PB11 I/O AD0 I – – PWM0 O – – PIO, I, PU, ST C8 VDDANA GPIO_ANA PB12 I/O AD1 I – – PWM1 O – – PIO, I, PU, ST D3 VDDANA GPIO_ANA PB13 I/O AD2 I – – PWM2 O – – PIO, I, PU, ST F5 VDDANA GPIO_ANA PB14 I/O AD3 I – – PWM3 O – – PIO, I, PU, ST E6 VDDANA GPIO_ANA PB15 I/O AD4 I – – – – – – PIO, I, PU, ST C9 VDDANA GPIO_ANA PB16 I/O AD5 I – – – I – – PIO, I, PU, ST D2 VDDANA GPIO_ANA PB17 I/O AD6 I – – – I – – PIO, I, PU, ST E7 VDDANA GPIO PB18 I/O – – IRQ I ADTRG I – – PIO, I, PU, ST F3 VDDIOP1 GPIO PC0 I/O – – LCDDAT0 O – – TWD1 I/O PIO, I, PU, ST G2 VDDIOP1 GPIO PC1 I/O – – LCDDAT1 O – – TWCK1 O PIO, I, PU, ST L7 VDDIOP1 GPIO PC2 I/O – – LCDDAT2 O – – TIOA3 I/O PIO, I, PU, ST G3 VDDIOP1 GPIO PC3 I/O – – LCDDAT3 O – – TIOB3 I/O PIO, I, PU, ST H5 VDDIOP1 GPIO PC4 I/O – – LCDDAT4 O – – TCLK3 I PIO, I, PU, ST M7 VDDIOP1 GPIO PC5 I/O – – LCDDAT5 O – – TIOA4 I/O PIO, I, PU, ST H3 VDDIOP1 GPIO PC6 I/O – – LCDDAT6 O – – TIOB4 I/O PIO, I, PU, ST H2 VDDIOP1 GPIO PC7 I/O – – LCDDAT7 O – – TCLK4 I PIO, I, PU, ST J3 VDDIOP1 GPIO PC8 I/O – – LCDDAT8 O – – UTXD0 O PIO, I, PU, ST M8 VDDIOP1 GPIO PC9 I/O – – LCDDAT9 O – – URXD0 I PIO, I, PU, ST J5 VDDIOP1 GPIO PC10 I/O – – LCDDAT10 O – – PWM0 O PIO, I, PU, ST K6 VDDIOP1 GPIO PC11 I/O – – LCDDAT11 O – – PWM1 O PIO, I, PU, ST P9 VDDIOP1 GPIO PC12 I/O – – LCDDAT12 O – – TIOA5 I/O PIO, I, PU, ST L6 VDDIOP1 GPIO PC13 I/O – – LCDDAT13 O – – TIOB5 I/O PIO, I, PU, ST J2 VDDIOP1 GPIO PC14 I/O – – LCDDAT14 O – – TCLK5 I PIO, I, PU, ST K3 VDDIOP1 GPIO_CLK PC15 I/O – – LCDDAT15 O – – PCK0 O PIO, I, PU, ST K2 VDDIOP1 GPIO PC16 I/O – – LCDDAT16 O – – UTXD1 O PIO, I, PU, ST K5 VDDIOP1 GPIO PC17 I/O – – LCDDAT17 O – – URXD1 I PIO, I, PU, ST L3 VDDIOP1 GPIO PC18 I/O – – LCDDAT18 O – – PWM0 O PIO, I, PU, ST N8 VDDIOP1 GPIO PC19 I/O – – LCDDAT19 O – – PWM1 O PIO, I, PU, ST L2 VDDIOP1 GPIO PC20 I/O – – LCDDAT20 O – – PWM2 O PIO, I, PU, ST P8 VDDIOP1 GPIO PC21 I/O – – LCDDAT21 O – – PWM3 O PIO, I, PU, ST M3 VDDIOP1 GPIO PC22 I/O – – LCDDAT22 O TXD3 O – – PIO, I, PU, ST L5 VDDIOP1 GPIO PC23 I/O – – LCDDAT23 O RXD3 I – – PIO, I, PU, ST N6 VDDIOP1 GPIO PC24 I/O – – LCDDISP O RTS3 O – – PIO, I, PU, ST N2 VDDIOP1 GPIO PC25 I/O – – – – CTS3 I – – PIO, I, PU, ST P7 VDDIOP1 GPIO PC26 I/O – – LCDPWM O SCK3 I/O – – PIO, I, PU, ST  2017 Microchip Technology Inc. DS60001517A-page 17 SAM9N12/SAM9CN11/SAM9CN12 Table 3-2: BGA247 Pin Description (Continued) Primary Ball Power Rail I/O Type Signal Alternate Dir Signal PIO Peripheral A Dir Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, ST M2 VDDIOP1 GPIO PC27 I/O – – LCDVSYNC O – – RTS1 O PIO, I, PU, ST M5 VDDIOP1 GPIO PC28 I/O – – LCDHSYNC O – – CTS1 I PIO, I, PU, ST N3 VDDIOP1 GPIO_CLK PC29 I/O – – LCDDEN O – – SCK1 I/O PIO, I, PU, ST M6 VDDIOP1 GPIO_CLK2 PC30 I/O – – LCDPCK O – – – – PIO, I, PU, ST P2 VDDIOP1 GPIO PC31 I/O – – FIQ I – – PCK1 O PIO, I, PU, ST R14 VDDNF EBI PD0 I/O – – NANDOE O – – – – PIO, I, PU R15 VDDNF EBI PD1 I/O – – NANDWE O – – – – PIO, I, PU T17 VDDNF EBI PD2 I/O – – A21/NANDALE O – – – – A21,O, PD P15 VDDNF EBI PD3 I/O – – A22/NANDCLE O – – – – A22,O, PD R17 VDDNF EBI PD4 I/O – – NCS3 O – – – – PIO, I, PU M15 VDDNF EBI PD5 I/O – – NWAIT I – – – – PIO, I, PU N15 VDDNF EBI PD6 I/O – – D16 O – – – – PIO, I, PU V13 VDDNF EBI PD7 I/O – – D17 O – – – – PIO, I, PU L14 VDDNF EBI PD8 I/O – – D18 O – – – – PIO, I, PU W18 VDDNF EBI PD9 I/O – – D19 O – – – – PIO, I, PU V18 VDDNF EBI PD10 I/O – – D20 O – – – – PIO, I, PU W19 VDDNF EBI PD11 I/O – – D21 O – – – – PIO, I, PU V19 VDDNF EBI PD12 I/O – – D22 O – – – – PIO, I, PU N18 VDDNF EBI PD13 I/O – – D23 O – – – – PIO, I, PU L15 VDDNF EBI PD14 I/O – – D24 O – – – – PIO, I, PU N17 VDDNF EBI PD15 I/O – – D25 O A20 O – – A20, O, PD M18 VDDNF EBI PD16 I/O – – D26 O A23 O – – A23, O, PD M17 VDDNF EBI PD17 I/O – – D27 O A24 O – – A24, O, PD P17 VDDNF EBI PD18 I/O – – D28 O A25 O – – A25, O, PD L18 VDDNF EBI PD19 I/O – – D29 O NCS2 O – – PIO, I, PU K15 VDDNF EBI PD20 I/O – – D30 O NCS4 O – – PIO, I, PU L17 VDDNF EBI PD21 I/O – – D31 O NCS5 O – – PIO, I, PU E8 E9 E13 F7 F8 F9 G14 VDDIOM POWER VDDIOM I – – – – – – – – I VDDNF POWER VDDNF I – – – – – – – – I M14 P13 U10 V9 V10 V11 DS60001517A-page 18  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 3-2: BGA247 Pin Description (Continued) Primary Ball Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST H6 H7 J6 J7 J8 F10 F11 F12 F13 F14 F15 F16 GNDIOM GND GNDIOM I – – – – – – – – I N11 M12 M13 VDDIOP0 POWER VDDIOP0 I – – – – – – – – I M9 M10 M11 VDDIOP1 POWER VDDIOP1 I – – – – – – – – I L10 L11 L12 L13 V14 GNDIOP GND GNDIOP I – – – – – – – – I B6 VDDBU POWER VDDBU I – – – – – – – – I B7 GNDBU GND GNDBU I – – – – – – – – I F6 VDDANA POWER VDDANA I – – – – – – – – I C3 GNDANA GND GNDANA I – – – – – – – – I V17 VDDPLL POWER VDDPLL I – – – – – – – – I U16 GNDPLL GND GNDPLL I – – – – – – – – I P14 VDDFUSE POWER VDDFUSE I – – – – – – – – I N14 GNDFUSE GND GNDFUSE I – – – – – – – – I R12 VDDOSC POWER VDDOSC I – – – – – – – – I U13 VDDUSB POWER VDDUSB I – – – – – – – – I U17 GNDUSB GND GNDUSB I – – – – – – – – I J12 J13 J14 K10 K11 K12 K13 K14 U15 VDDCORE POWER VDDCORE I – – – – – – – – I H9 J9 J10 J11 K7 K8 K9 L8 L9 GNDCORE GND GNDCORE I – – – – – – – – I A19 VDDIOM EBI D0 I/O – – – – – – – – O, PD E15 VDDIOM EBI D1 I/O – – – – – – – – O, PD  2017 Microchip Technology Inc. DS60001517A-page 19 SAM9N12/SAM9CN11/SAM9CN12 Table 3-2: BGA247 Pin Description (Continued) Primary Ball Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST C18 VDDIOM EBI D2 I/O – – – – – – – – O, PD D15 VDDIOM EBI D3 I/O – – – – – – – – O, PD B17 VDDIOM EBI D4 I/O – – – – – – – – O, PD E14 VDDIOM EBI D5 I/O – – – – – – – – O, PD C16 VDDIOM EBI D6 I/O – – – – – – – – O, PD A18 VDDIOM EBI D7 I/O – – – – – – – – O, PD B15 VDDIOM EBI D8 I/O – – – – – – – – O, PD G12 VDDIOM EBI D9 I/O – – – – – – – – O, PD C14 VDDIOM EBI D10 I/O – – – – – – – – O, PD D13 VDDIOM EBI D11 I/O – – – – – – – – O, PD A16 VDDIOM EBI D12 I/O – – – – – – – – O, PD A14 VDDIOM EBI D13 I/O – – – – – – – – O, PD B13 VDDIOM EBI D14 I/O – – – – – – – – O, PD H13 VDDIOM EBI D15 I/O – – – – – – – – O, PD J15 VDDIOM EBI_O A0 O NBS0 O – – – – – – O K18 VDDIOM EBI_O A1 O NBS2/ DQM2/ NWR2 O – – – – – – O K17 VDDIOM EBI_O A2 O – – – – – – – – O H15 VDDIOM EBI_O A3 O – – – – – – – – O J18 VDDIOM EBI_O A4 O – – – – – – – – O J17 VDDIOM EBI_O A5 O – – – – – – – – O G17 VDDIOM EBI_O A6 O – – – – – – – – O H17 VDDIOM EBI_O A7 O – – – – – – – – O H18 VDDIOM EBI_O A8 O – – – – – – – – O H14 VDDIOM EBI_O A9 O – – – – – – – – O G18 VDDIOM EBI_O A10 O – – – – – – – – O F18 VDDIOM EBI_O A11 O – – – – – – – – O F17 VDDIOM EBI_O A12 O – – – – – – – – O E19 VDDIOM EBI_O A13 O – – – – – – – – O D19 VDDIOM EBI_O A14 O – – – – – – – – O E18 VDDIOM EBI_O A15 O – – – – – – – – O G15 VDDIOM EBI_O A16 O BA0 O – – – – – – O E16 VDDIOM EBI_O A17 O BA1 O – – – – – – O B19 VDDIOM EBI_O A18 O BA2 O – – – – – – O D17 VDDIOM EBI_O A19 O – – – – – – – – O B9 VDDIOM EBI_O NCS0 O – – – – – – – – O, PU B8 VDDIOM EBI_O NCS1 O SDCS O – – – – – – O, PU E10 VDDIOM EBI_O NRD O – – – – – – – – O, PU G10 VDDIOM EBI_O NWR0 O NWRE O – – – – – – O, PU C10 VDDIOM EBI_O NWR1 O NBS1 O – – – – – – O, PU DS60001517A-page 20  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 3-2: BGA247 Pin Description (Continued) Primary Ball Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, ST G9 VDDIOM EBI_O NWR3 O NBS3/ DQM3 O – – – – – – O, PU B10 VDDIOM EBI_CLK SDCK O – – – – – – – – O B11 VDDIOM EBI_CLK #SDCK O – – – – – – – – O C12 VDDIOM EBI_O SDCKE O – – – – – – – – O, PU G11 VDDIOM EBI_O RAS O – – – – – – – – O, PU E12 VDDIOM EBI_O CAS O – – – – – – – – O, PU H12 VDDIOM EBI_O SDWE O – – – – – – – – O, PU H10 VDDIOM EBI_O SDA10 O – – – – – – – – O, PU A12 VDDIOM EBI_O DQM0 O – – – – – – – – O, PU C11 VDDIOM EBI_O DQM1 O – – – – – – – – O, PU H11 VDDIOM EBI DQS0 I/O – – – – – – – – I, PD E11 VDDIOM EBI DQS1 I/O – – – – – – – – I, PD B3 VDDANA POWER ADVREF I – – – – – – – – I T18 VDDUSB USBFS HDP I/O – – – – – – – – O, PD U18 VDDUSB USBFS HDM I/O – – – – – – – – O, PD P18 VDDUSB USBFS DDP I/O – – – – – – – – O, PD R18 VDDUSB USBFS DDM I/O – – – – – – – – O, PD C6 VDDBU SYSC WKUP I – – – – – – – – I, ST G8 VDDBU SYSC SHDN O – – – – – – – – O, PU U14 VDDIOP0 RSTJTAG BMS I – – – – – – – – I, PU, ST C4 VDDBU SYSC JTAGSEL I – – – – – – – – I, PD C5 VDDBU SYSC TST I – – – – – – – – I, PD, ST V8 VDDIOP0 RSTJTAG TCK I – – – – – – – – I, ST U8 VDDIOP0 RSTJTAG TDI I – – – – – – – – I, ST P12 VDDIOP0 RSTJTAG TDO O – – – – – – – – O R11 VDDIOP0 RSTJTAG TMS I – – – – – – – – I, ST V12 VDDIOP0 RSTJTAG RTCK O – – – – – – – – O U11 VDDIOP0 RSTJTAG NRST I/O – – – – – – – – I, PU, ST U9 VDDIOP0 RSTJTAG NTRST I – – – – – – – – I, PU, ST B4 VDDBU CLOCK XIN32 I – – – – – – – – I B5 VDDBU CLOCK XOUT32 O – – – – – – – – O V16 VDDIOP0 CLOCK XIN I – – – – – – – – I V15 VDDIOP0 CLOCK XOUT O – – – – – – – – O H8 – – NC – – – – – – – – – – U12 – – NC – – – – – – – – – – R13 – – NC – – – – – – – – – –  2017 Microchip Technology Inc. DS60001517A-page 21 SAM9N12/SAM9CN11/SAM9CN12 4. Power Considerations 4.1 Power Supplies The SAM9N12/CN11/CN12 has several types of power supply pins. Table 4-1 defines the different power supplies rails and the estimated power consumption at typical voltage. For details about power-up and power-down sequences, refer to Section 4.2 ”Power Sequence Requirements”. Table 4-1: SAM9N12/CN11/CN12 Power Supplies Name Voltage Range, Nominal Associated Ground VDDCORE 0.9–1.1V, 1.0V GNDCORE Core, including the processor, the embedded memories and the peripherals, the internal 12 MHz RC VDDIOM 1.65–1.95V, 1.8V 3.0–3.6V, 3.3V GNDIOM External Memory Interface I/O lines VDDNF 1.65–1.95V, 1.8V 3.0–3.6V, 3.3V GNDIOM NAND Flash I/O and control, D16–D32 and multiplexed SMC lines VDDIOP0 1.65–3.6V GNDIOP Part of Peripherals I/O lines VDDIOP1 1.65–3.6V GNDIOP Part of Peripherals I/O lines VDDBU 1.65–3.6V GNDBU Slow Clock oscillator, the internal 32 Kbyte RC and a part of the System Controller VDDUSB 3.0–3.6V, 3.3V GNDUSB USB interface VDDPLL 0.9–1.1V, 1.0V GNDPLL PLL cells VDDOSC 1.65–3.6V GNDPLL Main Oscillator cells VDDANA 3.0–3.6V, 3.3V GNDANA Analog to Digital Converter VDDFUSE 3.0–3.6V, 3.3V GNDFUSE Fuse box for programming 4.2 Powers Power Sequence Requirements The AT91 board design must comply with the power-up guidelines below to guarantee reliable operation of the device. Any deviation from these sequences may prevent the device from booting. DS60001517A-page 22  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 4.2.1 Power-Up Sequence Figure 4-1: VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > VOH VOH VDDIO > VIH VIH VDDCORE VDDCOREtyp VT+ t < t1 > Core Supply POR Output SLCK VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources reach their target values prior to the release of POR. • VDDIOP must be ≥ VIH (refer to Table 47-2 “DC Characteristics”, for more details), (tRST + t1) at the latest, after VDDCORE has reached VT+. • VDDIOM must reach VOH (refer to Table 47-2 “DC Characteristics”, for more details), (tRST + t1 + t2) at the latest, after VDDCORE has reached VT+ - tRST is a POR characteristic - t1 = 3 × tSLCK - t2 = 16 × tSLCK The tSLCK min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz). - tRST = 30 µs - t1 = 66 µs - t2 = 352 µs • VDDPLL is to be established prior to VDDCORE to ensure the PLL is powered once enabled into the ROM code. As a conclusion, establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE at last, to ensure a reliable operation of the device. 4.2.2 Power-Down Sequence To ensure that the device does not operate outside the operating conditions defined in Table 4-1 “SAM9N12/CN11/CN12 Power Supplies”, it is good practice to first place the device in reset state before removing its power supplies. No specific sequencing is required with respect to its supply channels as long as the NRST line is held active during the the power-down phase.  2017 Microchip Technology Inc. DS60001517A-page 23 SAM9N12/SAM9CN11/SAM9CN12 Figure 4-2: Recommended Power-Down Sequence tRSTPD NRST No specific order and no specific timing required among the channels VDDBU VDDCORE VDDPLLA VDDUTMIC VDDNF VDDANA VDDOSC VDDIOM VDDIOP0 VDDIOP1 VDDUTMII time Table 4-2: Power-down Timing Specification Symbol Parameter Conditions tRSTPD Reset Delay at Power-Down From NRST low to the first supply turn-off DS60001517A-page 24 Min Max Unit 0 – ms  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 5. Memories 5.1 Memory Mapping Figure 5-1 provides the device memory map. A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 6 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access.  2017 Microchip Technology Inc. DS60001517A-page 25 SAM9N12/SAM9CN11/SAM9CN12 Figure 5-1: SAM9N12/CN11/CN12 Memory Map Address Memory Space Internal Memory Mapping 0x0000 0000 0x0000 0000 Internal Memories 0x0020 0000 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 0x2FFF FFFF 0x3000 0000 0x0030 0000 256 Mbytes 0x0040 0000 0x0050 0000 EBI Chip Select 1/ DDR2/LPDDR SDR/LPSDR 256 Mbytes EBI Chip Select 2 256 Mbytes EBI Chip Select 3/ NANDFlash 256 Mbytes Boot Memory (1) 1 Mbyte 0x0010 0000 256 Mbytes ROM 1 Mbyte Undefined (Abort) 1 Mbyte SRAM 1 Mbyte Undefined (Abort) 1 Mbyte UHP RAM 1 Mbyte 0x0060 0000 Undefined (Abort) 0x0FFF FFFF 0x3FFF FFFF 0x4000 0000 0x4FFF FFFF 0x5000 0000 EBI Chip Select 4 Peripheral Mapping 0xF000 0000 SPI0 0xF000 4000 256 Mbytes SPI1 System Controller Mapping 0xF000 8000 MCI 0x5FFF FFFF 0x6000 0000 0xFFFF C000 0xF000 C000 EBI Chip Select 5 256 Mbytes SSC 0x6FFF FFFF 0x7000 0000 Reserved AES (2) 0xF001 0000 0xF001 4000 SHA (2) 0xF001 8000 0xFFFF DC00 FUSE 512 bytes MATRIX 512 bytes PMECC 1536 bytes 0xFFFF DE00 0xFFFF E000 Reserved 0xFFFF E600 0xF800 8000 TC0, TC1, TC2 TC3, TC4, TC5 0xFFFF EA00 TWI0 0xFFFF EC00 0xF801 0000 0xF801 4000 TWI1 0xF801 8000 Reserved 0xFFFF F000 USART0 0xFFFF F200 USART1 0xFFFF F400 USART2 0xFFFF F600 0xF802 0000 0xF802 4000 1,792 Mbytes 0xF802 8000 USART3 0xF802 C000 Reserved 0xFFFF FE00 UDP 0xFFFF FE10 0xF803 C000 0xFFFF FE20 0xF804 4000 UART1 0xF804 8000 TRNG ADC 0xF805 0000 Internal Peripherals 256 Mbytes 0xFFFF FFFF Reserved 512 bytes Reserved 512 bytes AIC 512 bytes DBGU 512 bytes PIOA 512 bytes PIOB 512 bytes PIOC 512 bytes PIOD 512 bytes PMC 512 bytes RST 16 bytes SHDWC 16 bytes Reserved 16 bytes PIT 16 bytes WDT 16 bytes SCKC 4 bytes 0xFFFF FE30 0xFFFF FE40 0xFFFF FE50 0xFFFF FE60 0xFFFF FE70 SYSC Reserved GPBR 16 bytes Reserved 0xFFFF FEB0 0xFFFF C000 0xFFFF FFFF DMAC 0xFFFF FE54 0xF804 C000 0xEFFF FFFF 0xF000 0000 512 bytes 0xFFFF FC00 LCDC UART0 SMC 0xFFFF FA00 0xF803 8000 0xF804 0000 512 bytes 0xFFFF F800 0xF803 4000 PWM 512 bytes 0xFFFF EE00 0xF801 C000 Undefined (Abort) PMERRLOC DDR2/LPDDR SDR/LPSDR 0xFFFF E800 0xF800 C000 RTC 0xFFFF FEC0 0xFFFF FFFF 16 bytes Reserved Notes: 1. Can be ROM, EBI1_NCS0 or SRAM depending on BMS and REMAP 2. Reserved for SAM9N12 DS60001517A-page 26  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 5.2 5.2.1 Embedded Memories Internal SRAM The SAM9N12/CN11/CN12 embeds a total of 32 Kbytes high-speed SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. 5.2.2 Internal ROM The SAM9CN12 contains the secure bootloader (standard bootloader for SAM9N12 and SAM9CN11) and specific tables used to compute SLC and MLC NAND Flash ECC. The ROM is mapped at address 0x0010 0000. It is also accessible at address 0x0 (BMS = 1) after the reset and before the Remap Command. 5.3 External Memories Overview The SAM9N12/CN11/CN12 features an External Bus Interface to provide interface to a wide range of external memories and to any parallel peripheral. 5.3.1 External Bus Interface • Integrates three External Memory Controllers: - Static Memory Controller - DDR2/SDRAM Controller - MLC NAND Flash ECC Controller • Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select) • Up to 6 chips selects, Configurable Assignment: - Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5 - DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1 - NAND Flash support on NCS3 5.3.2 Static Memory Controller • 8- or 16-bit Data Bus • Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 16-byte page size) • Multiple device adaptability - Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time • Slow Clock mode supported 5.3.3 DDR-SDRAM Controller • Supports DDR2-SDRAM, Low-power DDR1-SDRAM, SDR-SDRAM and Low-power SDR-SDRAM • Numerous Configurations Supported - 2K, 4K, 8K, 16K Row Address Memory Parts - SDRAM with 4 Internal Banks - SDR-SDRAM with 16-bit or 32-bit Data Path - DDR-SDRAM with 16-bit Data Path - One Chip Select for SDRAM Device (256 Mbytes Address Space) • Programming Facilities - Multibank Ping-pong Access (Up to 4 Banks or 8 Banks Opened at Same Time = Reduced Average Latency of Transactions) - Timing Parameters Specified by Software - Automatic Refresh Operation, Refresh Rate is Programmable - Automatic Update of DS, TCR and PASR Parameters (Low-power SDRAM Devices)  2017 Microchip Technology Inc. DS60001517A-page 27 SAM9N12/SAM9CN11/SAM9CN12 • Energy-saving Capabilities - Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported • SDRAM Power-up Initialization by Software • CAS Latency of 2, 3 Supported • Reset Function Supported (DDR2-SDRAM) • ODT (On-die Termination) Not Supported • Auto Precharge Command Not Used • SDR-SDRAM with 16-bit Datapath and Eight Columns Not Supported • DDR2-SDRAM with Eight Internal Banks Supported • Linear and interleaved decoding supported • Clock Frequency Change in Precharge Power-down Mode Not Supported • OCD (Off-chip Driver) Mode Not Supported 5.3.4 • • • • • • • • • Multibit Error Correcting Code Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes Programmable Error Correcting Capability: 2, 4, 8, 16 and 24 bit of errors per block Programmable block size: 512 bytes or 1024 bytes Programmable number of block per page: 1, 2, 4 or 8 blocks of data per page Programmable spare area size Supports spare area ECC protection Supports 8 Kbytes page size using 1024 bytes/block and 4 Kbytes page size using 512 bytes/block Multibit Error detection is interrupt driven 5.3.5 • • • • Programmable Multibit Error Correction Code (PMECC) Programmable Multi-bit ECC Error Location (PMERRLOC) Provides hardware acceleration for determining roots of polynomials defined over a finite field Programmable finite Field GF(2^13) or GF(2^14) Finds roots of error-locator polynomial. Programmable number of roots. DS60001517A-page 28  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 6. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. 6.1 System Controller Mapping The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF E400 and 0xFFFF FFFF. However, all the registers of the System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard Arm instruction set, as the Load/Store instruction have an indexing mode of ±4 Kbytes. Figure 6-1 shows the System Controller block diagram. Figure 5-1 shows the mapping of the User Interfaces of the System Controller peripherals.  2017 Microchip Technology Inc. DS60001517A-page 29 SAM9N12/SAM9CN11/SAM9CN12 6.2 System Controller Block DIagram Figure 6-1: SAM9N12/CN11/CN12 System Controller Block Diagram System Controller VDDCORE Powered irq fiq periph_irq[2..30] nirq nfiq Advanced Interrupt Controller pit_irq int ntrst por_ntrst wdt_irq dbgu_irq pmc_irq Arm926EJ-S proc_nreset PCK peripheral clock periph_nreset dbgu_irq Debug Unit debug dbgu_txd dbgu_rxd peripheral clock debug periph_nreset Periodic Interval Timer pit_irq SLCK debug idle proc_nreset Watchdog Timer wdt_irq jtag_nreset Boundary Scan TAP Controller MCK periph_nreset Bus Matrix wdt_fault WDRPROC NRST por_ntrst jtag_nreset VDDCORE POR Reset Controller periph_nreset proc_nreset backup_nreset VDDBU VDDBU POR VDDBU Powered SLCK SLCK backup_nreset Real-time Clock rtc_irq rtc_alarm SLCK SHDN WKUP backup_nreset Shutdown Controller UDPCK rtc_alarm 128-bit General-purpose Backup Registers 32 kHz RC Oscillator XIN32 XOUT32 Slow Clock Oscillator periph_irq[23] XIN 16 MHz Main Oscillator USB Device Full Speed Port BSC_CR SCKC_CR 12 MHz RC Oscillator XOUT periph_nreset SLCK periph_clk[2..30] pck[0–1] UHPCK UDPCK int MAINCK PLLB PLLBCK PLLA PLLACK Power Management Controller PCK MCK DDR sysclk LCD Pixel clock pmc_irq idle UHPCK periph_nreset periph_irq[22] USB Host Full Speed Port periph_clk[5..30] periph_nreset periph_nreset periph_nreset periph_clk[2..3] dbgu_rxd PA0–PA31 PB0–PB18 PC0–PC31 PD0–PD21 DS60001517A-page 30 PIO Controllers periph_irq[2..3] irq fiq dbgu_txd Embedded Peripherals periph_irq[5..30] in out enable  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 6.3 • • • • • • Chip Identification Chip ID: 0x819A_07A1 SAM9CN12 Chip ID Extension: 5 SAM9CN11 Chip ID Extension: 9 SAM9N12 Chip ID Extension: 6 JTAG ID: 0x05B3_003F Arm926 TAP ID: 0x0792_603F 6.4 Backup Section The SAM9N12/CN11/CN12 features a backup section that embeds: • • • • • • • RC Oscillator Slow Clock Oscillator Real Time Clock (RTC) Shutdown Controller (SHDWC) 128-bit General-purpose Backup Registers (GPBR) Slow Clock Controller Configuration Register (SCKC_CR) A part of the Reset Controller (RSTC) This backup section is powered by the VDDBU rail.  2017 Microchip Technology Inc. DS60001517A-page 31 SAM9N12/SAM9CN11/SAM9CN12 7. Peripherals 7.1 Peripheral Mapping As shown in Figure 5-1, the Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. 7.2 Peripheral Identifiers Table 7-1 defines the Peripheral Identifiers of the SAM9N12/CN11/CN12. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 7-1: SAM9N12/CN11/CN12 Peripheral Identifiers Instance ID Instance Name Instance Description External Interrupt Wired-or Interrupt 0 AIC Advanced Interrupt Controller FIQ – 1 SYS System Controller Interrupt – DBGU, PMC, SYSC, PMECC, PMERRLOC 2 PIOA, PIOB Parallel I/O Controller A and B – – 3 PIOC, PIOD Parallel I/O Controller C and D – – 4 FUSE FUSE Controller – – 5 USART0 Universal Synchronous Asynchronous Receiver Transceiver 0 – – 6 USART1 Universal Synchronous Asynchronous Receiver Transceiver 1 – – 7 USART2 Universal Synchronous Asynchronous Receiver Transceiver 2 – – 8 USART3 Universal Synchronous Asynchronous Receiver Transceiver 3 – – 9 TWI0 Two-wire Interface 0 – – 10 TWI1 Two-wire Interface 1 – – 11 Reserved – – – 12 HSMCI High Speed Multimedia Card Interface – – 13 SPI0 Serial Peripheral Interface 0 – – 14 SPI1 Serial Peripheral Interface 1 – – 15 UART0 Universal Asynchronous Receiver Transmitter 0 – – 16 UART1 Universal Asynchronous Receiver Transmitter 1 – – 17 TC0 TC1 Timer Counter 0 (channels 0, 1, 2) Timer Counter 1 (channels 3, 4, 5) – – 18 PWM Pulse Width Modulation Controller – – 19 ADC ADC Controller – – 20 DMAC DMA Controller – – 21 Reserved – – – 22 UHP USB Host Port – – 23 UDP USB Device Port – – DS60001517A-page 32  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 7-1: SAM9N12/CN11/CN12 Peripheral Identifiers (Continued) Instance ID Instance Name Instance Description External Interrupt Wired-or Interrupt 24 Reserved – – – 25 LCDC LCD Controller – – 26 Reserved – – – 27 SHA Secure Hash Algorithm – – 28 SSC Synchronous Serial Controller – – 29 AES Advanced Encryption Standard – – 30 TRNG True Random Number Generator – – 31 AIC Advanced Interrupt Controller IRQ – 7.3 Peripheral Interrupts and Clock Control 7.3.1 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • • • • • • • the DDR2/LPDDR Controller the Debug Unit the Periodic Interval Timer the Real-Time Clock the Watchdog Timer the Reset Controller the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 7.3.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 7.4 Peripheral Signal Multiplexing on I/O Lines The SAM9N12/CN11/CN12 features four PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO controller controls 32 lines for PIOA, 19 lines for PIOB, 32 lines for PIOC, and 22 lines for PIOD. Each line can be assigned to one of three peripheral functions: A, B or C. Refer to Section 3. “Package and Pinout” and the package pinouts in Table 3-1 “BGA217 Pin Description” and Table 3-2 “BGA247 Pin Description”. 7.4.1 Reset State The column “Reset State” in Table 3-1 and Table 3-2 indicates the reset state of the line with mnemonics. • “PIO”/”signal” Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO Line is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case on pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. • ‘I’/’O’ Indicates whether the signal is input or output state.  2017 Microchip Technology Inc. DS60001517A-page 33 SAM9N12/SAM9CN11/SAM9CN12 • “PU”/”PD” Indicates whether Pull-up or Pull-down, or nothing is enabled. • “ST” Indicates if Schmitt Trigger is enabled. Note: Example: The PB18 “Reset State” column shows “PIO, I, PU, ST”. That means the line PIO18 is configured as an Input with Pull-Up and Schmitt Trigger enabled. PD14 reset state is “PIO, I, PU”. That means PIO Input with Pull-Up. PD15 reset state is “A20, O, PD” which means output address line 20 with Pull-Down. 7.4.2 PIO Line Selection Peripheral A, B or C is selected via the PIO_ABCDSR1 and PIO_ABCDSR2 registers in the PIO Controller Interface. Table 7-2: PIO Line Selection Px value in PIO_ABCDSR2 Px value in PIO_ABCDSR1 A, B or C 0 0 A 0 1 B 1 0 C 7.5 Fuse Box Features SAM9CN12 embeds 320 One Time Programming (OTP) bits. When the OTP bit is set, it is seen as ‘1’. The user interface allows the user to perform the following operations: 7.5.1 Read • 10 registers SR0–SR9 that reflect OTP bit state • MSK field (write-once) allow user to mask registers SR1 to SR9 • All OTP bits are read as ‘1’ when VDDFUSE is floating, all security features are set. 7.5.2 Write • Done in one 32-bit DATA register • SEL field to select the 32-bit word 0 to 9 7.5.3 Table 7-3: Fuse Mapping OTP Mapping Bits [319:288] Functions config[319:312] RC_trim[311:305] RFU[304:288] [287:256] [255:224] [223:192] [191:160] [159:128] RFU[287:0](1) [127:96] [95:64] [63:32] [31:0] Note 1: For SAM9CN12 these bits are used for Keys and cannot be used by user for another purpose DS60001517A-page 34  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 7-4: Device Configuration OTP Bits Description Bit Number Acronym 312 W 313 B BMS sampling option is disabled if set, system boots only into ROM code 314 J JTAG and tap controller are disabled if set 315 S Secure boot Loader is disabled if set 316 K OTP keys are locked 317–319 Reserved Reserved  2017 Microchip Technology Inc. Function OTP bit writing is disabled if set OTP bits are not accessible in test mode DS60001517A-page 35 SAM9N12/SAM9CN11/SAM9CN12 8. Arm926EJ-S Processor Overview 8.1 Description The Arm926EJ-S processor is a member of the Arm9™ family of general-purpose microprocessors. The Arm926EJ-S implements Arm architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The Arm926EJ-S processor supports the 32-bit Arm and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The Arm926EJ-S processor supports the Arm debug architecture and includes logic to assist in both hardware and software debug. The Arm926EJ-S provides a complete high performance processor subsystem, including: • • • • Arm9EJ-S™ integer core Memory Management Unit (MMU) Separate instruction and data AMBA AHB bus interfaces Separate instruction and data TCM interfaces 8.2 Embedded Characteristics • Arm9EJ-S Based on Arm Architecture v5TEJ with Jazelle® Technology - Three Instruction Sets - Arm High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set - Jazelle 8-bit Instruction Set • 5-Stage Pipeline Architecture when Jazelle is not Used - Fetch (F) - Decode (D) - Execute (E) - Memory (M) - Writeback (W) • 6-Stage Pipeline when Jazelle is Used - Fetch - Jazelle/Decode (Two Cycles) - Execute - Memory - Writeback • ICache and DCache - Virtually-addressed 4-way Set Associative Caches - 8 Words per Line - Critical-word First Cache Refilling - Write-though and Write-back Operation for DCache Only - Pseudo-random or Round-robin Replacement - Cache Lockdown Registers - Cache Maintenance • Write Buffer - 16-word Data Buffer - 4-address Address Buffer - Software Control Drain • DCache Write-back Buffer - 8 Data Word Entries - One Address Entry - Software Control Drain • Tightly-coupled Memory (TCM) - Separate Instruction and Data TCM Interfaces DS60001517A-page 36  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 - Provides a Mechanism for DMA Support • Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for Large Pages and Small Pages - 16 Embedded Domains - 64 Entry Instruction TLB and 64 Entry Data TLB • Memory Access - 8-, 16-, and 32-bit Data Types - Separate AMBA AHB Buses for Both the 32-bit Data Interface and the 32-bit Instructions Interface • Bus Interface Unit - Arbitrates and Schedules AHB Requests - Enables Multi-layer AHB to be Implemented - Increases Overall Bus Bandwidth - Makes System Architecture Mode Flexible  2017 Microchip Technology Inc. DS60001517A-page 37 SAM9N12/SAM9CN11/SAM9CN12 8.3 Block Diagram Figure 8-1: Arm926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor External Coprocessors ETM9 External Coprocessor Interface Trace Port Interface Write Data Arm9EJ-S Processor Core Instruction Fetches Read Data Data Address Instruction Address MMU DTCM Interface Data TLB Instruction TLB ITCM Interface Data TCM Instruction TCM Instruction Address Data Address Data Cache AHB Interface and Write Buffer Instruction Cache AMBA AHB DS60001517A-page 38  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 8.4 8.4.1 Arm9EJ-S Processor Arm9EJ-S Operating States The Arm9EJ-S processor can operate in three different states, each with a specific instruction set: • Arm state: 32-bit, word-aligned Arm instructions. • Thumb state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 8.4.2 Switching State The operating state of the Arm9EJ-S core can be switched between: • Arm state and Thumb state using the BX and BLX instructions, and loads to the PC • Arm state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in Arm state. If an exception occurs in Thumb or Jazelle states, the processor reverts to Arm state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 8.4.3 Instruction Pipelines The Arm9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for Arm and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 8.4.4 Memory Access The Arm9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, halfwords must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The Arm9EJ-S control logic automatically detects these cases and stalls the core or forward data. 8.4.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on Arm processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of Arm9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing Arm or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in Arm9EJ-S decodes 95% of executed byte codes and turns them into Arm instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of Arm instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing Arm registers are re-used in Jazelle state and all registers then have particular functions in this mode. Minimum interrupt latency is maintained across both Arm state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to Arm state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 8.4.6 Arm9EJ-S Operating Modes In all states, there are seven operation modes: • • • • • • • User mode is the usual Arm program execution state. It is used for executing most application programs Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process Interrupt (IRQ) mode is used for general-purpose interrupt handling Supervisor mode is a protected mode for the operating system Abort mode is entered after a data or instruction prefetch abort System mode is a privileged user mode for the operating system Undefined mode is entered when an undefined instruction exception occurs  2017 Microchip Technology Inc. DS60001517A-page 39 SAM9N12/SAM9CN11/SAM9CN12 Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 8.4.7 Arm9EJ-S Registers The Arm9EJ-S core has a total of 37 registers. • 31 general-purpose 32-bit registers • Six 32-bit status registers Table 8-1 shows all the registers in all modes. Table 8-1: Arm9TDMI Modes and Registers Layout User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ Mode-specific banked registers The Arm state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. DS60001517A-page 40  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 The use and the function of all the registers described above should obey Arm Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return For more details, refer to Arm Software Development Kit. The Thumb state register set is a subset of the Arm state set. The programmer has direct access to: • • • • • Eight general-purpose registers r0-r7 Stack pointer, SP Link register, LR (Arm r14) PC CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the Arm9EJ-S Technical Reference Manual, revision r1p2 page 2-12). 8.4.7.1 Status Registers The Arm9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode Figure 8-2: Status Register Format 31 30 29 28 27 24 N Z C V Q J 7 6 5 Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than I F T 0 Mode Mode bits Thumb state bit FIQ disable IRQ disable Figure 8-2 shows the status register format, where: • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. • The J bit in the CPSR indicates when the Arm9EJ-S core is in Jazelle state, where: - J = 0: The processor is in Arm or Thumb state, depending on the T bit - J = 1: The processor is in Jazelle state. • Mode: five bits to encode the current processor mode 8.4.8 8.4.8.1 Exceptions Exception Types and Priorities The Arm9EJ-S supports five types of exceptions. Each type drives the Arm9EJ-S in a privileged mode. The types of exceptions are: • • • • • Fast interrupt (FIQ) Normal interrupt (IRQ) Data and Prefetched aborts (Abort) Undefined instruction (Undefined) Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state.  2017 Microchip Technology Inc. DS60001517A-page 41 SAM9N12/SAM9CN11/SAM9CN12 More than one exception can happen at a time, therefore the Arm9EJ-S takes the arisen exceptions according to the following priority order: • • • • • • Reset (highest priority) Data Abort FIQ IRQ Prefetch Abort BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the Arm9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. 8.4.8.2 Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an Arm exception, the Arm9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: - Arm and Jazelle states, the Arm9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). - THUMB state, the Arm9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The Arm9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the Arm9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of Arm9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the Arm9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 8.4.9 Arm Instruction Set Overview The Arm instruction set is divided into: • • • • • • Branch instructions Data processing instructions Status register transfer instructions Load and Store instructions Coprocessor instructions Exception-generating instructions Arm instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). DS60001517A-page 42  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 8-2 gives the Arm instruction mnemonic list. Table 8-2: Mnemonic Arm Instruction Mnemonic List Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry RSB Reverse Subtract RSC Reverse Subtract with Carry CMP Compare CMN Compare Negated TST Test TEQ Test Equivalence AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR MUL Multiply MLA Multiply Accumulate SMULL Sign Long Multiply UMULL Unsigned Long Multiply SMLAL Signed Long Multiply Accumulate UMLAL Unsigned Long Multiply Accumulate MSR B BX LDR Move to Status Register Branch MRS BL Move From Status Register Branch and Link Branch and Exchange SWI Software Interrupt Load Word STR Store Word LDRSH Load Signed Halfword LDRSB Load Signed Byte LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRBT Load Register Byte with Translation STRBT Store Register Byte with Translation LDRT Load Register with Translation STRT Store Register with Translation LDM Load Multiple STM Store Multiple SWP Swap Word MCR Move To Coprocessor MRC Move From Coprocessor LDC Load To Coprocessor STC Store From Coprocessor CDP Coprocessor Data Processing  2017 Microchip Technology Inc. SWPB Swap Byte DS60001517A-page 43 SAM9N12/SAM9CN11/SAM9CN12 8.4.10 New Arm Instruction Set Table 8-3: Mnemonic BXJ New Arm Instruction Mnemonic List Operation Mnemonic Operation Branch and exchange to Java MRRC Move double from coprocessor BLX (1) Branch, Link and exchange MCR2 Alternative move of Arm reg to coprocessor SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint SMULxy Signed Multiply 16 * 16 bit PLD SMULWy Signed Multiply 32 * 16 bit STRD Store Double Saturated Add STC2 Alternative Store from Coprocessor Saturated Add with Double LDRD Load Double Saturated subtract LDC2 Alternative Load to Coprocessor QADD QDADD QSUB QDSUB Saturated Subtract with double CLZ Soft Preload, Memory prepare to load from address Count Leading Zeroes Note 1: A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. DS60001517A-page 44  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 8.4.11 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the Arm instruction set. The Thumb instruction set is divided into: • • • • • Branch instructions Data processing instructions Load and Store instructions Load and Store multiple instructions Exception-generating instruction Table 8-4 gives the Thumb instruction mnemonic list. Table 8-4: Thumb Instruction Mnemonic List Mnemonic Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry CMP Compare CMN Compare Negated TST Test NEG Negate AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR LSL Logical Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right MUL Multiply BLX Branch, Link, and Exchange B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH Push Register to stack POP Pop Register from stack BCC Conditional Branch BKPT Breakpoint  2017 Microchip Technology Inc. DS60001517A-page 45 SAM9N12/SAM9CN11/SAM9CN12 8.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • • • • • Arm9EJ-S Caches (ICache, DCache and write buffer) TCM MMU Other system options To control these features, CP15 provides 16 additional registers. See Table 8-5. Table 8-5: CP15 Registers Register 0 Name Read/Write (1) Read/Unpredictable ID Code 0 Cache type(1) Read/Unpredictable 0 TCM status(1) Read/Unpredictable 1 Control Read/write 2 Translation Table Base Read/write 3 Domain Access Control Read/write 4 Reserved None 5 Data fault Status(1) Read/write (1) Read/write 5 Instruction fault status 6 Fault Address Read/write 7 Cache Operations Read/Write 8 TLB operations Unpredictable/Write (2) 9 cache lockdown Read/write 9 TCM region Read/write 10 TLB lockdown Read/write 11 Reserved None 12 Reserved None 13 (1) FCSE PID Read/write 13 Context ID(1) Read/Write 14 Reserved None 15 Test configuration Read/Write Note 1: Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2: Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. DS60001517A-page 46  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 8.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from Arm Register) instruction is used to write an Arm register to CP15. • MRC (Move to Arm Register from Coprocessor) instruction is used to read the value of CP15 to an Arm register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 cond 23 22 21 opcode_1 15 20 26 25 24 1 1 1 0 19 18 17 16 L 14 13 12 Rd 7 27 6 5 opcode_2 4 1 CRn 11 10 9 8 1 1 1 1 3 2 1 0 CRm CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. Rd[15:12]: Arm Register Defines the Arm register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. L: Instruction Bit 0: MCR instruction 1: MRC instruction opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. cond [31:28]: Condition For more details, see Chapter 2 in Arm926EJ-S TRM.  2017 Microchip Technology Inc. DS60001517A-page 47 SAM9N12/SAM9CN11/SAM9CN12 8.6 Memory Management Unit (MMU) The Arm926EJ-S processor implements an enhanced Arm architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, twolevel page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 7 shows the different attributes of each page in the physical memory. Table 8-6: Mapping Details Mapping Name Mapping Size Access Permission By Subpage Size Section 1M byte Section - Large Page 64K bytes 4 separated subpages 16K bytes Small Page 4K bytes 4 separated subpages 1K byte Tiny Page 1K byte Tiny Page - The MMU consists of: • Access control logic • Translation Look-aside Buffer (TLB) • Translation table walk hardware 8.6.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). DS60001517A-page 48  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 8.6.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 8.6.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, refer to chapter 3 in Arm926EJ-S Technical Reference Manual. 8.6.4 MMU Faults The MMU generates an abort on the following types of faults: • • • • Alignment faults (for data accesses only) Translation faults Domain faults Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, refer to chapter 3 in Arm926EJ-S Technical Reference Manual. 8.7 Caches and Write Buffer The Arm926EJ-S contains a 16KB Instruction Cache (ICache), a 16KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by Arm926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 8.7.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in Arm926EJS TRM).  2017 Microchip Technology Inc. DS60001517A-page 49 SAM9N12/SAM9CN11/SAM9CN12 On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 8.7.2 Data Cache (DCache) and Write Buffer Arm926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. 8.7.2.1 DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in Arm926EJS TRM). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 8.7.2.2 Write Buffer The Arm926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the Arm9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. 8.7.2.3 Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 8.7.2.4 Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 8.8 Bus Interface Unit The Arm926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. DS60001517A-page 50  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 The multi-master bus architecture has a number of benefits: • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. • Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 8.8.1 Supported Transfers The Arm926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any Arm9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Microchip bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 8-7 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 8-7: Supported Transfers HBurst[2:0] Description Single transfer of word, half word, or byte: SINGLE Single transfer  data write (NCNB, NCB, WT, or WB that has missed in DCache)  data read (NCNB or NCB)  NC instruction fetch (prefetched and non-prefetched)  page table walk read INCR4 Four-word incrementing burst Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. INCR8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. WRAP8 Eight-word wrapping burst Cache linefill 8.8.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of Arm9EJ-S core, are made as 32-bit accesses on the AHB. If the Arm9EJ-S is in Thumb state, then two instructions can be fetched at a time. 8.8.3 Address Alignment The Arm926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries.  2017 Microchip Technology Inc. DS60001517A-page 51 SAM9N12/SAM9CN11/SAM9CN12 9. Debug and Test 9.1 Description The SAM9CN12 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 9.2 Embedded Characteristics • Debug capabilities can be forbidden with a fuse bit. • Arm926 Real-time In-circuit Emulator - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel • Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins DS60001517A-page 52  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 9.3 Block Diagram Figure 9-1: Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset Arm9EJ-S ICE-RT DMA DBGU PIO Arm926EJ-S DTXD DRXD TAP: Test Access Port  2017 Microchip Technology Inc. DS60001517A-page 53 SAM9N12/SAM9CN11/SAM9CN12 9.4 9.4.1 Application Examples Debug Environment Figure 9-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 9-2: Application Debug and Trace Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector SAM9 RS232 Connector Terminal SAM9-based Application Board DS60001517A-page 54  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 9.4.2 Test Environment Figure 9-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 9-3: Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n SAM9 Chip 2 Chip 1 SAM9-based Application Board In Test 9.5 Debug and Test Pin Description Table 9-1: Debug and Test Pin List Pin Name Function Type Active Level Input/Output Low Low Reset/Test NRST Microcontroller Reset ICE and JTAG NTRST Test Reset Signal Input TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select RTCK Returned Test Clock JTAGSEL JTAG Selection Output Input Output Input Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output  2017 Microchip Technology Inc. DS60001517A-page 55 SAM9N12/SAM9CN11/SAM9CN12 9.6 9.6.1 Functional Description EmbeddedICE The Arm9EJ-S EmbeddedICE-RT is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an Arm9EJ-S core embedded within the Arm926EJ-S. The internal state of the Arm926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the Arm9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the Arm9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the Arm document: Arm9EJ-S Technical Reference Manual (DDI 0222A). 9.6.2 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in Arm cores and used to reset the debug logic. On Microchip Arm926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on Arm926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an Arm9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 9.6.3 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. For further details on the Debug Unit, see Section 23. “Debug Unit (DBGU)”. 9.6.4 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the Arm processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. DS60001517A-page 56  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 9.6.5 JTAG ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 MANUFACTURER IDENTITY 3 2 1 0 1 VERSION[31:28]: Product Version Number Set to 0x0. PART NUMBER[27:12]: Product Part Number Product part Number is 0x05B3 MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B3_003F.  2017 Microchip Technology Inc. DS60001517A-page 57 SAM9N12/SAM9CN11/SAM9CN12 10. Advanced Interrupt Controller (AIC) 10.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to 32 interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an Arm processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product’s pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or high-level or low-level sensitive. The Fast Forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. 10.2 Embedded Characteristics • Controls the Interrupt Lines (nIRQ and nFIQ) of an Arm Processor • 32 Individually Maskable and Vectored Interrupt Sources - Source 0 is Reserved for the Fast Interrupt Input (FIQ) - Source 1 is Reserved for System Peripherals - Source 2 to Source 31 Control up to 30 Embedded Peripheral Interrupts or External Interrupts - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources • 8-level Priority Controller - Drives the Normal Interrupt of the Processor - Handles Priority of the Interrupt Sources 1 to 31 - Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt • Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per Interrupt Source - Interrupt Vector Register Reads the Corresponding Current Interrupt Vector • Protect Mode - Easy Debugging by Preventing Automatic Operations when Protect Models Are Enabled • Fast Forcing - Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the Processor • General Interrupt Mask - Provides Processor Synchronization on Events Without Triggering an Interrupt • Register Write Protection DS60001517A-page 58  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.3 Block Diagram Figure 10-1: Block Diagram FIQ AIC Arm Processor IRQ0-IRQn Up to Thirty-two Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 10.4 Application Block Diagram Figure 10-2: Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 10.5 AIC Detailed Block Diagram Figure 10-3: AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller Fast Interrupt Controller External Source Input Stage Arm Processor nFIQ nIRQ IRQ0-IRQn Embedded Peripherals Interrupt Priority Controller Fast Forcing PIOIRQ Internal Source Input Stage Processor Clock Power Management Controller User Interface Wake Up APB  2017 Microchip Technology Inc. DS60001517A-page 59 SAM9N12/SAM9CN11/SAM9CN12 10.6 I/O Line Description Table 10-1: I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0–IRQn Interrupt 0–Interrupt n Input 10.7 Product Dependencies 10.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. Table 10-2: I/O Lines Instance Signal I/O Line Peripheral AIC FIQ PC31 A AIC IRQ PB18 A 10.7.2 Power Management The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the Arm processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event. 10.7.3 Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. DS60001517A-page 60  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.8 10.8.1 10.8.1.1 Functional Description Interrupt Source Control Interrupt Source Mode The AIC independently programs each interrupt source. The SRCTYPE field of the corresponding Source Mode Register (AIC_SMR) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes. 10.8.1.2 Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the Interrupt Mask Register (AIC_IMR). A disabled interrupt does not affect servicing of other interrupts. 10.8.1.3 Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the Interrupt Set Command Register (AIC_ISCR) and the Interrupt Clear Command Register (AIC_ICCR). Clearing or setting interrupt sources programmed in level-sensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization” circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation (see Section 10.8.3.1 “Priority Controller”). The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, see “Fast Forcing” ). The automatic clear of the interrupt source 0 is performed when the FIQ Vector Register (AIC_FVR) is read. 10.8.1.4 Interrupt Status For each interrupt, the AIC operation originates in the Interrupt Pending Register (AIC_IPR ) and its mask in the AIC_IMR. The AIC_IPR enables the actual activity of the sources, whether masked or not. The Interrupt Status Register (AIC_ISR) reads the number of the current interrupt (see “Priority Controller” ) and the Core Interrupt Status Register (AIC_CISR) gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. Figure 10-4: Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Edge Fast Interrupt Controller or Priority Controller AIC_IECR Detector Set Clear AIC_ISCR FF AIC_ICCR AIC_IDCR  2017 Microchip Technology Inc. DS60001517A-page 61 SAM9N12/SAM9CN11/SAM9CN12 Figure 10-5: External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg. Edge Detector Set FF Clear AIC_IDCR AIC_ISCR AIC_ICCR 10.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • • • • The time the software masks the interrupts. Occurrence, either at the processor level or at the AIC level. The execution time of the instruction in progress when the interrupt occurs. The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. Figure 10-6: External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles DS60001517A-page 62  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 10-7: External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles Figure 10-8: Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active Figure 10-9: Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 10.8.3 10.8.3.1 Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR. Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR, the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the Interrupt Vector Register (AIC_IVR) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt.  2017 Microchip Technology Inc. DS60001517A-page 63 SAM9N12/SAM9CN11/SAM9CN12 If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the AIC the end of the current service by writing the End of Interrupt Command Register (AIC_EOICR). The write of AIC_EOICR is the exit point of the interrupt handling. 10.8.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 10.8.3.3 Interrupt Vectoring The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFFF100 and thus accessible from the Arm interrupt vector at address 0x00000018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 10.8.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the Arm processor, and especially the processor interrupt modes and the associated status bits. It is assumed that: • The Advanced Interrupt Controller has been programmed, Source Vector registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. • The instruction at the Arm interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the Arm core adjusts R14_irq, decrementing it by four. 2. The Arm core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: - Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. - De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. - Automatically clears the interrupt, if it has been programmed to be edge-triggered. DS60001517A-page 64  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 - Pushes the current level and the current interrupt number on to the stack. - Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. Note: 7. If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. The AIC_EOICR must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. 8. Note: 10.8.4 10.8.4.1 The “I” bit in SPSR is significant. If it is set, it indicates that the Arm core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if Fast Forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 10.8.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR and AIC_IDCR respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR indicates whether the fast interrupt is enabled or disabled. 10.8.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR. This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFFF104 and thus accessible from the Arm fast interrupt vector at address 0x0000001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 10.8.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the Arm processor, and especially the processor interrupt modes and associated status bits. It is assumed that: • The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. • The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: • LDR PC, [PC, # -&F20] • The user does not need nested fast interrupts.  2017 Microchip Technology Inc. DS60001517A-page 65 SAM9N12/SAM9CN11/SAM9CN12 When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is: 1. 2. 3. 4. 5. 6. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the Arm core adjusts R14_fiq, decrementing it by four. The Arm core enters FIQ mode. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The “F” bit in SPSR is significant. If it is set, it indicates that the Arm core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the Arm vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. 10.8.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the AIC_IPR. The AIC_FVR reads the contents of AIC_SVR0, whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the Fast Forcing feature is used and the interrupt source should be cleared by writing to the AIC_ICCR. All enabled and pending interrupt sources that have the Fast Forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the AIC_ICCR. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the Fast Forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. DS60001517A-page 66  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 10-10: Fast Forcing Source 0 _ FIQ AIC_IPR Input Stage AIC_IMR Automatic Clear nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n AIC_IPR Input Stage Priority Manager Automatic Clear AIC_IMR nIRQ Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. 10.8.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the Arm processor’s ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the AIC_IVR. This has undesirable consequences: • If an enabled interrupt with a higher priority than the current one is pending, it is stacked. • If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing a one to the PROT bit in the Debug Control Register (AIC_DCR) enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the AIC_ISR, is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. 2. 3. 4. 5. Calculates active interrupt (higher than current or spurious). Determines and returns the vector of the active interrupt. Memorizes the interrupt. Pushes the current priority level onto the internal stack. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 10.8.6 Spurious Interrupt The AIC features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: • An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. • An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time (as in the case for the Watchdog). • An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source.  2017 Microchip Technology Inc. DS60001517A-page 67 SAM9N12/SAM9CN11/SAM9CN12 The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in the Spurious Vector Register (AIC_SPU). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 10.8.7 General Interrupt Mask The AIC features a General Interrupt Mask bit (GMSK in AIC_DCR) to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if GMSK is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution. 10.8.8 Register Write Protection To prevent any single software error from corrupting AIC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the AIC Write Protection Mode Register (AIC_WPMR). If a write access to a write-protected register is detected, the WPVS bit in the AIC Write Protection Status Register (AIC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the AIC_WPSR. The following registers can be write-protected: • • • • AIC Source Mode Register AIC Source Vector Register AIC Spurious Interrupt Vector Register AIC Debug Control Register DS60001517A-page 68  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9 Advanced Interrupt Controller (AIC) User Interface The AIC is mapped at the address 0xFFFFF000. It has a total 4 Kbyte addressing space. This permits the vectoring feature, as the PCrelative load/store instructions of the Arm processor support only a ± 4 Kbyte offset. Table 10-3: Register Mapping Offset Register Name Access Reset 0x00 0x04 Source Mode Register 0 AIC_SMR0 Read/Write 0x0 Source Mode Register 1 AIC_SMR1 Read/Write 0x0 ... ... ... ... ... 0x7C Source Mode Register 31 AIC_SMR31 Read/Write 0x0 0x80 Source Vector Register 0 AIC_SVR0 Read/Write 0x0 0x84 Source Vector Register 1 AIC_SVR1 Read/Write 0x0 ... ... ... ... ... 0xFC Source Vector Register 31 AIC_SVR31 Read/Write 0x0 0x100 Interrupt Vector Register AIC_IVR Read-only 0x0 0x104 FIQ Vector Register AIC_FVR Read-only 0x0 0x108 Interrupt Status Register AIC_ISR Read-only 0x0 AIC_IPR Read-only 0x0(1) (2) 0x10C Interrupt Pending Register 0x110 Interrupt Mask Register(2) AIC_IMR Read-only 0x0 0x114 Core Interrupt Status Register AIC_CISR Read-only 0x0 0x118–0x11C Reserved 0x120 Interrupt Enable Command Register – – – (2) AIC_IECR Write-only – (2) AIC_IDCR Write-only – AIC_ICCR Write-only – AIC_ISCR Write-only – AIC_EOICR Write-only – 0x124 Interrupt Disable Command Register 0x128 Interrupt Clear Command Register(2) (2) 0x12C Interrupt Set Command Register 0x130 End of Interrupt Command Register 0x134 Spurious Interrupt Vector Register AIC_SPU Read/Write 0x0 0x138 Debug Control Register AIC_DCR Read/Write 0x0 0x13C Reserved 0x140 Fast Forcing Enable Register – – – (2) AIC_FFER Write-only – (2) AIC_FFDR Write-only – AIC_FFSR Read-only 0x0 – – – 0x144 Fast Forcing Disable Register 0x148 Fast Forcing Status Register(2) 0x14C–0x1E0 Reserved 0x1E4 Write Protection Mode Register AIC_WPMR Read/Write 0x0 0x1E8 Write Protection Status Register AIC_WPSR Read-only 0x0 0x1EC–0x1FC Reserved – – – Note 1: The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2: PID2...PID31 bit fields refer to the identifiers as defined in Section 7.2 “Peripheral Identifiers”.  2017 Microchip Technology Inc. DS60001517A-page 69 SAM9N12/SAM9CN11/SAM9CN12 10.9.1 AIC Source Mode Register Name:AIC_SMR0..AIC_SMR31 Address:0xFFFFF000 AccessRead/Write Reset:0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 4 3 2 1 0 – – – 5 SRCTYPE PRIOR This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register. PRIOR: Priority Level The priority level is programmable from 0 (lowest priority) to 7 (highest priority). The priority level is not used for the FIQ in AIC_SMR0. SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. Value Name 0x0 INT_LEVEL_SENSITIVE 0x1 INT_EDGE_TRIGGERED 0x2 EXT_HIGH_LEVEL 0x3 EXT_POSITIVE_EDGE DS60001517A-page 70 Description High level Sensitive for internal source Low level Sensitive for external source Positive edge triggered for internal source Negative edge triggered for external source High level Sensitive for internal source High level Sensitive for external source Positive edge triggered for internal source Positive edge triggered for external source  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.2 AIC Source Vector Register Name:AIC_SVR0..AIC_SVR31 Address:0xFFFFF080 Access:Read/Write Reset:0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register. VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.  2017 Microchip Technology Inc. DS60001517A-page 71 SAM9N12/SAM9CN11/SAM9CN12 10.9.3 AIC Interrupt Vector Register Name: AIC_IVR Address:0xFFFFF100 Access:Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. DS60001517A-page 72  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.4 AIC FIQ Vector Register Name: AIC_FVR Address:0xFFFFF104 Access:Read-only Reset:0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU.  2017 Microchip Technology Inc. DS60001517A-page 73 SAM9N12/SAM9CN11/SAM9CN12 10.9.5 AIC Interrupt Status Register Name: AIC_ISR Address:0xFFFFF108 Access:Read-only Reset:0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 4 3 2 1 0 7 6 5 – – – IRQID IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. DS60001517A-page 74  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.6 AIC Interrupt Pending Register Name: AIC_IPR Address:0xFFFFF10C Access:Read-only Reset: 0x0 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ: Interrupt Pending 0: Corresponding interrupt is not pending. 1: Corresponding interrupt is pending. SYS: Interrupt Pending 0: Corresponding interrupt is not pending. 1: Corresponding interrupt is pending. PID2–PID31: Interrupt Pending 0: Corresponding interrupt is not pending. 1: Corresponding interrupt is pending.  2017 Microchip Technology Inc. DS60001517A-page 75 SAM9N12/SAM9CN11/SAM9CN12 10.9.7 AIC Interrupt Mask Register Name:AIC_IMR Address:0xFFFFF110 Access:Read-only Reset:0x0 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ: Interrupt Mask 0: Corresponding interrupt is disabled. 1: Corresponding interrupt is enabled. SYS: Interrupt Mask 0: Corresponding interrupt is disabled. 1: Corresponding interrupt is enabled. PID2–PID31: Interrupt Mask 0: Corresponding interrupt is disabled. 1: Corresponding interrupt is enabled. DS60001517A-page 76  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.8 AIC Core Interrupt Status Register Name: AIC_CISR Address:0xFFFFF114 Access:Read-only Reset:0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ NFIQ: NFIQ Status 0: nFIQ line is deactivated. 1: nFIQ line is active. NIRQ: NIRQ Status 0: nIRQ line is deactivated. 1: nIRQ line is active.  2017 Microchip Technology Inc. DS60001517A-page 77 SAM9N12/SAM9CN11/SAM9CN12 10.9.9 AIC Interrupt Enable Command Register Name: AIC_IECR Address:0xFFFFF120 Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ: Interrupt Enable 0: No effect. 1: Enables corresponding interrupt. SYS: Interrupt Enable 0: No effect. 1: Enables corresponding interrupt. PID2–PID31: Interrupt Enable 0: No effect. 1: Enables corresponding interrupt. DS60001517A-page 78  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.10 AIC Interrupt Disable Command Register Name: AIC_IDCR Address:0xFFFFF124 Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ: Interrupt Disable 0: No effect. 1: Disables corresponding interrupt. SYS: Interrupt Disable 0: No effect. 1: Disables corresponding interrupt. PID2–PID31: Interrupt Disable 0: No effect. 1: Disables corresponding interrupt.  2017 Microchip Technology Inc. DS60001517A-page 79 SAM9N12/SAM9CN11/SAM9CN12 10.9.11 AIC Interrupt Clear Command Register Name:AIC_ICCR Address:0xFFFFF128 Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ: Interrupt Clear 0: No effect. 1: Clears corresponding interrupt. SYS: Interrupt Clear 0: No effect. 1: Clears corresponding interrupt. PID2–PID31: Interrupt Clear 0: No effect. 1: Clears corresponding interrupt. DS60001517A-page 80  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.12 AIC Interrupt Set Command Register Name: AIC_ISCR Address:0xFFFFF12C Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ: Interrupt Set 0: No effect. 1: Sets corresponding interrupt. SYS: Interrupt Set 0: No effect. 1: Sets corresponding interrupt. PID2–PID31: Interrupt Set 0: No effect. 1: Sets corresponding interrupt.  2017 Microchip Technology Inc. DS60001517A-page 81 SAM9N12/SAM9CN11/SAM9CN12 10.9.13 AIC End of Interrupt Command Register Name:AIC_EOICR Address:0xFFFFF130 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – ENDIT ENDIT: Interrupt Processing Complete Command The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. DS60001517A-page 82  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.14 AIC Spurious Interrupt Vector Register Name:AIC_SPU Address:0xFFFFF134 Access:Read/Write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register. SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.  2017 Microchip Technology Inc. DS60001517A-page 83 SAM9N12/SAM9CN11/SAM9CN12 10.9.15 AIC Debug Control Register Name:AIC_DCR Address:0xFFFFF138 Access:Read/Write Reset:0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT This register can only be written if the WPEN bit is cleared in the AIC Write Protection Mode Register. PROT: Protection Mode 0: The Protection Mode is disabled. 1: The Protection Mode is enabled. GMSK: General Interrupt Mask 0: The nIRQ and nFIQ lines are normally controlled by the AIC. 1: The nIRQ and nFIQ lines are tied to their inactive state. DS60001517A-page 84  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.16 AIC Fast Forcing Enable Register Name:AIC_FFER Address:0xFFFFF140 Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – SYS: Fast Forcing Enable 0: No effect. 1: Enables the Fast Forcing feature on the corresponding interrupt. PID2–PID31: Fast Forcing Enable 0: No effect. 1: Enables the Fast Forcing feature on the corresponding interrupt.  2017 Microchip Technology Inc. DS60001517A-page 85 SAM9N12/SAM9CN11/SAM9CN12 10.9.17 AIC Fast Forcing Disable Register Name:AIC_FFDR Address:0xFFFFF144 Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – SYS: Fast Forcing Disable 0: No effect. 1: Disables the Fast Forcing feature on the corresponding interrupt. PID2–PID31: Fast Forcing Disable 0: No effect. 1: Disables the Fast Forcing feature on the corresponding interrupt. DS60001517A-page 86  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.18 AIC Fast Forcing Status Register Name:AIC_FFSR Address:0xFFFFF148 Access:Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – SYS: Fast Forcing Status 0: The Fast Forcing feature is disabled on the corresponding interrupt. 1: The Fast Forcing feature is enabled on the corresponding interrupt. PID2–PID31: Fast Forcing Status 0: The Fast Forcing feature is disabled on the corresponding interrupt. 1: The Fast Forcing feature is enabled on the corresponding interrupt.  2017 Microchip Technology Inc. DS60001517A-page 87 SAM9N12/SAM9CN11/SAM9CN12 10.9.19 AIC Write Protection Mode Register Name:AIC_WPMR Address:0xFFFFF1E4 Access:Read/Write Reset:See Table 10-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN WPEN: Write Protection Enable 0: Disables write protection if WPKEY corresponds to 0x414943 (“AIC” in ASCII). 1: Enables write protection if WPKEY corresponds to 0x414943 (“AIC” in ASCII). See Section 10.8.8 “Register Write Protection” for list of write-protected registers. WPKEY: Write Protection Key Value Name 0x414943 PASSWD DS60001517A-page 88 Description Writing any other value in this field aborts the write operation of bit WPEN. Always reads as 0.  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 10.9.20 AIC Write Protection Status Register Name:AIC_WPSR Address:0xFFFFF1E8 Access:Read-only Reset:See Table 10-3 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the AIC_WPSR. 1: A write protection violation has occurred since the last read of the AIC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.  2017 Microchip Technology Inc. DS60001517A-page 89 SAM9N12/SAM9CN11/SAM9CN12 11. Boot Strategies 11.1 SAM9CN12 Only The SAM9CN12 embeds a Secure Boot allowing firmware stored in external Non-Volatile Memory to be protected. The content of the external NVM is encrypted and signed based using a 256-bit AES algorithm. Prior to booting from the externally stored firmware, the secure boot will authenticate the firmware, decrypt it and store it in on-chip memory. Access to the on-chip memory is prevented and the maximum size of the firmware should not exceed 24 Kbytes. The programming of the external memory can only be done by the SAM9CN12 using a unique key stored in the on-chip OTP memory. Herewith the software is uniquely linked to each SAM9CN12 device. A direct copy of the NVM memory will not run on another SAM9CN12 device, improving the firmware protection even further. For software development the user should use the SAM9CN11 without secure boot and full access to on-chip memory for debug. Once the firmware development has been completed, the SAM9CN11 should be replaced by the SAM9CN12 and programmed via USB with the secure SAM Boot Assistant (SAM-BA®). Refer to the application note “Understanding and Using SAM9CN12 Secure Bootloader”, literature No. 11196, for more details (NDA required). 11.2 SAM9CN11 and SAM9N12 Only The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. The sampling of the BMS pin is done at reset. If BMS is detected at 0, the controller boots on the memory connected to Chip Select 0 of the External Bus Interface. In this boot mode, the chip starts with its default parameters (all registers in their reset state), including as follows: • the main clock is the on-chip 12 MHz RC oscillator • the Static Memory Controller is configured with its default parameters The user software in the external memory performs a complete configuration: • • • • • Enable the 32768 Hz oscillator if best accuracy is needed Program the PMC (main oscillator enable or bypass mode) Program and start the PLL Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock Switch the system clock to the new value If BMS is detected at 1, the boot memory is the embedded ROM and the Boot Program described below is executed (Section 11.2.1 “ROM Code”). 11.2.1 ROM Code The ROM Code is a boot program contained in the embedded ROM. It is also called “First level bootloader”. The ROM Code performs several steps: • basic chip initialization: XTAL or external clock frequency detection • attempt to retrieve a valid code from external non-volatile memories (NVM) • execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM DS60001517A-page 90  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 11.2.2 Flow Diagram The ROM Code implements the algorithm shown below in Figure 11-1. Figure 11-1: ROM Code Algorithm Flow Diagram Chip Setup Valid boot code found in one NVM Yes Copy and run it in internal SRAM No SAM-BA Monitor 11.2.3 Chip Setup At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz Fast RC Oscillator. Initialization follows the steps described below: 1. 2. 3. 4. 5. Stack setup for Arm supervisor mode. Main Oscillator Detection: The Main Clock is switched to the 32 kHz RC oscillator to allow external clock frequency to be measured. Then the Main Oscillator is enabled and set in bypass mode. If the MOSCSELS bit rises, an external clock is connected, and the next step is Main Clock Selection (3). If not, the Bypass mode is cleared to attempt external quartz detection. This detection is successful when the MOSCXTS and MOSCSELS bits rise, else the 12 MHz Fast RC internal oscillator is used as the Main Clock. Main Clock Selection: The Master Clock source is switched from the Slow Clock to the Main Oscillator without prescaler. The PMC Status Register is polled to wait for MCK Ready. PCK and MCK are now the Main Clock. C variable initialization: Non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-initialized data is set to 0 in the RAM. PLLA initialization: PLLA is configured to get a PCK at 48 MHz and an MCK at 48 MHz. If an external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz Fast RC, but USB will not be activated. Table 11-1: External Clock and Crystal frequencies allowed for Boot Sequence (in MHz) Boot Sequence ≤4 12 ≥ 28 Boot on external memories Yes Yes Yes SAM-BA Monitor through DBGU Yes Yes Yes SAM-BA Monitor through USB No Yes No Providing a clock frequency not at 12 MHz but between 4 and 28 MHz will be considered by the ROM Code as 12 MHz, and PLL settings will be configured accordingly.  2017 Microchip Technology Inc. DS60001517A-page 91 SAM9N12/SAM9CN11/SAM9CN12 11.2.4 NVM Boot 11.2.4.1 NVM Boot Sequence The boot sequence on external memory devices can be controlled using the Boot Sequence Controller Configuration Register (BSC_CR). The three LSBs of the BSC_CR are available to control the sequence. The user can then choose to bypass some steps shown in Figure 11-2 “NVM Bootloader Sequence Diagram” according to the value of the BOOT field in the BSC_CR. Table 11-2: Boot Sequence Controller Configuration Register Values BSC_CR.BOOT Value SPI0 NPCS0 SDCard NAND Flash SPI0 NPCS1 TWI EEPROM SAM-BA Monitor 0 Y Y Y Y Y Y 1 Y – Y Y Y Y 2 Y – – Y Y Y 3 Y – – Y Y Y 4 Y – – – Y Y 5 – – – – – Y 6 – – – – – Y 7 – – – – – Y DS60001517A-page 92  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 11-2: NVM Bootloader Sequence Diagram Device Setup SPI0 CS0 Flash Boot Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from SD Card to SRAM Run SD Card Bootloader Yes Copy from NAND Flash to SRAM Run NAND Flash Bootloader Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from TWI EEPROM to SRAM Run TWI EEPROM Bootloader No SD Card Boot No NAND Flash Boot No SPI0 CS1 Flash Boot No TWI EEPROM Boot No SAM-BA Monitor  2017 Microchip Technology Inc. DS60001517A-page 93 SAM9N12/SAM9CN11/SAM9CN12 11.2.4.2 NVM Bootloader Program Description Figure 11-3: NVM Bootloader Program Diagram Start Initialize NVM Initialization OK ? No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the PC to 0 to jump to the downloaded application End The NVM bootloader program first initializes the PIOs related to the NVM device. Then it configures the right peripheral depending on the NVM and tries to access this memory. If the initialization fails, it restores the reset values for the PIO and the peripheral and then tries the same operations on the next NVM of the sequence. If the initialization is successful, the NVM bootloader program reads the beginning of the NVM and determines if the NVM contains valid code. If the NVM does not contain valid code, the NVM bootloader program restores the reset value for the peripherals and then tries the same operations on the next NVM of the sequence. DS60001517A-page 94  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 If a valid code is found, this code is loaded from NVM into internal SRAM and executed by branching at address 0x0000_0000 after remap. This code may be the application code or a second-level bootloader. Figure 11-4: Remap Action after Download Completion 0x0000_0000 0x0000_0000 REMAP Internal ROM Internal SRAM 0x0010_0000 0x0010_0000 Internal ROM Internal ROM 0x0030_0000 0x0030_0000 Internal SRAM 11.2.4.3 Internal SRAM Valid Code Detection There are two kinds of valid code detection. • Arm Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven Arm exception vectors. Except for the sixth vector, these bytes must implement the Arm instructions for either branch or load PC with PC relative addressing. Figure 11-5: LDR Opcode 31 1 28 27 1 Figure 11-6: 1 0 0 24 23 1 I P U 20 19 1 W 0 16 15 Rn 12 11 Rd 0 Offset B Opcode 31 1 28 27 1 1 0 1 24 23 0 1 0 0 Offset (24 bits) Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: • • • • • Rn = Rd = PC = 0xF I==0 (12-bit immediate value) P==1 (pre-indexed) U offset added (U==1) or subtracted (U==0) W==1  2017 Microchip Technology Inc. DS60001517A-page 95 SAM9N12/SAM9CN11/SAM9CN12 The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with the user’s own vector. This information is described below. Figure 11-7: Structure of the Arm Vector 6 31 0 Size of the code to download in bytes The value has to be smaller than 24 Kbytes. This size is the internal SRAM size minus the stack size used by the ROM Code at the end of the internal SRAM. Example An example of valid vectors follows: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 ’ • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. - Address: Address in hexadecimal. - Output: The byte, halfword or word read in hexadecimal followed by ‘>’ • Send a file (S): Send a file to a specified address. - Address: Address in hexadecimal. - Output: ‘>’  2017 Microchip Technology Inc. DS60001517A-page 103 SAM9N12/SAM9CN11/SAM9CN12 Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address - Address: Address in hexadecimal. - NbOfBytes: Number of bytes in hexadecimal to receive. - Output: ‘>’ • Go (G): Jump to a specified address and execute the code. - Address: Address to jump in hexadecimal. - Output: ‘>’once returned from the program execution. If the executed program does not handle the link register at its entry and does not return, the prompt will not be displayed. • Get Version (V): Return the Boot Program version. - Output: version, date and time of ROM code followed by ‘>’. 11.2.5.2 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115,200 Baud, 8 bits of data, no parity, 1 stop bit. • Supported External Crystal/External Clocks The SAM-BA Monitor supports a frequency of 12 MHz to allow DBGU communication for both external crystal and external clock. • Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory in order to work. The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: • • • • = 01 hex = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) = 1’s complement of the blk#. = 2 bytes CRC16 Figure 11-11 shows a transmission using this protocol. Figure 11-11: Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK DS60001517A-page 104  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 11.2.5.3 USB Device Port • Supported External Crystal / External Clocks The frequencies supported by SAM-BA Monitor to allow USB communication are 4, 8, 12 or 16 MHz crystal or external clock. • USB Class The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, beginning with Windows 98SE. The CDC document, available at www.usb.org, describes how to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Microchip’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. • Enumeration Process The USB protocol is a master/slave protocol. The host starts the enumeration, sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 11-6: Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value. GET_STATUS Returns status for the specified recipient. SET_FEATURE Used to set or enable a specific feature. CLEAR_FEATURE Used to clear or disable a specific feature. The device also handles some class requests defined in the CDC class. Table 11-7: Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DTE device is now present. Unhandled requests are stalled. • Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response.  2017 Microchip Technology Inc. DS60001517A-page 105 SAM9N12/SAM9CN11/SAM9CN12 12. Boot Sequence Controller (BSC) 12.1 Description The System Controller embeds a Boot Sequence Controller (BSC). The boot sequence is programmable through the Boot Sequence Controller Configuration Register (BSC_CR) to save timeout delays on boot. The BSC_CR is powered by VDDBU. Any modification of the register value is stored and applied after the next reset. The register defaults to the factory value in case of battery removal. The BSC_CR is programmable with user programs or SAM-BA and is key-protected. 12.2 Embedded Characteristics • VDDBU powered register 12.3 Product Dependencies • Product-dependent order DS60001517A-page 106  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 12.4 Boot Sequence Controller (BSC) Registers User Interface Table 12-1: Offset 0x0 Register Mapping Register Name Boot Sequence Controller Configuration Register BSC_CR  2017 Microchip Technology Inc. Access Reset Read/Write – DS60001517A-page 107 SAM9N12/SAM9CN11/SAM9CN12 12.4.1 Boot Sequence Controller Configuration Register Name:BSC_CR Address:0xFFFFFE54 Access:Read/Write Factory Value: 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 – 10 – 9 – 8 – 3 2 1 0 WPKEY 23 22 21 20 WPKEY 15 – 14 – 13 – 12 – 7 6 5 4 BOOT BOOT: Boot Media Sequence This value is defined in Section 11. ”Boot Strategies”. It is only written if WPKEY carries the valid value. WPKEY: Write Protection Key (Write-only) Value Name 0x6683 PASSWD DS60001517A-page 108 Description Writing any other value in this field aborts the write operation of the BOOT field. Always reads as 0.  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 13. Reset Controller (RSTC) 13.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 13.2 Embedded Characteristics • Manages All Resets of the System, Including - External Devices Through the NRST Pin - Processor Reset - Peripheral Set Reset - Backed-up Peripheral Reset • Based on 2 Embedded Power-on Reset Cells • Reset Source Status - Status of the Last Reset - Either General Reset, Wake-up Reset, Software Reset, User Reset, Watchdog Reset • External Reset Signal Shaping 13.3 Block Diagram Figure 13-1: Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR Startup Counter Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager periph_nreset exter_nreset backup_neset WDRPROC wd_fault SLCK 13.4 13.4.1 Functional Description Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals.  2017 Microchip Technology Inc. DS60001517A-page 109 SAM9N12/SAM9CN11/SAM9CN12 • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in Section 47.4.4, Crystal Oscillator Characteristics. The Reset Controller Mode Register (RSTC_MR), used to configure the reset controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 13.4.2 NRST Manager After power-up, NRST is an output during the External Reset Length (ERSTL) time defined in the RSTC. When the ERSTL time has elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal. The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager. Figure 13-2: NRST Manager RSTC_SR URSTS NRSTL user_reset NRST RSTC_MR ERSTL nrst_out 13.4.2.1 External Reset Timer exter_nreset NRST Signal The NRST Manager handles the NRST input line asynchronously. When the line is low, a User Reset is immediately reported to the Reset State Manager. When the NRST goes from low to high, the internal reset is synchronized with the Slow Clock to provide a safe internal de-assertion of reset. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in the Reset Controller Status Register (RSTC_SR). As soon as the pin NRST is asserted, the bit URSTS in the RSTC_SR is set. This bit clears only when RSTC_SR is read. 13.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in the RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the reset controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 13.4.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. DS60001517A-page 110  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 13-3: BMS Sampling SLCK Core Supply POR output BMS Signal XXX H or L BMS sampling delay = 3 cycles proc_nreset 13.4.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the RSTC_SR. The update of the field RSTTYP is performed when the processor reset is released. 13.4.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in the RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises two cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the backup supply POR cell, all resets signals are immediately asserted, even if the main supply POR cell does not report a main supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (main supply POR output). Figure 13-4 shows how the General Reset affects the reset signals.  2017 Microchip Technology Inc. DS60001517A-page 111 SAM9N12/SAM9CN11/SAM9CN12 Figure 13-4: General Reset State SLCK Any Freq. MCK Backup Supply POR output Startup Time Main Supply POR output backup_nreset Processor Startup proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH BMS Sampling = 2 cycles 13.4.4.2 Wake-up Reset The wake-up reset occurs when the main supply is down. When the main supply POR output is active, all the reset signals are asserted except backup_nreset. When the main supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the Arm processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in the RSTC_SR is updated to report a wake-up reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the main supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the main supply POR. DS60001517A-page 112  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 13-5: Wake-up Reset SLCK Any Freq. MCK Main Supply POR output backup_nreset Resynch. 2 cycles Processor Startup proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 13.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin. When a falling edge occurs on NRST (reset activation), internal reset lines are immediately asserted. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the RSTC_SR is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.  2017 Microchip Technology Inc. DS60001517A-page 113 SAM9N12/SAM9CN11/SAM9CN12 Figure 13-6: User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Processor Startup proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 13.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing a 1 to PROCRST resets the processor and the watchdog timer. • PERRST: Writing a 1 to PERRST resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST bot set to 1 simultaneously.) • EXTRST: Writing a 1 to EXTRST asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the reset controller reports the software status in the field RSTTYP of the RSTC_SR. Other software resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the RSTC_SR. It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in the RSTC_CR has no effect. DS60001517A-page 114  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 13-7: Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 to 2 cycles Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL = 2) SRCMP in RSTC_SR 13.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC = 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on how field RSTC_MR.ERSTL is programmed. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN in the WDT_MR is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum. When bit WDT_MR.WDRSTEN is reset, the watchdog fault has no impact on the reset controller.  2017 Microchip Technology Inc. DS60001517A-page 115 SAM9N12/SAM9CN11/SAM9CN12 Figure 13-8: Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL = 2) 13.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • • • • • Backup Reset Wake-up Reset User Reset Watchdog Reset Software Reset Particular cases are listed below: • When in User Reset: - A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. - A software reset is impossible, since the processor reset is being activated. • When in Software Reset: - A watchdog event has priority over the current state. - The NRST has no effect. • When in Watchdog Reset: - The processor reset is active and so a Software Reset cannot be programmed. - A User Reset cannot be entered. DS60001517A-page 116  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 13.5 Reset Controller (RSTC) User Interface Table 13-1: Register Mapping Offset Register Name Access Reset Back-up Reset 0x00 Control Register RSTC_CR Write-only – – 0x04 Status Register RSTC_SR Read-only 0x0000_0100 (1) 0x0000_0000 (2) 0x08 Mode Register RSTC_MR Read/Write – 0x0000_0000 Note 1: Only power supply VDDCORE rising 2: Both power supplies VDDCORE and VDDBU rising  2017 Microchip Technology Inc. DS60001517A-page 117 SAM9N12/SAM9CN11/SAM9CN12 13.5.1 Reset Controller Control Register Name:RSTC_CR Address:0xFFFFFE00 Access Type:Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST PROCRST: Processor Reset 0: No effect 1: If KEY value = 0xA5, resets the processor PERRST: Peripheral Reset 0: No effect 1: If KEY value = 0xA5, resets the peripherals EXTRST: External Reset 0: No effect 1: If KEY value = 0xA5, asserts the NRST pin and resets the processor and the peripherals KEY: Write Access Password Value Name 0xA5 PASSWD DS60001517A-page 118 Description Writing any other value in this field aborts the write operation. Always reads as 0.  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 13.5.2 Reset Controller Status Register Name:RSTC_SR Address:0xFFFFFE04 Access Type:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS URSTS: User Reset Status A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the Master Clock (MCK) rising edge. Reading the RSTC_SR resets the URSTS bit. 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. RSTTYP: Reset Type This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. Value Name Description 0 GENERAL_RST Both VDDCORE and VDDBU rising 1 WKUP_RST VDDCORE rising 2 WDT_RST Watchdog fault occurred 3 SOFT_RST Processor reset required by the software 4 USER_RST NRST pin detected low NRSTL: NRST Pin Level This bit registers the NRST pin level sampled on each Master Clock (MCK) rising edge. SRCMP: Software Reset Command in Progress When set, this bit indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. 0: No software command is being performed by the reset controller. The reset controller is ready for a software command. 1: A software reset command is being performed by the reset controller. The reset controller is busy.  2017 Microchip Technology Inc. DS60001517A-page 119 SAM9N12/SAM9CN11/SAM9CN12 13.5.3 Reset Controller Mode Register Name:RSTC_MR Address:0xFFFFFE08 Access Type:Read/Write 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 – 0 – ERSTL 2 – ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows the assertion duration to be programmed between 60 µs and 2 seconds. KEY: Write Access Password Value Name 0xA5 PASSWD DS60001517A-page 120 Description Writing any other value in this field aborts the write operation. Always reads as 0.  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14. Real-time Clock (RTC) 14.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. 14.2 Embedded Characteristics • • • • Full Asynchronous Design for Ultra Low Power Consumption Gregorian Mode Supported Programmable Periodic Interrupt Safety/security Features: - Valid Time and Date Programmation Check • Register Write Protection 14.3 Block Diagram Figure 14-1: 14.4 14.4.1 Real-time Clock Block Diagram Slow Clock: SLCK 32768 Divider Bus Interface Bus Interface Time Date Entry Control Interrupt Control RTC Interrupt Product Dependencies Power Management The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior. 14.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading each status register of the System Controller peripherals successively.  2017 Microchip Technology Inc. DS60001517A-page 121 SAM9N12/SAM9CN11/SAM9CN12 14.5 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds reported in RTC Time Register (RTC_TIMR) and RTC Calendar Register (RTC_CALR). The valid year range is up to 2099 in Gregorian mode . The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years except 1900). This is correct up to the year 2099. 14.5.1 Reference Clock The reference clock is the Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 14.5.2 Timing The RTC is updated in real time at one-second intervals in Normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 14.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition: • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. • If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC, MIN, HOUR fields. Note: 14.5.4 To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR or RTC_CALALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN, DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREn, DATEEN, MTHEN fields. Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is followed for the alarm. The following checks are performed: 1. 2. 3. 4. 5. 6. 7. 8. Century (check if it is in range 19–20 ) Year (BCD entry check) Date (check range 01–31) Month (check if it is in BCD range 01–12, check validity regarding “date”) Day (check range 1–7) Hour (BCD checks: in 24-hour mode, check range 00–23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01–12) Minute (check BCD and range 00–59) Second (check BCD and range 00–59) DS60001517A-page 122  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Note: 14.5.5 If the 12-hour mode is selected by means of the RTC Mode Register (RTC_MR), a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIMR) to determine the range to be checked. Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register (RTC_CR). Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). The ACKUPD bit is automatically set within a second after setting the UPDTIM and/or UPDCAL bit (meaning one second is the maximum duration of the polling or wait for interrupt period). Once ACKUPD is set, it is mandatory to clear this flag by writing the corresponding bit in the RTC_SCCR, after which the user can write to the Time Register, the Calendar Register, or both. Once the update is finished, the user must clear UPDTIM and/or UPDCAL in the RTC_CR. When entering the programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for lowpower considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these bits again. This is done by waiting for the SEC flag in the RTC_SR before setting UPDTIM/UPDCAL bit. After clearing UPDTIM/UPDCAL, the SEC flag must also be cleared.  2017 Microchip Technology Inc. DS60001517A-page 123 SAM9N12/SAM9CN11/SAM9CN12 Figure 14-2: Update Sequence Begin Prepare Time or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD =1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End DS60001517A-page 124  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14.6 Real-time Clock (RTC) User Interface Table 14-1: Offset Register Mapping Register Name Access Reset 0x00 Control Register RTC_CR Read/Write 0x00000000 0x04 Mode Register RTC_MR Read/Write 0x00000000 0x08 Time Register RTC_TIMR Read/Write 0x00000000 0x0C Calendar Register RTC_CALR Read/Write 0x01210720 0x10 Time Alarm Register RTC_TIMALR Read/Write 0x00000000 0x14 Calendar Alarm Register RTC_CALALR Read/Write 0x01010000 0x18 Status Register RTC_SR Read-only 0x00000000 0x1C Status Clear Command Register RTC_SCCR Write-only – 0x20 Interrupt Enable Register RTC_IER Write-only – 0x24 Interrupt Disable Register RTC_IDR Write-only – 0x28 Interrupt Mask Register RTC_IMR Read-only 0x00000000 0x2C Valid Entry Register RTC_VER Read-only 0x00000000 0x30–0xC8 Reserved – – – 0xCC Reserved – – – 0xD0 Reserved – – – 0xD4–0xF8 Reserved – – – 0xFC Reserved – – – Note: If an offset is not listed in the table it must be considered as reserved.  2017 Microchip Technology Inc. DS60001517A-page 125 SAM9N12/SAM9CN11/SAM9CN12 14.6.1 RTC Control Register Name: RTC_CR Address:0xFFFFFEB0 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). UPDTIM: Update Request Time Register 0: No effect or, if UPDTIM has been previously written to 1, stops the update procedure. 1: Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. UPDCAL: Update Request Calendar Register 0: No effect or, if UPDCAL has been previously written to 1, stops the update procedure. 1: Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR depends on the value of TIMEVSEL. Value Name Description 0 MINUTE Minute change 1 HOUR Hour change 2 MIDNIGHT Every day at midnight 3 NOON Every day at noon CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) DS60001517A-page 126  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14.6.2 RTC Mode Register Name: RTC_MR Address:0xFFFFFEB4 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected.  2017 Microchip Technology Inc. DS60001517A-page 127 SAM9N12/SAM9CN11/SAM9CN12 14.6.3 RTC Time Register Name: RTC_TIMR Address:0xFFFFFEB8 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 4 – 3 SEC SEC: Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. MIN: Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. HOUR: Current Hour The range that can be set is 1–12 (BCD) in 12-hour mode or 0–23 (BCD) in 24-hour mode. AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0: AM. 1: PM. DS60001517A-page 128  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14.6.4 RTC Calendar Register Name: RTC_CALR Address:0xFFFFFEBC Access: Read/Write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 4 – CENT CENT: Current Century Only the BCD value 20 can be configured. The lowest four bits encode the units. The higher bits encode the tens. YEAR: Current Year The range that can be set is 00–99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. MONTH: Current Month The range that can be set is 01–12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. DAY: Current Day in Current Week The range that can be set is 1–7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. DATE: Current Day in Current Month The range that can be set is 01–31 (BCD). The lowest four bits encode the units. The higher bits encode the tens.  2017 Microchip Technology Inc. DS60001517A-page 129 SAM9N12/SAM9CN11/SAM9CN12 14.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address:0xFFFFFEC0 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 4 SECEN 3 SEC This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Note: To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then reenable it after the change has been made. This requires up to three accesses to the RTC_TIMALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields. SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. SECEN: Second Alarm Enable 0: The second-matching alarm is disabled. 1: The second-matching alarm is enabled. MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. MINEN: Minute Alarm Enable 0: The minute-matching alarm is disabled. 1: The minute-matching alarm is enabled. HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. HOUREN: Hour Alarm Enable 0: The hour-matching alarm is disabled. 1: The hour-matching alarm is enabled. DS60001517A-page 130  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address:0xFFFFFEC4 Access: Read/Write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Note: To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then reenable it after the change has been made. This requires up to three accesses to the RTC_CALALR. The first access clears the enable corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields. MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. MTHEN: Month Alarm Enable 0: The month-matching alarm is disabled. 1: The month-matching alarm is enabled. DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. DATEEN: Date Alarm Enable 0: The date-matching alarm is disabled. 1: The date-matching alarm is enabled.  2017 Microchip Technology Inc. DS60001517A-page 131 SAM9N12/SAM9CN11/SAM9CN12 14.6.7 RTC Status Register Name: RTC_SR Address:0xFFFFFEC8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD ACKUPD: Acknowledge for Update Value Name Description 0 FREERUN Time and calendar registers cannot be updated. 1 UPDATE Time and calendar registers can be updated. ALARM: Alarm Flag Value Name Description 0 NO_ALARMEVENT No alarm matching condition occurred. 1 ALARMEVENT An alarm matching condition has occurred. SEC: Second Event Value Name Description 0 NO_SECEVENT No second event has occurred since the last clear. 1 SECEVENT At least one second event has occurred since the last clear. TIMEV: Time Event Value Name Description 0 NO_TIMEVENT No time event has occurred since the last clear. 1 TIMEVENT At least one time event has occurred since the last clear. Note: The time event is selected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: minute change, hour change, noon, midnight (day change). CALEV: Calendar Event Value Name Description 0 NO_CALEVENT No calendar event has occurred since the last clear. 1 CALEVENT At least one calendar event has occurred since the last clear. Note: The calendar event is selected in the CALEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: week change, month change and year change. DS60001517A-page 132  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address:0xFFFFFECC Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). ALRCLR: Alarm Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). SECCLR: Second Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). TIMCLR: Time Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). CALCLR: Calendar Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR).  2017 Microchip Technology Inc. DS60001517A-page 133 SAM9N12/SAM9CN11/SAM9CN12 14.6.9 RTC Interrupt Enable Register Name: RTC_IER Address:0xFFFFFED0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. ALREN: Alarm Interrupt Enable 0: No effect. 1: The alarm interrupt is enabled. SECEN: Second Event Interrupt Enable 0: No effect. 1: The second periodic interrupt is enabled. TIMEN: Time Event Interrupt Enable 0: No effect. 1: The selected time event interrupt is enabled. CALEN: Calendar Event Interrupt Enable 0: No effect. 1: The selected calendar event interrupt is enabled. DS60001517A-page 134  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address:0xFFFFFED4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. ALRDIS: Alarm Interrupt Disable 0: No effect. 1: The alarm interrupt is disabled. SECDIS: Second Event Interrupt Disable 0: No effect. 1: The second periodic interrupt is disabled. TIMDIS: Time Event Interrupt Disable 0: No effect. 1: The selected time event interrupt is disabled. CALDIS: Calendar Event Interrupt Disable 0: No effect. 1: The selected calendar event interrupt is disabled.  2017 Microchip Technology Inc. DS60001517A-page 135 SAM9N12/SAM9CN11/SAM9CN12 14.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address:0xFFFFFED8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled. ALR: Alarm Interrupt Mask 0: The alarm interrupt is disabled. 1: The alarm interrupt is enabled. SEC: Second Event Interrupt Mask 0: The second periodic interrupt is disabled. 1: The second periodic interrupt is enabled. TIM: Time Event Interrupt Mask 0: The selected time event interrupt is disabled. 1: The selected time event interrupt is enabled. CAL: Calendar Event Interrupt Mask 0: The selected calendar event interrupt is disabled. 1: The selected calendar event interrupt is enabled. DS60001517A-page 136  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 14.6.12 RTC Valid Entry Register Name: RTC_VER Address:0xFFFFFEDC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed. NVCAL: Non-valid Calendar 0: No invalid data has been detected in RTC_CALR (Calendar Register). 1: RTC_CALR has contained invalid data since it was last programmed. NVTIMALR: Non-valid Time Alarm 0: No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1: RTC_TIMALR has contained invalid data since it was last programmed. NVCALALR: Non-valid Calendar Alarm 0: No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1: RTC_CALALR has contained invalid data since it was last programmed.  2017 Microchip Technology Inc. DS60001517A-page 137 SAM9N12/SAM9CN11/SAM9CN12 15. Periodic Interval Timer (PIT) 15.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Embedded Characteristics • 20-bit Programmable Counter plus 12-bit Interval Counter • Reset-on-read Feature • Both Counters Work on Master Clock/16 15.3 Block Diagram Figure 15-1: Periodic Interval Timer PIT_MR PIV = PIT_MR PITIEN set 0 PIT_SR PITS pit_irq reset 0 MCK Prescaler 15.4 0 0 1 12-bit Adder 1 read PIT_PIVR 20-bit Counter MCK/16 CPIV PIT_PIVR CPIV PIT_PIIR PICNT PICNT Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS bit is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. DS60001517A-page 138  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN = 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 15-2: Enabling/Disabling PIT with PITEN APB cycle APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN CPIV 0 PICNT 1 PIV - 1 0 PIV 1 0 1 0 PITS (PIT_SR) APB Interface read PIT_PIVR  2017 Microchip Technology Inc. DS60001517A-page 139 SAM9N12/SAM9CN11/SAM9CN12 15.5 Periodic Interval Timer (PIT) User Interface Table 15-1: Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read/Write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000 DS60001517A-page 140  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 15.5.1 Periodic Interval Timer Mode Register Name:PIT_MR Address:0xFFFFFE30 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 PITIEN 24 PITEN 23 – 22 – 21 – 20 – 19 18 17 16 15 14 13 12 11 10 9 8 3 2 1 0 PIV PIV 7 6 5 4 PIV PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). PITEN: Period Interval Timer Enabled 0: The Periodic Interval Timer is disabled when the PIV value is reached. 1: The Periodic Interval Timer is enabled. PITIEN: Periodic Interval Timer Interrupt Enable 0: The bit PITS in PIT_SR has no effect on interrupt. 1: The bit PITS in PIT_SR asserts interrupt.  2017 Microchip Technology Inc. DS60001517A-page 141 SAM9N12/SAM9CN11/SAM9CN12 15.5.2 Periodic Interval Timer Status Register Name:PIT_SR Address:0xFFFFFE34 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. DS60001517A-page 142  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 15.5.3 Periodic Interval Timer Value Register Name:PIT_PIVR Address:0xFFFFFE38 Access:Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.  2017 Microchip Technology Inc. DS60001517A-page 143 SAM9N12/SAM9CN11/SAM9CN12 15.5.4 Periodic Interval Timer Image Register Name:PIT_PIIR Address:0xFFFFFE3C Access:Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. DS60001517A-page 144  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 16. Watchdog Timer (WDT) 16.1 Description The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in Debug mode or Idle mode. 16.2 • • • • Embedded Characteristics 12-bit Key-protected Programmable Counter Watchdog Clock is Independent from Processor Clock Provides Reset or Interrupt Signals to the System Counter May Be Stopped while the Processor is in Debug State or in Idle Mode 16.3 Block Diagram Figure 16-1: Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR WDD reload Current Value 1/128 SLCK 1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 23.5.2 23.5.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing one to the RXEN bit in the Debug Unit Control register (DBGU_CR). At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing a one to the RXDIS bit in the DBGU_CR. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing a one to the RSTRX bit in the DBGU_CR. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 23.5.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Figure 23-4: Start Bit Detection Sampling Clock DRXD True Start Detection D0 Baud Rate Clock DS60001517A-page 272  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 23-5: Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling 23.5.2.3 D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit Receiver Ready When a complete character is received, it is transferred to the Debug Unit Receive Holding register (DBGU_RHR) and the RXRDY status bit in the Debug Unit Status register (DBGU_SR) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 23-6: Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 23.5.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes a one to the bit RSTSTA (Reset Status) in the DBGU_CR. Figure 23-7: Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 23.5.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in the Debug Unit Mode register (DBGU_MR). It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time as the RXRDY is set. The parity bit is cleared when a one is written to the bit RSTSTA (Reset Status) in the DBGU_CR. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 23-8: Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit  2017 Microchip Technology Inc. RSTSTA DS60001517A-page 273 SAM9N12/SAM9CN11/SAM9CN12 23.5.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time as the RXRDY bit is set. The bit FRAME remains high until a one is written to the RSTSTA bit in the DBGU_CR. Figure 23-9: Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 23.5.3 23.5.3.1 RSTSTA Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing a one to the TXEN bit in DBGU_CR. From this command, the transmitter waits for a character to be written in the Transmit Holding register (DBGU_THR) before actually starting the transmission. The programmer can disable the transmitter by writing a one to the TXDIS bit in the DBGU_CR. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing a one to the RSTTX bit in the DBGU_CR. This immediately stops the transmitter, whether or not it is processing characters. 23.5.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in DBGU_MR and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 23-10: Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit 23.5.3.3 D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in DBGU_SR. The transmission starts when the programmer writes in DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. DS60001517A-page 274  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 23-11: Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 Data 0 S Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR 23.5.4 Write Data 1 in DBGU_THR DMA Support Both the receiver and the transmitter of the Debug Unit’s UART are connected to a DMA Controller (DMAC) channel. The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface. 23.5.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.  2017 Microchip Technology Inc. DS60001517A-page 275 SAM9N12/SAM9CN11/SAM9CN12 Figure 23-12: Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter 23.5.6 TXD VDD Disabled Disabled RXD TXD Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the Arm Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the Arm Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 23.5.7 Chip Identifier The Debug Unit features two chip identifier registers, Debug Unit Chip ID register (DBGU_CIDR) and Debug Unit Extension ID register (DBGU_EXID). Both registers contain a hard-wired value that is read-only. The first register (DBGU_CIDR) contains the following fields: • EXT: shows the use of the extension identifier register • NVPTYP and NVPSIZ: identifies the type of embedded non-volatile memory and its size DS60001517A-page 276  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 • • • • ARCH: identifies the set of embedded peripherals SRAMSIZ: indicates the size of the embedded SRAM EPROC: indicates the embedded Arm processor VERSION: gives the revision of the silicon The second register (DBGU_EXID) is device-dependent and is read as 0 if the bit EXT is 0 in DBGU_CIDR. 23.5.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the Arm processor's ICE interface. This feature is implemented via the Debug Unit Force NTRST register (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.  2017 Microchip Technology Inc. DS60001517A-page 277 SAM9N12/SAM9CN11/SAM9CN12 23.6 Debug Unit (DBGU) User Interface Table 23-3: Register Mapping Offset Register Name Access Reset 0x0000 Control Register DBGU_CR Write-only – 0x0004 Mode Register DBGU_MR Read/Write 0x0 0x0008 Interrupt Enable Register DBGU_IER Write-only – 0x000C Interrupt Disable Register DBGU_IDR Write-only – 0x0010 Interrupt Mask Register DBGU_IMR Read-only 0x0 0x0014 Status Register DBGU_SR Read-only – 0x0018 Receive Holding Register DBGU_RHR Read-only 0x0 0x001C Transmit Holding Register DBGU_THR Write-only – 0x0020 Baud Rate Generator Register DBGU_BRGR Read/Write 0x0 – – – 0x0024 - 0x003C Reserved 0x0040 Chip ID Register DBGU_CIDR Read-only – 0x0044 Chip ID Extension Register DBGU_EXID Read-only – 0x0048 Force NTRST Register DBGU_FNR Read/Write 0x0 – – – 0x004C - 0x00FC DS60001517A-page 278 Reserved  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 23.6.1 Debug Unit Control Register Name:DBGU_CR Address:0xFFFFF200 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted. RSTTX: Reset Transmitter 0: No effect. 1: The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. RXEN: Receiver Enable 0: No effect. 1: The receiver is enabled if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. TXEN: Transmitter Enable 0: No effect. 1: The transmitter is enabled if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: The transmitter is disabled. If a character is being processed and a character has been written in the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME and OVRE in DBGU_SR.  2017 Microchip Technology Inc. DS60001517A-page 279 SAM9N12/SAM9CN11/SAM9CN12 23.6.2 Debug Unit Mode Register Name:DBGU_MR Address:0xFFFFF204 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 14 13 12 11 10 9 – – 15 CHMODE PAR 8 – 7 6 5 4 3 2 1 0 – – – – – – – – PAR: Parity Type Value Name Description 0b000 EVEN Even Parity 0b001 ODD Odd Parity 0b010 SPACE Space: Parity forced to 0 0b011 MARK Mark: Parity forced to 1 0b1xx NONE No Parity CHMODE: Channel Mode Value Name Description 0b00 NORM Normal Mode 0b01 AUTO Automatic Echo 0b10 LOCLOOP Local Loopback 0b11 REMLOOP Remote Loopback DS60001517A-page 280  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 23.6.3 Debug Unit Interrupt Enable Register Name:DBGU_IER Address:0xFFFFF208 Access:Write-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY RXRDY: Enable RXRDY Interrupt TXRDY: Enable TXRDY Interrupt OVRE: Enable Overrun Error Interrupt FRAME: Enable Framing Error Interrupt PARE: Enable Parity Error Interrupt TXEMPTY: Enable TXEMPTY Interrupt COMMTX: Enable COMMTX (from Arm) Interrupt COMMRX: Enable COMMRX (from Arm) Interrupt 0: No effect. 1: Enables the corresponding interrupt.  2017 Microchip Technology Inc. DS60001517A-page 281 SAM9N12/SAM9CN11/SAM9CN12 23.6.4 Debug Unit Interrupt Disable Register Name:DBGU_IDR Address:0xFFFFF20C Access:Write-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY RXRDY: Disable RXRDY Interrupt TXRDY: Disable TXRDY Interrupt OVRE: Disable Overrun Error Interrupt FRAME: Disable Framing Error Interrupt PARE: Disable Parity Error Interrupt TXEMPTY: Disable TXEMPTY Interrupt COMMTX: Disable COMMTX (from Arm) Interrupt COMMRX: Disable COMMRX (from Arm) Interrupt 0: No effect. 1: Disables the corresponding interrupt. DS60001517A-page 282  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 23.6.5 Debug Unit Interrupt Mask Register Name:DBGU_IMR Address:0xFFFFF210 Access:Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY RXRDY: Mask RXRDY Interrupt TXRDY: Disable TXRDY Interrupt OVRE: Mask Overrun Error Interrupt FRAME: Mask Framing Error Interrupt PARE: Mask Parity Error Interrupt TXEMPTY: Mask TXEMPTY Interrupt COMMTX: Mask COMMTX Interrupt COMMRX: Mask COMMRX Interrupt 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.  2017 Microchip Technology Inc. DS60001517A-page 283 SAM9N12/SAM9CN11/SAM9CN12 23.6.6 Debug Unit Status Register Name:DBGU_SR Address:0xFFFFF214 Access:Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY RXRDY: Receiver Ready 0: No character has been received since the last read of the DBGU_RHR, or the receiver is disabled. 1: At least one complete character has been received, transferred to DBGU_RHR and not yet read. TXRDY: Transmitter Ready 0: A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1: There is no character written to DBGU_THR not yet transferred to the Shift Register. OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. FRAME: Framing Error 0: No framing error has occurred since the last RSTSTA. 1: At least one framing error has occurred since the last RSTSTA. PARE: Parity Error 0: No parity error has occurred since the last RSTSTA. 1: At least one parity error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty 0: There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1: There are no characters in DBGU_THR and there are no characters being processed by the transmitter. COMMTX: Debug Communication Channel Write Status 0: COMMTX from the Arm processor is inactive. 1: COMMTX from the Arm processor is active. COMMRX: Debug Communication Channel Read Status 0: COMMRX from the Arm processor is inactive. 1: COMMRX from the Arm processor is active. DS60001517A-page 284  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 23.6.7 Debug Unit Receive Holding Register Name:DBGU_RHR Address:0xFFFFF218 Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last received character if RXRDY is set.  2017 Microchip Technology Inc. DS60001517A-page 285 SAM9N12/SAM9CN11/SAM9CN12 23.6.8 Debug Unit Transmit Holding Register Name:DBGU_THR Address:0xFFFFF21C Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. DS60001517A-page 286  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 23.6.9 Debug Unit Baud Rate Generator Register Name:DBGU_BRGR Address:0xFFFFF220 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD CD: Clock Divisor Value Name Description 0 DISABLED DBGU Disabled 1 MCK Peripheral clock – Peripheral clock/ (CD x 16) 2 to 65535  2017 Microchip Technology Inc. DS60001517A-page 287 SAM9N12/SAM9CN11/SAM9CN12 23.6.10 Debug Unit Chip ID Register Name:DBGU_CIDR Address:0xFFFFF240 Access:Read-only 31 30 29 EXT 28 27 26 NVPTYP 23 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 EPROC 3 2 VERSION VERSION: Version of the Device Values depend on the version of the device. EPROC: Embedded Processor Value Name Description 1 ARM946ES Arm946ES 2 ARM7TDMI Arm7TDMI 3 CM3 Cortex-M3 4 ARM920T Arm920T 5 ARM926EJS Arm926EJ-S 6 CA5 Cortex-A5 NVPSIZ: Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 – Reserved 7 128K 128 Kbytes 8 – Reserved 9 256K 256 Kbytes 10 512K 512 Kbytes 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved DS60001517A-page 288  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 NVPSIZ2: Second Nonvolatile Program Memory Size Value Name Description 0 NONE None 1 8K 8 Kbytes 2 16K 16 Kbytes 3 32K 32 Kbytes 4 – Reserved 5 64K 64 Kbytes 6 Reserved 7 128K 128 Kbytes 8 – Reserved 9 256K 256 Kbytes 10 512K 512 Kbytes 11 – Reserved 12 1024K 1024 Kbytes 13 – Reserved 14 2048K 2048 Kbytes 15 – Reserved SRAMSIZ: Internal SRAM Size Value Name Description 0 – Reserved 1 1K 1 Kbytes 2 2K 2 Kbytes 3 6K 6 Kbytes 4 112K 112 Kbytes 5 4K 4 Kbytes 6 80K 80 Kbytes 7 160K 160 Kbytes 8 8K 8 Kbytes 9 16K 16 Kbytes 10 32K 32 Kbytes 11 64K 64 Kbytes 12 128K 128 Kbytes 13 256K 256 Kbytes 14 96K 96 Kbytes 15 512K 512 Kbytes  2017 Microchip Technology Inc. DS60001517A-page 289 SAM9N12/SAM9CN11/SAM9CN12 ARCH: Architecture Identifier Value Name Description 0x19 AT91SAM9xx AT91SAM9xx Series 0x29 AT91SAM9XExx AT91SAM9XExx Series 0x34 AT91x34 AT91x34 Series 0x37 CAP7 CAP7 Series 0x39 CAP9 CAP9 Series 0x3B CAP11 CAP11 Series 0x40 AT91x40 AT91x40 Series 0x42 AT91x42 AT91x42 Series 0x55 AT91x55 AT91x55 Series 0x60 AT91SAM7Axx AT91SAM7Axx Series 0x61 AT91SAM7AQxx AT91SAM7AQxx Series 0x63 AT91x63 AT91x63 Series 0x70 AT91SAM7Sxx AT91SAM7Sxx Series 0x71 AT91SAM7XCxx AT91SAM7XCxx Series 0x72 AT91SAM7SExx AT91SAM7SExx Series 0x73 AT91SAM7Lxx AT91SAM7Lxx Series 0x75 AT91SAM7Xxx AT91SAM7Xxx Series 0x76 AT91SAM7SLxx AT91SAM7SLxx Series 0x80 ATSAM3UxC ATSAM3UxC Series (100-pin version) 0x81 ATSAM3UxE ATSAM3UxE Series (144-pin version) 0x83 ATSAM3AxC ATSAM3AxC Series (100-pin version) 0x84 ATSAM3XxC ATSAM3XxC Series (100-pin version) 0x85 ATSAM3XxE ATSAM3XxE Series (144-pin version) 0x86 ATSAM3XxG ATSAM3XxG Series (208/217-pin version) 0x88 ATSAM3SxA ATSAM3SxA Series (48-pin version) 0x89 ATSAM3SxB ATSAM3SxB Series (64-pin version) 0x8A ATSAM3SxC ATSAM3SxC Series (100-pin version) 0x92 AT91x92 AT91x92 Series 0x93 ATSAM3NxA ATSAM3NxA Series (48-pin version) 0x94 ATSAM3NxB ATSAM3NxB Series (64-pin version) 0x95 ATSAM3NxC ATSAM3NxC Series (100-pin version) 0x98 ATSAM3SDxA ATSAM3SDxA Series (48-pin version) 0x99 ATSAM3SDxB ATSAM3SDxB Series (64-pin version) 0x9A ATSAM3SDxC ATSAM3SDxC Series (100-pin version) 0xA5 ATSAMA5xx ATSAMA5xx Series 0xF0 AT75Cxx AT75Cxx Series DS60001517A-page 290  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 NVPTYP: Nonvolatile Program Memory Type Value Name Description 0 ROM ROM 1 ROMLESS ROMless or on-chip Flash 4 SRAM SRAM emulating ROM 2 FLASH Embedded Flash Memory 3 ROM_FLASH ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size EXT: Extension Flag 0: Chip ID has a single register definition without extension. 1: An extended Chip ID exists.  2017 Microchip Technology Inc. DS60001517A-page 291 SAM9N12/SAM9CN11/SAM9CN12 23.6.11 Debug Unit Chip ID Extension Register Name:DBGU_EXID Address:0xFFFFF244 Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID EXID: Chip ID Extension Read as 0 if the bit EXT in DBGU_CIDR is 0. DS60001517A-page 292  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 23.6.12 Debug Unit Force NTRST Register Name: DBGU_FNR Address:0xFFFFF248 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST FNTRST: Force NTRST 0: NTRST of the Arm processor’s TAP controller is driven by the power_on_reset signal. 1: NTRST of the Arm processor’s TAP controller is held low.  2017 Microchip Technology Inc. DS60001517A-page 293 SAM9N12/SAM9CN11/SAM9CN12 24. Fuse Controller (FUSE) 24.1 Description The Fuse Controller (FUSE) supports software fuse programming through a 32-bit register, only fuses set to level “1” are programmed. It reads the fuse states on startup and stores them into 32-bit registers. The first 8 Fuse Status registers (FUSE_SRx) can be masked and will read as a value of “0” regardless of the fuse state when masked. 24.2 Embedded Characteristics • Software Fuse Programming • User Write Access for Fuse • Part of Fuse can be Masked After Read 24.3 Block Diagram Figure 24-1: Fuse Controller Block Diagram Fuse States Fuse States Fuse Cells Fuse Controller Controls Controls 24.4 24.4.1 Functional Description Fuse Reading The fuse states are automatically read on CORE startup and are available for reading in the 10 Fuse Status (FUSE_SRx) registers. The fuse states of bits 31 to 0 will be available at FUSE_SR0, the fuse states of bits 63 to 32 will be available at FUSE_SR1 and so on. FUSE_SRx registers can be updated manually by using the RRQ bit of the Fuse Control register (FUSE_CR). RS and WS bits of the Fuse Index register (FUSE_IR) must be at level one before issuing the read request. DS60001517A-page 294  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 24-2: Fuse Read Clock FUSE_SRx outdated up to date RRQ WS RS 24.4.2 Fuse Programming All the fuses can be written by software. To program fuses, strictly follow the order of the sequence instructions as provided below: 1. 2. 3. 4. 5. Select the word to write, using the SELW field of the Fuse_Index register (FUSE_IR). Write the word to program in the Fuse_Data register (FUSE_DR). Check that RS and WS bits of the Fuse_Index register are at level one (no read and no write pending). Write the WRQ bit of the Fuse_Control register (FUSE_CR) to begin the fuse programming. The KEY field must be written at the same time with a value 0xFB to make the write request valid. Writing the WRQ bit will clear the WS bit. Check the WS bit of FUSE_SRx, when WS has a value of “1” the fuse write process is over. Only fuses to be set to level “1” are written. Figure 24-3: Fuse Write Clock WSEL DATA XX 00 XX 01 Fuse[31:0] Fuse[63:32] WRQ WS RS 24.4.3 Fuse Masking It is possible to mask the first 8 FUSE_SRx registers so that they will be read at a value of “0”, regardless of the fuse state. To activate fuse masking on the first 8 FUSE_SRx registers, the MSK bit of the Fuse Mode register (FUSE_MR) must be written to level “1”. The MSK bit is write-only. Solely a general reset can disable fuse masking.  2017 Microchip Technology Inc. DS60001517A-page 295 SAM9N12/SAM9CN11/SAM9CN12 24.5 Fuse Controller (FUSE) User Interface Table 24-1: Offset Register Mapping Register Name Access Reset 0x00 Fuse Control Register FUSE_CR Write-only – 0x04 Fuse Mode Register FUSE_MR Write-only – 0x08 Fuse Index Register FUSE_IR Read/Write 0x00000000 0x0C Fuse Data Register FUSE_DR Read/Write – 0x10 Fuse Status Register 0 FUSE_SR0 Read-only 0x00000000 0x14 Fuse Status Register 1 FUSE_SR1 Read-only 0x00000000 ... ... ... FUSE_SR9 Read-only 0x00000000 ... 0x34 ... Fuse Status Register 9 0x38–0xDC Reserved – – – 0xE0–0xFC Reserved – – – DS60001517A-page 296  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 24.5.1 Fuse Control Register Name:FUSE_CR Address:0xFFFFDC00 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 RRQ 0 WRQ KEY 7 – 6 – 5 – 4 – WRQ: Write Request 0: No effect. 1: Request the word DATA to be programmed, ignored if KEY field is not filled with 0xFB. RRQ: Read Request 0: No effect. 1: Requests the fuses to be read and FUSE_SRx registers are then updated. Ignored if KEY field is not filled with 0xFB. KEY: Password Key Value Name 0xFB PASSWORD  2017 Microchip Technology Inc. Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. DS60001517A-page 297 SAM9N12/SAM9CN11/SAM9CN12 24.5.2 Fuse Mode Register Name:FUSE_MR Address:0xFFFFDC04 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MSK MSK: Mask Fuse Status Registers 0: No effect. 1: Masks the first 8 FUSE_SRx registers. DS60001517A-page 298  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 24.5.3 Fuse Index Register Name:FUSE_IR Address:0xFFFFDC08 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 RS 0 WS WSEL 2 – WS: Write Status 0: Write is pending or no write has been requested since general reset. 1: Write of fuses is done. RS: Read Status 0: Read is pending or no read has been requested since general reset. 1: Read of fuses is done. WSEL: Word Selection 0-15: Selects the word to write.  2017 Microchip Technology Inc. DS60001517A-page 299 SAM9N12/SAM9CN11/SAM9CN12 24.5.4 Fuse Data Register Name:FUSE_DR Address:0xFFFFDC0C Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA DATA: Data to Program Data to program. Only bits of with a value of “1” will be programmed. DS60001517A-page 300  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 24.5.5 Fuse Status Register Name:FUSE_SRx [x=0..9] Address:0xFFFFDC10 Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FUSE 23 22 21 20 FUSE 15 14 13 12 FUSE 7 6 5 4 FUSE FUSE: Fuse Status Indicates the status of corresponding fuses: 0: Unprogrammed. 1: Programmed.  2017 Microchip Technology Inc. DS60001517A-page 301 SAM9N12/SAM9CN11/SAM9CN12 25. Bus Matrix (MATRIX) 25.1 Description The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with Arm Advanced Peripheral Bus and provides a Chip Configuration User Interface with Registers that allow the Bus Matrix to support application specific features. 25.2 Embedded Characteristics • 6-layer Matrix, handling requests from 6 masters • Programmable Arbitration strategy - Fixed-priority Arbitration - Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master • Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support • One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one after remap • Boot Mode Select - Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0 • Remap Command - Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash) - Allows Handling of Dynamic Exception Vectors 25.3 Matrix Masters The Bus Matrix of the SAM9N12/SAM9CN11/SAM9CN12 product manages six masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 25-1: List of Bus Matrix Masters Master 0 Arm926 Instruction Master 1 Arm926 Data Master 2&3 DMA Controller Master 4 USB Host DMA Master 5 LCD DMA 25.4 Matrix Slaves The Bus Matrix of the SAM9N12/SAM9CN11/SAM9CN12 product manages five slaves. Each slave has its own arbiter, allowing a different arbitration per slave. DS60001517A-page 302  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 25-2: List of Bus Matrix Slaves Slave 0 Internal SRAM Internal ROM Slave 1 USB Host User Interface Slave 2 External Bus Interface Slave 3 Peripheral Bridge 0 Slave 4 Peripheral Bridge 1 25.5 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table. Table 25-3: SAM9N12/SAM9CN11/SAM9CN12 Master to Slave Access Masters Slaves 0 1 Internal SRAM Internal ROM USB Host User Interface 0 1 2&3 4 5 Arm926 Instruction Arm926 Data DMA USB Host DMA LCD DMA X X X X X X X X – – 2 External Bus Interface X X X X X 3 Peripheral Bridge 0 X X X – – 4 Peripheral Bridge 1 X X X – – 25.6 Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently. 25.7 Special Bus Granting Mechanism The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first access of a burst or single transfer as long as the slave is free from any other master access, but does not provide any benefit as soon as the slave is continuously accessed by more than one master, since arbitration is pipelined and then has no negative effect on the slave bandwidth or access latency. This bus granting mechanism sets a different default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master. To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to Section 25.10.2 “Bus Matrix Slave Configuration Registers”.  2017 Microchip Technology Inc. DS60001517A-page 303 SAM9N12/SAM9CN11/SAM9CN12 25.7.1 No Default Master After the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits lowpower mode. This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or more masters. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. 25.7.2 Last Access Master After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. 25.7.3 Fixed Default Master After the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master does not change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG). This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. Every request attempted by this fixed default master will not cause any arbitration latency whereas other non privileged masters will still get one latency cycle. This technique is useful for a master that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. 25.8 Arbitration The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each slave differently. The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for each slave: 1. 2. Round-Robin Arbitration (default) Fixed Priority Arbitration The resulting algorithm may be complemented by selecting a default master configuration for each slave. When a re-arbitration must be done, specific conditions apply. See Section 25.8.1 “Arbitration Scheduling”. 25.8.1 Arbitration Scheduling Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. 2. 3. 4. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. Single Cycles: When a slave is currently doing a single access. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See Section 25.8.1.1 “Undefined Length Burst Arbitration”. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. See Section 25.8.1.2 “Slot Cycle Limit Arbitration”. DS60001517A-page 304  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 25.8.1.1 Undefined Length Burst Arbitration In order to optimize AHB burst lengths and arbitration, it may be interesting to set a maximum for undefined length bursts (INCR). The Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected from among the following Undefined Length Burst Type (ULBT) possibilities: 1. 2. 3. 4. 5. 6. 7. 8. Unlimited: No predicted end of burst is generated and therefore INCR burst transfer will not be broken by this way, but will be able to complete unless broken at the Slot Cycle Limit. This is normally the default and should be let as is in order to be able to allow full 1 Kilobyte AHB intra-boundary 256-beat word bursts performed by some Microchip AHB masters. 1-beat bursts: Predicted end of burst is generated at each single transfer inside the INCR transfer. 4-beat bursts: Predicted end of burst is generated at the end of each 4-beat boundary inside INCR transfer. 8-beat bursts: Predicted end of burst is generated at the end of each 8-beat boundary inside INCR transfer. 16-beat bursts: Predicted end of burst is generated at the end of each 16-beat boundary inside INCR transfer. 32-beat bursts: Predicted end of burst is generated at the end of each 32-beat boundary inside INCR transfer. 64-beat bursts: Predicted end of burst is generated at the end of each 64-beat boundary inside INCR transfer. 128-beat bursts: Predicted end of burst is generated at the end of each 128-beat boundary inside INCR transfer. Use of undefined length 16-beat bursts or less is discouraged since this generally decreases significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. If the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ULBT should be let at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kbyte address boundaries. Unless duly needed the ULBT should be let to its default 0 value for power saving. This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). 25.8.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as back to back undefined length bursts or very long bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access cycle. Unless some master has a very tight access latency constraint which could lead to data overflow or underflow due to a badly undersized internal fifo with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or let to its default maximum value in order not to inefficiently break long bursts performed by some Microchip masters. However, the Slot Cycle Limit should not be disabled in the very particular case of a master capable of accessing the slave by performing back to back undefined length bursts shorter than the number of ULBT beats with no Idle cycle in between, since in this case the arbitration could be frozen all along the bursts sequence. In most cases this feature is not needed and should be disabled for power saving. Warning: This feature cannot prevent any slave from locking its access indefinitely. 25.8.2 Arbitration Priority Scheme The bus Matrix arbitration scheme is organized in priority pools. Round-Robin priority is used inside the highest and lowest priority pools, whereas fix level priority is used between priority pools and inside the intermediate priority pools. For each slave, each master x is assigned to one of the slave priority pools through the Priority Registers for Slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating masters requests, this programmed priority level always takes precedence. After reset, all the masters are belonging to the lowest priority pool (MxPR = 0) and so are granted bus access in a true Round-Robin fashion. The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one master belong to this pool, these will be granted bus access in a biased Round-Robin fashion which allow tight and deterministic maximum access latency from AHB bus request. In fact, at worst, any currently high priority master request will be granted after the current bus master access is ended and the other high priority pool masters, if any, have been granted once each. The lowest priority pool shares the remaining bus bandwidth between AHB Masters. Intermediate priority pools allow fine priority tuning. Typically, a moderately latency critical master or a bandwidth only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master priority.  2017 Microchip Technology Inc. DS60001517A-page 305 SAM9N12/SAM9CN11/SAM9CN12 All combination of MxPR values are allowed for all masters and slaves. For example some masters might be assigned to the highest priority pool (round-robin) and the remaining masters to the lowest priority pool (round-robin), with no master for intermediate fix priority levels. If more than one master is requesting the slave bus, whatever are the respective masters priorities, no master will be granted the slave bus for two consecutive runs. A master can only get back to back grants as long as it is the only requesting master. 25.8.2.1 Fixed Priority Arbitration This arbitration algorithm is the first and only applied between masters from distinct priority pools. It is also used inside priority pools other than the highest and lowest ones (intermediate priority pools). It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the MxPR field for each master inside the MATRIX_PRAS and MATRIX_PRBS Priority Registers. If two or more master requests are active at the same time, the master with the highest priority number MxPR is serviced first. Inside intermediate priority pools, if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. 25.8.2.2 Round-Robin Arbitration This algorithm is only used inside the highest and lowest priority pools. It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a fair way. If two or more master requests are active at the same time inside the priority pool, they are serviced in a round-robin increasing master number order. 25.9 Write Protect Registers To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from address offset 0x000 to 0x1FC can be write protected by setting the WPEN bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR). If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the appropriate access key WPKEY. DS60001517A-page 306  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 25.10 Bus Matrix (MATRIX) User Interface Table 25-4: Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read/Write 0x00000001 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read/Write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read/Write 0x00000000 0x000C Master Configuration Register 3 MATRIX_MCFG3 Read/Write 0x00000000 0x0010 Master Configuration Register 4 MATRIX_MCFG4 Read/Write 0x00000000 0x0014 Master Configuration Register 5 MATRIX_MCFG5 Read/Write 0x00000000 – – 0x0018–0x003C Reserved – 0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read/Write 0x000001FF 0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read/Write 0x000001FF 0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read/Write 0x000001FF 0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read/Write 0x000001FF 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read/Write 0x000001FF – – Read/Write 0x00000000 – – Read/Write 0x00000000 – – Read/Write 0x00000000 – – Read/Write 0x00000000 – – Read/Write 0x00000000 – – Read/Write 0x00000000 0x0054–0x007C Reserved 0x0080 Priority Register A for Slave 0 0x0084 Reserved 0x0088 Priority Register A for Slave 1 0x008C Reserved 0x0090 Priority Register A for Slave 2 0x0094 Reserved 0x0098 Priority Register A for Slave 3 0x009C Reserved 0x00A0 Priority Register A for Slave 4 0x00A4–0x00FC 0x0100 Reserved Master Remap Control Register – MATRIX_PRAS0 – MATRIX_PRAS1 – MATRIX_PRAS2 – MATRIX_PRAS3 – MATRIX_PRAS4 – MATRIX_MRCR 0x0104–0x010C Reserved – – – 0x0110–0x01E0 Chip Configuration Registers – – – 0x01E4 Write Protect Mode Register MATRIX_WPMR Read/Write 0x00000000 0x01E8 Write Protect Status Register MATRIX_WPSR Read-only 0x00000000  2017 Microchip Technology Inc. DS60001517A-page 307 SAM9N12/SAM9CN11/SAM9CN12 25.10.1 Bus Matrix Master Configuration Registers Name:MATRIX_MCFG0...MATRIX_MCFG5 Addresses:0xFFFFDE00 [0], 0xFFFFDE04 [1], 0xFFFFDE08 [2], 0xFFFFDE0C [3], 0xFFFFDE10 [4], 0xFFFFDE14 [5] Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 2 1 0 7 6 5 4 3 – – – – – ULBT ULBT: Undefined Length Burst Type 0: Unlimited Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. 1: Single Access The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst. 2: 4-beat Burst The undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end. 3: 8-beat Burst The undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end. 4: 16-beat Burst The undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end. 5: 32-beat Burst The undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end. 6: 64-beat Burst The undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end. 7: 128-beat Burst The undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end. Unless duly needed the ULBT should be let to its default 0 value for power saving. DS60001517A-page 308  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 25.10.2 Bus Matrix Slave Configuration Registers Name:MATRIX_SCFG0...MATRIX_SCFG4 Addresses:0xFFFFDE40 [0], 0xFFFFDE44 [1], 0xFFFFDE48 [2], 0xFFFFDE4C [3], 0xFFFFDE50 [4] Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – 15 14 13 12 11 10 9 8 – – – – – – – SLOT_CYCLE 7 6 5 4 3 2 1 0 FIXED_DEFMSTR DEFMSTR_TYPE SLOT_CYCLE SLOT_CYCLE: Maximum Bus Grant Duration for Masters When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place so as to let an other master access this slave. If an other master is requesting the slave bus, then the current master burst is broken. If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to the ULBT. This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access or in the particular case of a master performing back to back undefined length bursts indefinitely freezing the arbitration. This limit must not be small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice. In most cases this feature is not needed and should be disabled for power saving. See Section 25.8.1.2 “Slot Cycle Limit Arbitration”. DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having one clock cycle latency when the last master tries to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one clock cycle latency when the fixed master tries to access the slave again. FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.  2017 Microchip Technology Inc. DS60001517A-page 309 SAM9N12/SAM9CN11/SAM9CN12 25.10.3 Bus Matrix Priority Registers A For Slaves Name:MATRIX_PRAS0...MATRIX_PRAS4 Addresses:0xFFFFDE80 [0], 0xFFFFDE88 [1], 0xFFFFDE90 [2], 0xFFFFDE98 [3], 0xFFFFDEA0 [4] Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – 15 14 11 10 – – – – 7 6 – – M5PR 13 12 M3PR 5 4 M1PR 3 2 – – 16 M4PR 9 8 M2PR 1 0 M0PR MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-Robin arbitration is used inside the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used inside intermediate priority pools (MxPR = 1) and (MxPR = 2). See Section 25.8.2 “Arbitration Priority Scheme” for details. DS60001517A-page 310  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 25.10.4 Bus Matrix Master Remap Control Register Name:MATRIX_MRCR Address:0xFFFFDF00 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 RCBx: Remap Command Bit for Master x 0: Disables remapped address decoding for the selected Master. 1: Enables remapped address decoding for the selected Master.  2017 Microchip Technology Inc. DS60001517A-page 311 SAM9N12/SAM9CN11/SAM9CN12 25.10.5 Chip Configuration User Interface Table 25-5: Chip Configuration User Interface Offset Register 0x0110–0x0114 Reserved 0x0118 0x011C–0x01FC EBI Chip Select Assignment Register Reserved DS60001517A-page 312 Name – CCFG_EBICSA – Access Reset Value – – Read/Write 0x00000000 – –  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 25.10.5.1 EBI Chip Select Assignment Register Name:CCFG_EBICSA Access:Read/Write Reset:0x0000_0000 31 30 29 28 27 26 25 24 – – – – – – – NFD0_ON_D16 23 22 21 20 19 18 17 16 – – – – – – EBI_DRIVE – 15 14 13 12 11 10 9 8 – – – – – – EBI_DBPDC EBI_DBPUC 7 6 5 4 3 2 1 0 – – – – EBI_CS3A – EBI_CS1A – EBI_CS1A: EBI Chip Select 1 Assignment 0: EBI Chip Select 1 is assigned to the Static Memory Controller. 1: EBI Chip Select 1 is assigned to the DDR2SDR Controller. EBI_CS3A: EBI Chip Select 3 Assignment 0: EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC. 1: EBI Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated. EBI_DBPUC: EBI Data Bus Pull-Up Configuration 0: EBI D0–D15 Data Bus bits are internally pulled-up to the VDDIOM power supply. 1: EBI D0–D15 Data Bus bits are not internally pulled-up. EBI_DBPDC: EBI Data Bus Pull-Down Configuration 0: EBI D0–D15 Data Bus bits are internally pulled-down to the GND. 1: EBI D0–D15 Data Bus bits are not internally pulled-down. EBI_DRIVE: EBI I/O Drive Configuration 0: LOW drive(1) 1: HIGH drive (default)(1) Note 1: Load capacitance defined in Table 47-18 ”I/O Characteristics” NFD0_ON_D16: NAND Flash databus selection 0: NAND Flash I/Os are connected to D0–D15. VDDNF must be equal to VDDIOM (default). 1: NAND Flash I/Os are connected to D16–D31. VDDNF can be different from or equal to VDDIOM. This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC will lead to an unpredictable behavior of that device. In that case, the default value must be selected. Table 25-6: Connection Examples with Various VDDNF and VDDIOM NFD0_ON_D16 Signals VDDIOM VDDNF External Memory 0 NFD0 = D0, ..., NFD15 = D15 1.8V 1.8V DDR2 or LPDDR or LPSDR + NAND Flash 1.8V 0 NFD0 = D0, ..., NFD15 = D15 3.3V 3.3V 32-bit SDR + NAND Flash 3.3V  2017 Microchip Technology Inc. DS60001517A-page 313 SAM9N12/SAM9CN11/SAM9CN12 Table 25-6: Connection Examples with Various VDDNF and VDDIOM (Continued) 1 NFD0 = D16, ..., NFD15 = D31 1.8V 1.8V DDR2 or LPDDR or LPSDR + NAND Flash 1.8V 1 NFD0 = D16, ..., NFD15 = D31 1.8V 3.3V DDR2 or LPDDR or LPSDR + NAND Flash 3.3V 1 NFD0 = D16, ..., NFD15 = D31 3.3V 1.8V 16-bit SDR + NAND Flash 1.8V DS60001517A-page 314  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 25.10.6 Write Protect Mode Register Name:MATRIX_WPMR Address:0xFFFFDFE4 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 25.9 “Write Protect Registers”. WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). Protects the entire MATRIX address space from address offset 0x000 to 0x1FC. WPKEY: Write Protect Key (Write-only) Value 0x4D4154 Name PASSWD  2017 Microchip Technology Inc. Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. DS60001517A-page 315 SAM9N12/SAM9CN11/SAM9CN12 25.10.7 Write Protect Status Register Name:MATRIX_WPSR Address:0xFFFFDFE8 Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 25.9 “Write Protect Registers”. WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR. 1: At least one Write Protect Violation has occurred since the last write of the MATRIX_WPMR. WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the register address offset in which a write access has been attempted. Otherwise it reads as 0. DS60001517A-page 316  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26. External Bus Interface (EBI) 26.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an Arm-based device. The Static Memory, DDR, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, DDR2 and SDRAM. The EBI operates with 1.8V or 3.3V Power Supply (VDDIOM). The EBI also supports the NAND Flash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (NCS[5:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 26.2 Embedded Characteristics 32-bit Wide Interface, Supporting: • 16-bit DDR2/LPDDR, 32-bit SDRAM/LPSDR • Static Memories • NAND Flash with Multi-bit ECC  2017 Microchip Technology Inc. DS60001517A-page 317 SAM9N12/SAM9CN11/SAM9CN12 26.3 EBI Block Diagram Figure 26-1: Organization of the External Bus Interface External Bus Interface Bus Matrix D[15:0] AHB DDR2 LPDDR SDRAM Controller A0/NBS0 A1/NWR2/NBS2/DQM2 A[15:2], A19 A16/BA0 A17/BA1 MUX Logic Static Memory Controller A18/BA2 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3/DQM3 SDCK, SDCK#, SDCKE DQM[1:0] DQS[1:0] RAS, CAS SDWE, SDA10 NAND Flash Logic NCS3/NANDCS PMECC PMERRLOC Controllers NANDOE NANDWE PIO A21/NANDALE A22/NANDCLE Address Decoders Chip Select Assignor D[31:16] A[25:20] NCS5 NCS4 User Interface NCS2 NWAIT APB DS60001517A-page 318  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26.4 I/O Lines Description Table 26-1: EBI I/O Lines Description Name Function Type Active Level I/O – Output – Input Low EBI EBI_D0–EBI_D31 Data Bus EBI_A0–EBI_A25 Address Bus EBI_NWAIT External Wait Signal SMC EBI_NCS0–EBI_NCS5 Chip Select Lines Output Low EBI_NWR0–EBI_NWR3 Write Signals Output Low EBI_NRD Read Signal Output Low EBI_NWE Write Enable Output Low EBI_NBS0–EBI_NBS3 Byte Mask Signals Output Low EBI for NAND Flash Support EBI_NANDCS NAND Flash Chip Select Line Output Low EBI_NANDOE NAND Flash Output Enable Output Low EBI_NANDWE NAND Flash Write Enable Output Low DDR2/SDRAM Controller EBI_SDCK, EBI_SDCK# DDR2/SDRAM Differential Clock Output – EBI_SDCKE DDR2/SDRAM Clock Enable Output High EBI_SDCS DDR2/SDRAM Controller Chip Select Line Output Low EBI_BA0–2 Bank Select Output – EBI_SDWE DDR2/SDRAM Write Enable Output Low EBI_RAS - EBI_CAS Row and Column Signal Output Low EBI_SDA10 SDRAM Address 10 Line Output – The connection of some signals through the MUX logic is not direct and depends on the memory controller currently in use. Table 26-2 details the connections between the two Memory Controllers and the EBI pins. Table 26-2: EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins SDRAM I/O Lines EBI_NWR1/NBS1/CFIOR NBS1 SMC I/O Lines NWR1 EBI_A0/NBS0 Not Supported SMC_A0 EBI_A1/NBS2/NWR2 Not Supported SMC_A1 EBI_A[11:2] SDRAMC_A[9:0] SMC_A[11:2] EBI_SDA10 SDRAMC_A10 Not Supported EBI_A12 Not Supported SMC_A12 EBI_A[14:13] SDRAMC_A[12:11] SMC_A[14:13] EBI_A[25:15] Not Supported SMC_A[25:15] EBI_D[31:0] D[31:0] D[31:0]  2017 Microchip Technology Inc. DS60001517A-page 319 SAM9N12/SAM9CN11/SAM9CN12 26.5 Application Example 26.5.1 Hardware Interface Table 26-3 details the connections to be applied between the EBI pins and the external devices for each memory controller. Table 26-3: EBI Pins and External Static Device Connections Pins of the SMC Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D0–D7 D8–D15 – D8–D15 D8–D15 D8–D15 D8–15 D8–15 D16–D24 – – – D16–D23 D16–D23 D16–D23 D25–D31(5)) – – – D24–D31 D24–D31 D24–D31 Signals: EBI_ A0/NBS0 A0 A1/NWR2/NBS2/DQM2 – NLB (3) BE0 WE NLB(4) BE2 – NLB (2) A1 A0 A0 A[2:22] A[1:21] A[1:21] A[0:20] A[0:20] A[0:20] A[23:25] A[22:24] A[22:24] A[21:23] A[21:23] A[21:23] NCS0 CS CS CS CS CS CS NCS1/DDRSDCS CS CS CS CS CS CS NCS2(5) CS CS CS CS CS CS NCS3/NANDCS CS CS CS CS CS CS NCS4(5) CS CS CS CS CS CS (5) NCS5 CS CS CS CS CS CS NRD OE OE OE OE OE OE NWR0/NWE WE WE(1) WE WE(2) WE WE NUB WE(2) NUB(3) BE1 (2) NUB(4) BE3 A2–A22(5) A23–A25 (5) NWR1/NBS1 NWR3/NBS3/DQM3 – – (1) WE – – WE Note 1: NWR1 enables upper byte writes. NWR0 enables lower byte writes. 2: NWRx enables corresponding byte x writes. (x = 0, 1, 2 or 3). 3: NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4: NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. 5: D25–D31 and A20, A23-A25, NCS2, NCS4, NCS5 are multiplexed on PD15–PD31. DS60001517A-page 320  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 26-4: EBI Pins and External Device Connections Pins of the Interfaced Device DDRSDRC Signals: EBI_ Power supply D0–D15 SMC DDR2/LPDDR SDR/LPSDR NAND Flash VDDIOM D0–D15 D0–D15 NFD0–NFD15(1) D16–D31 VDDNF – D16–D31 NFD0–NFD15(1) A0/NBS0 VDDIOM – – – A1/NWR2/NBS2/DQM2 VDDIOM – DQM2 – DQM0–DQM1 VDDIOM DQM0–DQM1 DQM0–DQM1 – DQS0–DQS1 VDDIOM DQS0–DQS1 – – A2–A10 VDDIOM A[0:8] A[0:8] – A11 VDDIOM A9 A9 – SDA10 VDDIOM A10 A10 – A12 VDDIOM – – – A13–A14 VDDIOM A[11:12] A[11:12] – A15 VDDIOM A13 – – A16/BA0 VDDIOM BA0 BA0 – A17/BA1 VDDIOM BA1 BA1 – A18/BA2 VDDIOM BA2 BA2 – A19 VDDIOM – – – A20 VDDIOM – – – A21/NANDALE VDDNF – – ALE A22/NANDCLE VDDNF – – CLE A23–A24 VDDIOM – – – A25 VDDIOM – – – NCS0 VDDIOM – – – NCS1/DDRSDCS VDDIOM DDRCS SDCS – NCS2 VDDIOM – – – NCS3/NANDCS VDDNF – – CE NCS4 VDDIOM – – – NCS5 VDDIOM – – – NANDOE VDDNF – – OE NANDWE VDDNF – – WE NRD VDDIOM – – – NWR0/NWE VDDIOM – – – NWR1/NBS1 VDDIOM – – – NWR3/NBS3/DQM3 VDDIOM – DQM3 –  2017 Microchip Technology Inc. DS60001517A-page 321 SAM9N12/SAM9CN11/SAM9CN12 Table 26-4: EBI Pins and External Device Connections (Continued) Pins of the Interfaced Device DDRSDRC Signals: EBI_ Power supply SDCK SMC DDR2/LPDDR SDR/LPSDR NAND Flash VDDIOM CK CK – SDCK# VDDIOM CK# – – SDCKE VDDIOM CKE CKE – RAS VDDIOM RAS RAS – CAS VDDIOM CAS CAS – SDWE VDDIOM WE WE – Pxx VDDNF – – CE Pxx VDDNF – – RDY Note 1: A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0–D7 or D16–D24 depending on memory power supplies. This switch is located in the EBI Chip Select Assignment Register (CCFG_EBICSA) in the Bus Matrix user interface. 26.5.2 Connection Examples Figure 26-2 shows an example of connections between the EBI and external devices. Figure 26-2: EBI Connections to Memory Devices EBI D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE D0-D7 2M x 8 SDRAM D8-D15 D0-D7 CS CLK CKE SDWE WE RAS CAS DQM NBS0 A0-A9, A11 A10 BA0 BA1 2M x 8 SDRAM D0-D7 CS CLK CKE SDWE WE RAS CAS DQM NBS1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25 D16-D23 D0-D7 NCS0 NCS1/SDCS NCS2 NCS3 NCS4 NCS5 CS CLK CKE SDWE WE RAS CAS DQM 2M x 8 SDRAM A0-A9, A11 A10 BA0 BA1 D24-D31 2M x 8 SDRAM D0-D7 CS CLK CKE SDWE WE RAS CAS DQM NBS3 A2-A11, A13 SDA10 A16/BA0 A17/BA1 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 NBS2 128K x 8 SRAM D0-D7 D0-D7 CS OE NRD/NOE WE A0/NWR0/NBS0 DS60001517A-page 322 A0-A16 128K x 8 SRAM A1-A17 D8-D15 D0-D7 A0-A16 A1-A17 CS OE NRD/NOE WE NWR1/NBS1  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26.6 26.6.1 Product Dependencies I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 26.7 Functional Description The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: • • • • • • the Static Memory Controller (SMC) the DDR2/SDRAM Controller (DDR2SDRC) the Programmable Multibit Error Correction Code Controller (PMECC) a chip select assignment feature that assigns an AHB address space to the external devices a multiplex controller circuit that shares the pins between the different Memory Controllers programmable NAND Flash support logic 26.7.1 Bus Multiplexing The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the memory controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed independently by the DDR2SDR Controller without delaying the other external memory controller accesses. 26.7.2 Pull-up Control The EBI Chip Select Assignment Register (CCFG_EBICSA) in the Chip Configuration User Interface permits enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the EBIx_DBPUC bit disables the pull-up resistors on the lines D0–D15. Enabling the pull-up resistor on the lines D16–D31 can be performed by programming the appropriate PIO controller. 26.7.3 Drive level The EBI I/Os accept two drive level, HIGH and LOW. This allows to avoid overshoots and give the best performances according to the bus load and external memories. The voltage ranges and the slew rates are determined by programming the EBI_DRIVE field in the CCFG_EBICSA register. At reset the selected current drive is HIGH. 26.7.4 Power Supplies The product embeds a dual power supply for EBI, VDDNF for NAND Flash signals, and VDDIOM for others. This allows to use an 1.8V or 3.3V NAND Flash independently of SDRAM power supply. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D15 or D16-D32 depending on memory power supplies. This switch is located in the CCFG_EBICSA register. In the following example the NAND Flash and the external RAM (DDR2 or LPDDR or 16-bit LPSDR) are in the same power supply range, (NFD0_ON_D16 = 0).  2017 Microchip Technology Inc. DS60001517A-page 323 SAM9N12/SAM9CN11/SAM9CN12 Figure 26-3: NAND Flash and the external RAM power supply (NFD0_ON_D16 = 0) DDR2 or LPDDR or 16-bit LPSDR (1.8V) D[15:0] D[15:0] NAND Flash (1.8V) D[15:0] A[22:21] ALE CLE EBI 32bit SDRAM (3.3V) D[15:0] D[31:16] D[15:0] D[31:16] NAND Flash (3.3V) D[15:0] A[22:21] ALE CLE EBI In the following example the NAND Flash and the external RAM (DDR2 or LPDDR or 16-bit LPSDR) are NOT in the same power supply range (NFD0_ON_D16 = 1). This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC will lead to an unpredictable behavior of that device. In that case, the default value must be selected. Figure 26-4: NAND Flash and the external RAM power supply (NFD0_ON_D16 = 1) DDR2 or LPDDR or 16-bit LPSDR (1.8V) D[15:0] D[15:0] NAND Flash (3.3V) D[31:16] A[22:21] EBI D[15:0] ALE CLE At reset NFD0_ON_D16 = 1 and NAND Flash bus is connected to D16–D31. 26.7.5 Static Memory Controller For information on the Static Memory Controller, refer to Section 29. “Static Memory Controller (SMC)”. 26.7.6 DDR2SDRAM Controller For information on the DDR2SDR Controller, refer to Section 30. “DDR SDR SDRAM Controller (DDRSDRC)”. DS60001517A-page 324  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26.7.7 Programmable Multi-bit ECC Controller For information on the PMECC Controller, refer to Section 27. “Programmable Multibit Error Correction Code Controller (PMECC)”. 26.7.8 NAND Flash Support External Bus Interfaces 1 integrate circuitry that interfaces to NAND Flash devices. 26.7.8.1 External Bus Interface The NAND Flash logic is driven by the SMC on the NCS3 address space. Programming the EBI_CS3A field in the CCFG_EBICSA register in the Chip Configuration User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to Section 25. “Bus Matrix (MATRIX)”. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF). The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure 26-5 for more information. For details on these waveforms, refer to Section 29. “Static Memory Controller (SMC)”. 26.7.8.2 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 26-5: NAND Flash Application Example D[7:0] AD[7:0] A[22:21] ALE CLE NCSx/NANDCS Not Connected EBI NAND Flash NANDOE NANDWE  2017 Microchip Technology Inc. NOE NWE PIO CE PIO R/B DS60001517A-page 325 SAM9N12/SAM9CN11/SAM9CN12 26.8 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 26.8.1 26.8.1.1 2x8-bit DDR2 on EBI Hardware Configuration Figure 26-6: 26.8.1.2 2x8-bit DDR2 on EBI Configuration Software Configuration • Assign EBI_CS1 to the DDR2 controller by setting the EBI_CS1A bit in the EBI Chip Select Assignment Register. • Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency. The DDR2 initialization sequence is described in Section 30.4.3 “DDR2-SDRAM Initialization”. In this case VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data bus. NFD0_ON_D16 is to be set to 1. DS60001517A-page 326  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26.8.2 26.8.2.1 16-bit LPDDR on EBI Hardware Configuration Figure 26-7: 26.8.2.2 16-bit LPDDR on EBI Configuration Software Configuration The following configuration has to be performed: • Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register. • Initialize the DDR2 Controller depending on the LPDDR device and system bus frequency. The LPDDR initialization sequence is described in Section 30.4.2 “Low-power DDR1-SDRAM Initialization”. In this case VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data bus. NFD0_ON_D16 is to be set to 1.  2017 Microchip Technology Inc. DS60001517A-page 327 SAM9N12/SAM9CN11/SAM9CN12 26.8.3 26.8.3.1 16-bit SDRAM Hardware Configuration Figure 26-8: 26.8.3.2 16-bit SDRAM Configuration Software Configuration The following configuration has to be performed: • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in Section 30.4.1 “SDR-SDRAM Initialization”. In this case VDDNF can be different from VDDIOM. The NAND Flash device can be 3.3V or 1.8V and wired on D16–D31 data bus. NFD0_ON_D16 is to be set to 1. DS60001517A-page 328  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26.8.4 2x16-bit SDRAM 26.8.4.1 Hardware Configuration Figure 26-9: 2x16-bit SDRAM Configuration A[1..14] D[0..31] SDRAM MN1 VDDIOM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 23 24 25 26 29 30 31 32 33 34 22 35 BA0 BA1 20 21 A14 36 40 CKE 37 CLK 38 DQM0 DQM1 15 39 CAS RAS 17 18 WE 16 19 R1 470K MN2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C1 VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VDDIOM C1 C3 C5 C7 100NF 100NF 100NF 100NF C2 C4 C6 100NF 100NF 100NF VDDIOM A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 23 24 25 26 29 30 31 32 33 34 22 35 BA0 BA1 20 21 A14 36 40 CKE 37 CLK 38 DQM2 DQM3 15 39 CAS RAS 17 18 WE 16 19 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C1 VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 VDDIOM C8 C10 C12 C14 100NF 100NF 100NF 100NF C9 C11 C13 100NF 100NF 100NF MT48LC16M16A2P-75IT SDCS R2 0R R3 470K 256 Mbits R4 26.8.4.2 256 Mbits 0R Software Configuration The following configuration has to be performed: • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register. • Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in Section 30.4.1 “SDR-SDRAM Initialization”. In this case, VDDNF must be equal to VDDIOM. The NAND Flash device must be 3.3V and wired on D0–D15 data bus. NFD0_ON_D16 must be set to 0.  2017 Microchip Technology Inc. DS60001517A-page 329 SAM9N12/SAM9CN11/SAM9CN12 26.8.5 26.8.5.1 8-bit NAND Flash with NFD0_ON_D16 = 0 Hardware Configuration Figure 26-10: 8-bit NAND Flash with NFD0_ON_D16 = 0 D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.C 48 47 46 45 40 39 38 35 34 33 28 27 VCC VCC 37 12 VSS VSS 36 13 2 Gb D0 D1 D2 D3 D4 D5 D6 D7 3V3 C2 100NF C1 100NF TSOP48 PACKAGE 26.8.5.2 Software Configuration The following configuration has to be performed: • Set NFD0_ON_D16 = 0 in the EBI Chip Select Assignment Register. • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register. • Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bits A21 and A22 during accesses. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. DS60001517A-page 330  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26.8.6 26.8.6.1 16-bit NAND Flash with NFD0_ON_D16 = 0 Hardware Configuration Figure 26-11: 16-bit NAND Flash with NFD0_ON_D16 = 0 D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 3V3 R1 10K R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.C 39 38 36 VCC VCC 37 12 VSS VSS VSS 48 25 13 2 Gb D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 C2 100NF C1 100NF TSOP48 PACKAGE 26.8.6.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the SMC Mode Register.  2017 Microchip Technology Inc. DS60001517A-page 331 SAM9N12/SAM9CN11/SAM9CN12 26.8.7 26.8.7.1 8-bit NAND Flash with NFD0_ON_D16 = 1 Hardware Configuration Figure 26-12: 26.8.7.2 8-bit NAND Flash with NFD0_ON_D16 = 1 Software Configuration The following configuration has to be performed: • • • • Set NFD0_ON_D16 = 1 in the EBI Chip Select Assignment Register. Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register. Configure the PIOD controller to assign the required PIOD[23..0] to EBI function. Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bit A21 and A22 during accesses. • Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. DS60001517A-page 332  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 26.8.8 26.8.8.1 16-bit NAND Flash with NFD0_ON_D16 = 1 Hardware Configuration Figure 26-13: 26.8.8.2 16-bit NAND Flash with NFD0_ON_D16 = 1 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the SMC Mode Register.  2017 Microchip Technology Inc. DS60001517A-page 333 SAM9N12/SAM9CN11/SAM9CN12 26.8.9 26.8.9.1 NOR Flash on NCS0 Hardware Configuration Figure 26-14: NOR Flash on NCS0 D[0..15] A[1..22] U1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 NRST NWE 3V3 NCS0 NRD 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 12 11 14 13 26 28 RESET WE WP VPP CE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AT49BV6416 3V3 VCCQ 47 VCC 37 VSS VSS 46 27 C2 100NF C1 100NF TSOP48 PACKAGE 26.8.9.2 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. DS60001517A-page 334  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 27. Programmable Multibit Error Correction Code Controller (PMECC) 27.1 Description The Programmable Multibit Error Correction Code Controller (PMECC) is a programmable binary BCH (Bose, Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both Single-Level Cell (SLC) and Multi-level Cell (MLC) NAND Flash devices. It supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data. 27.2 • • • • • • • • • • • Embedded Characteristics 8-bit Nand Flash Data Bus Support Multibit Error Correcting Code Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bit of errors per sector Programmable Sector Size: 512 bytes or 1024 bytes Programmable Number of Sectors per page: 1, 2, 4 or 8 sectors of data per page Programmable Spare Area Size Supports Spare Area ECC Protection Supports 8 Kbytes page size using 1024 bytes per sector and 4 Kbytes page size using 512 bytes per sector Configurable through APB interface Multibit Error Detection is Interrupt Driven 27.3 Block Diagram Figure 27-1: Block Diagram MLC/SLC NAND Flash device Static Memory Controller 8-bit Data Bus Control Bus PMECC Controller Programmable BCH Algorithm User Interface APB  2017 Microchip Technology Inc. DS60001517A-page 335 SAM9N12/SAM9CN11/SAM9CN12 27.4 Functional Description The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This operation is performed by the processor. It moves the content of the PMECCx registers into the NAND Flash memory. The number of registers depends on the selected error correction capability, refer to Table 27-1 “Relevant Redundancy Registers”. This operation is executed for each sector. At decoding time, the PMECC module generates the remainder of the received codeword by minimal polynomials. When all polynomial remainders for a given sector are set to zero, no error occurred. When the polynomial remainders are other than zero, the codeword is corrupted and further processing is required. The PMECC module generates an interrupt indicating that an error occurred. The processor must read the PMECC Interrupt Status Register (PMECC_ISR). This register indicates which sector is corrupted. To find the error location within a sector, the processor must execute the following decoding steps: 1. 2. 3. Syndrome computation Find the error locator polynomials Find the roots of the error locator polynomial All decoding steps involve finite field computation. It means that a library of finite field arithmetic must be available to perform addition, multiplication and inversion. The finite field arithmetic operations can be performed through the use of a memory mapped lookup table, or direct software implementation. The software implementation presented is based on lookup tables. Two tables named gf_log and gf_antilog are used. If alpha is the primitive element of the field, then a power of alpha is in the field. Assume beta = alpha ^ index, then beta belongs to the field, and gf_log(beta) = gf_log(alpha ^ index) = index. The gf_antilog tables provide exponent inverse of the element, if beta = alpha ^ index, then gf_antilog(index) = beta. The first step consists of the syndrome computation. The PMECC module computes the remainders and software must substitute the power of the primitive element. The procedure implementation is given in Section 27.5.1 “Remainder Substitution Procedure”. The second step is the most software intensive. It is the Berlekamp’s iterative algorithm for finding the error-location polynomial. The procedure implementation is given in Section 27.5.2 “Find the Error Location Polynomial Sigma(x)”. The Last step is finding the root of the error location polynomial. This step can be very software intensive. Indeed, there is no straightforward method of finding the roots, except by evaluating each element of the field in the error location polynomial. However a hardware accelerator can be used to find the roots of the polynomial. The Programmable Multibit Error Correction Code Location (PMERRLOC) module provides this kind of hardware acceleration. DS60001517A-page 336  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 27-2: Software/Hardware Multibit Error Correction Dataflow NAND Flash PROGRAM PAGE Operation Software NAND Flash READ PAGE Operation Hardware Accelerator Configure PMECC : error correction capability sector size/page size NAND write field set to true spare area desired layout Move the NAND Page to external Memory whether using DMA or Processor Software Hardware Accelerator Configure PMECC : error correction capability sector size/page size NAND write field set to false spare area desired layout PMECC computes redundancy as the data is written into external memory Move the NAND Page from external Memory whether using DMA or Processor PMECC computes polynomial remainders as the data is read from external memory PMECC modules indicate if at least one error is detected. Copy redundancy from PMECC user interface to user defined spare area. using DMA or Processor. If a sector is corrupted use the substitute() function to determine the syndromes. When the table of syndromes is completed, use the get_sigma() function to get the error location polynomial. Find the error positions finding the roots of the error location polynomial. And correct the bits.  2017 Microchip Technology Inc. This step can be hardware assisted using the PMERRLOC module. DS60001517A-page 337 SAM9N12/SAM9CN11/SAM9CN12 27.4.1 MLC/SLC Write Page Operation using PMECC When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR bit in the PMECC Configuration Register (PMECC_CFG) set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN in PMECC_CFG is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero. When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance. Table 27-1: Relevant Redundancy Registers BCH_ERR field Sector size set to 512 bytes Sector size set to 1024 bytes 0 PMECC_ECC0 PMECC_ECC0 1 PMECC_ECC0, PMECC_ECC1 PMECC_ECC0, PMECC_ECC1 2 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3 3 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6 4 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6, PMECC_ECC7, PMECC_ECC8, PMECC_ECC9 PMECC_ECC0, PMECC_ECC1, PMECC_ECC2, PMECC_ECC3, PMECC_ECC4, PMECC_ECC5, PMECC_ECC6, PMECC_ECC7, PMECC_ECC8, PMECC_ECC9, PMECC_ECC10 Table 27-2: Number of relevant ECC bytes per sector, copied from LSbyte to MSbyte BCH_ERR field 27.4.1.1 Sector size set to 512 bytes Sector size set to 1024 bytes 0 4 bytes 4 bytes 1 7 bytes 7 bytes 2 13 bytes 14 bytes 3 20 bytes 21 bytes 4 39 bytes 42 bytes SLC/MLC Write Operation with Spare Enable Bit Set When the SPAREEN bit in PMECC_CFG is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing one in the DATA bit in the PMECC Control Register (PMECC_CTRL). When the encoding process is over, the redundancy is written to the spare area in user mode, USER bit in PMECC_CTRL must be set to one. DS60001517A-page 338  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 27-3: NAND Write Operation with Spare Encoding Write NAND operation with SPAREEN set to one pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 sparesize Sector 3 Spare 512 or 1024 bytes ecc_area start_addr end_addr ECC computation enable signal 27.4.1.2 MLC/SLC Write Operation with Spare Area Disabled When the SPAREEN bit in PMECC_CFG is set to zero the spare area is not encoded with the stream of data. This mode is entered by writing one to the DATA bit in PMECC_CTRL. Figure 27-4: NAND Write Operation Write NAND operation with SPAREEN set to zero pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 Sector 3 512 or 1024 bytes ECC computation enable signal  2017 Microchip Technology Inc. DS60001517A-page 339 SAM9N12/SAM9CN11/SAM9CN12 27.4.2 MLC/SLC Read Page Operation using PMECC Table 27-3: Relevant Remainders Registers BCH_ERR field 27.4.2.1 Sector size set to 512 bytes Sector size set to 1024 bytes 0 PMECC_REM0 PMECC_REM0 1 PMECC_REM0, PMECC_REM1 PMECC_REM0, PMECC_REM1 2 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3 3 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7 4 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7, PMECC_REM8, PMECC_REM9, PMECC_REM10, PMECC_REM11 PMECC_REM0, PMECC_REM1, PMECC_REM2, PMECC_REM3, PMECC_REM4, PMECC_REM5, PMECC_REM6, PMECC_REM7, PMECC_REM8, PMECC_REM9, PMECC_REM10, PMECC_REM11 MLC/SLC Read Operation with Spare Decoding When the spare area is protected, the spare area contains valid data. As the redundancy may be included in the middle of the information stream, the user programs the start address and the end address of the ECC area. The controller will automatically skip the ECC area. This mode is entered by writing one in the DATA bit in PMECC_CTRL. When the page has been fully retrieved from NAND, the ECC area is read using the user mode by writing one to the USER bit in PMECC_CTRL. Figure 27-5: Read Operation with Spare Decoding Read NAND operation with SPAREEN set to One and AUTO set to Zero pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 sparesize Sector 3 Spare 512 or 1024 bytes ecc_area start_addr end_addr Remainder computation enable signal 27.4.2.2 MLC/SLC Read Operation If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered by writing one in the DATA bit in PMECC_CTRL. When the AUTO bit in PMECC_CFG is set to one the ECC is retrieved automatically, otherwise the ECC must be read using user mode. DS60001517A-page 340  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 27-6: Read Operation Read NAND operation with SPAREEN set to Zero and AUTO set to One pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 sparesize Sector 3 Spare 512 or 1024 bytes ecc_area ECC_SEC2 ECC_SEC1 ECC_SEC0 ECC_SEC3 end_addr start_addr Remainder computation enable signal 27.4.2.3 MLC/SLC User Read ECC Area This mode allows a manual retrieve of the ECC. This mode is entered writing one in the USER bit in PMECC_CTRL. Figure 27-7: User Read Mode ecc_area_size ECC ecc_area addr = 0 end_addr Partial Syndrome computation enable signal 27.5 27.5.1 Software Implementation Remainder Substitution Procedure The substitute function evaluates the polynomial remainder, with different values of the field primitive elements. The finite field arithmetic addition operation is performed with the Exclusive or. The finite field arithmetic multiplication operation is performed through the gf_log, gf_antilog lookup tables. The REM2NP1 and REMN2NP3 fields of the PMECC Remainder x registers (PMECC_REMx) contain only odd remainders. Each bit indicates whether the coefficient of the polynomial remainder is set to zero or not.  2017 Microchip Technology Inc. DS60001517A-page 341 SAM9N12/SAM9CN11/SAM9CN12 NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. si[] is a table that holds the current syndrome value, an element of that table belongs to the field. This is also a shared variable for the next step of the decoding operation. oo[] is a table that contains the degree of the remainders. int { int int for { substitute() i; j; (i = 1; i < 2 * NB_ERROR_MAX; i++) si[i] = 0; } for (i = 1; i < 2*NB_ERROR; i++) { for (j = 0; j < oo[i]; j++) { if (REM2NPX[i][j]) { si[i] = gf_antilog[(i * j)%NB_FIELD_ELEMENTS] ^ si[i]; } } } return 0; } DS60001517A-page 342  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 27.5.2 Find the Error Location Polynomial Sigma(x) The sample code below gives a Berlekamp iterative procedure for finding the value of the error location polynomial. The input of the procedure is the si[] table defined in the remainder substitution procedure. The output of the procedure is the error location polynomial named smu (sigma mu). The polynomial coefficients belong to the field. The smu[NB_ERROR+1][] is a table that contains all these coefficients. NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. int get_sigma() { int i; int j; int k; /* mu */ int mu[NB_ERROR_MAX+2]; /* sigma ro */ int sro[2*NB_ERROR_MAX+1]; /* discrepancy */ int dmu[NB_ERROR_MAX+2]; /* delta order */ int delta[NB_ERROR_MAX+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* First Row */ /* */ /* Mu */ mu[0] = -1; /* Actually -1/2 */ /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ delta[0] = (mu[0] * 2 - lmu[0]) >> 1; /* */ /* Second Row */ /* */ /* Mu */ mu[1] = 0; /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[1][i] = 0; smu[1][0] = 1; /* discrepancy set to Syndrome 1 */ dmu[1] = si[1]; /* polynom order set to 0 */ lmu[1] = 0; /* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i UDP_CSR[ep]; \ reg |= UDP_REG_NO_EFFECT_1_ALL; reg |= (bits); \ \ UDP->UDP_CSR[ep] = reg; \ for (nop_count = 0; nop_count < 20; nop_count ++) {\ __NOP(); } \ \ } while (0)  2017 Microchip Technology Inc. DS60001517A-page 537 SAM9N12/SAM9CN11/SAM9CN12 /*! Clears specified bit(s) in the UDP_CSR. * \param ep Endpoint number. * \param bits Bitmap to set to 0. */ #define udp_clear_csr(ep, bits) \ do { \ volatile uint32_t reg; \ volatile uint32_t nop_count; \ reg = UDP->UDP_CSR[ep]; \ reg |= UDP_REG_NO_EFFECT_1_ALL; reg &= ~(bits); \ \ UDP->UDP_CSR[ep] = reg; \ for (nop_count = 0; nop_count < 20; nop_count ++) {\ __NOP(); } \ \ } while (0) In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. However, RX_DATA_BK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 5 peripheral clock cycles before accessing DPR. TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (cleared by the firmware): 0: Clear the flag, clear the interrupt 1: No effect Read (Set by the USB peripheral): 0: Data IN transaction has not been acknowledged by the Host 1: Data IN transaction is achieved, acknowledged by the Host After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (cleared by the firmware): 0: Notify USB peripheral device that data have been read in the FIFO’s Bank 0. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO’s Bank 0. 1: A data packet has been received, it has been stored in the FIFO’s Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_FDRx. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. DS60001517A-page 538  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0: No setup packet available. 1: A setup data packet has been sent by the host and is available in the FIFO. Write: 0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1: No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. STALLSENT: Stall Sent This flag generates an interrupt while it is set to one. This ends a STALL handshake. Read: 0: Host has not acknowledged a stall 1: Host has acknowledged the stall Write: 0: Resets the STALLSENT flag, clears the interrupt 1: No effect This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0: There is no data to send. 1: The data is waiting to be sent upon reception of token IN. Write: 0: Can be used in the procedure to cancel transmission data. (See Section 32.6.2.5 ”Transmit Data Cancellation”) 1: A new data payload has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0: Normal state 1: Stall state Write: 0: Return to normal state 1: Send STALL to the host  2017 Microchip Technology Inc. DS60001517A-page 539 SAM9N12/SAM9CN11/SAM9CN12 Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (cleared by the firmware): 0: Notifies USB device that data have been read in the FIFO’s Bank 1. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO’s Bank 1. 1: A data packet has been received, it has been stored in FIFO’s Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. DIR: Transfer Direction (only available for control endpoints) (Read/Write) 0: Allows Data OUT transactions in the control data stage. 1: Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. EPTYPE: Endpoint Type (Read/Write) Value Name Description 0 CTRL Control 1 ISO_OUT Isochronous OUT 2 BULK_OUT Bulk OUT 3 INT_OUT Interrupt OUT 4 – Reserved 5 ISO_IN Isochronous IN 6 BULK_IN Bulk IN 7 INT_IN Interrupt IN DTGLE: Data Toggle (Read-only) 0: Identifies DATA0 packet 1: Identifies DATA1 packet Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. DS60001517A-page 540  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 EPEDS: Endpoint Enable Disable Read: 0: Endpoint disabled 1: Endpoint enabled Write: 0: Disables endpoint 1: Enables endpoint Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). RXBYTECNT: Number of Bytes Available in the FIFO (Read-only) When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx.  2017 Microchip Technology Inc. DS60001517A-page 541 SAM9N12/SAM9CN11/SAM9CN12 32.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS) Name:UDP_CSRx [x = 0..5] (ISOCHRONOUS) Address:0xF803C030 Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 25 RXBYTECNT 24 19 18 17 16 RXBYTECNT 15 EPEDS 14 – 13 – 12 – 11 DTGLE 10 9 EPTYPE 8 7 6 5 4 3 2 0 TXPKTRDY ISOERROR RXSETUP 1 RX_DATA_ BK0 DIR RX_DATA_BK1 FORCESTALL TXCOMP TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (cleared by the firmware): 0: Clear the flag, clear the interrupt. 1: No effect. Read (Set by the USB peripheral): 0: Data IN transaction has not been acknowledged by the Host. 1: Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (cleared by the firmware): 0: Notify USB peripheral device that data have been read in the FIFO’s Bank 0. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO’s Bank 0. 1: A data packet has been received, it has been stored in the FIFO’s Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_FDRx. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0: No setup packet available. 1: A setup data packet has been sent by the host and is available in the FIFO. DS60001517A-page 542  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Write: 0: Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1: No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. ISOERROR: A CRC error has been detected in an isochronous transfer This flag generates an interrupt while it is set to one. Read: 0: No error in the previous isochronous transfer. 1: CRC error has been detected, data available in the FIFO are corrupted. Write: 0: Resets the ISOERROR flag, clears the interrupt. 1: No effect. TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0: There is no data to send. 1: The data is waiting to be sent upon reception of token IN. Write: 0: Can be used in the procedure to cancel transmission data. (See Section 32.6.2.5 ”Transmit Data Cancellation”) 1: A new data payload has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0: Normal state. 1: Stall state. Write: 0: Return to normal state. 1: Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.  2017 Microchip Technology Inc. DS60001517A-page 543 SAM9N12/SAM9CN11/SAM9CN12 RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (cleared by the firmware): 0: Notifies USB device that data have been read in the FIFO’s Bank 1. 1: To leave the read value unchanged. Read (set by the USB peripheral): 0: No data packet has been received in the FIFO’s Bank 1. 1: A data packet has been received, it has been stored in FIFO’s Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. DIR: Transfer Direction (only available for control endpoints) (Read/Write) 0: Allows Data OUT transactions in the control data stage. 1: Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. EPTYPE: Endpoint Type (Read/Write) Value Name Description 0 CTRL Control 1 ISO_OUT Isochronous OUT 2 BULK_OUT Bulk OUT 3 INT_OUT Interrupt OUT 4 – Reserved 5 ISO_IN Isochronous IN 6 BULK_IN Bulk IN 7 INT_IN Interrupt IN DTGLE: Data Toggle (Read-only) 0: Identifies DATA0 packet 1: Identifies DATA1 packet Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. EPEDS: Endpoint Enable Disable Read: 0: Endpoint disabled 1: Endpoint enabled Write: 0: Disables endpoint 1: Enables endpoint Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). DS60001517A-page 544  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 RXBYTECNT: Number of Bytes Available in the FIFO (Read-only) When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx.  2017 Microchip Technology Inc. DS60001517A-page 545 SAM9N12/SAM9CN11/SAM9CN12 32.7.12 UDP FIFO Data Register Name:UDP_FDRx [x = 0..5] Address:0xF803C050 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA FIFO_DATA: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. DS60001517A-page 546  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 32.7.13 UDP Transceiver Control Register Name:UDP_TXVC Address:0xF803C074 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 PUON TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the PMC must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register. TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS bit. To enable the transceiver, TXVDIS must be cleared. PUON: Pull-up On 0: The 1.5KΩ integrated pull-up on DDP is disconnected. 1: The 1.5 KΩ integrated pull-up on DDP is connected. NOTE: If the USB pull-up is not connected on DDP, the user should not write in any UDP register other than the UDP_TXVC register. This is because if DDP and DDM are floating at 0, or pulled down, then SE0 is received by the device with the consequence of a USB Reset.  2017 Microchip Technology Inc. DS60001517A-page 547 SAM9N12/SAM9CN11/SAM9CN12 33. USB Host Port (UHP) 33.1 Description The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology. The USB Host Port controller is fully compliant with the OpenHCI specification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification le on www.hp.com. The standard OHCI USB stack driver can be easily ported to Microchip’s architecture in the same way all existing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses. 33.2 • • • • • • Embedded Characteristics Compliant with OpenHCI Rev 1.0 Specification Compliant with USB V2.0 Full-speed and Low-speed Specification Supports Both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices Root Hub Integrated with 1 Downstream USB Ports Embedded USB Transceivers Supports Power Management 33.3 Block Diagram Figure 33-1: Block Diagram HCI Slave Block AHB Slave OHCI Registers Control ED & TD Regsisters AHB HCI Master Block OHCI Root Hub Registers List Processor Block Root Hub and Host SIE Embedded USB v2.0 Full-speed Transceiver PORT S/M USB transceiver DP DM PORT S/M USB transceiver DP DM Data FIFO 64 x 8 Master uhp_int MCK UHPCK Access to the USB host operational registers is achieved through the AHB bus slave interface. The OpenHCI host controller initializes master DMA transfers through the ASB bus master interface as follows: • • • • Fetches endpoint descriptors and transfer descriptors Access to endpoint data from system memory Access to the HC communication area Write status and retire transfer Descriptor DS60001517A-page 548  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Memory access errors (abort, misalignment) lead to an “UnrecoverableError” indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller. Microchip’s standard product does not dedicate pads to external over current protection. 33.4 33.4.1 Product Dependencies I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller. 33.4.2 Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%. Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain). 33.4.3 Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling USB host interrupts requires programming the AIC before configuring the UHP. 33.5 Functional Description Refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 33.5.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers. They are mapped in the memory mapped area. Within the operational register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second communication channel. The host controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue and status information associated with start-of-frame processing. The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint.  2017 Microchip Technology Inc. DS60001517A-page 549 SAM9N12/SAM9CN11/SAM9CN12 Figure 33-2: USB Host Communication Device Enumeration Open HCI Operational Registers Host Controller Communications Area Mode Interrupt 0 HCCA Interrupt 1 Status Interrupt 2 ... Event Interrupt 31 Frame Int ... Ratio Control Bulk ... Done Device Register in Memory Space Shared RAM = Transfer Descriptor 33.5.2 = Endpoint Descriptor Host Controller Driver Figure 33-3: USB Host Drivers User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver HUB Driver USB Driver Host Controller Driver Hardware Host Controller Hardware USB Handling is done through several layers as follows: • • • • • Host controller hardware and serial engine: Transmits and receives USB data on the bus. Host controller driver: Drives the Host controller hardware and handles the USB protocol. USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent interface. Mini driver: Handles device specific commands. Class driver: Handles standard devices. This acts as a generic driver for a class of devices, for example the HID driver. DS60001517A-page 550  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 33.6 Typical Connection Figure 33-4: Board Schematic to Interface UHP Device Controller 5V 0.20A Type A Connector 10μF HDMA or HDMB HDPA or HDPB 100nF 10nF REXT REXT A termination serial resistor must be connected to HDP and HDM. The resistor value is defined in the electrical specification of the product (REXT).  2017 Microchip Technology Inc. DS60001517A-page 551 SAM9N12/SAM9CN11/SAM9CN12 34. High Speed Multimedia Card Interface (HSMCI) 34.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1. The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The HSMCI supports stream, block and multi block data read and write, and is compatible with the DMA Controller (DMAC), minimizing processor intervention for large buffer transfers. The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences between SD and High Speed MultiMedia Cards are the initialization process and the bus topology. HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable. 34.2 • • • • • • • • • • • • • • Embedded Characteristics Compatible with MultiMedia Card Specification Version 4.3 Compatible with SD Memory Card Specification Version 2.0 Compatible with SDIO Specification Version 2.0 Compatible with CE-ATA Specification 1.1 Cards Clock Rate Up to Master Clock Divided by 2 Boot Operation Mode Support High Speed Mode Support Embedded Power Management to Slow Down Clock Rate When Not Used Supports 1 Multiplexed Slot(s) - Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card Support for Stream, Block and Multi-block Data Read and Write Supports Connection to DMA Controller (DMAC) - Minimizes Processor Intervention for Large Buffer Transfers Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access Support for CE-ATA Completion Signal Disable Command Protection Against Unexpected Modification On-the-Fly of the Configuration Registers DS60001517A-page 552  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 34.3 Block Diagram Figure 34-1: Block Diagram (8-bit configuration) APB Bridge DMAC APB MCCK (1) MCCDA HSMCI Interface PMC MCK (1) MCDA0 (1) PIO MCDA1 (1) MCDA2 (1) MCDA3 (1) MCDA4 (1) MCDA5 (1) Interrupt Control MCDA6 (1) MCDA7 (1) HSMCI Interrupt Note 1: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy.  2017 Microchip Technology Inc. DS60001517A-page 553 SAM9N12/SAM9CN11/SAM9CN12 34.4 Application Block Diagram Figure 34-2: Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 10 11 1213 8 MMC 34.5 SDCard Pin Name List Table 34-1: I/O Lines Description for 8-bit Configuration Pin Name(1) Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA7 Data 0..7 of Slot A I/O/PP DAT[0..7] of an MMC DAT[0..3] of an SD Card/SDIO Note 1: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCCDB to HSMCIx_CDB, MCCDC to HSMCIx_CDC, MCCDD to HSMCIx_CDD, MCDAy to HSMCIx_DAy, MCDBy to HSMCIx_DBy, MCDCy to HSMCIx_DCy, MCDDy to HSMCIx_DDy. 2: I: Input, O: Output, PP: Push/Pull, OD: Open Drain. DS60001517A-page 554  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 34.6 Product Dependencies 34.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 34-2: I/O Lines Instance Signal I/O Line Peripheral HSMCI MCCDA PA16 A HSMCI MCCK PA17 A HSMCI MCDA0 PA15 A HSMCI MCDA1 PA18 A HSMCI MCDA2 PA19 A HSMCI MCDA3 PA20 A HSMCI MCDA4 PA11 B HSMCI MCDA5 PA12 B HSMCI MCDA6 PA13 B HSMCI MCDA7 PA14 B 34.6.2 Power Management The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the HSMCI clock. 34.6.3 Interrupt Sources The HSMCI has an interrupt line connected to the interrupt controller. Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI. Table 34-3: 34.7 Peripheral IDs Instance ID HSMCI 12 Bus Topology Figure 34-3: High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 10 11 1213 8 MMC  2017 Microchip Technology Inc. DS60001517A-page 555 SAM9N12/SAM9CN11/SAM9CN12 The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 34-4: Bus Topology Pin Number Name Type(1) Description HSMCI Pin Name(2) (Slot z) 1 DAT[3] I/O/PP Data MCDz3 2 CMD I/O/PP/OD Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data 0 MCDz0 8 DAT[1] I/O/PP Data 1 MCDz1 9 DAT[2] I/O/PP Data 2 MCDz2 10 DAT[4] I/O/PP Data 4 MCDz4 11 DAT[5] I/O/PP Data 5 MCDz5 12 DAT[6] I/O/PP Data 6 MCDz6 13 DAT[7] I/O/PP Data 7 MCDz7 Note 1: I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. Figure 34-4: MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 10 11 9 10 11 9 10 11 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. DS60001517A-page 556  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 34-5: SD Memory Card Bus Topology 1 2 3 4 56 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 34-5. Table 34-5: SD Memory Card Bus Signals Description HSMCI Pin Name(2) (Slot z) Pin Number Name Type(1) 1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 MCDz3 2 CMD PP Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data line Bit 0 MCDz0 8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1 9 DAT[2] I/O/PP Data line Bit 2 MCDz2 Note 1: I: input, O: output, PP: Push Pull, OD: Open Drain. 2: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 34-6: Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 34.8 High Speed MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command—A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. • Response—A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.  2017 Microchip Technology Inc. DS60001517A-page 557 SAM9N12/SAM9CN11/SAM9CN12 • Data—Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System Specification. See also Table 34-6. High Speed MultiMedia Card bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock HSMCI clock. Two types of data transfer commands are defined: • Sequential commands—These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands—These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a predefined block count (see Section 34.8.2 “Data Transfer Operation”). The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations. 34.8.1 Command - Response Operation After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR. The PWSEN bit saves power by dividing the HSMCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command Register (HSMCI_CMDR). The HSMCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: NID Cycles Host Command CMD S T Content CRC E Z ****** Response Z S T CID Content High Impedance State Z Z Z The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 34-6 and Table 34-7. Table 34-6: CMD Index CMD2 ALL_SEND_CID Command Description Type bcr(1 ) Argument Response Abbreviation Command Description [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note 1: bcr means broadcast command with response. DS60001517A-page 558  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 34-7: Fields and Values for HSMCI_CMDR Field Value CMDNB (command number) 2 (CMD2) RSPTYP (response type) 2 (R2: 136 bits response) SPCMD (special command) 0 (not a special command) OPCMD (open drain command) 1 MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles) TRCMD (transfer command) 0 (No transfer) TRDIR (transfer direction) X (available only in transfer command) TRTYP (transfer type) X (available only in transfer command) IOSPCMD (SDIO special command) 0 (not a special command) The HSMCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (HSMCI_ARGR) with the command argument. • Set the command register (HSMCI_CMDR) (see Table 34-7). The command is sent immediately after writing the command register. While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a new command shall not be sent. The NOTBUSY flag in the Status Register (HSMCI_SR) is asserted when the card releases the busy indication. If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the HSMCI Interrupt Enable Register (HSMCI_IER) allows using an interrupt method.  2017 Microchip Technology Inc. DS60001517A-page 559 SAM9N12/SAM9CN11/SAM9CN12 Figure 34-7: Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? RETURN ERROR(1) Read response if required Does the command involve a busy indication? No RETURN OK Read HSMCI_SR 0 NOTBUSY 1 RETURN OK Note: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed MultiMedia Card specification). DS60001517A-page 560  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 34.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the DMA Controller. In all cases, the block length (BLKLEN field) must be defined either in the HSMCI Mode Register (HSMCI_MR) or in the HSMCI Block Register (HSMCI_BLKR). This field determines the size of the data block. Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with predefined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with predefined block count, the host must correctly program the HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the HSMCI_BLKR defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 34.8.3 Read Operation The following flowchart (Figure 34-8) shows how to read a single block with or without use of DMAC facilities. In this example, a polling method is used to wait for the end of read. Similarly, the user can configure the HSMCI Interrupt Enable Register (HSMCI_IER) to trigger an interrupt at the end of read.  2017 Microchip Technology Inc. DS60001517A-page 561 SAM9N12/SAM9CN11/SAM9CN12 Figure 34-8: Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) No Yes Read with DMAC Reset the DMAEN bit HSMCI_DMA &= ~DMAEN Set the block length (in bytes) HSMCI_BLKR l= (BlockLength RXD MISO SPI Master -> RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS  2017 Microchip Technology Inc. DS60001517A-page 765 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-38: SPI Transfer Format (CPHA = 0, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 5 7 6 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 39.6.7.4 Receiver and Transmitter Control See Section 39.6.2 ”Receiver and Transmitter Control” 39.6.7.5 Character Transmission The characters are sent by writing in the Transmit Holding register (US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI Master mode. In the USART Mode Register (SPI_MODE) (USART_MR), the value configured on the bit WRDBT can prevent any character transmission (even if US_THR has been written) while the receiver side is not ready (character not read). When WRDBT equals 0, the character is transmitted whatever the receiver status. If WRDBT is set to 1, the transmitter waits for the Receive Holding register (US_RHR) to be read before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side. The chip select line is de-asserted for a period equivalent to three bits between the transmission of two data. The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave mode and if a character must be sent while the US_THR is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in US_CR. In SPI Master mode, the slave select line (NSS) is asserted at low level one tbit (tbit being the nominal time required to transmit a bit) before the transmission of the MSB bit and released at high level one tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of three tbit always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing a 1 to the RTSEN bit in the US_CR. The slave select line (NSS) can be released at high level only by writing a 1 to the RTSDIS bit in the US_CR (for example, when all data have been transferred to the slave device). In SPI Slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least one tbit before the first serial clock cycle corresponding to the MSB bit. DS60001517A-page 766  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.6.7.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the RXRDY bit in the Status register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in the US_CR. To ensure correct behavior of the receiver in SPI Slave mode, the master device sending the frame must ensure a minimum delay of one tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least one tbit before the first serial clock cycle corresponding to the MSB bit. 39.6.7.7 Receiver Timeout Because the receiver baud rate clock is active only during data transfers in SPI mode, a receiver timeout is impossible in this mode, whatever the time-out value is (field TO) in the US_RTOR. 39.6.8 LIN Mode The LIN mode provides master node and slave node connectivity on a LIN bus. The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: • Single master/multiple slaves concept • Low-cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine. • Self synchronization without quartz or ceramic resonator in the slave nodes • Deterministic signal transmission • Low cost single-wire implementation • Speed up to 20 kbit/s LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required. The LIN mode enables processing LIN frames with a minimum of action from the microprocessor. 39.6.8.1 Modes of Operation The USART can act either as a LIN master node or as a LIN slave node. The node configuration is chosen by setting the USART_MODE field in the USART Mode register (US_MR): • LIN master node (USART_MODE = 0xA) • LIN slave node (USART_MODE = 0xB) In order to avoid unpredictable behavior, any change of the LIN node configuration must be followed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See Section 39.6.8.3 “Receiver and Transmitter Control”.) 39.6.8.2 Baud Rate Configuration See Section 39.6.1.1 ”Baud Rate in Asynchronous Mode” The baud rate is configured in US_BRGR. 39.6.8.3 Receiver and Transmitter Control See Section 39.6.2 ”Receiver and Transmitter Control” 39.6.8.4 Character Transmission See Section 39.6.3.1 ”Transmitter Operations”. 39.6.8.5 Character Reception See Section 39.6.3.7 ”Receiver Operations”.  2017 Microchip Technology Inc. DS60001517A-page 767 SAM9N12/SAM9CN11/SAM9CN12 39.6.8.6 Header Transmission (Master Node Configuration) All the LIN frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. So in master node configuration, the frame handling starts with the sending of the header. The header is transmitted as soon as the identifier is written in the LIN Identifier register (US_LINIR). At this moment the flag TXRDY falls. The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other. The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the Identifier corresponds to the character written in the LIN Identifier register (US_LINIR). The Identifier parity bits can be automatically computed and sent (see Section 39.6.8.9 ”Identifier Parity”). The flag TXRDY rises when the identifier character is transferred into the Shift register of the transmitter. As soon as the Synch Break Field is transmitted, the flag LINBK in US_CSR is set to 1. Likewise, as soon as the Identifier Field is sent, the flag bit LINID in the US_CSR is set to 1. These flags are reset by writing a 1 to the bit RSTSTA in US_CR. Figure 39-39: Header Transmission Baud Rate Clock TXD Break Field 13 dominant bits (at 0) Write US_LINIR US_LINIR Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Stop Start ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit ID TXRDY LINBK in US_CSR LINID in US_CSR Write RSTSTA=1 in US_CR 39.6.8.7 Header Reception (Slave Node Configuration) All the LIN frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field. As long as a Break Field has not been detected, the USART stays idle and the received data are not taken in account. When a Break Field has been detected, the flag LINBK in US_CSR is set to 1 and the USART expects the Synch Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized (see Section 39.6.8.8 ”Slave Node Synchronization”). If the received Synch character is not 0x55, an Inconsistent Synch Field error is generated (see Section 39.6.8.14 ”LIN Errors”). After receiving the Synch Field, the USART expects to receive the Identifier Field. When the Identifier Field has been received, the flag bit LINID in the US_CSR is set to 1. At this moment the field IDCHR in the LIN Identifier register (US_LINIR) is updated with the received character. The Identifier parity bits can be automatically computed and checked (see Section 39.6.8.9 ”Identifier Parity”). The flag bits LINID and LINBK are reset by writing a 1 to the bit RSTSTA in US_CR. DS60001517A-page 768  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 39-40: Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINBK LINID US_LINIR Write RSTSTA=1 in US_CR 39.6.8.8 Slave Node Synchronization The synchronization is done only in slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times. Figure 39-41: Synch Field Synch Field 8 Tbit 2 Tbit Start bit 2 Tbit 2 Tbit 2 Tbit Stop bit The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 39.6.1 ”Baud Rate Generator”). When the start bit of the Synch Field is detected, the counter is reset. Then during the next eight tbit of the Synch Field, the counter is incremented. At the end of these eight tbit, the counter is stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) give the new clock divider (LINCD) and the three least significant bits of this value (the remainder) give the new fractional part (LINFP). When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in US_BRGR. If it appears that the sampled Synch character is not equal to 0x55, then the error flag LINISFE in US_CSR is set to 1. It is reset by writing bit RSTSTA to 1 in US_CR.  2017 Microchip Technology Inc. DS60001517A-page 769 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-42: Slave Node Synchronization Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINIDRX Reset Synchro Counter 000_0011_0001_0110_1101 US_BRGR Clock Divider (CD) Initial CD US_BRGR Fractional Part (FP) Initial FP US_LINBRR Clock Divider (CD) Initial CD 0000_0110_0010_1101 US_LINBRR Fractional Part (FP) Initial FP 101 The accuracy of the synchronization depends on several parameters: • Nominal clock frequency (fNom) (the theoretical slave node clock frequency) • Baud Rate • Oversampling (OVER = 0 → 16X or OVER = 0 → 8X) The following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (fSLAVE is the real slave node clock frequency): [ α × 8 × ( 2 – OVER ) + β ] × Baudrate Baudrate_deviation =  100 × ------------------------------------------------------------------------------------------------- %   8 × f SLAVE    [ α × 8 × ( 2 – OVER ) + β ] × Baudrate Baudrate_deviation =  100 × ------------------------------------------------------------------------------------------------- % f TOL_UNSYNCH   8 ×  ------------------------------------- × f Nom   100 – 0.5 ≤ α ≤ +0.5 -1 < β < +1 fTOL_UNSYNCH is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard imposes that it must not exceed ±15%. The LIN Standard imposes also that for communication between two nodes, their bit rate must not differ by more than ±2%. This means that the baudrate_deviation must not exceed ±1%. It follows from that, a minimum value for the nominal clock frequency:    [--------------------------------------------------------------------------------------------------0.5 × 8 × ( 2 – OVER ) + 1 ] × Baudrate- f Nom ( min ) =  100 ×  Hz – 15   -------- × 1% 8 × + 1    100  Examples: • • • • Baud rate = 20 kbit/s, OVER = 0 (Oversampling 16X) → fNom(min) = 2.64 MHz Baud rate = 20 kbit/s, OVER = 1 (Oversampling 8X) → fNom(min) = 1.47 MHz Baud rate = 1 kbit/s, OVER = 0 (Oversampling 16X) → fNom(min) = 132 kHz Baud rate = 1 kbit/s, OVER = 1 (Oversampling 8X) → fNom(min) = 74 kHz DS60001517A-page 770  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.6.8.9 Identifier Parity A protected identifier consists of two subfields: the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. The USART interface can generate/check these parity bits, but this feature can also be disabled. The user can choose between two modes by the PARDIS bit of US_LINMR: • PARDIS = 0: - During header transmission, the parity bits are computed and sent with the six least significant bits of the IDCHR field of the LIN Identifier register (US_LINIR). The bits 6 and 7 of this register are discarded. - During header reception, the parity bits of the identifier are checked. If the parity bits are wrong, an Identifier Parity error occurs (see Section 39.6.3.8 “Parity”). Only the six least significant bits of the IDCHR field are updated with the received Identifier. The bits 6 and 7 are stuck to 0. • PARDIS = 1: - During header transmission, all the bits of the IDCHR field of the LIN Identifier register (US_LINIR) are sent on the bus. - During header reception, all the bits of the IDCHR field are updated with the received Identifier. 39.6.8.10 Node Action Depending on the identifier, the node is affected – or not – by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations: • PUBLISH: the node sends the response. • SUBSCRIBE: the node receives the response. • IGNORE: the node is not concerned by the response, it does not send and does not receive the response. This configuration is made by the field Node Action (NACT) in the US_LINMR (see Section 39.7.26 “USART LIN Mode Register”). Example: a LIN cluster that contains a master and two slaves: • Data transfer from the master to the slave1 and to the slave2: NACT(master)=PUBLISH NACT(slave1)=SUBSCRIBE NACT(slave2)=SUBSCRIBE • Data transfer from the master to the slave1 only: NACT(master)=PUBLISH NACT(slave1)=SUBSCRIBE NACT(slave2)=IGNORE • Data transfer from the slave1 to the master: NACT(master)=SUBSCRIBE NACT(slave1)=PUBLISH NACT(slave2)=IGNORE • Data transfer from the slave1 to the slave2: NACT(master)=IGNORE NACT(slave1)=PUBLISH NACT(slave2)=SUBSCRIBE • Data transfer from the slave2 to the master and to the slave1: NACT(master)=SUBSCRIBE NACT(slave1)=SUBSCRIBE NACT(slave2)=PUBLISH  2017 Microchip Technology Inc. DS60001517A-page 771 SAM9N12/SAM9CN11/SAM9CN12 39.6.8.11 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1). The user can choose between these two modes by the DLM bit of US_LINMR: • DLM = 0: The response data length is configured by the user via the DLC field of US_LINMR. The response data length is equal to (DLC + 1) bytes. DLC can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes. • DLM = 1: The response data length is defined by the Identifier (IDCHR in US_LINIR) according to the table below. The DLC field of US_LINMR is discarded. The response can contain 2 or 4 or 8 data bytes. Table 39-14: Response Data Length if DLM = 1 IDCHR[5] IDCHR[4] Response Data Length [Bytes] 0 0 2 0 1 2 1 0 4 1 1 8 Figure 39-43: Response Data Length User configuration: 1–256 data fields (DLC+1) Identifier configuration: 2/4/8 data fields Sync Break 39.6.8.12 Sync Field Identifier Field Data Field Data Field Data Field Data Field Checksum Field Checksum The last field of a frame is the checksum. The checksum contains the inverted 8-bit sum with carry, over all data bytes or all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic checksum and it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves. The USART can be configured to: • Send/Check an Enhanced checksum automatically (CHKDIS = 0 & CHKTYP = 0) • Send/Check a Classic checksum automatically (CHKDIS = 0 & CHKTYP = 1) • Not send/check a checksum (CHKDIS = 1) This configuration is made by the Checksum Type (CHKTYP) and Checksum Disable (CHKDIS) fields of US_LINMR. If the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see Section 39.6.8.11 “Response Data Length”). 39.6.8.13 Frame Slot Mode This mode is useful only for master nodes. It complies with the following rule: each frame slot should be longer than or equal to tFrame_Maximum. If the Frame slot mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after tFrame_Maximum delay, from the start of frame. So the master node cannot send a new header if the frame slot duration of the previous frame is inferior to tFrame_Maximum. If the Frame slot mode is disabled (FSDIS = 1) and a frame transfer has been completed, the TXRDY flag is set again immediately. DS60001517A-page 772  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 The tFrame_Maximum is calculated as shown below: If the Checksum is sent (CHKDIS = 0): tHeader_Nominal = 34 × tbit tResponse_Nominal = 10 × (NData + 1) × tbit tFrame_Maximum = 1.4 × (tHeader_Nominal + tResponse_Nominal + 1)(1) tFrame_Maximum = 1.4 × (34 + 10 × (DLC + 1 + 1) + 1) × tbit tFrame_Maximum = (77 + 14 × DLC) × tbit If the Checksum is not sent (CHKDIS = 1): tHeader_Nominal = 34 × tbit tResponse_Nominal = 10 × NData × tbit tFrame_Maximum = 1.4 × (tHeader_Nominal + tResponse_Nominal + 1)(1) tFrame_Maximum = 1.4 × (34 + 10 × (DLC + 1) + 1) × tbit tFrame_Maximum = (63 + 14 × DLC) × tbit Note 1: The term “+1” leads to an integer result for tFrame_Maximum (LIN Specification 1.3). Figure 39-44: Frame Slot Mode Frame slot = tFrame_Maximum Frame Data3 Header Break Synch Response space Protected Identifier Interframe space Response Data 1 Data N-1 Checksum Data N TXRDY Frame Slot Mode Frame Slot Mode Disabled Enabled Write US_LINID Write US_THR Data 1 Data 2 Data 3 Data N LINTC 39.6.8.14 LIN Errors Bit Error This error is generated in master of slave node configuration, when the USART is transmitting and if the transmitted value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is aborted at the next byte border. This error is reported by flag LINBE in US_CSR. Inconsistent Synch Field Error This error is generated in slave node configuration, if the Synch Field character received is other than 0x55. This error is reported by flag LINISFE in the US_CSR. Identifier Parity Error This error is generated in slave node configuration, if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). This error is reported by flag LINIPE in the US_CSR.  2017 Microchip Technology Inc. DS60001517A-page 773 SAM9N12/SAM9CN11/SAM9CN12 Checksum Error This error is generated in master of slave node configuration, if the received checksum is wrong. This flag can be set to 1 only if the checksum feature is enabled (CHKDIS = 0). This error is reported by flag LINCE in the US_CSR. Slave Not Responding Error This error is generated in master of slave node configuration, when the USART expects a response from another node (NACT = SUBSCRIBE) but no valid message appears on the bus within the time given by the maximum length of the message frame, tFrame_Maximum (see Section 39.6.8.13 “Frame Slot Mode”). This error is disabled if the USART does not expect any message (NACT = PUBLISH or NACT = IGNORE). This error is reported by flag LINSNRE in the US_CSR. 39.6.8.15 LIN Frame Handling Master Node Configuration • • • • • • Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. Write USART_MODE in US_MR to select the LIN mode and the master node configuration. Write CD and FP in US_BRGR to configure the baud rate. Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FSDIS and DLC in US_LINMR to configure the frame transfer. Check that TXRDY in US_CSR is set to 1 Write IDCHR in US_LINIR to send the header What comes next depends on the NACT configuration: • Case 1: NACT = PUBLISH, the USART sends the response - Wait until TXRDY in US_CSR rises - Write TCHR in US_THR to send a byte - If all the data have not been written, redo the two previous steps - Wait until LINTC in US_CSR rises - Check the LIN errors • Case 2: NACT = SUBSCRIBE, the USART receives the response - Wait until RXRDY in US_CSR rises - Read RCHR in US_RHR - If all the data have not been read, redo the two previous steps - Wait until LINTC in US_CSR rises - Check the LIN errors • Case 3: NACT = IGNORE, the USART is not concerned by the response - Wait until LINTC in US_CSR rises - Check the LIN errors DS60001517A-page 774  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 39-45: Master Node Configuration, NACT = PUBLISH Frame slot = tFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 39-46: Master Node Configuration, NACT = SUBSCRIBE Frame slot = tFrame_Maximum Frame Header Break Synch Data3 Response space Protected Identifier Interframe space Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC  2017 Microchip Technology Inc. DS60001517A-page 775 SAM9N12/SAM9CN11/SAM9CN12 Figure 39-47: Master Node Configuration, NACT = IGNORE Frame slot = tFrame_Maximum Frame Break Response space Header Data3 Synch Protected Identifier Interframe space Response Data 1 Data N-1 Checksum Data N TXRDY FSDIS=1 FSDIS=0 RXRDY Write US_LINIR LINTC Slave Node Configuration • • • • • • • Write TXEN and RXEN in US_CR to enable both the transmitter and the receiver. Write USART_MODE in US_MR to select the LIN mode and the slave node configuration. Write CD and FP in US_BRGR to configure the baud rate. Wait until LINID in US_CSR rises Check LINISFE and LINPE errors Read IDCHR in US_RHR Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in US_LINMR to configure the frame transfer. IMPORTANT: If the NACT configuration for this frame is PUBLISH, the US_LINMR must be written with NACT = PUBLISH even if this field is already correctly configured, in order to set the TXREADY flag and the corresponding write transfer request. What comes next depends on the NACT configuration: • Case 1: NACT = PUBLISH, the LIN controller sends the response - Wait until TXRDY in US_CSR rises - Write TCHR in US_THR to send a byte - If all the data have not been written, redo the two previous steps - Wait until LINTC in US_CSR rises - Check the LIN errors • Case 2: NACT = SUBSCRIBE, the USART receives the response - Wait until RXRDY in US_CSR rises - Read RCHR in US_RHR - If all the data have not been read, redo the two previous steps - Wait until LINTC in US_CSR rises - Check the LIN errors • Case 3: NACT = IGNORE, the USART is not concerned by the response - Wait until LINTC in US_CSR rises - Check the LIN errors DS60001517A-page 776  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 39-48: Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Write US_THR Data 1 Data 2 Data 3 Data N LINTC Figure 39-49: Slave Node Configuration, NACT = SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 39-50: Slave Node Configuration, NACT = IGNORE Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read US_LINID Read US_RHR LINTC 39.6.8.16 LIN Frame Handling with the DMAC The USART can be used in association with the DMAC in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. The DMAC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The DMAC always writes in the Transmit Holding register (US_THR) and it always reads in the Receive Holding register (US_RHR). The size of the data written or read by the DMAC in the USART is always a byte.  2017 Microchip Technology Inc. DS60001517A-page 777 SAM9N12/SAM9CN11/SAM9CN12 Master Node Configuration The user can choose between two DMAC modes by the PDCM bit in the US_LINMR: • PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the DMAC in the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR). Because the DMAC transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is written. • PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in US_LINMR. The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT = PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE). Figure 39-51: Master Node with DMAC (PDCM = 1) WRITE BUFFER WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS NACT PARDIS CHKDIS CHKTYP DLM FSDIS DLC DLC NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE IDENTIFIER APB bus APB bus IDENTIFIER (Peripheral) DMA Controller USART LIN Controller READ BUFFER (Peripheral) DMA Controller RXRDY USART LIN Controller TXRDY DATA 0 DATA 0 | | | | TXRDY | | | | DATA N Figure 39-52: DATA N Master Node with DMAC (PDCM = 0) WRITE BUFFER WRITE BUFFER IDENTIFIER IDENTIFIER NODE ACTION = PUBLISH DATA 0 | | | | DATA N NODE ACTION = SUBSCRIBE APB bus APB bus READ BUFFER (Peripheral) DMA Controller USART LIN Controller TXRDY DATA 0 (Peripheral) DMA Controller RXRDY USART LIN Controller TXRDY | | | | DATA N DS60001517A-page 778  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Slave Node Configuration In this configuration, the DMAC transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in US_LINMR. The WRITE buffer contains the DATA if the USART sends the response (NACT = PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE). Figure 39-53: Slave Node with DMAC WRITE BUFFER READ BUFFER DATA 0 DATA 0 NACT = SUBSCRIBE APB bus | | | | (Peripheral) DMA Controller APB bus USART LIN Controller TXRDY DATA N 39.6.8.17 | | | | (Peripheral) DMA Controller USART LIN Controller RXRDY DATA N Wake-up Request Any node in a sleeping LIN cluster may request a wake-up. In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 µs to 5 ms. For this, it is necessary to send the character 0xF0 in order to impose five successive dominant bits. Whatever the baud rate is, this character complies with the specified timings. • Baud rate min = 1 kbit/s → tbit = 1 ms → 5 tbit = 5 ms • Baud rate max = 20 kbit/s → tbit = 50 µs → 5 tbit = 250 µs In the LIN 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose eight successive dominant bits. The user can choose by the WKUPTYP bit in US_LINMR either to send a LIN 2.0 wakeup request (WKUPTYP = 0) or to send a LIN 1.3 wakeup request (WKUPTYP = 1). A wake-up request is transmitted by writing a 1 to the LINWKUP bit in the US_CR. Once the transfer is completed, the LINTC flag is asserted in the Status register (US_SR). It is cleared by writing a 1 to the RSTSTA bit in the US_CR. 39.6.8.18 Bus Idle Time-out If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in Sleep mode. In the LIN 2.0 specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25,000 tbit. In slave Node configuration, the receiver time-out detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in US_CSR rises and can generate an interrupt, thus indicating to the driver to go into Sleep mode. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of US_RTOR. If a 0 is written to the TO field, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 17-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the US_CSR rises. If STTTO is performed, the counter clock is stopped until a first character is received. If RETTO is performed, the counter starts counting down immediately from the value TO.  2017 Microchip Technology Inc. DS60001517A-page 779 SAM9N12/SAM9CN11/SAM9CN12 Table 39-15: Receiver Time-out Programming LIN Specification 2.0 Time-out period US_RTOR.TO 1,000 bit/s 4,000 2,400 bit/s 9,600 9,600 bit/s 1.3 39.6.9 Baud Rate 4s 38,400 19,200 bit/s 76,800 20,000 bit/s 80,000 – 25,000 25,000 tbit Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In Loopback mode, the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 39.6.9.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 39-54: Normal Mode Configuration RXD Receiver TXD Transmitter 39.6.9.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 39-55. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 39-55: Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 39.6.9.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 39-56. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. DS60001517A-page 780  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 39-56: Local Loopback Mode Configuration RXD Receiver 1 Transmitter 39.6.9.4 TXD Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 39-57. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 39-57: Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 39.6.10 Register Write Protection To prevent any single software error from corrupting USART behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the USART Write Protection Mode Register (US_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the USART Write Protection Status Register (US_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the US_WPSR. The following registers can be write-protected: • • • • USART Mode Register USART Baud Rate Generator Register USART Receiver Time-out Register USART Transmitter Timeguard Register • USART FI DI RATIO Register • USART IrDA Filter Register • USART Manchester Configuration Register  2017 Microchip Technology Inc. DS60001517A-page 781 SAM9N12/SAM9CN11/SAM9CN12 39.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 39-16: Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read/Write 0x0 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only – 0x0010 Interrupt Mask Register US_IMR Read-only 0x0 0x0014 Channel Status Register US_CSR Read-only 0x0 0x0018 Receive Holding Register US_RHR Read-only 0x0 0x001C Transmit Holding Register US_THR Write-only – 0x0020 Baud Rate Generator Register US_BRGR Read/Write 0x0 0x0024 Receiver Time-out Register US_RTOR Read/Write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read/Write 0x0 Reserved – – – 0x0040 FI DI Ratio Register US_FIDI Read/Write 0x174 0x0044 Number of Errors Register US_NER Read-only 0x0 0x0048 Reserved – – – 0x004C IrDA Filter Register US_IF Read/Write 0x0 0x0050 Manchester Configuration Register US_MAN Read/Write 0x30011004 0x0054 LIN Mode Register US_LINMR Read/Write 0x0 0x002C–0x003C 0x0058 LIN Identifier Register US_LINIR 0x005C LIN Baud Rate Register US_LINBRR Reserved – 0x00E4 Write Protection Mode Register 0x00E8 0x0060–0x00E0 0x00EC–0x00FC Read/Write (1) 0x0 Read-only 0x0 – – US_WPMR Read/Write 0x0 Write Protection Status Register US_WPSR Read-only 0x0 Reserved – – – Note 1: Write is possible only in LIN master node configuration. DS60001517A-page 782  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.1 USART Control Register Name:US_CR Address:0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see Section 39.7.2 ”USART Control Register (SPI_MODE)”. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR, LINBE, LINISFE, LINIPE, LINCE, LINSNRE, LINID, LINTC, LINBK and RXBRK in US_CSR. STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.  2017 Microchip Technology Inc. DS60001517A-page 783 SAM9N12/SAM9CN11/SAM9CN12 STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. STTTO: Clear TIMEOUT Flag and Start Time-out After Next Character Received 0: No effect. 1: Starts waiting for a character before enabling the time-out counter. Immediately disables a time-out period in progress. Resets the status bit TIMEOUT in US_CSR. SENDA: Send Address 0: No effect. 1: In Multidrop mode only, the next character written to the US_THR is sent with the address bit set. RSTIT: Reset Iterations 0: No effect. 1: Resets ITER in US_CSR. No effect if the ISO7816 is not enabled. RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. RETTO: Start Time-out Immediately 0: No effect 1: Immediately restarts time-out period. RTSEN: Request to Send Pin Control 0: No effect. 1: Drives RTS pin to 0 if US_MR.USART_MODE field = 0. RTSDIS: Request to Send Pin Control 0: No effect. 1: Drives RTS pin to 1 if US_MR.USART_MODE field = 0. LINABT: Abort LIN Transmission 0: No effect. 1: Abort the current LIN transmission. LINWKUP: Send LIN Wakeup Signal 0: No effect. 1: Sends a wakeup signal on the LIN bus. DS60001517A-page 784  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.2 USART Control Register (SPI_MODE) Name:US_CR (SPI_MODE) Address:0xF801C000 (0), 0xF8020000 (1), 0xF8024000 (2), 0xF8028000 (3) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits OVRE, UNRE in US_CSR. FCS: Force SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect. 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI slave devices supporting the CSAAT mode (Chip Select Active After Transfer).  2017 Microchip Technology Inc. DS60001517A-page 785 SAM9N12/SAM9CN11/SAM9CN12 RCS: Release SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect. 1: Releases the Slave Select Line NSS (RTS pin). DS60001517A-page 786  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.3 USART Mode Register Name:US_MR Address:0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access:Read/Write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. For SPI configuration, see Section 39.7.4 ”USART Mode Register (SPI_MODE)”. USART_MODE: USART Mode of Operation Value Name Description 0x0 NORMAL Normal mode 0x1 RS485 RS485 0x2 HW_HANDSHAKING Hardware Handshaking 0x3 — Reserved 0x4 IS07816_T_0 IS07816 Protocol: T = 0 0x6 IS07816_T_1 IS07816 Protocol: T = 1 0x8 IRDA IrDA 0xA LIN_MASTER LIN master 0xB LIN_SLAVE LIN Slave 0xE SPI_MASTER SPI master 0xF SPI_SLAVE SPI Slave USCLKS: Clock Selection Value Name Description 0 MCK Peripheral clock is selected 1 DIV Peripheral clock divided (DIV = 8) is selected 2 — Reserved 3 SCK Serial clock (SCK) is selected  2017 Microchip Technology Inc. DS60001517A-page 787 SAM9N12/SAM9CN11/SAM9CN12 CHRL: Character Length Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits SYNC: Synchronous Mode Select 0: USART operates in Asynchronous mode. 1: USART operates in Synchronous mode. PAR: Parity Type Value Name Description 0 EVEN Even parity 1 ODD Odd parity 2 SPACE Parity forced to 0 (Space) 3 MARK Parity forced to 1 (Mark) 4 NO No parity 6 MULTIDROP Multidrop mode NBSTOP: Number of Stop Bits Value Name Description 0 1_BIT 1 stop bit 1 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 2 2_BIT 2 stop bits CHMODE: Channel Mode Value Name Description 0 NORMAL Normal mode 1 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 2 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 3 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. MSBF: Bit Order 0: Least significant bit is sent/received first. 1: Most significant bit is sent/received first. MODE9: 9-bit Character Length 0: CHRL defines character length 1: 9-bit character length CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. DS60001517A-page 788  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 OVER: Oversampling Mode 0: 16 × Oversampling 1: 8 × Oversampling INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITER is asserted. Note: MAX_ITERATION field must be set to 0 if DSNACK is cleared. INVDATA: Inverted Data 0: The data field transmitted on TXD line is the same as the one written in US_THR or the content read in US_RHR is the same as RXD line. Normal mode of operation. 1: The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted mode of operation, useful for contactless card application. To be used with configuration bit MSBF. VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on MODSYNC value. 1: The sync field is updated when a character is written into US_THR. MAX_ITERATION: Maximum Number of Automatic Iteration 0–7: Defines the maximum number of iterations in mode ISO7816, protocol T = 0. FILTER: Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). MAN: Manchester Encoder/Decoder Enable 0: Manchester encoder/decoder are disabled. 1: Manchester encoder/decoder are enabled. MODSYNC: Manchester Synchronization Mode 0:The Manchester start bit is a 0 to 1 transition 1: The Manchester start bit is a 1 to 0 transition. ONEBIT: Start Frame Delimiter Selector 0: Start frame delimiter is COMMAND or DATA SYNC. 1: Start frame delimiter is one bit.  2017 Microchip Technology Inc. DS60001517A-page 789 SAM9N12/SAM9CN11/SAM9CN12 39.7.4 USART Mode Register (SPI_MODE) Name:US_MR (SPI_MODE) Address:0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 – 18 CLKO 17 – 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 6 5 4 3 2 1 0 7 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. USART_MODE: USART Mode of Operation Value Name Description 0xE SPI_MASTER SPI master 0xF SPI_SLAVE SPI Slave USCLKS: Clock Selection Value Name Description 0 MCK Peripheral clock is selected 1 DIV Peripheral clock divided (DIV = 8) is selected 3 SCK Serial Clock SLK is selected CHRL: Character Length Value Name Description 3 8_BIT Character length is 8 bits CPHA: SPI Clock Phase – Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF): 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. CPOL: SPI Clock Polarity Applicable if USART operates in SPI mode (slave or master, USART_MODE = 0xE or 0xF): 0: The inactive state value of SPCK is logic level zero. 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices. DS60001517A-page 790  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. WRDBT: Wait Read Data Before Transfer 0: The character transmission starts as soon as a character is written into US_THR (assuming TXRDY was set). 1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receive Holding Register has been read).  2017 Microchip Technology Inc. DS60001517A-page 791 SAM9N12/SAM9CN11/SAM9CN12 39.7.5 USART Interrupt Enable Register Name:US_IER Address:0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 39.7.6 ”USART Interrupt Enable Register (SPI_MODE)”. For LIN specific configuration, see Section 39.7.7 ”USART Interrupt Enable Register (LIN_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. RXRDY: RXRDY Interrupt Enable TXRDY: TXRDY Interrupt Enable RXBRK: Receiver Break Interrupt Enable OVRE: Overrun Error Interrupt Enable FRAME: Framing Error Interrupt Enable PARE: Parity Error Interrupt Enable TIMEOUT: Time-out Interrupt Enable TXEMPTY: TXEMPTY Interrupt Enable ITER: Max number of Repetitions Reached Interrupt Enable NACK: Non Acknowledge Interrupt Enable CTSIC: Clear to Send Input Change Interrupt Enable MANE: Manchester Error Interrupt Enable DS60001517A-page 792  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.6 USART Interrupt Enable Register (SPI_MODE) Name:US_IER (SPI_MODE) Address:0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. RXRDY: RXRDY Interrupt Enable TXRDY: TXRDY Interrupt Enable OVRE: Overrun Error Interrupt Enable TXEMPTY: TXEMPTY Interrupt Enable UNRE: SPI Underrun Error Interrupt Enable NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable  2017 Microchip Technology Inc. DS60001517A-page 793 SAM9N12/SAM9CN11/SAM9CN12 39.7.7 USART Interrupt Enable Register (LIN_MODE) Name:US_IER (LIN_MODE) Address:0xF801C008 (0), 0xF8020008 (1), 0xF8024008 (2), 0xF8028008 (3) Access:Write-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 LINTC 14 LINID 13 LINBK 12 – 11 – 10 – 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. RXRDY: RXRDY Interrupt Enable TXRDY: TXRDY Interrupt Enable OVRE: Overrun Error Interrupt Enable FRAME: Framing Error Interrupt Enable PARE: Parity Error Interrupt Enable TIMEOUT: Time-out Interrupt Enable TXEMPTY: TXEMPTY Interrupt Enable LINBK: LIN Break Sent or LIN Break Received Interrupt Enable LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Enable LINTC: LIN Transfer Completed Interrupt Enable LINBE: LIN Bus Error Interrupt Enable LINISFE: LIN Inconsistent Synch Field Error Interrupt Enable LINIPE: LIN Identifier Parity Interrupt Enable LINCE: LIN Checksum Error Interrupt Enable LINSNRE: LIN Slave Not Responding Error Interrupt Enable DS60001517A-page 794  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.8 USART Interrupt Disable Register Name:US_IDR Address:0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 39.7.9 ”USART Interrupt Disable Register (SPI_MODE)”. For LIN specific configuration, see Section 39.7.10 ”USART Interrupt Disable Register (LIN_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. RXRDY: RXRDY Interrupt Disable TXRDY: TXRDY Interrupt Disable RXBRK: Receiver Break Interrupt Disable OVRE: Overrun Error Interrupt Enable FRAME: Framing Error Interrupt Disable PARE: Parity Error Interrupt Disable TIMEOUT: Time-out Interrupt Disable TXEMPTY: TXEMPTY Interrupt Disable ITER: Max Number of Repetitions Reached Interrupt Disable NACK: Non Acknowledge Interrupt Disable CTSIC: Clear to Send Input Change Interrupt Disable MANE: Manchester Error Interrupt Disable  2017 Microchip Technology Inc. DS60001517A-page 795 SAM9N12/SAM9CN11/SAM9CN12 39.7.9 USART Interrupt Disable Register (SPI_MODE) Name:US_IDR (SPI_MODE) Address:0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. RXRDY: RXRDY Interrupt Disable TXRDY: TXRDY Interrupt Disable OVRE: Overrun Error Interrupt Disable TXEMPTY: TXEMPTY Interrupt Disable UNRE: SPI Underrun Error Interrupt Disable NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable DS60001517A-page 796  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.10 USART Interrupt Disable Register (LIN_MODE) Name:US_IDR (LIN_MODE) Address:0xF801C00C (0), 0xF802000C (1), 0xF802400C (2), 0xF802800C (3) Access:Write-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 LINTC 14 LINID 13 LINBK 12 – 11 – 10 – 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. RXRDY: RXRDY Interrupt Disable TXRDY: TXRDY Interrupt Disable OVRE: Overrun Error Interrupt Disable FRAME: Framing Error Interrupt Disable PARE: Parity Error Interrupt Disable TIMEOUT: Time-out Interrupt Disable TXEMPTY: TXEMPTY Interrupt Disable LINBK: LIN Break Sent or LIN Break Received Interrupt Disable LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Disable LINTC: LIN Transfer Completed Interrupt Disable LINBE: LIN Bus Error Interrupt Disable LINISFE: LIN Inconsistent Synch Field Error Interrupt Disable LINIPE: LIN Identifier Parity Interrupt Disable LINCE: LIN Checksum Error Interrupt Disable LINSNRE: LIN Slave Not Responding Error Interrupt Disable  2017 Microchip Technology Inc. DS60001517A-page 797 SAM9N12/SAM9CN11/SAM9CN12 39.7.11 USART Interrupt Mask Register Name:US_IMR Address:0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 39.7.12 ”USART Interrupt Mask Register (SPI_MODE)”. For LIN specific configuration, see Section 39.7.13 ”USART Interrupt Mask Register (LIN_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. RXRDY: RXRDY Interrupt Mask TXRDY: TXRDY Interrupt Mask RXBRK: Receiver Break Interrupt Mask OVRE: Overrun Error Interrupt Mask FRAME: Framing Error Interrupt Mask PARE: Parity Error Interrupt Mask TIMEOUT: Time-out Interrupt Mask TXEMPTY: TXEMPTY Interrupt Mask ITER: Max Number of Repetitions Reached Interrupt Mask NACK: Non Acknowledge Interrupt Mask CTSIC: Clear to Send Input Change Interrupt Mask MANE: Manchester Error Interrupt Mask DS60001517A-page 798  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.12 USART Interrupt Mask Register (SPI_MODE) Name:US_IMR (SPI_MODE) Address:0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. RXRDY: RXRDY Interrupt Mask TXRDY: TXRDY Interrupt Mask OVRE: Overrun Error Interrupt Mask TXEMPTY: TXEMPTY Interrupt Mask UNRE: SPI Underrun Error Interrupt Mask NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask  2017 Microchip Technology Inc. DS60001517A-page 799 SAM9N12/SAM9CN11/SAM9CN12 39.7.13 USART Interrupt Mask Register (LIN_MODE) Name:US_IMR (LIN_MODE) Address:0xF801C010 (0), 0xF8020010 (1), 0xF8024010 (2), 0xF8028010 (3) Access:Read-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 LINTC 14 LINID 13 LINBK 12 – 11 – 10 – 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. RXRDY: RXRDY Interrupt Mask TXRDY: TXRDY Interrupt Mask OVRE: Overrun Error Interrupt Mask FRAME: Framing Error Interrupt Mask PARE: Parity Error Interrupt Mask TIMEOUT: Time-out Interrupt Mask TXEMPTY: TXEMPTY Interrupt Mask LINBK: LIN Break Sent or LIN Break Received Interrupt Mask LINID: LIN Identifier Sent or LIN Identifier Received Interrupt Mask LINTC: LIN Transfer Completed Interrupt Mask LINBE: LIN Bus Error Interrupt Mask LINISFE: LIN Inconsistent Synch Field Error Interrupt Mask LINIPE: LIN Identifier Parity Interrupt Mask LINCE: LIN Checksum Error Interrupt Mask LINSNRE: LIN Slave Not Responding Error Interrupt Mask DS60001517A-page 800  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.14 USART Channel Status Register Name:US_CSR Address:0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 39.7.15 ”USART Channel Status Register (SPI_MODE)”. For LIN specific configuration, see Section 39.7.16 ”USART Channel Status Register (LIN_MODE)”. RXRDY: Receiver Ready (cleared by reading US_RHR) 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. TXRDY: Transmitter Ready (cleared by writing US_THR) 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. RXBRK: Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 0: No break received or end of break detected since the last RSTSTA. 1: Break received or end of break detected since the last RSTSTA. OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. FRAME: Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. PARE: Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. TIMEOUT: Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). TXEMPTY: Transmitter Empty (cleared by writing US_THR) 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register.  2017 Microchip Technology Inc. DS60001517A-page 801 SAM9N12/SAM9CN11/SAM9CN12 ITER: Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 0: Maximum number of repetitions has not been reached since the last RSTIT. 1: Maximum number of repetitions has been reached since the last RSTIT. NACK: Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 0: Non acknowledge has not been detected since the last RSTNACK. 1: At least one non acknowledge has been detected since the last RSTNACK. CTSIC: Clear to Send Input Change Flag (cleared on read) 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. CTS: Image of CTS Input 0: CTS input is driven low. 1: CTS input is driven high. MANERR: Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. DS60001517A-page 802  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.15 USART Channel Status Register (SPI_MODE) Name:US_CSR (SPI_MODE) Address:0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 NSS 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. RXRDY: Receiver Ready (cleared by reading US_RHR) 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. TXRDY: Transmitter Ready (cleared by writing US_THR) 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty (cleared by writing US_THR) 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. UNRE: Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No SPI underrun error has occurred since the last RSTSTA. 1: At least one SPI underrun error has occurred since the last RSTSTA. NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 0: No NSS line event has been detected since the last read of US_CSR. 1: A rising or falling edge event has been detected on NSS line since the last read of US_CSR . NSS: Image of NSS Line 0: NSS line is driven low (if NSSE = 1, falling edge occurred on NSS line). 1: NSS line is driven high (if NSSE = 1, rising edge occurred on NSS line).  2017 Microchip Technology Inc. DS60001517A-page 803 SAM9N12/SAM9CN11/SAM9CN12 39.7.16 USART Channel Status Register (LIN_MODE) Name:US_CSR (LIN_MODE) Address:0xF801C014 (0), 0xF8020014 (1), 0xF8024014 (2), 0xF8028014 (3) Access:Read-only 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 LINBLS 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 LINTC 14 LINID 13 LINBK 12 – 11 – 10 – 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. RXRDY: Receiver Ready (cleared by reading US_THR) 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. TXRDY: Transmitter Ready (cleared by writing US_THR) 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. FRAME: Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. PARE: Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. TIMEOUT: Receiver Time-out (cleared by writing a one to bit US_CR.RSTSTA) 0: There has not been a time-out since the last start time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last start time-out command (STTTO in US_CR). DS60001517A-page 804  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 TXEMPTY: Transmitter Empty (cleared by writing US_THR) 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. LINBK: LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) Applicable if USART operates in LIN master mode (USART_MODE = 0xA): 0: No LIN break has been sent since the last RSTSTA. 1:At least one LIN break has been sent since the last RSTSTA If USART operates in LIN slave mode (USART_MODE = 0xB): 0: No LIN break has received sent since the last RSTSTA. 1:At least one LIN break has been received since the last RSTSTA. LINID: LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) If USART operates in LIN master mode (USART_MODE = 0xA): 0: No LIN identifier has been sent since the last RSTSTA. 1:At least one LIN identifier has been sent since the last RSTSTA. If USART operates in LIN slave mode (USART_MODE = 0xB): 0: No LIN identifier has been received since the last RSTSTA. 1:At least one LIN identifier has been received since the last RSTSTA LINTC: LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) 0: The USART is idle or a LIN transfer is ongoing. 1: A LIN transfer has been completed since the last RSTSTA. LINBLS: LIN Bus Line Status 0: LIN bus line is set to 0. 1: LIN bus line is set to 1. LINBE: LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No bit error has been detected since the last RSTSTA. 1: A bit error has been detected since the last RSTSTA. LINISFE: LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No LIN inconsistent synch field error has been detected since the last RSTSTA 1: The USART is configured as a slave node and a LIN Inconsistent synch field error has been detected since the last RSTSTA. LINIPE: LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No LIN identifier parity error has been detected since the last RSTSTA. 1: A LIN identifier parity error has been detected since the last RSTSTA. LINCE: LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No LIN checksum error has been detected since the last RSTSTA. 1: A LIN checksum error has been detected since the last RSTSTA. LINSNRE: LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No LIN slave not responding error has been detected since the last RSTSTA. 1: A LIN slave not responding error has been detected since the last RSTSTA.  2017 Microchip Technology Inc. DS60001517A-page 805 SAM9N12/SAM9CN11/SAM9CN12 39.7.17 USART Receive Holding Register Name:US_RHR Address:0xF801C018 (0), 0xF8020018 (1), 0xF8024018 (2), 0xF8028018 (3) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last character received if RXRDY is set. RXSYNH: Received Sync 0: Last character received is a data. 1: Last character received is a command. DS60001517A-page 806  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.18 USART Transmit Holding Register Name:US_THR Address:0xF801C01C (0), 0xF802001C (1), 0xF802401C (2), 0xF802801C (3) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. TXSYNH: Sync Field to be Transmitted 0: The next character sent is encoded as a data. Start frame delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start frame delimiter is COMMAND SYNC.  2017 Microchip Technology Inc. DS60001517A-page 807 SAM9N12/SAM9CN11/SAM9CN12 39.7.19 USART Baud Rate Generator Register Name:US_BRGR Address:0xF801C020 (0), 0xF8020020 (1), 0xF8024020 (2), 0xF8028020 (3) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 OVER = 0 CD OVER = 1 0 1 to 65535 SYNC = 1 or USART_MODE = SPI (Master or Slave) USART_MODE = ISO7816 Baud Rate Clock Disabled CD = Selected Clock / (16 × Baud Rate) CD = Selected Clock / (8 × Baud Rate) CD = Selected Clock / Baud Rate CD = Selected Clock / (FI_DI_RATIO × Baud Rate) FP: Fractional Part 0: Fractional divider is disabled. 1–7: Baud rate resolution, defined by FP × 1/8. Warning: When the value of field FP is greater than 0, the SCK (oversampling clock) generates non-constant duty cycles. The SCK high duration is increased by “selected clock” period from time to time. The duty cycle depends on the value of the CD field. DS60001517A-page 808  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.20 USART Receiver Time-out Register Name:US_RTOR Address:0xF801C024 (0), 0xF8020024 (1), 0xF8024024 (2), 0xF8028024 (3) Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. TO: Time-out Value 0: The receiver time-out is disabled. 1–131071: The receiver time-out is enabled and TO is Time-out Delay / Bit Period.  2017 Microchip Technology Inc. DS60001517A-page 809 SAM9N12/SAM9CN11/SAM9CN12 39.7.21 USART Transmitter Timeguard Register Name:US_TTGR Address:0xF801C028 (0), 0xF8020028 (1), 0xF8024028 (2), 0xF8028028 (3) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. TG: Timeguard Value 0: The transmitter timeguard is disabled. 1–255: The transmitter timeguard is enabled and TG is Timeguard Delay / Bit Period. DS60001517A-page 810  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.22 USART FI DI RATIO Register Name:US_FIDI Address:0xF801C040 (0), 0xF8020040 (1), 0xF8024040 (2), 0xF8028040 (3) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the baud rate generator generates no signal. 1–2: Do not use. 3–2047: If ISO7816 mode is selected, the baud rate is the clock provided on SCK divided by FI_DI_RATIO.  2017 Microchip Technology Inc. DS60001517A-page 811 SAM9N12/SAM9CN11/SAM9CN12 39.7.23 USART Number of Errors Register Name:US_NER Address:0xF801C044 (0), 0xF8020044 (1), 0xF8024044 (2), 0xF8028044 (3) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE = 0x4 or 0x6 in the USART Mode Register. NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. DS60001517A-page 812  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.24 USART IrDA Filter Register Name:US_IF Address:0xF801C04C (0), 0xF802004C (1), 0xF802404C (2), 0xF802804C (3) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE = 0x8 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. IRDA_FILTER: IrDA Filter The IRDA_FILTER value must be defined to meet the following criteria: tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs  2017 Microchip Technology Inc. DS60001517A-page 813 SAM9N12/SAM9CN11/SAM9CN12 39.7.25 USART Manchester Configuration Register Name:US_MAN Address:0xF801C050 (0), 0xF8020050 (1), 0xF8024050 (2), 0xF8028050 (3) Access:Read/Write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 7 – 6 – 5 – 4 – 3 25 24 RX_PP 17 16 10 – 9 8 2 1 RX_PL TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. TX_PL: Transmitter Preamble Length 0: The transmitter preamble pattern generation is disabled 1–15: The preamble length is TX_PL × Bit Period TX_PP: Transmitter Preamble Pattern The following values assume that TX_MPOL field is not set: Value Name Description 0 ALL_ONE The preamble is composed of ‘1’s 1 ALL_ZERO The preamble is composed of ‘0’s 2 ZERO_ONE The preamble is composed of ‘01’s 3 ONE_ZERO The preamble is composed of ‘10’s TX_MPOL: Transmitter Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1–15: The detected preamble length is RX_PL × Bit Period RX_PP: Receiver Preamble Pattern detected The following values assume that RX_MPOL field is not set: Value Name Description 00 ALL_ONE The preamble is composed of ‘1’s 01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s DS60001517A-page 814  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 RX_MPOL: Receiver Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register. DRIFT: Drift Compensation 0: The USART cannot recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.  2017 Microchip Technology Inc. DS60001517A-page 815 SAM9N12/SAM9CN11/SAM9CN12 39.7.26 USART LIN Mode Register Name:US_LINMR Address:0xF801C054 (0), 0xF8020054 (1), 0xF8024054 (2), 0xF8028054 (3) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT This register is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. NACT: LIN Node Action Value Name Description 00 PUBLISH The USART transmits the response. 01 SUBSCRIBE The USART receives the response. 10 IGNORE The USART does not transmit and does not receive the response. Values which are not listed in the table must be considered as “reserved”. PARDIS: Parity Disable 0: In master node configuration, the identifier parity is computed and sent automatically. In master node and slave node configuration, the parity is checked automatically. 1: Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked. CHKDIS: Checksum Disable 0: In master node configuration, the checksum is computed and sent automatically. In slave node configuration, the checksum is checked automatically. 1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked. CHKTYP: Checksum Type 0: LIN 2.0 “enhanced” checksum 1: LIN 1.3 “classic” checksum DLM: Data Length Mode 0: The response data length is defined by field DLC of this register. 1: The response data length is defined by bits 5 and 6 of the identifier (IDCHR in US_LINIR). FSDIS: Frame Slot Mode Disable 0: The Frame slot mode is enabled. 1: The Frame slot mode is disabled. DS60001517A-page 816  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 WKUPTYP: Wakeup Signal Type 0: Setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: Setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. DLC: Data Length Control 0–255: Defines the response data length if DLM = 0,in that case the response data length is equal to DLC+1 bytes. PDCM: DMAC Mode 0: The LIN mode register US_LINMR is not written by the DMAC. 1: The LIN mode register US_LINMR (excepting that flag) is written by the DMAC.  2017 Microchip Technology Inc. DS60001517A-page 817 SAM9N12/SAM9CN11/SAM9CN12 39.7.27 USART LIN Identifier Register Name:US_LINIR Address:0xF801C058 (0), 0xF8020058 (1), 0xF8024058 (2), 0xF8028058 (3) Access:Read/Write or Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR This register is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. IDCHR: Identifier Character If USART_MODE = 0xA (master node configuration): IDCHR is Read/Write and its value is the identifier character to be transmitted. If USART_MODE = 0xB (slave node configuration): IDCHR is Read-only and its value is the last identifier character that has been received. DS60001517A-page 818  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.28 USART LIN Baud Rate Register Name:US_LINBRR Address:0xF801C05C (0), 0xF802005C (1), 0xF802405C (2), 0xF802805C (3) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LINFP 16 15 14 13 12 11 10 9 8 3 2 1 0 LINCD 7 6 5 4 LINCD This register is relevant only if USART_MODE = 0xA or 0xB in the USART Mode Register. Returns the baud rate value after the synchronization process completion. LINCD: Clock Divider after Synchronization LINFP: Fractional Part after Synchronization  2017 Microchip Technology Inc. DS60001517A-page 819 SAM9N12/SAM9CN11/SAM9CN12 39.7.29 USART Write Protection Mode Register Name:US_WPMR Address:0xF801C0E4 (0), 0xF80200E4 (1), 0xF80240E4 (2), 0xF80280E4 (3) Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). See Section 39.6.10 ”Register Write Protection” for the list of registers that can be write-protected. WPKEY: Write Protection Key Value 0x555341 Name Description PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. DS60001517A-page 820  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 39.7.30 USART Write Protection Status Register Name:US_WPSR Address:0xF801C0E8 (0), 0xF80200E8 (1), 0xF80240E8 (2), 0xF80280E8 (3) Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the US_WPSR. 1: A write protection violation has occurred since the last read of the US_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.  2017 Microchip Technology Inc. DS60001517A-page 821 SAM9N12/SAM9CN11/SAM9CN12 40. Universal Asynchronous Receiver Transmitter (UART) 40.1 Description The Universal Asynchronous Receiver Transmitter (UART) features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. Moreover, the association with a DMA controller permits packet handling for these tasks with processor time reduced to a minimum. 40.2 Embedded Characteristics • Two-pin UART - Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Interrupt Generation - Support for Two DMA Channels with Connection to Receiver and Transmitter 40.3 Block Diagram Figure 40-1: UART Block Diagram UART UTXD Transmit DMA Controller Parallel Input/ Output Baud Rate Generator Receive bus clock URXD Bridge APB Interrupt Control PMC Table 40-1: uart_irq peripheral clock UART Pin Description Pin Name Description Type URXD UART Receive Data Input UTXD UART Transmit Data Output DS60001517A-page 822  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 40.4 40.4.1 Product Dependencies I/O Lines The UART pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Controller to enable I/O line operations of the UART. Table 40-2: 40.4.2 I/O Lines Instance Signal I/O Line Peripheral UART0 URXD0 PC9 C UART0 UTXD0 PC8 C UART1 URXD1 PC17 C UART1 UTXD1 PC16 C Power Management The UART clock can be controlled through the Power Management Controller (PMC). In this case, the user must first configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1. 40.4.3 Interrupt Sources The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling requires programming of the Interrupt Controller before configuring the UART. Table 40-3: 40.5 Peripheral IDs Instance ID UART0 15 UART1 16 Functional Description The UART operates in Asynchronous mode only and supports only 8-bit character handling (with parity). It has no clock pin. The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART. 40.5.1 Baud Rate Generator The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the peripheral clock divided by 16 times the clock divisor (CD) value written in the Baud Rate Generator register (UART_BRGR). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains inactive. The maximum allowable baud rate is peripheral clock divided by 16. The minimum allowable baud rate is peripheral clock divided by (16 x 65536). Figure 40-2: Baud Rate Generator CD CD peripheral clock 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock  2017 Microchip Technology Inc. DS60001517A-page 823 SAM9N12/SAM9CN11/SAM9CN12 40.5.2 40.5.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the Control Register (UART_CR) with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The receiver can be put in reset state by writing UART_CR with the bit RSTRX at 1. In this case, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 40.5.2.2 Start Detection and Data Sampling The UART only supports asynchronous operations, and this affects only its receiver. The UART receiver detects the start of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on URXD is interpreted as a valid start bit if it is detected for more than seven cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after detecting the falling edge of the start bit. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Figure 40-3: Start Bit Detection URXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA Figure 40-4: Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period URXD Sampling 40.5.2.3 D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit Receiver Ready When a complete character is received, it is transferred to the Receive Holding Register (UART_RHR) and the RXRDY status bit in the Status Register (UART_SR) is set. The bit RXRDY is automatically cleared when UART_RHR is read. DS60001517A-page 824  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 40-5: Receiver Ready S URXD D0 D1 D2 D3 D4 D5 D6 D7 D0 S P D1 D2 D3 D4 D5 D6 D7 P RXRDY Read UART_RHR 40.5.2.4 Receiver Overrun The OVRE status bit in UART_SR is set if UART_RHR has not been read by the software (or the DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received. OVRE is cleared when the software writes a 1 to the bit RSTSTA (Reset Status) in UART_CR. Figure 40-6: Receiver Overrun S URXD D0 D1 D2 D3 D4 D5 D6 D7 P stop D0 S D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 40.5.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in the Mode Register (UART_MR). It then compares the result with the received parity bit. If different, the parity error bit PARE in UART_SR is set at the same time RXRDY is set. The parity bit is cleared when UART_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 40-7: URXD Parity Error S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit 40.5.2.6 RSTSTA Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until the Control Register (UART_CR) is written with the bit RSTSTA at 1.  2017 Microchip Technology Inc. DS60001517A-page 825 SAM9N12/SAM9CN11/SAM9CN12 Figure 40-8: URXD Receiver Framing Error S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 40.5.3 40.5.3.1 RSTSTA Transmitter Transmitter Reset, Enable and Disable After device reset, the UART transmitter is disabled and must be enabled before being used. The transmitter is enabled by writing UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register (UART_THR) before actually starting the transmission. The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the internal shift register and/or a character has been written in the UART_THR, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 40.5.3.2 Transmit Format The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the format defined in UART_MR and the data stored in the internal shift register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the following figure. The field PARE in UART_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 40-9: Character Transmission Example: Parity enabled Baud Rate Clock UTXD Start Bit 40.5.3.3 D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in UART_SR. The transmission starts when the programmer writes in the UART_THR, and after the written character is transferred from UART_THR to the internal shift register. The TXRDY bit remains high until a second character is written in UART_THR. As soon as the first character is completed, the last character written in UART_THR is transferred into the internal shift register and TXRDY rises again, showing that the holding register is empty. When both the internal shift register and UART_THR are empty, i.e., all the characters written in UART_THR have been processed, the TXEMPTY bit rises after the last stop bit has been completed. DS60001517A-page 826  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 40-10: Transmitter Control UART_THR Data 0 Data 1 Shift Register UTXD Data 0 Data 0 S Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in UART_THR 40.5.4 Write Data 1 in UART_THR DMA Support Both the receiver and the transmitter of the UART are connected to a DMA Controller (DMAC) channel. The DMA Controller channels are programmed via registers that are mapped within the DMAC user interface. 40.5.5 Test Modes The UART supports three test modes. These modes of operation are programmed by using the CHMODE field in UART_MR. The Automatic echo mode allows a bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to the UTXD line. The transmitter operates normally, but has no effect on the UTXD line. The Local loopback mode allows the transmitted characters to be received. UTXD and URXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no effect and the UTXD line is held high, as in idle state. The Remote loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.  2017 Microchip Technology Inc. DS60001517A-page 827 SAM9N12/SAM9CN11/SAM9CN12 Figure 40-11: Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback TXD VDD Disabled RXD Receiver Disabled Transmitter DS60001517A-page 828 TXD  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 40.6 Universal Asynchronous Receiver Transmitter (UART) User Interface Table 40-4: Register Mapping Offset Register Name Access Reset 0x0000 Control Register UART_CR Write-only – 0x0004 Mode Register UART_MR Read/Write 0x0 0x0008 Interrupt Enable Register UART_IER Write-only – 0x000C Interrupt Disable Register UART_IDR Write-only – 0x0010 Interrupt Mask Register UART_IMR Read-only 0x0 0x0014 Status Register UART_SR Read-only – 0x0018 Receive Holding Register UART_RHR Read-only 0x0 0x001C Transmit Holding Register UART_THR Write-only – 0x0020 Baud Rate Generator Register UART_BRGR Read/Write 0x0 0x0024 Reserved – – – 0x0028–0x003C Reserved – – – 0x0040–0x00E8 Reserved – – – 0x00EC–0x00FC Reserved – – –  2017 Microchip Technology Inc. DS60001517A-page 829 SAM9N12/SAM9CN11/SAM9CN12 40.6.1 UART Control Register Name:UART_CR Address:0xF8040000 (0), 0xF8044000 (1) Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted. RSTTX: Reset Transmitter 0: No effect. 1: The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. RXEN: Receiver Enable 0: No effect. 1: The receiver is enabled if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. TXEN: Transmitter Enable 0: No effect. 1: The transmitter is enabled if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. RSTSTA: Reset Status 0: No effect. 1: Resets the status bits PARE, FRAME and OVRE in the UART_SR. DS60001517A-page 830  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 40.6.2 UART Mode Register Name:UART_MR Address:0xF8040004 (0), 0xF8044004 (1) Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 14 13 12 11 10 9 – – 15 CHMODE 8 – PAR 7 6 5 4 3 2 1 0 – – – – – – – – PAR: Parity Type Value Name Description 0 EVEN Even Parity 1 ODD Odd Parity 2 SPACE Space: parity forced to 0 3 MARK Mark: parity forced to 1 4 NO No parity CHMODE: Channel Mode Value Name Description 0 NORMAL Normal mode 1 AUTOMATIC Automatic echo 2 LOCAL_LOOPBACK Local loopback 3 REMOTE_LOOPBACK Remote loopback  2017 Microchip Technology Inc. DS60001517A-page 831 SAM9N12/SAM9CN11/SAM9CN12 40.6.3 UART Interrupt Enable Register Name:UART_IER Address:0xF8040008 (0), 0xF8044008 (1) Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. RXRDY: Enable RXRDY Interrupt TXRDY: Enable TXRDY Interrupt OVRE: Enable Overrun Error Interrupt FRAME: Enable Framing Error Interrupt PARE: Enable Parity Error Interrupt TXEMPTY: Enable TXEMPTY Interrupt DS60001517A-page 832  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 40.6.4 UART Interrupt Disable Register Name:UART_IDR Address:0xF804000C (0), 0xF804400C (1) Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. RXRDY: Disable RXRDY Interrupt TXRDY: Disable TXRDY Interrupt OVRE: Disable Overrun Error Interrupt FRAME: Disable Framing Error Interrupt PARE: Disable Parity Error Interrupt TXEMPTY: Disable TXEMPTY Interrupt  2017 Microchip Technology Inc. DS60001517A-page 833 SAM9N12/SAM9CN11/SAM9CN12 40.6.5 UART Interrupt Mask Register Name:UART_IMR Address:0xF8040010 (0), 0xF8044010 (1) Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. RXRDY: Mask RXRDY Interrupt TXRDY: Disable TXRDY Interrupt OVRE: Mask Overrun Error Interrupt FRAME: Mask Framing Error Interrupt PARE: Mask Parity Error Interrupt TXEMPTY: Mask TXEMPTY Interrupt DS60001517A-page 834  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 40.6.6 UART Status Register Name:UART_SR Address:0xF8040014 (0), 0xF8044014 (1) Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE – – – TXRDY RXRDY RXRDY: Receiver Ready 0: No character has been received since the last read of the UART_RHR, or the receiver is disabled. 1: At least one complete character has been received, transferred to UART_RHR and not yet read. TXRDY: Transmitter Ready 0: A character has been written to UART_THR and not yet transferred to the internal shift register, or the transmitter is disabled. 1: There is no character written to UART_THR not yet transferred to the internal shift register. OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. FRAME: Framing Error 0: No framing error has occurred since the last RSTSTA. 1: At least one framing error has occurred since the last RSTSTA. PARE: Parity Error 0: No parity error has occurred since the last RSTSTA. 1: At least one parity error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty 0: There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1: There are no characters in UART_THR and there are no characters being processed by the transmitter.  2017 Microchip Technology Inc. DS60001517A-page 835 SAM9N12/SAM9CN11/SAM9CN12 40.6.7 UART Receiver Holding Register Name:UART_RHR Address:0xF8040018 (0), 0xF8044018 (1) Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last received character if RXRDY is set. DS60001517A-page 836  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 40.6.8 UART Transmit Holding Register Name:UART_THR Address:0xF804001C (0), 0xF804401C (1) Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.  2017 Microchip Technology Inc. DS60001517A-page 837 SAM9N12/SAM9CN11/SAM9CN12 40.6.9 UART Baud Rate Generator Register Name:UART_BRGR Address:0xF8040020 (0), 0xF8044020 (1) Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD CD: Clock Divisor 0: Baud rate clock is disabled 1 to 65,535: f peripheral clock CD = ------------------------------------16 × Baud Rate DS60001517A-page 838  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41. Analog-to-Digital Converter (ADC) 41.1 Description The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to Figure 41-1 “Analog-to-Digital Converter Block Diagram with Touchscreen Mode”. It also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions of 12 analog lines. The conversions extend from 0V to the voltage carried on pin ADVREF. The ADC digital controller embeds circuitry to reduce the resolution down to 8 bits. The 8-bit resolution mode prevents using 16-bit Peripheral DMA transfer into memory when only 8-bit resolution is required by the application. Note that using this low resolution mode does not increase the conversion rate. Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given range or outside the range, thresholds and ranges being fully configurable. The ADC also integrates a Sleep mode and a conversion sequencer and connects with a DMA channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as startup time and tracking time. This ADC Controller includes a Resistive Touchscreen Controller. It supports 4-wire and 5-wire technologies. 41.2 • • • • • • • • • • • • • • Embedded Characteristics 10-bit Resolution 300 sps Conversion Rate Wide Range of Power Supply Operation Resistive 4-wire and 5-wire Touchscreen Controller - Position and Pressure Measurement for 4-wire Screens - Position Measurement for 5-wire Screens - Average of Up to 8 Measures for Noise Filtering Programmable Pen Detection Sensitivity Integrated Multiplexer Offering Up to 12 Independent Analog Inputs Individual Enable and Disable of Each Channel Hardware or Software Trigger - External Trigger Pin - Internal Trigger Counter - Trigger on Pen Contact Detection DMA Support Possibility of ADC Timings Configuration Two Sleep Modes and Conversion Sequencer - Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels - Possibility of Customized Channel Sequence Standby Mode for Fast Wakeup Time Response - Power Down Capability Automatic Window Comparison of Converted Values Register Write Protection  2017 Microchip Technology Inc. DS60001517A-page 839 SAM9N12/SAM9CN11/SAM9CN12 41.3 Block Diagram Figure 41-1: Analog-to-Digital Converter Block Diagram with Touchscreen Mode ADC Controller Periodic Trigger Trigger Selection ADTRG ADC Interrupt Control Logic Interrupt Controller ADC cell VDDANA ADCCLK ADVREF System Bus Touchscreen Analog Inputs AD0/XP/UL 0 AD1/XM/UR 1 Touchscreen Switches AD2/YP/LL 2 AD3/YM/Sense 3 AD4/LR 4 PIO AD- Other Analog Inputs DMA Peripheral Bridge Successive Approximation Register Analog-to-Digital Converter User Interface Bus Clock APB AD- PMC Peripheral Clock CHx AD- GND 41.4 Signal Description Table 41-1: ADC Pin Description Pin Name Description VDDANA Analog power supply ADVREF Reference voltage AD0–AD11 Analog input channels ADTRG External trigger DS60001517A-page 840  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.5 Product Dependencies 41.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller peripheral clock in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 41.5.2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADC interrupt requires the interrupt controller to be programmed first. Table 41-2: Peripheral IDs Instance ID ADC 19 41.5.3 I/O Lines The digital input ADC_ADTRG is multiplexed with digital functions on the I/O line and the selection of ADC_ADTRG is made using the PIO controller. The analog inputs ADC_ADx are multiplexed with digital functions on the I/O lines. ADC_ADx inputs are selected as inputs of the ADCC when writing a one in the corresponding CHx bit of ADC_CHER and the digital functions are not selected. Table 41-3: 41.5.4 I/O Lines Instance Signal I/O Line Peripheral ADC ADTRG PB18 B ADC AD0 PB11 X1 ADC AD1 PB12 X1 ADC AD2 PB13 X1 ADC AD3 PB14 X1 ADC AD4 PB15 X1 ADC AD5 PB16 X1 ADC AD6 PB17 X1 ADC AD7 PB6 X1 ADC AD8 PB7 X1 ADC AD9 PB8 X1 ADC AD10 PB9 X1 ADC AD11 PB10 X1 Timer Triggers Timer counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be unconnected. 41.5.5 Conversion Performances For performance and electrical characteristics of the ADC, see the section ‘Electrical Characteristics’.  2017 Microchip Technology Inc. DS60001517A-page 841 SAM9N12/SAM9CN11/SAM9CN12 41.6 41.6.1 Functional Description Analog-to-Digital Conversion ADC conversions are sequenced by two operating times: the tracking time and the conversion time. • The tracking time represents the time between the channel selection change and the time for the controller to start the ADC. The tracking time is set using the TRACKTIM field of the Mode Register (ADC_MR). • The conversion time represents the time for the ADC to convert the analog signal. In order to guarantee a conversion with minimum error, after any start of conversion, the ADC controller waits a number of ADC clock cycles (called hold time) before changing the channel selection again (and so starts a new tracking operation). Figure 41-2: Sequence of ADC Conversions ADCCLK Trigger event (Hard or Soft) Analog cell IOs ADC_ON ADC_Start ADC_eoc ADC_SEL CH0 LCDR CH1 CH2 CH0 CH1 DRDY Conversion of CH0 Start Up Time (and tracking of CH0) 41.6.2 Tracking of CH1 Conversion of CH1 Tracking of CH2 ADC Clock The ADC uses the ADC clock (ADCCLK) to perform conversions. The ADC clock frequency is selected in the PRESCAL field of ADC_MR. The ADC clock frequency is between fperipheral clock/2, if PRESCAL is 0, and fperipheral clock/512, if PRESCAL is set to 255 (0xFF). PRESCAL must be programmed to provide the ADC clock frequency parameter given in the section ‘Electrical Characteristics’. 41.6.3 ADC Reference Voltage The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 41.6.4 Conversion Resolution The ADC analog cell features a 10-bit resolution. The ADC digital controller embeds circuitry to reduce the resolution down to 8 bits. The 8-bit selection is performed by setting the LOWRES bit in ADC_MR. By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the LOWRES bit, the ADC switches to the lowest resolution and the conversion results can be read in the lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding Channel Data register (ADC_CDR) and of the LDATA field in the Last Converted Data register (ADC_LCDR) read 0. DS60001517A-page 842  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.6.5 Conversion Results When a conversion is completed, the resulting digital value is stored in the Channel Data register (ADC_CDRx) of the current channel and in the ADC Last Converted Data register (ADC_LCDR). By setting the TAG option in the Extended Mode Register (ADC_EMR), ADC_LCDR presents the channel number associated with the last converted data in the CHNB field. The channel EOC bit and the DRDY bit in the Interrupt Status register (ADC_ISR) are set. In the case of a connected DMA channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDRx clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit. Figure 41-3: EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_ISR) DRDY (ADC_ISR) If ADC_CDR is not read before further incoming data is converted, the corresponding OVREx flag is set in the Overrun Status register (ADC_OVER). New data converted when DRDY is high sets the GOVRE bit in ADC_ISR. The OVREx flag is automatically cleared when ADC_OVER is read, and the GOVRE flag is automatically cleared when ADC_ISR is read.  2017 Microchip Technology Inc. DS60001517A-page 843 SAM9N12/SAM9CN11/SAM9CN12 Figure 41-4: EOCx, OVREx and GOVREx Flag Behavior Trigger event CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR Undefined Data ADC_CDR0 Undefined Data ADC_CDR1 EOC0 (ADC_ISR) EOC1 (ADC_ISR) GOVRE (ADC_ISR) Data B Data A Data C Data A Undefined Data Data C Data B Conversion A Read ADC_CDR0 Conversion C Conversion B Read ADC_CDR1 Read ADC_ISR DRDY (ADC_ISR) Read ADC_OVER OVRE0 (ADC_OVER) OVRE1 (ADC_OVER) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and corresponding EOCx and GOVRE flags in ADC_ISR and OVREx flags in ADC_OVER are unpredictable. 41.6.6 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control register (ADC_CR) with the START bit at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels or the external trigger input of the ADC (ADTRG). The TRGMOD field in the ADC Trigger Register (ADC_TRGR) selects the hardware trigger from the following: • • • • any edge, either rising or falling or both, detected on the external trigger pin ADTRG the Pen Detect, depending on how the PENDET bit is set in the ADC Touchscreen Mode Register (ADC_TSMR) a continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it finishes the current one a periodic trigger, which is defined by programming the TRGPER field in ADC_TRGR The minimum time between two consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQRx, ADC_TSMR. If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a range of two peripheral clock periods to one ADC clock period. DS60001517A-page 844  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 41-5: Hardware Trigger Delay trigger start delay Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a DMA, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. 41.6.7 Sleep Mode and Conversion Sequencer The ADC Sleep mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep mode is selected by setting the SLEEP bit in ADC_MR. Sleep mode is managed by a conversion sequencer, which automatically processes the conversions of all channels at lowest power consumption. This mode can be used when the minimum period of time between two successive trigger events is greater than the startup period of the ADC. See the section ‘ADC Characteristics’ in the ‘Electrical Characteristics’. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a startup time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are ignored. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using the internal timer (ADC_TRGR). The periodic acquisition of several samples can be processed automatically without any intervention of the processor via the DMA. The sequence can be customized by programming the Sequence Channel Register ADC_SEQR1 and setting the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific order of channels and can program up to 12 conversions by sequence. The user is free to create a personal sequence by writing channel numbers in ADC_SEQR1. Not only can channel numbers be written in any sequence, channel numbers can be repeated several times. When the bit USEQ in ADC_MR is set, the fields USCHx in ADC_SEQR1 are used to define the sequence. Only enabled USCHx fields will be part of the sequence. Each USCHx field has a corresponding enable, CHx-1, in ADC_CHER. If all ADC channels (i.e., 12) are used on an application board, there is no restriction of usage of the user sequence. However, if some ADC channels are not enabled for conversion but rather used as pure digital inputs, the respective indexes of these channels cannot be used in the user sequence fields (see ADC_SEQRx). For example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQRx fields USCH1 up to USCH12 must not contain the value 4. Thus the length of the user sequence may be limited by this behavior. As an example, if only four channels over 12 (CH0 up to CH3) are selected for ADC conversions, the user sequence length cannot exceed four channels. Each trigger event may launch up to four successive conversions of any combination of channels 0 up to 3 but no more (i.e., in this case the sequence CH0, CH0, CH1, CH1, CH1 is impossible). A sequence that repeats the same channel several times requires more enabled channels than channels actually used for conversion. For example, the sequence CH0, CH0, CH1, CH1 requires four enabled channels (four free channels on application boards) whereas only CH0, CH1 are really converted. Note: 41.6.8 The reference voltage pins always remain connected in Normal mode as in Sleep mode. Comparison Window The ADC Controller features automatic comparison functions. It compares converted values to a low threshold, a high threshold or both, depending on the value of the CMPMODE bit in ADC_EMR. The comparison can be done on all channels or only on the channel specified in the CMPSEL field of ADC_EMR. To compare all channels, the CMPALL bit of ADC_EMR must be set. The flag can be read on the COMPE bit of the Interrupt Status register (ADC_ISR) and can trigger an interrupt. The high threshold and the low threshold can be read/write in the Compare Window register (ADC_CWR).  2017 Microchip Technology Inc. DS60001517A-page 845 SAM9N12/SAM9CN11/SAM9CN12 If the comparison window is to be used with the LOWRES bit set in ADC_MR, the thresholds do not need to be adjusted, as the adjustment is done internally. However, whether the LOWRES bit is set or not, thresholds must always be configured in accordance with the maximum ADC resolution. 41.6.9 ADC Timings Each ADC has its own minimal startup time that is programmed through the field STARTUP in ADC_MR. A minimal tracking time is necessary for the ADC to guarantee the best converted final value between two channel selections. This time must be programmed in the TRACKTIM field in ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the TRACKTIM field. See the section ‘ADC Characteristics’ in ‘Electrical Characteristics’. 41.6.10 41.6.10.1 Touchscreen Touchscreen Mode The TSMODE parameter of the ADC Touchscreen Mode Register (ADC_TSMR) is used to enable/disable the touchscreen functionality, to select the type of screen (4-wire or 5-wire) and, in the case of a 4-wire screen and to activate (or not) the pressure measurement. In 4-wire mode, channel 0, 1, 2 and 3 must not be used for classic ADC conversions. Likewise, in 5-wire mode, channel 0, 1, 2, 3, and 4 must not be used for classic ADC conversions. 41.6.10.2 4-wire Resistive Touchscreen Principles A resistive touchscreen is based on two resistive films, each one being fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. In between, there is a layer acting as an insulator, but also enables contact when you press the screen. This is illustrated in Figure 41-6. The ADC controller has the ability to perform without external components: • position measurement • pressure measurement • pen detection Figure 41-6: Touchscreen Position Measurement Pen Contact XP YM YP XM VDD XP YP XP Volt XM Vertical Position Detection DS60001517A-page 846 VDD YP GND Volt YM GND Horizontal Position Detection  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.6.10.3 4-wire Position Measurement Method As shown in Figure 41-6, to detect the position of a contact, a supply is first applied from top to bottom. Due to the linear resistance of the film, there is a voltage gradient from top to bottom. When a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film. If the input impedance on the right and left electrodes sense is high enough, the film does not affect this voltage, despite its resistive nature. For the horizontal direction, the same method is used, but by applying supply from left to right. The range depends on the supply voltage and on the loss in the switches that connect to the top and bottom electrodes. In an ideal world (linear, with no loss through switches), the horizontal position is equal to: VYM / VDD or VYP / VDD. The implementation with on-chip power switches is shown in Figure 41-7. The voltage measurement at the output of the switch compensates for the switches loss. It is possible to correct for switch loss by performing the operation: [VYP - VXM] / [VXP - VXM]. This requires additional measurements, as shown in Figure 41-7. Figure 41-7: Touchscreen Switches Implementation XP VDDANA 0 XM GND 1 To the ADC YP VDDANA 2 YM GND 3 VDDANA VDDANA Switch Resistor Switch Resistor YP XP XP YP YM XM Switch Resistor Switch Resistor GND Horizontal Position Detection  2017 Microchip Technology Inc. GND Vertical Position Detection DS60001517A-page 847 SAM9N12/SAM9CN11/SAM9CN12 41.6.10.4 4-wire Pressure Measurement Method The method to measure the pressure (Rp) applied to the touchscreen is based on the known resistance of the X-Panel resistance (Rxp). Three conversions (Xpos,Z1,Z2) are necessary to determine the value of Rp (Zaxis resistance). Rp = Rxp × (Xpos/1024) × [(Z2/Z1)-1] Figure 41-8: Pressure Measurement VDDANA VDDANA Switch Resistor Switch Resistor XP YP Open circuit Switch Resistor XP YP Rp YM XM Rp YM XM GND XPos Measure(Yp) YM XM Open circuit Switch Resistor Switch Resistor Open circuit XP YP Rp 41.6.10.5 VDDANA Switch Resistor GND GND Z1 Measure(Xp) Z2 Measure(Xp) 5-wire Resistive Touchscreen Principles To make a 5-wire touchscreen, a resistive layer with a contact point at each corner and a conductive layer are used. The 5-wire touchscreen differs from the 4-wire type mainly in that the voltage gradient is applied only to one layer, the resistive layer, while the other layer is the sense layer for both measurements. The measurement of the X position is obtained by biasing the upper left corner and lower left corner to VDDANA and the upper right corner and lower right to ground. To measure along the Y axis, bias the upper left corner and upper right corner to VDDANA and bias the lower left corner and lower right corner to ground. DS60001517A-page 848  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 41-9: 5-Wire Principle UL Pen Contact Resistive layer UR Sense LL LR Conductive Layer UL VDDANA UR VDDANA for Yp GND for Xp Sense LL VDDANA for Xp GND for Yp 41.6.10.6 LR GND 5-wire Position Measurement Method In an application only monitoring clicks, 100 points per second is typically needed. For handwriting or motion detection, the number of measurements to consider is approximately 200 points per second. This must take into account that multiple measurements are included (over sampling, filtering) to compute the correct point. The 5-wire touchscreen panel works by applying a voltage at the corners of the resistive layer and measuring the vertical or horizontal resistive network with the sense input. The ADC converts the voltage measured at the point the panel is touched. A measurement of the Y position of the pointing device is made by: • Connecting Upper left (UL) and upper right (UR) corners to VDDANA • Connecting Lower left (LL) and lower right (LR) corners to ground. • The voltage measured is determined by the voltage divider developed at the point of touch (Yposition) and the SENSE input is converted by ADC. A measurement of the X position of the pointing device is made by: • Connecting the upper left (UL) and lower left (LL) corners to ground • Connecting the upper right and lower right corners to VDDANA. • The voltage measured is determined by the voltage divider developed at the point of touch (Xposition) and the SENSE input is converted by ADC.  2017 Microchip Technology Inc. DS60001517A-page 849 SAM9N12/SAM9CN11/SAM9CN12 Figure 41-10: Touchscreen Switches Implementation UL VDDANA 0 UR GND VDDANA 1 GND LL VDDANA Sense LR UL VDDANA 2 To the ADC 3 GND 4 UR VDDANA for Ypos GND for Xpos Sense LL 41.6.10.7 VDDANA for Xpos GND for Ypos LR GND Sequence and Noise Filtering The ADC Controller can manage ADC conversions and touchscreen measurement. On each trigger event the sequence of ADC conversions is performed as described in Section 41.6.7 “Sleep Mode and Conversion Sequencer”. The touchscreen measure frequency can be specified in number of trigger events by writing the TSFREQ parameter in ADC_TSMR. An internal counter counts triggers up to TSFREQ, and every time it rolls out, a touchscreen sequence is appended to the classic ADC conversion sequence (see Figure 41-11). Additionally the user can average multiple touchscreen measures by writing the TSAV parameter in ADC_TSMR. This can be 1, 2, 4 or 8 measures performed on consecutive triggers as illustrated in Figure 41-11 below. Consequently, the TSFREQ parameter must be greater or equal to the TSAV parameter. DS60001517A-page 850  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 41-11: Insertion of Touchscreen Sequences (TSFREQ = 2; TSAV = 1) Trigger event ADC_SEL C T C T C C C C: Classic ADC Conversion Sequence - T C T C T: Touchscreen Sequence XRDY Read the ADC_XPOSR Read the ADC_XPOSR YRDY Note: 41.6.10.8 ADC_SEL: Command to the ADC analog cell Read the ADC_YPOSR Read the ADC_YPOSR Measured Values, Registers and Flags As soon as the controller finishes the Touchscreen sequence, XRDY, YRDY and PRDY are set and can generate an interrupt. These flags can be read in the ADC Interrupt Status register (ADC_ISR). They are reset independently by reading in the ADC Touchscreen X Position register (ADC_XPOSR), the ADC Touchscreen Y Position register (ADC_YPOSR) and the ADC Touchscreen Pressure register (ADC_PRESSR). ADC_XPOSR presents XPOS (VX - VXmin) on its LSB and XSCALE (VXMAX - VXmin) aligned on the 16th bit. ADC_YPOSR presents YPOS (VY - VYmin) on its LSB and YSCALE (VYMAX - VYmin) aligned on the 16th bit. To improve the quality of the measure, the user must calculate XPOS/XSCALE and YPOS/YSCALE. VXMAX, VXmin, VYMAX, and VYmin are measured at the first start up of the controller. These values can change during use, so it can be necessary to refresh them. Refresh can be done by writing ‘1’ in the TSCALIB field of the control register (ADC_CR). ADC_PRESSR presents Z1 on its LSB and Z2 aligned on the 16th bit. See Section 41.6.10.4 “4-wire Pressure Measurement Method”. 41.6.10.9 Pen Detect Method When there is no contact, it is not necessary to perform a conversion. However, it is important to detect a contact by keeping the power consumption as low as possible. The implementation polarizes one panel by closing the switch on (XP/UL) and ties the horizontal panel by an embedded resistor connected to YM / Sense. This resistor is enabled by a fifth switch. Since there is no contact, no current is flowing and there is no related power consumption. As soon as a contact occurs, a current is flowing in the Touchscreen and a Schmitt trigger detects the voltage in the resistor. The Touchscreen Interrupt configuration is entered by programming the PENDET bit in ADC_TSMR. If this bit is written at 1, the controller samples the pen contact state when it is not converting and waiting for a trigger. To complete the circuit, a programmable debouncer is placed at the output of the Schmitt trigger. This debouncer is programmable up to 215 ADC clock periods. The debouncer length can be selected by programming the field PENDBC in ADC_TSMR. Due to the analog switch’s structure, the debouncer circuitry is only active when no conversion (touchscreen or classic ADC channels) is in progress. Thus, if the time between the end of a conversion sequence and the arrival of the next trigger event is lower than the debouncing time configured on PENDBC, the debouncer will not detect any contact.  2017 Microchip Technology Inc. DS60001517A-page 851 SAM9N12/SAM9CN11/SAM9CN12 Figure 41-12: Touchscreen Pen Detect X+/UL VDDANA 0 X-/UR GND VDDANA 1 GND Y+/LL Y-/SENSE LR VDDANA GND GND 2 To the ADC 3 4 PENDBC Debouncer Pen Interrupt GND The touchscreen pen detect can be used to generate an ADC interrupt to wake up the system. The pen detect generates two types of status, reported in ADC_ISR: • the PEN bit is set as soon as a contact exceeds the debouncing time as defined by PENDBC and remains set until ADC_ISR is read. • the NOPEN bit is set as soon as no current flows for a time over the debouncing time as defined by PENDBC and remains set until ADC_ISR is read. Both bits are automatically cleared as soon as ADC_ISR is read, and can generate an interrupt by writing ADC_IER. Moreover, the rising of either one of them clears the other, they cannot be set at the same time. The PENS bit of ADC_ISR shows the current status of the pen contact. 41.6.11 Buffer Structure The DMA read channel is triggered each time a new data is stored in ADC_LCDR. The same structure of data is repeatedly stored in ADC_LCDR each time a trigger event occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_TSMR) the structure differs. Each data read to DMA buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR, the four most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better checking the DMA buffer integrity. DS60001517A-page 852  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 41-13: Buffer Structure Assuming ADC_CHSR = 0x000_01600 ADC_EMR(TAG) = 1 trig.event1 DMA Buffer Structure trig.event2 Assuming ADC_CHSR = 0x000_01600 ADC_EMR(TAG) = 0 5 ADC_CDR5 DMA Transfer Base Address (BA) 6 ADC_CDR6 BA + 0x02 8 ADC_CDR8 BA + 0x04 5 ADC_CDR5 6 trig.event1 0 ADC_CDR5 0 ADC_CDR6 0 ADC_CDR8 BA + 0x06 0 ADC_CDR5 ADC_CDR6 BA + 0x08 0 ADC_CDR6 8 ADC_CDR8 BA + 0x0A 0 ADC_CDR8 5 ADC_CDR5 BA + [(N-1) * 6] 0 ADC_CDR5 6 ADC_CDR6 BA + [(N-1) * 6]+ 0x02 0 ADC_CDR6 8 ADC_CDR8 BA + [(N-1) * 6]+ 0x04 0 ADC_CDR8 DMA Buffer Structure trig.event2 trig.eventN trig.eventN As soon as touchscreen conversions are required, the pen detection function may help the post-processing of the buffer. Refer to Section 41.6.11.4 “Pen Detection Status”. 41.6.11.1 Classical ADC Channels Only When no touchscreen conversion is required (i.e., TSMODE = 0 in ADC_TSMR), the structure of data within the buffer is defined by ADC_MR, ADC_CHSR, ADC_SEQRx. See Figure 41-13. If the user sequence is not used (i.e., USEQ is cleared in ADC_MR) then only the value of ADC_CHSR defines the data structure. For each trigger event, enabled channels will be consecutively stored in ADC_LCDR and automatically read to the buffer. When the user sequence is configured (i.e., USEQ is set in ADC_MR) not only does ADC_CHSR modify the data structure of the buffer, but ADC_SEQRx registers may modify the data structure of the buffer as well. 41.6.11.2 Touchscreen Channels Only When only touchscreen conversions are required (i.e., TSMODE ≠ 0 in ADC_TSMR and ADC_CHSR equals 0), the structure of data within the buffer is defined by ADC_TSMR. When TSMODE = 1 or 3, each trigger event adds two half-words in the buffer (assuming TSAV = 0), first half-word being XPOS of ADC_XPOSR then YPOS of ADC_YPOSR. If TSAV/TSFREQ ≠ 0, the data structure remains unchanged. Not all trigger events add data to the buffer. When TSMODE = 2, each trigger event adds four half-words to the buffer (assuming TSAV = 0), first half-word being XPOS of ADC_XPOSR followed by YPOS of ADC_YPOSR and finally Z1 followed by Z2, both located in ADC_PRESSR. When TAG is set (ADC_EMR), the CHNB field (four most significant bits of ADC_LCDR) is cleared when XPOS is transmitted and set when YPOS is transmitted, allowing an easier post-processing of the buffer or a better checking of the buffer integrity. In case 4-wire with Pressure mode is selected, Z1 value is transmitted to the buffer along with tag set to 2 and Z2 is tagged with value 3. XSCALE and YSCALE (calibration values) are not transmitted to the buffer because they are supposed to be constant and moreover only measured at the very first start up of the controller or upon user request. There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR but it is recommended to use the pen detection function for buffer post-processing (refer to Section 41.6.11.4 “Pen Detection Status”).  2017 Microchip Technology Inc. DS60001517A-page 853 SAM9N12/SAM9CN11/SAM9CN12 Figure 41-14: Buffer Structure When Only Touchscreen Channels are Enabled Assuming ADC_TSMR(TSMOD) = 1 or 3 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1 trig.event1 DMA Buffer Structure trig.event2 0 1 ADC_XPOSR DMA Transfer Base Address (BA) ADC_YPOSR BA + 0x02 0 ADC_XPOSR BA + 0x04 1 ADC_YPOSR BA + 0x06 0 ADC_XPOSR BA + [(N-1) * 4] trig.eventN 1 ADC_YPOSR DMA Buffer Structure trig.event2 DMA Buffer Structure trig.event2 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_XPOSR 0 ADC_YPOSR trig.eventN Assuming ADC_TSMR(TSMOD) = 2 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0 0 ADC_XPOSR trig.event1 DMA Transfer Base Address (BA) 0 ADC_XPOSR 1 ADC_YPOSR BA + 0x02 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + 0x04 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + 0x06 0 ADC_PRESSR(Z2) 0 ADC_XPOSR BA + 0x08 0 ADC_XPOSR 1 ADC_YPOSR BA + 0x0A 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + 0x0C 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + 0x0E 0 ADC_PRESSR(Z2) 0 ADC_XPOSR BA + [(N-1) * 8] 0 ADC_XPOSR 1 ADC_YPOSR 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + [(N-1) * 8]+ 0x04 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + [(N-1) * 8]+ 0x06 0 ADC_PRESSR(Z2) DMA Buffer Structure trig.event2 trig.eventN 41.6.11.3 trig.event1 BA + [(N-1) * 4]+ 0x02 Assuming ADC_TSMR(TSMOD) = 2 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1 trig.event1 Assuming ADC_TSMR(TSMOD) =1 or 3 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0 trig.eventN BA + [(N-1) * 8]+ 0x02 Interleaved Channels When both classic ADC channels (CH4/CH5 up to CH12 are set in ADC_CHSR) and touchscreen conversions are required (TSMODE ≠ 0 in ADC_TSMR) the structure of the buffer differs according to TSAV and TSFREQ values. If TSFREQ ≠ 0, not all events generate touchscreen conversions, therefore the buffer structure is based on 2TSFREQ trigger events. Given a TSFREQ value, the location of touchscreen conversion results depends on TSAV value. When TSFREQ = 0, TSAV must equal 0. There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR but it is recommended to use the pen detection function for buffer post-processing (refer to Section 41.6.11.4 “Pen Detection Status”). DS60001517A-page 854  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 41-15: Buffer Structure When Classic ADC and Touchscreen Channels are Interleaved Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100, ADC_EMR(TAG) =1 trig.event1 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 8 DMA Buffer Structure trig.event2 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100, ADC_EMR(TAG) = 0 trig.event1 DMA Buffer Structure trig.event2 8 0 ADC_CDR8 BA + 0x06 ADC_XPOSR BA + 0x08 BA + 0x0A 1 ADC_YPOSR 8 ADC_CDR8 BA + [(N-1) * 6] ADC_XPOSR BA + [(N-1) * 6]+ 0x02 ADC_YPOSR BA + [(N-1) * 6]+ 0x04 trig.eventN ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR trig.eventN 0 1 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = 0 ADC_TSMR(TSFREQ) = 1 ADC_CHSR = 0x000_0100, ADC_EMR(TAG) = 1 trig.event1 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 8 ADC_CDR8 BA + 0x06 8 ADC_CDR8 BA + 0x08 0 ADC_XPOSR BA + 0x0A 1 ADC_YPOSR BA + 0x0c 8 ADC_CDR8 BA + 0x0e 8 ADC_CDR8 BA + [(N-1) * 8] ADC_XPOSR BA + [(N-1) * 8]+ 0x02 1 ADC_YPOSR BA + [(N-1) * 8]+ 0x04 8 ADC_CDR8 BA + [(N-1) * 8]+ 0x06 8 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = 1 ADC_TSMR(TSFREQ) = 1 ADC_CHSR = 0x000_0100, ADC_EMR(TAG) = 1 trig.event1 trig.event2 DMA Buffer Structure trig.event2 trig.event3 trig.event4 trig.eventN DMA Buffer Structure 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR trig.event3 trig.event4 trig.eventN 0 trig.eventN+1 41.6.11.4 0 trig.eventN+1 Pen Detection Status If the pen detection measure is enabled (PENDET is set in ADC_TSMR), the XPOS, YPOS, Z1, Z2 values transmitted to the buffer through ADC_LCDR are cleared (including the CHNB field), if the PENS flag of ADC_ISR is 0. When the PENS flag is set, XPOS, YPOS, Z1, Z2 are normally transmitted. Therefore, using pen detection together with tag function eases the post-processing of the buffer, especially to determine which touchscreen converted values correspond to a period of time when the pen was in contact with the screen.  2017 Microchip Technology Inc. DS60001517A-page 855 SAM9N12/SAM9CN11/SAM9CN12 When the pen detection is disabled or the tag function is disabled, XPOS, YPOS, Z1, Z2 are normally transmitted without tag and no relationship can be found with pen status, thus post-processing may not be easy. Figure 41-16: Buffer Structure With and Without Pen Detection Enabled Assuming ADC_TSMR(TSMOD) = 1, PENDET = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100, ADC_EMR(TAG) = 1 PENS = 1 8 DMA buffer Structure trig.event2 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 8 0 ADC_CDR8 BA + 0x06 ADC_XPOSR BA + 0x08 trig.event1 DMA buffer Structure PENS = 1 trig.event1 Assuming ADC_TSMR(TSMOD) = 1, PENDET = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100, ADC_EMR(TAG) = 0 BA + 0x0A 1 ADC_YPOSR 8 ADC_CDR8 BA + [(N-1) * 6] 0 BA + [(N-1) * 6]+ 0x02 0 0 BA + [(N-1) * 6]+ 0x04 8 ADC_CDR8 0 0 0 0 0 2 successive tags cleared => PENS = 0 41.6.12 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR* 0 ADC_YPOSR* 0 ADC_CDR8 0 ADC_XPOSR* 0 ADC_YPOSR* trig.eventN PENS = 0 PENS = 0 trig.eventN trig.eventN+1 trig.event2 0 ADC_XPOSR*, ADC_YPOSR* can be any value when PENS = 0 Register Write Protection To prevent any single software error from corrupting ADC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the “ADC Write Protection Mode Register” (ADC_WPMR). If a write access to the protected registers is detected, the WPVS flag in the “ADC Write Protection Status Register” (ADC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS flag is automatically reset by reading ADC_WPSR. The following registers can be write-protected: • • • • • • • • • ADC Mode Register ADC Channel Sequence 1 Register ADC Channel Enable Register ADC Channel Disable Register ADC Extended Mode Register ADC Compare Window Register ADC Analog Control Register ADC Touchscreen Mode Register ADC Trigger Register DS60001517A-page 856  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7 Analog-to-Digital (ADC) User Interface Table 41-4: Offset Register Mapping Register Name Access Reset 0x00 Control Register ADC_CR Write-only – 0x04 Mode Register ADC_MR Read/Write 0x00000000 0x08 Channel Sequence Register 1 ADC_SEQR1 Read/Write 0x00000000 0x0C Reserved – – – 0x10 Channel Enable Register ADC_CHER Write-only – 0x14 Channel Disable Register ADC_CHDR Write-only – 0x18 Channel Status Register ADC_CHSR Read-only 0x00000000 0x1C Reserved – – – 0x20 Last Converted Data Register ADC_LCDR Read-only 0x00000000 0x24 Interrupt Enable Register ADC_IER Write-only – 0x28 Interrupt Disable Register ADC_IDR Write-only – 0x2C Interrupt Mask Register ADC_IMR Read-only 0x00000000 0x30 Interrupt Status Register ADC_ISR Read-only 0x00000000 0x34 Reserved – – – 0x38 Reserved – – – 0x3C Overrun Status Register ADC_OVER Read-only 0x00000000 0x40 Extended Mode Register ADC_EMR Read/Write 0x00000000 0x44 Compare Window Register ADC_CWR Read/Write 0x00000000 0x50 Channel Data Register 0 ADC_CDR0 Read-only 0x00000000 0x54 Channel Data Register 1 ADC_CDR1 Read-only 0x00000000 ... ... ... ... Channel Data Register 11 ADC_CDR11 Read-only 0x00000000 Reserved – – – Analog Control Register ADC_ACR Read/Write 0x00000100 Reserved – – – 0xB0 Touchscreen Mode Register ADC_TSMR Read/Write 0x00000000 0xB4 Touchscreen X Position Register ADC_XPOSR Read-only 0x00000000 0xB8 Touchscreen Y Position Register ADC_YPOSR Read-only 0x00000000 0xBC Touchscreen Pressure Register ADC_PRESSR Read-only 0x00000000 0xC0 Trigger Register ADC_TRGR Read/Write 0x00000000 Reserved – – – 0xE4 Write Protection Mode Register ADC_WPMR Read/Write 0x00000000 0xE8 Write Protection Status Register ADC_WPSR Read-only 0x00000000 Reserved – – – ... 0x7C 0x80–0x90 0x94 0x98–0xAC 0xC4–0xE0 0xEC–0xFC Note: Any offset not listed in the table must be considered as “reserved”.  2017 Microchip Technology Inc. DS60001517A-page 857 SAM9N12/SAM9CN11/SAM9CN12 41.7.1 ADC Control Register Name:ADC_CR Address:0xF804C000 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TSCALIB 1 START 0 SWRST SWRST: Software Reset 0: No effect. 1: Resets the ADC, simulating a hardware reset. START: Start Conversion 0: No effect. 1: Begins analog-to-digital conversion. TSCALIB: Touchscreen Calibration 0: No effect. 1: Programs screen calibration (VDD/GND measurement) If conversion is in progress, the calibration sequence starts at the beginning of a new conversion sequence. If no conversion is in progress, the calibration sequence starts at the second conversion sequence located after the TSCALIB command (Sleep mode, waiting for a trigger event). TSCALIB measurement sequence does not affect the Last Converted Data Register (ADC_LCDR). DS60001517A-page 858  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.2 ADC Mode Register Name:ADC_MR Address:0xF804C004 Access:Read/Write 31 USEQ 30 – 29 – 28 – 27 23 – 22 – 21 – 20 – 19 15 14 13 12 26 25 24 17 16 TRACKTIM 18 STARTUP 11 10 9 8 3 2 – 1 0 – PRESCAL 7 – 6 – 5 SLEEP 4 LOWRES This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. LOWRES: Resolution Value Name Description 0 BITS_10 10-bit resolution. 1 BITS_8 8-bit resolution SLEEP: Sleep Mode Value Name Description 0 NORMAL Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. 1 SLEEP Sleep Mode: The ADC core and reference voltage circuitry are OFF between conversions. PRESCAL: Prescaler Rate Selection PRESCAL = (fperipheral clock / (2 × fADCCLK)) - 1. STARTUP: Startup Time Value Name Description 0 SUT0 0 periods of ADCCLK 1 SUT8 8 periods of ADCCLK 2 SUT16 16 periods of ADCCLK 3 SUT24 24 periods of ADCCLK 4 SUT64 64 periods of ADCCLK 5 SUT80 80 periods of ADCCLK 6 SUT96 96 periods of ADCCLK 7 SUT112 112 periods of ADCCLK 8 SUT512 512 periods of ADCCLK 9 SUT576 576 periods of ADCCLK 10 SUT640 640 periods of ADCCLK 11 SUT704 704 periods of ADCCLK 12 SUT768 768 periods of ADCCLK  2017 Microchip Technology Inc. DS60001517A-page 859 SAM9N12/SAM9CN11/SAM9CN12 Value Name Description 13 SUT832 832 periods of ADCCLK 14 SUT896 896 periods of ADCCLK 15 SUT960 960 periods of ADCCLK TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) × ADCCLK periods USEQ: Use Sequence Enable Value Name Description 0 NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 1 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert the same channel several times. DS60001517A-page 860  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.3 ADC Channel Sequence 1 Register Name:ADC_SEQR1 Address:0xF804C008 Access:Read/Write 31 30 29 28 27 26 USCH8 23 22 21 20 19 18 USCH6 15 14 13 6 24 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 25 USCH7 USCH3 5 4 3 USCH2 2 USCH1 This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. USCHx: User Sequence Number x The allowed range is 0 up to 11, thus only the sequencer from CH0 to CH11 can be used. This register activates only if the USEQ field in ADC_MR field is set to ‘1’. Any USCHx field is processed only if the CHx-1 it in ADC_CHSR reads logical ‘1’, else any value written in USCHx does not add the corresponding channel in the conversion sequence. Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs. When configuring consecutive fields with the same value, the associated channel is sampled as many time as the number of consecutive values, this part of the conversion sequence being triggered by a unique event.  2017 Microchip Technology Inc. DS60001517A-page 861 SAM9N12/SAM9CN11/SAM9CN12 41.7.4 ADC Channel Enable Register Name:ADC_CHER Address:0xF804C010 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel. Note: If USEQ = 1 in ADC_MR, CHx corresponds to the enable of sequence number x+1 described in ADC_SEQR1 (e.g. CH0 enables sequence number USCH1). DS60001517A-page 862  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.5 ADC Channel Disable Register Name:ADC_CHDR Address:0xF804C014 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and corresponding EOCx and GOVRE flags in ADC_ISR and OVREx flags in ADC_OVER are unpredictable.  2017 Microchip Technology Inc. DS60001517A-page 863 SAM9N12/SAM9CN11/SAM9CN12 41.7.6 ADC Channel Status Register Name:ADC_CHSR Address:0xF804C018 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 CHx: Channel x Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. DS60001517A-page 864  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.7 ADC Last Converted Data Register Name:ADC_LCDR Address:0xF804C020 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. CHNB: Channel Number Indicates the last converted channel when the TAG bit is set in ADC_EMR. If the TAG bit is not set, CHNB = 0.  2017 Microchip Technology Inc. DS60001517A-page 865 SAM9N12/SAM9CN11/SAM9CN12 41.7.8 ADC Interrupt Enable Register Name:ADC_IER Address:0xF804C024 Access:Write-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. EOCx: End of Conversion Interrupt Enable x XRDY: Touchscreen Measure XPOS Ready Interrupt Enable YRDY: Touchscreen Measure YPOS Ready Interrupt Enable PRDY: Touchscreen Measure Pressure Ready Interrupt Enable DRDY: Data Ready Interrupt Enable GOVRE: General Overrun Error Interrupt Enable COMPE: Comparison Event Interrupt Enable PEN: Pen Contact Interrupt Enable NOPEN: No Pen Contact Interrupt Enable DS60001517A-page 866  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.9 ADC Interrupt Disable Register Name:ADC_IDR Address:0xF804C028 Access:Write-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. EOCx: End of Conversion Interrupt Disable x XRDY: Touchscreen Measure XPOS Ready Interrupt Disable YRDY: Touchscreen Measure YPOS Ready Interrupt Disable PRDY: Touchscreen Measure Pressure Ready Interrupt Disable DRDY: Data Ready Interrupt Disable GOVRE: General Overrun Error Interrupt Disable COMPE: Comparison Event Interrupt Disable PEN: Pen Contact Interrupt Disable NOPEN: No Pen Contact Interrupt Disable  2017 Microchip Technology Inc. DS60001517A-page 867 SAM9N12/SAM9CN11/SAM9CN12 41.7.10 ADC Interrupt Mask Register Name:ADC_IMR Address:0xF804C02C Access:Read-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. EOCx: End of Conversion Interrupt Mask x XRDY: Touchscreen Measure XPOS Ready Interrupt Mask YRDY: Touchscreen Measure YPOS Ready Interrupt Mask PRDY: Touchscreen Measure Pressure Ready Interrupt Mask DRDY: Data Ready Interrupt Mask GOVRE: General Overrun Error Interrupt Mask COMPE: Comparison Event Interrupt Mask PEN: Pen Contact Interrupt Mask NOPEN: No Pen Contact Interrupt Mask DS60001517A-page 868  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.11 ADC Interrupt Status Register Name:ADC_ISR Address:0xF804C030 Access:Read-only 31 PENS 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 EOCx: End of Conversion x (automatically set / cleared) 0: The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the corresponding ADC_CDRx registers. 1: The corresponding analog channel is enabled and conversion is complete. XRDY: Touchscreen XPOS Measure Ready (cleared on read) 0: No measure has been performed since the last read of ADC_XPOSR. 1: At least one measure has been performed since the last read of ADC_ISR. YRDY: Touchscreen YPOS Measure Ready (cleared on read) 0: No measure has been performed since the last read of ADC_YPOSR. 1: At least one measure has been performed since the last read of ADC_ISR. PRDY: Touchscreen Pressure Measure Ready (cleared on read) 0: No measure has been performed since the last read of ADC_PRESSR. 1: At least one measure has been performed since the last read of ADC_ISR. DRDY: Data Ready (automatically set / cleared) 0: No data has been converted since the last read of ADC_LCDR. 1: At least one data has been converted and is available in ADC_LCDR. GOVRE: General Overrun Error (cleared on read) 0: No general overrun error occurred since the last read of ADC_ISR. 1: At least one general overrun error has occurred since the last read of ADC_ISR. COMPE: Comparison Event (cleared on read) 0: No comparison event since the last read of ADC_ISR. 1: At least one comparison event (defined in ADC_EMR and ADC_CWR) has occurred since the last read of ADC_ISR. PEN: Pen contact (cleared on read) 0: No pen contact since the last read of ADC_ISR. 1: At least one pen contact since the last read of ADC_ISR. NOPEN: No Pen Contact (cleared on read) 0: No loss of pen contact since the last read of ADC_ISR. 1: At least one loss of pen contact since the last read of ADC_ISR.  2017 Microchip Technology Inc. DS60001517A-page 869 SAM9N12/SAM9CN11/SAM9CN12 PENS: Pen Detect Status 0: The pen does not press the screen. 1: The pen presses the screen. Note: PENS is not a source of interruption. DS60001517A-page 870  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.12 ADC Overrun Status Register Name:ADC_OVER Address:0xF804C03C Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 OVREx: Overrun Error x 0: No overrun error on the corresponding channel since the last read of ADC_OVER. 1: An overrun error has occurred on the corresponding channel since the last read of ADC_OVER.  2017 Microchip Technology Inc. DS60001517A-page 871 SAM9N12/SAM9CN11/SAM9CN12 41.7.13 ADC Extended Mode Register Name:ADC_EMR Address:0xF804C040 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 CMPALL 8 – 7 6 5 4 3 – 2 – 1 0 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. CMPMODE: Comparison Mode Value Name Description 0 LOW Generates an event when the converted data is lower than the low threshold of the window. 1 HIGH Generates an event when the converted data is higher than the high threshold of the window. 2 IN Generates an event when the converted data is in the comparison window. 3 OUT Generates an event when the converted data is out of the comparison window. CMPSEL: Comparison Selected Channel If CMPALL = 0: CMPSEL indicates which channel has to be compared. If CMPALL = 1: No effect. CMPALL: Compare All Channels 0: Only channel indicated in CMPSEL field is compared. 1: All channels are compared. TAG: Tag of ADC_LCDR 0: Sets CHNB field to zero in ADC_LCDR. 1: Appends the channel number to the conversion result in ADC_LCDR. DS60001517A-page 872  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.14 ADC Compare Window Register Name:ADC_CWR Address:0xF804C044 Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. LOWTHRES: Low Threshold Low threshold associated to compare settings of ADC_EMR. If LOWRES is set in ADC_MR, only the 10 LSB of LOWTHRES must be programmed. The two LSB will be automatically discarded to match the value carried on ADC_CDR (8-bit). HIGHTHRES: High Threshold High threshold associated to compare settings of ADC_EMR. If LOWRES is set in ADC_MR, only the 10 LSB of HIGHTHRES must be programmed. The two LSB will be automatically discarded to match the value carried on ADC_CDR (8-bit).  2017 Microchip Technology Inc. DS60001517A-page 873 SAM9N12/SAM9CN11/SAM9CN12 41.7.15 ADC Channel Data Register Name:ADC_CDRx [x=0..11] Address:0xF804C050 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. ADC_CDRx is only loaded if the corresponding analog channel is enabled. DS60001517A-page 874  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.16 ADC Analog Control Register Name:ADC_ACR Address:0xF804C094 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 PENDETSENS This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. PENDETSENS: Pen Detection Sensitivity Modifies the pen detection input pull-up resistor value. See the section ‘Electrical Characteristics’ for further details.  2017 Microchip Technology Inc. DS60001517A-page 875 SAM9N12/SAM9CN11/SAM9CN12 41.7.17 ADC Touchscreen Mode Register Name:ADC_TSMR Address:0xF804C0B0 Access:Read/Write 31 30 29 28 27 – 26 – 18 PENDBC 23 – 22 NOTSDMA 21 – 20 – 19 15 – 14 – 13 – 12 – 11 7 – 6 – 5 4 3 – TSAV 25 – 24 PENDET 17 16 9 8 TSSCTIM 10 TSFREQ 2 – 1 0 TSMODE This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. TSMODE: Touchscreen Mode Value Name Description 0 NONE No Touchscreen 1 4_WIRE_NO_PM 4-wire Touchscreen without pressure measurement 2 4_WIRE 4-wire Touchscreen with pressure measurement 3 5_WIRE 5-wire Touchscreen When TSMOD equals 01 or 10 (i.e., 4-wire mode), channels 0, 1, 2 and 3 must not be used for classic ADC conversions. When TSMOD equals 11 (i.e., 5-wire mode), channels 0, 1, 2, 3, and 4 must not be used. TSAV: Touchscreen Average Value Name Description 0 NO_FILTER No Filtering. Only one ADC conversion per measure 1 AVG2CONV Averages 2 ADC conversions 2 AVG4CONV Averages 4 ADC conversions 3 AVG8CONV Averages 8 ADC conversions TSFREQ: Touchscreen Frequency Defines the touchscreen frequency compared to the trigger frequency. TSFREQ must be greater or equal to TSAV. The touchscreen frequency is: Touchscreen Frequency = Trigger Frequency / 2TSFREQ TSSCTIM: Touchscreen Switches Closure Time Defines closure time of analog switches necessary to establish the measurement conditions. The closure time is: Switch Closure Time = (TSSCTIM × 4) ADCCLK periods. DS60001517A-page 876  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 PENDET: Pen Contact Detection Enable 0: Pen contact detection disabled. 1: Pen contact detection enabled. When PENDET = 1, XPOS, YPOS, Z1, Z2 values of ADC_XPOSR, ADC_YPOSR, ADC_PRESSR are automatically cleared when PENS = 0 in ADC_ISR. NOTSDMA: No TouchScreen DMA 0: XPOS, YPOS, Z1, Z2 are transmitted in ADC_LCDR. 1: XPOS, YPOS, Z1, Z2 are never transmitted in ADC_LCDR, therefore the buffer does not contains touchscreen values. PENDBC: Pen Detect Debouncing Period Debouncing period = 2PENDBC ADCCLK periods.  2017 Microchip Technology Inc. DS60001517A-page 877 SAM9N12/SAM9CN11/SAM9CN12 41.7.18 ADC Touchscreen X Position Register Name:ADC_XPOSR Address:0xF804C0B4 Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 XSCALE 19 18 11 10 XSCALE 15 – 14 – 13 – 12 – 7 6 5 4 XPOS 3 2 XPOS XPOS: X Position The position measured is stored here. If XPOS = 0 or XPOS = XSIZE, the pen is on the border. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), XPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). XSCALE: Scale of XPOS Indicates the max value that XPOS can reach. This value should be close to 210. DS60001517A-page 878  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.19 ADC Touchscreen Y Position Register Name:ADC_YPOSR Address:0xF804C0B8 Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 YSCALE 19 18 11 10 YSCALE 15 – 14 – 13 – 12 – 7 6 5 4 YPOS 3 2 YPOS YPOS: Y Position The position measured is stored here. If YPOS = 0 or YPOS = YSIZE, the pen is on the border. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), YPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). YSCALE: Scale of YPOS Indicates the max value that YPOS can reach. This value should be close to 210.  2017 Microchip Technology Inc. DS60001517A-page 879 SAM9N12/SAM9CN11/SAM9CN12 41.7.20 ADC Touchscreen Pressure Register Name:ADC_PRESSR Address:0xF804C0BC Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 Z2 19 18 11 10 Z2 15 – 14 – 13 – 12 – 7 6 5 4 Z1 3 2 Z1 Z1: Data of Z1 Measurement Data Z1 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), Z1 is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). Z2: Data of Z2 Measurement Data Z2 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), Z2 is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). Note: These two values are unavailable if TSMODE is not set to 2 in ADC_TSMR. DS60001517A-page 880  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.21 ADC Trigger Register Name:ADC_TRGR Address:0xF804C0C0 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 TRGPER 23 22 21 20 TRGPER 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 0 – – – – – 1 TRGMOD TRGMOD: Trigger Mode Value Name Description 0 NO_TRIGGER No trigger, only software trigger can start conversions 1 EXT_TRIG_RISE External trigger rising edge 2 EXT_TRIG_FALL External trigger falling edge 3 EXT_TRIG_ANY External trigger any edge 4 PEN_TRIG Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) 5 PERIOD_TRIG ADC internal periodic trigger (see field TRGPER) 6 CONTINUOUS Continuous Mode TRGPER: Trigger Period Effective only if TRGMOD defines a periodic trigger. Defines the periodic trigger period, with the following equation: Trigger Period = (TRGPER + 1) / ADCCLK The minimum time between two consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence depending on the configuration of registers ADC_MR, ADC_CHSR, ADC_SEQRx, ADC_TSMR. When TRGMOD is set to pen detect trigger (i.e., 100) and averaging is used (i.e., field TSAV ≠ 0 in ADC_TSMR) only one measure is performed. Thus, XRDY, YRDY, PRDY, DRDY will not rise on pen contact trigger. To achieve measurement, several triggers must be provided either by software or by setting the TRGMOD on continuous trigger (i.e., 110) until flags rise.  2017 Microchip Technology Inc. DS60001517A-page 881 SAM9N12/SAM9CN11/SAM9CN12 41.7.22 ADC Write Protection Mode Register Name:ADC_WPMR Address:0xF804C0E4 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII). 1: Enables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII). See Section 41.6.12 “Register Write Protection” for the list of write-protected registers. WPKEY: Write Protection Key Value 0x414443 Name PASSWD DS60001517A-page 882 Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 41.7.23 ADC Write Protection Status Register Name:ADC_WPSR Address:0xF804C0E8 Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of ADC_WPSR. 1: A write protection violation has occurred since the last read of ADC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.  2017 Microchip Technology Inc. DS60001517A-page 883 SAM9N12/SAM9CN11/SAM9CN12 42. Synchronous Serial Controller (SSC) 42.1 Description The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC high-level of programmability and its use of DMA permit a continuous high bit rate data transfer without processor intervention. Featuring connection to the DMA, the SSC permits interfacing with low processor overhead to the following: • Codecs in master or slave mode • DAC through dedicated serial interface, particularly I2S • Magnetic card reader 42.2 • • • • • • Embedded Characteristics Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications Contains an Independent Receiver and Transmitter and a Common Clock Divider Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead Offers a Configurable Frame Sync and Data Length Receiver and Transmitter Can be Programmed to Start Automatically or on Detection of Different Events on the Frame Sync Signal Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization Signal 42.3 Block Diagram Figure 42-1: Block Diagram System Bus Peripheral Bridge Bus Clock DMA Peripheral Bus TF TK PMC TD Peripheral Clock SSC Interface PIO RF RK Interrupt Control RD SSC Interrupt DS60001517A-page 884  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.4 Application Block Diagram Figure 42-2: Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 42.5 Codec Time Slot Management Frame Management Line Interface SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 42-3: Audio Application Block Diagram Clock SCK TK Word Select WS TF I2S RECEIVER Data SD SSC TD RD Clock SCK RF Word Select WS RK Data SD MSB LSB Left Channel  2017 Microchip Technology Inc. MSB Right Channel DS60001517A-page 885 SAM9N12/SAM9CN11/SAM9CN12 Figure 42-4: Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF CODEC Serial Data Out TD SSC Serial Data In RD RF RK Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Dend Serial Data Out Serial Data In Figure 42-5: Time Slot Application Block Diagram SCLK TK FSYNC TF CODEC First Time Slot Data Out TD SSC RD Data In RF RK CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Second Time Slot Dend Serial Data Out Serial Data in DS60001517A-page 886  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.6 Pin Name List Table 42-1: I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 42.7 Type Product Dependencies 42.7.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. Table 42-2: 42.7.2 I/O Lines Instance Signal I/O Line Peripheral SSC RD PA27 B SSC RF PA29 B SSC RK PA28 B SSC TD PA26 B SSC TF PA25 B SSC TK PA24 B Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. 42.7.3 Interrupt The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts requires programming the interrupt controller before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt Mask Register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC Interrupt Status Register. Table 42-3: Peripheral IDs Instance ID SSC 28  2017 Microchip Technology Inc. DS60001517A-page 887 SAM9N12/SAM9CN11/SAM9CN12 42.8 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the peripheral clock divided by 2. Figure 42-6: SSC Functional Block Diagram Transmitter Peripheral Clock TK Input Clock Divider Transmit Clock Controller RX clock TXEN RX Start Start Selector TF TK Frame Sync Controller TF Data Controller TD TX Start Transmit Shift Register Transmit Holding Register APB TX clock Clock Output Controller Transmit Sync Holding Register User Interface Receiver RK Input RK Frame Sync Controller RF Data Controller RD Receive Clock RX Clock Controller TX Clock RXEN TX Start Start RF Selector RC0R Interrupt Control Clock Output Controller RX Start Receive Shift Register Receive Holding Register Receive Sync Holding Register To Interrupt Controller DS60001517A-page 888  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.8.1 Clock Management The transmitter clock can be generated by: • an external clock received on the TK I/O pad • the receiver clock • the internal clock divider The receiver clock can be generated by: • an external clock received on the RK I/O pad • the transmitter clock • the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 42.8.1.1 Clock Divider Figure 42-7: Divided Clock Block Diagram Clock Divider SSC_CMR Peripheral Clock /2 12-bit Counter Divided Clock The peripheral clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register (SSC_CMR), allowing a peripheral clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of peripheral clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the peripheral clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 42-8: Divided Clock Generation Peripheral Clock Divided Clock DIV = 1 Divided Clock Frequency = fperipheral clock/2 Peripheral Clock Divided Clock DIV = 3 Divided Clock Frequency = fperipheral clock/6  2017 Microchip Technology Inc. DS60001517A-page 889 SAM9N12/SAM9CN11/SAM9CN12 42.8.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in the Transmit Clock Mode Register (SSC_TCMR). Transmit Clock can be inverted independently by the CKI bits in the SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the SSC_TCMR to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) can lead to unpredictable results. Figure 42-9: Transmitter Clock Management TK (pin) MUX Tri_state Controller Receiver Clock Clock Output Divider Clock CKO CKS 42.8.1.3 Data Transfer INV MUX Tri_state Controller CKI CKG Transmitter Clock Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the SSC_RCMR to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. Figure 42-10: Receiver Clock Management RK (pin) MUX Tri_state Controller Clock Output Transmitter Clock Divider Clock CKO CKS DS60001517A-page 890 Data Transfer INV MUX Tri_state Controller CKI CKG Receiver Clock  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.8.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: - Peripheral clock divided by 2 if Receiver Frame Synchro is input - Peripheral clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: - Peripheral clock divided by 6 if Transmit Frame Synchro is input - Peripheral clock divided by 2 if Transmit Frame Synchro is output 42.8.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the SSC_TCMR. See Section 42.8.4 “Start”. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See Section 42.8.5 “Frame Sync”. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in the SSC_SR. When the Transmit Holding register is transferred in the transmit shift register, the status flag TXRDY is set in the SSC_SR and additional data can be loaded in the holding register. Figure 42-11: Transmitter Block Diagram SSC_CRTXEN SSC_SRTXEN TXEN SSC_CRTXDIS SSC_RCMR.START SSC_TCMR.START RXEN TXEN TX Start RX Start Start RF Selector RF RC0R SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB SSC_TFMR.DATDEF SSC_TFMR.MSBF TX Controller TX Start Start Selector TD Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY != 0 SSC_TFMR.DATLEN 0 SSC_THR Transmitter Clock 1 SSC_TSHR SSC_TFMR.FSLEN TX Controller counter reached STTDLY 42.8.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See Section 42.8.4 “Start”. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See Section 42.8.5 “Frame Sync”. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in the SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the Receive Holding Register (SSC_RHR), the status flag OVERUN is set in the SSC_SR and the receiver shift register is transferred in the SSC_RHR.  2017 Microchip Technology Inc. DS60001517A-page 891 SAM9N12/SAM9CN11/SAM9CN12 Figure 42-12: Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS SSC_TCMR.START SSC_RCMR.START TXEN RX Start RF Start Selector RXEN RF RC0R Start Selector SSC_RFMR.MSBF SSC_RFMR.DATNB RX Start RX Controller RD Receive Shift Register SSC_RCMR.STTDLY != 0 load SSC_RSHR SSC_RFMR.FSLEN load SSC_RHR Receiver Clock SSC_RFMR.DATLEN RX Controller counter reached STTDLY 42.8.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. • Synchronously with the transmitter/receiver • On detection of a falling/rising edge on TF/RF • On detection of a low level/high level on TF/RF • On detection of a level change or an edge on TF/RF A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (SSC_RCMR/SSC_TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (SSC_TFMR/SSC_RFMR). DS60001517A-page 892  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 42-13: Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO B1 STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) BO X B1 BO B1 STTDLY TD (Output) X B1 BO BO B1 STTDLY Figure 42-14: Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) Start = Falling Edge on RF RD (Input) Start = High Level on RF Start = Rising Edge on RF Start = Level Change on RF Start = Any Edge on RF  2017 Microchip Technology Inc. X BO STTDLY BO X B1 STTDLY RD (Input) BO X B1 STTDLY RD (Input) BO X B1 STTDLY RD (Input) RD (Input) B1 BO X B1 BO B1 STTDLY X BO B1 BO B1 STTDLY DS60001517A-page 893 SAM9N12/SAM9CN11/SAM9CN12 42.8.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 256 bit times. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 42.8.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the shift register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 256. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the receive shift register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 42.8.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). 42.8.6 Receive Compare Modes Figure 42-15: Receive Compare Modes RK RD (Input) CMP0 CMP1 CMP2 CMP3 Ignored B0 B1 B2 Start FSLEN 42.8.6.1 STDLY DATLEN Compare Functions The length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 256 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the STOP bit in the SSC_RCMR. 42.8.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select the following parameters: • Event that starts the data transfer (START) • Delay in number of bit periods between the start event and the first data bit (STTDLY) DS60001517A-page 894  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 • • • • Length of the data (DATLEN) Number of data to be transferred for each start event (DATNB) Length of synchronization transferred for each start event (FSLEN) Bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. Table 42-4: Data Frame Registers Transmitter Receiver Field Length Comment SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame SSC_TFMR SSC_RFMR MSBF – Most significant bit first SSC_TFMR SSC_RFMR FSLEN Up to 256 Size of Synchro data register SSC_TFMR – DATDEF 0 or 1 Data default value ended SSC_TFMR – FSDEN – Enable send SSC_TSHR SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit start delay Figure 42-16: Transmit and Receive Frame Format in Edge/Pulse Start Modes Start Start PERIOD (1) TF/RF FSLEN TD (If FSDEN = 1) Sync Data Default From SSC_TSHR From DATDEF TD (If FSDEN = 0) RD Default Data Default From SSC_THR From DATDEF Data Data From DATDEF Sync Data Data From SSC_THR Ignored To SSC_RSHR STTDLY From SSC_THR From SSC_THR Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN Sync Data Default From DATDEF Ignored Sync Data DATNB Note: 1. Example of input on falling edge of TF/RF. In the example illustrated in Figure 42-17, the SSC_THR is loaded twice. The FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.  2017 Microchip Technology Inc. DS60001517A-page 895 SAM9N12/SAM9CN11/SAM9CN12 Figure 42-17: Transmit Frame Format in Continuous Mode (STTDLY = 0) Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Figure 42-18: Receive Frame Format in Continuous Mode (STTDLY = 0) Start = Enable Receiver RD 42.8.8 Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in the SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 42.8.9 Interrupt Most bits in the SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing the Interrupt Enable Register (SSC_IER) and Interrupt Disable Register (SSC_IDR). These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in the Interrupt Mask Register (SSC_IMR), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt controller. DS60001517A-page 896  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 42-19: Interrupt Block Diagram SSC_IMR SSC_IER SSC_IDR Set Clear Transmitter TXRDY TXEMPTY TXSYNC Interrupt Control SSC Interrupt Receiver RXRDY OVRUN RXSYNC 42.8.10 Register Write Protection To prevent any single software error from corrupting AIC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the SSC Write Protection Mode Register (SSC_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the SSC Write Protection Status Register (SSC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the SSC_WPSR. The following registers can be write-protected: • • • • • • • SSC Clock Mode Register SSC Receive Clock Mode Register SSC Receive Frame Mode Register SSC Transmit Clock Mode Register SSC Transmit Frame Mode Register SSC Receive Compare 0 Register SSC Receive Compare 1 Register  2017 Microchip Technology Inc. DS60001517A-page 897 SAM9N12/SAM9CN11/SAM9CN12 42.9 Synchronous Serial Controller (SSC) User Interface Table 42-5: Offset Register Mapping Register 0x0 Control Register 0x4 Clock Mode Register 0x8–0xC Reserved Name Access Reset SSC_CR Write-only – SSC_CMR Read/Write 0x0 – – – 0x10 Receive Clock Mode Register SSC_RCMR Read/Write 0x0 0x14 Receive Frame Mode Register SSC_RFMR Read/Write 0x0 0x18 Transmit Clock Mode Register SSC_TCMR Read/Write 0x0 0x1C Transmit Frame Mode Register SSC_TFMR Read/Write 0x0 0x20 Receive Holding Register SSC_RHR Read-only 0x0 0x24 Transmit Holding Register SSC_THR Write-only – – – – 0x28–0x2C Reserved 0x30 Receive Sync. Holding Register SSC_RSHR Read-only 0x0 0x34 Transmit Sync. Holding Register SSC_TSHR Read/Write 0x0 0x38 Receive Compare 0 Register SSC_RC0R Read/Write 0x0 0x3C Receive Compare 1 Register SSC_RC1R Read/Write 0x0 0x40 Status Register SSC_SR Read-only 0x000000CC 0x44 Interrupt Enable Register SSC_IER Write-only – 0x48 Interrupt Disable Register SSC_IDR Write-only – 0x4C Interrupt Mask Register SSC_IMR Read-only 0x0 – – – 0x50–0xE0 Reserved 0xE4 Write Protection Mode Register SSC_WPMR Read/Write 0x0 0xE8 Write Protection Status Register SSC_WPSR Read-only 0x0 0xEC–0xFC Reserved – – – 0x100–0x124 Reserved – – – DS60001517A-page 898  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.1 SSC Control Register Name:SSC_CR Address:0xF0010000 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception. TXEN: Transmit Enable 0: No effect. 1: Enables Transmit if TXDIS is not set. TXDIS: Transmit Disable 0: No effect. 1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR.  2017 Microchip Technology Inc. DS60001517A-page 899 SAM9N12/SAM9CN11/SAM9CN12 42.9.2 SSC Clock Mode Register Name:SSC_CMR Address:0xF0010004 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register. DIV: Clock Divider 0: The Clock Divider is not active. Any other value: The divided clock equals the peripheral clock divided by 2 times DIV. The maximum bit rate is fperipheral clock/2. The minimum bit rate is fperipheral clock/2 × 4095 = fperipheral clock/8190. DS60001517A-page 900  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.3 SSC Receive Clock Mode Register Name:SSC_RCMR Address:0xF0010010 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 PERIOD 23 22 21 20 STTDLY 15 – 7 14 – 13 – 12 STOP 11 6 5 CKI 4 3 CKO CKG START 2 1 0 CKS This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register. CKS: Receive Clock Selection Value Name Description 0 MCK Divided Clock 1 TK TK Clock signal 2 RK RK pin CKO: Receive Clock Output Mode Selection Value Name Description 0 NONE None, RK pin is an input 1 CONTINUOUS Continuous Receive Clock, RK pin is an output 2 TRANSFER Receive Clock only during data transfers, RK pin is an output CKI: Receive Clock Inversion 0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. CKG: Receive Clock Gating Selection Value Name Description 0 CONTINUOUS None 1 EN_RF_LOW Receive Clock enabled only if RF Low 2 EN_RF_HIGH Receive Clock enabled only if RF High  2017 Microchip Technology Inc. DS60001517A-page 901 SAM9N12/SAM9CN11/SAM9CN12 START: Receive Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 1 TRANSMIT Transmit start 2 RF_LOW Detection of a low level on RF signal 3 RF_HIGH Detection of a high level on RF signal 4 RF_FALLING Detection of a falling edge on RF signal 5 RF_RISING Detection of a rising edge on RF signal 6 RF_LEVEL Detection of any level change on RF signal 7 RF_EDGE Detection of any edge on RF signal 8 CMP_0 Compare 0 STOP: Receive Stop Selection 0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD + 1) Receive Clock. DS60001517A-page 902  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.4 SSC Receive Frame Mode Register Name:SSC_RFMR Address:0xF0010014 Access:Read/Write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 – 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register. DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Receive Clock periods. FSOS: Receive Frame Sync Output Selection Value Name Description 0 NONE None, RF pin is an input 1 NEGATIVE Negative Pulse, RF pin is an output 2 POSITIVE Positive Pulse, RF pin is an output 3 LOW Driven Low during data transfer, RF pin is an output 4 HIGH Driven High during data transfer, RF pin is an output 5 TOGGLING Toggling at each start of data transfer, RF pin is an output  2017 Microchip Technology Inc. DS60001517A-page 903 SAM9N12/SAM9CN11/SAM9CN12 FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. Value Name Description 0 POSITIVE Positive Edge Detection 1 NEGATIVE Negative Edge Detection FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description above. DS60001517A-page 904  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.5 SSC Transmit Clock Mode Register Name:SSC_TCMR Address:0xF0010018 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 PERIOD 23 22 21 20 STTDLY 15 – 7 14 – 13 – 12 – 11 6 5 CKI 4 3 CKO CKG START 2 1 0 CKS This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register. CKS: Transmit Clock Selection Value Name Description 0 MCK Divided Clock 1 RK RK Clock signal 2 TK TK pin CKO: Transmit Clock Output Mode Selection Value Name Description 0 NONE None, TK pin is an input 1 CONTINUOUS Continuous Transmit Clock, TK pin is an output 2 TRANSFER Transmit Clock only during data transfers, TK pin is an output CKI: Transmit Clock Inversion 0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. CKG: Transmit Clock Gating Selection Value Name Description 0 CONTINUOUS None 1 EN_TF_LOW Transmit Clock enabled only if TF Low 2 EN_TF_HIGH Transmit Clock enabled only if TF High  2017 Microchip Technology Inc. DS60001517A-page 905 SAM9N12/SAM9CN11/SAM9CN12 START: Transmit Start Selection Value Name Description 0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data 1 RECEIVE Receive start 2 TF_LOW Detection of a low level on TF signal 3 TF_HIGH Detection of a high level on TF signal 4 TF_FALLING Detection of a falling edge on TF signal 5 TF_RISING Detection of a rising edge on TF signal 6 TF_LEVEL Detection of any level change on TF signal 7 TF_EDGE Detection of any edge on TF signal STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 × (PERIOD + 1) Transmit Clock. DS60001517A-page 906  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.6 SSC Transmit Frame Mode Register Name:SSC_TFMR Address:0xF001001C Access:Read/Write 31 30 29 28 27 – 26 – 21 FSOS 20 19 18 FSLEN_EXT 23 FSDEN 22 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register. DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. . DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. DATNB: Data Number per Frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1). FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT × 16) + 1 Transmit Clock period. FSOS: Transmit Frame Sync Output Selection Value Name Description 0 NONE None, TF pin is an input 1 NEGATIVE Negative Pulse, TF pin is an output 2 POSITIVE Positive Pulse, TF pin is an output 3 LOW Driven Low during data transfer 4 HIGH Driven High during data transfer 5 TOGGLING Toggling at each start of data transfer  2017 Microchip Technology Inc. DS60001517A-page 907 SAM9N12/SAM9CN11/SAM9CN12 FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). Value Name Description 0 POSITIVE Positive Edge Detection 1 NEGATIVE Negative Edge Detection FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description above. DS60001517A-page 908  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.7 SSC Receive Holding Register Name:SSC_RHR Address:0xF0010020 Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.  2017 Microchip Technology Inc. DS60001517A-page 909 SAM9N12/SAM9CN11/SAM9CN12 42.9.8 SSC Transmit Holding Register Name:SSC_THR Address:0xF0010024 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. DS60001517A-page 910  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.9 SSC Receive Synchronization Holding Register Name:SSC_RSHR Address:0xF0010030 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT RSDAT: Receive Synchronization Data  2017 Microchip Technology Inc. DS60001517A-page 911 SAM9N12/SAM9CN11/SAM9CN12 42.9.10 SSC Transmit Synchronization Holding Register Name:SSC_TSHR Address:0xF0010034 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TSDAT 7 6 5 4 TSDAT TSDAT: Transmit Synchronization Data DS60001517A-page 912  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.11 SSC Receive Compare 0 Register Name:SSC_RC0R Address:0xF0010038 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register. CP0: Receive Compare Data 0  2017 Microchip Technology Inc. DS60001517A-page 913 SAM9N12/SAM9CN11/SAM9CN12 42.9.12 SSC Receive Compare 1 Register Name:SSC_RC1R Address:0xF001003C Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP1 7 6 5 4 CP1 This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register. CP1: Receive Compare Data 1 DS60001517A-page 914  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.13 SSC Status Register Name:SSC_SR Address:0xF0010040 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the transmit shift register (TSR). 1: SSC_THR is empty. TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from TSR. 1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register. TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled.  2017 Microchip Technology Inc. DS60001517A-page 915 SAM9N12/SAM9CN11/SAM9CN12 RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled. DS60001517A-page 916  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.14 SSC Interrupt Enable Register Name:SSC_IER Address:0xF0010044 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt. RXRDY: Receive Ready Interrupt Enable 0: No effect. 1: Enables the Receive Ready Interrupt. OVRUN: Receive Overrun Interrupt Enable 0: No effect. 1: Enables the Receive Overrun Interrupt. CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.  2017 Microchip Technology Inc. DS60001517A-page 917 SAM9N12/SAM9CN11/SAM9CN12 42.9.15 SSC Interrupt Disable Register Name:SSC_IDR Address:0xF0010048 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt. RXRDY: Receive Ready Interrupt Disable 0: No effect. 1: Disables the Receive Ready Interrupt. OVRUN: Receive Overrun Interrupt Disable 0: No effect. 1: Disables the Receive Overrun Interrupt. CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt. DS60001517A-page 918  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.16 SSC Interrupt Mask Register Name:SSC_IMR Address:0xF001004C Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 – 6 – 5 OVRUN 4 RXRDY 3 – 2 – 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled. TXEMPTY: Transmit Empty Interrupt Mask 0: The Transmit Empty Interrupt is disabled. 1: The Transmit Empty Interrupt is enabled. RXRDY: Receive Ready Interrupt Mask 0: The Receive Ready Interrupt is disabled. 1: The Receive Ready Interrupt is enabled. OVRUN: Receive Overrun Interrupt Mask 0: The Receive Overrun Interrupt is disabled. 1: The Receive Overrun Interrupt is enabled. CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled.  2017 Microchip Technology Inc. DS60001517A-page 919 SAM9N12/SAM9CN11/SAM9CN12 42.9.17 SSC Write Protection Mode Register Name:SSC_WPMR Address:0xF00100E4 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x535343 (“SSC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x535343 (“SSC” in ASCII). See Section 42.8.10 “Register Write Protection” for the list of registers that can be protected. WPKEY: Write Protection Key Value 0x535343 Name PASSWD DS60001517A-page 920 Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 42.9.18 SSC Write Protection Status Register Name:SSC_WPSR Address:0xF00100E8 Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the SSC_WPSR. 1: A write protection violation has occurred since the last read of the SSC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. WPVSRC: Write Protect Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.  2017 Microchip Technology Inc. DS60001517A-page 921 SAM9N12/SAM9CN11/SAM9CN12 43. LCD Controller (LCDC) 43.1 Description The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module. The LCDC has one display input buffer that fetches pixels through the AB master interface and a lookup table to allow palletized display configurations. The LCDC is programmable on a per overlay basis, and supports different LCD resolution, window size, image format and pixel depth. The LCDC is connected to the Arm Advanced High Performance Bus (AHB) as a master for reading pixel data. It also integrates an APB interface to configure its registers. 43.2 • • • • • • • • • • • • • • Embedded Characteristics One AHB Master Interface Supports Single Scan Active TFT Display Supports 12-, 16-, 18- and 24-bit Output Mode through the Spatial Dithering Unit Asynchronous Output Mode Supported 1, 2, 4, 8 bits per pixel (palletized) 12, 16, 18, 19, 24, 25 and 32 bits per pixel (non-palletized) Supports One Base Layer (background) Little Endian Memory Organization Programmable Timing Engine, with Integer Clock Divider Programmable Polarity for Data, Line Synchro and Frame Synchro Display Size up to 1280 × 860 Color Lookup Table with up to 256 entries Programmable Negative and Positive Row Striding DMA User interface uses Linked List Structure and Add-to-queue Structure 43.3 Block Diagram Figure 43-1: AHB Bus Block Diagram LCD_DAT[23:0] 32-bit APB Interface Configuration Registers SYSCTRL Unit LCD_VSYNC LTE Unit 32-bit AHB Master Interface DEAG Unit LCD_HSYNC LCD_PCLK Base Layer CLUT LCD_DEN LCD_PWM LCD_DISP DEAG: DMA Engine Address Generation LTE: LCD Timing Engine DS60001517A-page 922  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.4 I/O Lines Description Table 43-1: I/O Lines Description Name Description Type LCD_PWM Contrast control signal, using Pulse Width Modulation Output LCD_HSYNC Horizontal Synchronization Pulse Output LCD_VSYNC Vertical Synchronization Pulse Output LCD_DAT[23:0] LCD 24-bit data bus Output LCD_DEN Data Enable Output LCD_DISP Display Enable signal Output LCD_PCLK Pixel Clock Output 43.5 43.5.1 Product Dependencies I/O Lines The pins used for interfacing the LCDC may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the LCDC are not used by the application, they can be used for other purposes by the PIO Controller. Table 43-2: I/O Lines Instance Signal I/O Line Peripheral LCDC LCDDAT0 PC0 A LCDC LCDDAT1 PC1 A LCDC LCDDAT2 PC2 A LCDC LCDDAT3 PC3 A LCDC LCDDAT4 PC4 A LCDC LCDDAT5 PC5 A LCDC LCDDAT6 PC6 A LCDC LCDDAT7 PC7 A LCDC LCDDAT8 PC8 A LCDC LCDDAT9 PC9 A LCDC LCDDAT10 PC10 A LCDC LCDDAT11 PC11 A LCDC LCDDAT12 PC12 A LCDC LCDDAT13 PC13 A LCDC LCDDAT14 PC14 A LCDC LCDDAT15 PC15 A LCDC LCDDAT16 PC16 A LCDC LCDDAT17 PC17 A LCDC LCDDAT18 PC18 A LCDC LCDDAT19 PC19 A LCDC LCDDAT20 PC20 A  2017 Microchip Technology Inc. DS60001517A-page 923 SAM9N12/SAM9CN11/SAM9CN12 Table 43-2: 43.5.2 I/O Lines (Continued) Instance Signal I/O Line Peripheral LCDC LCDDAT21 PC21 A LCDC LCDDAT22 PC22 A LCDC LCDDAT23 PC23 A LCDC LCDDEN PC29 A LCDC LCDDISP PC24 A LCDC LCDHSYNC PC28 A LCDC LCDPCK PC30 A LCDC LCDPWM PC26 A LCDC LCDVSYNC PC27 A Power Management The LCDC is not continuously clocked. The user must first enable the LCDC clock in the Power Management Controller before using it (PMC_PCER). 43.5.3 Interrupt Sources The LCDC interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller. Using the LCDC interrupt requires prior programming of the AIC. Table 43-3: Peripheral IDs Instance ID LCDC 25 43.6 Functional Description The LCD module integrates the following digital blocks: • • • • • DMA Engine Address Generation (DEAG)—This block performs data prefetch and requests access to the AHB interface. Input FIFO stores the stream of pixels. Color Lookup Table (CLUT)—These 256 RAM-based lookup table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp. Output FIFO—stores the pixel prior to display. LCD Timing Engine—provides a fully programmable HSYNC-VSYNC interface. The DMA controller reads the image through the AHB master interface. The LCDC engine formats the display data and writes the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the LCD_DAT[23:0] display bus. 43.6.1 43.6.1.1 Timing Engine Configuration Pixel Clock Period Configuration The pixel clock (PCLK) generated by the timing engine is the source clock (SCLK) divided by the field CLKDIV in the LCDC_LCDCFG0 register. The source clock can be selected between the system clock and the 2x system clock with the field CLKSEL located in the LCDC_LCDCFG0 register. Pixel Clock period formula: SCLK PCLK = -------------------------------CLKDIV + 2 The Pixel Clock polarity is also programmable. DS60001517A-page 924  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.6.1.2 Horizontal and Vertical Synchronization Configuration The following fields are used to configure the timing engine: • • • • • • • • LCDC_LCDCFG1.HSPW LCDC_LCDCFG1.VSPW LCDC_LCDCFG2.VFPW LCDC_LCDCFG2.VBPW LCDC_LCDCFG3.HFPW LCDC_LCDCFG3.HBPW LCDC_LCDCFG4.PPL LCDC_LCDCFG4.RPF The polarity of output signals is also programmable. 43.6.1.3 Timing Engine Power Up Software Operation The following sequence is used to enable the display: 1. 2. 3. 4. 5. 6. 7. Configure LCD timing parameters, signal polarity and clock period. Enable the Pixel Clock by writing one to to bit LCDC_LCDEN.CLKEN. Poll bit LCDC_LCDSR.CLKSTS to check that the clock is running. Enable Horizontal and Vertical Synchronization by writing one to bit LCDC_LCDEN.SYNCEN. Poll bit LCDC_LCDSR.LCDSTS to check that the synchronization is up. Enable the display power signal writing one to bit LCDC_LCDEN.DISPEN. Poll bit LCDC_LCDSR.DISPSTS to check that the power signal is activated. The field LCDC_LCDCFG5.GUARDTIME is used to configure the number of frames before the assertion of the DISP signal. 43.6.1.4 Timing Engine Power Down Software Operation The following sequence is used to disable the display: 1. 2. 3. 4. 5. Disable the DISP signal writing bit LCDC_LCDDIS.DISPDIS. Poll bit LCDC_LCDSR.DISPSTS to verify that the DISP is no longer activated. Disable the HSYNC and VSYNC signals by writing one to to bit LCDC_LCDDIS.SYNCDIS. Poll bit LCDC_LCDSR.LCDSTS to check that the synchronization is off. Disable the Pixel clock by writing one to bit LCDC_LCDDIS.CLKDIS. 43.6.2 DMA Software Operations 43.6.2.1 DMA Channel Descriptor (DSCR) Alignment and Structure The DMA Channel Descriptor (DSCR) must be word aligned. The DMA Channel Descriptor structure contains three fields: • DSCR.CHXADDR: Frame Buffer base address register • DSCR.CHXCTRL: Transfer Control register • DSCR.CHXNEXT: Next Descriptor Address register Table 43-4: 43.6.2.2 1. 2. 3. DMA Channel Descriptor Structure System Memory Structure Field for channel CHX DSCR + 0x0 ADDR DSCR + 0x4 CTRL DSCR + 0x8 NEXT Programming a DMA Channel Check the status of the channel reading the CHXCHSR register. Write the channel descriptor (DSCR) structure in the system memory by writing DSCR.CHXADDR Frame base address, DSCR.CHXCTRL channel control and DSCR.CHXNEXT next descriptor location. If more than one descriptor is expected, the DFETCH bit of DSCR.CHXCTRL is set to one to enable the descriptor fetch operation.  2017 Microchip Technology Inc. DS60001517A-page 925 SAM9N12/SAM9CN11/SAM9CN12 4. 5. 6. Write the DSCR.CHXNEXT register with the address location of the descriptor structure and set DFETCH bit of the DSCR.CHXCTRL register to one. Enable the relevant channel by writing one to the CHEN bit of the CHXCHER register. An interrupt may be raised if unmasked when the descriptor has been loaded. 43.6.2.3 1. 2. 3. 4. 5. 43.6.2.4 1. 2. 3. 4. 5. Disabling a DMA channel Clear the DFETCH bit in the DSCR.CHXCTRL field of the DSCR structure will disable the channel at the end of the frame. Set the DSCR.CHXNEXT register of the DSCR structure will disable the channel at the end of the frame. Writing one to the CHDIS bit of the CHXCHDR register will disable the channel at the end of the frame. Writing one to the CHRST bit of the CHXCHDR register will disable the channel immediately. This may occur in the middle of the image. Poll CHSR bit in the CHXCHSR register until the channel is successfully disabled. DMA Dynamic Linking of a New Transfer Descriptor Write the new descriptor structure in the system memory. Write the address of the new structure in the CHXHEAD register. Add the new structure to the queue of descriptors by writing one to the A2QEN bit of the CHXCHER register. The new descriptor will be added to the queue on the next frame. An interrupt will be raised if unmasked, when the head descriptor structure has been loaded by the DMA channel. 43.6.2.5 DMA Interrupt Generation The DMA controller operation sets the following interrupt flags in the interrupt status register CHXISR: • • • • DMA field indicates that the DMA transfer is completed. DSCR field indicates that the descriptor structure is loaded in the DMA controller. ADD field indicates that a descriptor has been added to the descriptor queue. DONE field indicates that the channel transfer has terminated and the channel is automatically disabled. 43.6.2.6 DMA Address Alignment Requirements When programming the DSCR.CHXADDR register of the DSCR structure the following requirement must be met. Table 43-5: DMA address alignment when CLUT Mode is selected CLUT Mode DMA Address Alignment 1 bpp 8-bit 2 bpp 8-bit 4 bpp 8-bit 8 bpp 8-bit Table 43-6: DMA address alignment when RGB Mode is selected RGB Mode DMA Address Alignment 12 bpp RGB 444 16-bit 16 bpp ARGB 4444 16-bit 16 bpp RGBA 4444 16-bit 16 bpp RGB 565 16-bit 16 bpp TRGB 1555 16-bit 18 bpp RGB 666 32-bit 18 bpp RGB 666 PACKED 8-bit 19 bpp TRGB 1666 32-bit DS60001517A-page 926  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 43-6: DMA address alignment when RGB Mode is selected RGB Mode DMA Address Alignment 19 bpp TRGB 1666 8-bit 24 bpp RGB 888 32-bit 24 bpp RGB 888 PACKED 8-bit 25 bpp TRGB 1888 32-bit 32 bpp ARGB 8888 32-bit 32 bpp RGBA 8888 32-bit 43.6.3 Display Software Configuration 43.6.3.1 System Bus Access Attributes These attributes are defined to improve bandwidth of the pixel stream. • DLBO bit: when set to one only defined burst lengths are performed when the DMA channel retrieves the data from the memory. • BLEN field: defines the maximum burst length of the DMA channel. 43.6.3.2 Color Attributes • CLUTMODE field: selects the Color Lookup Table mode • RGBMODE field: selects the RGB mode 43.6.3.3 1. 2. 3. Window Attributes Software Operation When required, write the overlay attributes configuration registers. Set UPDATEEN field of the CHXCHER register. Poll UPDATESR field in the CHXCHSR, the update applies when that field is reset. 43.6.4 RGB Frame Buffer Memory Bitmap 43.6.4.1 1 bpp Through Color Lookup Table Table 43-7: 1 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 1 bpp p3 p3 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p1 p1 p1 p1 p1 p1 p1 p1 p1 p11 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 0 43.6.4.2 Table 43-8: 0x2 0x1 0x0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Table 43-9: 0x2 p15 p14 p13 p12 0x1 5 4 3 2 1 0 p11 p10 p9 p8 0x0 p7 p6 9 p5 8 7 p4 6 5 p3 4 3 p2 2 1 p1 0 p0 4 bpp Through Color Lookup Table 4 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 4 bpp 6 2 bpp memory mapping, little endian organization 0x3 43.6.4.3 7 2 bpp Through Color Lookup Table Mem addr Pixel 2 bpp 8 0x2 p7  2017 Microchip Technology Inc. p6 0x1 p5 p4 0x0 p3 p2 9 8 7 6 5 p1 4 3 2 1 0 p0 DS60001517A-page 927 SAM9N12/SAM9CN11/SAM9CN12 43.6.4.4 8 bpp Through Color Lookup Table Table 43-10: 8 bpp memory mapping, little endian organization Mem addr 0x3 0x2 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 8 bpp 43.6.4.5 0x1 p3 0x0 p2 5 4 3 2 1 0 3 2 1 0 12 bpp memory mapping, little endian organization Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 12 bpp 0x2 – R1[3:0] 0x1 G1[3:0] 0x0 B1[3:0] – 9 8 7 R0[3:0] 6 5 4 G0[3:0] B0[3:0] 16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4 Table 43-12: 16 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 16 bpp 0x2 A1[3:0] R1[3:0] 0x1 G1[3:0] 0x0 B1[3:0] A0[3:0] 9 8 7 R0[3:0] 6 5 4 3 G0[3:0] 2 1 0 B0[3:0] 16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4 Table 43-13: 16 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 16 bpp 0x2 R1[3:0] G13:0] 0x1 B1[3:0] A1[3:0] 0x0 R0[3:0] 9 8 7 G0[3:0] 6 5 4 3 B0[3:0] 2 1 0 A0[3:0] 16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5 Table 43-14: 16 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 16bpp 43.6.4.9 6 p0 0x3 43.6.4.8 7 p1 Mem addr 43.6.4.7 8 12 bpp Memory Mapping, RGB 4:4:4 Table 43-11: 43.6.4.6 9 0x2 R1[4:0] G1[5:0] 0x1 B1[4:0] 0x0 9 R0[4:0] 8 7 6 5 4 3 G0[5:0] 2 1 0 1 0 B0[4:0] 16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5 Table 43-15: 16 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 4 bpp A1 DS60001517A-page 928 0x2 R1[4:0] G1[4:0] 0x1 B1[4:0] A0 0x0 R0[4:0] 9 8 7 6 G0[4:0] 5 4 3 2 B0[4:0]  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.6.4.10 18 bpp Unpacked Memory Mapping with Transparency Bit, RGB 6:6:6 Table 43-16: 18 bpp unpacked memory mapping, little endian organization Mem addr 0x3 0x2 0x1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 18 bpp 43.6.4.11 0x0 R0[5:0] 6 5 4 3 2 1 0 1 0 1 0 B0[5:0] 18 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 18 bpp G1[1:0] Table 43-18: 0x2 0x1 B1[5:0] 0x0 R0[5:0] 8 7 6 5 4 3 2 B0[5:0] 18 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 18 bpp 0x6 R2[3:0] Table 43-19: 9 G0[5:0] Mem addr G2[5:0] 0x5 0x4 9 8 B2[5:0] 7 6 5 4 3 R1[5:2] 2 G1[5:2] 18 bpp packed memory mapping, little endian organization at address 0x8, 0x9, 0xA, 0xB Mem addr 0xB Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 18 bpp G4[1:0] 0xA 0x9 B4[5:0] R3[5:0] 0x8 9 8 7 6 G3[5:0] 5 4 3 2 B3[3:0] 1 0 R2[5:4] 19 bpp Unpacked Memory Mapping with Transparency Bit, RGB 1:6:6:6 Table 43-20: 19 bpp unpacked memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x2 Pixel 19 bpp 0x1 A0 0x0 R0[5:0] 9 8 7 6 5 4 G0[5:0] 3 2 1 0 1 0 1 0 B0[5:0] 19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6 Table 43-21: 19 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 19 bpp G1[1:0] Table 43-22: 0x2 B1[5:0] 0x1 A0 0x0 R0[5:0] 9 8 7 6 5 4 G0[5:0] 3 2 B0[5:0] 19 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 19 bpp 7 G0[5:0] Mem addr 43.6.4.13 8 18 bpp Packed Memory Mapping with Transparency Bit, RGB 6:6:6 Table 43-17: 43.6.4.12 9 0x6 R2[3:0]  2017 Microchip Technology Inc. G2[5:0] 0x5 B2[5:0] 0x4 A1 9 8 7 6 R1[5:2] 5 4 3 2 G1[5:2] DS60001517A-page 929 SAM9N12/SAM9CN11/SAM9CN12 Table 43-23: 19 bpp packed memory mapping, little endian organization at address 0x8, 0x9, 0xA, 0xB Mem addr 0xB Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 19 bpp G4[1:0] 43.6.4.14 0xA B4[5:0] 0x9 A3 R3[5:0] 0x8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x2 Pixel 24 bpp 5 4 3 2 B3[3:0] 0x1 R0[7:0] 1 0 R2[5:4] 0x0 9 8 7 6 5 G0[7:0] 4 3 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 B0[7:0] 24 bpp Packed Memory Mapping, RGB 8:8:8 Table 43-25: 24 bpp packed memory mapping, little endian organization at address 0x0, 0x1, 0x2, 0x3 Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 24 bpp 0x2 B1[7:0] Table 43-26: 0x1 R0[7:0] 0x0 9 8 7 6 5 G0[7:0] 4 3 B0[7:0] 24 bpp packed memory mapping, little endian organization at address 0x4, 0x5, 0x6, 0x7 Mem addr 0x7 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 24 bpp 0x6 G2[7:0] 0x5 B2[7:0] 0x4 9 8 7 6 5 R1[7:0] 4 3 G1[7:0] 25 bpp Memory Mapping, ARGB 1:8:8:8 Table 43-27: 25 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x2 Pixel 25 bpp A0 0x1 R0[7:0] 0x0 9 8 7 6 5 G0[7:0] 4 3 B0[7:0] 32 bpp Memory Mapping, ARGB 8:8:8:8 Table 43-28: 32 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 32 bpp 43.6.4.18 6 24 bpp memory mapping, little endian organization 0x3 43.6.4.17 7 G3[5:0] Mem addr 43.6.4.16 8 24 bpp Unpacked Memory Mapping, RGB 8:8:8 Table 43-24: 43.6.4.15 9 0x2 A0[7:0] 0x1 R0[7:0] 0x0 9 8 7 6 5 G0[7:0] 4 3 B0[7:0] 32 bpp Memory Mapping, RGBA 8:8:8:8 Table 43-29: 32 bpp memory mapping, little endian organization Mem addr 0x3 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Pixel 32 bpp DS60001517A-page 930 0x2 R0[7:0] 0x1 G0[7:0] 0x0 B0[7:0] 9 8 7 6 5 4 3 A0[7:0]  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.6.5 Output Timing Generation 43.6.5.1 Active Display Timing Mode Figure 43-2: Active Display Timing LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] HSW VBP VSW HBP LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] HSW HBP HFP PPL HSW HBP LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] PPL  2017 Microchip Technology Inc. HFP HSW VFP DS60001517A-page 931 SAM9N12/SAM9CN11/SAM9CN12 Figure 43-3: VSPDLYS = 0 Vertical Synchronization Timing (part 1 of 2) VSPDLYE = 0 VSPSU = 0 VSPHO = 0 VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VBP HBP VBP HBP VBP HBP VBP HBP VBP HBP LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 0 VSPDLYE = 1 VSW VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 1 VSW VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VSPSU = 1 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW DS60001517A-page 932 VSW  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 43-4: VSPDLYS = 1 Vertical Synchronization Timing (part 2 of 2) VSPDLYE = 0 VSPSU = 0 VSPHO = 1 VSPSU = 1 VSPHO = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VBP HBP VBP HBP LCD_PCLK LCD_VSYNC LCD_HSYNC HSW  2017 Microchip Technology Inc. VSW DS60001517A-page 933 SAM9N12/SAM9CN11/SAM9CN12 Figure 43-5: DISP Signal Timing Diagram VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC lcd display off LCD_DISP lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display off lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display off lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP DS60001517A-page 934 lcd display on lcd display off  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.6.6 43.6.6.1 Output Format Active Mode Output Pin Assignment Table 43-30: Active Mode Output with 24-bit Bus Interface Configuration Pin ID TFT 24-bit TFT 18-bit TFT 16-bit TFT 12-bit LCD_DAT[23] R[7] – – – LCD_DAT[22] R[6] – – – LCD_DAT[21] R[5] – – – LCD_DAT[20] R[4] – – – LCD_DAT[19] R[3] – – – LCD_DAT[18] R[2] – – – LCD_DAT[17] R[1] R[5] – – LCD_DAT[16] R[0] R[4] – – LCD_DAT[15] G[7] R[3] R[4] – LCD_DAT[14] G[6] R[2] R[3] – LCD_DAT[13] G[5] R[1] R[2] – LCD_DAT[12] G[4] R[0] R[1] – LCD_DAT[11] G[3] G[5] R[0] R[3] LCD_DAT[10] G[2] G[4] G[5] R[2] LCD_DAT[9] G[1] G[3] G[4] R[1] LCD_DAT[8] G[0] G[2] G[3] R[0] LCD_DAT[7] B[7] G[1] G[2] G[3] LCD_DAT[6] B[6] G[0] G[1] G[2] LCD_DAT[5] B[5] B[5] G[0] G[1] LCD_DAT[4] B[4] B[4] B[4] G[0] LCD_DAT[3] B[3] B[3] B[3] B[3] LCD_DAT[2] B[2] B[2] B[2] B[2] LCD_DAT[1] B[1] B[1] B[1] B[1] LCD_DAT[0] B[0] B[0] B[0] B[0]  2017 Microchip Technology Inc. DS60001517A-page 935 SAM9N12/SAM9CN11/SAM9CN12 43.7 LCD Controller (LCDC) User Interface Table 43-31: Register Mapping Offset Register Name Access Reset 0x00000000 LCD Controller Configuration Register 0 LCDC_LCDCFG0 Read/Write 0x00000000 0x00000004 LCD Controller Configuration Register 1 LCDC_LCDCFG1 Read/Write 0x00000000 0x00000008 LCD Controller Configuration Register 2 LCDC_LCDCFG2 Read/Write 0x00000000 0x0000000C LCD Controller Configuration Register 3 LCDC_LCDCFG3 Read/Write 0x00000000 0x00000010 LCD Controller Configuration Register 4 LCDC_LCDCFG4 Read/Write 0x00000000 0x00000014 LCD Controller Configuration Register 5 LCDC_LCDCFG5 Read/Write 0x00000000 0x00000018 LCD Controller Configuration Register 6 LCDC_LCDCFG6 Read/Write 0x00000000 0x0000001C Reserved – – – 0x00000020 LCD Controller Enable Register LCDC_LCDEN Write-only – 0x00000024 LCD Controller Disable Register LCDC_LCDDIS Write-only – 0x00000028 LCD Controller Status Register LCDC_LCDSR Read-only 0x00000000 0x0000002C LCD Controller Interrupt Enable Register LCDC_LCDIER Write-only - 0x00000030 LCD Controller Interrupt Disable Register LCDC_LCDIDR Write-only - 0x00000034 LCD Controller Interrupt Mask Register LCDC_LCDIMR Read-only 0x00000000 0x00000038 LCD Controller Interrupt Status Register LCDC_LCDISR Read-only 0x00000000 0x0000003C Reserved – – – 0x00000040 Base Layer Channel Enable Register LCDC_BASECHER Write-only – 0x00000044 Base Layer Channel Disable Register LCDC_BASECHDR Write-only – 0x00000048 Base Layer Channel Status Register LCDC_BASECHSR Read-only 0x00000000 0x0000004C Base Layer Interrupt Enable Register LCDC_BASEIER Write-only – 0x00000050 Base Layer Interrupt Disabled Register LCDC_BASEIDR Write-only – 0x00000054 Base Layer Interrupt Mask Register LCDC_BASEIMR Read-only 0x00000000 0x00000058 Base Layer Interrupt status Register LCDC_BASEISR Read-only 0x00000000 0x0000005C Base Layer DMA Head Register LCDC_BASEHEAD Read/Write 0x00000000 0x00000060 Base Layer DMA Address Register LCDC_BASEADDR Read/Write 0x00000000 0x00000064 Base Layer DMA Control Register LCDC_BASECTRL Read/Write 0x00000000 0x00000068 Base Layer DMA Next Register LCDC_BASENEXT Read/Write 0x00000000 0x0000006C Base Layer Configuration Register 0 LCDC_BASECFG0 Read/Write 0x00000000 0x00000070 Base Layer Configuration Register 1 LCDC_BASECFG1 Read/Write 0x00000000 0x00000074 Base Layer Configuration Register 2 LCDC_BASECFG2 Read/Write 0x00000000 0x00000078 Base Layer Configuration Register 3 LCDC_BASECFG3 Read/Write 0x00000000 0x0000007C Base Layer Configuration Register 4 LCDC_BASECFG4 Read/Write 0x00000000 0x80–0x3FC Reserved – – – Read/Write 0x00000000 ... ... 0x400 ... DS60001517A-page 936 (1) LCDC_BASECLUT0 ... ... Base CLUT Register 0  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 43-31: Register Mapping (Continued) Offset 0x7FC 0x800–0x1FFC Register Name (1) Base CLUT Register 255 LCDC_BASECLUT255 Reserved – Access Reset Read/Write 0x00000000 – – Note 1: The CLUT registers are located in RAM.  2017 Microchip Technology Inc. DS60001517A-page 937 SAM9N12/SAM9CN11/SAM9CN12 43.7.1 LCD Controller Configuration Register 0 Name: LCDC_LCDCFG0 Address:0xF8038000 Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 – 14 – 6 – 13 – 5 – 12 – 4 – 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 CLKPWMSEL 10 – 2 CLKSEL 9 – 1 – 8 CGDISBASE 0 CLKPOL CLKDIV CLKPOL: LCD Controller Clock Polarity 0: Data/Control signals are launched on the rising edge of the Pixel Clock. 1: Data/Control signals are launched on the falling edge of the Pixel Clock. CLKSEL: LCD Controller Clock Source Selection 0: The Asynchronous output stage of the LCD controller is fed by MCK. 1: The Asynchronous output state of the LCD controller is fed by 2x MCK. CLKPWMSEL: LCD Controller PWM Clock Source Selection 0: The slow clock is selected and feeds the PWM module. 1: The system clock is selected and feeds the PWM module. CGDISBASE: Clock Gating Disable Control for the Base Layer 0: Automatic Clock Gating is enabled for the Base Layer. 1: Clock is running continuously. CLKDIV: LCD Controller Clock Divider 8-bit width clock divider for pixel clock LCD_PCLK. pixel_clock = selected_clock / (CLKDIV + 2) where selected_clock is equal to system_clock when CLKSEL field is set to 0 and system_clock2x when CLKSEL is set to one. DS60001517A-page 938  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.2 LCD Controller Configuration Register 1 Name: LCDC_LCDCFG1 Address:0xF8038004 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VSPW HSPW HSPW: Horizontal Synchronization Pulse Width Width of the LCD_HSYNC pulse, given in pixel clock cycles. Width is (HSPW + 1) LCD_PCLK cycles. VSPW: Vertical Synchronization Pulse Width Width of the LCD_VSYNC pulse, given in number of lines. Width is (VSPW + 1) lines.  2017 Microchip Technology Inc. DS60001517A-page 939 SAM9N12/SAM9CN11/SAM9CN12 43.7.3 LCD Controller Configuration Register 2 Name: LCDC_LCDCFG2 Address:0xF8038008 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VBPW VFPW VFPW: Vertical Front Porch Width This field indicates the number of lines at the end of the Frame. The blanking interval is equal to (VFPW+1) lines. VBPW: Vertical Back Porch Width This field indicates the number of lines at the beginning of the Frame. The blanking interval is equal to VBPW lines. DS60001517A-page 940  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.4 LCD Controller Configuration Register 3 Name: LCDC_LCDCFG3 Address:0xF803800C Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 14 – 6 13 – 5 12 – 4 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 10 – 2 9 – 1 8 – 0 HBPW HFPW HFPW: Horizontal Front Porch Width Number of pixel clock cycles inserted at the end of the active line. The interval is equal to (HFPW + 1) LCD_PCLK cycles. HBPW: Horizontal Back Porch Width Number of pixel clock cycles inserted at the beginning of the line. The interval is equal to (HBPW + 1) LCD_PCLK cycles.  2017 Microchip Technology Inc. DS60001517A-page 941 SAM9N12/SAM9CN11/SAM9CN12 43.7.5 LCD Controller Configuration Register 4 Name: LCDC_LCDCFG4 Address:0xF8038010 Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 14 – 6 13 – 5 12 – 4 27 – 19 26 11 – 3 10 18 25 RPF 17 24 9 PPL 1 8 16 RPF 2 0 PPL RPF: Number of Active Rows Per Frame Number of active lines in the frame. The frame height is equal to (RPF + 1) lines. PPL: Number of Pixels Per Line Number of pixels in the frame. The number of active pixels in the frame is equal to (PPL + 1) pixels. DS60001517A-page 942  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.6 LCD Controller Configuration Register 5 Name: LCDC_LCDCFG5 Address:0xF8038014 Access: Read/Write 31 – 23 – 15 – 7 DISPDLY 30 – 22 – 14 – 6 DITHER 29 – 21 – 13 VSPHO 5 – 28 – 20 27 – 19 12 VSPSU 4 DISPPOL 11 – 3 VSPDLYE 26 – 18 GUARDTIME 10 – 2 VSPDLYS 25 – 17 24 – 16 9 8 MODE 1 VSPOL 0 HSPOL HSPOL: Horizontal Synchronization Pulse Polarity 0: Active High 1: Active Low VSPOL: Vertical Synchronization Pulse Polarity 0: Active High 1: Active Low VSPDLYS: Vertical Synchronization Pulse Start 0: The first active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. 1: The first active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. VSPDLYE: Vertical Synchronization Pulse End 0: The second active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. 1: The second active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. DISPPOL: Display Signal Polarity 0: Active High 1: Active Low DITHER: LCD Controller Dithering 0: Dithering logical unit is disabled. 1: Dithering logical unit is activated. DISPDLY: LCD Controller Display Power Signal Synchronization 0: the LCD_DISP signal is asserted synchronously with the second active edge of the horizontal pulse. 1: the LCD_DISP signal is asserted asynchronously with both edges of the horizontal pulse. MODE: LCD Controller Output Mode Value Name Description 0 OUTPUT_12BPP LCD output mode is set to 12 bits per pixel 1 OUTPUT_16BPP LCD output mode is set to 16 bits per pixel 2 OUTPUT_18BPP LCD output mode is set to 18 bits per pixel 3 OUTPUT_24BPP LCD output mode is set to 24 bits per pixel  2017 Microchip Technology Inc. DS60001517A-page 943 SAM9N12/SAM9CN11/SAM9CN12 VSPSU: LCD Controller Vertical Synchronization Pulse Setup Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. 1: The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse. VSPHO: LCD Controller Vertical Synchronization Pulse Hold Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. 1: The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse. GUARDTIME: LCD DISPLAY Guard Time Number of frames inserted during start up before LCD_DISP assertion. Number of frames inserted after LCD_DISP reset. DS60001517A-page 944  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.7 LCD Controller Configuration Register 6 Name: LCDC_LCDCFG6 Address:0xF8038018 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 7 – 6 – 5 – 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 PWMCVAL 4 3 PWMPOL – 2 1 PWMPS 0 PWMPS: PWM Clock Prescaler This field selects the configuration of the counter prescaler module. Value Name Description 0 DIV_1 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK 1 DIV_2 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK / 2 2 DIV_4 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK / 4 3 DIV_8 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK / 8 4 DIV_16 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK / 16 5 DIV_32 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK / 32 6 DIV_64 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK / 64 PWMPOL: LCD Controller PWM Signal Polarity This bit defines the polarity of the PWM output signal. 0: Output pulses are low level 1: Output pulses are high level (The output will be high whenever the value in the counter is less than the value CVAL). PWMCVAL: LCD Controller PWM Compare Value PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.  2017 Microchip Technology Inc. DS60001517A-page 945 SAM9N12/SAM9CN11/SAM9CN12 43.7.8 LCD Controller Enable Register Name: LCDC_LCDEN Address:0xF8038020 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 PWMEN 26 – 18 – 10 – 2 DISPEN 25 – 17 – 9 – 1 SYNCEN 24 – 16 – 8 – 0 CLKEN CLKEN: LCD Controller Pixel Clock Enable 0: No effect 1: Pixel clock logical unit is activated SYNCEN: LCD Controller Horizontal and Vertical Synchronization Enable 0: No effect 1: Both horizontal and vertical synchronization (LCD_VSYNC and LCD_HSYNC) signals are generated. DISPEN: LCD Controller DISP Signal Enable 0: No effect 1: LCD_DISP signal is generated PWMEN: LCD Controller Pulse Width Modulation Enable 0: No effect 1: PWM is enabled DS60001517A-page 946  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.9 LCD Controller Disable Register Name: LCDC_LCDDIS Address:0xF8038024 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 PWMRST 3 PWMDIS 26 – 18 – 10 DISPRST 2 DISPDIS 25 – 17 – 9 SYNCRST 1 SYNCDIS 24 – 16 – 8 CLKRST 0 CLKDIS CLKDIS: LCD Controller Pixel Clock Disable 0: No effect. 1: Disable the pixel clock. SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable 0: No effect. 1: Disable the synchronization signals after the end of the frame. DISPDIS: LCD Controller DISP Signal Disable 0: No effect. 1: Disable the DISP signal. PWMDIS: LCD Controller Pulse Width Modulation Disable 0: No effect. 1: Disable the pulse width modulation signal. CLKRST: LCD Controller Clock Reset 0: No effect. 1: Reset the pixel clock generator module. The pixel clock duty cycle may be violated. SYNCRST: LCD Controller Horizontal and Vertical Synchronization Reset 0: No effect. 1: Reset the timing engine. Both Horizontal and vertical pulse width are violated. DISPRST: LCD Controller DISP Signal Reset 0: No effect. 1: Reset the DISP signal. PWMRST: LCD Controller PWM Reset 0: No effect. 1: Reset the PWM module, the duty cycle may be violated.  2017 Microchip Technology Inc. DS60001517A-page 947 SAM9N12/SAM9CN11/SAM9CN12 43.7.10 LCD Controller Status Register Name: LCDC_LCDSR Address:0xF8038028 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 SIPSTS 27 – 19 – 11 – 3 PWMSTS 26 – 18 – 10 – 2 DISPSTS 25 – 17 – 9 – 1 LCDSTS 24 – 16 – 8 – 0 CLKSTS CLKSTS: Clock Status 0: Pixel Clock is disabled. 1: Pixel Clock is running. LCDSTS: LCD Controller Synchronization status 0: Timing Engine is disabled. 1: Timing Engine is running. DISPSTS: LCD Controller DISP Signal Status 0: DISP is disabled. 1: DISP signal is activated. PWMSTS: LCD Controller PWM Signal Status 0: PWM is disabled. 1: PWM signal is activated. SIPSTS: Synchronization In Progress 0: Clock domain synchronization is terminated. 1: A double domain synchronization is in progress, access to the LCDC_LCDEN and LCDC_LCDDIS registers has no effect. DS60001517A-page 948  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.11 LCD Controller Interrupt Enable Register Name: LCDC_LCDIER Address:0xF803802C Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRIE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISPIE 25 – 17 – 9 – 1 DISIE 24 – 16 – 8 BASEIE 0 SOFIE SOFIE: Start of Frame Interrupt Enable Register 0: No effect. 1: Enable the interrupt. DISIE: LCD Disable Interrupt Enable Register 0: No effect. 1: Enable the interrupt. DISPIE: Power UP/Down Sequence Terminated Interrupt Enable Register 0: No effect. 1: Enable the interrupt. FIFOERRIE: Output FIFO Error Interrupt Enable Register 0: No effect. 1: Enable the interrupt. BASEIE: Base Layer Interrupt Enable Register 0: No effect. 1: Enable the interrupt.  2017 Microchip Technology Inc. DS60001517A-page 949 SAM9N12/SAM9CN11/SAM9CN12 43.7.12 LCD Controller Interrupt Disable Register Name: LCDC_LCDIDR Address:0xF8038030 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRID 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISPID 25 – 17 – 9 – 1 DISID 24 – 16 – 8 BASEID 0 SOFID SOFID: Start of Frame Interrupt Disable Register 0: No effect. 1: Disable the interrupt. DISID: LCD Disable Interrupt Disable Register 0: No effect. 1: Disable the interrupt. DISPID: Power UP/Down Sequence Terminated Interrupt Disable Register 0: No effect. 1: Disable the interrupt. FIFOERRID: Output FIFO Error Interrupt Disable Register 0: No effect. 1: Disable the interrupt. BASEID: Base Layer Interrupt Disable Register 0: No effect. 1: Disable the interrupt. DS60001517A-page 950  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.13 LCD Controller Interrupt Mask Register Name: LCDC_LCDIMR Address:0xF8038034 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERRIM 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISPIM 25 – 17 – 9 – 1 DISIM 24 – 16 – 8 BASEIM 0 SOFIM SOFIM: Start of Frame Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. DISIM: LCD Disable Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. DISPIM: Power UP/Down Sequence Terminated Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. FIFOERRIM: Output FIFO Error Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. BASEIM: Base Layer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled.  2017 Microchip Technology Inc. DS60001517A-page 951 SAM9N12/SAM9CN11/SAM9CN12 43.7.14 LCD Controller Interrupt Status Register Name: LCDC_LCDISR Address:0xF8038038 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 FIFOERR 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 DISP 25 – 17 – 9 – 1 DIS 24 – 16 – 8 BASE 0 SOF SOF: Start of Frame Interrupt Status Register When set to one this flag indicates that a start of frame event has been detected. This flag is reset after a read operation. DIS: LCD Disable Interrupt Status Register When set to one this flag indicates that the horizontal and vertical timing generator has been successfully disabled. This flag is reset after a read operation. DISP: Power-up/Power-down Sequence Terminated Interrupt Status Register When set to one this flag indicates whether the power-up sequence or power-down sequence has terminated. This flag is reset after a read operation. FIFOERR: Output FIFO Error When set to one this flag indicates that an underflow occurs in the output FIFO. This flag is reset after a read operation. BASE: Base Layer Raw Interrupt Status Register When set to one this flag indicates that a Base layer interrupt is pending. This flag is reset as soon as the BASEISR register is read. DS60001517A-page 952  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.15 Base Layer Channel Enable Register Name: LCDC_BASECHER Address:0xF8038040 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN CHEN: Channel Enable Register 0: No effect. 1: Enable the DMA channel. UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: update windows attributes on the next start of frame. A2QEN: Add Head Pointer Enable Register Write this field to one to add the head pointer to the descriptor list. This field is reset by hardware as soon as the head register is added to the list.  2017 Microchip Technology Inc. DS60001517A-page 953 SAM9N12/SAM9CN11/SAM9CN12 43.7.16 Base Layer Channel Disable Register Name: LCDC_BASECHDR Address:0xF8038044 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. DS60001517A-page 954  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.17 Base Layer Channel Status Register Name: LCDC_BASECHSR Address:0xF8038048 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending.  2017 Microchip Technology Inc. DS60001517A-page 955 SAM9N12/SAM9CN11/SAM9CN12 43.7.18 Base Layer Interrupt Enable Register Name: LCDC_BASEIER Address:0xF803804C Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. DS60001517A-page 956  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.19 Base Layer Interrupt Disable Register Name: LCDC_BASEIDR Address:0xF8038050 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled.  2017 Microchip Technology Inc. DS60001517A-page 957 SAM9N12/SAM9CN11/SAM9CN12 43.7.20 Base Layer Interrupt Mask Register Name: LCDC_BASEIMR Address:0xF8038054 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. DS60001517A-page 958  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.21 Base Layer Interrupt Status Register Name: LCDC_BASEISR Address:0xF8038058 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. DONE: End of List Detected When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation.  2017 Microchip Technology Inc. DS60001517A-page 959 SAM9N12/SAM9CN11/SAM9CN12 43.7.22 Base Layer Head Register Name: LCDC_BASEHEAD Address:0xF803805C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD 23 22 21 20 15 14 13 12 HEAD HEAD 7 6 5 4 HEAD HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. DS60001517A-page 960  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.23 Base Layer Address Register Name: LCDC_BASEADDR Address:0xF8038060 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 15 14 13 12 ADDR ADDR 7 6 5 4 ADDR ADDR: DMA Transfer Start Address Frame buffer base address.  2017 Microchip Technology Inc. DS60001517A-page 961 SAM9N12/SAM9CN11/SAM9CN12 43.7.24 Base Layer Control Register Name: LCDC_BASECTRL Address:0xF8038064 Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is disabled. DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. DS60001517A-page 962  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.25 Base Layer Next Register Name: LCDC_BASENEXT Address:0xF8038068 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT 23 22 21 20 15 14 13 12 NEXT NEXT 7 6 5 4 NEXT NEXT: DMA Descriptor Next Address DMA Descriptor next address, this address must be word aligned.  2017 Microchip Technology Inc. DS60001517A-page 963 SAM9N12/SAM9CN11/SAM9CN12 43.7.26 Base Layer Configuration 0 Register Name: LCDC_BASECFG0 Address:0xF803806C Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 – BLEN: AHB Burst Length Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one 32-bit data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of four 32-bit data. An AHB INCR4 Burst is preferred. SINGLE, INCR and INCR4 bursts can be used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of eight 32-bit data. An AHB INCR8 Burst is preferred. SINGLE, INCR, INCR4 and INCR8 bursts can be used. INCR is used for a burst of 2 and 3 beats. 3 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of sixteen 32-bit data. An AHB INCR16 Burst is preferred. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts can be used. INCR is used for a burst of 2 and 3 beats. DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). DS60001517A-page 964  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.27 Base Layer Configuration 1 Register Name: LCDC_BASECFG1 Address:0xF8038070 Access: Read/Write 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 20 – 12 5 4 – RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN CLUTEN: Color Lookup Table Mode Enable 0: RGB mode is selected. 1: Color lookup table is selected. RGBMODE: RGB Mode Input Selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666_PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 CLUTMODE: Color Lookup Table Mode Input Selection Value Name Description 0 1BPP color lookup table mode set to 1 bit per pixel 1 2BPP color lookup table mode set to 2 bits per pixel 2 4BPP color lookup table mode set to 4 bits per pixel 3 8BPP color lookup table mode set to 8 bits per pixel  2017 Microchip Technology Inc. DS60001517A-page 965 SAM9N12/SAM9CN11/SAM9CN12 43.7.28 Base Layer Configuration 2 Register Name: LCDC_BASECFG2 Address:0xF8038074 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE 23 22 21 20 15 14 13 12 XSTRIDE XSTRIDE 7 6 5 4 XSTRIDE XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. DS60001517A-page 966  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.29 Base Layer Configuration 3 Register Name: LCDC_BASECFG3 Address:0xF8038078 Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF 7 6 5 4 BDEF RDEF: Red Default Default Red color when the Base DMA channel is disabled. GDEF: Green Default Default Green color when the Base DMA channel is disabled. BDEF: Blue Default Default Blue color when the Base DMA channel is disabled.  2017 Microchip Technology Inc. DS60001517A-page 967 SAM9N12/SAM9CN11/SAM9CN12 43.7.30 Base Layer Configuration 4 Register Name: LCDC_BASECFG4 Address:0xF803807C Access: Read/Write 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REP 1 – 24 – 16 – 8 DMA 0 – DMA: Use DMA Data Path 0: The default color is used on the Base Layer. 1: The DMA channel retrieves the pixels stream from the memory. REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the MSB. DS60001517A-page 968  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 43.7.31 Base CLUT Register x Register Name: LCDC_BASECLUTx [x=0..255] Address: 0xF8038400 Access: Read/Write 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RCLUT GCLUT 7 6 5 4 BCLUT BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table.  2017 Microchip Technology Inc. DS60001517A-page 969 SAM9N12/SAM9CN11/SAM9CN12 44. Advanced Encryption Standard (AES) 44.1 Description The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-38A Recommendation. It is compatible with all these modes via DMA Controller channels, minimizing processor intervention for large buffer transfers. The 128-bit/192-bit/256-bit key is stored in four/six/eight 32-bit write-only AES Key Word Registers (AES_KEYWR0–3). The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit write-only AES Input Data Registers (AES_IDATAR0–3) and AES Initialization Vector Registers (AES_IVR0–3). As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data are ready to be read out on the four 32-bit AES Output Data Registers (AES_ODATAR0–3) or through the DMA channels. 44.2 Embedded Characteristics • • • • • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) 128-bit/192-bit/256-bit Cryptographic Key 12/14/16 Clock Cycles Encryption/Decryption Processing Time with a 128-bit/192-bit/256-bit Cryptographic Key Double Input Buffer Optimizes Runtime Support of the Modes of Operation Specified in the NIST Special Publication 800-38A: - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) including CBC-MAC - Cipher Feedback (CFB) - Output Feedback (OFB) - Counter (CTR) • 8, 16, 32, 64 and 128-bit Data Sizes Possible in CFB Mode • Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation • Connection to DMA Optimizes Data Transfers for all Operating Modes 44.3 Product Dependencies 44.3.1 Power Management The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to configure the PMC to enable the AES clock. 44.3.2 Interrupt The AES interface has an interrupt line connected to the Interrupt Controller. Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES. Table 44-1: 44.4 Peripheral IDs Instance ID AES 29 Functional Description The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection between the encryption and the decryption processes. DS60001517A-page 970  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. This 128-bit/192bit/256-bit key is defined in the AES_KEYWRx. The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector (IV), which must be set in the AES_IVRx. The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The AES_IVRx are also used by the CTR mode to set the counter value. 44.4.1 AES Register Endianism In Arm processor-based products, the system bus and processors manipulate data in little-endian form. The AES interface requires littleendian format words. However, in accordance with the protocol of the FIPS 197 specification, data is collected, processed and stored by the AES algorithm in big-endian form. The following example illustrates how to configure the AES: If the first 64 bits of a message (according to FIPS 197, i.e., big-endian format) to be processed is 0xcafedeca_01234567, then the AES_IDATAR0 and AES_IDATAR1 registers must be written with the following pattern: • AES_IDATAR0 = 0xcadefeca • AES_IDATAR1 = 0x67452301 44.4.2 Operation Modes The AES supports the following modes of operation: • • • • ECB: Electronic Code Book CBC: Cipher Block Chaining OFB: Output Feedback CFB: Cipher Feedback - CFB8 (CFB where the length of the data segment is 8 bits) - CFB16 (CFB where the length of the data segment is 16 bits) - CFB32 (CFB where the length of the data segment is 32 bits) - CFB64 (CFB where the length of the data segment is 64 bits) - CFB128 (CFB where the length of the data segment is 128 bits) • CTR: Counter The data pre-processing, post-processing and data chaining for the concerned modes are automatically performed. Refer to the NIST Special Publication 800-38A for more complete information. These modes are selected by setting the OPMOD field in the AES_MR. In CFB mode, five data sizes are possible (8, 16, 32, 64 or 128 bits), configurable by means of the CFBS field in the AES_MR (Section 44.5.2 “AES Mode Register”). In CTR mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after processing 1 megabyte of data. If the file to be processed is greater than 1 megabyte, this file must be split into fragments of 1 megabyte or less for the first fragment if the initial value of the counter is greater than 0. Prior to loading the first fragment into AES_IDATARx, AES_IVRx must be fully programmed with the initial counter value. For any fragment, after the transfer is completed and prior to transferring the next fragment, AES_IVRx must be programmed with the appropriate counter value. If the initial value of the counter is greater than 0 and the data buffer size to be processed is greater than 1 megabyte, the size of the first fragment to be processed must be 1 megabyte minus 16x(initial value) to prevent a rollover of the internal 1-bit counter. To have a sequential increment, the counter value must be programmed with the value programmed for the previous fragment + 216 (or less for the first fragment). All AES_IVRx fields must be programmed to take into account the possible carry propagation. 44.4.3 Double Input Buffer The AES_IDATARx can be double-buffered to reduce the runtime of large files. This mode allows writing a new message block when the previous message block is being processed. This is only possible when DMA accesses are performed (SMOD = 0x2). The DUALBUFF bit in the AES_MR must be set to ‘1’ to access the double buffer.  2017 Microchip Technology Inc. DS60001517A-page 971 SAM9N12/SAM9CN11/SAM9CN12 44.4.4 Start Modes The SMOD field in the AES_MR allows selection of the encryption (or decryption) Start mode. 44.4.4.1 Manual Mode The sequence order is as follows: 1. 2. 3. Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD. Write the 128-bit/192-bit/256-bit key in the AES_KEYWRx. Write the initialization vector (or counter) in the AES_IVRx. Note: 4. 5. 6. 7. 8. The AES_IVRx concern all modes except ECB. Set the bit DATRDY (Data Ready) in the AES Interrupt Enable Register (AES_IER), depending on whether an interrupt is required or not at the end of processing. Write the data to be encrypted/decrypted in the authorized AES_IDATARx (see Table 44-2). Set the START bit in the AES Control Register (AES_CR) to begin the encryption or the decryption process. When processing completes, the DATRDY flag in the AES Interrupt Status Register (AES_ISR) is raised. If an interrupt has been enabled by setting the DATRDY bit in the AES_IER, the interrupt line of the AES is activated. When software reads one of the AES_ODATARx, the DATRDY bit is automatically cleared. Table 44-2: Authorized Input Data Registers Operation Mode Input Data Registers to Write ECB All CBC All OFB All 128-bit CFB All 64-bit CFB AES_IDATAR0 and AES_IDATAR1 32-bit CFB AES_IDATAR0 16-bit CFB AES_IDATAR0 8-bit CFB AES_IDATAR0 CTR All Note 1: In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing. 2: In 32, 16, and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing. 44.4.4.2 Auto Mode The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of AES_IDATARx is written, processing is automatically started without any action in the AES_CR. 44.4.4.3 DMA Mode The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without any action by software during processing. The SMOD field in the AES_MR must be configured to 0x2 and the DMA must be configured with non-incremental addresses. The start address of any transfer descriptor must be configured with the address of AES_IDATAR0. The DMA chunk size configuration depends on the AES mode of operation and is listed in Table 44-3 “DMA Data Transfer Type for the Different Operation Modes”. DS60001517A-page 972  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 When writing data to AES with a first DMA channel, data are first fetched from a memory buffer (source data). It is recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data size depends on the mode of operation. When reading data from the AES with the second DMA channel, the source data is the data read from AES and data destination is the memory buffer. In this case, the source data size depends on the AES mode of operation and is listed in Table 44-3. Table 44-3: 44.4.5 DMA Data Transfer Type for the Different Operation Modes Operation Mode Chunk Size Destination/Source Data Transfer Type ECB 4 Word CBC 4 Word OFB 4 Word CFB 128-bit 4 Word CFB 64-bit 1 Word CFB 32-bit 1 Word CFB 16-bit 1 Half-word CFB 8-bit 1 Byte CTR 4 Word Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption algorithm (CBCMAC algorithm for example). After each end of encryption/decryption, the output data are available either on the AES_ODATARx for Manual and Auto mode or at the address specified in the receive buffer pointer for DMA mode (see Table 44-4 “Last Output Data Mode Behavior versus Start Modes”). The Last Output Data (LOD) bit in the AES_MR allows retrieval of only the last data of several encryption/decryption processes. Therefore, there is no need to define a read buffer in DMA mode. This data are only available on the AES_ODATARx. 44.4.5.1 Manual and Auto Modes • If AES_MR.LOD = 0 The DATRDY flag is cleared when at least one of the AES_ODATARx is read (see Figure 44-1). Figure 44-1: Manual and Auto Modes with AES_MR.LOD = 0 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx register(s) (Auto mode) Read the AES_ODATARx DATRDY Encryption or Decryption Process If the user does not want to read the AES_ODATARx between each encryption/decryption, the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user cannot know the end of the following encryptions/decryptions. • If AES_MR.LOD = 1 This mode is optimized to process AES CPC-MAC operating mode. The DATRDY flag is cleared when at least one AES_IDATAR is written (see Figure 44-2). No more AES_ODATAR reads are necessary between consecutive encryptions/decryptions.  2017 Microchip Technology Inc. DS60001517A-page 973 SAM9N12/SAM9CN11/SAM9CN12 Figure 44-2: Manual and Auto Modes with AES_MR.LOD = 1 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx register(s) (Auto mode) Write AES_IDATARx register(s) DATRDY Encryption or Decryption Process 44.4.5.2 DMA Mode • If AES_MR.LOD = 0 This mode may be used for all AES operating modes except CBC-MAC where AES_MR.LOD = 1 mode is recommended. The end of the encryption/decryption is indicated by the end of DMA transfer associated to AES_ODATARx (see Figure 44-3). Two DMA channels are required: one for writing message blocks to AES_IDATARx and one to obtain the result from AES_ODATARx. Figure 44-3: DMA Transfer with AES_MR.LOD = 0 Enable DMA Channels associated to AES_IDATARx and AES_ODATARx Multiple Encryption or Decryption Processes DMA Buffer transfer complete flag /channel m Write accesses into AES_IDATARx Read accesses into AES_ODATARx DMA Buffer transfer complete flag /channel n Message fully processed (cipher or decipher) last block can be read • If AES_MR.LOD = 1 This mode is optimized to process AES CBC-MAC operating mode. The user must first wait for the DMA buffer transfer complete flag, then for the flag DATRDY to rise to ensure that the encryption/decryption is completed (see Figure 44-4). In this case, no receive buffers are required. The output data are only available on the AES_ODATARx. Figure 44-4: DMA Transfer with AES_MR.LOD = 1 Enable DMA Channels associated with AES_IDATARx and AES_ODATARx registers Multiple Encryption or Decryption Processes DMA status flag for end of buffer transfer Write accesses into AES_IDATARx DATRDY Message fully transferred Message fully processed (cipher or decipher) MAC result can be read Table 44-4 summarizes the different cases. DS60001517A-page 974  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 44-4: Last Output Data Mode Behavior versus Start Modes Manual and Auto Modes Sequence AES_MR.LOD = 0 DATRDY Flag Clearing Condition(1) At least one AES_ODATAR must be read At least one AES_IDATAR must be written Not used Managed by the DMA DATRDY DATRDY 2 DMA Buffer transfer complete flags (channel m and channel n) DMA buffer transfer complete flag, then AES DATRDY flag In the AES_ODATARx In the AES_ODATARx At the address specified in the Channel Buffer Transfer Descriptor In the AES_ODATARx End of Encryption/ Decryption Notification Encrypted/Decrypted Data Result Location AES_MR.LOD = 1 DMA Transfer AES_MR.LOD = 0 AES_MR.LOD = 1 Note 1: Depending on the mode, there are other ways of clearing the DATRDY flag. See Section 44.5.6 “AES Interrupt Status Register”. Warning: In DMA mode, reading the AES_ODATARx before the last data transfer may lead to unpredictable results. 44.4.6 44.4.6.1 Security Features Unspecified Register Access Detection When an unspecified register access occurs, the URAD flag in the AES_ISR is raised. Its source is then reported in the Unspecified Register Access Type (URAT) field. Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: • • • • • • Input Data Register written during the data processing when SMOD = IDATAR0_START Output Data Register read during data processing Mode Register written during data processing Output Data Register read during sub-keys generation Mode Register written during sub-keys generation Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in the AES_CR.  2017 Microchip Technology Inc. DS60001517A-page 975 SAM9N12/SAM9CN11/SAM9CN12 44.5 Advanced Encryption Standard (AES) User Interface Table 44-5: Offset Register Mapping Register Name Access Reset 0x00 Control Register AES_CR Write-only – 0x04 Mode Register AES_MR Read/Write 0x0 Reserved – – – 0x10 Interrupt Enable Register AES_IER Write-only – 0x14 Interrupt Disable Register AES_IDR Write-only – 0x18 Interrupt Mask Register AES_IMR Read-only 0x0 0x1C Interrupt Status Register AES_ISR Read-only 0x0 0x20 Key Word Register 0 AES_KEYWR0 Write-only – 0x24 Key Word Register 1 AES_KEYWR1 Write-only – 0x28 Key Word Register 2 AES_KEYWR2 Write-only – 0x2C Key Word Register 3 AES_KEYWR3 Write-only – 0x30 Key Word Register 4 AES_KEYWR4 Write-only – 0x34 Key Word Register 5 AES_KEYWR5 Write-only – 0x38 Key Word Register 6 AES_KEYWR6 Write-only – 0x3C Key Word Register 7 AES_KEYWR7 Write-only – 0x40 Input Data Register 0 AES_IDATAR0 Write-only – 0x44 Input Data Register 1 AES_IDATAR1 Write-only – 0x48 Input Data Register 2 AES_IDATAR2 Write-only – 0x4C Input Data Register 3 AES_IDATAR3 Write-only – 0x50 Output Data Register 0 AES_ODATAR0 Read-only 0x0 0x54 Output Data Register 1 AES_ODATAR1 Read-only 0x0 0x58 Output Data Register 2 AES_ODATAR2 Read-only 0x0 0x5C Output Data Register 3 AES_ODATAR3 Read-only 0x0 0x60 Initialization Vector Register 0 AES_IVR0 Write-only – 0x64 Initialization Vector Register 1 AES_IVR1 Write-only – 0x68 Initialization Vector Register 2 AES_IVR2 Write-only – 0x6C Initialization Vector Register 3 AES_IVR3 Write-only – 0x08–0x0C 0x70–0xAC Reserved – – – 0xB0–0xFC Reserved – – – DS60001517A-page 976  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 44.5.1 AES Control Register Name: AES_CR Address:0xF000C000 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START START: Start Processing 0: No effect. 1: Starts manual encryption/decryption process. SWRST: Software Reset 0: No effect. 1: Resets the AES. A software-triggered hardware reset of the AES interface is performed.  2017 Microchip Technology Inc. DS60001517A-page 977 SAM9N12/SAM9CN11/SAM9CN12 44.5.2 AES Mode Register Name: AES_MR Address:0xF000C004 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 CKEY 15 – 14 13 LOD 12 11 OPMOD 7 6 5 PROCDLY CFBS 10 9 KEYSIZE 4 8 SMOD 3 2 1 0 DUALBUFF – – CIPHER CIPHER: Processing Mode 0: Decrypts data. 1: Encrypts data. DUALBUFF: Dual Input Buffer Value Name Description 0 INACTIVE AES_IDATARx cannot be written during processing of previous block. 1 ACTIVE AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. PROCDLY: Processing Delay Processing Time = N × (PROCDLY + 1) where N = 10 when KEYSIZE = 0 N = 12 when KEYSIZE = 1 N = 14 when KEYSIZE = 2 The processing time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption. Note: The best performance is achieved with PROCDLY equal to 0. SMOD: Start Mode Value Name Description 0 MANUAL_START Manual Mode 1 AUTO_START Auto Mode 2 IDATAR0_START AES_IDATAR0 access only Auto Mode (DMA) Values which are not listed in the table must be considered as “reserved”. If a DMA transfer is used, configure SMOD to 0x2. Refer to Section 44.4.4.3 “DMA Mode” for more details. DS60001517A-page 978  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 KEYSIZE: Key Size Value Name Description 0 AES128 AES Key Size is 128 bits 1 AES192 AES Key Size is 192 bits 2 AES256 AES Key Size is 256 bits Values which are not listed in the table must be considered as “reserved”. OPMOD: Operation Mode Value Name Description 0 ECB ECB: Electronic Code Book mode 1 CBC CBC: Cipher Block Chaining mode 2 OFB OFB: Output Feedback mode 3 CFB CFB: Cipher Feedback mode 4 CTR CTR: Counter mode (16-bit internal counter) Values which are not listed in the table must be considered as “reserved”. For CBC-MAC operating mode, set OPMOD to CBC and LOD to 1. LOD: Last Output Data Mode 0: No effect. After each end of encryption/decryption, the output data are available either on the output data registers (Manual and Auto modes) or at the address specified in the Channel Buffer Transfer Descriptor for DMA mode. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1: The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions (see Section 44.4.5 “Last Output Data Mode”). Warning: In DMA mode, reading to the Output Data registers before the last data encryption/decryption process may lead to unpredictable results. CFBS: Cipher Feedback Data Size Value Name Description 0 SIZE_128BIT 128-bit 1 SIZE_64BIT 64-bit 2 SIZE_32BIT 32-bit 3 SIZE_16BIT 16-bit 4 SIZE_8BIT 8-bit Values which are not listed in table must be considered as “reserved”. CKEY: Key Value 0xE Name Description PASSWD This field must be written with 0xE the first time the AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE. Always reads as 0.  2017 Microchip Technology Inc. DS60001517A-page 979 SAM9N12/SAM9CN11/SAM9CN12 44.5.3 AES Interrupt Enable Register Name: AES_IER Address:0xF000C010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. DATRDY: Data Ready Interrupt Enable URAD: Unspecified Register Access Detection Interrupt Enable DS60001517A-page 980  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 44.5.4 AES Interrupt Disable Register Name: AES_IDR Address:0xF000C014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. DATRDY: Data Ready Interrupt Disable URAD: Unspecified Register Access Detection Interrupt Disable  2017 Microchip Technology Inc. DS60001517A-page 981 SAM9N12/SAM9CN11/SAM9CN12 44.5.5 AES Interrupt Mask Register Name: AES_IMR Address:0xF000C018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. DATRDY: Data Ready Interrupt Mask URAD: Unspecified Register Access Detection Interrupt Mask DS60001517A-page 982  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 44.5.6 AES Interrupt Status Register Name: AES_ISR Address:0xF000C01C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) 0: Output data not valid. 1: Encryption or decryption process is completed. Note: If AES_MR.LOD = 1: In Manual and Auto mode, the DATRDY flag can also be cleared by writing at least one AES_IDATARx. URAD: Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAT: Unspecified Register Access (cleared by writing SWRST in AES_CR) Value Name Description 0 IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD = 0x2 mode. 1 ODR_RD_PROCESSING Output Data Register read during the data processing. 2 MR_WR_PROCESSING Mode Register written during the data processing. 3 ODR_RD_SUBKGEN Output Data Register read during the sub-keys generation. 4 MR_WR_SUBKGEN Mode Register written during the sub-keys generation. 5 WOR_RD_ACCESS Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field.  2017 Microchip Technology Inc. DS60001517A-page 983 SAM9N12/SAM9CN11/SAM9CN12 44.5.7 AES Key Word Register x Name: AES_KEYWRx [x=0..7] Address:0xF000C020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEYW 23 22 21 20 KEYW 15 14 13 12 KEYW 7 6 5 4 KEYW KEYW: Key Word The four/six/eight 32-bit Key Word Registers set the 128-bit/192-bit/256-bit cryptographic key used for AES encryption/decryption. AES_KEYWR0 corresponds to the first word of the key and respectively AES_KEYWR3/AES_KEYWR5/AES_KEYWR7 to the last one. These registers are write-only to prevent the key from being read by another application. DS60001517A-page 984  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 44.5.8 AES Input Data Register x Name: AES_IDATARx [x=0..3] Address:0xF000C040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA IDATA: Input Data Word The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption. AES_IDATAR0 corresponds to the first word of the data to be encrypted/decrypted, and AES_IDATAR3 to the last one. These registers are write-only to prevent the input data from being read by another application.  2017 Microchip Technology Inc. DS60001517A-page 985 SAM9N12/SAM9CN11/SAM9CN12 44.5.9 AES Output Data Register x Name: AES_ODATARx [x=0..3] Address:0xF000C050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted. AES_ODATAR0 corresponds to the first word, AES_ODATAR3 to the last one. DS60001517A-page 986  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 44.5.10 AES Initialization Vector Register x Name: AES_IVRx [x=0..3] Address:0xF000C060 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV IV: Initialization Vector The four 32-bit Initialization Vector Registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input. AES_IVR0 corresponds to the first word of the Initialization Vector, AES_IVR3 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application. For CBC, OFB and CFB modes, the IV input value corresponds to the initialization vector. For CTR mode, the IV input value corresponds to the initial counter value. Note: These registers are not used in ECB mode and must not be written.  2017 Microchip Technology Inc. DS60001517A-page 987 SAM9N12/SAM9CN11/SAM9CN12 45. Secure Hash Algorithm (SHA) 45.1 Description The Secure Hash Algorithm (SHA) is compliant with the American FIPS (Federal Information Processing Standard) Publication 180-2 specification. The 512-bit block of message is respectively stored in 16 x 32-bit registers, (SHA_IDATARx/SHA_ODATARx) which are write-only. As soon as the input data is written, the hash processing may be started. The registers comprising the block of a padded message must be entered consecutively. Then the message digest is ready to be read out on the 5 up to 8 x 32-bit output data registers (SHA_ODATARx) or through the DMA channels. 45.2 Embedded Characteristics • Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, ) • Compliant with FIPS Publication 180-2 • Configurable Processing Period: - 85 Clock Cycles to obtain a fast SHA1 runtime or 209 Clock Cycles for Maximizing Bandwidth of Other Applications - 72 Clock Cycles to obtain a fast SHA224, SHA256 runtime or 194 Clock Cycles for Maximizing Bandwidth of Other Applications • Connection to DMA Channel Capabilities Optimizes Data Transfers • Double Input Buffer Optimizes Runtime 45.3 Product Dependencies 45.3.1 Power Management The SHA may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the SHA clock. 45.3.2 Interrupt Sources The SHA interface has an interrupt line connected to the Interrupt Controller. Handling the SHA interrupt requires programming the interrupt controller before configuring the SHA. Table 45-1: Peripheral IDs Instance ID SHA 27 45.4 Functional Description The Secure Hash Algorithm (SHA) module requires a padded message according to FIPS180-2 specification. The first block of the message must be indicated to the module by a specific command. The SHA module produces an N-bit message digest each time a block is written and processing period ends, where N is 160 for SHA1, 224 for SHA224,256 for SHA256. 45.4.1 SHA Algorithm The SHA can process SHA1, SHA224, SHA256 by configuring the ALGO field in the SHA Mode register (SHA_MR). 45.4.2 Processing Period The processing period can be configured. The short processing period allocates bandwidth to the SHA module, whereas the long processing period allocates more bandwidth on the system bus to other applications. An example is DMA channels not associated with SHA. In SHA1 mode, the shortest processing period is 85 clock cycles + 2 clock cycles for start command synchronization. The longest period is 209 clock cycles + 2 clock cycles. In SHA256 and SHA224 mode, the shortest processing period is 72 clock cycles + 2 clock cycles for start command synchronization. The longest period is 194 clock cycles + 2 clock cycles. DS60001517A-page 988  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 45.4.3 Double Input Buffer The SHA Input Data registers (SHA_IDATARx) can be double-buffered to reduce the runtime of large files. Double-buffering allows a new message block to be written while the previous message block is being processed. This is only possible when DMA accesses are performed (SMOD = 2). The DUALBUFF bit in the SHA_MR must be set to have double input buffer access. 45.4.4 Start Modes The SMOD field in the SHA_MR is used to select the Hash Processing Start mode. 45.4.4.1 Manual Mode In Manual mode, the sequence is as follows: 1. 2. 3. 4. 5. 6. 7. Set the bit DATRDY (Data Ready) in the SHA_IER, depending on whether an interrupt is required at the end of processing. For the first block of a message, the FIRST command must be set by writing a 1 into the corresponding bit of the SHA Control Register (SHA_CR). For the other blocks, there is nothing to write. Write the block to be processed in the SHA_IDATARx. To begin processing, set the START bit in the SHA_CR. When processing is completed, the bit DATRDY in the Interrupt Status register (SHA_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated. Repeat the write procedure for each block, start procedure and wait for the interrupt procedure up to the last block of the entire message. Each time the start procedure is complete, the DATRDY flag is cleared. After the last block is processed (DATRDY flag is set, if an interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated), read the message digest in the Output Data Registers. The DATRDY flag is automatically cleared when reading the SHA_ODATARx registers. 45.4.4.2 Auto Mode In Auto mode, processing starts as soon as the correct number of SHA_IDATARx is written. No action in the SHA_CR is necessary. 45.4.4.3 DMA Mode The DMA can be used in association with the SHA to perform the algorithm on a complete message without any action by the software during processing. The SMOD field in SHA_MR must be configured to 2. The DMA must be configured with non-incremental addresses. The start address of any transfer descriptor must be set to point to the SHA_IDATAR0. The DMA chunk size must be set to transfer, for each trigger request, 16 words of 32 bits. The FIRST bit of the SHA_CR must be set before starting the DMA when the first block is transferred. The DMA generates an interrupt when the end of buffer transfer is completed but the SHA processing is still in progress. The end of SHA processing is indicated by the flag DATRDY in the SHA_SR. The end of SHA processing requires two interrupts to be verified. The DMA end of transfer interrupt must be verified first, then the SHA DATRDY interrupt must be enabled and verified (see Figure 45-1).  2017 Microchip Technology Inc. DS60001517A-page 989 SAM9N12/SAM9CN11/SAM9CN12 Figure 45-1: interrupts Processing with DMA Enable DMA Channels associated with SHA_IDATARx registers Message Processing (Multiple Block) DMA status flag for end of buffer transfer Write accesses into SHA_IDATARx DATRDY Message fully transferred 45.4.4.4 Message fully processed SHA result can be read SHA Register Endianism In Arm processor-based products, the system bus and processors manipulate data in little-endian form. The SHA interface requires littleendian format words. However, in accordance with the protocol of FIPS 180-2 specification, data is collected, processed and stored by the SHA algorithm in big-endian form. The following example illustrates how to configure the SHA: If the first 64 bits of a message (according to FIPS 180-2, i.e., big-endian format) to be processed is 0xcafedeca_01234567, then the SHA_IDATAR0 and SHA_IDATAR1 registers must be written with the following pattern: • SHA_IDATAR0 = 0xcadefeca • SHA_IDATAR1 = 0x67452301 In a little-endian system, the message (according to FIPS 180-2) starting with pattern 0xcafedeca_01234567 is stored into memory as follows: - 0xca stored at initial offset (for example 0x00), then 0xfe stored at initial offset + 1 (i.e., 0x01), 0xde stored at initial offset + 2 (i.e., 0x02), 0xca stored at initial offset + 3 (i.e., 0x03). If the message is received through a serial-to-parallel communication channel, the first received character is 0xca and it is stored at the first memory location (initial offset). The second byte, 0xfe, is stored at initial offset + 1. When reading on a 32-bit little-endian system bus, the first word read back from system memory is 0xcadefeca. When the SHA_ODATARx registers are read, the hash result is organized in little-endian format, allowing system memory storage in the same format as the message. Taking an example from the FIPS 180-2 specification Appendix B.1, the endianism conversion can be observed. For this example, the 512-bit message is: 0x6162638000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000018 and the expected SHA-256 result is: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad If the message has not already been stored in the system memory, the first step is to convert the input message to little-endian before writing to the SHA_IDATARx registers. This would result in a write of: SHA_IDATAR0 = 0x80636261...... SHA_IDATAR15 = 0x18000000 The data in the output message digest registers, SHA_ODATARx, contain SHA_ODATAR0 = 0xbf1678ba... SHA_ODATAR7 = 0xad1500f2 which is the little-endian format of 0xba7816bf,..., 0xf20015ad. Reading SHA_ODATAR0 to SHA_ODATAR1 and storing into a little-endian memory system forces hash results to be stored in the same format as the message. When the output message is read, the user can convert back to big-endian for a resulting message value of: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad DS60001517A-page 990  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 45.4.5 Security Features When an unspecified register access occurs, the URAD bit in the SHA_ISR is set. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: • • • • SHA_IDATARx written during data processing in DMA mode SHA_ODATARx read during data processing SHA_MR written during data processing Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in the SHA_CR.  2017 Microchip Technology Inc. DS60001517A-page 991 SAM9N12/SAM9CN11/SAM9CN12 45.5 Secure Hash Algorithm (SHA) User Interface Table 45-2: Offset Register Mapping Register Name Access Reset 0x00 Control Register SHA_CR Write-only – 0x04 Mode Register SHA_MR Read/Write 0x0000100 Reserved – – – 0x10 Interrupt Enable Register SHA_IER Write-only – 0x14 Interrupt Disable Register SHA_IDR Write-only – 0x18 Interrupt Mask Register SHA_IMR Read-only 0x0 0x1C Interrupt Status Register SHA_ISR Read-only 0x0 Reserved – – – Input Data 0 Register SHA_IDATAR0 Write-only – ... ... ... ... 0x7C Input Data 15 Register SHA_IDATAR15 Write-only – 0x80 Output Data 0 Register SHA_ODATAR0 Read-only 0x0 ... ... ... ... Output Data 7 Register SHA_ODATAR7 Read-only 0x0 Reserved – – – 0x08–0x0C 0x20–0x3C 0x40 ... ... 0x9C 0xA0–0xFC DS60001517A-page 992  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 45.5.1 SHA Control Register Name: SHA_CR Address:0xF0014000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – FIRST – – – START START: Start Processing 0: No effect. 1: Starts manual hash algorithm process. FIRST: First Block of a Message 0: No effect. 1: Indicates that the next block to process is the first one of a message. SWRST: Software Reset 0: No effect. 1: Resets the SHA. A software-triggered hardware reset of the SHA interface is performed.  2017 Microchip Technology Inc. DS60001517A-page 993 SAM9N12/SAM9CN11/SAM9CN12 45.5.2 SHA Mode Register Name: SHA_MR Address:0xF0014004 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – DUALBUFF 15 14 13 12 11 10 9 8 – – – – ALGO 7 6 5 4 3 2 – – – PROCDLY – – 1 0 SMOD SMOD: Start Mode Value Name Description 0 MANUAL_START Manual Mode 1 AUTO_START Auto Mode 2 IDATAR0_START SHA_IDATAR0 access only Auto Mode Values not listed in the table must be considered as “reserved”. If a DMA transfer is used, configure the SMOD value with 1 or 2. Refer to Section 45.4.4.3 “DMA Mode” for more details. PROCDLY: Processing Delay Value Name Description 0 SHORTEST SHA processing runtime is the shortest one 1 LONGEST SHA processing runtime is the longest one (reduces the SHA bandwidth requirement, reduces the system bus overload) When SHA1 algorithm is processed, runtime period is either 85 or 209 clock cycles. When SHA256 or SHA224 algorithm is processed, runtime period is either 72 or 194 clock cycles. ALGO: SHA Algorithm Value Name Description 0 SHA1 SHA1 algorithm processed 1 SHA256 SHA256 algorithm processed 2 Reserved – 3 Reserved – 4 SHA224 SHA224 algorithm processed Values not listed in the table must be considered as “reserved”. DUALBUFF: Dual Input Buffer Value Name Description 0 INACTIVE SHA_IDATARx and SHA_ODATARx cannot be written during processing of previous block. 1 ACTIVE SHA_IDATARx and SHA_ODATARx can be written during processing of previous block when SMOD value = 2. It speeds up the overall runtime of large files. DS60001517A-page 994  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 45.5.3 SHA Interrupt Enable Register Name: SHA_IER Address:0xF0014010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. DATRDY: Data Ready Interrupt Enable URAD: Unspecified Register Access Detection Interrupt Enable  2017 Microchip Technology Inc. DS60001517A-page 995 SAM9N12/SAM9CN11/SAM9CN12 45.5.4 SHA Interrupt Disable Register Name: SHA_IDR Address:0xF0014014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. DATRDY: Data Ready Interrupt Disable URAD: Unspecified Register Access Detection Interrupt Disable DS60001517A-page 996  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 45.5.5 SHA Interrupt Mask Register Name: SHA_IMR Address:0xF0014018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. DATRDY: Data Ready Interrupt Mask URAD: Unspecified Register Access Detection Interrupt Mask  2017 Microchip Technology Inc. DS60001517A-page 997 SAM9N12/SAM9CN11/SAM9CN12 45.5.6 SHA Interrupt Status Register Name: SHA_ISR Address:0xF001401C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR, or by reading SHA_IODATARx) 0: Output data is not valid. 1: 512-bit block process is completed. DATRDY is cleared when one of the following conditions is met: • Bit START in SHA_CR is set. • Bit SWRST in SHA_CR is set. • The hash result is read. URAD: Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR) 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAT: Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR) Value Description 0 SHA_IDATAR0 to SHA_IDATAR15 written during the data processing in DMA mode (URAD = 1 and URAT = 0 can occur only if DUALBUFF is cleared in SHA_MR). 1 Output Data Register read during the data processing. 2 SHA_MR written during the data processing. 3 Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field. DS60001517A-page 998  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 45.5.7 SHA Input Data x Register Name: SHA_IDATARx [x=0..15] Address:0xF0014040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA IDATA: Input Data The 32-bit Input Data registers allow to load the data block used for hash processing. These registers are write-only to prevent the input data from being read by another application. SHA_IDATAR0 corresponds to the first word of the block, SHA_IDATAR15 to the last word of the last block in case SHA algorithm is set to SHA1, SHA224, SHA256.  2017 Microchip Technology Inc. DS60001517A-page 999 SAM9N12/SAM9CN11/SAM9CN12 45.5.8 SHA Output Data Register x Name: SHA_ODATARx [x=0..15] Address:0xF0014080 Access: Read only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data These registers can be used to read the resulting message digest. When SHA processing is in progress, these registers return 0x0000. SHA_ODATAR0 corresponds to the first word of the message digest; SHA_ODATAR4 to the last one in SHA1 mode, SHA_ODATAR6 in SHA224, SHA_ODATAR7 in SHA256, . When SHA224 is selected, the content of SHA_ODATAR7 must be ignored. DS60001517A-page 1000  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 46. True Random Number Generator (TRNG) 46.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 (A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications) and the Diehard Suite of Tests. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 1402 and 140-3. 46.2 Embedded Characteristics • Passes NIST Special Publication 800-22 Test Suite • Passes Diehard Suite of Tests • May be used as Entropy Source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3 • Provides a 32-bit Random Number Every 84 Clock Cycles 46.3 Block Diagram Figure 46-1: TRNG Block Diagram TRNG Interrupt Controller Control Logic MCK PMC User Interface Entropy Source APB 46.4 Product Dependencies 46.4.1 Power Management The TRNG interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TRNG user interface clock. The user interface clock is independent from any clock that may be used in the entropy source logic circuitry. The source of entropy can be enabled before enabling the user interface clock. 46.4.2 Interrupt Sources The TRNG interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TRNG. Table 46-1: 46.5 Peripheral IDs Instance ID TRNG 30 Functional Description As soon as the TRNG is enabled in the control register (TRNG_CR), the generator provides one 32-bit value every 84 clock cycles. The TRNG interrupt line can be enabled in the TRNG_IER (respectively disabled in the TRNG_IDR). This interrupt is set when a new random value is available and is cleared when the status register (TRNG_ISR) is read. The flag DATRDY of the (TRNG_ISR) is set when the random data is ready to be read out on the 32-bit output data register (TRNG_ODATA). The normal mode of operation checks that the status register flag equals 1 before reading the output data register when a 32-bit random value is required by the software application.  2017 Microchip Technology Inc. DS60001517A-page 1001 SAM9N12/SAM9CN11/SAM9CN12 Figure 46-2: TRNG Data Generation Sequence Clock TRNG_CR.ENABLE = 1 84 clock cycles 84 clock cycles 84 clock cycles TRNG Interrupt Line Read TRNG_ISR Read TRNG_ODATA DS60001517A-page 1002 Read TRNG_ISR Read TRNG_ODATA  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 46.6 True Random Number Generator (TRNG) User Interface Table 46-2: Register Mapping Offset 0x00 Register Name Access Reset Write-only – – – Control Register TRNG_CR Reserved – 0x10 Interrupt Enable Register TRNG_IER Write-only – 0x14 Interrupt Disable Register TRNG_IDR Write-only – 0x18 Interrupt Mask Register TRNG_IMR Read-only 0x0000_0000 0x1C Interrupt Status Register TRNG_ISR Read-only 0x0000_0000 Reserved – – – Output Data Register TRNG_ODATA Read-only 0x0000_0000 Reserved – – – 0x04–0x0C 0x20–0x4C 0x50 0x54–0xFC  2017 Microchip Technology Inc. DS60001517A-page 1003 SAM9N12/SAM9CN11/SAM9CN12 46.6.1 TRNG Control Register Name:TRNG_CR Address:0xF8048000 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE ENABLE: Enables the TRNG to Provide Random Values 0: Disables the TRNG. 1: Enables the TRNG if 0x524E47 (“RNG” in ASCII) is written in KEY field at the same time. KEY: Security Key Value 0x524E47 Name Description PASSWD Writing any other value in this field aborts the write operation. DS60001517A-page 1004  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 46.6.2 TRNG Interrupt Enable Register Name: TRNG_IER Address:0xF8048010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.  2017 Microchip Technology Inc. DS60001517A-page 1005 SAM9N12/SAM9CN11/SAM9CN12 46.6.3 TRNG Interrupt Disable Register Name: TRNG_IDR Address:0xF8048014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. DS60001517A-page 1006  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 46.6.4 TRNG Interrupt Mask Register Name: TRNG_IMR Address:0xF8048018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.  2017 Microchip Technology Inc. DS60001517A-page 1007 SAM9N12/SAM9CN11/SAM9CN12 46.6.5 TRNG Interrupt Status Register Name: TRNG_ISR Address:0xF804801C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready 0: Output data is not valid or TRNG is disabled. 1: New random value is completed. DATRDY is cleared when this register is read. DS60001517A-page 1008  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 46.6.6 TRNG Output Data Register Name: TRNG_ODATA Address:0xF8048050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data.  2017 Microchip Technology Inc. DS60001517A-page 1009 SAM9N12/SAM9CN11/SAM9CN12 47. Electrical Characteristics 47.1 Absolute Maximum Ratings Table 47-1: Absolute Maximum Ratings* Junction Temperature...................................................125°C Storage Temperature....................................-60°C to +150°C Voltage on Input Pins with Respect to Ground....-0.3V to VDDIO + 0.3V (+4V max) Maximum Operating Voltage (VDDCORE and VDDPLL) .............................................1.2V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (VDDIOM, VDDIOPx, VDDOSC, VDDANA, VDDNF, VDDUSB, VDDFUSE, and VDDBU) .................4.0V Total DC Output Current on all I/O lines.....................350 mA 47.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to +85°C, unless otherwise specified. Table 47-2: DC Characteristics Symbol Parameter Conditions Min Typ Max Unit TA Operating Temperature (Industrial) -40 – +85 °C VDDCOR DC Supply Core 0.9 1.0 1.1 V VDDBU DC Supply Backup 1.8 – 3.6 V VDDPLL DC Supply PLL 0.9 1.0 1.1 V 1.65 – 3.6 V E VDDOSC DC Supply Oscillator VDDIOM DC Supply EBI I/Os 1.65/3.0 1.8/3.3 1.95/3.6 V VDDNF DC Supply NAND Flash I/Os 1.65/3.0 1.8/3.3 1.95/3.6 V VDDIOP0 DC Supply Peripheral I/Os 1.65 – 3.6 V VDDIOP1 DC Supply Peripheral I/Os 1.65 – 3.6 V VDDANA DC Supply Analog 3.0 3.3 3.6 V VDDUSB DC Supply USB 3.0 3.3 3.6 V VDDFUS 3.0 – 3.6 V VDDIO 3.0–3.6V -0.3 – 0.8 V VDDIO 1.65–1.95V -0.3 – 0.3 × VDDIO V 2 – VDDIO + 0.3 V 0.7 × VDDIO – VDDIO + 0.3 V DC Supply Fuse Box E VIL Input Low-level Voltage VIH Input High-level Voltage DS60001517A-page 1010 VDDIO 3.0–3.6V VDDIO 1.65–1.95V  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 47-2: DC Characteristics (Continued) Symbol Parameter VOL VOH Output Low-level Voltage Output High-level Voltage Conditions Min Typ Max Unit IO Max, VDDIO 3.0–3.6V – – 0.4 V CMOS (IO < 0.3 mA), VDDIO 1.65–1.95V – – 0.1 V TTL (IO Max), VDDIO 1.65–1.95V – – 0.4 V IO Max, VDDIO 3.0–3.6V VDDIO - 0.4 – – V CMOS (IO < 0.3 mA), VDDIO 1.65–1.95V VDDIO - 0.1 – – V TTL (IO Max), VDDIO 1.65–1.95V VDDIO - 0.4 – – V 0.8 1.1 – V VT- Schmitt trigger Negative going threshold Voltage IO Max, VDDIO 3.0–3.6V TTL (IO Max), VDDIO 1.65–1.95V – – 0.3 × VDDIO V Schmitt trigger Positive going threshold Voltage IO Max, VDDIO 3.0–3.6V – 1.6 2.0 V VT+ 0.3 × VDDIO – – V – 0.75 V Schmitt trigger Hysteresis VDDIO 3.0–3.6V 0.5 Vhys VDDIO 1.65–1.95V 0.28 – 0.6 V PA0–PA31 PB0–PB31 PD0–PD31 PE0–PE31 NTRST and NRST 40 75 190 PC0–PC31 VDDIOM1 in 1.8V range 240 – 1000 PC0–PC31 VDDIOM1 in 3.3V range 120 – 350 PA0–PA31 PB0–PB31 PD0–PD31 PE0–PE31 – – 8 PC0–PC31 VDDIOM1 in 1.8V range – – 2 PC0–PC31 VDDIOM1 in 3.3V range – – 4 – 11 – RPULLU Pull-up Resistance P IO Output Current TTL (IO Max), VDDIO 1.65–1.95V On VDDCORE = 1.0V, MCK = 0 Hz, excluding POR All inputs driven TMS, TDI, TCK, NRST = 1 ISC TA = 25°C kΩ mA mA TA = 85°C – – 25 Logic cells consumption, excluding POR TA = 25°C – 8 – All inputs driven WKUP = 0 TA = 85°C – Static Current  2017 Microchip Technology Inc. On VDDBU = 3.3V, µA – 15 DS60001517A-page 1011 SAM9N12/SAM9CN11/SAM9CN12 47.3 Power Consumption • Typical power consumption of PLLs, Slow Clock and Main Oscillator • Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup • Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock 47.3.1 Power Consumption versus Modes The values in Table 47-3 and Table 47-4 represent the power consumption estimated on the power supplies with operating conditions as follows: • • • • • • • VDDIOM = 1.8V VDDIOP0 and VDDIOP1 = 3.3V VDDPLL = 1.0V VDDCORE = 1.0V VDDBU = 3.3V TA = 25 °C There is no consumption on the I/Os of the device Figure 47-1: Measures Schematics VDDBU AMP1 VDDCORE AMP2 Table 47-3: Power Consumption for Different Modes Mode Conditions Consumption Unit 103 mA 33 mA 7 mA 8 µA Arm Core clock is 400 MHz. Active MCK is 133 MHz. All peripheral clocks activated. onto AMP2 Idle state, waiting an interrupt. Idle All peripheral clocks de-activated. onto AMP2 Arm Core clock is 500 Hz. Ultra Low-power All peripheral clocks de-activated. onto AMP2 Backup DS60001517A-page 1012 Device only VDDBU powered onto AMP1  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 47-4: Power Consumption by Peripheral in Active Mode Peripheral Consumption PIO Controller 6 USART 6 ADC 5 TWI 2 SPI 3 UART 3 UHP 5 UDP 5 LCDC 3 PWM 6 HSMCI 3 SSC 5 Timer Counter Channels 12 DMA 1 AES 4 SHA 3 TRNG 1 47.4 Unit µA/MHz Clock Characteristics 47.4.1 Processor Clock Table 47-5: Processor Clock Waveform Parameters Symbol Parameter Conditions 1/ (tCPPCK) Processor Clock Frequency VDDCORE min Min Max Unit 250(1) 400 MHz Note 1: With DDR2 usage. There are no limitations for LPDDR, SDRAM and mobile SDRAM. 47.4.2 System Clock The system clock is the maximum clock at which the system is able to run. It is given by the smallest value of the internal bus clock and EBI clock. Table 47-6: System Clock Waveform Parameters Symbol Parameter Conditions 1/ (tCPMCK) System Clock Frequency VDDCORE min Min Max Unit 125(1) 133 MHz Note 1: With DDR2 usage. There are no limitations for LPDDR, SDRAM and mobile SDRAM.  2017 Microchip Technology Inc. DS60001517A-page 1013 SAM9N12/SAM9CN11/SAM9CN12 47.4.3 Main Oscillator Characteristics Table 47-7: Main Oscillator Characteristics Symbol Parameter 1/(tCPMAIN) Crystal Oscillator Frequency CCRYSTAL( 1) Crystal Load Capacitance CINT(1) Internal Load Capacitance CLEXT Conditions Min Typ Max Unit 8 16 20 MHz 12.5 – 17.5 pF 1.85 2.1 2.35 pF (1) – 20.8 – pF (1) – 30.8 – pF – – – % CCRYSTAL = 12.5 pF External Load Capacitance CCRYSTAL = 17.5 pF Duty Cycle @ 3 MHz tSTART 20 @ 8 MHz Startup Time – @ 16 MHz – @ 20 MHz IDDST Standby Current Consumption Standby mode – – – @ 16 MHz – @ 20 MHz IDD ON Current Dissipation ms 1 µA 15 @ 8 MHz Drive Level 2 2 @ 3 MHz PON 4 30 50 µW 50 @ 3 MHz 280 380 @ 8 MHz 380 510 500 630 580 750 – @ 16 MHz @ 20 MHz µA Note 1: The CCRYSTAL value is specified by the crystal manufacturer. In our case, CCRYSTAL must be between 12.5 pF and 17.5 pF. All parasitic capacitance, package and board, must be calculated in order to reach 12.5 pF (minimum targeted load for the oscillator) by taking into account the internal load CINT. So, to target the minimum oscillator load of 12.5 pF, external capacitance must be 12.5 pF - 2.1 pF = 10.4 pF, which means that 20.8 pF is the target value (20.8 pF from XIN to GND and 20.8 pF from XOUT to GND). If 17.5 pF load is targeted, the sum of pad, package, board and external capacitances must be 17.5 pF - 2.1 pF = 15.4 pF, which means 30.8 pF (30.8 pF from XIN to GND and 30.8 pF from XOUT to GND). Figure 47-2: Main Oscillator Schematic XIN XOUT GNDPLL 1K CCRYSTAL CLEXT DS60001517A-page 1014 CLEXT  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 47.4.4 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. Table 47-8: Symbol Crystal Characteristics Parameter Conditions Min Typ Max Fundamental @ 3 MHz ESR Equivalent Series Resistor Rs Fundamental @ 8 MHz Fundamental @ 16 MHz Unit 200 – 100 – Ω 80 Fundamental @ 20 MHz 50 Cm Motional Capacitance – – 8 fF CSHUNT Shunt Capacitance – – 7 pF 47.4.5 XIN Clock Characteristics Table 47-9: XIN Clock Electrical Characteristics Symbol Parameter 1/ (tCPXIN) Min Max Unit XIN Clock Frequency – 50 MHz tCPXIN XIN Clock Period 20 – ns tCHXIN XIN Clock High Half-period 0.4 × tCPXIN 0.6 × tCPXIN ns tCLXIN XIN Clock Low Half-period 0.4 × tCPXIN 0.6 × tCPXIN ns CIN XIN Input Capacitance – 25 pF RIN XIN Pull-down Resistor – 500 VXINLOW XIN Low Voltage VXINHIGH XIN High Voltage Conditions Main Oscillator in Bypass mode, i.e., when CKGR_MOR.MOSCEN = 0 and CKGR_MOR.OSCBYPASS = 1 (see Section 21.13.7 ”PMC Clock Generator Main Oscillator Register”) -0.3V 0.7 × VDDOSC kΩ (1) V VDDOSC + 0.3(1) V 0.3 × VDDOSC Note 1: Do not exceed 3.6V  2017 Microchip Technology Inc. DS60001517A-page 1015 SAM9N12/SAM9CN11/SAM9CN12 47.5 12 MHz RC Oscillator Characteristics Table 47-10: 12 MHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit F0 Nominal Frequency 8.4 12 15.6 MHz Duty Duty Cycle 45 50 55 % IDD ON Power Consumption Oscillation tSTART Startup time 6 – 10 µs IDD Standby consumption – – 22 µA 86 140 – 86 125 µA STDBY 47.6 32 kHz Oscillator Characteristics Table 47-11: 32 kHz Oscillator Characteristics Symbol Parameter 1/ (tCP32KHz) Crystal Oscillator Frequency CCRYSTAL3 Load Capacitance Conditions Min Typ Max Unit – 32.768 – kHz Crystal @ 32.768 kHz 6 – 12.5 pF CCRYSTAL32 = 6 pF – 6 – pF CCRYSTAL32 = 12.5 pF – 19 – pF 40 50 60 % CCRYSTAL32 = 6 pF – – 400 ms CCRYSTAL32 = 12.5 pF – – 900 ms CCRYSTAL32 = 6 pF – – 600 ms CCRYSTAL32 = 12.5 pF – – 1200 ms 2 CLEXT32(2) External Load Capacitance Duty Cycle RS = 50 kΩ(1) tSTART Startup Time RS = 100 kΩ(1) Note 1: RS is the equivalent series resistance. 2: CLEXT32 is determined by taking into account internal, parasitic and package load capacitance. Figure 47-3: 32 kHz Oscillator Schematic XIN32 XOUT32 GNDBU CCRYSTAL32 CLEXT32 DS60001517A-page 1016 CLEXT32  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 47.6.1 32 kHz Crystal Characteristics Table 47-12: 32 kHz Crystal Characteristics Symbol Parameter Conditions Min Typ Max Unit ESR Equivalent Series Resistor RS Crystal @ 32.768 kHz – 50 100 kΩ Cm Motional Capacitance Crystal @ 32.768 kHz 0.6 – 3 fF CSHUNT Shunt Capacitance Crystal @ 32.768 kHz 0.6 – 2 pF (1) CCRYSTAL32 = 6 pF – 0.55 1.3 µA (1) CCRYSTAL32 = 12.5pF – 0.85 1.6 µA – 0.7 2.0 µA – 1.1 2.2 µA – – 0.3 µA RS = 50 kΩ IDD ON Current dissipation RS = 50 kΩ RS = 100 kΩ(1) CCRYSTAL32 = 6 pF (1) RS = 100 kΩ IDD CCRYSTAL32 = 12.5 pF Standby consumption STDBY Note 1: RS is the equivalent series resistance. 47.6.2 XIN32 Clock Characteristics Table 47-13: XIN32 Clock Electrical Characteristics Symbol Parameter 1/ (tCPXIN32) Min Max Unit XIN32 Clock Frequency – 44 kHz tCPXIN32 XIN32 Clock Period 22 – µs tCHXIN32 XIN32 Clock High Half-period 11 – µs tCLXIN32 XIN32 Clock Low Half-period 11 – µs tCLCH32 XIN32 Clock Rise time 400 – ns tCLCL32 XIN32 Clock Fall time 400 – ns CIN32 XIN32 Input Capacitance – 6 pF RIN32 XIN32 Pull-down Resistor – 4 MΩ VIN32 XIN32 Voltage VDDBU VDDBU V VINIL32 XIN32 Input Low Level Voltage -0.3 0.3 × VDDBU V VINIH32 XIN32 Input High Level Voltage 0.7 × VDDBU VDDBU + 0.3 V 47.7 Conditions 32.768 kHz Oscillator in Bypass mode, i.e., when RCEN = 0, OSC32EN = 0, OSC32BYP = 1 and OSCSEL = 1 in “Slow Clock Controller Configuration Register” (SCKC_CR) . See Section 19.4.2 “Bypassing the 32.768 kHz Crystal Oscillator”. 32 kHz RC Oscillator Characteristics Table 47-14: 32 kHz RC Oscillator Characteristics Symbol Parameter 1/(tCPRCz) Min Typ Max Unit Crystal Oscillator Frequency 20 32 44 kHz Duty Cycle 45 – 55 % tSTART Startup Time – – 75 µs IDD ON Power Consumption Oscillation – 1.1 2.1 µA IDD STDBY Standby consumption – – 0.4 µA  2017 Microchip Technology Inc. Conditions After startup time DS60001517A-page 1017 SAM9N12/SAM9CN11/SAM9CN12 47.8 PLL Characteristics Table 47-15: PLLA Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output Frequency Refer to Table 47-16 400 – 800 MHz fIN Input Frequency 2 – 32 MHz Active mode – 3.6 4.5 mA IPLL Current Consumption Standby mode – – 1 µA tSTART Startup Time – – 50 µs PMC_PLLICPR.ICPLLA and CKGR_PLLAR.OUTA must be configured for each PLLA frequency range as shown in Table 47-16. Table 47-16: PLLA Frequency Configuration with PMC_PLLICPR.ICPLLA and CKGR_PLLAR.OUTA PLL Frequency Range (MHz) ICPLLA 745–800 0 0 0 695–750 0 0 1 645–700 0 1 0 595–650 0 1 1 545–600 1 0 0 495–550 1 0 1 445–500 1 1 0 400–450 1 1 1 Table 47-17: OUTA PLLB Characteristics Symbol Parameter Conditions Min Typ Max Unit fOUT Output Frequency Field CKGR_PLLBR.OUTB = 00 30 – 100 MHz fIN Input Frequency 2 – 32 MHz Active mode @ 100 MHz – – 1.2 mA IPLL Current Consumption Standby mode – – 1 µA tSTART Startup Time – – 100 µs 47.9 I/Os Criteria used to define the maximum frequency of the I/Os: • Output duty cycle (40%–60%) • Minimum output swing: 100 mV to VDDIO - 100 mV DS60001517A-page 1018  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 • Addition of rising and falling time inferior to 75% of the period Table 47-18: Symbol I/O Characteristics Parameter Conditions Min Max – 66 CCFG_EBICSA.EBI_DRIVE = HIGH, CLOAD = 40 pF(1) – 66 CCFG_EBICSA.EBI_DRIVE = LOW, CLOAD = 20 pF(1) – 66 CCFG_EBICSA.EBI_DRIVE = HIGH, CLOAD = 30 pF(1) – 66 CCFG_EBICSA.EBI_DRIVE = LOW, CLOAD = 20 pF 3.3V domain VDDIOP powered pins frequency FreqMax 1.8V domain (1) Unit MHz MHz Note 1: CLOAD = maximum external capacitance 47.10 Analog-to-Digital Converter (ADC) Table 47-19: Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency 10-bit resolution mode Startup Time Return from Idle Mode Track and Hold Acquisition Time (TTH) (1) ADC Clock = 13.2 MHz Min Typ Max Unit – – 13.2 MHz – – 40 µs 0.5 – – – – – µs (1) Conversion Time (TCT) Throughput Rate ADC Clock = 13.2 MHz ADC Clock = 5 MHz(1) ADC Clock = 13.2 MHz(1) ADC Clock = 5 MHz(1) 1.74 4.6 440 192 µs ksps Note 1: The Track-and-Hold Acquisition Time is given by: TTH (ns) = 500 + (0.12 × ZIN) (Ω) The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion time is give by: 23 TCT ( µs ) = --------- ( MHz ) fclk The full speed is obtained for an input source impedance of < 50 Ω maximum, or TTH = 500 ns. In order to make the ADC work properly, the TRACKTIM field in the ADC Mode Register is to be calculated according to this Track and Hold Acquisition Time, also called Sampled and Hold Time. Table 47-20: External Voltage Reference Input Parameter Min Typ Max Unit 2.4 – VDDANA V ADVREF Average Current – – 600 µA Current Consumption on VDDANA – – 600 µA ADVREF Input Voltage Range  2017 Microchip Technology Inc. Conditions DS60001517A-page 1019 SAM9N12/SAM9CN11/SAM9CN12 Table 47-21: Analog Inputs Parameter Conditions Min Typ Max Unit Input Voltage Range 0 – ADVREF V Input Peak Current – – 2.5 mA Input Capacitance – 7 10 pF Input Impedance – 50 Min Typ Max Unit Resolution – 10 – bit INL Integral Non-linearity – – ±2 LSB DNL Differential Non-linearity – – EO Offset Error – – EG Gain Error – – Table 47-22: Symbol Ω Transfer Characteristics Parameter Conditions ADC Clock = 13.2 MHz ADC Clock = 5 MHz ADC Clock = 13.2 MHz ADC Clock = 5 MHz ±2 ±0.9 ±10 ±3 LSB LSB LSB ±2 47.11 USB Transceiver Characteristics Table 47-23: Symbol USB Electrical Characteristics Parameter Conditions Min Typ Max Unit Input Levels VIL Low Level – – 0.8 V VIH High Level 2.0 – – V VDI Differential Input Sensitivity 0.2 – – V VCM Differential Input Common Mode Range 0.8 – 2.5 V CIN Transceiver capacitance Capacitance to ground on each line – – 9.18 pF Ilkg Hi-Z State Data Line Leakage 0V < VIN < 3.3V - 10 – + 10 µA REXT Recommended External USB Series Resistor In series with each USB pin with ±5% – 27 – Ω |(D+) - (D-)| Output Levels VOL Low Level Output Measured with RL of 1.425 kΩ tied to 3.6V 0.0 – 0.3 V VOH High Level Output Measured with RL of 14.25 kΩ tied to GND 2.8 – 3.6 V VCRS Output Signal Crossover Voltage Measure conditions described in Figure 47-22 1.3 – 2.0 V Pull-up and Pull-down Resistor RPUI Bus Pull-up Resistor on Upstream Port (idle bus) 0.900 – 1.575 kΩ RPUA Bus Pull-up Resistor on Upstream Port (upstream port receiving) 1.425 – 3.090 kΩ RPD Bus Pull-down resistor 14.25 – 24.8 kΩ DS60001517A-page 1020  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 47.12 Core Power Supply POR Characteristics Table 47-24: Power-On-Reset Characteristics Symbol Parameter Conditions Min Typ Max Unit VT+ Threshold Voltage Rising Minimum Slope of +2.0V/30ms 0.5 0.7 0.89 V VT- Threshold Voltage Falling 0.4 0.6 0.85 V tRST Reset Time 30 70 130 µs IDD Current consumption – 3 7 µA After tRST 47.13 SMC Timings 47.13.1 Timing Conditions Timings are given assuming a capacitance load on data, control and address pads. Table 47-25: Capacitance Load Corner Supply Max Min 3.3V 50 pF 5 pF 1.8V 30 pF 5 pF In the following tables, tCPMCK is MCK period. 47.13.2 47.13.2.1 Timing Extraction Zero Hold Mode Restrictions Table 47-26: Zero Hold Mode Use Maximum System Clock Frequency (MCK) Min Symbol Parameter fmax MCK frequency  2017 Microchip Technology Inc. 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit 66 66 MHz DS60001517A-page 1021 SAM9N12/SAM9CN11/SAM9CN12 47.13.2.2 Read Timings Table 47-27: SMC Read Signals - NRD Controlled (READ_MODE = 1) Min Symbol Parameter 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit 13.7 11.8 ns 0 0 ns 10.7 8.8 ns 0 0 ns NO HOLD SETTINGS (nrd hold = 0) SMC1 Data Setup before NRD High SMC2 Data Hold after NRD High HOLD SETTINGS (nrd hold ≠ 0) SMC3 Data Setup before NRD High SMC4 Data Hold after NRD High HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold = 0) SMC5 NBS0/A0, NBS1, NBS2/A1, NBS3, A2–A25 Valid before NRD High SMC6 NCS low before NRD High SMC7 NRD Pulse Width 47.13.2.3 (nrd setup + nrd pulse) × tCPMCK - (nrd setup + nrd pulse) × tCPMCK 5.3 5.1 ns (nrd setup + nrd pulse - ncs rd setup) × tCPMCK -4.8 (nrd setup + nrd pulse - ncs rd setup) × tCPMCK - 4.9 ns nrd pulse × tCPMCK - 3.4 nrd pulse × tCPMCK - 3.5 ns 3.3V VDDIOM Supply Unit 26.7 24.7 ns 0 0 ns 12.4 10.4 ns 0 0 ns (ncs rd setup + ncs rd pulse) × tCPMCK - 18.1 (ncs rd setup + ncs rd pulse) × tCPMCK - 18.2 ns Write Timings Table 47-28: SMC Read Signals - NCS Controlled (READ_MODE = 0) Min Symbol Parameter 1.8V VDDIOM Supply NO HOLD SETTINGS (ncs rd hold = 0) SMC8 Data Setup before NCS High SMC9 Data Hold after NCS High HOLD SETTINGS (ncs rd hold ≠ 0) SMC10 Data Setup before NCS High SMC11 Data Hold after NCS High HOLD or NO HOLD SETTINGS (ncs rd hold ≠ 0, ncs rd hold = 0) SMC12 NBS0/A0, NBS1, NBS2/A1, NBS3, A2–A25 valid before NCS High SMC13 NRD low before NCS High (ncs rd setup + ncs rd pulse - nrd setup) × tCPMCK - 2.8 (ncs rd setup + ncs rd pulse - nrd setup) × tCPMCK - 2.9 ns SMC14 NCS Pulse Width ncs rd pulse length × tCPMCK - 4.0 ncs rd pulse length × tCPMCK - 4.0 ns DS60001517A-page 1022  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Table 47-29: SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Min Symbol Parameter 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0) SMC15 Data Out Valid before NWE High nwe pulse × tCPMCK - 4.1 nwe pulse × tCPMCK - 4.0 ns SMC16 NWE Pulse Width nwe pulse × tCPMCK - 3.0 nwe pulse × tCPMCK - 3.1 ns SMC17 NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25 valid before NWE low nwe setup × tCPMCK - 4.2 nwe setup × tCPMCK - 4.1 ns SMC18 NCS low before NWE high (nwe setup - ncs rd setup + nwe pulse) × tCPMCK - 3.8 (nwe setup - ncs rd setup + nwe pulse) × tCPMCK - 3.7 ns nwe hold × tCPMCK - 4.0 nwe hold × tCPMCK - 3.1 ns (nwe hold - ncs wr hold) × tCPMCK - 2.8 (nwe hold - ncs wr hold) × tCPMCK - 2.0 ns 1.4 ns HOLD SETTINGS (nwe hold ≠ 0) SMC19 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25 change SMC20 NWE High to NCS Inactive (1) NO HOLD SETTINGS (nwe hold = 0) SMC21 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25, NCS change(1) 1.6 Note 1: hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “NWE hold length”. Table 47-30: SMC Write NCS Controlled (WRITE_MODE = 0) Min Symbol Parameter 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit SMC22 Data Out Valid before NCS High ncs wr pulse × tCPMCK - 4.3 ncs wr pulse × tCPMCK - 4.5 ns SMC23 NCS Pulse Width ncs wr pulse × tCPMCK - 4.0 ncs wr pulse × tCPMCK - 4.0 ns SMC24 NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25 valid before NCS low ncs wr setup × tCPMCK - 3.6 ncs wr setup × tCPMCK - 3.5 ns SMC25 NWE low before NCS high (ncs wr setup - nwe setup + ncs pulse) × tCPMCK - 3.9 (ncs wr setup - nwe setup + ncs pulse) × tCPMCK - 3.9 ns SMC26 NCS High to Data Out, NBS0/A0, NBS1, NBS2/A1, NBS3, A2–A25 change ncs wr hold × tCPMCK - 6.1 ncs wr hold × tCPMCK - 5.2 ns SMC27 NCS High to NWE Inactive (ncs wr hold - nwe hold) × tCPMCK - 4.8 (ncs wr hold - nwe hold) × tCPMCK - 4.4 ns  2017 Microchip Technology Inc. DS60001517A-page 1023 SAM9N12/SAM9CN11/SAM9CN12 Figure 47-4: SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC24 SMC26 A0/A1/NBS[3:0]/A2–A25 SMC13 SMC13 NRD SMC14 NCS SMC8 SMC14 SMC9 SMC10 SMC23 SMC11 SMC22 SMC26 D0–D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD Figure 47-5: NCS Controlled READ with HOLD NCS Controlled WRITE SMC Timings - NRD Controlled Read and NWE Controlled Write SMC21 SMC5 SMC17 SMC5 SMC17 SMC19 A0/A1/NBS[3:0]/A2–A25 SMC6 SMC18 SMC21 SMC6 SMC18 SMC20 NCS NRD SMC7 SMC7 SMC1 SMC2 SMC15 SMC21 SMC3 SMC4 SMC15 SMC19 D0–D31 NWE SMC16 NRD Controlled READ with NO HOLD DS60001517A-page 1024 NWE Controlled WRITE with NO HOLD SMC16 NRD Controlled READ with HOLD NWE Controlled WRITE with HOLD  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 47.14 DDRSDRC Timings The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules. DDR2, LP-DDR and SDR timings are specified by the JEDEC standard. Supported speed grade limitations: • DDR2-400 limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK/CK#) • LP-DDR (1.8V, 30 pF on data/control, 10pF on CK) tcyc = 5.0 ns, fmax = 125 MHz tcyc = 6.0 ns, fmax = 110 MHz tcyc = 7.5 ns, fmax = 95 MHz • SDR-100 (3.3V, 50 pF on data/control, 10 pF on CK) • SDR-133 (3.3V, 50 pF on data/control, 10 pF on CK) • LP-SDR-133 (1.8V, 30 pF on data/control, 10 pF on CK) 47.15 Peripheral Timings 47.15.1 47.15.1.1 SPI Maximum SPI Frequency The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes. • Master Write Mode The SPI only sends data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 47.9 “I/Os”), the maximum SPI frequency is defined by the pin FreqMax value. • Master Read Mode 1 f SPCK Max = ------------------------------------------------------SPI 0 ( orSPI 3 ) + t valid tvalid is the slave time response to output data after deleting an SPCK edge. F or a non-volatile memory with tvalid (or tv) = 12 ns Max, fSPCKMax = 47.1 MHz @ VDDIO = 3.3V. • Slave Read Mode In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold timings SPI7/SPI8(or SPI10/ SPI11). Since this gives a frequency well above the pad limit, the limit in slave read mode is given by SPCK pad. • Slave Write Mode 1 f SPCK Max = ------------------------------------------------------SPI 6 ( orSPI 9 ) + t setup tsetup is the setup time from the master before sampling data (12 ns). This gives fSPCKMax = 44.6 MHz @ VDDIO = 3.3V. 47.15.1.2 Timing Conditions Timings are given assuming a capacitance load on MISO, SPCK and MOSI. Table 47-31: Capacitance Load for MISO, SPCK and MOSI (product dependent) Corner Supply Max Min 3.3V 40 pF 5 pF 1.8V 20 pF 5 pF  2017 Microchip Technology Inc. DS60001517A-page 1025 SAM9N12/SAM9CN11/SAM9CN12 47.15.1.3 Timing Extraction Figure 47-6: SPI Master mode 1 and 2 SPCK SPI1 SPI0 MISO SPI2 MOSI Figure 47-7: SPI Master mode 0 and 3 SPCK SPI4 SPI3 MISO SPI5 MOSI Figure 47-8: SPI Slave mode 0 and 3 NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI DS60001517A-page 1026  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 47-9: SPI Slave mode 1 and 2 NPCS0 SPI13 SPI12 SPCK SPI9 MISO SPI10 SPI11 MOSI Figure 47-10: SPI Slave mode - NPCS timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI13 SPI9 SPCK (CPOL = 1) SPI16 MISO Table 47-32: Symbol SPI Timings with 3.3V Peripheral Supply Parameter Conditions Min Max Unit – 66 MHz 13.7 – ns Master Mode SPISPCK SPI Clock SPI0 MISO Setup time before SPCK rises SPI1 MISO Hold time after SPCK rises 0 – ns SPI2 SPCK rising to MOSI 0 7.6 ns SPI3 MISO Setup time before SPCK falls 13.2 – ns SPI4 MISO Hold time after SPCK falls 0 – ns SPI5 SPCK falling to MOSI 0 7.7 ns 2.7 14.1 ns Slave Mode SPI6 SPCK falling to MISO  2017 Microchip Technology Inc. DS60001517A-page 1027 SAM9N12/SAM9CN11/SAM9CN12 Table 47-32: SPI Timings with 3.3V Peripheral Supply (Continued) Symbol Parameter SPI7 Min Max Unit MOSI Setup time before SPCK rises 2.7 – ns SPI8 MOSI Hold time after SPCK rises 0.2 – ns SPI9 SPCK rising to MISO 2.5 13.8 ns SPI10 MOSI Setup time before SPCK falls 2.2 – ns SPI11 MOSI Hold time after SPCK falls 0.6 – ns SPI12 NPCS0 setup to SPCK rising 4.3 – ns SPI13 NPCS0 hold after SPCK falling 0 – ns SPI14 NPCS0 setup to SPCK falling 3.8 – ns SPI15 NPCS0 hold after SPCK rising 0 – ns SPI16 NPCS0 falling to MISO valid – 14.5 ns Min Max Unit – 66 MHz 16.3 – ns Table 47-33: Symbol Conditions SPI Timings with 1.8V Peripheral Supply Parameter Conditions Master Mode SPISPCK SPI Clock SPI0 MISO Setup time before SPCK rises SPI1 MISO Hold time after SPCK rises 0 – ns SPI2 SPCK rising to MOSI 0 6.9 ns SPI3 MISO Setup time before SPCK falls 15.1 – ns SPI4 MISO Hold time after SPCK falls 0 – ns SPI5 SPCK falling to MOSI 0 7.0 ns Slave Mode SPI6 SPCK falling to MISO 3.5 16.8 ns SPI7 MOSI Setup time before SPCK rises 2.9 – ns SPI8 MOSI Hold time after SPCK rises 0.3 – ns SPI9 SPCK rising to MISO 3.3 16.4 ns SPI10 MOSI Setup time before SPCK falls 2.4 – ns SPI11 MOSI Hold time after SPCK falls 0.7 – ns SPI12 NPCS0 setup to SPCK rising 4.5 – ns SPI13 NPCS0 hold after SPCK falling 0 – ns SPI14 NPCS0 setup to SPCK falling 3.9 – ns SPI15 NPCS0 hold after SPCK rising 0 – ns SPI16 NPCS0 falling to MISO valid – 17.3 ns DS60001517A-page 1028  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 47.15.2 47.15.2.1 SSC Timing Conditions 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 30 pF Timings are given assuming a capacitance load as specified in Table 47-34. Table 47-34: Capacitance Load Corner 47.15.2.2 Supply Max Min 3.3V 30 pF 5 pF 1.8V 20 pF 5 pF Timing Extraction Figure 47-11: SSC Transmitter, TK and TF in output TK (CKI = 0) TK (CKI = 1) SSC0 TF/TD Figure 47-12: SSC Transmitter, TK in input and TF in output TK (CKI = 0) TK (CKI = 1) SSC1 TF/TD  2017 Microchip Technology Inc. DS60001517A-page 1029 SAM9N12/SAM9CN11/SAM9CN12 Figure 47-13: SSC Transmitter, TK in output and TF in input TK (CKI = 0) TK (CKI = 1) SSC2 SSC3 TF SSC4 TD Figure 47-14: SSC Transmitter, TK and TF in Input SSC15 TK (CKI = 0) SSC14 SSC14 TK (CKI = 1) SSC5 SSC6 TF SSC7 TD Figure 47-15: SSC Receiver RK and RF in Input RK (CKI = 0) RK (CKI = 1) SSC8 SSC9 RF/RD DS60001517A-page 1030  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Figure 47-16: SSC Receiver, RK in input and RF in Output RK (CKI = 1) RK (CKI = 0) SSC8 SSC9 RD SSC10 RF Figure 47-17: SSC Receiver, RK and RF in Output RK (CKI = 1) RK (CKI = 0) SSC11 SSC12 RD SSC13 RF Figure 47-18: SSC Receiver, RK in Output and RF in Input RK (CKI = 0) RK (CKI = 1) SSC11 SSC12 RF/RD Table 47-35: Symbol SSC Timings 3.3V Domain Parameter Conditions Min Max Unit TK edge to TF/TD (TK output, TF output) 2.1(1) 13.2(1) ns SSC1 TK edge to TF/TD (TK input, TF output) 2.1(1) 11.1(1) ns SSC2 TF setup time before TK edge (TK output) 10.6 - tCPMCK – ns SSC3 TF hold time after TK edge (TK output) tCPMCK - 2.0 – ns Transmitter SSC0  2017 Microchip Technology Inc. DS60001517A-page 1031 SAM9N12/SAM9CN11/SAM9CN12 Table 47-35: SSC Timings 3.3V Domain (Continued) Symbol Parameter Conditions SSC4 TK edge to TF/TD (TK output, TF input) STTDLY = 0 START = 4, 5 or 7 SSC5 TF setup time before TK edge (TK input) SSC6 TF hold time after TK edge (TK input) Min Max Unit 2.0 13.2 2.0 + (2 × tCPMCK) 13.2 + (2 × tCPMCK) 0 – ns tCPMCK – ns 2.1 11.1 2.1 + (3 × tCPMCK) 11.1 + (3 × tCPMCK) 0 – ns tCPMCK – ns 2.1 10.8 ns ns SSC7 TK edge to TF/TD (TK input, TF input) SSC8 RF/RD setup time before RK edge (RK input) SSC9 RF/RD hold time after RK edge (RK input) SSC10 RK edge to RF (RK input) SSC11 RF/RD setup time before RK edge (RK output) 10.4 - tCPMCK – ns SSC12 RF/RD hold time after RK edge (RK output) tCPMCK - 1.9 – ns 2.0 13.2 ns 10 ns – ns Max Unit STTDLY = 0 START = 4, 5 or 7 ns Receiver RK edge to RF (RK output) SSC13 SSC14 (1) TK rise time or fall time 10 to 90% SSC15 (1) TK low or high time VTK>VIH or VTKVIH or VTK WPKEY, SPIWPEN --> WPEN) - WPEN: added details on Disable/Enable conditions and the list of protected registers - WPKEY: replaced the bitfield description with a table Section 35.8.11 ”SPI Write Protection Status Register”: 8136 - removed ‘SPI’ prefix in bitfield names (SPIWPVSRC --> WPVSRC, SPIWPVS --> WPVS) - WPVS: replaced the bitfield description table with the corresponding text (simplified) TC: Section 36.7 ”Timer Counter (TC) User Interface”: rfo - changed the order of register description sections to match Table 36-5 ”Register Mapping” Section 36.7.2 ”TC Channel Mode Register: Capture Mode”: 9107 - TCCLKS: added details for values 0 - 4 in the bitfield description table Section 36.7.3 ”TC Channel Mode Register: Waveform Mode”: 8885/ - TCCLKS: added details for values 0 - 4 in the bitfield description table 9107 - ENETRG: added a note on TIOA and TIOB controled by a selected external event PWM: Section 37.5.2 ”Power Management”, replaced the 2nd paragraph with a new content DS60001517A-page 1064 8105  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063J Change Request Ref.(1) Comments (Continued) TWI: rfo Section 38.6.2 ”Power Management”, removed erroneous bullet “Enable the peripheral clock”. Section 38.8 ”Master Mode”: - Section 38.8.6.1 ”7-bit Slave Addressing”, replaced ‘N’ acronym with ‘NA’ in Table 38-6 ”Abbreviations”. rfo - Section 38.8.7.1 ”Data Transmit with the DMA”: - added Steps 6 - 9 8555/ - Section 38.8.7.2 ”Data Receive with the DMA”: 8552/ - replaced the acronym ‘PDC’ with ‘DMA’ in the 1st paragraph rfo - added a paragraph on slave mode - updated Step 2 - added Step 4 and Step 12 8944/rfo - Section 38.8.9 ”Read-write Flowcharts”, added missing “yes” and “no” in: - Figure 38-18, "TWI Write Operation with Multiple Data Bytes with or without Internal Address" 9055 - Figure 38-21, "TWI Read Operation with Multiple Data Bytes with or without Internal Address" Section 38.10 ”Slave Mode” - added Section 38.10.6 ”Using the DMA Controller” including subsections on data transmit and data receive 8845 Section 38.11 ”Write Protection System”: - replaced the acronym of the TWI Write Protection Status register with a cross-reference to the corresponding section (the acronym changed: TWI_WPROT_STATUS --> TWI_WPSR) - renamed bitfields of the write protection registers (WPROTERR --> WPVSRC, WPROTADDR --> WPVSRC, SECURITY_CODE --> WPKEY) Section 38.12 ”Two-wire Interface (TWI) User Interface”: - Table 38-7 ”Register Mapping”, added an offset for reserved registers (0x38-0xE0). - Section 38.12.5 ”TWI Clock Waveform Generator Register”, fixed typos. 8814 - Section 38.12.6 ”TWI Status Register”, replaced the description of ”NACK: Not Acknowledged (clear on read)”, used in master mode, with a new text (value “1”, address byte is now referenced too) 9145 - Section 38.12.11 ”TWI Transmit Holding Register”, changed the register access to Write-only 9050 - Section 38.12.12 ”TWI Write Protection Mode Register” 9050 - changed the register acronym: TWI_WPROT_MODE --> TWI_WPMR - renamed bitfields: WPROT --> WPEN, SECURITY_CODE --> WPKEY - WPROT/WPEN: added details on Disable/Enable conditions and the list of protected registers - SECURITY_CODE/WPKEY: replaced the bit description with a table - Section 38.12.13 ”TWI Write Protection Status Register” 9050 - change the register acronym: TWI_WPROT_STATUS --> TWI_WPSR - renamed bitfields: WPROTERR --> WPVSRC, WPROTADDR --> WPVSRC - updated entirely the description of bitfields  2017 Microchip Technology Inc. DS60001517A-page 1065 SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063J Change Request Ref.(1) Comments (Continued) USART: Section 39.3 ”Block Diagram” and Section 39.7.7 ”SPI Mode”: 9356 - moved Table 40-1. SPI Operating Modes to Section 39.7.7.1 ”Modes of Operation” (now Table 39-13 ”SPI Operating Mode”) Section 39.7.1 ”Baud Rate Generator”, replaced “or 6” with “or 6 times lower” in the last phrase of the introduction text. rfo Section 39.7.3.8 ”Parity”, corrected Figure 39-22, "Parity Error" for stop bit value. 8943 Section 39.7.3.10 ”Transmitter Timeguard”, updated the Baud Rate value from “33,400” to “38,400” in Table 39-9 ”Maximum Timeguard Length Depending on Baud Rate”. Section 39.7.3.11 ”Receiver Time-out”, updated the Baud Rate value from “33,400” to “38,400” in Table 3910 ”Maximum Time-out Period”. Section 39.7.5.3 ”IrDA Demodulator”, added a paragraph on IRDA_FILTER programming criteria. 8508 Section 39.7.8.16 ”LIN Frame Handling With the DMAC”, removed abundant “DMAC” acronym in the 1st paragraph. Section 39.8 ”Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface”: - Table 39-17 ”Register Mapping”: - added a row for LIN Baud Rate Register (offset 0x005C) 8445/ - updated offset values and added a new row for reserved registers (0x0060-0x00E0, 0x00EC-0x00FC) 8943 - added Section 39.8.28 ”USART LIN Baud Rate Register” 8445 - Section 39.8.22 ”USART FI DI RATIO Register”: 8643 - US_FIDI register table: expanded FI_DI_RATIO bitfield to 16 bits - Section 39.8.24 ”USART IrDA FILTER Register”: 8508 - IRDA_FILTER: replaced the bitfield description with a new content including IRDA_FILTER programming criteria - Section 39.8.29 ”USART Write Protect Mode Register”: 8791 - WPKEY: replaced the bitfield description with a table UART: Section 40.2 ”Embedded Characteristics”, removed a redundant bullet on UART compatible features 8326 Section 40.4.3 ”Interrupt Source”, replaced “NVIC” with a generic term “Interrupt Controller”. Section 40.6 ”Universal Asynchronous Receiver Transmitter (UART) User Interface”: 7967 - Table 40-3 ”Register Mapping”: updated offset values and added a new row for reserved registers (0x0040-0x00E8, 0x00EC-0x00FC) DS60001517A-page 1066  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063J Change Request Ref.(1) Comments (Continued) ADC: Section 41.1 ”Description”, updated text in the entire section. 8509/rfo Section 41.6.2 ”Conversion Reference”, added details on reference voltage in the 1st sentence. 8385/rfo Section 41.6.4 ”Conversion Results”, removed “...and EOC bit corresponding to the last converted channel” from the last phrase of the third paragraph. 8357 Section 41.6.5 ”Conversion Triggers”, added a title to Figure 41-5, "Hardware Trigger Delay". 8997 Section 41.5.6 ”Conversion Performance”, updated references to electrical characteristics of the product. Section 41.7.11 ”Write Protected Registers”, added ADC Analog Control Register in the list of writeprotected registers. 8583 Section 41.8 ”Analog-to-Digital Converter (ADC) User Interface”: - removed duplicate information on registers not listed in Table 41-4 ”Register Mapping” rfo - Section 41.8.2 ”ADC Mode Register”, removed FWUP bitfield 8461/rfo - Section 41.8.15 ”ADC Compare Window Register”: 8045 - LOWTHRES: added details in the bitfield descriptions on programming conditions - HIGHTHRES: added details in the bitfield descriptions on programming conditions - Section 41.8.19 ”ADC Touchscreen X Position Register”: 8229 - ADC_XPOSR register table: expanded XPOS and XSCALE bitfields (bits 0-11 and 16-27 respectively) - Section 41.8.20 ”ADC Touchscreen Y Position Register”: - ADC_YPOSR register table: expanded YPOS and YSCALE bitfields (bits 0-11 and 16-27 respectively) - Section 41.8.21 ”ADC Touchscreen Pressure Register”: - ADC_PRESSR register table: expanded Z1 and Z2 bitfields (bits 0-11 and 16-27 respectively) - Section 41.8.23 ”ADC Write Protect Mode Register”: 8583/ - WPEN: added ADC Analog Control Register in the list of write-protected registers 8856 - WPKEY: replaced the bitfield description with a table SSC: Section 42.9.14 ”SSC Interrupt Enable Register”: 8993 - TXRDY: fixed a typo (‘0 = 0 =’ --> ‘0 = ’) Section 42.9.17 ”SSC Write Protect Mode Register”: 8841 - WPKEY: replaced the bitfield description with a table AES: Section 44.6.2 ”AES Mode Register”: 8859 - CKEY: replaced the bitfield description with a table Section 44.6.10 ”AES Initialization Vector Register x”: 8892 - IV: added details on CBC, OFB, CFB, and CTR modes in the bitfield description SHA: Section 45.5 ”Secure Hash Algorithm (SHA) User Interface”: 8216 - Table 45-2 ”Register Mapping”: changed the reset value for SHA_MR from 0x1 to 0x0000100  2017 Microchip Technology Inc. DS60001517A-page 1067 SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063J Change Request Ref.(1) Comments (Continued) TRNG: Added new sections: - Section 46.3 ”Block Diagram” - Section 46.4 ”Product Dependencies” including subsections - Section 46.5 ”Functional Description” 8567 Section 46.1 ”Description”, moved 2nd and 3d paragraphs to Section 46.5 ”Functional Description” and added a paragraph on TRNG as an entropy source. Section 46.2 ”Embedded Characteristics”: - added a bullet on TRNG as an entropy source - moved Figure 46-2, "TRNG Data Generation Sequence" to Section 46.5 ”Functional Description” Electrical Characteristics: Section 47.1 “Absolute Maximum Ratings”: rfo - removed operating temperature references from Table 47-1 ”Absolute Maximum Ratings*” Section 47.2 “DC Characteristics”: - added operating temperature references to Table 47-2 ”DC Characteristics” rfo - removed references to VDDCORE ripple, VDDBU ripple, VDDPLL ripple, and VDDOSC ripple parameters rfo Added titles to Figure 47-2 "Main Oscillator Schematic" and Figure 47-3 "32 kHz Oscillator Schematic". rfo Section 47.12 “Core Power Supply POR Characteristics”: 8807/rfo - added Section 47.13 “Power Sequence Requirements” - added Section 47.13.1 “Power-Up Sequence” Ordering Information: Table 50-1, “SAM9N12/CN11/CN12 Ordering Information”: - added MRL and Carrier Type columns 8804 - added ordering codes for MRLB ERRATA: Doc. Rev 11063I Added Section 51.2.2 “12 MHz RC Oscillator”. 9164 Updated Section 51.1.1.1 “Boot from SPI Serial Flash Devices (xx25xxx) Is not Working”. 9051 Updated the section structure and added Section 51.4 ”SAM9CN12 Errata: Revision B”. rfo Comments Change Request Ref. PMC: Note added in MAINFRDY field in Section 21.12.8 “PMC Clock Generator Main Clock Frequency Register”. DS60001517A-page 1068 8870  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063I Change Request Ref. Comments DMAC: Text updated in Section 31.1 “Description”, Section 31.2 “Embedded Characteristics”, Section 31.5.4.3 “Ending Multi-buffer Transfers”, Section 31.6 “DMAC Software Requirements”. 8441 Ordering Information: In Table 50-1, “SAM9N12/CN11/CN12 Ordering Information”, BGA247 package ordering codes added. 8804 Errata: Section 51.2.1 “LCD Controller (LCDC)” deleted. Section 51.1.2 “16 MHz Main Crystal - SAM9CN12 - Rev. A” added. Doc. Rev 11063H 8804 Change Request Ref.(1) Comments PMC: Reset value of CKGR_MOR register updated to 0x0000_0008 in Table 21-3, “Register Mapping”. 8447 PMERRLOC: SIGMAN replaced with SIGMAx in Section 28.5.10 “Error Location SIGMAx Register”. 8339 HSMCI: In Section 34.14.7 “HSMCI Block Register”, replaced BNCT bitfield table with the corresponding description and updated warning note. 8431 Table updated in Section 34.14.16 “HSMCI DMA Configuration Register”. rfo Replaced references to advanced interrupt controller/AIC with “interrupt controller” in Section 34.6.3 “Interrupt”. TWI: In Section 38.1 “Description”, removed “20” at the end of the 1st paragraph. 7921 Add-on for PDC/DMA transfer in Section 38.8.7 “Using the DMA Controller”. 8426 AES: Information on processing files greater than 1 megabyte added in Section 44.4.1 “Operation Modes”. 7966 Typo fixed in Section 44.4.3.1 “Manual Mode”. 8389 Removed units in the Chunk Size column in Table 44-3, “DMA Data Transfer Type for the Different Operation Modes”. rfo Electrical Characteristics: Section 47.11 “USB Transceiver Characteristics” and Section 47.15.5 “UDP” added. 8504 Errata: Section 51.2.1 “LCD Controller (LCDC)” added. 7996 Section 51.2.1 “LCD Controller (LCDC)” added. 8321  2017 Microchip Technology Inc. DS60001517A-page 1069 SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063G Change Request Ref.(1) Comments Overview: Added “Write Protected Registers in Section “Features”. 8213 Product name updated to SAM9N12/SAM9CN11/SAM9CN12. 8244 “Description” updated with the various devices configurations. Bullets for SAM9CN11 and SAM9N12 added in Section 6.3 “Chip Identification”. Boot Strategies: Boot Strategy from SAM9CN12 removed to create the separate Secure Boot document, and replaced by the previous Boot Strategies from SAM9N12. 8202 Table 11-1, “External Clock and Crystal frequencies allowed for Boot Sequence (in MHz)” added in Section 11.2.3 “Chip Setup”. 8270 RSTC: RSTC conditions improved. 8083 HSMCI: Sentence "This flag must be used only for Write Operations” removed in “NOTBUSY: HSMCI Not Busy” on page 616. 8394 USART: Whole chapter updated. rfo SSC: Reworked tables and bitfield descriptions in Section 42.9.3 “SSC Receive Clock Mode Register”, Section 42.9.4 “SSC Receive Frame Mode Register”, Section 42.9.5 “SSC Transmit Clock Mode Register”, Section 42.9.6 “SSC Transmit Frame Mode Register”. Replaced AIC/NVIC wording with “interrupt controller”. 8466 AES: Hardware Counter Measures updated in Section 44.2 ”Embedded Characteristics” and in Section 44.5.1 ”Unspecified Register Access Detection”. rfo SHA: Mode Register reset value updated to 0x1 in Table 45-2, “Register Mapping”. rfo Ordering Information: Ordering codes added for SAM9N12 and SAM9CN11. 8244 Errata: Errata created. Section 49.3 “Marking” moved to Section 51.2 “SAM9N12/CN11/CN12 Errata” on page 1112. rfo Back page: Date updated. DS60001517A-page 1070 rfo  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063F Change Request Ref.(1) Comments Description: Section 1. “Description”, 125 MHz --> 133 MHz 7928 “FIPS PUB 46-3 compliant TDES” removed from 3rd paragraph rfo Signal Description: rfo Table 2-1, “Signal Description List”, NFD0-NFD16 --> NFD0-NFD15 Power Considerations: Section 5.2 Programmable I/O Lines Power Supplies and Current Drive removed from Section 4. “Power Considerations”, as the same contents already exists in Section 26.7.4 “Power Supplies” System Controller: rfo rfo Section 6.3 “Chip Identification”, Chip ID: 0x819A_07A0 --> 0x819A_07A1 Peripherals: Table 7-1, “SAM9N12/CN11/CN12 Peripheral Identifiers”:Replaced keyword ‘Reserved’ on 4th row with ‘FUSE’ 8039 EBI: Section 26.7.4 “Power Supplies”, following sentences added before the 2nd figure: “This can be used if the SMC connects to the NAND Flash only. Using this function with another device on the SMC will lead to an unpredictable behavior of that device. In that case, a default value must be selected.” FUSE: 8008 7928 Section 24. “Fuse Controller (FUSE)” added. MATRIX: Section 25.10.5.1 “EBI Chip Select Assignment Register”, NFD0_ON_D16 bitfield description updated 8008 PMC: Section 20.2 “Embedded Characteristics”, 266 MHz DDR --> 133 MHz DDR 7975 Section 21.8 “Peripheral Clock Controller”, PMC_PCR, 0x10030102 --> PMC_PCR,0x10031002 7920 Electrical Characteristics: rfo Table 47-5, “Processor Clock Waveform Parameters” and Table 47-6, “System Clock Waveform Parameters”, ‘Corner MAX’ changed to ‘VVDDCORE min’ and second row removed. In the note below, ‘LDDDR’ changed to ‘LPDDR’ Table 47-9, “XIN Clock Electrical Characteristics”, VIN row split into 2 rows: VXINLOW and VXINHIGH Section 47.13 “SMC Timings”, “SMC Timings are given for MAX corners” removed Table 47-19, “Channel Conversion Time and ADC Clock” : ‘ADC Clock = 5 MHz’ row added to Conversion Time (TCT) and to ‘Throughput Rate’ 8009 rfo 7947 Table 47-22, “Transfer Characteristics”, 2 rows added: ‘ADC Clock = 13.2 MHz’ and ‘ADC Clock = 5 MHz’  2017 Microchip Technology Inc. DS60001517A-page 1071 SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063E Change Request Ref. Comments Overview: “Description”, updated...”Processor running up to 400 MHz...” 7847 updated...”System running up to 133 MHz...” DDRSDRC: 7891 Former Section 29.7 “Programmable IO Delays” removed from datasheet. PIO: Section 22.5.11 “Programmable I/O Delays”, “Only PADs PA[15:11] and PA[20:18] can be configured.” 7886 Section 22.5.12 “Programmable I/O Drive”, “It is possible to configure the I/O drive for pads PA[31:0], PB[18:0] and PC[31:0].” PMC: Section 20.2 “Embedded Characteristics”, updated, “266 MHz DDR system clock”. 7874 Section 21.12.8 “PMC Clock Generator Main Clock Frequency Register”, added RCMEAS bit to register. 7726 Electrical Characteristics: Table 47-3, “Power Consumption for Different Modes”,  Updated, Active mode power consumption, 103 mA  Updated, Idle mode power consumption, 33 mA 7847 Table 47-5, “Processor Clock Waveform Parameters”  Updated, MAX = 400 MHz Table 47-6, “System Clock Waveform Parameters” Updated, MAX = 133 MHz Section 46.14.5 Two-wire Serial Interface Characteristics removed. 7863 Footnotes updated in Table 47-35, “SSC Timings 3.3V Domain” Back page: Doc. Rev 11063D Updated point of contact information. Marcom Comments Change Request Ref.(1) Overview: Section 5. “Memories”, ...Internal ROM... bootstrap routine, revised. rfo Section 7.5 “Fuse Box Features”, removed table 8.3 Debug and Test: Section 9.6.3 “Debug Unit”, removed unnecessary line on Chip ID rfo Section 9.6.5 “JTAG ID Code Register”, fixed typo in title, revised part number and JTAG ID Code value. DMAC: Section 31.2 “Embedded Characteristics”, missing elements recovered. 7271 TRNG: Section 46. “True Random Number Generator (TRNG)”, faulty section number corrected. Subsequent section numbering and TOC affected. DS60001517A-page 1072 rfo:  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063C Change Request Ref.(1) Comments Overview: “Description” SLC NAND Flash is supported. rfo Section 1. “Description”, 1st paragraph, the 2nd sentence was removed. Table 3-1, “BGA217 Pin Description”, table updated with values in Ball column. Table 4-1, “SAM9N12/CN11/CN12 Power Supplies”, VDDFUSE Voltage Range updated, 3.0V-3.6V. 7395 Section 5.3.3 “DDR-SDRAM Controller”, revised. rfo Section 6.3 “Chip Identification”, removed “two” lines. 7269 Section 7.4 “Peripheral Signal Multiplexing on I/O Lines”, removed irrelevant text. rfo Elsewhere, minor grammar revisions. Advance Information status moved to Preliminary. ARM Processor: rfo: Section 8. “ARM926EJ-S Processor Overview”, removed Tightly-Coupled Memory Interface chapter. Debug and Test: Figure 9-1, Debug and Test Block Diagram, removed PDC. rfo Boot Program: Figure 11-1, ROM Code Algorithm Flow Diagram, updated. 7304 Section 11.2 “SAM9CN11 and SAM9N12 Only”, and forward, grammar and format edits. rfo ADC: 72497250 Section 41.8.12 “ADC Interrupt Status Register”, fixed ADC_SR typos to ADC_ISR. Section 41.8.14 “ADC Extended Mode Register”, values 2 and 3 swapped in CMPMODE bitfield table. Section 41.8.16 “ADC Channel Data Register”, DATA bitfield extended to fields 11 and 10. 7313 rfo Section 41.6.5 “Conversion Triggers”, TRGMOD bitfield refers to Section 41.8.22 “ADC Trigger Register”. AES: Section 44.5.1 “Unspecified Register Access Detection”, updated. 7357 AIC: Section 10.9 “Write Protection Registers” added to datasheet. 7045 “SRCTYPE: Interrupt Source Type” on page 71 bitfield description table updated. 7144 “PRIOR: Priority Level” on page 71, bitfield described in a table. 7191 DDRSDRC: Section 30.2 “Embedded Characteristics”,removed... “eight internal banks not supported.” 7396 Section 30.5.4.1 “Self-refresh Mode” UDP_EN replaced by UPD_MR. In Section 30.7.7 “DDRSDRC Lowpower Register” UDP_MR typo corrected. 7210 “TWTR: Internal Write to Read Delay”, bitfield table updated. rfo DMAC: “FC: Flow Control”, removed last four lines from bitfield table. 7353 Section 31.5.1 “Basic Definitions”, added Programmable Arbitration Policy. 7366 External Memories: Section 26.8.7 “8-bit NAND Flash with NFD0_ON_D16 = 1” Section 26.8.7.2 “Software Configuration”, added the line: “Configure the PIOD controller to assign...”  2017 Microchip Technology Inc. rfo DS60001517A-page 1073 SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063C Change Request Ref.(1) Comments (Continued) HSMCI: Table 35-8, “Register Mapping” and Section 35.14.20 “HSMCI FIFOx Memory Aperture”, HSMCI_FIFOx offset updated. 7253 MATRIX: Section 25-5 “Chip Configuration User Interface”, CCFG_EBICSA offset values revised. rfo PIO: Figure 23-3, I/O Line Control Logic, Table 23-2, “Register Mapping”, “PIO Input Filter Slow Clock Disable Register”, “PIO Input Filter Slow Clock Enable Register”, “PIO Input Filter Slow Clock Status Register”,updated IFSxx register acronyms. 6787 Table 23-2, “Register Mapping”, “PIO I/O Drive Register 1” and “PIO I/O Drive Register 2” added to datasheet. 6876, 7255 PMC: Section 21.12 “Power Management Controller (PMC) User Interface”, PLLB is usable as input clock. 7304 Section 21-3 “Register Mapping”, offset 0x0038 updated with USB Clock Register (PMC_USB). rfo Section 21.5 “Processor Clock Controller”, revised. 7369 Section 21.12.10 “PMC Clock Generator PLLB Register”, removed USBDIV bitfields. rfo Section 21.12.12 “USB Clock Register”, added to datasheet. PMEEC: ERRIE, ERRID, ERRIM bitfields are 1 bit wide. See:Section 28.6.8 “PMECC Interrupt Enable Register”, Section 28.6.9 “PMECC Interrupt Disable Register” and Section 28.6.10 “PMECC Interrupt Mask Register”. 7202 PMERRLOC: Table 29-3, “Register Mapping” PMECC SIGMA 24 is located at 0x088. 7203 Section 29.5.10 “Error Location SIGMAx Register”, updated. SCKC: Section 20. “Slow Clock Controller (SCKC)”, added to datasheet. rfo SMC: Table 30-1, “I/O Line Description”, replaced NCS[7:0] by NCS[5:0] rfo SPI: Section 36.8.9 “SPI Chip Select Register”, “SCBR: Serial Clock Baud Rate”, data transfer note added. 7247 Section 36.8.3 “SPI Receive Data Register”added requirements to bitfield “PCS: Peripheral Chip Select”. Section 36.8.9 “SPI Chip Select Register”, “BITS: Bits Per Transfer”, bitfield table; Description column revised. 7319 7267 Section 36.7.3.5 “Peripheral Selection”, added paragraph at end of the section. TC: Section 37.7.5 “TC Channel Mode Register: Waveform Mode”, updated WAVSEL bitfield table. 7190 “TC Counter Value Register”, “TC Register A”, “TC Register B”, “TC Register C” all bitfields are filled. Figure 37-5, Capture Mode and Figure 37-6, Waveform Mode, revise the counter component. 7318 TRNG: Section 47.2 “Embedded Characteristics”, removed 133 MHz Clock Frequency. rfo Section 47.3.1 “TRNG Control Register”, added KEY bitfield. 5914 DS60001517A-page 1074  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Doc. Rev 11063C Change Request Ref.(1) Comments (Continued) TWI: Section 39.8.7 “Using the DMA Controller”, added to the datasheet. 7306 UDP: Section 33.4 “Product Dependencies”, second paragraph removed. Section 33.5 “Typical Connection”, revised schematic and VBUS Monitoring. 7322 Section 33.6.3.2 “Entering Attached State”, revised, replaced paragraphs before Warning. Section 33.7.12 “UDP Transceiver Control Register”, bit field 9 is dedicated to PUON. UHP: Section 33-1 “Block Diagram”, removed Warning. 7322 Section 33.6 “Typical Connection”, revised schematic and text. USART: Melange of references to PDC/DMA removed in favor of DMA implementation. 7284 UART: Section 41-1 “UART Functional Block Diagram”, revised. 7285 Electrical Characteristics: Table 47-7, “Main Oscillator Characteristics”, revised schematic in note below table. 7304 Table 47-11, “32 kHz Oscillator Characteristics”, revised schematic in note below table. Table 47-5, “Processor Clock Waveform Parameters”, updated. 7334 Table 47-6, “System Clock Waveform Parameters”, replaces “Master Clock Waveform Parameters”. Section 47.13 “SMC Timings”, added to datasheet. Section 47.14 “DDRSDRC Timings”, added to datasheet. Section 47.15 “Peripheral Timings”, added to datasheet. Table 47-2, “DC Characteristics” rfo Table 47-3, “Power Consumption for Different Modes” Table 47-4, “Power Consumption by Peripheral in Active Mode” Table 47-18, “I/O Characteristics” former TBDs assigned values Doc. Rev 11063B Comments Change Request Ref. Table 3-2, “BGA247 Pin Description” updated. 7271 Note 1: “rfo” indicates changes requested during document review and approval loop. Doc. Rev 11063A Comments Change Request Ref. First issue  2017 Microchip Technology Inc. DS60001517A-page 1075 SAM9N12/SAM9CN11/SAM9CN12 The Microchip Web Site Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Design Support”, click on “Customer Change Notification” and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support DS60001517A-page 1076  2017 Microchip Technology Inc. SAM9N12/SAM9CN11/SAM9CN12 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. AT91SAM9 CN12 B - C U R Example: a) Architecture AT91SAM9CN12B-CUR = Arm926 generalpurpose microprocessor, crypto, Secure Boot, 217-ball, industrial temperature, BGA package. Product Group Mask Revision Package Temperature Range Carrier Type Architecture: ATSAM9 = Arm926 processor Product Group: N12 = General-purpose microprocessor CN11 = N12 + crypto (for evaluation only) CN12 = CN11 + crypto + Secure Boot Mask Revision: B Package: C CF = BGA217 = TFBGA247 Note 1: Temperature Range: U = -40°C to +85°C (industrial) Carrier Type: Blank R = Standard Packaging (tray) = Tape and Reel(1)  2017 Microchip Technology Inc. 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. DS60001517A-page 1077 Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. 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Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-2170-2 DS60001517A-page 1078  2017 Microchip Technology Inc. Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2017 Microchip Technology Inc. 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