SAM9XE Series
Atmel | SMART ARM-based Embedded MCU
DATASHEET
Description
The Atmel® | SMART SAM9XE microcontroller series is based on the integration
of an ARM926EJ-S™ processor with fast ROM, RAM and Flash, and a wide
range of peripherals.
The embedded Flash memory can be programmed in-system via the JTAG-ICE
interface or via a parallel interface on a production programmer prior to mounting.
Built-in lock bits, a security bit and MMU protect the firmware from accidental
overwrite and preserve its confidentiality.
The SAM9XE series embeds an Ethernet MAC, one USB Device Port, and a USB
Host Controller. It also integrates several standard peripherals, including six
UARTs, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and a
MultiMedia/SD Card Interface.
The SAM9XE system controller includes a reset controller capable of managing
the power-on sequence of the microcontroller and the complete system. Correct
device operation can be monitored by a built-in brownout detector and a watchdog
running off an integrated RC oscillator.
The SAM9XE series architecture includes a 6-layer matrix, allowing a maximum
internal bandwidth of six 32-bit buses. It also features an External Bus Interface
capable of interfacing with a wide range of memory devices.
The pinout and ball-out are fully compatible with the Atmel | SMART SAM9260
eMPU with the exception that the pin BMS is replaced by the pin ERASE.
SAM9XE Embedded Internal Memories Configuration
Device
ROM
SRAM
High-speed Flash
SAM9XE128
32 KB
16 KB
128 KB
SAM9XE256
32 KB
32 KB
256 KB
SAM9XE512
32 KB
32 KB
512 KB
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Features
Incorporates the ARM926EJ-S ARM® Thumb® Processor
̶ DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
̶ 8 KB Data Cache, 16 KB Instruction Cache, Write Buffer
̶ 200 MIPS at 180 MHz
̶ Memory Management Unit
̶ EmbeddedICE, Debug Communication Channel Support
Additional Embedded Memories
̶ One 32 KB Internal ROM, Single-cycle Access at Maximum Matrix Speed
̶ One 32 KB (SAM9XE256 and SAM9XE512) or 16 KB (SAM9XE128) Internal SRAM, Single-cycle Access at
Maximum Matrix Speed
̶ Internal High-speed Flash: 128 KB (SAM9XE128), 256 KB (SAM9XE256) or 512 KB (SAM9XE512) organized
in 256, 512 or 1024 pages of 512 bytes respectively
̶
128-bit Wide Access
̶
Fast Read Time: 45 ns
̶
Page Programming Time: 4 ms, Including Page Auto-erase
Full Erase Time: 10 ms
̶
10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit
Enhanced Embedded Flash Controller (EEFC)
̶ Interface of the Flash Block with the 32-bit Internal Bus
̶ Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface
2
External Bus Interface (EBI)
̶ Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash®
USB 2.0 Full Speed (12 Mbit/s) Device Port
̶ On-chip Transceiver, 2688-byte Configurable Integrated DPRAM
USB 2.0 Full Speed (12 Mbit/s) Host Single Port in 208-pin PQFP Device and Double Port in 217-ball LFBGA
Device
̶ Single or Dual On-chip Transceivers
̶ Integrated FIFOs and Dedicated DMA Channels
Ethernet MAC 10/100 Base-T
̶ Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
̶ 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Image Sensor Interface (ISI)
̶ ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
̶ 12-bit Data Interface for Support of High Sensibility Sensors
̶ SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
Bus Matrix
̶ Six 32-bit-layer Matrix
̶ Remap Command
Fully-featured System Controller, including
̶ Reset Controller (RSTC), Shutdown Controller (SHDWC)
̶ 128-bit (4 x 32-bit) General Purpose Backup Registers
̶ Clock Generator and Power Management Controller
̶ Advanced Interrupt Controller (AIC) and Debug Unit (DBGU)
̶ Periodic Interval Timer (PIT), Watchdog Timer (WDT) and Real-time Timer (RTT)
Reset Controller (RSTC)
̶ Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Clock Generator (CKGR)
̶ Selectable 32768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power
Supply, Providing a Permanent Slow Clock
̶ 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL
Power Management Controller (PMC)
̶ Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
̶ Two Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
̶ Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
̶ Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
̶ 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention
̶ Mode for General Purpose Two-wire UART Serial Communication
Periodic Interval Timer (PIT)
̶ 20-bit Interval Timer Plus 12-bit Interval Counter
Watchdog Timer (WDT)
̶ Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Real-time Timer (RTT)
̶ 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
One 4-channel 10-bit Analog-to-Digital Converter
Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
̶ 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
̶ Input Change Interrupt Capability on Each I/O Line
̶ Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
Peripheral DMA Controller (PDC) Channels
Two-slot Multimedia Card Interface (MCI)
̶ SDCard/SDIO and MultiMediaCard™ Compliant
̶ Automatic Protocol Control and Fast Automatic Data Transfers with PDC
One Synchronous Serial Controllers (SSC)
̶ Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
̶ I²S Analog Interface Support, Time Division Multiplex Support
̶ High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
̶ Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
̶ Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
̶ Full Modem Signal Control on USART0
One 2-wire UART
Two Master/Slave Serial Peripheral Interface (SPI)
̶ 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
̶ Synchronous Communications
Two 3-channel 16-bit Timer/Counters (TC)
̶ Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
̶ Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
̶ High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
3
4
2 Two-wire Interfaces (TWI)
̶ Master, Multi-master and Slave Mode Operation
̶ General Call Supported in Slave Mode
̶ Connection to PDC Channel to Optimize Data Transfers in Master Mode Only
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies:
̶ 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
̶ 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
̶ 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-Digital Converter)
̶ Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
Available in 208-pin PQFP and 217-ball LFBGA Green-compliant Packages
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
1.
Block Diagram
Figure 1-1, “SAM9XE Series Block Diagram,” on page 6 shows all the features for the 217-LFBGA package.
Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in
“Multiplexing on PIO Controller A” on page 40, “Multiplexing on PIO Controller B” on page 41, “Multiplexing on PIO
Controller C” on page 42. The USB Host Port B is also not available.
Table 1-1 defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package.
Table 1-1.
Unavailable Signals in 208-pin PQFP Device
PIO
Peripheral A
Peripheral B
–
HDPB
–
–
HDMB
–
PA30
SCK2
RXD4
PA31
SCK0
TXD4
PB12
TWD1
ISI_D10
PB13
TWCK1
ISI_D11
PC2
AD2
PCK1
PC3
AD3
SPI1_NPCS3
PC12
IRQ0
NCS7
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
5
I_
M
IS CK
I_
IS PC
I_ K
IS DO
I_ -I
V
IS SY SI_
I_ N D7
HS C
YN
C
HD
HD PA
M
A
HD
PB
HD
M
B
IS
SE
JT
AG
Transc.
FIQ
IRQ0-IRQ2
AIC
DRXD
DTXD
PCK0-PCK1
DBGU
In-Circuit Emulator
PLLA
10/100 Ethernet
MAC
ARM926EJ-S Processor
PDC
PLLRCA
XIN
XOUT
JTAG Selection and Boundary Scan
System Controller
TST
NT
R
TD ST
TDI
TMO
TC S
RTK
CK
ER
AS
E
L
SLAVE
Filter
ICache
16 Kbytes
PMC
DCache
8 Kbytes
MMU
FIFO
PLLB
Transc.
Image
Sensor
Interface
USB
OHCI
DMA
DMA
FIFO
DMA
Bus Interface
I
D
3–20 MHz
Main Osc.
WDT
PIT
6-layer Matrix
Backup Section
OSCSEL
XIN32
XOUT32
RC
Oscillator
128-bit
GPBR
32 kHz
XTAL Osc.
RTT
PIOA
SHDN
WKUP
SHDWC
VDDBU
POR
VDDCORE
POR
Flash
128, 256
or 512
Kbytes
PIOB
PIOC
ROM
32 Kbytes
Fast SRAM
16 or 32
Kbytes
Peripheral
Bridge
EBI
24-channel
Peripheral
DMA
CompactFlash
NAND Flash
RSTC
BOD
NRST
APB
SDRAM
Controller
PDC
MCI
PDC
TWI0
TWI1
PDC
USART0
USART1
USART2
USART3
USART4
PDC
SPI0
SPI1
PDC
TC0
TC1
TC2
TC3
TC4
TC5
SSC
PDC
DPRAM
4-channel
10-bit ADC
USB
Device
Static
Memory
Controller
ECC
Controller
SPI0_, SPI1_
DD
DDM
P
VR
EF
DA
G
N
ND A
AN
A
VD
AD
NP
NPCS
NPCS3
NPCS2
C 1
SP S0
M CK
O
TC
M SI
IS
L
O
TI K0O T
TI A0 CL
O -T K
TC B0 IO 2
L -T A
TI K3 IOB2
O TI A3 TC 2
O -T LK
B3 IO 5
-T A
IO 5
B5
TK
TF
TD
RD
RF
RK
AD
0A
AD D3
TR
IG
Transceiver
T
CT TWWD
RTS0- CK
SC S0 CTS
RX K0 RTS3
-S
TXD0- CK3
D0 RX 3
-T D5
X
DSD5
DCR0
D0
R
DT I0
R0
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
MASTER
ET
ETXC
K
ECXE -E
N R
ERRS -E XC
T
ERXE -EC XE K
R O
ET X0 -E L R
- R
M X0 ER XD
D - X
M C ETX 3 V
DI
3
F1 O
00
SAM9XE Series Block Diagram
M
C
M DB0
CD A0 MC
-M DB
CD 3
M A3
CC
M D
CC B
M DA
CC
K
6
Figure 1-1.
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15, A18-A20
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
A21/NANDALE
A22/NANDCLE
D16-D31
NWAIT
A23-A24
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
CFCE1-CFCE2
NCS2, NCS6, NCS7
NCS3/NANDCS
2.
Signal Description
Table 2-1 gives details on the signal name classified by peripheral.
Table 2-1.
Signal Name
Signal Description List
Function
Type
Active Reference
Level
Voltage Comments
Power Supplies
VDDIOM
EBI I/O Lines Power Supply
Power
1.65V to 1.95V or 3.0V to 3.6V
VDDIOP0
Peripherals I/O Lines Power Supply
Power
3.0V to 3.6V
VDDIOP1
Peripherals I/O Lines Power Supply
Power
1.65V to 3.6V
VDDBU
Backup I/O Lines Power Supply
Power
1.65V to 1.95V
VDDANA
Analog Power Supply
Power
3.0V to 3.6V
VDDPLL
PLL Power Supply
Power
1.65V to 1.95V
VDDCORE
Core Chip and Embedded Memories
Power Supply
Power
1.65V to 1.95V
GND
Ground
Ground
GNDPLL
PLL Ground
Ground
GNDANA
Analog Ground
Ground
GNDBU
Backup Ground
Ground
XIN
Main Oscillator Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
Clocks, Oscillators and PLLs
Input
Output
Input
XOUT32
Slow Clock Oscillator Output
OSCSEL
Slow Clock Oscillator Selection
Output
Input
PLLRCA
PLL A Filter
Input
PCK0–PCK1
Programmable Clock Output
SHDN
Shutdown Control
WKUP
Wake-up Input
VDDBU
Accepts between 0V and VDDBU
(2)
Output
Shutdown, Wakeup Logic
Output
Low
Input
VDDBU
Driven at 0V only
VDDBU
Accepts between 0V and VDDBU
ICE and JTAG
NTRST
Test Reset Signal
Input
TCK
Test Clock
Input
Low
VDDIOP0 No pull-up resistor, Schmitt trigger
TDI
Test Data In
Input
VDDIOP0 No pull-up resistor, Schmitt trigger
TDO
Test Data Out
TMS
Test Mode Select
Input
JTAGSEL
JTAG Selection
Input
VDDBU
RTCK
Return Test Clock
Output
VDDIOP0
Output
VDDIOP0 Pull-up resistor (100 kΩ)
VDDIOP0
VDDIOP0 No pull-up resistor, Schmitt trigger
Pull-down resistor (15 kΩ)
Flash Memory
ERASE
Flash and NVM Configuration Bits
Erase Command
Input
High
VDDIOP0 Pull-down resistor (15 kΩ)
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
7
Table 2-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active Reference
Level
Voltage Comments
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
I/O
Low
Input
Open-drain output, Pull-up
VDDIOP0 resistor (100 kΩ)
Inserted in the Boundary Scan
VDDBU
Pull-down resistor (15 kΩ)
Debug Unit - DBGU
DRXD
Debug Receive Data
Input
(2)
DTXD
Debug Transmit Data
Output
(2)
Advanced Interrupt Controller - AIC
IRQ0–IRQ2
External Interrupt Inputs
Input
(2)
FIQ
Fast Interrupt Input
Input
(2)
PIO Controller - PIOA / PIOB / PIOC
PA0–PA31
Parallel IO Controller A
I/O
VDDIOP0
Pulled-up input at reset
(100 kΩ)(1)
PB0–PB31
Parallel IO Controller B
I/O
VDDIOP0
Pulled-up input at reset
(100 kΩ)(1)
PC0–PC31
Parallel IO Controller C
I/O
(2)
Pulled-up input at reset
(100 kΩ)(1)
External Bus Interface - EBI
D0–D31
Data Bus
A0–A25
Address Bus
NWAIT
External Wait Signal
I/O
VDDIOM
Pulled-up input at reset
Output
VDDIOM
0 at reset
Input
Low
VDDIOM
Static Memory Controller - SMC
NCS0–NCS7
Chip Select Lines
Output
Low
VDDIOM
NWR0–NWR3
Write Signal
Output
Low
VDDIOM
NRD
Read Signal
Output
Low
VDDIOM
NWE
Write Enable
Output
Low
VDDIOM
NBS0–NBS3
Byte Mask Signal
Output
Low
VDDIOM
CompactFlash Support
CFCE1–CFCE2
CompactFlash Chip Enable
Output
Low
VDDIOM
CFOE
CompactFlash Output Enable
Output
Low
VDDIOM
CFWE
CompactFlash Write Enable
Output
Low
VDDIOM
CFIOR
CompactFlash IO Read
Output
Low
VDDIOM
CFIOW
CompactFlash IO Write
Output
Low
VDDIOM
CFRNW
CompactFlash Read Not Write
Output
CFCS0–CFCS1
CompactFlash Chip Select Lines
Output
VDDIOM
Low
VDDIOM
NAND Flash Support
NANDCS
NAND Flash Chip Select
Output
Low
VDDIOM
NANDOE
NAND Flash Output Enable
Output
Low
VDDIOM
NANDWE
NAND Flash Write Enable
Output
Low
VDDIOM
8
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Table 2-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active Reference
Level
Voltage Comments
SDRAM Controller - SDRAMC
SDCK
SDRAM Clock
Output
VDDIOM
SDCKE
SDRAM Clock Enable
Output
High
VDDIOM
SDCS
SDRAM Controller Chip Select
Output
Low
VDDIOM
BA0–BA1
Bank Select
Output
SDWE
SDRAM Write Enable
Output
Low
VDDIOM
RAS - CAS
Row and Column Signal
Output
Low
VDDIOM
SDA10
SDRAM Address 10 Line
Output
VDDIOM
VDDIOM
Multimedia Card Interface - MCI
MCCK
Multimedia Card Clock
Output
VDDIOP0
MCCDA
Multimedia Card Slot A Command
I/O
VDDIOP0
MCDA0–MCDA3
Multimedia Card Slot A Data
I/O
VDDIOP0
MCCDB
Multimedia Card Slot B Command
I/O
VDDIOP0
MCDB0–MCDB3
Multimedia Card Slot B Data
I/O
VDDIOP0
Universal Synchronous Asynchronous Receiver Transmitter - USARTx
SCKx
USARTx Serial Clock
I/O
(2)
TXDx
USARTx Transmit Data
I/O
(2)
RXDx
USARTx Receive Data
Input
(2)
RTSx
USARTx Request To Send
Output
(2)
CTSx
USARTx Clear To Send
Input
(2)
DTR0
USART0 Data Terminal Ready
Output
(2)
DSR0
USART0 Data Set Ready
Input
(2)
DCD0
USART0 Data Carrier Detect
Input
(2)
RI0
USART0 Ring Indicator
Input
(2)
Synchronous Serial Controller - SSC
TD
SSC Transmit Data
Output
(2)
RD
SSC Receive Data
Input
(2)
TK
SSC Transmit Clock
I/O
(2)
RK
SSC Receive Clock
I/O
(2)
TF
SSC Transmit Frame Sync
I/O
(2)
RF
SSC Receive Frame Sync
I/O
(2)
TCLKx
TC Channel x External Clock Input
TIOAx
Timer/Counter - TCx
Input
(2)
TC Channel x I/O Line A
I/O
(2)
TIOBx
TC Channel x I/O Line B
I/O
(2)
SPIx_MISO
Master In Slave Out
I/O
(2)
SPIx_MOSI
Master Out Slave In
I/O
(2)
SPIx_SPCK
SPI Serial Clock
I/O
(2)
SPIx_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
(2)
Output
Low
(2)
Serial Peripheral Interface - SPIx
SPIx_NPCS1–SPIx_NPCS3 SPI Peripheral Chip Select
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
9
Table 2-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active Reference
Level
Voltage Comments
Two-wire Interface - TWI
TWDx
Two-wire Serial Data
I/O
(2)
TWCKx
Two-wire Serial Clock
I/O
(2)
HDPA
USB Host Port A Data +
Analog
VDDIOP0
HDMA
USB Host Port A Data -
Analog
VDDIOP0
HDPB
USB Host Port B Data +
Analog
VDDIOP0
HDMB
USB Host Port B Data +
Analog
VDDIOP0
USB Host Port - UHP
USB Device Port - UDP
DDM
USB Device Port Data -
Analog
VDDIOP0
DDP
USB Device Port Data +
Analog
VDDIOP0
ETXCK
Transmit Clock or Reference Clock
Input
VDDIOP0 MII only, REFCK in RMII
ERXCK
Receive Clock
Input
VDDIOP0 MII only
ETXEN
Transmit Enable
ETX0–ETX3
Transmit Data
Output
VDDIOP0 ETX0–ETX1 only in RMII
ETXER
Transmit Coding Error
Output
VDDIOP0 MII only
ERXDV
Receive Data Valid
Input
VDDIOP0 RXDV in MII, CRSDV in RMII
ERX0–ERX3
Receive Data
Input
VDDIOP0 ERX0–ERX1 only in RMII
Ethernet MAC 10/100 - EMAC
Output
VDDIOP0
ERXER
Receive Error
Input
VDDIOP0
ECRS
Carrier Sense and Data Valid
Input
VDDIOP0 MII only
ECOL
Collision Detect
Input
VDDIOP0 MII only
EMDC
Management Data Clock
EMDIO
Management Data Input/Output
EF100
Force 100Mbit/sec.
Output
VDDIOP0
I/O
Output
VDDIOP0
High
VDDIOP0
Image Sensor Interface - ISI
ISI_D0–ISI_D11
Image Sensor Data
Input
VDDIOP1
ISI_MCK
Image sensor Reference clock
output
VDDIOP1
ISI_HSYNC
Image Sensor Horizontal Synchro
input
VDDIOP1
ISI_VSYNC
Image Sensor Vertical Synchro
input
VDDIOP1
ISI_PCK
Image Sensor Data clock
input
VDDIOP1
AD0–AD3
Analog Inputs
Analog
VDDANA
ADVREF
Analog Positive Reference
Analog
VDDANA
ADTRG
ADC Trigger
Input
VDDANA
Analog-to-Digital Converter - ADC
10
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Digital pulled-up inputs at reset
Table 2-1.
Signal Name
Signal Description List (Continued)
Function
Type
Active Reference
Level
Voltage Comments
Fast Flash Programming Interface - FFPI
PGMEN[3:0]
Programming Enabling
Input
PGMNCMD
Programming Command
Input
Low
VDDIOP0
PGMRDY
Programming Ready
Output
High
VDDIOP0
PGMNOE
Programming Read
Input
Low
VDDIOP0
PGMNVALID
Data Direction
Output
Low
VDDIOP0
PGMM[3:0]
Programming Mode
Input
VDDIOP0
PGMD[15:0]
Programming Data
I/O
VDDIOP0
Notes:
VDDIOP0
1. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all
the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus
Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of
the peripheral multiplexing tables.
2. Refer to PIO Multiplexing (see Section 9.3 “Peripheral Signals Multiplexing on I/O Lines”).
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
11
3.
Package and Pinout
The SAM9XE devices are available in the following Green-compliant packages:
3.1
208-pin PQFP (0.5 mm pitch)
217-ball LFBGA (0.8 mm ball pitch)
208-pin PQFP Package Outline
Figure 3-1 shows the orientation of the 208-pin PQFP package.
A detailed mechanical description is given in Section 43. “Mechanical Characteristics”.
Figure 3-1.
208-pin PQFP Package Outline (Top View)
156
105
157
104
208
53
1
3.2
52
208-pin PQFP Package Pinout
Table 3-1.
Pinout for 208-pin PQFP Package
Pin
Signal Name
Pin
Signal Name
Pin
1
PA24
53
GND
105 RAS
157 ADVREF
2
PA25
54
DDM
106 D0
158 PC0
3
PA26
55
DDP
107 D1
159 PC1
4
PA27
56
PC13
108 D2
160 VDDANA
5
VDDIOP0
57
PC11
109 D3
161 PB10
6
GND
58
PC10
110 D4
162 PB11
7
PA28
59
PC14
111
D5
163 PB20
8
PA29
60
PC9
112 D6
164 PB21
9
PB0
61
PC8
113 GND
165 PB22
10
PB1
62
PC4
114 VDDIOM
166 PB23
11
PB2
63
PC6
115 SDCK
167 PB24
12
PB3
64
PC7
116 SDWE
168 PB25
13
VDDIOP0
65
VDDIOM
117 SDCKE
169 VDDIOP1
14
GND
66
GND
118 D7
170 GND
15
PB4
67
PC5
119 D8
171 PB26
16
PB5
68
NCS0
120 D9
172 PB27
12
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Signal Name
Pin
Signal Name
Table 3-1.
Pinout for 208-pin PQFP Package (Continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
17
PB6
69
CFOE/NRD
121 D10
173 GND
18
PB7
70
CFWE/NWE/NWR0
122 D11
174 VDDCORE
19
PB8
71
NANDOE
123 D12
175 PB28
20
PB9
72
NANDWE
124 D13
176 PB29
21
PB14
73
A22
125 D14
177 PB30
22
PB15
74
A21
126 D15
178 PB31
23
PB16
75
A20
127 PC15
179 PA0
24
VDDIOP0
76
A19
128 PC16
180 PA1
25
GND
77
VDDCORE
129 PC17
181 PA2
26
PB17
78
GND
130 PC18
182 PA3
27
PB18
79
A18
131 PC19
183 PA4
28
PB19
80
BA1/A17
132 VDDIOM
184 PA5
29
TDO
81
BA0/A16
133 GND
185 PA6
30
TDI
82
A15
134 PC20
186 PA7
31
TMS
83
A14
135 PC21
187 VDDIOP0
32
VDDIOP0
84
A13
136 PC22
188 GND
33
GND
85
A12
137 PC23
189 PA8
34
TCK
86
A11
138 PC24
190 PA9
35
NTRST
87
A10
139 PC25
191 PA10
36
NRST
88
A9
140 PC26
192 PA11
37
RTCK
89
A8
141 PC27
193 PA12
38
VDDCORE
90
VDDIOM
142 PC28
194 PA13
39
GND
91
GND
143 PC29
195 PA14
40
ERASE
92
A7
144 PC30
196 PA15
41
OSCSEL
93
A6
145 PC31
197 PA16
42
TST
94
A5
146 GND
198 PA17
43
JTAGSEL
95
A4
147 VDDCORE
199 VDDIOP0
44
GNDBU
96
A3
148 VDDPLL
200 GND
45
XOUT32
97
A2
149 XIN
201 PA18
46
XIN32
98
NWR2/NBS2/A1
150 XOUT
202 PA19
47
VDDBU
99
NBS0/A0
151 GNDPLL
203 VDDCORE
48
WKUP
100 SDA10
152 NC
204 GND
49
SHDN
101 CFIOW/NBS3/NWR3
153 GNDPLL
205 PA20
50
HDMA
102 CFIOR/NBS1/NWR1
154 PLLRCA
206 PA21
51
HDPA
103 SDCS/NCS1
155 VDDPLL
207 PA22
52
VDDIOP0
104 CAS
156 GNDANA
208 PA23
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
13
3.3
217-ball LFBGA Package Outline
Figure 3-2 shows the orientation of the 217-ball LFBGA package.
A detailed mechanical description is given in Section 43. “Mechanical Characteristics”.
Figure 3-2.
217-ball LFBGA Package Outline (Top View)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M N P R T U
Ball A1
3.4
217-ball LFBGA Package Pinout
Table 3-2.
Pinout for 217-ball LFBGA Package
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
CFIOW/NBS3/NWR3
D5
A5
J14
TDO
P17
PB5
A2
NBS0/A0
D6
GND
J15
PB19
R1
NC
A3
NWR2/NBS2/A1
D7
A10
J16
TDI
R2
GNDANA
A4
A6
D8
GND
J17
PB16
R3
PC29
A5
A8
D9
VDDCORE
K1
PC24
R4
VDDANA
A6
A11
D10 GND
K2
PC20
R5
PB12
A7
A13
D11
K3
D15
R6
PB23
A8
BA0/A16
D12 GND
K4
PC21
R7
GND
A9
A18
D13 DDM
K8
GND
R8
PB26
A10
A21
D14 HDPB
K9
GND
R9
PB28
A11
A22
D15 NC
K10
GND
R10 PA0
A12
CFWE/NWE/NWR0
D16 VDDBU
K14
PB4
R11
A13
CFOE/NRD
D17 XIN32
K15
PB17
R12 PA5
A14
NCS0
E1
D10
K16
GND
R13 PA10
A15
PC5
E2
D5
K17
PB15
R14 PA21
A16
PC6
E3
D3
L1
GND
R15 PA23
A17
PC4
E4
D4
L2
PC26
R16 PA24
B1
SDCK
E14
HDPA
L3
PC25
R17 PA29
B2
CFIOR/NBS1/NWR1
E15
HDMA
L4
VDDIOP0
T1
PLLRCA
B3
SDCS/NCS1
E16
GNDBU
L14
PA28
T2
GNDPLL
14
VDDIOM
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
PA4
Table 3-2.
Pinout for 217-ball LFBGA Package (Continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
B4
SDA10
E17
XOUT32
L15
PB9
T3
PC0
B5
A3
F1
D13
L16
PB8
T4
PC1
B6
A7
F2
SDWE
L17
PB14
T5
PB10
B7
A12
F3
D6
M1
VDDCORE
T6
PB22
B8
A15
F4
GND
M2
PC31
T7
GND
B9
A20
F14
OSCSEL
M3
GND
T8
PB29
B10
NANDWE
F15
ERASE
M4
PC22
T9
PA2
B11
PC7
F16
JTAGSEL
M14 PB1
T10
PA6
B12
PC10
F17
TST
M15 PB2
T11
PA8
B13
PC13
G1
PC15
M16 PB3
T12
PA11
B14
PC11
G2
D7
M17 PB7
T13
VDDCORE
B15
PC14
G3
SDCKE
N1
XIN
T14
PA20
B16
PC8
G4
VDDIOM
N2
VDDPLL
T15
GND
B17
WKUP
G14 GND
N3
PC23
T16
PA22
C1
D8
G15 NRST
N4
PC27
T17
PA27
C2
D1
G16 RTCK
N14 PA31
U1
GNDPLL
C3
CAS
G17 TMS
N15 PA30
U2
ADVREF
C4
A2
H1
PC18
N16 PB0
U3
PC2
C5
A4
H2
D14
N17 PB6
U4
PC3
C6
A9
H3
D12
P1
XOUT
U5
PB20
C7
A14
H4
D11
P2
VDDPLL
U6
PB21
C8
BA1/A17
H8
GND
P3
PC30
U7
PB25
C9
A19
H9
GND
P4
PC28
U8
PB27
C10 NANDOE
H10 GND
P5
PB11
U9
PA12
C11
H14 VDDCORE
P6
PB13
U10 PA13
C12 PC12
H15 TCK
P7
PB24
U11
C13 DDP
H16 NTRST
P8
VDDIOP1
U12 PA15
C14 HDMB
H17 PB18
P9
PB30
U13 PA19
C15 NC
J1
PC19
P10
PB31
U14 PA17
C16 VDDIOP0
J2
PC17
P11
PA1
U15 PA16
C17 SHDN
J3
VDDIOM
P12
PA3
U16 PA18
D1
D9
J4
PC16
P13
PA7
U17 VDDIOP0
D2
D2
J8
GND
P14
PA9
D3
RAS
J9
GND
P15
PA26
D4
D0
J10
GND
P16
PA25
PC9
PA14
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
15
4.
Power Considerations
4.1
Power Supplies
The SAM9XE devices have several types of power supply pins. Some supply pins share common ground (GND)
pins whereas others have separate grounds. See Table 4-1.
Table 4-1.
Pin(s)
SAM9XE Power Supply Pins
Item(s) powered
Range
Typical
1.65–1.95 V
1.8V
1.65–1.95 V(1)
1.8V
Ground
Core, including the processor
VDDCORE
Embedded memories
Peripherals
VDDIOM
External Bus Interface I/O lines
VDDIOP0
Peripheral I/O lines and the USB transceivers
3.0–3.6 V
3.3V
VDDIOP1
Peripherals I/O lines involving the Image Sensor Interface
1.65–3.6 V
1.8V
2.5V
3.3V
1.65–1.95 V
1.8V
GNDBU
1.65–1.95 V
1.8V
GNDPLL
3.0–3.6 V
3.3V
GNDANA
VDDBU
Slow Clock oscillator
Part of the System Controller
VDDPLL
PLL cells main oscillator
VDDANA
Analog-to-Digital Converter
Note:
1.
3.0–3.6 V
(1)
3.3V
GND
Desired voltage range selectable by software
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and their associated I/O
lines in the multiplexing tables. These supplies enable the user to power the device differently for interfacing with
memories and for interfacing with peripherals.
4.2
Power Sequence Requirements
The board design must comply with the power-up guidelines below to guarantee reliable operation of the device.
Any deviation from these sequences may prevent the device from booting.
4.2.1
Power-up Sequence
VDDCORE and VDDBU are controlled by internal POR (Power-On-Reset) to guarantee that these power sources
reach their target values prior to the release of POR.
To ensure a working system, VDDIOP0, VDDIOP1, and VDDIOM should be established to power external
memories and I/Os before the first access. This can be achieved if VDDIOP0, VDDIOP1, and VDDIOM are
powered before VDDCORE.
4.2.2
Power-down Sequence
To ensure external memories and I/Os are powered until the last access, switch off VDDIOM, VDDIOP0 and
VDDIOP1 power supplies after or at the same time as switching off VDDCORE.
No power-up or power-down restrictions apply to VDDBU, VDDPLL and VDDANA.
16
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
5.
I/O Line Considerations
5.1
ERASE Pin
The ERASE pin is used to re-initialize the Flash content and the NVM bits. It integrates a permanent pull-down
resistor of about 15 kΩ, so that it can be left unconnected for normal operations. The ERASE pin is powered by
VDDIOP0 rail.
This pin is debounced on the RC oscillator or 32768 Hz low-power oscillator to improve the glitch tolerance.
Minimum debouncing time is 200 ms.
5.2
I/O Line Drive Levels
The PIO lines PA0 to PA31 and PB0 to PB31 and PC0 to PC3 are high-drive current capable. Each of these I/O
lines can drive up to 16 mA permanently with a total of 350 mA on all I/O lines.
Refer to Section 42.2 “DC Characteristics”.
5.3
Shutdown Logic Pins
The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up.
An external pull-up to VDDBU is needed and its value must be higher than 1 MΩ. The resistor value is calculated
according to the regulator enable implementation and the SHDN level.
The WKUP pin is an input-only. It can accept voltages only between 0V and VDDBU.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
17
6.
Processor and Architecture
6.1
ARM926EJ-S Processor
RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration
Two Instruction Sets
̶
ARM High-performance 32-bit Instruction Set
̶
Thumb High Code Density 16-bit Instruction Set
DSP Instruction Extensions
5-Stage Pipeline Architecture:
̶
Instruction Fetch (F)
̶
Instruction Decode (D)
̶
Execute (E)
̶
Data Memory (M)
̶
Register Write (W)
8 KB Data Cache, 16 KB Instruction Cache
̶
Virtually-addressed 4-way Associative Cache
̶
Eight words per line
̶
Write-through and Write-back Operation
̶
Pseudo-random or Round-robin Replacement
Write Buffer
̶
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
̶
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
̶
Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
Access Permission for Sections
̶
Access Permission for large pages and small pages can be specified separately for each quarter of
the page
̶
̶
18
16 embedded domains
Bus Interface Unit (BIU)
̶
Arbitrates and Schedules AHB Requests
̶
Separate Masters for both instruction and data access providing complete Matrix system flexibility
̶
Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
̶
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
6.2
Bus Matrix
6-layer Matrix, handling requests from 6 masters
Programmable Arbitration strategy
̶
Fixed-priority Arbitration
̶
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default
master
Burst Management
̶
Breaking with Slot Cycle Limit Support
̶
Undefined Burst Length Support
One Address Decoder provided per Master
̶
6.2.1
Three different slaves may be assigned to each decoded memory area: one for internal ROM boot,
one for internal flash boot, one after remap
Boot Mode Select
̶
Non-volatile Boot Memory can be internal ROM or internal Flash
̶
Selection is made by General purpose NVM bit sampled at reset
Remap Command
̶
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or Flash)
̶
Allows Handling of Dynamic Exception Vectors
Matrix Masters
The Bus Matrix manages six Masters, thus each master can perform an access concurrently with others,
depending on whether the slave it accesses is available.
Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the
addressing, all the masters have the same decodings.
Table 6-1.
6.2.2
List of Bus Matrix Masters
Master 0
ARM926™ Instruction
Master 1
ARM926 Data
Master 2
Peripheral DMA Controller
Master 3
USB Host Controller
Master 4
Image Sensor Controller
Master 5
Ethernet MAC
Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 6-2.
Slave 0
Slave 1
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
USB Host User Interface
Slave 2
External Bus Interface
Slave 3
Internal Flash
Slave 4
Internal Peripherals
Slave 5
Reserved
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
19
6.2.3
Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing
access from the Ethernet MAC to the internal peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table.
Table 6-3.
Masters to Slaves Access
0 and 1
2
3
4
5
ARM926
Instruction and
Data
Peripheral DMA
Controller
ISI Controller
Ethernet MAC
USB Host
Controller
Internal SRAM
X
X
X
X
X
Internal ROM
X
X
–
–
–
UHP User Interface
X
–
–
–
–
2
External Bus Interface
X
X
X
X
X
3
Internal Flash
X
–
–
X
–
4
Internal Peripherals
X
X
–
–
–
–
Reserved
–
–
–
–
–
Master
Slave
0
1
20
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
6.3
Peripheral DMA Controller
Acting as one Matrix Master
Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.
Next Pointer Support, forbids strong real-time constraints on buffer management.
Twenty-four channels
̶
Two for each USART
̶
Two for the Debug Unit
̶
Two for each Serial Synchronous Controller
̶
Two for each Serial Peripheral Interface
̶
Two for the Two Wire Interface
̶
One for Multimedia Card Interface
̶
One for Analog-to-Digital Converter
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities
(Low to High priorities):
̶
TWI0 Transmit Channel
̶
TWI1 Transmit Channel
̶
DBGU Transmit Channel
̶
USART4 Transmit Channel
̶
USART3 Transmit Channel
̶
USART2 Transmit Channel
̶
USART1 Transmit Channel
̶
USART0 Transmit Channel
̶
SPI1 Transmit Channel
̶
SPI0 Transmit Channel
̶
SSC Transmit Channel
̶
TWI0 Receive Channel
̶
TWI1 Receive Channel
̶
DBGU Receive Channel
̶
USART4 Receive Channel
̶
USART3 Receive Channel
̶
USART2 Receive Channel
̶
USART1 Receive Channel
̶
USART0 Receive Channel
̶
ADC Receive Channel
̶
SPI1 Receive Channel
̶
SPI0 Receive Channel
̶
SSC Receive Channel
̶
MCI Transmit/Receive Channel
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
21
6.4
Debug and Test Features
22
ARM926 Real-time In-circuit Emulator
̶
Two real-time Watchpoint Units
̶
Two Independent Registers: Debug Control Register and Debug Status Register
̶
Test Access Port Accessible through JTAG Protocol
̶
Debug Communications Channel
Debug Unit
̶
Two-pin UART
̶
Debug Communication Channel Interrupt Handling
̶
Chip ID Register
IEEE1149.1 JTAG Boundary-scan on All Digital Pins
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
7.
Memories
Figure 7-1.
Memory Mapping
Address Memory Space
Internal Memory Mapping
0x0000 0000
Notes : (1) Can be ROM or Flash
depending on GPNVM[3]
0x0000 0000
Boot Memory (1)
Internal Memories
256 Mbytes
0x10 0000
ROM
0x0FFF FFFF
EBI
Chip Select 0
Reserved
256 Mbytes
0x20 0000
Flash
128, 256 or 512 Kbytes
0x28 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
32 Kbytes
0x10 8000
0x1000 0000
Reserved
EBI
Chip Select 1/
SDRAMC
256 Mbytes
0x30 0000
SRAM
32 Kbytes
0x30 8000
Reserved
0x3000 0000
0x50 0000
EBI
Chip Select 2
UHP
256 Mbytes
0x50 4000
EBI
Chip Select 3/
NANDFlash
256 Mbytes
0x0FFF FFFF
EBI
Chip Select 4/
Compact Flash
Slot 0
256 Mbytes
EBI
Chip Select 5/
Compact Flash
Slot 1
256 Mbytes
16 Kbytes
0x3FFF FFFF
0x4000 0000
Reserved
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
0x7000 0000
Peripheral Mapping
0xF000 0000
System Controller Mapping
Reserved
0xFFFA 0000
EBI
Chip Select 6
256 Mbytes
0x7FFF FFFF
0x8000 0000
TCO, TC1, TC2
16 Kbytes
UDP
16 Kbytes
MCI
16 Kbytes
TWI0
16 Kbytes
0xFFFF C000
Reserved
0xFFFA 4000
0xFFFF E800
0xFFFA 8000
EBI
Chip Select 7
256 Mbytes
0xFFFA C000
0x8FFF FFFF
0x9000 0000
ECC
512 bytes
SDRAMC
512 bytes
SMC
512 bytes
MATRIX
512 bytes
0xFFFF EA00
0xFFFF EC00
0xFFFB 0000
USART0
16 Kbytes
0xFFFB 4000
0xFFFF EE00
USART1
16 Kbytes
0xFFFB 8000
USART2
16 Kbytes
SSC
16 Kbytes
ISI
16 Kbytes
EMAC
16 Kbytes
0xFFFF F000
0xFFFB C000
AIC
512 bytes
0xFFFF F200
0xFFFC 0000
1,518 Mbytes
SPI0
16 Kbytes
SPI1
16 Kbytes
USART3
16 Kbytes
USART4
16 Kbytes
0xFFFF FC00
16 Kbytes
0xFFFF FD00
0xFFFD 8000
TWI1
TC3, TC4, TC5
16 Kbytes
0xFFFF FD20
0xFFFE 0000
ADC
0xFFFF FD30
16 Kbytes
0xFFFF FD50
0xFFFF C000
EEFC
512 bytes
PMC
256 bytes
RSTC
16 bytes
SHDWC
16 bytes
RTT
16 bytes
PIT
16 bytes
WDT
16 bytes
Reserved
0xFFFF FD60
SYSC
0xFFFF FFFF
512 bytes
0xFFFF FD40
0xFFFE 4000
Reserved
0xFFFF FFFF
PIOC
0xFFFF FD10
0xFFFD C000
256 Mbytes
512 bytes
0xFFFF FA00
0xFFFD 4000
Internal Peripherals
512 bytes
0xFFFF F800
0xFFFD 0000
0xF000 0000
PIOA
PIOB
0xFFFC C000
0xEFFF FFFF
512 bytes
0xFFFF F600
0xFFFC 8000
Undefined
(Abort)
DBGU
0xFFFF F400
0xFFFC 4000
16 Kbytes
0xFFFF FD70
0xFFFF FFFF
GPBR
16 bytes
Reserved
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
23
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High
performance Bus (AHB) for its Master and Slave interfaces with additional features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 MB. Banks 1 to 7 are directed to the EBI
that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the
addressing of the internal memories, and a second level of decoding provides 1 MB of internal memory area. Bank
15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master requesting such an
access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master.
However, in order to simplify the mappings, all the masters have a similar address decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the
memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap, refer to
Table 7-3, “Internal Memory Mapping,” on page 28 for details.
7.1
Embedded Memories
7.1.1
SAM9XE128
32 KB ROM
̶
Single Cycle Access at full matrix speed
16 KB Fast SRAM
128 KB Embedded Flash
̶
7.1.2
Single Cycle Access at full matrix speed
SAM9XE256
32 KB ROM
̶
Single Cycle Access at full matrix speed
32 KB Fast SRAM
̶
7.1.3
Single Cycle Access at full matrix speed
256 KB Embedded Flash
SAM9XE512
32 KB ROM
32 KB Fast SRAM
̶
̶
Single Cycle Access at full matrix speed
7.1.4
Single Cycle Access at full matrix speed
512 KB Embedded Flash
ROM Topology
The embedded ROM contains the Fast Flash Programming and the SAM-BA® boot programs. Each of these two
programs is stored on 16 KB Boundary of FFPI and the program executed at address zero depends on the
combination of the TST pin and PA0 to PA3 pins. Figure 7-2 shows the contents of the ROM and the program
available at address zero.
24
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Figure 7-2.
ROM Boot Memory Map
0x0000 0000
0x0000 0000
0x0000 0000
SAM-BA
Program
SAM-BA
Program
FFPI
Program
TST=0
TST=1
PA0=1
PA1=1
PA2=0
PA3=0
FFPI
Program
0x0000 7FFF
0x0000 3FFF
ROM
0x0000 3FFF
7.1.4.1 Fast Flash Programming Interface
The Fast Flash Programming Interface programs the device through a serial JTAG interface or a multiplexed fullyhandshaked parallel port. It allows gang-programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin
and the PA0 and PA1 pins are all tied high, while PA2 and PA3 are tied low.
Table 7-1.
Signal Description
Signal Name
PIO
Type
Active Level
Comments
PGMEN0
PA0
Input
High
Must be connected to VDDIO
PGMEN1
PA1
Input
High
Must be connected to VDDIO
PGMEN2
PA2
Input
Low
Must be connected to GND
PGMEN3
PA3
Input
Low
Must be connected to GND
PGMNCMD
PA4
Input
Low
Pulled-up input at reset
PGMRDY
PA5
Output
High
Pulled-up input at reset
PGMNOE
PA6
Input
Low
Pulled-up input at reset
PGMNVALID
PA7
Output
Low
Pulled-up input at reset
PGMM[3:0]
PA8..PA10
Input
Pulled-up input at reset
PGMD[15:0]
PA12..PA27
Input/Output
Pulled-up input at reset
7.1.4.2 SAM-BA Boot Assistant
The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip
Flash memory.
The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port.
Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via software autodetection.
Communication through the USB Device Port is depends on crystal selected:
̶
limited to an 18432 Hz crystal if the internal RC oscillator is selected
̶
supports a wide range of crystals from 3 to 20 MHz if the 32768 Hz crystal is selected
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
SAM9XE Series [DATASHEET]
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25
7.1.5
Embedded Flash
The Flash is organized in 256/512/1024 pages of 512 bytes directly connected to the 32-bit internal bus. Each
page contains 128 words.
The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is write-only as 128 32bit words, and accessible all along the 1 MB address space, so that each word can be written at its final address.
The Flash benefits from the integration of a power reset cell and from a brownout detector to prevent code
corruption during power supply changes, even in the worst conditions.
7.1.5.1 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked.
The Enhanced Embedded Flash Controller (EEFC) is a slave for the bus matrix and is configurable through its
User Interface on the APB bus. It ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit
wide memory interface increases performance, four 32-bit data are read during each access, this multiply the
throughput by 4 in case of consecutive data.
It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of
commands. One of the commands returns the embedded Flash descriptor definition that informs the system about
the Flash organization, thus making the software generic programming of the access parameters of the Flash
(number of wait states, timings, etc.)
7.1.5.2 Lock Regions
The memory plane of 128, 256 or 512 KB is organized in 8, 16 or 32 locked regions of 32 pages each. Each lock
region can be locked independently, so that the software protects the first memory plane against erroneous
programming:
If a locked-regions erase or program command occurs, the command is aborted and the EEFC could trigger an
interrupt.
The Lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables
the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
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Figure 7-3.
Flash First Memory Plane Mapping
0x0020 0000
Locked Region 0
Page 0
Locked Regions Area
128, 256 or 512 Kbytes
256, 512 or
1024 Pages
Page 31
Locked Region 7, 15 or 31
0x0021 FFFF
or 0x0023 FFFF
or 0x0027 FFFF
512 bytes
16 Kbytes
32 bits wide
7.1.5.3 GPNVM Bits
The SAM9XE devices feature four GPNVM bits that can be cleared or set respectively through the commands
“Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
Table 7-2.
General-purpose Non-volatile Memory Bits
GPNVMBit[#]
Function
0
Security Bit
1
Brownout Detector Enable
2
Brownout Detector Reset Enable
3
Boot Mode Select (BMS)
7.1.5.4 Security Bit
The SAM9XE devices feature a security bit, based on a specific GPNVM bit, GPNVMBit[0]. When the security is
enabled, access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is
forbidden. This ensures the confidentiality of the code programmed in the Flash.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash are permitted.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation.
SAM9XE Series [DATASHEET]
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27
7.1.5.5 Non-volatile Brownout Detector Control
Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a power loss, the
brownout detector operations remain in their state.
7.1.6
GPNVMBit[1] is used as a brownout detector enable bit. Setting GPNVMBit[1] enables the BOD, clearing it
disables the BOD. Asserting ERASE clears GPNVMBit[1] and thus disables the brownout detector by
default.
GPNVMBit[2] is used as a brownout reset enable signal for the reset controller. Setting GPNVMBit[2]
enables the brownout reset when a brownout is detected, clearing GPNVMBit[2] disables the brownout
reset. Asserting ERASE disables the brownout reset by default.
Boot Strategies
Table 7-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the
GPNVMBit[3] state at reset.
Table 7-3.
Internal Memory Mapping
REMAP = 0
Address
GPNVMBit[3] clear
GPNVMBit[3] set
REMAP = 1
0x0000 0000
ROM
Flash
SRAM
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory
layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by
software once the system has booted. Refer to Section 20. “SAM9XE Bus Matrix” for more details.
When REMAP = 0, a non-volatile bit stored in Flash memory (GPNVMBit[3]) allows the user to lay out to 0x0, at his
convenience, the ROM or the Flash. Refer to Section 19. “Enhanced Embedded Flash Controller (EEFC)” for more
details.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in Figure 7-1 on page 23.
The SAM9XE Matrix manages a boot memory that depends on the value of GPNVMBit[3] at reset. The internal
memory area mapped between address 0x0 and 0x0FFF FFFF is reserved for this purpose.
If GPNVMBit[3] is set, the boot memory is the internal Flash memory
If GPNVMBit[3] is clear (Flash reset State), the boot memory is the embedded ROM. After a Flash erase, the boot
memory is the internal ROM.
7.1.6.1 GPNVMBit[3] = 0, Boot on Embedded ROM
The system boots using the Boot Program.
Boot on slow clock (On-chip RC oscillator or 32768 Hz low-power oscillator)
Auto baud rate detection
SAM-BA Boot in case no valid program is detected in external NVM, supporting
̶
Serial communication on a DBGU
̶
USB Device Port
7.1.6.2 GPNVMBit[3] = 1, Boot on Internal Flash
Boot on slow clock (On-chip RC oscillator or 32768 Hz low-power oscillator)
The customer-programmed software must perform a complete configuration.
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To speed up the boot sequence when booting at 32 kHz, the user must take the following steps:
1.
7.2
Program the PMC (main oscillator enable or bypass mode)
2.
Program and start the PLL
3.
Switch the main clock to the new value.
External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256 MB
memory area assigned.
Refer to the memory map in Figure 7-1 on page 23.
7.2.1
External Bus Interface
Integrates three External Memory Controllers:
̶
Static Memory Controller
̶
SDRAM Controller
̶
ECC Controller
Additional logic for NAND Flash
Full 32-bit External Data Bus
Up to 26-bit Address Bus (up to 64 MB linear)
Up to 8 chip selects, Configurable Assignment:
Static Memory Controller on NCS0
̶
SDRAM Controller or Static Memory Controller on NCS1
̶
Static Memory Controller on NCS2
̶
Static Memory Controller on NCS3, Optional NAND Flash support
̶
̶
Static Memory Controller on NCS4–NCS5, Optional CompactFlash support
̶
7.2.2
Static Memory Controller on NCS6–NCS7
Static Memory Controller
8-, 16- or 32-bit Data Bus
Multiple Access Modes supported
̶
Byte Write or Byte Select Lines
̶
Asynchronous read in Page Mode supported (4- up to 32-byte page size)
Multiple device adaptability
̶
Compliant with LCD Module
̶
Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
̶
Programmable Wait State Generation
̶
External Wait Request
̶
Programmable Data Float Time
Slow Clock mode supported
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29
7.2.3
SDRAM Controller
Supported devices:
̶
Standard and Low Power SDRAM (Mobile SDRAM)
Numerous configurations supported
̶
2K, 4K, 8K Row Address Memory Parts
̶
SDRAM with two or four Internal Banks
̶
SDRAM with 16- or 32-bit Datapath
Programming facilities
̶
Word, half-word, byte access
̶
Automatic page break when Memory Boundary has been reached
̶
Multibank Ping-pong Access
̶
Timing parameters specified by software
̶
Automatic refresh operation, refresh rate is programmable
Energy-saving capabilities
̶
Self-refresh, power down and deep power down modes supported
Error detection
̶
7.2.4
Refresh Error Interrupt
SDRAM Power-up Initialization by software
CAS Latency of 1, 2 and 3 supported
Auto Precharge Command not used
Error Correction Code Controller
Hardware error correction code generation
Supports NAND Flash and SmartMedia devices with 8- or 16-bit datapath
Supports NAND Flash and SmartMedia with page sizes of 528,1056, 2112 and 4224 bytes specified by
software
Supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit datapath
Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit
datapath
Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit
datapath
̶
7.2.5
Detection and correction by software
I/O Drive Selection
The purpose of this control is to adapt the signal to the frequency. Two bits enable the user to select High or Low
Drive for memory data/addresses/control signals.
Setting the EBI_DRIVE field [17:16] in the EBI Chip Select Assignment Register (EBI_CSA) located in the Chip
Configuration User Interface of the Bus Matrix, enables control of the EBI.
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8.
System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system, such as power,
resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for
the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range
for external memories.
The System Controller’s peripherals are all mapped within the highest 16 KB of address space, between
addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All the registers of the
System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the
Load/Store instruction have an indexing mode of ±4 KB.
Figure 8-1 on page 32 shows the System Controller block diagram.
Figure 7-1 on page 23 shows the mapping of the User Interfaces of the System Controller peripherals.
SAM9XE Series [DATASHEET]
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31
8.1
System Controller Block Diagram
Figure 8-1.
System Controller Block Diagram
System Controller
VDDCORE Powered
irq0-irq2
fiq
periph_irq[2..24]
efc2_irq
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
ntrst
PCK
debug
MCK
periph_nreset
dbgu_rxd
Debug
Unit
MCK
debug
periph_nreset
Periodic
Interval
Timer
pit_irq
Watchdog
Timer
wdt_irq
gpnvm[2]
POR
dbgu_txd
jtag_nreset
MCK
periph_nreset
Reset
Controller
periph_nreset
proc_nreset
backup_nreset
security_bit(gpnvm0)
flash_poe
flash_poe
flash_wrdis
VDDBU Powered
SLCK
SLCK
backup_nreset
Real-time
Timer
rtt_irq
SLCK
XIN32
backup_nreset
periph_nreset
rtt0_alarm
PLLRCA
USB Host
Port
periph_irq[20]
Slow Clock
Osicllator
128-bit General-Purpose
Backup Registers
SLCK
XOUT
gpnvm[1..3]
periph_clk[20]
Shutdown
Controller
XOUT32
XIN
cal
UHPCK
WKUP
OSCSEL
Embedded
Flash
rtt_alarm
SHDN
RC
Oscillator
Bus Matrix
rstc_irq
NRST
VDDBU
POR
Boundary Scan
TAP Controller
gpnvm[3]
bod_rst_en
BOD
por_ntrst
jtag_nreset
dbgu_irq
wdt_fault
WDRPROC
flash_wrdis
VDDBU
ARM926EJ-S
proc_nreset
cal
gpnvm[1]
VDDCORE
por_ntrst
int
SLCK
debug
idle
proc_nreset
VDDCORE
nirq
nfiq
Advanced
Interrupt
Controller
UDPCK
int
Main
Oscillator
MAINCK
PLLA
PLLACK
PLLB
Power
Management
Controller
periph_clk[2..27]
pck[0-1]
periph_clk[10]
PCK
UDPCK
periph_nreset
USB
Device
Port
periph_irq[10]
UHPCK
MCK
PLLBCK
pmc_irq
periph_nreset
idle
periph_clk[6..24]
periph_nreset
periph_nreset
periph_clk[2..4]
dbgu_rxd
PA0-PA31
PB0-PB31
PC0-PC31
32
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PIO
Controllers
periph_irq[2..4]
irq0-irq2
fiq
dbgu_txd
Embedded
Peripherals
periph_irq[6..24]
in
out
enable
8.2
Reset Controller
Based on two Power-on reset cells
̶
One on VDDBU and one on VDDCORE
Status of the last reset
̶
8.3
Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or
watchdog reset
Controls the internal resets and the NRST pin output
̶
Allows shaping a reset signal for the external devices
̶
At reset the NRST pin is an output
Brownout Detector and Power-on Reset
The SAM9XE devices embed one brownout detection circuit and power-on reset cells. The power-on reset are
supplied with and monitor VDDCORE and VDDBU.
Signals (flash_poe and flash_wrdis) are provided to the Flash to prevent any code corruption during power-up or
power-down sequences or if brownouts occur on the VDDCORE power supply.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up
until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full reinitialization of the device.
The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It
secures system operations in the most difficult environments and prevents code corruption in case of brownout on
the VDDCORE.
When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (VBOT-), the
brownout output is immediately activated. For more details on VBOT, see Table 42-3, “Brownout Detector
Characteristics”.
When VDDCORE increases above the trigger level (VBOT+, defined as VBOT + Vhys), the reset is released. The
brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer
than about 1 µs.
The VDDCORE threshold voltage has a hysteresis of about 50 mV typical, to ensure spike free brownout
detection. The typical value of the brownout detector threshold is 1.55V with an accuracy of ± 2% and is factory
calibrated.
The brownout detector is low-power, as it consumes less than 12 µA static current. However, it can be deactivated
to save its static current. In this case, it consumes less than 1 µA. The deactivation is configured through the
GPNVMBit[1] of the Flash.
Additional information can be found in Section 42. “Electrical Characteristics”.
8.4
Shutdown Controller
Shutdown and Wake-up logic
̶
Software programmable assertion of the SHDN pin
̶
Deassertion Programmable on a WKUP pin level change or on alarm
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33
8.5
Clock Generator
Embeds a low power 32768 Hz slow clock oscillator and a low-power RC oscillator selectable with OSCSEL
signal
̶
8.6
8.8
8.9
̶
Oscillator bypass feature
̶
Supports 3 to 20 MHz crystals
Embeds 2 PLLs
̶
PLL A outputs 80 to 240 MHz clock
̶
PLL B outputs 70 MHz to 130 MHz clock
̶
Both integrate an input divider to increase output accuracy
̶
PLLB embeds its own filter
Provides:
̶
the Processor Clock PCK
̶
the Master Clock MCK, in particular to the Matrix and the memory interfaces
̶
the USB Device Clock UDPCK
̶
independent peripheral clocks, typically at the frequency of MCK
̶
2 programmable clock outputs: PCK0, PCK1
Five flexible operating modes:
̶
Normal Mode, processor and peripherals running at a programmable frequency
̶
Idle Mode, processor stopped waiting for an interrupt
̶
Slow Clock Mode, processor and peripherals running at low frequency
̶
Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped
waiting for an interrupt
̶
Backup Mode, Main Power Supplies off, VDDBU powered by a battery
Periodic Interval Timer
Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
Includes a 12-bit Interval Overlay Counter
Real-time OS or Linux®/WindowsCE® compliant tick generator
Watchdog Timer
16-bit key-protected only-once-Programmable Counter
Windowed, prevents the processor to be in a dead-lock on the watchdog access
Real-time Timer
34
Embeds the main oscillator
Power Management Controller
8.7
Provides the permanent slow clock SLCK to the system
Real-time Timer with 32-bit free-running back-up counter
Integrates a 16-bit programmable prescaler running on slow clock
Alarm Register capable to generate a wake-up of the system through the Shutdown Controller
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
8.10
General-purpose Back-up Registers
8.11
Four 32-bit general-purpose backup registers
Advanced Interrupt Controller
Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
Thirty-two individually maskable and vectored interrupt sources
̶
̶
Source 0 is reserved for the Fast Interrupt Input (FIQ)
Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
̶
Programmable Edge-triggered or Level-sensitive Internal Sources
̶
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
Three External Sources plus the Fast Interrupt signal
8-level Priority Controller
̶
Drives the Normal Interrupt of the processor
̶
Handles priority of the interrupt sources 1 to 31
̶
Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
̶
Optimizes Interrupt Service Routine Branch and Execution
̶
One 32-bit Vector Register per interrupt source
̶
Interrupt Vector Register reads the corresponding current Interrupt Vector
Protect Mode
̶
Easy debugging by preventing automatic operations when protect modules are enabled
Fast Forcing
̶
8.12
Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
Debug Unit
Composed of two functions
̶
Two-pin UART
̶
Debug Communication Channel (DCC) support
Two-pin UART
̶
Implemented features are 100% compatible with the standard Atmel USART
̶
Independent receiver and transmitter with a common programmable Baud Rate Generator
̶
Even, Odd, Mark or Space Parity Generation
̶
Parity, Framing and Overrun Error Detection
̶
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
̶
Support for two PDC channels with connection to receiver and transmitter
Debug Communication Channel Support
̶
Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM
Processor’s ICE Interface
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35
8.13
Chip Identification
36
Chip ID:
̶
0x329AA3A0 for the SAM9XE512
̶
0x329A93A0 for the SAM9XE256
̶
0x329973A0 for the SAM9XE128
JTAG ID: 05B1_C03F
ARM926 TAP ID: 0x0792603F
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9.
Peripherals
9.1
User Interface
The Peripherals are mapped in the upper 256 MB of the address space between the addresses 0xFFFA 0000 and
0xFFFC FFFF. Each User Peripheral is allocated 16 KB of address space. A complete memory map is presented
in Figure 7-1 on page 23.
9.2
Peripheral Identifier
The SAM9XE devices embed a wide range of peripherals. Table 9-1 defines the Peripheral Identifiers of the
SAM9XE devices. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced
Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
Table 9-1.
Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
Peripheral Name
External Interrupt
0
AIC
Advanced Interrupt Controller
FIQ
1
SYSC
System Controller Interrupt
2
PIOA
Parallel I/O Controller A
3
PIOB
Parallel I/O Controller B
4
PIOC
Parallel I/O Controller C
5
ADC
Analog-to-Digital Converter
6
US0
USART 0
7
US1
USART 1
8
US2
USART 2
9
MCI
Multimedia Card Interface
10
UDP
USB Device Port
11
TWI0
Two Wire Interface 0
12
SPI0
Serial Peripheral Interface 0
13
SPI1
Serial Peripheral Interface1
14
SSC
Synchronous Serial Controller
15
–
Reserved
16
–
Reserved
17
TC0
Timer/Counter 0
18
TC1
Timer/Counter 1
19
TC2
Timer/Counter 2
20
UHP
USB Host Port
21
EMAC
Ethernet MAC
22
ISI
Image Sensor Interface
23
US3
USART 3
24
US4
USART 4
25
TWI1
Two Wire Interface 1
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37
Table 9-1.
Peripheral ID
Peripheral Mnemonic
Peripheral Name
26
TC3
Timer/Counter 3
27
TC4
Timer/Counter 4
28
TC5
Timer/Counter 5
29
AIC
Advanced Interrupt Controller
IRQ0
30
AIC
Advanced Interrupt Controller
IRQ1
31
Note:
9.2.1
Peripheral Identifiers (Continued)
External Interrupt
AIC
Advanced Interrupt Controller
IRQ2
Setting AIC, SYSC, UHP, ADC and IRQ0–2 bits in the clock set/clear registers of the PMC has no effect. The ADC
clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each
conversion.
Peripheral Interrupts and Clock Control
9.2.1.1 System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
SDRAM Controller
Debug Unit
Periodic Interval Timer
Real-time Timer
Watchdog Timer
Reset Controller
Power Management Controller
Enhanced Embedded Flash Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced
Interrupt Controller.
9.2.1.2 External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a
dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.
38
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
9.3
Peripheral Signals Multiplexing on I/O Lines
The SAM9XE devices feature three PIO controllers (PIOA, PIOB, PIOC) which multiplex the I/O lines of the
peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B.
The multiplexing tables in the following sections define how the I/O lines of peripherals A and B are multiplexed on
the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s
own comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is
mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state
as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR
(Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address
lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also
enabled in this case.
SAM9XE Series [DATASHEET]
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39
9.3.1
PIO Controller A Multiplexing
Table 9-2.
Multiplexing on PIO Controller A
PIO Controller A
I/O Line
Peripheral A
Peripheral B
PA0
SPI0_MISO
PA1
SPI0_MOSI
PA2
SPI0_SPCK
PA3
SPI0_NPCS0
PA4
Application Usage
Reset State
Power Supply
MCDB0
I/O
VDDIOP0
MCCDB
I/O
VDDIOP0
I/O
VDDIOP0
MCDB3
I/O
VDDIOP0
RTS2
MCDB2
I/O
VDDIOP0
PA5
CTS2
MCDB1
I/O
VDDIOP0
PA6
MCDA0
I/O
VDDIOP0
PA7
MCCDA
I/O
VDDIOP0
PA8
MCCK
I/O
VDDIOP0
PA9
MCDA1
I/O
VDDIOP0
PA10
MCDA2
ETX2
I/O
VDDIOP0
PA11
MCDA3
ETX3
I/O
VDDIOP0
PA12
ETX0
I/O
VDDIOP0
PA13
ETX1
I/O
VDDIOP0
PA14
ERX0
I/O
VDDIOP0
PA15
ERX1
I/O
VDDIOP0
PA16
ETXEN
I/O
VDDIOP0
PA17
ERXDV
I/O
VDDIOP0
PA18
ERXER
I/O
VDDIOP0
PA19
ETXCK
I/O
VDDIOP0
PA20
EMDC
I/O
VDDIOP0
PA21
EMDIO
I/O
VDDIOP0
PA22
ADTRG
ETXER
I/O
VDDIOP0
PA23
TWD0
ETX2
I/O
VDDIOP0
PA24
TWCK0
ETX3
I/O
VDDIOP0
PA25
TCLK0
ERX2
I/O
VDDIOP0
PA26
TIOA0
ERX3
I/O
VDDIOP0
PA27
TIOA1
ERXCK
I/O
VDDIOP0
PA28
TIOA2
ECRS
I/O
VDDIOP0
PA29
SCK1
ECOL
I/O
VDDIOP0
PA30(1)
SCK2
RXD4
I/O
VDDIOP0
PA31(1)
SCK0
TXD4
I/O
VDDIOP0
Note:
40
Comments
1. Not available in the 208-lead PQFP package.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Function
Comments
9.3.2
PIO Controller B Multiplexing
Table 9-3.
Multiplexing on PIO Controller B
PIO Controller B
Application Usage
I/O Line
Peripheral A
Peripheral B
PB0
SPI1_MISO
TIOA3
PB1
SPI1_MOSI
PB2
SPI1_SPCK
PB3
SPI1_NPCS0
TIOA5
PB4
TXD0
PB5
RXD0
I/O
VDDIOP0
PB6
TXD1
TCLK1
I/O
VDDIOP0
PB7
RXD1
TCLK2
I/O
VDDIOP0
PB8
TXD2
I/O
VDDIOP0
PB9
RXD2
I/O
VDDIOP0
PB10
TXD3
ISI_D8
I/O
VDDIOP1
PB11
Comments
Reset State
Power Supply
I/O
VDDIOP0
TIOB3
I/O
VDDIOP0
TIOA4
I/O
VDDIOP0
I/O
VDDIOP0
I/O
VDDIOP0
RXD3
ISI_D9
I/O
VDDIOP1
PB12
(1)
TWD1
ISI_D10
I/O
VDDIOP1
PB13
(1)
TWCK1
ISI_D11
I/O
VDDIOP1
PB14
DRXD
I/O
VDDIOP0
PB15
DTXD
I/O
VDDIOP0
PB16
TK
I/O
VDDIOP0
TCLK3
PB17
TF
TCLK4
I/O
VDDIOP0
PB18
TD
TIOB4
I/O
VDDIOP0
PB19
RD
TIOB5
I/O
VDDIOP0
PB20
RK
ISI_D0
I/O
VDDIOP1
PB21
RF
ISI_D1
I/O
VDDIOP1
PB22
DSR0
ISI_D2
I/O
VDDIOP1
PB23
DCD0
ISI_D3
I/O
VDDIOP1
PB24
DTR0
ISI_D4
I/O
VDDIOP1
PB25
RI0
ISI_D5
I/O
VDDIOP1
PB26
RTS0
ISI_D6
I/O
VDDIOP1
PB27
CTS0
ISI_D7
I/O
VDDIOP1
PB28
RTS1
ISI_PCK
I/O
VDDIOP1
PB29
CTS1
ISI_VSYNC
I/O
VDDIOP1
PB30
PCK0
ISI_HSYNC
I/O
VDDIOP1
PB31
PCK1
ISI_MCK
I/O
VDDIOP1
Note:
Function
Comments
1. Not available in the 208-lead PQFP package.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41
9.3.3
PIO Controller C Multiplexing
Table 9-4.
Multiplexing on PIO Controller C
PIO Controller C
I/O Line
Peripheral A
Application Usage
Peripheral B
Comments
Reset State
Power Supply
PC0
SCK3
AD0
I/O
VDDANA
PC1
PCK0
AD1
I/O
VDDANA
PC2(1)
PCK1
AD2
I/O
VDDANA
SPI1_NPCS3
AD3
I/O
VDDANA
(1)
PC3
PC4
A23
SPI1_NPCS2
A23
VDDIOM
PC5
A24
SPI1_NPCS1
A24
VDDIOM
PC6
TIOB2
CFCE1
I/O
VDDIOM
PC7
TIOB1
CFCE2
I/O
VDDIOM
PC8
NCS4/CFCS0
RTS3
I/O
VDDIOM
PC9
NCS5/CFCS1
TIOB0
I/O
VDDIOM
PC10
A25/CFRNW
CTS3
A25
VDDIOM
PC11
NCS2
SPI0_NPCS1
I/O
VDDIOM
IRQ0
NCS7
I/O
VDDIOM
(1)
PC12
PC13
FIQ
NCS6
I/O
VDDIOM
PC14
NCS3/NANDCS
IRQ2
I/O
VDDIOM
PC15
NWAIT
IRQ1
I/O
VDDIOM
PC16
D16
SPI0_NPCS2
I/O
VDDIOM
PC17
D17
SPI0_NPCS3
I/O
VDDIOM
PC18
D18
SPI1_NPCS1
I/O
VDDIOM
PC19
D19
SPI1_NPCS2
I/O
VDDIOM
PC20
D20
SPI1_NPCS3
I/O
VDDIOM
PC21
D21
EF100
I/O
VDDIOM
PC22
D22
TCLK5
I/O
VDDIOM
PC23
D23
I/O
VDDIOM
PC24
D24
I/O
VDDIOM
PC25
D25
I/O
VDDIOM
PC26
D26
I/O
VDDIOM
PC27
D27
I/O
VDDIOM
PC28
D28
I/O
VDDIOM
PC29
D29
I/O
VDDIOM
PC30
D30
I/O
VDDIOM
PC31
D31
I/O
VDDIOM
Note:
42
1. Not available in the 208-lead PQFP package.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Function
Comments
9.4
Embedded Peripherals
9.4.1
Serial Peripheral Interface
9.4.2
9.4.3
Supports communication with serial external devices
̶
Four chip selects with external decoder support allow communication with up to 15 peripherals
̶
Serial memories, such as DataFlash and 3-wire EEPROMs
̶
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
̶
External co-processors
Master or slave serial peripheral bus interface
̶
8- to 16-bit programmable data length per chip select
̶
Programmable phase and polarity per chip select
̶
Programmable transfer delays between consecutive transfers and between clock and data per chip
select
̶
Programmable delay between consecutive transfers
̶
Selectable mode fault detection
Very fast transfers supported
̶
Transfers with baud rates up to MCK
̶
The chip select line may be left active to speed up transfers on the same device
Two-wire Interface
Master, Multi-master and Slave modes supported
General call supported in Slave mode
Connection to PDC Channel
USART
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
̶
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
̶
Parity generation and error detection
̶
Framing error detection, overrun error detection
̶
MSB- or LSB-first
̶
Optional break generation and detection
̶
By 8 or by 16 oversampling receiver frequency
̶
Hardware handshaking RTS-CTS
̶
Receiver time-out and transmitter timeguard
̶
Optional Multi-drop Mode with address generation and detection
̶
Optional Manchester Encoding
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
̶
NACK handling, error counter with repetition and iteration limit
IrDA modulation and demodulation
̶
Communication at up to 115.2 kbps
Test Modes
̶
Remote Loopback, Local Loopback, Automatic Echo
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
43
9.4.4
9.4.5
Serial Synchronous Controller
Provides serial synchronous communication links used in audio and telecommunications applications (with
CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
Contains an independent receiver and transmitter and a common clock divider
Offers a configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of different event on the
frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
Timer Counter
Six 16-bit Timer Counter Channels
Wide range of functions including:
9.4.6
44
Frequency Measurement
̶
Event Counting
̶
Interval Measurement
̶
Pulse Generation
̶
Delay Timing
̶
Pulse Width Modulation
̶
Up/down Capabilities
Each channel is user-configurable and contains:
̶
Three external clock inputs
̶
Five internal clock inputs
̶
Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
Multimedia Card Interface
One double-channel Multimedia Card Interface
Compatibility with MultiMedia Card Specification Version 2.2
Compatibility with SD Memory Card Specification Version 1.0
Compatibility with SDIO Specification Version V1.0.
Cards clock rate up to Master Clock divided by 2
Embedded power management to slow down clock rate when not used
MCI has two slot, each supporting
9.4.7
̶
̶
One slot for one MultiMediaCard bus (up to 30 cards) or
̶
One SD Memory Card
Support for stream, block and multi-block data read and write
USB Host Port
Compliance with Open HCI Rev 1.0 Specification
Compliance with USB V2.0 Full-speed and Low-speed Specification
Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices
Root hub integrated with two downstream USB ports in the 217-LFBGA package
Two embedded USB transceivers
Supports power management
Operates as a master on the Matrix
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
9.4.8
USB Device Port
USB V2.0 full-speed compliant, 12 Mbits per second
Embedded USB V2.0 full-speed transceiver
Embedded 2,688-byte dual-port RAM for endpoints
Suspend/Resume logic
Ping-pong mode (two memory banks) for isochronous and bulk endpoints
Eight general-purpose endpoints
9.4.9
̶
Endpoint 0 and 3: 64 bytes, no ping-pong mode
̶
Endpoint 1, 2, 6, 7: 64 bytes, ping-pong mode
̶
Endpoint 4 and 5: 512 bytes, ping-pong mode
Embedded pad pull-up
Ethernet 10/100 MAC
Compatibility with IEEE Standard 802.3
10 and 100 Mbits per second data throughput capability
Full- and half-duplex operations
MII or RMII interface to the physical layer
Register Interface to address, data, status and control registers
DMA Interface, operating as a master on the Memory Controller
Interrupt generation to signal receive and transmit completion
128-byte transmit and 128-byte receive FIFOs
Automatic pad and CRC generation on transmitted frames
Address checking logic to recognize four 48-bit addresses
Supports promiscuous mode where all valid frames are copied to memory
Supports physical layer management through MDIO interface
9.4.10 Image Sensor Interface
ITU-R BT. 601/656 8-bit mode external interface support
Support for ITU-R BT.656-4 SAV and EAV synchronization
Vertical and horizontal resolutions up to 2048 x 2048
Preview Path up to 640*480
Support for packed data formatting for YCbCr 4:2:2 formats
Preview scaler to generate smaller size image
9.4.11 Analog-to-Digital Converter
4-channel ADC
10-bit 312K samples/sec. Successive Approximation Register ADC
-2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
Individual enable and disable of each channel
External voltage reference for better accuracy on low voltage inputs
Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs
TIOA0 to TIOA2 trigger
Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after
conversions of all enabled channels
Four analog inputs shared with digital signals
SAM9XE Series [DATASHEET]
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45
10.
ARM926EJ-S Processor
10.1
Overview
The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The
ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full
memory management, high performance, low die size and low power are all important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to
trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes
features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time
compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced
multiplier design for improved DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware
and software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
an ARM9EJ-S integer core
a Memory Management Unit (MMU)
separate instruction and data AMBA AHB bus interfaces
separate instruction and data TCM interfaces
Table 10-1.
46
Reference Document Table
Owner-Reference
Denomination
ARM Ltd. - DD10198B
ARM926EJS Technical Reference Manual
ARM Ltd. - DD10222B
ARM9EJ-S Technical Reference Manual
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
10.2
Block Diagram
Figure 10-1.
ARM926EJ-S Internal Functional Block Diagram
CP15 System
Configuration
Coprocessor
External Coprocessors
ETM9
External
Coprocessor
Interface
Trace Port
Interface
Write Data
ARM9EJ-S
Processor Core
Instruction
Fetches
Read
Data
Data
Address
Instruction
Address
MMU
DTCM
Interface
Data TLB
Instruction
TLB
ITCM
Interface
Data TCM
Instruction TCM
Instruction
Address
Data
Address
Data Cache
AHB Interface
and
Write Buffer
Instruction
Cache
AMBA AHB
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47
10.3
ARM9EJ-S Processor
10.3.1 ARM9EJ-S Operating States
The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:
ARM state: 32-bit, word-aligned ARM instructions.
Thumb state: 16-bit, halfword-aligned Thumb instructions.
Jazelle state: variable length, byte-aligned Jazelle instructions.
In Jazelle state, all instruction Fetches are in words.
10.3.2 Switching State
The operating state of the ARM9EJ-S core can be switched between:
ARM state and Thumb state using the BX and BLX instructions, and loads to the PC
ARM state and Jazelle state using the BXJ instruction
All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the
processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from
the exception handler.
10.3.3 Instruction Pipelines
The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor.
A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute,
Memory and Writeback stages.
A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock
cycles), Execute, Memory and Writeback stages.
10.3.4 Memory Access
The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to
four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte
boundary.
Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in
the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these
cases and stalls the core or forward data.
10.3.5 Jazelle Technology
The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing
high performance for the next generation of Java-powered wireless and embedded devices.
The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine).
Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte
codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and
turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down
into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible
to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and
all registers then have particular functions in this mode.
Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can
be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of
the interrupt handler. This means that no special provision has to be made for handling interrupts while executing
byte codes, whether in hardware or in software.
48
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10.3.6 ARM9EJ-S Operating Modes
In all states, there are seven operation modes:
User mode is the usual ARM program execution state. It is used for executing most application programs
Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or
channel process
Interrupt (IRQ) mode is used for general-purpose interrupt handling
Supervisor mode is a protected mode for the operating system
Abort mode is entered after a data or instruction prefetch abort
System mode is a privileged user mode for the operating system
Undefined mode is entered when an undefined instruction exception occurs
Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes,
are entered in order to service interrupts or exceptions or to access protected resources.
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49
10.3.7 ARM9EJ-S Registers
The ARM9EJ-S core has a total of 37 registers:
31 general-purpose 32-bit registers
Six 32-bit status registers
Table 10-2 shows all the registers in all modes.
Table 10-2.
ARM9TDMI Modes and Registers Layout
User and
System Mode
Supervisor
Mode
Abort Mode
Undefined Mode
Interrupt Mode
Fast Interrupt
Mode
R0
R0
R0
R0
R0
R0
R1
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R2
R3
R3
R3
R3
R3
R3
R4
R4
R4
R4
R4
R4
R5
R5
R5
R5
R5
R5
R6
R6
R6
R6
R6
R6
R7
R7
R7
R7
R7
R7
R8
R8
R8
R8
R8
R8_FIQ
R9
R9
R9
R9
R9
R9_FIQ
R10
R10
R10
R10
R10
R10_FIQ
R11
R11
R11
R11
R11
R11_FIQ
R12
R12
R12
R12
R12
R12_FIQ
R13
R13_SVC
R13_ABORT
R13_UNDEF
R13_IRQ
R13_FIQ
R14
R14_SVC
R14_ABORT
R14_UNDEF
R14_IRQ
R14_FIQ
PC
PC
PC
PC
PC
PC
CPSR
CPSR
CPSR
CPSR
CPSR
CPSR
SPSR_SVC
SPSR_ABORT
SPSR_UNDEF
SPSR_IRQ
SPSR_FIQ
Mode-specific banked registers
The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the
Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either
data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL
or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status
Register (CPSR) contains condition code flags and the current mode bits.
In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ
mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc,
r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when
interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines.
There is another register called Saved Program Status Register (SPSR) that becomes available in privileged
modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of
the exception that caused entry to the current (privileged) mode.
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In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS)
which defines:
constraints on the use of registers
stack conventions
argument passing and result return
For more details, refer to ARM Software Development Kit.
The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:
Eight general-purpose registers r0–r7
Stack pointer, SP
Link register, LR (ARM r14)
PC
CPSR
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S
Technical Reference Manual, revision r1p2 page 2-12).
10.3.7.1 Status Registers
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status
registers:
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operation mode
Figure 10-2.
Status Register Format
3130292827
24
N Z C V Q
J
7 6 5
Reserved
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
I F T
0
Mode
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Figure 10-2 shows the status register format, where:
N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD,
QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations.
The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR
instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.
The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:
̶
J = 0: The processor is in ARM or Thumb state, depending on the T bit
̶
J = 1: The processor is in Jazelle state.
Mode: five bits to encode the current processor mode
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10.3.7.2 Exceptions
10.3.7.3 Exception Types and Priorities
The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types
of exceptions are:
Fast interrupt (FIQ)
Normal interrupt (IRQ)
Data and Prefetched aborts (Abort)
Undefined instruction (Undefined)
Software interrupt and Reset (Supervisor)
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the
state.
More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to
the following priority order:
Reset (highest priority)
Data Abort
FIQ
IRQ
Prefetch Abort
BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority)
The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the
same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher
priority than FIQs to ensure that the transfer error does not escape detection.
10.3.7.4 Exception Modes and Handling
Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an
interrupt from a peripheral.
When handling an ARM exception, the ARM9EJ-S core performs the following operations:
1.
Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new
mode that has been entered. When the exception entry is from:
̶
̶
ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current
PC(r15) + 4 or PC + 8 depending on the exception).
Thumb state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2,
PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct
place on return.
2.
Copies the CPSR into the appropriate SPSR.
3.
Forces the CPSR mode bits to a value that depends on the exception.
4.
Forces the PC to fetch the next instruction from the relevant exception vector.
The register r13 is also banked across exception modes to provide each exception handler with private stack
pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in the banked LR
minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception.
This action restores both PC and the CPSR.
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The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the
requirement for register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When
a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the
exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for
example because a branch occurs while it is in the pipeline, the abort does not take place.
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the
Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction
reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs
while it is in the pipeline, the breakpoint does not take place.
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10.3.8 ARM Instruction Set Overview
The ARM instruction set is divided into:
Branch instructions
Data processing instructions
Status register transfer instructions
Load and Store instructions
Coprocessor instructions
Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual referenced in Table 10-1 on page 46.
Table 10-3 gives the ARM instruction mnemonic list.
Table 10-3.
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
RSB
Reverse Subtract
RSC
Reverse Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
TEQ
Test Equivalence
AND
Logical AND
BIC
Bit Clear
EOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
MUL
Multiply
MLA
Multiply Accumulate
SMULL
Sign Long Multiply
UMULL
Unsigned Long Multiply
SMLAL
Signed Long Multiply Accumulate
UMLAL
Unsigned Long Multiply Accumulate
MSR
B
BX
LDR
Move to Status Register
Branch
MRS
BL
Move From Status Register
Branch and Link
Branch and Exchange
SWI
Software Interrupt
Load Word
STR
Store Word
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDRH
Load Half Word
STRH
Store Half Word
LDRB
Load Byte
STRB
Store Byte
LDRBT
54
ARM Instruction Mnemonic List
Load Register Byte with Translation
STRBT
Store Register Byte with Translation
LDRT
Load Register with Translation
STRT
Store Register with Translation
LDM
Load Multiple
STM
Store Multiple
SWP
Swap Word
MCR
Move To Coprocessor
MRC
Move From Coprocessor
LDC
Load To Coprocessor
STC
Store From Coprocessor
CDP
Coprocessor Data Processing
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SWPB
Swap Byte
10.3.9 New ARM Instruction Set
Table 10-4.
Mnemonic
BXJ
New ARM Instruction Mnemonic List
Operation
Mnemonic
Operation
Branch and exchange to Java
MRRC
Move double from coprocessor
Branch, Link and exchange
MCR2
Alternative move of ARM reg to coprocessor
SMLAxy
Signed Multiply Accumulate 16 * 16 bit
MCRR
Move double to coprocessor
SMLAL
Signed Multiply Accumulate Long
CDP2
Alternative Coprocessor Data Processing
SMLAWy
Signed Multiply Accumulate 32 * 16 bit
BKPT
Breakpoint
SMULxy
Signed Multiply 16 * 16 bit
PLD
SMULWy
Signed Multiply 32 * 16 bit
STRD
Store Double
Saturated Add
STC2
Alternative Store from Coprocessor
Saturated Add with Double
LDRD
Load Double
Saturated subtract
LDC2
Alternative Load to Coprocessor
BLX
(1)
QADD
QDADD
QSUB
QDSUB
Note:
Saturated Subtract with double
CLZ
Soft Preload, Memory prepare to load from
address
Count Leading Zeroes
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
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10.3.10 Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Branch instructions
Data processing instructions
Load and Store instructions
Load and Store multiple instructions
Exception-generating instruction
For further details, see the ARM Technical Reference Manual referenced in Table 10-1 on page 46.
Table 10-5 gives the Thumb instruction mnemonic list.
Table 10-5.
Mnemonic
Operation
Mnemonic
Operation
MOV
Move
MVN
Move Not
ADD
Add
ADC
Add with Carry
SUB
Subtract
SBC
Subtract with Carry
CMP
Compare
CMN
Compare Negated
TST
Test
NEG
Negate
AND
Logical AND
BIC
Bit Clear
EOR
Logical Exclusive OR
ORR
Logical (inclusive) OR
LSL
Logical Shift Left
LSR
Logical Shift Right
ASR
Arithmetic Shift Right
ROR
Rotate Right
MUL
Multiply
BLX
Branch, Link, and Exchange
B
Branch
BL
BX
LDR
Branch and Link
Branch and Exchange
SWI
Software Interrupt
Load Word
STR
Store Word
LDRH
Load Half Word
STRH
Store Half Word
LDRB
Load Byte
STRB
Store Byte
LDRSH
Load Signed Halfword
LDRSB
Load Signed Byte
LDMIA
Load Multiple
STMIA
Store Multiple
PUSH
Push Register to stack
POP
Pop Register from stack
Conditional Branch
BKPT
Breakpoint
BCC
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10.4
CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list
below:
ARM9EJ-S
Caches (ICache, DCache and write buffer)
TCM
MMU
Other system options
To control these features, CP15 provides 16 additional registers. See Table 10-6.
Table 10-6.
CP15 Registers
Register
Read/Write
(1)
Read/Unpredictable
0
ID Code
0
Cache type(1)
Read/Unpredictable
0
(1)
TCM status
Read/Unpredictable
1
Control
Read/write
2
Translation Table Base
Read/write
3
Domain Access Control
Read/write
4
Reserved
None
5
Notes:
Name
Data fault Status
(1)
Read/write
(1)
5
Instruction fault status
Read/write
6
Fault Address
Read/write
7
Cache Operations
Read/Write
8
TLB operations
Unpredictable/Write
(2)
Read/write
9
cache lockdown
9
TCM region
Read/write
10
TLB lockdown
Read/write
11
Reserved
None
12
Reserved
None
13
FCSE PID(1)
Read/write
13
(1)
Context ID
Read/Write
14
Reserved
None
15
Test configuration
Read/Write
1.
2.
Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on
the value of the opcode_2 field.
Register location 9 provides access to more than one register. The register accessed depends on the value of the
CRm field.
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10.4.1 CP15 Registers Access
CP15 registers can only be accessed in privileged mode by:
MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.
MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM
register.
Other instructions like CDP, LDC, STC can cause an undefined instruction exception.
The assembler code for these instructions is:
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
The MCR, MRC instructions bit pattern is shown below:
31
30
29
28
cond
23
22
21
opcode_1
15
20
13
12
Rd
6
26
25
24
1
1
1
0
19
18
17
16
L
14
7
27
5
opcode_2
4
CRn
11
10
9
8
1
1
1
1
3
2
1
0
1
CRm
• CRm[3:0]: Specified Coprocessor Action
Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior.
• opcode_2[7:5]
Determines specific coprocessor operation code. By default, set to 0.
• Rd[15:12]: ARM Register
Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable.
• CRn[19:16]: Coprocessor Register
Determines the destination coprocessor register.
• L: Instruction Bit
0: MCR instruction
1: MRC instruction
• opcode_1[23:20]: Coprocessor Code
Defines the coprocessor specific code. Value is c15 for CP15.
• cond [31:28]: Condition
For more details, see Chapter 2 in ARM926EJ-S TRM.
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10.5
Memory Management Unit (MMU)
The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory
features required by operating systems like Symbian® OS, WindowsCE, and Linux. These virtual memory features
are memory access permission controls and virtual to physical address translations.
The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE
(Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual
addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry
in the set contains the access permissions and the physical address that correspond to the virtual address.
The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a
pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain,
etc.) or an entry in the second level translation tables; coarse table and fine table.
The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table
contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table
contains a pointer to large, small and tiny pages.
Table 10-7 shows the different attributes of each page in the physical memory.
Table 10-7.
Mapping Details
Mapping Name
Mapping Size
Access Permission By
Subpage Size
Section
1 Mbyte
Section
–
Large Page
64 Kbytes
4 separated subpages
16 Kbytes
Small Page
4 Kbytes
4 separated subpages
1 Kbyte
Tiny Page
1 Kbyte
Tiny Page
–
The MMU consists of:
Access control logic
Translation Look-aside Buffer (TLB)
Translation table walk hardware
10.5.1 Access Control Logic
The access control logic controls access information for every entry in the translation table. The access control
logic checks two pieces of access information: domain and access permissions. The domain is the primary access
control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to
proceed. The domain determines whether the access permissions are used to qualify the access or whether they
should be ignored.
The second access control mechanism is access permissions that are defined for sections and for large, small and
tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can
be associated with 4 sets of access permissions, one for each subpage (quarter of a page).
10.5.2 Translation Look-aside Buffer (TLB)
The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation
process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control
logic determines if the access is permitted and outputs the appropriate physical address corresponding to the
MVA. If access is not permitted, the MMU signals the CPU core to abort.
If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the
translation information from the translation table in physical memory.
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10.5.3 Translation Table Walk Hardware
The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets
the physical address and access permissions and updates the TLB.
The number of stages in the hardware table walking is one or two depending whether the address is marked as a
section-mapped access or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses
are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A
section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two
fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual.
10.5.4 MMU Faults
The MMU generates an abort on the following types of faults:
Alignment faults (for data accesses only)
Translation faults
Domain faults
Permission faults
The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result
of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and
address information about faults generated by the data accesses in the data fault status register and fault address
register. It also retains the status of faults generated by instruction fetches in the instruction fault status register.
The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain
number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA
associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3
in ARM926EJ-S Technical Reference Manual.
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10.6
Caches and Write Buffer
The ARM926EJ-S contains a 16-Kbyte Instruction Cache (ICache), a 8-Kbyte Data Cache (DCache), and a write
buffer. Although the ICache and DCache share common features, each still has some specific mechanisms.
The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the
Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The
ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement.
A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as
wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a
request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line
(eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining
words, no matter where the word is located in the line.
The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache
operations) and CP15 register 9 (cache lockdown).
10.6.1 Instruction Cache (ICache)
The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1
to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit.
When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is
disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flatmapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning
and/or invalidating.
When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in
page 4-4 in ARM926EJ-S TRM).
On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be
enabled as soon as possible after reset.
10.6.2 Data Cache (DCache) and Write Buffer
ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on
data access performance. The operations of DCache and write buffer are closely connected.
10.6.2.1 DCache
The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation
checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the
AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection
checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache
cleaning and/or invalidating every time a context switch occurs.
The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing
modified lines back to external memory. This means that the MMU is not involved in write-back operations.
Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second
four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or
a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory.
DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4
on page 4-5 in ARM926EJ-S TRM).
The DCache supports write-through and write-back cache operations, selected by memory region using the C and
B bits in the MMU translation tables.
The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data
for cache line eviction or cleaning of dirty cache lines.
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The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer
operations are closely connected as their configuration is set in each section by the page descriptor in the MMU
translation table.
10.6.2.2 Write Buffer
The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write
buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid
stalling the processor when writes to external memory are performed. When a store occurs, data is written to the
write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed
(typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks.
DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each
section and page descriptor within the MMU translation tables.
10.6.2.3 Write-though Operation
When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer
which transfers it to external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.
10.6.2.4 Write-back Operation
When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not upto-date with those in the external memory.
When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer
which transfers it to external memory.
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10.7
Bus Interface Unit
The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU
implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between
multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix
and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture.
The multi-master bus architecture has a number of benefits:
It allows the development of multi-master systems with an increased bus bandwidth and a flexible
architecture.
Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave
muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant,
nor do they have to support retry and split transactions.
The arbitration becomes effective when more than one master wants to access the same slave
simultaneously.
10.7.1 Supported Transfers
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight
words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that
the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests.
Table 10-8 gives an overview of the supported transfers and different kinds of transactions they are used for.
Table 10-8.
HBurst[2:0]
Supported Transfers
Description
Operation
Single transfer of word, half word, or byte:
Single
Single transfer
data write (NCNB, NCB, WT, or WB that has missed in DCache)
data read (NCNB or NCB)
NC instruction fetch (prefetched and non-prefetched)
page table walk read
Incr4
Four-word incrementing burst
Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,
NCB, WT, or WB write.
Incr8
Eight-word incrementing burst
Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
Wrap8
Eight-word wrapping burst
Cache linefill
10.7.2 Thumb Instruction Fetches
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the
ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
10.7.3 Address Alignment
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary
boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word
boundaries.
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11.
SAM9XE Debug and Test
11.1
Overview
The SAM9XE features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit
Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through
programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM.
It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the
Debug Communication Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test
environment.
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Block Diagram
Figure 11-1.
Debug and Test Block Diagram
TMS
TCK
TDI
NTRST
ICE/JTAG
TAP
Boundary
Port
JTAGSEL
TDO
RTCK
POR
Reset
and
Test
ARM9EJ-S
TST
ICE-RT
ARM926EJ-S
PDC
DBGU
PIO
11.2
DTXD
DRXD
TAP: Test Access Port
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11.3
Application Examples
11.3.1 Debug Environment
Figure 11-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard
debugging functions, such as downloading code and single-stepping through the program. A software debugger
running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the
ICE/JTAG interface.
Figure 11-2.
Application Debug and Trace Environment Example
Host Debugger PC
ICE/JTAG
Interface
ICE/JTAG
Connector
SAM9XE
RS232
Connector
SAM9XE-based Application Board
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Terminal
11.3.2 Test Environment
Figure 11-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this
example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
Figure 11-3.
Application Test Environment Example
Test Adaptor
Tester
JTAG
Interface
ICE/JTAG
Connector
Chip n
SAM9XE
Chip 2
Chip 1
SAM9XE-based Application Board In Test
11.4
Debug and Test Pin Description
Table 11-1.
Pin Name
Debug and Test Pin List
Function
Type
Active Level
Input/Output
Low
Input
High
Low
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
ICE and JTAG
NTRST
Test Reset Signal
Input
TCK
Test Clock
Input
TDI
Test Data In
Input
TDO
Test Data Out
TMS
Test Mode Select
RTCK
Returned Test Clock
JTAGSEL
JTAG Selection
Output
Input
Output
Input
Debug Unit
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
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11.5
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations.
All the JTAG signals are supplied with VDDIOP0.
68
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11.6
Functional Description
11.6.1 Test Pin
One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied
at low level to ensure normal operating conditions. Other values associated with this pin are reserved for
manufacturing test.
11.6.2 Embedded In-circuit Emulator
The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host
computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the
ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows
instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when
in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the
ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of
the Embedded ICE-RT. The scan chains are controlled by the ICE/JTAG port.
Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and
JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document:
ARM9EJ-S Technical Reference Manual (DDI 0222A).
11.6.3 Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace
purposes and offers an ideal means for in-situ programming solutions and debug monitor communication.
Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with
processor time reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the
ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to
the system through the ICE interface.
A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal
configuration.
The SAM9XE Debug Unit Chip ID value is 0x0198 03A0 on 32-bit width.
For further details on the Debug Unit, see Section 29. “Debug Unit (DBGU)”.
11.6.4 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS
functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that
identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after
JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
11.6.4.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associated control
signals.
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69
Each SAM9XE input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can
be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit
selects the direction of the pad.
Table 11-2.
SAM9XE JTAG Boundary Scan Register
Bit Number
Pin Name
Pin Type
A0
IN/OUT
A1
IN/OUT
A10
IN/OUT
A11
IN/OUT
A12
IN/OUT
A13
IN/OUT
A14
IN/OUT
A15
IN/OUT
A16
IN/OUT
A17
IN/OUT
A18
IN/OUT
A19
IN/OUT
A2
IN/OUT
A20
IN/OUT
A21
IN/OUT
A22
IN/OUT
A3
IN/OUT
A4
IN/OUT
307
306
305
304
303
302
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
285
284
283
282
281
280
279
278
277
276
275
274
273
272
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Associated BSR Cells
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
Table 11-2.
SAM9XE JTAG Boundary Scan Register (Continued)
Bit Number
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
Pin Name
Pin Type
A5
IN/OUT
A6
IN/OUT
A7
IN/OUT
A8
IN/OUT
A9
IN/OUT
BMS
INPUT
CAS
IN/OUT
D0
IN/OUT
D1
IN/OUT
D10
IN/OUT
D11
IN/OUT
D12
IN/OUT
D13
IN/OUT
D14
IN/OUT
D15
IN/OUT
D2
IN/OUT
D3
IN/OUT
D4
IN/OUT
D5
IN/OUT
D6
IN/OUT
Associated BSR Cells
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
INPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
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71
Table 11-2.
SAM9XE JTAG Boundary Scan Register (Continued)
Bit Number
Pin Name
Pin Type
D7
IN/OUT
D8
IN/OUT
D9
IN/OUT
NANDOE
IN/OUT
NANDWE
IN/OUT
NCS0
IN/OUT
NCS1
IN/OUT
NRD
IN/OUT
NRST
IN/OUT
NWR0
IN/OUT
NWR1
IN/OUT
NWR3
IN/OUT
OSCSEL
INPUT
PA0
IN/OUT
PA1
IN/OUT
PA10
IN/OUT
PA11
IN/OUT
PA12
IN/OUT
PA13
IN/OUT
PA14
IN/OUT
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
72
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Associated BSR Cells
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
INPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
Table 11-2.
SAM9XE JTAG Boundary Scan Register (Continued)
Bit Number
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
Pin Name
Pin Type
PA15
IN/OUT
PA16
IN/OUT
PA17
IN/OUT
PA18
IN/OUT
PA19
IN/OUT
PA2
IN/OUT
PA20
IN/OUT
PA21
IN/OUT
PA22
IN/OUT
PA23
IN/OUT
PA24
IN/OUT
PA25
IN/OUT
PA26
IN/OUT
PA27
IN/OUT
PA28
IN/OUT
PA29
IN/OUT
PA3
IN/OUT
159
internal
158
internal
157
internal
156
internal
155
154
PA4
IN/OUT
Associated BSR Cells
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
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73
Table 11-2.
SAM9XE JTAG Boundary Scan Register (Continued)
Bit Number
Pin Name
Pin Type
PA5
IN/OUT
PA6
IN/OUT
PA7
IN/OUT
PA8
IN/OUT
PA9
IN/OUT
PB0
IN/OUT
PB1
IN/OUT
PB10
IN/OUT
PB11
IN/OUT
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
internal
134
internal
133
internal
132
internal
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
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PB14
IN/OUT
PB15
IN/OUT
PB16
IN/OUT
PB17
IN/OUT
PB18
IN/OUT
PB19
IN/OUT
PB2
IN/OUT
PB20
IN/OUT
PB21
IN/OUT
Associated BSR Cells
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
Table 11-2.
SAM9XE JTAG Boundary Scan Register (Continued)
Bit Number
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
Pin Name
Pin Type
PB22
IN/OUT
PB23
IN/OUT
PB24
IN/OUT
PB25
IN/OUT
PB26
IN/OUT
PB27
IN/OUT
PB28
IN/OUT
PB29
IN/OUT
PB3
IN/OUT
PB30
IN/OUT
PB31
IN/OUT
PB4
IN/OUT
PB5
IN/OUT
PB6
IN/OUT
PB7
IN/OUT
PB8
IN/OUT
PB9
IN/OUT
PC0
IN/OUT
PC1
IN/OUT
PC10
IN/OUT
Associated BSR Cells
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
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75
Table 11-2.
SAM9XE JTAG Boundary Scan Register (Continued)
Bit Number
Pin Name
Pin Type
PC11
IN/OUT
73
72
71
internal
70
internal
69
68
67
66
65
64
63
62
61
60
59
58
57
56
IN/OUT
PC14
IN/OUT
PC15
IN/OUT
PC16
IN/OUT
PC17
IN/OUT
PC18
IN/OUT
PC19
IN/OUT
55
internal
54
internal
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
76
PC13
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
PC20
IN/OUT
PC21
IN/OUT
PC22
IN/OUT
PC23
IN/OUT
PC24
IN/OUT
PC25
IN/OUT
PC26
IN/OUT
PC27
IN/OUT
PC28
IN/OUT
PC29
IN/OUT
Associated BSR Cells
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
Table 11-2.
SAM9XE JTAG Boundary Scan Register (Continued)
Bit Number
Pin Name
Pin Type
33
internal
32
internal
31
Associated BSR Cells
CONTROL
PC30
IN/OUT
PC31
IN/OUT
PC4
IN/OUT
PC5
IN/OUT
PC6
IN/OUT
PC7
IN/OUT
PC8
IN/OUT
PC9
IN/OUT
RAS
IN/OUT
RTCK
OUT
SDA10
IN/OUT
SDCK
IN/OUT
SDCKE
IN/OUT
SDWE
IN/OUT
SHDN
OUT
01
TST
INPUT
INPUT
00
WKUP
INPUT
INPUT
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
INPUT/OUTPUT
CONTROL
OUTPUT
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77
11.6.5 JID Code Register
Access: Read-only
31
30
29
28
27
VERSION
23
22
26
25
24
PART NUMBER
21
20
19
18
17
16
10
9
8
PART NUMBER
15
14
13
12
11
PART NUMBER
7
6
MANUFACTURER IDENTITY
5
4
MANUFACTURER IDENTITY
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
Product part Number is 0x5B13
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
Bit[0] Required by IEEE Std. 1149.1.
Set to 0x1.
JTAG ID Code value is 0x05B1_303F.
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3
2
1
0
1
12.
SAM9XE Boot Program
12.1
Overview
The Boot Program integrates different programs permitting download and/or upload into the different memories of
the product.
First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port.
SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port.
12.2
Flow Diagram
The Boot Program implements the algorithm in Figure 12-1.
Figure 12-1.
Boot Program Algorithm Flow Diagram
Start
Internal RC Oscillator
Yes
Main Oscillator Bypass
No
No
Large
Crystal Table
Reduced
Crystal Table
Yes
Input Frequency
Table
No
USB Enumeration
Successful ?
Yes
Run SAM-BA Boot
No
Character(s) received
on DBGU ?
SAM-BA Boot
Yes
Run SAM-BA Boot
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79
12.3
Device Initialization
Initialization follows the steps described below:
1.
FIQ Initialization
2.
Stack setup for ARM supervisor mode
3.
External Clock Detection
4.
Switch Master Clock on Main Oscillator
5.
C variable initialization
6.
Main oscillator frequency detection if no external clock detected
7.
PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register
located in the Power Management Controller (PMC) determines the frequency of the main oscillator and
thus the correct factor for the PLLB.
a. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is active, Table 12-1 defines the
crystals supported by the Boot Program when using the internal RC oscillator.
Table 12-1.
Reduced Crystal Table (MHz) OSCSEL = 0
3.0
6.0
18.432
Other
Boot on DBGU
Yes
Yes
Yes
Yes
Boot on USB
Yes
Yes
Yes
No
Note:
Any other crystal can be used but it prevents using the USB.
b.
If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is bypassed, Table 12-2 defines
the frequencies supported by the Boot Program when bypassing main oscillator.
Table 12-2.
Input Frequencies Supported by Software Auto-detection (MHz) OSCSEL = 0
1.0
2.0
6.0
12.0
25.0
50.0
Other
Boot on DBGU
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Boot on USB
Yes
Yes
Yes
Yes
Yes
Yes
No
Note:
Any other input frequency can be used but it prevents using the USB.
c.
If an external 32768 Hz Oscillator is used (OSCSEL = 1) (OSCSEL = 1 and Bypass mode), Table 123 defines the crystals supported by the Boot Program.
Table 12-3.
Large Crystal Table (MHz) OSCSEL = 1
3.0
3.2768
3.6864
3.84
4.0
4.433619
4.9152
5.0
5.24288
6.0
6.144
6.4
6.5536
7.159090
7.3728
7.864320
8.0
9.8304
10.0
11.05920
12.0
12.288
13.56
14.31818
14.7456
16.0
16.367667
17.734470
18.432
20.0
Note:
Booting on USB or on DBGU is possible with any of these crystals.
8.
Initialization of the DBGU serial port (115200 bauds, 8, N, 1) only if OSCSEL = 1
9.
Enable the user reset
10. Jump to SAM-BA Boot sequence
11. Disable the Watchdog
12. Initialization of the USB Device Port
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Figure 12-2.
Clocks and DBGU Configurations
Start
No
Internal RC Oscillator?
(OSCSEL = 0)
Yes
Scan Large Crystal Table
Scan Reduced Crystal Table
MCK = PLLB/2
UDPCK = PLLB/2
MCK = Mosc
UDPCK = PLLB/2
"ROMBoot>" displayed on DBGU
DBGU not configured
No
End
No
(USB)
Autobaudrate ?
Yes (DBGU)
MCK = Mosc
UDPCK = PLLB/2
MCK = PLLB
UDPCK = xxxx
DBGU not configured
DBGU configured
End
End
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81
12.4
SAM-BA Boot
The SAM-BA boot principle is to:
̶
Wait for USB Device enumeration.
̶
In parallel, wait for character(s) received on the DBGU if MCK is configured to 48 MHz (OSCSEL = 1).
̶
Figure 12-3.
If not, the auto baud rate sequence is executed in parallel (see Figure 12-3).
Auto Baud Rate Flow Diagram
Device
Setup
Character '0x80'
received ?
No
1st measurement
Yes
Character '0x80'
received ?
No
2nd measurement
No
Test Communication
Yes
Character '#'
received ?
Yes
Send Character '>'
UART operational
Run SAM-BA Boot
Once the communication interface is identified, the application runs in an infinite loop waiting for different
commands as in Table 12-4 on page 83.
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Table 12-4.
Commands Available through the SAM-BA Boot
Command
Action
Argument(s)
Example
O
write a byte
Address, Value#
O200001,CA#
o
read a byte
Address,#
o200001,#
H
write a half word
Address, Value#
H200002,CAFE#
h
read a half word
Address,#
h200002,#
W
write a word
Address, Value#
W200000,CAFEDECA#
w
read a word
Address,#
w200000,#
S
send a file
Address,#
S200000,#
R
receive a file
Address, NbOfBytes#
R200000,1234#
G
go
Address#
G200200#
V
display version
No argument
V#
Write commands: Writes a byte (O), a halfword (H) or a word (W) to the target.
̶
Address: Address in hexadecimal.
̶
Value: Byte, halfword or word to write in hexadecimal.
̶
Output: ‘>’.
Read commands: Reads a byte (o), a halfword (h) or a word (w) from the target.
̶
Output: The byte, halfword or word read in hexadecimal following by ‘>’
̶
Address: Address in hexadecimal
̶
Output: ‘>’.
There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command
execution.
Receive a file (R): Receives data into a file from a specified address
̶
Address: Address in hexadecimal
̶
NbOfBytes: Number of bytes in hexadecimal to receive
̶
Address: Address in hexadecimal
Send a file (S): Sends a file to a specified address
Note:
̶
Output: ‘>’
Go (G): Jumps to a specified address and execute the code
̶
Address: Address to jump in hexadecimal
̶
Output: ‘>’
Get Version (V): Returns the SAM-BA boot version
̶
Output: ‘>’
12.4.1 DBGU Serial Port
Communication is performed through the DBGU serial port initialized to 115200 baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send the application file to the target. The size of the binary file to send depends on the
SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size
because the Xmodem protocol requires some SRAM memory to work.
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12.4.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to
guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each
block of the transfer looks like:
in which:
̶
= 01 hex
̶
= binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
̶
= 1’s complement of the blk#.
̶
= 2 bytes CRC16
Figure 12-4 shows a transmission using this protocol.
Figure 12-4.
Xmodem Transfer Example
Host
Device
C
SOH 01 FE Data[128] CRC CRC
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
12.4.3 USB Device Port
A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device
initialization procedure with PLLB configuration.
The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232
software to talk over the USB. The CDC class is implemented in all releases of Windows ® , beginning with
Windows 98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as
ISDN modems and virtual COM ports.
The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host
operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence
between vendor ID and product ID.
Atmel provides an INF example to see the device as a new serial port and also provides another custom driver
used by the SAM-BA application: atm6124.sys.
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12.4.3.1 Enumeration Process
The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the
device through the control endpoint. The device handles standard requests as defined in the USB Specification.
Table 12-5.
Handled Standard Requests
Request
Definition
GET_DESCRIPTOR
Returns the current device configuration value.
SET_ADDRESS
Sets the device address for all future device access.
SET_CONFIGURATION
Sets the device configuration.
GET_CONFIGURATION
Returns the current device configuration value.
GET_STATUS
Returns status for the specified recipient.
SET_FEATURE
Used to set or enable a specific feature.
CLEAR_FEATURE
Used to clear or disable a specific feature.
The device also handles some class requests defined in the CDC class.
Table 12-6.
Handled Class Requests
Request
Definition
SET_LINE_CODING
Configures DTE rate, stop bits, parity and number of character bits.
GET_LINE_CODING
Requests current DTE rate, stop bits, parity and number of character bits.
SET_CONTROL_LINE_STATE
RS-232 signal used to tell the DCE device the DTE device is now present.
Unhandled requests are STALLed.
12.4.3.2 Communication Endpoints
There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the
host through the endpoint 1. If required, the message is split by the host into several data payloads by the host
driver.
If the command requires a response, the host can send IN transactions to pick up the response.
12.4.4 In-Application Programming (IAP) Feature
The IAP feature is a function located in ROM that can be called by any software application.
When called, this function sends the desired FLASH command to the EEFC and waits for the FLASH to be ready
(looping while the FRDY bit is not set in the MC_FSR).
Since this function is executed from ROM, this allows FLASH programming (like sector write) to be done by code
running in FLASH.
The IAP function entry point is retrieved by reading the SWI vector in ROM (0x100008).
This function takes one argument in parameter: the command to be sent to the EEFC.
This function returns the value of the MC_FSR.
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IAP software code example:
(unsigned int) (*IAP_Function)(unsigned long);
void main (void)
{
unsigned long FlashSectorNum = 200;
unsigned long flash_cmd = 0;
unsigned long flash_status = 0;
/* Initialize the function pointer (retrieve function address from SWI vector)
*/
IAP_Function = ((unsigned long) (*)(unsigned long))
0x100008;
/* Send your data to the sector */
/* build the command to send to EFC */
flash_cmd =
(0x5A 32
kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher
frequency on XIN speeds up the programmer handshake.
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Table 13-18.
Reset TAP Controller and Go to Select-DR-Scan
TDI
TMS
TAP Controller State
X
1
X
1
X
1
X
1
X
1
Test-Logic Reset
X
0
Run-Test/Idle
Xt
1
Select-DR-Scan
13.3.3 Read/Write Handshake
The read/write handshake is done by carrying out read/write operations on two registers of the device that are
accessible through the JTAG:
Debug Comms Control Register: DCCR
Debug Comms Data Register: DCDR
Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address
field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register
to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field
and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data.
Refer to the ARM7TDMI reference manuel for more information on Comm channel operations.
Figure 13-5.
TAP 8-bit DR Register
TDI
r/w
4
Address
0
31
5
Address
Decoder
0
Data
TDO
32
Debug Comms Control Register
Debug Comms Data Register
A read or write takes place when the TAP controller enters UPDATE-DR state. Refer to the IEEE 1149.1 for more
details on JTAG operations.
The address of the Debug Comms Control Register is 0x04.
The address of the Debug Comms Data Register is 0x05.
The Debug Comms Control Register is read-only and allows synchronized handshaking between the
processor and the debugger.
̶
Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data
Register. If the device is busy W = 0, then the programmer must poll until W = 1.
̶
Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register. If R
= 1, data previously placed there through the scan chain has not been collected by the device and so
the programmer must wait.
The write handshake is done by polling the Debug Comms Control Register until the R bit is cleared. Once
cleared, data can be written to the Debug Comms Data Register.
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The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data
can be read in the Debug Comms Data Register.
13.3.4 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 13-3 on page
89. Commands are run by the programmer through the serial interface that is reading and writing the Debug
Comms Registers.
13.3.4.1 Flash Read Command
This command is used to read the Flash contents. The memory map is accessible through this command. Memory
is seen as an array of words (32-bit wide). The read command can start at any valid address in the memory plane.
This address must be word-aligned. The address is automatically incremented.
Table 13-19.
Read Command
Read/Write
DR Data
Write
(Number of Words to Read) 15
16
17
18
19
...
124
125
126
127
Dec Factor
X
1
1.063
1.125
1.188
...
7.750
7.813
7.875
7.938
Table 40-7.
Decimation and Scaler Offset Values
INPUT
352*288
640*480
800*600
1280*1024
1600*1200
2048*1536
F
NA
16
20
32
40
51
F
16
32
40
64
80
102
F
16
26
33
56
66
85
F
16
53
66
113
133
170
OUTPUT
VGA
640*480
QVGA
320*240
CIF
352*288
QCIF
176*144
Example:
Input 1280*1024 Output = 640*480
Hratio = 1280/640 = 2
Vratio = 1024/480 = 2.1333
The decimation factor is 2 so 32/16.
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Figure 40-5.
Resize Examples
1280
32/16 decimation
640
1024
480
1280
56/16 decimation
352
1024
288
40.3.4.2 Color Space Conversion
This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples
value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable:
C0 0 C1
Y – Y off
R
G = C 0 – C 2 – C 3 × C b – C boff
B
C0 C4 0
C r – C roff
Example of programmable value to convert YCrCb to RGB:
R = 1.164 ⋅ ( Y – 16 ) + 1.596 ⋅ ( C r – 128 )
G = 1.164 ⋅ ( Y – 16 ) – 0.813 ⋅ ( C r – 128 ) – 0.392 ⋅ ( C b – 128 )
B = 1.164 ⋅ ( Y – 16 ) + 2.107 ⋅ ( C b – 128 )
An example of programmable value to convert from YUV to RGB:
R = Y + 1.596 ⋅ V
G = Y – 0.394 ⋅ U – 0.436 ⋅ V
B = Y + 2.032 ⋅ U
40.3.4.3 Memory Interface
Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:5:5 format compliant with 16-bit
format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer
bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards
the three LSBs from the red and blue channels, and two LSBs from the green channel. When grayscale mode is
enabled, two memory format are supported. One mode supports 2 pixels per word, and the other mode supports 1
pixel per word.
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Table 40-8.
Grayscale Memory Mapping Configuration for 12-bit Data
GS_MODE
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
0
P_0[11:4]
P_0[3:0], 0000
P_1[11:4]
P_1[3:0], 0000
1
P_0[11:4]
P_0[3:0], 0000
0
0
40.3.4.4 FIFO and DMA Features
Both preview and codec datapaths contain FIFOs, asynchronous buffers that are used to safely transfer formatted
pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and
triggers a relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified
length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list
operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or
more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each
FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation
at another frame buffer address. The FBD is defined by a series of two words. The first one defines the current
frame buffer address, and the second defines the next FBD memory location. This DMA transfer mode is only
available for preview datapath and is configured in the ISI_PPFBD register that indicates the memory location of
the first FBD.
The primary FBD is programmed into the camera interface controller. The data to be transferred described by an
FBD requires several burst access. In the example below, the use of two ping-pong frame buffers is described.
40.3.4.5 Example
The first FBD, stored at address 0x30000, defines the location of the first frame buffer.
Destination Address: frame buffer ID0 0x02A000
Next FBD address: 0x30010
Second FBD, stored at address 0x30010, defines the location of the second frame buffer.
Destination Address: frame buffer ID1 0x3A000
Transfer width: 32 bit
Next FBD address: 0x30000, wrapping to first FBD.
Using this technique, several frame buffers can be configured through the linked list. Figure 40-6 illustrates a
typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1,
frame n+2 is mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2
encoded frame is stored in a dedicated memory space.
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Figure 40-6.
Three Frame Buffers Application and Memory Mapping
Codec Done
Codec Request
frame n-1
frame n
frame n+1
frame n+2
frame n+3
frame n+4
Memory Space
Frame Buffer 3
Frame Buffer 0
LCD
Frame Buffer 1
ISI config Space
4:2:2 Image
Full ROI
40.3.5 Codec Path
40.3.5.1 Color Space Conversion
Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the
format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space
with the formulas given below:
Y
Cr =
C0 C1 C2
Cb
–C6 –C7 C8
C3 –C4 –C5
Y off
R
× G + Cr off
B
Cb off
An example of coefficients are given below:
Y = 0.257 ⋅ R + 0.504 ⋅ G + 0.098 ⋅ B + 16
C = 0.439 ⋅ R – 0.368 ⋅ G – 0.071 ⋅ B + 128
r
C b = – 0.148 ⋅ R – 0.291 ⋅ G + 0.439 ⋅ B + 128
40.3.5.2 Memory Interface
Dedicated FIFO are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit
word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not
supported.
40.3.5.3 DMA Features
Unlike preview datapath, codec datapath DMA mode does not support linked list operation. Only the
CODEC_DMA_ADDR is used to configure the frame buffer base address.
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40.4
Image Sensor Interface (ISI) User Interface
Table 40-9.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
ISI Control 1 Register
ISI_CR1
Read/Write
0x00000002
0x04
ISI Control 2 Register
ISI_CR2
Read/Write
0x00000000
0x08
ISI Status Register
ISI_SR
Read-only
0x00000000
0x0C
ISI Interrupt Enable Register
ISI_IER
Write-only
–
0x10
ISI Interrupt Disable Register
ISI_IDR
Write-only
–
0x14
ISI Interrupt Mask Register
ISI_IMR
Read-only
0x00000000
0x18
Reserved
–
–
–
0x1C
Reserved
–
–
–
0x20
ISI Preview Size Register
ISI_PSIZE
Read/Write
0x00000000
0x24
ISI Preview Decimation Factor Register
ISI_PDECF
Read/Write
0x00000010
0x28
ISI Preview Primary FBD Register
ISI_PPFBD
Read/Write
0x00000000
0x2C
ISI Codec DMA Base Address Register
ISI_CDBA
Read/Write
0x00000000
0x30
ISI CSC YCrCb To RGB Set 0 Register
ISI_Y2R_SET0
Read/Write
0x6832cc95
0x34
ISI CSC YCrCb To RGB Set 1 Register
ISI_Y2R_SET1
Read/Write
0x00007102
0x38
ISI CSC RGB To YCrCb Set 0 Register
ISI_R2Y_SET0
Read/Write
0x01324145
0x3C
ISI CSC RGB To YCrCb Set 1 Register
ISI_R2Y_SET1
Read/Write
0x01245e38
0x40
ISI CSC RGB To YCrCb Set 2 Register
ISI_R2Y_SET2
Read/Write
0x01384a4b
0x44–0xF8
Reserved
–
–
–
0xFC
Reserved
–
–
–
Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program
the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller.
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40.4.1 ISI Control 1 Register
Name:
ISI_CR1
Address:
0xFFFC0000
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
SFD
23
22
21
20
SLD
15
CODEC_ON
14
7
CRC_SYNC
6
EMB_SYNC
13
12
FULL
11
–
10
9
FRATE
8
5
–
4
PIXCLK_POL
3
VSYNC_POL
2
HSYNC_POL
1
ISI_DIS
0
ISI_RST
THMASK
• ISI_RST: Image sensor interface reset
Write-only. Refer to bit SOFTRST in Section 40.4.3 “ISI Status Register” on page 788 for soft reset status.
0: No action
1: Resets the image sensor interface.
• ISI_DIS: Image sensor disable:
0: Enable the image sensor interface.
1: Finish capturing the current frame and then shut down the module.
• HSYNC_POL: Horizontal synchronization polarity
0: HSYNC active high
1: HSYNC active low
• VSYNC_POL: Vertical synchronization polarity
0: VSYNC active high
1: VSYNC active low
• PIXCLK_POL: Pixel clock polarity
0: Data is sampled on rising edge of pixel clock
1: Data is sampled on falling edge of pixel clock
• EMB_SYNC: Embedded synchronization
0: Synchronization by HSYNC, VSYNC
1: Synchronization by embedded synchronization sequence SAV/EAV
• CRC_SYNC: Embedded synchronization
0: No CRC correction is performed on embedded synchronization
1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in
the status register.
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• FRATE: Frame rate [0..7]
0: All the frames are captured, else one frame every FRATE+1 is captured.
• FULL: Full mode is allowed
1: Both codec and preview datapaths are working simultaneously
• THMASK: Threshold mask
0: 4, 8 and 16 AHB bursts are allowed
1: 8 and 16 AHB bursts are allowed
2: Only 16 AHB bursts are allowed
• CODEC_ON: Enable the codec path enable bit
Write-only.
0: The codec path is disabled
1: The codec path is enabled and the next frame is captured. Refer to bit CDC_PND in “ISI Status Register” on page 788.
• SLD: Start of Line Delay
SLD pixel clock periods to wait before the beginning of a line.
• SFD: Start of Frame Delay
SFD lines are skipped at the beginning of the frame.
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40.4.2 ISI Control 2 Register
Name:
ISI_CR2
Address:
0xFFFC0004
Access:
Read/Write
31
30
29
RGB_CFG
23
28
27
–
26
25
IM_HSIZE
24
20
19
18
17
16
YCC_SWAP
22
21
IM_HSIZE
15
COL_SPACE
14
RGB_SWAP
13
GRAYSCALE
12
RGB_MODE
11
GS_MODE
10
9
IM_VSIZE
8
7
6
5
4
3
2
1
0
IM_VSIZE
• IM_VSIZE: Vertical size of the Image sensor [0..2047]
Vertical size = IM_VSIZE + 1
• GS_MODE
0: 2 pixels per word
1: 1 pixel per word
• RGB_MODE: RGB input mode
0: RGB 8:8:8 24 bits
1: RGB 5:6:5 16 bits
• GRAYSCALE
0: Grayscale mode is disabled
1: Input image is assumed to be grayscale coded
• RGB_SWAP
0: D7 -> R7
1: D0 -> R7
The RGB_SWAP has no effect when the grayscale mode is enabled.
• COL_SPACE: Color space for the image data
0: YCbCr
1: RGB
• IM_HSIZE: Horizontal size of the Image sensor [0..2047]
Horizontal size = IM_HSIZE + 1
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• YCC_SWAP: Defines the YCC image data
YCC_SWAP
Byte 0
Byte 1
Byte 2
Byte 3
00: Default
Cb(i)
Y(i)
Cr(i)
Y(i+1)
01: Mode1
Cr(i)
Y(i)
Cb(i)
Y(i+1)
10: Mode2
Y(i)
Cb(i)
Y(i+1)
Cr(i)
11: Mode3
Y(i)
Cr(i)
Y(i+1)
Cb(i)
• RGB_CFG: Defines RGB pattern when RGB_MODE is set to 1
RGB_CFG
Byte 0
Byte 1
Byte 2
Byte 3
00: Default
R/G(MSB)
G(LSB)/B
R/G(MSB)
G(LSB)/B
01: Mode1
B/G(MSB)
G(LSB)/R
B/G(MSB)
G(LSB)/R
10: Mode2
G(LSB)/R
B/G(MSB)
G(LSB)/R
B/G(MSB)
11: Mode3
G(LSB)/B
R/G(MSB)
G(LSB)/B
R/G(MSB)
If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence.
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40.4.3 ISI Status Register
Name:
ISI_SR
Address:
0xFFFC0008
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
FR_OVR
8
FO_C_EMP
7
FO_P_EMP
6
FO_P_OVF
5
FO_C_OVF
4
CRC_ERR
3
CDC_PND
2
SOFTRST
1
DIS
0
SOF
• SOF: Start of frame
0: No start of frame has been detected.
1: A start of frame has been detected.
• DIS: Image Sensor Interface disable
0: The image sensor interface is enabled.
1: The image sensor interface is disabled and stops capturing data. The DMA controller and the core can still read the
FIFOs.
• SOFTRST: Software reset
0: Software reset not asserted or not completed.
1: Software reset has completed successfully.
• CDC_PND: Codec request pending
0: No request asserted.
1: A codec request is pending. If a codec request is asserted during a frame, the CDC_PND bit rises until the start of a new
frame. The capture is completed when the flag FO_C_EMP = 1.
• CRC_ERR: CRC synchronization error
0: No crc error in the embedded synchronization frame (SAV/EAV)
1: The CRC_SYNC is enabled in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one.
• FO_C_OVF: FIFO codec overflow
0: No overflow
1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an
attempt is made to write a new sample to the FIFO.
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• FO_P_OVF: FIFO preview overflow
0: No overflow
1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an
attempt is made to write a new sample to the FIFO.
• FO_P_EMP
0:The DMA has not finished transferring all the contents of the preview FIFO.
1:The DMA has finished transferring all the contents of the preview FIFO.
• FO_C_EMP
0: The DMA has not finished transferring all the contents of the codec FIFO.
1: The DMA has finished transferring all the contents of the codec FIFO.
• FR_OVR: Frame rate overrun
0: No frame overrun.
1: Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs.
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40.4.4 ISI Interrupt Enable Register
Name:
ISI_IER
Address:
0xFFFC000C
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
FR_OVR
8
FO_C_EMP
7
FO_P_EMP
6
FO_P_OVF
5
FO_C_OVF
4
CRC_ERR
3
–
2
SOFTRST
1
DIS
0
SOF
• SOF: Start of Frame
1: Enables the Start of Frame interrupt.
• DIS: Image Sensor Interface disable
1: Enables the DIS interrupt.
• SOFTRST: Soft Reset
1: Enables the Soft Reset Completion interrupt.
• CRC_ERR: CRC synchronization error
1: Enables the CRC_SYNC interrupt.
• FO_C_OVF: FIFO codec Overflow
1: Enables the codec FIFO overflow interrupt.
• FO_P_OVF: FIFO preview Overflow
1: Enables the preview FIFO overflow interrupt.
• FO_P_EMP
1: Enables the preview FIFO empty interrupt.
• FO_C_EMP
1: Enables the codec FIFO empty interrupt.
• FR_OVR: Frame overrun
1: Enables the Frame overrun interrupt.
790
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
40.4.5 ISI Interrupt Disable Register
Name:
ISI_IDR
Address:
0xFFFC0010
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
FR_OVR
8
FO_C_EMP
7
FO_P_EMP
6
FO_P_OVF
5
FO_C_OVF
4
CRC_ERR
3
–
2
SOFTRST
1
DIS
0
SOF
• SOF: Start of Frame
1: Disables the Start of Frame interrupt.
• DIS: Image Sensor Interface disable
1: Disables the DIS interrupt.
• SOFTRST
1: Disables the soft reset completion interrupt.
• CRC_ERR: CRC synchronization error
1: Disables the CRC_SYNC interrupt.
• FO_C_OVF: FIFO codec overflow
1: Disables the codec FIFO overflow interrupt.
• FO_P_OVF: FIFO preview overflow
1: Disables the preview FIFO overflow interrupt.
• FO_P_EMP
1: Disables the preview FIFO empty interrupt.
• FO_C_EMP
1: Disables the codec FIFO empty interrupt.
• FR_OVR
1: Disables frame overrun interrupt.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
791
40.4.6 ISI Interrupt Mask Register
Name:
ISI_IMR
Address:
0xFFFC0014
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
FR_OVR
8
FO_C_EMP
7
FO_P_EMP
6
FO_P_OVF
5
FO_C_OVF
4
CRC_ERR
3
–
2
SOFTRST
1
DIS
0
SOF
• SOF: Start of Frame
0: The Start of Frame interrupt is disabled.
1: The Start of Frame interrupt is enabled.
• DIS: Image sensor interface disable
0: The DIS interrupt is disabled.
1: The DIS interrupt is enabled.
• SOFTRST
0: The soft reset completion interrupt is enabled.
1: The soft reset completion interrupt is disabled.
• CRC_ERR: CRC synchronization error
0: The CRC_SYNC interrupt is disabled.
1: The CRC_SYNC interrupt is enabled.
• FO_C_OVF: FIFO codec overflow
0: The codec FIFO overflow interrupt is disabled.
1: The codec FIFO overflow interrupt is enabled.
• FO_P_OVF: FIFO preview overflow
0: The preview FIFO overflow interrupt is disabled.
1: The preview FIFO overflow interrupt is enabled.
• FO_P_EMP
0: The preview FIFO empty interrupt is disabled.
1: The preview FIFO empty interrupt is enabled.
792
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
• FO_C_EMP
0: The codec FIFO empty interrupt is disabled.
1: The codec FIFO empty interrupt is enabled.
• FR_OVR: Frame Rate Overrun
0: The frame overrun interrupt is disabled.
1: The frame overrun interrupt is enabled.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
793
40.4.7 ISI Preview Register
Name:
ISI_PSIZE
Address:
0xFFFC0020
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
23
22
21
20
19
18
17
11
–
10
–
9
3
2
1
24
PREV_HSIZE
16
PREV_HSIZE
15
–
14
–
13
–
12
–
7
6
5
4
PREV_VSIZE
• PREV_VSIZE: Vertical size for the preview path
Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode).
• PREV_HSIZE: Horizontal size for the preview path
Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode).
794
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
8
PREV_VSIZE
0
40.4.8 ISI Preview Decimation Factor Register
Name:
ISI_PDECF
Address:
0xFFFC0024
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
DEC_FACTOR
• DEC_FACTOR: Decimation factor
DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
795
40.4.9 ISI Preview Primary FBD Register
Name:
ISI_PPFBD
Address:
0xFFFC0028
Access:
Read/Write
31
30
29
28
27
PREV_FBD_ADDR
26
25
24
23
22
21
20
19
PREV_FBD_ADDR
18
17
16
15
14
13
12
11
PREV_FBD_ADDR
10
9
8
7
6
5
4
3
PREV_FBD_ADDR
2
1
0
• PREV_FBD_ADDR: Base address for preview frame buffer descriptor
Written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used.
The frame buffer is forced to word alignment.
796
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
40.4.10 ISI Codec DMA Base Address Register
Name:
ISI_CDBA
Address:
0xFFFC002C
Access:
Read/Write
31
30
29
28
27
CODEC_DMA_ADDR
26
25
24
23
22
21
20
19
CODEC_DMA_ADDR
18
17
16
15
14
13
12
11
CODEC_DMA_ADDR
10
9
8
7
6
5
4
3
CODEC_DMA_ADDR
2
1
0
• CODEC_DMA_ADDR: Base address for codec DMA
This register contains codec datapath start address of buffer location.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
797
40.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register
Name:
ISI_Y2R_SET0
Address:
0xFFFC0030
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
C3
23
22
21
20
C2
15
14
13
12
C1
7
6
5
4
C0
• C0: Color Space Conversion Matrix Coefficient C0
C0 element, default step is 1/128, ranges from 0 to 1.9921875
• C1: Color Space Conversion Matrix Coefficient C1
C1 element, default step is 1/128, ranges from 0 to 1.9921875
• C2: Color Space Conversion Matrix Coefficient C2
C2 element, default step is 1/128, ranges from 0 to 1.9921875
• C3: Color Space Conversion Matrix Coefficient C3
C3 element default step is 1/128, ranges from 0 to 1.9921875
798
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
40.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register
Name:
ISI_Y2R_SET1
Address:
0xFFFC0034
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
Cboff
13
Croff
12
Yoff
11
–
10
–
9
–
8
C4
C4
• C4: Color Space Conversion Matrix coefficient C4
C4 element default step is 1/128, ranges from 0 to 3.9921875
• Yoff: Color Space Conversion Luminance default offset
0: No offset
1: Offset = 128
• Croff: Color Space Conversion Red Chrominance default offset
0: No offset
1: Offset = 16
• Cboff: Color Space Conversion Blue Chrominance default offset
0: No offset
1: Offset = 16
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
799
40.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register
Name:
ISI_R2Y_SET0
Address:
0xFFFC0038
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
Roff
23
22
21
20
19
18
17
16
11
10
9
8
3
2
1
0
C2
15
14
13
12
C1
7
6
5
4
C0
• C0: Color Space Conversion Matrix coefficient C0
C0 element default step is 1/256, from 0 to 0.49609375
• C1: Color Space Conversion Matrix coefficient C1
C1 element default step is 1/128, from 0 to 0.9921875
• C2: Color Space Conversion Matrix coefficient C2
C2 element default step is 1/512, from 0 to 0.2480468875
• Roff: Color Space Conversion Red component offset
0: No offset
1: Offset = 16
800
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
40.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register
Name:
ISI_R2Y_SET1
Address:
0xFFFC003C
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
Goff
23
22
21
20
19
18
17
16
11
10
9
8
3
2
1
0
C5
15
14
13
12
C4
7
6
5
4
C3
• C3: Color Space Conversion Matrix coefficient C3
C0 element default step is 1/128, ranges from 0 to 0.9921875
• C4: Color Space Conversion Matrix coefficient C4
C1 element default step is 1/256, ranges from 0 to 0.49609375
• C5: Color Space Conversion Matrix coefficient C5
C1 element default step is 1/512, ranges from 0 to 0.2480468875
• Goff: Color Space Conversion Green component offset
0: No offset
1: Offset = 128
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
801
40.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register
Name:
ISI_R2Y_SET2
Address:
0xFFFC0040
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
Boff
23
22
21
20
19
18
17
16
11
10
9
8
3
2
1
0
C8
15
14
13
12
C7
7
6
5
4
C6
• C6: Color Space Conversion Matrix coefficient C6
C6 element default step is 1/512, ranges from 0 to 0.2480468875
• C7: Color Space Conversion Matrix coefficient C7
C7 element default step is 1/256, ranges from 0 to 0.49609375
• C8: Color Space Conversion Matrix coefficient C8
C8 element default step is 1/128, ranges from 0 to 0.9921875
• Boff: Color Space Conversion Blue component offset
0: No offset
1: Offset = 128
802
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.
Analog-to-Digital Converter (ADC)
41.1
Description
The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It
also integrates an 4-to-1 analog multiplexer, making possible the analog-to-digital conversions of 4 analog lines.
The conversions extend from 0V to ADVREF.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for
all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the
ADTRG pin or internal triggers from Timer Counter output(s) are configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These
features reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time.
41.2
Block Diagram
Figure 41-1.
Analog-to-Digital Converter Block Diagram
Timer
Counter
Channels
PMC
MCK
ADC Controller
Trigger
Selection
ADTRG
Control
Logic
ADC Interrupt
AIC
ADC cell
VDDANA
ADVREF
ASB
AD-
Dedicated
Analog
Inputs
PDC
ADUser
Interface
AD-
AD-
Analog Inputs
Multiplexed
with I/O lines
PIO
Peripheral Bridge
Successive
Approximation
Register
Analog-to-Digital
Converter
APB
AD-
AD-
GND
41.3
Signal Description
Table 41-1.
ADC Pin Description
Pin Name
Description
VDDANA
Analog power supply
ADVREF
Reference voltage
AD0–AD3
Analog input channels
ADTRG
External trigger
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
803
41.4
Product Dependencies
41.4.1 Power Management
The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is
automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode,
the Power Management Controller has no effect on the ADC behavior.
41.4.2 Interrupt Sources
The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the
ADC interrupt requires the AIC to be programmed first.
41.4.3 Analog Inputs
The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is
automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By
default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to
the GND.
41.4.4 I/O Lines
The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO
Controller should be set accordingly to assign the pin ADTRG to the ADC function.
41.4.5 Timer Triggers
Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all
of the timer counters may be non-connected.
41.4.6 Conversion Performances
For performance and electrical characteristics of the ADC, see the DC Characteristics section.
804
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.5
Functional Description
41.5.1 Analog-to-Digital Conversion
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data
requires Sample and Hold Clock cycles as defined in the field SHTIM of the “ADC Mode Register” on page 811
and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register
(ADC_MR).
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F).
PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in
the Product definition section.
41.5.2 Conversion Reference
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs
between these voltages convert to values based on a linear conversion.
41.5.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the
ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the
data registers is fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the
conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the
DATA field in the corresponding ADC_CDR and of the LDATA field in the ADC_LCDR read 0.
Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit.
Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are
optimized.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
805
41.5.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register
(ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR).
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC
channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY
bit and the EOC bit corresponding to the last converted channel.
Figure 41-2.
EOCx and DRDY Flag Behavior
Write the ADC_CR
with START = 1
Read the ADC_CDRx
Write the ADC_CR
with START = 1
CHx
(ADC_CHSR)
EOCx
(ADC_SR)
Conversion Time
DRDY
(ADC_SR)
806
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Conversion Time
Read the ADC_LCDR
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE)
flag is set in the Status Register (ADC_SR).
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in
ADC_SR.
The OVRE and GOVRE flags are automatically cleared when ADC_SR is read.
Figure 41-3.
GOVRE and OVREx Flag Behavior
Read ADC_SR
ADTRG
CH0
(ADC_CHSR)
CH1
(ADC_CHSR)
ADC_LCDR
Undefined Data
ADC_CDR0
Undefined Data
ADC_CDR1
EOC0
(ADC_SR)
EOC1
(ADC_SR)
Data B
Data A
Data C
Data A
Data C
Undefined Data
Data B
Conversion
Conversion
Conversion
Read ADC_CDR0
Read ADC_CDR1
GOVRE
(ADC_SR)
DRDY
(ADC_SR)
OVRE0
(ADC_SR)
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled
during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are
unpredictable.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
807
41.5.5 Conversion Triggers
Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger
is provided by writing the Control Register (ADC_CR) with the bit START at 1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of
the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR). The
selected hardware trigger is enabled with the bit TRGEN in the Mode Register (ADC_MR).
If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If
one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform
Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware
logic automatically performs the conversions on the active channels, then waits for a new request. The Channel
Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or
disabled independently.
If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the
resulting data buffers should be interpreted accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware
trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger.
41.5.6 Sleep Mode and Conversion Sequencer
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for
conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode Register ADC_MR.
The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the
conversions of all channels at lowest power consumption.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up
time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are
complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into
account.
The conversion sequencer allows automatic processing with minimum processor intervention and optimized power
consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic
acquisition of several samples can be processed automatically without any intervention of the processor via the
PDC.
Note:
The reference voltage pins always remain connected in normal mode as in sleep mode.
41.5.7 ADC Timings
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register
ADC_MR.
In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final
value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode
Register ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into
consideration to program a precise value in the SHTIM field. See the section, ADC Characteristics in the product
datasheet.
808
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.6
Analog-to-Digital Converter (ADC) User Interface
Table 41-2.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
ADC_CR
Write-only
–
0x04
Mode Register
ADC_MR
Read/Write
0x00000000
0x08
Reserved
–
–
–
0x0C
Reserved
–
–
–
0x10
Channel Enable Register
ADC_CHER
Write-only
–
0x14
Channel Disable Register
ADC_CHDR
Write-only
–
0x18
Channel Status Register
ADC_CHSR
Read-only
0x00000000
0x1C
Status Register
ADC_SR
Read-only
0x000C0000
0x20
Last Converted Data Register
ADC_LCDR
Read-only
0x00000000
0x24
Interrupt Enable Register
ADC_IER
Write-only
–
0x28
Interrupt Disable Register
ADC_IDR
Write-only
–
0x2C
Interrupt Mask Register
ADC_IMR
Read-only
0x00000000
0x30
Channel Data Register 0
ADC_CDR0
Read-only
0x00000000
0x34
Channel Data Register 1
ADC_CDR1
Read-only
0x00000000
...
...
...
...
Channel Data Register 3
ADC_CDR3
Read-only
0x00000000
Reserved
–
–
–
...
0x40
0x44–0xFC
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
809
41.6.1 ADC Control Register
Name:
ADC_CR
Address:
0xFFFE0000
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
START
0
SWRST
• SWRST: Software Reset
0: No effect.
1: Resets the ADC simulating a hardware reset.
• START: Start Conversion
0: No effect.
1: Begins analog-to-digital conversion.
810
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.6.2 ADC Mode Register
Name:
ADC_MR
Address:
0xFFFE0004
Access:
Read/Write
31
–
30
–
29
–
28
–
27
23
–
22
21
20
19
STARTUP
15
14
13
12
26
25
24
18
17
16
11
10
9
8
3
2
TRGSEL
1
0
TRGEN
SHTIM
PRESCAL
7
–
6
–
5
SLEEP
4
LOWRES
• TRGEN: Trigger Enable
TRGEN
Selected TRGEN
0
Hardware triggers are disabled. Starting a conversion is only possible by software.
1
Hardware trigger selected by TRGSEL field is enabled.
• TRGSEL: Trigger Selection
TRGSEL
Selected TRGSEL
0
0
0
TIO Output of the Timer Counter Channel 0
0
0
1
TIO Output of the Timer Counter Channel 1
0
1
0
TIO Output of the Timer Counter Channel 2
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
External trigger
1
1
1
Reserved
• LOWRES: Resolution
LOWRES
Selected Resolution
0
10-bit resolution
1
8-bit resolution
• SLEEP: Sleep Mode
SLEEP
Selected Mode
0
Normal Mode
1
Sleep Mode
• PRESCAL: Prescaler Rate Selection
ADCClock = MCK / ((PRESCAL+1) * 2)
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
811
• STARTUP: Start Up Time
Startup Time = (STARTUP+1) * 8 / ADCClock
• SHTIM: Sample & Hold Time
Sample & Hold Time = SHTIM/ADCClock
812
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.6.3 ADC Channel Enable Register
Name:
ADC_CHER
Address:
0xFFFE0010
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CH3
2
CH2
1
CH1
0
CH0
• CHx: Channel x Enable
0: No effect.
1: Enables the corresponding channel.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
813
41.6.4 ADC Channel Disable Register
Name:
ADC_CHDR
Address:
0xFFFE0014
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CH3
2
CH2
1
CH1
0
CH0
• CHx: Channel x Disable
0: No effect.
1: Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
814
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.6.5 ADC Channel Status Register
Name:
ADC_CHSR
Address:
0xFFFE0018
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CH3
2
CH2
1
CH1
0
CH0
• CHx: Channel x Status
0: Corresponding channel is disabled.
1: Corresponding channel is enabled.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
815
41.6.6 ADC Status Register
Name:
ADC_SR
Address:
0xFFFE001C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
RXBUFF
18
ENDRX
17
GOVRE
16
DRDY
15
–
14
–
13
–
12
–
11
OVRE3
10
OVRE2
9
OVRE1
8
OVRE0
7
–
6
–
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
• EOCx: End of Conversion x
0: Corresponding analog channel is disabled, or the conversion is not finished.
1: Corresponding analog channel is enabled and conversion is complete.
• OVREx: Overrun Error x
0: No overrun error on the corresponding channel since the last read of ADC_SR.
1: There has been an overrun error on the corresponding channel since the last read of ADC_SR.
• DRDY: Data Ready
0: No data has been converted since the last read of ADC_LCDR.
1: At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error
0: No General Overrun Error occurred since the last read of ADC_SR.
1: At least one General Overrun Error has occurred since the last read of ADC_SR.
• ENDRX: End of RX Buffer
0: The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR.
1: The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR.
• RXBUFF: RX Buffer Full
0: ADC_RCR or ADC_RNCR have a value other than 0.
1: Both ADC_RCR and ADC_RNCR have a value of 0.
816
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.6.7 ADC Last Converted Data Register
Name:
ADC_LCDR
Address:
0xFFFE0020
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
7
6
5
4
3
2
1
8
LDATA
0
LDATA
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
817
41.6.8 ADC Interrupt Enable Register
Name:
ADC_IER
Address:
0xFFFE0024
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
RXBUFF
18
ENDRX
17
GOVRE
16
DRDY
15
–
14
–
13
–
12
–
11
OVRE3
10
OVRE2
9
OVRE1
8
OVRE0
7
–
6
–
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
• EOCx: End of Conversion Interrupt Enable x
• OVREx: Overrun Error Interrupt Enable x
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
0: No effect.
1: Enables the corresponding interrupt.
818
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.6.9 ADC Interrupt Disable Register
Name:
ADC_IDR
Address:
0xFFFE0028
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
RXBUFF
18
ENDRX
17
GOVRE
16
DRDY
15
–
14
–
13
–
12
–
11
OVRE3
10
OVRE2
9
OVRE1
8
OVRE0
7
–
6
–
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
• EOCx: End of Conversion Interrupt Disable x
• OVREx: Overrun Error Interrupt Disable x
• DRDY: Data Ready Interrupt Disable
• GOVRE: General Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
0: No effect.
1: Disables the corresponding interrupt.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
819
41.6.10 ADC Interrupt Mask Register
Name:
ADC_IMR
Address:
0xFFFE002C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
RXBUFF
18
ENDRX
17
GOVRE
16
DRDY
15
–
14
–
13
–
12
–
11
OVRE3
10
OVRE2
9
OVRE1
8
OVRE0
7
–
6
–
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
• EOCx: End of Conversion Interrupt Mask x
• OVREx: Overrun Error Interrupt Mask x
• DRDY: Data Ready Interrupt Mask
• GOVRE: General Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
820
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
41.6.11 ADC Channel Data Register
Name:
ADC_CDRx
Address:
0xFFFE0030
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
7
6
5
4
3
2
1
8
DATA
0
DATA
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
821
42.
Electrical Characteristics
42.1
Absolute Maximum Ratings
Table 42-1.
Absolute Maximum Ratings*
Operating Temperature (Industrial)................-40°C to +85°C
*NOTICE:
Storage Temperature....................................-60°C to +150°C
Voltage on Input Pins
with Respect to Ground....-0.3V to VDDIO + 0.3V (+ 4V max)
Maximum Operating Voltage
(VDDCORE, VDDPLL and VDDBU)...............................2.0V
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at these or other conditions beyond those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Maximum Operating Voltage
(VDDIOM and VDDIOP)..................................................4.0V
Total DC Output Current on all I/O lines.....................350 mA
42.2
DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise
specified.
Table 42-2.
DC Characteristics
Symbol Parameter
Conditions
VDDCORE DC Supply Core
Min
Typ
Max
Unit
1.65
1.8
1.95
V
VDDBU
DC Supply Backup
1.65
1.8
1.95
V
VDDPLL
DC Supply PLL
1.65
1.8
1.95
V
VDDIOM
DC Supply Memory I/Os
1.65/3.0
1.8/3.3
1.95/3.6
V
VDDIOP0 DC Supply Peripheral I/Os
3.0
3.3
3.6
V
VDDIOP1 DC Supply Peripheral I/Os
1.65
1.8/2.5/3.3
3.6
V
VDDANA DC Supply Analog
3.0
3.3
3.6
V
VIL
Input Low-level Voltage
VIH
Input High-level Voltage
VOL
VOH
822
VDDIO from 3.0V to 3.6V
-0.3
0.8
V
VDDIO from 1.65V to 1.95V
-0.3
0.3 × VDDIO
V
2
VDDIO + 0.3
V
0.7 × VDDIO
VDDIO + 0.3
V
IO Max, VDDIO from 3.0V to 3.6V
0.4
V
CMOS (IO < 0.3 mA) VDDIO from 1.65V to
1.95V
0.1
V
TTL (IO Max) VDDIO from 1.65V to 1.95V
0.4
V
VDDIO from 3.0V to 3.6V
VDDIO from 1.65V to 1.95V
Output Low-level Voltage
Output High-level Voltage
IO Max, VDDIO from 3.0V to 3.6V
VDDIO - 0.4
V
CMOS (IO < 0.3 mA) VDDIO from 1.65V to
1.95V
VDDIO - 0.1
V
TTL (IO Max) VDDIO from 1.65V to 1.95V
VDDIO - 0.4
V
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Table 42-2.
DC Characteristics (Continued)
Symbol Parameter
RPULLUP Pull-up Resistance
IO
Output Current
Conditions
Min
Typ
Max
Unit
PA0–PA31 PB0–PB31 PC0–PC3
NRTST and NRST
50
100
180
kΩ
PC4–PC31
VDDIOM in 1.8V range
240
1000
kΩ
PC4–PC31
VDDIOM in 3.3V range
50
350
kΩ
PA0–PA31 PB0–PB31 PC0–PC3
8
mA
PC4–PC31 in 3.3V range
2
mA
PC4–PC31 in 1.8V range
4
mA
On VDDCORE = 1.8V,
MCK = 0 Hz, excluding POR
TA = 25°C
500
µA
All inputs driven TMS, TDI, TCK,
TA = 85°C
NRST = 1
ISC
Static Current
Table 42-3.
Symbol
Parameter
Threshold Level
Vhys
Hysteresis
IDD
Current Consumption
Table 42-4.
Symbol
TA = 25°C
All inputs driven
WKUP = 0
TA = 85°C
2
µA
20
Brownout Detector Characteristics
VBOT-
tSTART
On VDDBU = 1.8V,
Logic cells consumption,
excluding POR
5000
Conditions
Min
Typ
Max
Unit
1.52
1.55
1.58
V
Vhys = VBOT+ - VBOT-
50
65
mV
BOD on (GPNVMbit[1] is set)
12
18
µA
1
µA
200
µs
BOD off (GPNVMbit[1] is cleared)
Startup Time
100
DC Flash Characteristics
Parameter
Conditions
Min
Max
Unit
tPU
Power-up delay
30
µs
ISTDBY
Standby current
20
µA
Read at maximum frequency (access time
= 60 ns)
VDDCORE = 1.8V
13.0
mA
Write
VDDCORE = 1.8V
7.0
mA
ICC
Active current
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
823
42.3
Power Consumption
Typical power consumption of PLLs, Slow Clock and Main Oscillator.
Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup.
Power consumption by peripheral: calculated as the difference in current measurement after having enabled
then disabled the corresponding clock.
42.3.1 Power Consumption versus Modes
The values in Table 42-5 and Table 42-6 on page 825 are estimated values of the power consumption with
operating conditions as follows:
VDDIOM = VDDIOP = 3.3V
VDDPLL = 1.8V
VDDCORE = VDDBU = 1.8V
TA = 25°C
There is no consumption on the I/Os of the device
Figure 42-1.
Measures Schematics
VDDBU
AMP1
VDDCORE
AMP2
These figures represent the power consumption estimated on the power supplies.
Table 42-5.
Power Consumption for Different Modes
Mode
Conditions
Consumption
Unit
130
mA
17
mA
600
µA
5
µA
ARM Core clock is 180 MHz.
Active
MCK is 90 MHz.
All peripheral clocks deactivated.
onto AMP2
Idle state, waiting an interrupt.
Idle
All peripheral clocks deactivated.
onto AMP2
ARM Core clock is 500 Hz.
Ultra low power
All peripheral clocks deactivated.
onto AMP2
Backup
824
Device only VDDBU powered
onto AMP1
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Table 42-6.
Power Consumption by Peripheral in Active Mode
Peripheral
Consumption
PIO Controller
10
USART
30
UHP
14
UDP
20
ADC
17
TWI
21
SPI
10
MCI
30
SSC
20
Timer Counter Channels
6
ISI
8
EMAC
88
Unit
µA/MHz
42.4
I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
Output duty cycle (40%–60%)
Minimum output swing: 100 mV to VDDIO - 100 mV
Addition of rising and falling time inferior to 75% of the period
Table 42-7.
Symbol
fmax
I/O Characteristics
Parameter
Conditions
VDDIOP0 powered pins frequency
3.3V domain(1)
3.3V domain
(1)
2.5V domain
(2)
1.8V domain
(3)
VDDIOP1 powered pins frequency
Notes:
1. VDDIOP from 3.0V to 3.6V
2. VDDIOP from 2.3V to 2.7V
3. VDDIOP from 1.65V to 1.95V
42.5
Clock Characteristics
Min
Max
Unit
Max. external cap. load = 40 pF
83.3
MHz
Max. external cap. load = 40 pF
83.3
MHz
Max. external cap. load = 30 pF
71.4
MHz
Max. external cap. load = 20 pF
50
MHz
42.5.1 Processor Clock Characteristics
Table 42-8.
Processor Clock Waveform Parameters
Symbol
Parameter
Conditions
1/(tCPPCK)
Processor Clock Frequency
1/(tCPPCK)
Processor Clock Frequency
Min
Max
Unit
VDDCORE = 1.65V, TA = 85°C
160
MHz
VDDCORE = 1.8V, TA = 85°C
180
MHz
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
825
42.5.2 Master Clock Characteristics
Table 42-9.
Symbol
Master Clock Waveform Parameters
Parameter
Conditions
1/(tCPMCK)
Master Clock Frequency
1/(tCPMCK)
Master Clock Frequency
Min
Max
Unit
VDDCORE = 1.65V , TA = 85°C
80
MHz
VDDCORE = 1.8V, TA = 85°C
90
MHz
Max
Unit
50
MHz
42.5.3 XIN Clock Characteristics
Table 42-10.
XIN Clock Electrical Characteristics
Symbol
Parameter
1/(tCPXIN)
XIN Clock Frequency
Conditions
Min
tCPXIN
XIN Clock Period
tCHXIN
XIN Clock High Half-period
0.4 × tCPXIN
0.6 × tCPXIN
ns
tCLXIN
XIN Clock Low Half-period
0.4 × tCPXIN
0.6 × tCPXIN
ns
25
pF
1000
kΩ
1.8
V
CIN
XIN Input Capacitance
RIN
XIN Pull-down Resistor
VIN
VIN Voltage
42.6
20
ns
Main Oscillator in Bypass mode (i.e., when
MOSCEN = 0 and OSCBYPASS = 1 in the
CKGR_MOR). See “PMC Clock Generator Main
Oscillator Register”.
Crystal Oscillator Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of
power supply, unless otherwise specified.
42.6.1 32 kHz Oscillator Characteristics
Table 42-11.
Symbol
32 kHz Oscillator Characteristics
Parameter
1/(tCP32KHz)
Crystal Oscillator Frequency
CCRYSTAL32
Load Capacitance
CLEXT32(2)
External Load Capacitance
Conditions
Min
Crystal @ 32.768 kHz
pF
CCRYSTAL32 = 12.5 pF
17
pF
40
60
%
CCRYSTAL32 = 6 pF
300
ms
CCRYSTAL32 = 12.5 pF
900
ms
CCRYSTAL32 = 6 pF
600
ms
CCRYSTAL32 = 12.5 pF
1200
ms
1. RS is the equivalent series resistance.
2. CLEXT32 is determined by taking into account internal, parasitic and package load capacitance.
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
12.5
pF
Startup Time
SAM9XE Series [DATASHEET]
kHz
4
RS = 100 kΩ(1)
826
6
Unit
CCRYSTAL32 = 6 pF
RS = 50 kΩ(1)
Notes:
Max
32.768
Duty Cycle
tSTART
Typ
Figure 42-2.
32 kHz Oscillator Schematic
SAM9XE
XIN32
XOUT32
GNDBU
CCRYSTAL32
CLEXT32
Table 42-12.
Symbol
ESR
CLEXT32
Crystal Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
50
100
kΩ
1
3
fF
0.8
1.7
pF
Max
Unit
Equivalent Series Resistor Rs
Motional Capacitance
Cm
CSHUNT
Crystal @ 32.768 kHz
Shunt Capacitance
42.6.2 RC Oscillator Characteristics
Table 42-13.
RC Oscillator Characteristics
Symbol
Parameter
1/(tCPRCz)
Crystal Oscillator Frequency
22
42
kHz
Duty Cycle
45
55
%
75
µs
tSTART
Conditions
Min
Typ
Startup Time
42.6.3 Slow Clock Selection
Table 42-14.
Slow Clock Selection
OSCSEL Signal State
Slow Clock
Startup Time
0
Internal RC Oscillator
200 µs
1
External 32768 Hz Crystal
1200 ms
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
827
42.6.4 Main Oscillator Characteristics
Table 42-15.
Symbol
Main Oscillator Characteristics
Parameter
Conditions
1/(tCPMAIN) Crystal Oscillator Frequency
CCRYSTAL
Crystal Load Capacitance
CLEXT(6)
External Load Capacitance
Max
Unit
3
16
20
MHz
17.5
pF
CCRYSTAL = 12.5 pF(5)
(5)
CCRYSTAL = 17.5 pF
tSTART
30
Startup Time
IDD STDBY
VDDPLL = 1.65–1.95 V
3
pF
13
pF
50
70
CSHUNT = 3 pF, 1/(tCPMAIN) = 3 MHz
14.5
CSHUNT = 7 pF, 1/(tCPMAIN) = 8 MHz
4
CSHUNT = 7 pF, 1/(tCPMAIN) = 16 MHz
1.4
CSHUNT = 7 pF, 1/(tCPMAIN) = 20 MHz
1
1
@ 3 MHz
15
@ 8 MHz
30
@ 16 MHz
50
@ 20 MHz
50
Drive Level
@ 3 MHz(1)
150
250
(2)
150
250
(3)
300
450
@ 20 MHz(4)
400
550
Current Dissipation
@ 16 MHz
1.
2.
3.
4.
5.
6.
µA
RS = 100 to 200 Ω; CSHUNT = 2.0 to 2.5 pF; Cm = 2 to 1.5 fF (typ, worst case) using 1 kΩ serial resistor on XOUT.
RS = 50 to 100 Ω; CSHUNT = 2.0 to 2.5 pF; Cm = 4 to 3 fF (typ, worst case).
RS = 25 to 50 Ω; CSHUNT = 2.5 to 3.0 pF; Cm = 7 to 5 fF (typ, worst case).
RS = 20 to 50 Ω; CSHUNT = 3.2 to 4.0 pF; Cm = 10 to 8 fF (typ, worst case).
Additional user load capacitance should be subtracted from CLEXT.
CLEXT is determined by taking into account internal, parasitic and package load capacitance.
Figure 42-3.
µA
µW
@ 8 MHz
IDD ON
%
ms
Standby Current Consumption Standby mode
PON
Main Oscillator Schematic
SAM9XE
XIN
XOUT
GNDPLL
1K
CCRYSTAL
CLEXT
828
Typ
12.5
Duty Cycle
Notes:
Min
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
CLEXT
42.6.5 Crystal Characteristics
Table 42-16.
Symbol
ESR
Crystal Characteristics
Parameter
Conditions
Min
Typ
Max
Fundamental @ 3 MHz
200
Fundamental @ 8 MHz
100
Fundamental @ 16 MHz
80
Fundamental @ 20 MHz
50
Equivalent Series Resistor Rs
Cm
CSHUNT
Unit
Ω
Motional Capacitance
8
fF
Shunt Capacitance
7
pF
Max
Unit
42.6.6 PLL Characteristics
Table 42-17.
Symbol
fOUT
PLLA Characteristics(1)
Parameter
Conditions
Min
Field CKGR_PLL.OUTA = 00
80
160
MHz
Field CKGR_PLL.OUTA = 10
150
220
MHz
1
32
MHz
4.5
mA
1
µA
Max
Unit
130
MHz
5
(1)
MHz
1.2
mA
1
µA
1
ms
Output Frequency
fIN
Input Frequency
IPLL
Current Consumption
Active mode @ 240 MHz
Note:
1. Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
Symbol
PLLB Characteristics
Parameter
Conditions
Min
Output Frequency
Field CKGR_PLL.OUTA = 01
70
fIN
Input Frequency
IPLL
Current Consumption
1
Active mode @ 130 MHz
tSTART
Note:
3.6
Standby mode
Table 42-18.
fOUT
Typ
Standby mode
Startup TIme
Typ
1. The embedded filter is optimized for a 2 MHz input frequency. DIVB must be selected to meet this requirement.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
829
42.7
ADC Characteristics
Table 42-19.
Channel Conversion Time and ADC Clock
Parameter
Conditions
ADC Clock Frequency
10-bit resolution mode
Startup Time
Return from Idle mode
Track and Hold Acquisition Time (TTH)
ADC Clock = 5 MHz
Conversion Time
ADC Clock = 5 MHz
Throughput Rate
ADC Clock = 5 MHz
Note:
Min
Typ
Max
Unit
5
MHz
15
µs
(1)
µs
1.2
2
µs
312
ksps
1. In worst case, the Track-and-Hold Acquisition Time is given by:
TTH (µs) = 1.2 + (0.09 × ZIN)(kΩ)
In case of very high input impedance, this value must be respected in order to guarantee the correct converted value. An
internal input current buffer supplies the current required for the low input impedance (1 mA max).
To achieve optimal performance of the ADC, the analog power supply VDDANA and the ADVREF input voltage
must be decoupled with a 4.7 µF capacitor in parallel with a 100 nF capacitor.
Table 42-20.
External Voltage Reference Input
Parameter
Conditions
ADVREF Input Voltage Range
Min
Typ
Max
Unit
VDDANA
V
220
µA
300
620
µA
Typ
Max
Unit
ADVREF
V
1
µA
12
14
pF
Typ
Max
Unit
2.4
ADVREF Average Current
Current Consumption on VDDANA
Table 42-21.
Analog Inputs
Parameter
Min
Input Voltage Range
0
Input Leakage Current
Input Capacitance
Table 42-22.
Symbol
Transfer Characteristics
Parameter
Min
Resolution
INL
Integral Non-linearity
DNL
Differential Non-linearity
10
-0.9
bit
±2
LSB
+1
LSB
EO
Offset Error
±2
LSB
EG
Gain Error
±2
LSB
830
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
42.8
USB Transceiver Characteristics
Table 42-23.
Symbol
USB Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
0.8
V
Input Levels
VIL
Low Level
VIH
High Level
VDI
Differential Input Sensitivity
VCM
Differential Input Common Mode
Range
CIN
Transceiver Capacitance
Capacitance to ground on each line
Ilkg
Hi-Z State Data Line Leakage
0V < VIN < 3.3V
Recommended External USB Series
Resistor
In series with each USB pin with ±5%
REXT
|(D+) - (D-)|
2.0
V
0.2
V
0.8
- 10
2.5
V
9.18
pF
+ 10
µA
Ω
27
Output Levels
VOL
Low Level Output
Measured with RL of 1.425 kΩ tied to 3.6V
0.0
0.3
V
VOH
High Level Output
Measured with RL of 14.25 kΩ tied to GND
2.8
3.6
V
VCRS
Output Signal Crossover Voltage
Measure conditions described in Figure 42-1
1.3
2.0
V
Pull-up and Pull-down Resistor
RPUI
Bus Pull-up Resistor on Upstream
Port (idle bus)
0.900
1.575
kΩ
RPUA
Bus Pull-up Resistor on Upstream
Port (upstream port receiving)
1.425
3.090
kΩ
RPD
Bus Pull-down resistor
14.25
24.8
kΩ
200
µA
150
µA
IVDDIO
Current Consumption VDDIO
IVDDCORE
42.9
Current Consumption VDDCORE
Transceiver enabled in input mode
DDP = 1 and DDM = 0
Core Power Supply POR Characteristics
Table 42-24.
Symbol
Power-On-Reset Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
VT+
Threshold Voltage Rising
Minimum Slope of +2.0V/200ms
1.35
1.50
1.59
V
VT-
Threshold Voltage Falling
1.25
1.30
1.40
V
tRST
Reset Time
100
200
350
µs
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
831
42.10 Embedded Flash Characteristics
The maximum operating frequency given in Table 42-26 is limited by the Embedded Flash access time when the
processor is fetching code out of it. The table provides the device maximum operating frequency defined by the
value of field EEFC_FMR.FWS. This field defines the number of wait states required to access the Embedded
Flash Memory.
Table 42-25.
Maximum MCK Frequency vs. Embedded Flash Wait States
Maximum MCK Frequency (MHz)
EEFC_FMR.FWS
Conditions
VDDCORE = 1.8V
VDDCORE = 1.65V
0
19
17
1
40
36
60
48
3
76
62
4
90
80
2
Table 42-26.
TA = 85°C
AC Flash Characteristics
Parameter
Conditions
Min
Max
Unit
Per page including auto-erase
4
ms
Per page without auto-erase
2
ms
Program Cycle Time
Full Chip Erase
10
ms
42.11 SMC Timings
42.11.1 Timing Conditions
SMC timings are given in worst case conditions (1.65V/3.0V, TA = 85°C).
Timings are given assuming a capacitance load on data, control and address pads as defined in Table 42-27.
Table 42-27.
Capacitance Load
Supply
CLOAD Max
3.3V
50 pF
1.8V
30 pF
In the following tables tCPMCK represents the MCK period.
832
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
42.11.2 Read Timings
Table 42-28.
SMC Read Signals - NRD Controlled (READ_MODE = 1)
Min
Symbol
Parameter
1.8V VDDIOM Supply
3.3V VDDIOM Supply
Unit
NO HOLD SETTINGS (nrd hold = 0)
SMC1
Data Setup before NRD High
12.6
12.61
ns
SMC2
Data Hold after NRD High
-7.2
-7.2
ns
HOLD SETTINGS (nrd hold ≠ 0)
SMC3
Data Setup before NRD High
9
9
ns
SMC4
Data Hold after NRD High
0
0
ns
HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold = 0)
SMC5
NBS0/A0, NBS1, NBS2/A1, NBS3,
A2–A25 Valid before NRD High
(nrd setup + nrd pulse) × tCPMCK -3.0
(nrd setup + nrd pulse) × tCPMCK -3.1
ns
SMC6
NCS low before NRD High
(nrd setup + nrd pulse - ncs rd setup)
× tCPMCK -7.1
(nrd setup + nrd pulse - ncs rd setup)
× tCPMCK -7.2
ns
SMC7
NRD Pulse Width
nrd pulse × tCPMCK -0.3
nrd pulse × tCPMCK -0.3
ns
3.3V VDDIOM Supply
Unit
Table 42-29.
SMC Read Signals - NCS Controlled (READ_MODE= 0)
Min
Symbol
Parameter
1.8V VDDIOM Supply
NO HOLD SETTINGS (ncs rd hold = 0)
SMC8
Data Setup before NCS High
8
7.8
ns
SMC9
Data Hold after NCS High
0
0
ns
6.6
6.4
ns
0
0
ns
(ncs rd setup + ncs rd pulse) ×
tCPMCK -3.3
(ncs rd setup + ncs rd pulse) ×
tCPMCK -3.4
ns
HOLD SETTINGS (ncs rd hold ≠ 0)
SMC10
Data Setup before NCS High
SMC11
Data Hold after NCS High
HOLD or NO HOLD SETTINGS (ncs rd hold ≠ 0, ncs rd hold = 0)
SMC12
NBS0/A0, NBS1, NBS2/A1, NBS3,
A2–A25 valid before NCS High
SMC13
NRD low before NCS High
(ncs rd setup + ncs rd pulse - nrd
setup) × tCPMCK -0.9
(ncs rd setup + ncs rd pulse - nrd
setup) × tCPMCK -0.9
ns
SMC14
NCS Pulse Width
ncs rd pulse length × tCPMCK -7.7
ncs rd pulse length × tCPMCK -7.7
ns
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
833
42.11.3 Write Timings
Table 42-30.
SMC Write Signals - NWE Controlled (Write_Mode = 1)
Min
Symbol
Parameter
1.8V VDDIOM Supply
3.3V VDDIOM Supply
Unit
HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0)
nwe pulse × tCPMCK - 1
nwe pulse × tCPMCK - 0.99
ns
NWE Pulse Width
nwe pulse × tCPMCK - 1.7
nwe pulse × tCPMCK - 1.7
ns
SMC17
NBS0/A0 NBS1, NBS2/A1, NBS3,
A2–A25 valid before NWE low
nwe setup × tCPMCK - 2.8
nwe setup × tCPMCK - 2.7
ns
SMC18
NCS low before NWE high
(nwe setup - ncs rd setup + nwe
pulse) × tCPMCK - 1.2
(nwe setup - ncs rd setup + nwe
pulse) × tCPMCK - 1.2
ns
nwe hold × tCPMCK - 2.8
nwe hold × tCPMCK - 5.6
ns
(nwe hold - ncs wr hold) × tCPMCK 1.4
(nwe hold - ncs wr hold) × tCPMCK 1.4
ns
3.2
ns
SMC15
Data Out Valid before NWE High
SMC16
HOLD SETTINGS (nwe hold ≠ 0)
SMC19
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2–A25
change
SMC20
NWE High to NCS Inactive (1)
NO HOLD SETTINGS (nwe hold = 0)
SMC21
Note:
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2–A25,
NCS change(1)
3.3
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “NWE hold
length”.
Table 42-31.
SMC Write NCS Controlled (WRITE_MODE=0)
Min
Symbol
Parameter
1.8V VDDIOM Supply
3.3V VDDIOM Supply
Unit
SMC22
Data Out Valid before NCS High
ncs wr pulse × tCPMCK - 1.2
ncs wr pulse × tCPMCK - 5.8
ns
SMC23
NCS Pulse Width
ncs wr pulse × tCPMCK - 1.13
ncs wr pulse × tCPMCK - 1.12
ns
SMC24
NBS0/A0 NBS1, NBS2/A1, NBS3,
A2–A25 valid before NCS low
ncs wr setup × tCPMCK - 1.7
ncs wr setup × tCPMCK - 3.0
ns
SMC25
NWE low before NCS high
(ncs wr setup - nwe setup + ncs
pulse) × tCPMCK - 1.13
(ncs wr setup - nwe setup + ncs
pulse) × tCPMCK - 1.12
ns
SMC26
NCS High to Data Out, NBS0/A0,
NBS1, NBS2/A1, NBS3, A2–A25,
change
ncs wr hold × tCPMCK - 3.3
ncs wr hold × tCPMCK - 3.4
ns
SMC27
NCS High to NWE Inactive
(ncs wr hold - nwe hold) × tCPMCK 0.91
(ncs wr hold - nwe hold) × tCPMCK 0.88
ns
834
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Figure 42-4.
SMC Timings - NCS Controlled Read and Write
SMC12
SMC12
SMC26
SMC24
A0/A1/NBS[3:0]/A2-A25
SMC13
SMC13
NRD
SMC14
NCS
SMC14
SMC9
SMC8
SMC10
SMC23
SMC11
SMC22
SMC26
D0 - D15
SMC27
SMC25
NWE
NCS Controlled READ
with NO HOLD
Figure 42-5.
NCS Controlled READ
with HOLD
NCS Controlled WRITE
SMC Timings - NRD Controlled Read and NWE Controlled Write
SMC21
SMC17
SMC5
SMC5
SMC17
SMC19
A0/A1/NBS[3:0]/A2-A25
SMC6
SMC21 SMC6
SMC18
SMC18
SMC20
NCS
NRD
SMC7
SMC7
SMC1
SMC2
SMC15
SMC21
SMC3
SMC4
SMC15
SMC19
D0 - D31
NWE
SMC16
NRD Controlled READ
with NO HOLD
NWE Controlled WRITE
with NO HOLD
SMC16
NRD Controlled READ
with HOLD
NWE Controlled WRITE
with HOLD
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
835
42.12 SDRAMC
42.12.1 Timing Conditions
SDRAMC timings are given in worst case conditions (1.65V/3.0V, TA = 85°C).
Timings are given assuming a capacitance load on data, control and address pads as defined in Table 42-32, as
well as the SDCK pad as defined in Table 42-33.
Table 42-32.
Capacitance Load on Data, Control and Address Pads
Table 42-33.
Supply
CLOAD Max
3.3V
50 pF
1.8V
30 pF
Capacitance Load on SDCK Pad
Supply
CLOAD Max
3.3V
10 pF
1.8V
10 pF
42.12.2 Timing Figures
Table 42-34.
SDRAM Characteristics
Timings Standard
Parameter
Supply
Min
SDRAM Controller Clock Frequency
Control/Address/Data In Setup(1)(2)
PC100
Control/Address/Data In Hold
(1)(2)
3.3V
Control/Address/Data In Hold
1
ns
3.3V
1.5
ns
0.8
ns
1.8V
836
1.
2.
3.
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
MHz
ns
1
ns
6/8(3)
2.5
Control is the set of following signals: SDCKE, SDCS, RAS, CAS, SDA10, BAx, DQMx, and SDWE
Address is the set of A0–A9, A11–A13
133 MHz with CAS Latency = 3, 100 MHz with CAS Latency = 2
SAM9XE Series [DATASHEET]
(3)
1.5
Data Out Access time after SDCK rising
Notes:
ns
133/100
(1)(2)
Data Out change time after SDCK rising
ns
3.0
SDRAM Controller Clock Frequency
Control/Address/Data In Hold
MHz
5.4
Data Out change time after SDCK rising
Mobile SDRAM
ns
133
(1)(2)
(1)(2)
ns
3
Data Out Access time after SDCK rising
Control/Address/Data In Setup
MHz
ns
SDRAM Controller Clock Frequency
PC133
100
6
Data Out change time after SDCK rising
(1)(2)
Unit
2
Data Out Access time after SDCK rising
Control/Address/Data In Setup
Max
ns
ns
42.13 EMAC Timings
Table 42-35.
EMAC Signals Relative to EMDC
Symbol
Parameter
Min
Max
Unit
EMAC1
Setup for EMDIO from EMDC rising
29.4
ns
EMAC2
Hold for EMDIO from EMDC rising
0
ns
EMAC3
EMDIO toggling from EMDC falling
0
4.3
ns
Min
Max
Unit
42.13.1 MII Mode
Table 42-36.
EMAC MII Specific Signals
Symbol
Parameter
EMAC4
Setup for ECOL from ETXCK rising
0
ns
EMAC5
Hold for ECOL from ETXCK rising
1.2
ns
EMAC6
Setup for ECRS from ETXCK rising
0.9
ns
EMAC7
Hold for ECRS from ETXCK rising
0
ns
EMAC8
ETXER toggling from ETXCK rising
15.6
ns
EMAC9
ETXEN toggling from ETXCK rising
14.8
ns
EMAC10
ETX toggling from ETXCK rising
15.5
ns
EMAC11
Setup for ERX from ERXCK
0
ns
EMAC12
Hold for ERX from ERXCK
4.3
ns
EMAC13
Setup for ERXER from ERXCK
0
ns
EMAC14
Hold for ERXER from ERXCK
4.1
ns
EMAC15
Setup for ERXDV from ERXCK
0
ns
EMAC16
Hold for ERXDV from ERXCK
3.7
ns
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
837
Figure 42-6.
EMAC MII Mode
EMDC
EMAC1
EMAC3
EMAC2
EMDIO
EMAC4
EMAC5
EMAC6
EMAC7
ECOL
ECRS
ETXCK
EMAC8
ETXER
EMAC9
ETXEN
EMAC10
ETX[3:0]
ERXCK
EMAC11
EMAC12
ERX[3:0]
EMAC13
EMAC14
EMAC15
EMAC16
ERXER
ERXDV
838
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
42.13.2 RMII Mode
Table 42-37.
EMAC RMII Specific Signals
Symbol
Parameter
Min
Max
Unit
EMAC21
ETXEN toggling from EREFCK rising
13.5
16
ns
EMAC22
ETX toggling from EREFCK rising
12.3
15.5
ns
EMAC23
Setup for ERX from EREFCK
0
ns
EMAC24
Hold for ERX from EREFCK
1.3
ns
EMAC25
Setup for ERXER from EREFCK
0
ns
EMAC26
Hold for ERXER from EREFCK
1.2
ns
EMAC27
Setup for ECRSDV from EREFCK
0.9
ns
EMAC28
Hold for ECRSDV from EREFCK
0
ns
Figure 42-7.
EMAC RMII Mode
EREFCK
EMAC21
ETXEN
EMAC22
ETX[1:0]
EMAC23
EMAC24
ERX[1:0]
EMAC25
EMAC26
EMAC27
EMAC28
ERXER
ECRSDV
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
839
42.14 Peripheral Timings
42.14.1 SPI
42.14.1.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write
modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or
SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 42.6 “Crystal
Oscillator Characteristics”), the maximum SPI frequency is the one from the pad.
Master Read Mode
1
f SPCK Max = -----------------------------------------------------SPI 0 ( orSPI 3 ) + t valid
tvalid is the slave time response to output data after deleting an SPCK edge. For a non-volatile memory with
tvalid (or tV) = 12 ns Max, fSPCKMax = 37.7 MHz @ VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold
timings SPI7/SPI8(or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in slave
read mode is given by SPCK pad.
Slave Write Mode
1
f SPCK Max = -----------------------------------------------------------------------------2x ( S PI 6max ( orSPI 9max ) + t su )
For 3.3V I/O domain and SPI6, fSPCKMax = 18.7 MHz. tsu is the setup time from the master before sampling
data.
42.14.1.2 SPI Timings
SPI timings are given assuming a capacitance load on MISO, SPCK and MOSI as defined in Table 42-38.
Table 42-38.
Capacitance Load for MISO, SPCK and MOSI
Corner
Figure 42-8.
Supply
Max
1.8V/3.3V
20 pF
SPI Master Mode 1 and 2
SPCK
SPI0
MISO
SPI2
MOSI
840
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
SPI1
Figure 42-9.
SPI Master Mode 0 and 3
SPCK
SPI3
SPI4
MISO
SPI5
MOSI
Figure 42-10. SPI Slave Mode 0 and 3
SPCK
SPI6
MISO
SPI7
SPI8
SPI10
SPI11
MOSI
Figure 42-11. SPI Slave Mode 1 and 2
SPCK
SPI9
MISO
MOSI
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
841
Table 42-39.
Symbol
SPICLK
842
SPI Timings
Parameter
Conditions
Min
SPCK frequency
Max
Unit
47
MHz
SPI0
MISO Setup time before SPCK rises
5.8 + 0.5 × tCPMCK
15.4 + 0.5 × tCPMC
ns
SPI1
MISO Hold time after SPCK rises
5.14 + 0.5 × tCPMCK
14.5 + 0.5 × tCPMC
ns
SPI2
SPCK rising to MOSI
-0.16
0.44
ns
SPI3
MISO Setup time before SPCK falls
5.72 + 0.5 × tCPMCK
15.7 + 0.5 × tCPMCK
ns
SPI4
MISO Hold time after SPCK falls
4.7 + 0.5 × tCPMCK
14.8 +0.5 × tCPMCK
ns
SPI5
SPCK falling to MOSI
0.091
0.15
ns
SPI6
SPCK falling to MISO
5.33
18.55
ns
SPI7
MOSI Setup time before SPCK rises
1.41
ns
SPI8
MOSI Hold time after SPCK rises
0
ns
SPI9
SPCK rising to MISO
5.33
SPI10
MOSI Setup time before SPCK falls
1.41
ns
SPI11
MOSI Hold time after SPCK falls
0
ns
SPI12
NPCS0 setup to SPCK rising
0
ns
SPI13
NPCS0 hold after SPCK falling
7.02
ns
SPI14
NPCS0 setup to SPCK falling
0
ns
SPI15
NPCS0 hold after SPCK rising
4.97
ns
SPI16
NPCS0 falling to MISO valid
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Master Mode
Slave Mode
14.7
14.7
ns
ns
42.14.2 ISI
Figure 42-12. ISI Timing Diagram
ISI1
VSYNC
ISI7
HSYNC
ISI2
ISI5
ISI6
PIXCLK
DATA[7:0]
Valid Data
ISI3
Table 42-40.
Symbol
Valid Data
Valid Data
ISI4
ISI Timings
Parameter
Peripheral Supply
Min
Max
Unit
ISI1
VSYNC to HSYNC
1.62
ns
ISI2
HSYNC to PIXCLK
1.86
ns
ISI3
DATA setup time
-0.9
ns
ISI4
DATA hold time
3.96
ns
ISI5
PIXCLK high time
-0.14
ns
ISI6
PIXCLK low time
0.29
ns
ISI7
PIXCLK frequency
ISI1
VSYNC to HSYNC
1.56
ns
ISI2
HSYNC to PIXCLK
1.95
ns
ISI3
DATA setup time
-1.02
ns
ISI4
DATA hold time
4.14
ns
ISI5
PIXCLK high time
-0.1
ns
ISI6
PIXCLK low time
0.25
ns
ISI7
PIXCLK frequency
ISI1
VSYNC to HSYNC
1.67
ns
ISI2
HSYNC to PIXCLK
-2.26
ns
ISI3
DATA setup time
-1.33
ns
ISI4
DATA hold time
4.56
ns
ISI5
PIXCLK high time
-0.01
ns
ISI6
PIXCLK low time
0.15
ns
ISI7
PIXCLK frequency
3.3V
74.8
2.5V
69.8
1.8V
64.4
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
MHz
MHz
MHz
843
42.14.3 SSC
42.14.3.1 Timing Conditions
SSC timings are given in worst case conditions (1.65V/3.0V, TA = 85°C).
.
Table 42-41.
Capacitance Load
Supply
CLOAD Max
3.3V
30 pF
1.8V
20 pF
42.14.3.2 Timing Extraction
Figure 42-13. SSC Transmitter, TK and TF as Output
TK (CKI = 0)
TK (CKI = 1)
SSC0
TF/TD
Figure 42-14. SSC Transmitter, TK as Input and TF as Output
TK (CKI = 0)
TK (CKI = 1)
SSC1
TF/TD
844
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Figure 42-15. SSC Transmitter, TK as Output and TF as Input
TK (CKI = 0)
TK (CKI = 1)
SSC2
SSC3
TF
SSC4
TD
Figure 42-16. SSC Transmitter, TK and TF as Input
TK (CKI = 1)
TK (CKI = 0)
SSC5
SSC6
TF
SSC7
TD
Figure 42-17. SSC Receiver RK and RF as Input
RK (CKI = 0)
RK (CKI = 1)
SSC8
SSC9
RF/RD
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
845
Figure 42-18. SSC Receiver, RK as Input and RF as Output
RK (CKI = 1)
RK (CKI = 0)
SSC8
SSC9
RD
SSC10
RF
Figure 42-19. SSC Receiver, RK and RF as Output
RK (CKI = 1)
RK (CKI = 0)
SSC11
RD
SSC13
RF
Figure 42-20. SSC Receiver, RK as Output and RF as Input
RK (CKI = 0)
RK (CKI = 1)
SSC11
RF/RD
846
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
SSC12
SSC12
Table 42-42.
Symbol
SSC Timings
Parameter
Conditions
Min
Max
Unit
2.66
ns
Transmitter
SSC0
TK edge to TF/TD (TK output, TF output)
0.17
SSC1
TK edge to TF/TD (TK input, TF output)
6.4
ns
SSC2
TF setup time before TK edge (TK output)
6.1 - tCPMCK
ns
SSC3
TF hold time after TK edge (TK output)
tCPMCK - 5.77
ns
SSC4
TK edge to TF/TD (TK output, TF input)
0.78 + (2 × tCPMCK)
SSC5
TF setup time before TK edge (TK input)
0
ns
SSC6
TF hold time after TK edge (TK input)
tCPMCK
ns
SSC7
TK edge to TF/TD (TK input, TF input)
7 + (3 × tCPMCK)
2.8 + (2 × tCPMCK)
18 + (3 × tCPMCK)
ns
ns
Receiver
SSC8
RF/RD setup time before RK edge (RK input)
SSC9
RF/RD hold time after RK edge (RK input)
SSC10
RK edge to RF (RK input)
SSC11
RF/RD setup time before RK edge (RK output)
SSC12
RF/RD hold time after RK edge (RK output)
SSC13
RK edge to RF (RK output)
0
ns
tCPMCK
ns
4.7
24.2
ns
14.7 - tCPMCK
ns
tCPMCK - 5.3
ns
0
0.8
ns
Figure 42-21. Min and Max Access Time of Output Signals
TK (CKI =1)
TK (CKI =0)
SSC0min
SSC0max
TF/TD
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
847
42.14.4 MCI
The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data
bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content
(empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application
(user programming).
These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card.
Figure 42-22. MCI Timing Diagram
MCI1
CLK
MCI2
MCI3
CMD_DAT Input
MCI4
MCI5
CMD_DAT Output
Shaded areas are not valid
Table 42-43.
Symbol
MCI1
MCI Timings
Parameter
CLK frequency at Data transfer Mode
Conditions
Min
CLOAD = 25 pf
25
CLOAD = 100 pf
20
CLOAD = 250 pf
20
CLK frequency at Identification Mode
848
Max
400
Unit
MHz
kHz
CLK Low time
CLOAD = 100 pf
10
ns
CLK High time
CLOAD = 100 pf
10
ns
CLK Rise time
CLOAD = 100 pf
10
ns
CLK Fall time
CLOAD = 100 pf
10
ns
CLK Low time
CLOAD = 250 pf
50
ns
CLK High time
CLOAD = 250 pf
50
ns
CLK Rise time
CLOAD = 250 pf
50
ns
CLK Fall time
CLOAD = 250 pf
50
ns
MCI2
Input hold time
3
ns
MCI3
Input setup time
3
ns
MCI4
Output change after CLK rising
5
ns
MCI5
Output valid before CLK rising
5
ns
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
42.14.5 UDP
Figure 42-23. USB Data Signal Rise and Fall Times
Rise Time
Fall Time
90%
VCRS
10%
Differential
Data Lines
10%
tr
tf
REXT = 27 ohms
fOSC = 6 MHz/750 kHz
Buffer
Table 42-44.
Symbol
In Full Speed
Parameter
Conditions
tr
Transition Rise Time
CLOAD = 50 pf
tf
Transition Fall Time
CLOAD = 50 pf
trfm
CLOAD
Rise/Fall time Matching
Min
Typ
Max
Unit
4
20
ns
4
20
ns
90
111.11
%
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
849
43.
Mechanical Characteristics
43.1
SAM9XE Package Drawings
Figure 43-1.
Table 43-1.
217-ball LFBGA Package Drawing
Soldering Information (Substrate Level)
Ball Land
0.43 mm +/- 0.05
Soldering Mask Opening
0.30 mm +/- 0.05
Table 43-2.
Device and 217-ball LFBGA Package Maximum Weight
450
mg
Table 43-3.
217-ball LFBGA Package Characteristics
Moisture Sensitivity Level
Table 43-4.
3
Package Reference
JEDEC Drawing Reference
MO-205
JESD97 Classification
e1
850
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
Figure 43-2.
208-lead PQFP Package Drawing
Table 43-5.
Device and 208-lead PQFP Package Maximum Weight
5.5
Table 43-6.
g
208-lead PQFP Package Characteristics
Moisture Sensitivity Level
Table 43-7.
3
Package Reference
JEDEC Drawing Reference
MS-022
JESD97 Classification
e3
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
851
43.2
Soldering Profile
Table 43-8 gives the recommended soldering profile from J-STD-20.
Table 43-8.
Soldering Profile
Profile Feature
Green Package
Average Ramp-up Rate (217°C to Peak)
3°C/sec. max.
Preheat Temperature 175°C ±25°C
180 sec. max.
Temperature Maintained Above 217°C
60 sec. to 150 sec.
Time within 5°C of Actual Peak Temperature
20 sec. to 40 sec.
Peak Temperature Range
260 +0 °C
Ramp-down Rate
6°C/sec. max.
Time 25°C to Peak Temperature
8 min. max.
Note:
It is recommended to apply a soldering temperature higher than 250°C
A maximum of three reflow passes is allowed per component.
852
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
44.
Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking may be in one of the following formats:
YYWW
V
XXXXXXXXX
ARM
where
“YY”: manufactory year
“WW”: manufactory week
“V”: revision
“XXXXXXXXX”: lot number
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
853
45.
Ordering Information
Table 45-1.
Ordering Information
Ordering Code
MRL
Package
AT91SAM9XE256B-CU
B
LFBGA217
AT91SAM9XE512B-QU
B
PQFP208
AT91SAM9XE512B-CU
B
LFBGA217
(1)
AT91SAM9XE128-QU
A
PQFP208
AT91SAM9XE128-CU(1)
A
LFBGA217
(1)
A
PQFP208
(1)
A
LFBGA217
(1)
AT91SAM9XE512-QU
A
PQFP208
AT91SAM9XE512-CU(1)
A
LFBGA217
AT91SAM9XE256-QU
AT91SAM9XE256-CU
Note:
854
Carrier Type
Operating Temperature Range
Tray
Industrial -40°C to 85°C
1. This ordering code is obsolete. Contact your local Atmel sales representative for more information.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
46.
Errata
46.1
SAM9XE128/256/512 Errata - Revision A and Revision B Parts
46.1.1 Analog-to-Digital Converter (ADC)
46.1.1.1 ADC: Sleep Mode
If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after
a conversion occurs.
Problem Fix/Workaround
To activate sleep mode as soon as possible, it is recommended to write successively, ADC Mode Register
(SLEEP) then ADC Control Register (START bit field), in order to start an analog-to-digital conversion and then put
ADC into sleep mode at the end of this conversion.
46.1.2 Error Correction Code Controller (ECC)
46.1.2.1 ECC: Computation with a 1 clock cycle long NRD/NWE pulse
If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, HECC can't compute the parity.
Problem/Fix Workaround
It is recommended to program SMC with a value higher than 1.
46.1.2.2 ECC: Incomplete parity status when error in ECC parity
When a single correctable error is detected in ECC value, the error is located in ECC Parity register's field which
contains a 1 in the 24 least significant bits except when the error is located in the 12th or the 24th bit. In this case
these bits are always stuck at 0.
A Single correctable error is detected but it is impossible to correct it.
Problem/Fix Workaround
None.
46.1.2.3 ECC: 1-bit ECC per 512 Words
1-bit ECC per 512 words is not functional.
Problem/Fix Workaround
Perform the ECC computation by software.
46.1.2.4 ECC: Unsupported hardware ECC on 16-bit NAND Flash
Hardware ECC on 16-bit NAND Flash is not supported.
Problem/Fix Workaround
Perform the ECC by software.
46.1.3 MultiMedia Card Interface (MCI)
46.1.3.1 MCI: Busy signal of R1b responses is not taken in account
The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29,
CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a conflict can occur on data line0 if the
MCI sends data to the card while the card is still busy. The behavior is correct for CMD12 command
(STOP_TRANSFER).
Problem Fix/Workaround
None
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
855
46.1.3.2 MCI: SDIO Interrupt does not work with slots other than A
If there is 1-bit data bus width on slots other than slot A, the SDIO interrupt can not be captured. The sample is
made on the wrong data line.
Problem Fix/Workaround
None
46.1.3.3 MCI: Data Write Operation and number of bytes
The Data Write operation with a number of bytes less than 12 is impossible.
Problem Fix/Workaround
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The BLKLEN or BCNT
field are used to specify the real count number.
46.1.3.4 MCI: Flag Reset is not correct in half duplex mode
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be incorrect. These flags
are reset correctly after a PDC channel enable.
Problem Fix/Workaround
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the PDC channel by
writing PDC_TXTEN or PDC_RXTEN.
46.1.3.5 MCI: Small Block Reading
In case of a read of a small block (i.e., 5 bytes) by the READ_SINGLE_BLOCK command (CMD17), the DATA
FSM may not perform correctly. This occurs if the read transfer is done before the response start bit is sent by the
card. It leads to erratic behavior of the NOTBUSY flag and to a false data time-out error, DTOE.
Problem Fix/Workaround
None.
46.1.3.6 MCI: old SDCard Compatibility
Busy line is sampled 2 clock cycles after the command End Bit when the R1B response type is expected. This
timing is not strictly defined in SD mode.
This timing is defined with MMC specification 4.1. (R1b Busy Timing)
Problem Fix/Workaround
None.
46.1.4 Reset Controller (RSTC)
46.1.4.1 RSTC: Reset Type Status is wrong at power-up
RSTTYP status in the Reset Controller Status Register is wrong at power-up.
It should be “0” (General Reset) but it is “5” (Brownout Reset). The value is the same if Brownout and Brownout
Reset are enabled or not. The BODSTS bit remains correct.
Problem Fix/Workaround
None.
856
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
46.1.5 Static Memory Controller (SMC)
46.1.5.1 SMC: Chip Select Parameters Modification
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code from a memory
connected on this CS0, may lead to unpredictable behavior.
Problem Fix/Workaround
The code used to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a
memory connected to another Chip Select.
46.1.6 Serial Peripheral Interface (SPI)
46.1.6.1 SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
If the SPI is used in the following configuration:
master mode
CPOL = 1 and NCPHA = 0
multiple chip selects used with one transfer with baud rate (SCBR) equal to 1 (i.e., when serial clock
frequency equals the system clock frequency) and the other transfers set with SCBR not equal to 1
transmit with the slowest chip select and then with the fastest one,
then an additional pulse will be generated on output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and
the others differ from 1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with baud rate = 1, the issue does not appear.
46.1.6.2 SPI: Software Reset must be Written Twice
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work properly (the clock is
enabled before the chip select.)
Problem Fix/Workaround
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly set.
46.1.6.3 SPI: Inaccurate RHR.PCS in Variable Mode
When the SPI is configured in master mode, connected to four slaves and the variable peripheral mode is
selected, the PCS field in the SPI_RDR does not accurately tell which slave the received data came from if all Chip
Selects are used consecutively.
Problem Fix/Workaround
Use DLYBCT field of the SPI Chip Select Register to include a delay between two consecutive transfers.
46.1.7 Serial Synchronous Controller (SSC)
46.1.7.1 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when start of edge
(rising or falling) of synchro with a Start Delay equal to zero.
Problem Fix/Workaround
None.
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
857
46.1.7.2 SSC: Delay on TD (transmit data signal)
When:
TCMR.START = Receive Start
TCMR.STTDLY is more than ZERO
RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge
RFMR.FSOS = None (input)
Unexpected delay from 2 to 3 system clock cycles is added to TD output. TD should be synchronized on serial
clock edge but is actually output a few cycles of SSC clock later.
Problem Fix/Workaround
None.
46.1.7.3 SSC: Data sent without any frame synchro
When SSC is configured with the following conditions:
RF is in input,
TD is synchronized on a receive START (any condition: START field = 2 to 7)
TF toggles at each start of data transfer
Transmit STTDLY = 0
Check TD and TF after a receive START
The data is sent but there is no toggle of the TF line
Problem/Fix Workaround
Transmit STTDLY must be other than 0.
46.1.7.4 SSC: Last RK Clock Cycle when RK outputs a clock during data transfer
When the SSC receiver is used with the following conditions:
the internal clock divider is used (CKS = 0 and DIV different from 0)
RK pin set as output and provides the clock during data transfer (CKO = 2)
data sampled on RK falling edge (CKI = 0)
At the end of the data, the RK pin is set in high impedance which might be seen as an unexpected clock cycle.
Problem Fix/Workaround
Enable the pull-up on RK pin.
46.1.7.5 SSC: First RK Clock Cycle when RK outputs a clock during data transfer
When the SSC receiver is used with the following conditions:
RX clock is divided clock (CKS =0 and DIV different from 0)
RK pin set as output and provides the clock during data transfer (CKO = 2)
data sampled on RK falling edge (CKI =0)
The first clock cycle time generated by the RK pin is equal to MCK /(2 x (value +1)).
Problem Fix/Workaround
None.
46.1.8 Two-wire Interface (TWI)
46.1.8.1 TWI: Software Reset
The RXRDY Flag is not reset when a software reset is performed.
Problem Fix/Workaround
None.
858
SAM9XE Series [DATASHEET]
Atmel-6254E-ATARM-SAM9XE-Datasheet_20-Nov-15
46.1.8.2 TWI: Overrun in Master Read Mode
When the shift register and the receive holding register (RHR) are full and TWI reads new data, then an overrun
error occurs.
Problem Fix/Workaround
None.
46.1.9 USB Host Port (UHP)
46.1.9.1 UHP: Non-ISO IN transfers
Conditions:
Consider the following sequence:
1.
The Host controller issues an IN token.
2.
The Device provides the IN data in a short packet.
3.
The Host controller writes the received data to the system memory.
4.
The Host controller is now supposed to carry out two Write transactions (TD status write and TD retirement
write) to the system memory in order to complete the status update.
5.
The Host controller raises the request for the first write transaction. By the time the transaction is completed,
a frame boundary is crossed.
6.
After completing the first write transaction, the Host controller skips the second write transaction.
Consequence: When this defect manifests itself, the Host controller re-attempts the same IN token.
Problem Fix/Workaround
This problem can be avoided if the system guarantees that the status update can be completed within the same
frame.
46.1.9.2 UHP: ISO OUT Transfers
Conditions:
Consider the following sequence:
1.
The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory.
2.
When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the
packet are not available. This results in a buffer underrun condition.
3.
While there is an underrun condition, if the Host controller is in the process of bit-stuffing, it causes the Host
controller to hang.
Consequence: After the failure condition, the Host controller stops sending the SOF. This causes the connected
device to go into suspend state.
Problem Fix/Workaround
This problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer.
46.1.9.3 UHP: Remote Wakeup Event
Conditions:
When a Remote Wakeup event occurs on a downstream port, the OHCI Host controller begins sending resume
signaling to the device. The Host controller is supposed to send this resume signaling for 20 ms. However, if the
driver sets the HcControl, HCFS into USBOPERATIONAL state during the resume event, then the Host controller
terminates sending the resume signal with an EOP to the device.
Consequence: If the Device does not recognize the resume (