Features
• Low-Voltage and Standard-Voltage Operation
•
•
•
•
•
•
•
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
3-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
2 MHz Clock Rate (5V)
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-lead PDIP and 8-lead JEDEC SOIC Packages
3-Wire
Serial EEPROM
Description
1K (64 x 16)
The AT93C46C provides 1024 bits of serial electrically-erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each. The device is optimized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46C is available in space saving 8lead PDIP and 8-lead JEDEC SOIC packages.
AT93C46C
The AT93C46C is enabled through the Chip Select pin (CS), and accessed via a 3wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely selftimed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is
brought “high” following the initiation of a WRITE cycle, the DO pin outputs the
READY/BUSY status of the part.
The AT93C46C is available in 2.7V to 5.5V and 2.5V to 5.5V versions.
Pin Configurations
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
NC
No Connect
DC
Don’t Connect
8-lead PDIP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
NC
GND
8-lead SOIC
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
NC
GND
Rev. 1122D–SEEPR–08/02
1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA
Block Diagram
2
AT93C46C
1122D–SEEPR–08/02
AT93C46C
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V,
TAC = 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Min
Typ
Max
Units
2.5
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC
Supply Current
ISB1
Standby Current
ISB2
READ at 1.0 MHz
0.5
2.0
mA
WRITE at 1.0 MHz
0.5
2.0
mA
VCC = 2.5V
CS = 0V
14.0
20.0
µA
Standby Current
VCC = 2.7V
CS = 0V
14.0
20.0
µA
ISB3
Standby Current
VCC = 5.0V
CS = 0V
35.0
50.0
µA
IIL
Input Leakage
VIN = 0V to VCC
0.1
1.0
µA
IOL
Output Leakage
VIN = 0V to VCC
0.1
1.0
µA
VIL1(1)
VIH1(1)
Input Low Voltage
Input High Voltage
2.5V ≤ VCC ≤ 5.5V
VCC x 0.3
VCC + 1
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
4.5V ≤ VCC ≤ 5.5V
0.4
V
VOL2
VOH2
Output Low Voltage
Output High Voltage
2.5V ≤ VCC ≤ 2.7V
Note:
VCC = 5.0V
-0.6
VCC x 0.7
IOL = 2.1 mA
IOH = -0.4 mA
2.4
IOL = 0.15 mA
IOH = -100 µA
V
0.2
VCC - 0.2
V
V
1. VIL min and VIH max are reference only and are not tested.
3
1122D–SEEPR–08/02
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
fSK
SK Clock Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
0
0
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
tSKH
SK High Time
tSKL
SK Low Time
tCS
Minimum CS Low Time
tCSS
CS Hold Time
tDIH
DI Hold Time
tPD1
CS to DO in High Impedance
tWP
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
100
100
200
ns
0
ns
100
100
200
ns
Relative to SK
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
250
250
500
ns
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
100
100
200
ns
10
ms
Write Cycle Time
4.5V ≤ VCC ≤ 5.5V
Endurance(1)
Note:
4
MHz
Relative to SK
CS to Status Valid
tDF
2
1
0.5
ns
Output Delay to ‘0’
tSV
Units
50
50
100
Output Delay to ‘1’
tPD0
Max
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
DI Setup Time
tCSH
Typ
Relative to SK
CS Setup Time
tDIS
Min
5.0V, 25°C, Page Mode
3
1M
ms
Write
Cycle
1. This parameter is characterized and is not 100% tested.
AT93C46C
1122D–SEEPR–08/02
AT93C46C
Instruction Set for the AT93C46C
Address
Instruction
SB
Op Code
x 16
READ
1
10
A5 - A 0
Reads data stored in memory, at specified address.
EWEN
1
00
11XXXX
Write enable must precede all programming modes.
ERASE
1
11
A5 - A0
Erase memory location An - A0.
WRITE
1
01
A5 - A 0
Writes memory location An - A0.
ERAL
1
00
10XXXX
Erases all memory locations. Valid only at VCC = 4.5V to 5.5V.
WRAL
1
00
01XXXX
Writes all memory locations. Valid only at VCC = 4.5V to 5.5V.
EWDS
1
00
00XXXX
Disables all programming instructions.
Functional
Description
Comments
The AT93C46C is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory Address
location.
READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic
“1” indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy Status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle, tWP.
5
1122D–SEEPR–08/02
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the
memory array to the logic “1” state and is primarily used for testing purposes. The DO
pin outputs the READY/BUSY status of the part if CS is brought high after being kept
low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ±
10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C46C
1122D–SEEPR–08/02
AT93C46C
Timing Diagrams
Synchronous Data Timing
Note:
This is the minimum SK period.
7
1122D–SEEPR–08/02
Organization Key for Timing Diagrams
AT93C46C
I/O
x 16
AN
A5
DN
D15
READ Timing
tCS
High Impedance
EWEN Timing(1)
tCS
CS
SK
DI
Note:
1
0
0
1
1
...
1. Requires a minimum of nine clock cycles.
EWDS Timing(1)
tCS
CS
SK
DI
Note:
8
1
0
0
0
0
...
1. Requires a minimum of nine clock cycles.
AT93C46C
1122D–SEEPR–08/02
AT93C46C
WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
HIGH IMPEDANCE
BUSY
READY
tWP
WRAL Timing(1)(2)
tCS
CS
SK
DI
DO
1
0
0
0
1
...
DN
...
D0
BUSY
HIGH IMPEDANCE
READY
tWP
Notes:
1. Valid only at VCC = 4.5V to 5.5V.
2. Requires a minimum of nine clock cycles.
9
1122D–SEEPR–08/02
ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
1
1
AN AN-1 AN-2
...
A0
tDF
tSV
DO
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
READY
tWP
ERAL Timing(1)
tCS
CS
CHECK
STATUS
STANDBY
tSV
tDF
SK
DI
DO
1
0
0
1
0
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
READY
tWP
Note:
10
1. Valid only at VCC = 4.5V to 5.5V.
AT93C46C
1122D–SEEPR–08/02
AT93C46C
Ordering Information
Ordering Code
Package
AT93C46C-10PI-2.7
AT93C46C-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
AT93C46C-10PI-2.5
AT93C46C-10SI-2.5
8P3
8S1
Industrial
(-40°C to 85°C)
Note:
Operation Range
For 2.7V and 2.5V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics
table.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
-2.7
Low Voltage (2.7V to 5.5V)
-2.5
Low Voltage (2.5V to 5.5V)
11
1122D–SEEPR–08/02
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
Notes:
0.210
0.100 BSC
eA
0.300 BSC
0.115
NOTE
2
3
3
e
L
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
AT93C46C
1122D–SEEPR–08/02
AT93C46C
8S1 – JEDEC SOIC
3
2
1
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
A2
C
L
SYMBOL
MIN
NOM
MAX
A
–
–
1.75
B
–
–
0.51
C
–
–
0.25
D
–
–
5.00
E
–
–
4.00
e
E
End View
NOTE
1.27 BSC
H
–
–
6.20
L
–
–
1.27
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
A
13
1122D–SEEPR–08/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Other terms and product names may be the trademarks of others.
Printed on recycled paper.
1122D–SEEPR–08/02
xM
