AT93C56B-MAHM-T

AT93C56B/AT93C66B Three-wire Serial EEPROM 2-Kbit (256 x 8 or 128 x 16) and 4-Kbit (512 x 8 or 256 x 16) Features • • • • • • • • • • Low-Voltage Operation: – VCC = 1.7V to 5.5V User-Selectable Internal Organization: – 2K: 256 x 8 or 128 x 16 – 4K: 512 x 8 or 256 x 16 Industrial Temperature Range: -40°C to +85°C Three-Wire Serial Interface Sequential Read Operation 2 MHz Clock Rate (5V) Self-Timed Write Cycle within 5 ms Maximum High Reliability: – Endurance: 1,000,000 write cycles – Data retention: 100 years Green Package Options (Lead-free/Halide-free/RoHS compliant) Die Sale Options: Wafer Form Packages • 8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN, 8-Pad XDFN and 8-Ball VFBGA © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 1 AT93C56B/AT93C66B Table of Contents Features......................................................................................................................................................... 1 Packages........................................................................................................................................................1 1. Package Types (not to scale)..................................................................................................................4 2. Pin Descriptions...................................................................................................................................... 5 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 3. Description.............................................................................................................................................. 7 3.1. 4. READ......................................................................................................................................... 12 Erase/Write Enable (EWEN)...................................................................................................... 13 Erase/Write Disable (EWDS)..................................................................................................... 13 ERASE....................................................................................................................................... 14 WRITE........................................................................................................................................14 Write All (WRAL)........................................................................................................................ 15 Erase All (ERAL)........................................................................................................................ 15 Packaging Information.......................................................................................................................... 17 6.1. 7. Absolute Maximum Ratings..........................................................................................................8 DC and AC Operating Range.......................................................................................................8 DC Characteristics....................................................................................................................... 8 AC Characteristics........................................................................................................................9 Synchronous Data Timing.......................................................................................................... 10 Electrical Specifications..............................................................................................................11 Device Commands and Addressing......................................................................................................12 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 6. Block Diagram.............................................................................................................................. 7 Electrical Characteristics.........................................................................................................................8 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 5. Chip Select (CS)...........................................................................................................................5 Serial Data Clock (SK)................................................................................................................. 5 Serial Data Input (DI)....................................................................................................................5 Serial Data Output (DO)............................................................................................................... 5 Ground (GND).............................................................................................................................. 5 Internal Organization (ORG)........................................................................................................ 6 Device Power Supply (VCC)......................................................................................................... 6 Package Marking Information.....................................................................................................17 Revision History.................................................................................................................................... 28 The Microchip Website.................................................................................................................................29 Product Change Notification Service............................................................................................................29 Customer Support........................................................................................................................................ 29 Product Identification System.......................................................................................................................30 Microchip Devices Code Protection Feature................................................................................................ 30 © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 2 AT93C56B/AT93C66B Legal Notice................................................................................................................................................. 31 Trademarks.................................................................................................................................................. 31 Quality Management System....................................................................................................................... 32 Worldwide Sales and Service.......................................................................................................................33 © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 3 AT93C56B/AT93C66B Package Types (not to scale) 1. Package Types (not to scale) 8-lead SOIC/TSSOP (Top View) 8-pad UDFN/XDFN (Top View) CS 1 8 Vcc CS 1 8 Vcc SK 2 7 NC SK 2 7 NC DI 3 6 ORG DI 3 6 ORG DO 4 5 GND DO 4 5 GND 8-ball VFBGA (Top View) © 2019 Microchip Technology Inc. CS 1 8 Vcc SK 2 7 NC DI 3 6 ORG DO 4 5 GND Datasheet DS20006260A-page 4 AT93C56B/AT93C66B Pin Descriptions 2. Pin Descriptions The descriptions of the pins are listed below in the Table 2-1. Table 2-1. Pin Function Table Name 8‑Lead SOIC 8‑Lead TSSOP 8‑Pad UDFN(1) 8-Pad XDFN 8-Ball VFBGA Function CS 1 1 1 1 1 Chip Select SK 2 2 2 2 2 Serial Data Clock DI 3 3 3 3 3 Serial Data Input DO 4 4 4 4 4 Serial Data Output GND 5 5 5 5 5 Ground ORG 6 6 6 6 6 Internal Organization NC 7 7 7 7 7 No Connect VCC 8 8 8 8 8 Device Power Supply Note:  1. The exposed pad on this package can be connected to GND or left floating. 2.1 Chip Select (CS) The Chip Select (CS) pin is used to control device selection. The AT93C56B/AT93C66B is selected when the CS pin is high. When the device is not selected, data will not be accepted via the Serial Data Input (DI) pin, and the Serial Output (DO) pin will remain in a high-impedance state. 2.2 Serial Data Clock (SK) The Serial Data Clock (SK) pin is used to synchronize the communication between a master and the AT93C56B/ AT93C66B. Instructions, addresses or data present on the Serial Data Input (DI) pin is latched in on the rising edge of SK, while output on the Serial Data Output (DO) pin is also clocked out on the rising edge of SK. 2.3 Serial Data Input (DI) The Serial Data Input (DI) pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the Serial Data Clock (SK). 2.4 Serial Data Output (DO) The Serial Data Output (DO) pin is used to transfer data out of the AT93C56B/AT93C66B. During a read sequence, data is shifted out on this pin after the rising edge of the Serial Data Clock (SK). This pin also outputs the Ready/Busy status of the part if CS is brought high after being low for a minimum of tcs and an erase or write operation has been initiated. 2.5 Ground (GND) The ground reference for the power supply. The Ground (GND) pin should be connected to the system ground. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 5 AT93C56B/AT93C66B Pin Descriptions 2.6 Internal Organization (ORG) The Internal Organization (ORG) pin is used to select between the x16 or x8 memory organizations of the device. When the ORG pin is tied to VCC, the x16 memory organization is selected. When the ORG pin is tied to VSS, the x8 memory organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 MΩ pull-up resistor, then the x16 organization is selected. 2.7 Device Power Supply (VCC) The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 6 AT93C56B/AT93C66B Description 3. Description The AT93C56B/AT93C66B provides 2,048/4,096 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 128/256 words of 16 bits each (when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low‑power and low‑voltage operations are essential. The AT93C56B/AT93C66B is available in space-saving 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN and 8-ball VFBGA packages. All packages operate from 1.7V to 5.5V. The AT93C56B/AT93C66B is enabled through the Chip Select (CS) pin and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Serial Data Clock (SK). Upon receiving a READ instruction at DI, the address is decoded, and the data is clocked out serially on the DO pin. The write cycle is completely self-timed, and no separate erase cycle is required before write. The write cycle is only enabled when the part is in the Erase/ Write Enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the Ready/ Busy status of the part. Block Diagram Memory System Control Module CS High Voltage Generation Circuit SK EEPROM Array 256/512 x 8 or 128/256 x 16 DI Row Decoder 3.1 Column Decoder Power-on Reset Generator VCC Address Register and Counter ORG Data Register Clock Generator DO GND Output Buffer Note:  When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, and the application does not load the input beyond the capability of the 10 MΩ pull-up resistor, then the x16 organization is selected. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 7 AT93C56B/AT93C66B Electrical Characteristics 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Temperature under bias -55°C to +125°C Storage temperature -65°C to +150°C VCC 6.25V Voltage on any pin with respect to ground -1.0V to +7.0V DC output current 5.0 mA Note:  Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 DC and AC Operating Range Table 4-1. DC and AC Operating Range AT93C56B/AT93C66B 4.3 Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C VCC Power Supply Low-Voltage Grade 1.7V to 5.5V DC Characteristics Table 4-2. DC Characteristics(1) Parameter Symbol Minimum Typical Maximum Units Supply Voltage VCC1 1.7 — 5.5 V Supply Voltage VCC2 2.5 — 5.5 V Supply Voltage VCC3 4.5 — 5.5 V Supply Current ICC1 — 0.5 2.0 mA VCC = 5.0V, Read at 1 MHz Supply Current ICC2 — 0.5 2.0 mA VCC = 5.0V, Write at 1 MHz Standby Current (1.7V Option) ISB1 — 0.4 1.0 μA VCC = 1.7V, CS = 0V Standby Current (2.5V Option) ISB2 — 6.0 10.0 μA VCC = 2.5V, CS = 0V Standby Current (5.0V Option) ISB3 — 10.0 15.0 μA VCC = 5.0V, CS = 0V Input Leakage Current IIL — 0.1 3.0 μA VIN = 0 to VCC Output Leakage Current ILO — 0.1 3.0 μA VIN = 0 to VCC Input Low‑Voltage VIL1 -0.6 — 0.8 V 2.5V ≤ VCC ≤ 5.5V (Note 2) © 2019 Microchip Technology Inc. Datasheet Test Conditions DS20006260A-page 8 AT93C56B/AT93C66B Electrical Characteristics ...........continued Parameter Symbol Minimum Typical Maximum Units Test Conditions Input High‑Voltage VIH1 2.0 — VCC + 1 V 2.5V ≤ VCC ≤ 5.5V (Note 2) Input Low‑Voltage VIL2 -0.6 — VCC x 0.3 V 1.7V ≤ VCC ≤ 2.5V (Note 2) Input High‑Voltage VIH2 VCC x 0.7 — VCC + 1 V 1.7V ≤ VCC ≤ 2.5V (Note 2) Output Low‑Voltage VOL1 — — 0.4 V 2.5V ≤ VCC ≤ 5.5V, IOL = 2.1 mA Output High‑Voltage VOH1 2.4 — — V 2.5V ≤ VCC ≤ 5.5V, IOH = -0.4 mA Output Low‑Voltage VOL2 — — 0.2 V 1.7V ≤ VCC ≤ 2.5V, IOL = 0.15 mA Output High‑Voltage VOH2 VCC - 0.2 — — V 1.7V ≤ VCC ≤ 2.5V, IOH = -100 µA Note:  1. 2. 4.4 Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted). VIL min and VIH max are reference only and are not tested. AC Characteristics Table 4-3. AC Characteristics(1) Parameter Symbol Minimum Typical Maximum Units fSK 0 — 2 MHz 4.5V ≤ VCC ≤ 5.5V 0 — 1 MHz 2.5V ≤ VCC ≤ 5.5V 0 — 250 kHz 1.7V ≤ VCC ≤ 5.5V 250 — — ns 2.5V ≤ VCC ≤ 5.5V 1000 — — ns 1.7V ≤ VCC ≤ 5.5V 250 — — ns 2.5V ≤ VCC ≤ 5.5V 1000 — — ns 1.7V ≤ VCC ≤ 5.5V 250 — — ns 2.5V ≤ VCC ≤ 5.5V 1000 — — ns 1.7V ≤ VCC ≤ 5.5V 50 — — ns 2.5V ≤ VCC ≤ 5.5V, Relative to SK 200 — — ns 1.7V ≤ VCC ≤ 5.5V, Relative to SK 100 — — ns 2.5V ≤ VCC ≤ 5.5V, Relative to SK 400 — — ns 1.7V ≤ VCC ≤ 5.5V, Relative to SK 0 — — ns Relative to SK Clock Frequency, SK High Time, SK Low Time, SK Minimum CS Low Time CS Setup Time DI Setup Time CS Hold Time © 2019 Microchip Technology Inc. tSKH tSKL tCS tCSS tDIS tCSH Datasheet Test Conditions DS20006260A-page 9 AT93C56B/AT93C66B Electrical Characteristics ...........continued Parameter Symbol Minimum Typical Maximum Units tDIH 100 — — ns 2.5V ≤ VCC ≤ 5.5V, Relative to SK 400 — — ns 1.7V ≤ VCC ≤ 5.5V, Relative to SK — — 250 ns 2.5V ≤ VCC ≤ 5.5V — — 1000 ns 1.7V ≤ VCC ≤ 5.5V — — 250 ns 2.5V ≤ VCC ≤ 5.5V — — 1000 ns 1.7V ≤ VCC ≤ 5.5V — — 250 ns 2.5V ≤ VCC ≤ 5.5V — — 1000 ns 1.7V ≤ VCC ≤ 5.5V, — — 150 ns 2.5V ≤ VCC ≤ 5.5V, CS = VIL — — 400 ns 1.7V ≤ VCC ≤ 5.5V, CS = VIL 0.1 3 5 ms 1.7V ≤ VCC ≤ 5.5V DI Hold Time Output Delay to 1 tPD1 Output Delay to 0 tPD0 CS to Status Valid CS to DO in High‑impedance tSV tDF Write Cycle Time tWP Test Conditions Note:  1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). 4.5 Synchronous Data Timing Figure 4-1. Synchronous Data Timing CS SK DI VIH VIL 1µs(1) tSKH tCSS tSKL VIH VIL VIH tDIS tDIH VIL tPD0 DO (Read) DO (Program) tCSH tPD1 tDF VOH VOL VOH tDF tSV Status Valid VOL Note:  1. This is the minimum SK period. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 10 AT93C56B/AT93C66B Electrical Characteristics 4.6 4.6.1 Electrical Specifications Power-Up Requirements and Reset Behavior During a power-up sequence, the VCC supplied to the AT93C56B/AT93C66B should monotonically rise from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs. 4.6.1.1 Device Reset To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the AT93C56B/AT93C66B includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby mode. The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the first command to the device. See Power-up Conditions(1) for the values associated with these power-up parameters. Table 4-4. Power-up Conditions(1) Symbol Parameter tPUP Time required after VCC is stable before the device can accept commands VPOR Power-on Reset Threshold Voltage tPOFF Minimum time at VCC = 0V between power cycles Min. Max. Units 100 － µs － 1.5 V 500 － ms Note:  1. These parameters are characterized but they are not 100% tested in production. If an event occurs in the system where the VCC level supplied to the AT93C56B/AT93C66B drops below the maximum VPOR level specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up sequence in compliance with the requirements defined in this section. 4.6.2 Pin Capacitance Table 4-5. Pin Capacitance(1) Symbol COUT CIN Test Condition Max. Units Conditions Output Capacitance (DO) 5 pF VOUT = 0V Input Capacitance (CS, SK, DI, ORG) 5 pF VIN = 0V Note:  1. This parameter is characterized but is not 100% tested in production. 4.6.3 EEPROM Cell Performance Characteristics Table 4-6. EEPROM Cell Performance Characteristics Operation Write Endurance(1) Data Retention(1) Test Condition TA = 25°C, VCC = 5.0V TA = 55°C Min. Max. Units 1,000,000 — Write Cycles 100 — Years Note:  1. Performance is determined through characterization and the qualification process. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 11 AT93C56B/AT93C66B Device Commands and Addressing 5. Device Commands and Addressing The AT93C56B/AT93C66B is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of CS and consists of a Start bit (SB), followed by the appropriate opcode, and the desired memory address location. Table 5-1. AT93C56B/AT93C66B Instruction Set Instruction SB Opcode Address Data X8(1) X16(1) X8 Comments X16 READ 1 10 A8‑A0 A7‑A0 Reads data stored in memory at specified address. EWEN 1 00 11XXXXXXX 11XXXXXX Write Enable must precede all programming modes. ERASE 1 11 A8‑A0 A7‑A0 Erases memory location AN‑A0. WRITE 1 01 A8‑A0 A7‑A0 ERAL 1 00 10XXXXXXX 10XXXXXX WRAL 1 00 01XXXXXXX 01XXXXXX EWDS 1 00 00XXXXXXX 00XXXXXX D7‑D0 D15‑D0 Writes memory location AN‑A0. Erases all memory locations. Valid only at VCC3. See Table 4-2. D7‑D0 D15‑D0 Writes all memory locations. Valid only at VCC3. See Table 4-2. Disables all programming instructions. Note:  1. The ‘X’ in the address field represents a “don’t care” bit and must be sent to the device. Table 5-2. Organization Key for Timing Diagrams I/O AT93C56B (2K) AT93C66B (4K) x8 x16 x8 x16 AN A8(1) A7(2) A8 A7 DN D7 D15 D7 D15 Note:  1. A8 is a “don’t care” value, but the extra clock is required. 2. A7 is a “don’t care” value, but the extra clock is required. 5.1 READ The READ instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the DO pin. Output data changes are synchronized with the rising edges of the SK pin. The AT93C56B/AT93C66B supports sequential read operations. The device will automatically increment the internal Address Pointer and clock out the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (Logic ‘0’) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. Note:  A dummy bit (logic ‘0’) precedes the initial 8-bit or 16-bit data output string. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 12 AT93C56B/AT93C66B Device Commands and Addressing Figure 5-1. READ Timing tCS CS SK DI DO 5.2 1 1 0 AN A0 High-impedance 0 DN D0 Erase/Write Enable (EWEN) To ensure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Note:  Once in the write enabled state, programming remains enabled until an EWDS instruction is executed, or VCC power is removed from the part. Figure 5-2. EWEN Timing tCS CS SK DI 5.3 1 0 0 1 1 ... Erase/Write Disable (EWDS) To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 13 AT93C56B/AT93C66B Device Commands and Addressing Figure 5-3. EWDS Timing tCS CS SK DI 5.4 1 0 0 0 0 ... ERASE The ERASE instruction programs all bits in the specified memory location to the logic ‘1’ state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A logic ‘1’ at the DO pin indicates that the selected memory location has been erased, and the part is ready for another instruction. Figure 5-4. ERASE Timing tCS Standby Check Status CS SK DI 1 1 1 AN AN-1 AN-2 ... A0 tDF tSV DO High-impedance High-impedance Busy Ready tWP 5.5 WRITE The WRITE instruction contains the 8 bits or 16 bits of data to be written into the specified memory location. The selftimed programming cycle, tWP, starts after the last bit of data is received at DI pin . The DO pin outputs the Ready/ Busy status of the part if CS is brought high after being kept low for a minimum of tCS. A logic ‘0’ at DO indicates that programming is still in progress. A logic ‘1’ indicates that the memory location at the specified address has been written with the data pattern contained in the instruction, and the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the end of the self-timed programming cycle, tWP. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 14 AT93C56B/AT93C66B Device Commands and Addressing Figure 5-5. WRITE Timing tCS Check Status CS Standby SK 1 DI 0 1 ... AN A0 DN ... D0 tSV High-impedance DO tDF Busy Ready tWP 5.6 Write All (WRAL) The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. Note:  The WRAL instruction is valid only at VCC3 (see Table 4-2). Figure 5-6. WRAL Timing tCS Check Status CS Standby SK DI DO 1 0 0 0 1 ... DN ... D0 tDF tSV High-impedance Busy Ready tWP 5.7 Erase All (ERAL) The Erase All (ERAL) instruction programs every bit in the memory array to the logic ‘1’ state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of tCS. Note:  The ERAL instruction is valid only at VCC3 (see Table 4-2). © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 15 AT93C56B/AT93C66B Device Commands and Addressing Figure 5-7. ERAL Timing tCS Standby Check Status CS SK DI 1 0 0 1 0 tDF tSV DO High-impedance Busy High-impedance Ready tWP © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 16 AT93C56B/AT93C66B Packaging Information 6. Packaging Information 6.1 Package Marking Information AT93C56B and AT93C66B: Package Marking Information 8-lead TSSOP 8-lead SOIC 8-pad XDFN 1.8 x 2.2 mm Body ATMLHYWW ###% CO YYWWNNN ### NNN ATHYWW ###%CO YYWWNNN 8-pad UDFN 8-ball VFBGA 2.0 x 3.0 mm Body 1.5 x 2.0 mm Body ### H% NNN Note 1: ###U WNNN designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT93C56B Truncation Code ###: 56B AT93C66B Truncation Code ###: 66B Date Codes YY = Year 16: 2016 17: 2017 18: 2018 19: 2019 Voltages 20: 2020 21: 2021 22: 2022 23: 2023 Y = Year 6: 2016 7: 2017 8: 2018 9: 2019 0: 2020 1: 2021 2: 2022 3: 2023 WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Country of Origin Device Grade CO = Country of Origin H or U: Industrial Grade % = Minimum Voltage M: 1.7V min Atmel Truncation AT: Atmel ATM: Atmel ATML: Atmel Lot Number or Trace Code NNN = Alphanumeric Trace Code © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 17 AT93C56B/AT93C66B Packaging Information 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 2 1 e B NOTE 5 NX b 0.25 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 18 AT93C56B/AT93C66B Packaging Information 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L L1 Footprint Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 19 AT93C56B/AT93C66B Packaging Information 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 20 M AT93C56B/AT93C66B Packaging Diagrams and Parameters Packaging Information 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 1.20 Overall Width E Molded Package Width E1 4.30 6.40 BSC 4.40 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint L1 4.50 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-086B © 2007 Microchip Technology Inc. © 2019 Microchip Technology Inc. DS00049AR-page 117 Datasheet DS20006260A-page 21 M Note: AT93C56B/AT93C66B Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 96 © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 22 AT93C56B/AT93C66B Packaging Information 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN] Atmel Legacy YNZ Package Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) E (DATUM B) NOTE 1 2X 0.10 C 1 2 2X 0.10 C TOP VIEW A1 0.10 C C SEATING PLANE A 8X (A3) SIDE VIEW 0.10 0.08 C C A B D2 e 2 1 2 0.10 E2 C A B K N L 8X b 0.10 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 23 AT93C56B/AT93C66B Packaging Information 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN] Atmel Legacy YNZ Package Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Notes: Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 Terminal Thickness A3 Overall Length D Exposed Pad Length D2 Overall Width E Exposed Pad Width E2 b Terminal Width Terminal Length L Terminal-to-Exposed-Pad K MIN 0.50 0.00 1.40 1.20 0.18 0.35 0.20 MILLIMETERS NOM 8 0.50 BSC 0.55 0.02 0.152 REF 2.00 BSC 1.50 3.00 BSC 1.30 0.25 0.40 - MAX 0.60 0.05 1.60 1.40 0.30 0.45 - 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 24 AT93C56B/AT93C66B Packaging Information 8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN] Atmel Legacy YNZ Package Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X2 EV G2 8 ØV C Y2 G1 Y1 1 2 SILK SCREEN X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 Contact Pad to Center Pad (X8) G1 Contact Pad to Contact Pad (X6) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 1.60 1.40 2.90 0.30 0.85 0.20 0.33 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-21355-Q4B Rev A © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 25 AT93C56B/AT93C66B Packaging Information D 7 8 6 5 E PIN #1 ID 2 1 3 4 A1 Top View A Side View e1 b L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – 0.40 A1 0.00 – 0.05 D 1.70 1.80 1.90 E 2.10 2.20 2.30 b 0.15 0.20 0.25 0.10 PIN #1 ID 0.15 b e e 0.40 TYP e1 L End View NOTE 1.20 REF 0.26 0.30 0.35 9/10/2012 TITLE GPC DRAWING NO. REV. 8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN (XDFN) DTP 8ME1 B Note:  For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 26 AT93C56B/AT93C66B Packaging Information 0.10 d (4X) 0.08 C d f E 0.10 C A C D 2. b j j PIN 1 BALL PAD CORNER n 0.15 m C A B n 0.08m C A1 B A2 TOP VIEW PIN 1 BALL PAD CORNER 3 2 1 A SIDE VIEW 4 d (d1) 8 7 6 5 COMMON DIMENSIONS (Unit of Measure - mm) e (e1) BOTTOM VIEW 8 SOLDER BALLS Notes: 1. This drawing is for general information only. SYMBOL MIN NOM MAX A 0.73 0.79 0.85 A1 0.09 0.14 0.19 A2 0.40 0.45 0.50 b 0.20 0.25 0.30 D 2. Dimension ‘b’ is measured at maximum solder ball diameter. 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu. NOTE 2 1.50 BSC E 2.0 BSC e 0.50 BSC e1 0.25 REF d 1.00 BSC d1 0.25 REF 7/1/14 TITLE GPC DRAWING NO. 8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GXU 8U3-1 REV. G Note:  For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 27 AT93C56B/AT93C66B Revision History 7. Revision History Revision A (October 2019) Updated to the Microchip template. Microchip DS20006260 replaces Atmel document 8735. Updated Package Marking Information. Removed lead finish designation. Updated trace code format in package markings. Updated section content throughout for clarification. Updated 8U3-1 VFBGA package drawing. Updated the SOIC, TSSOP, UDFN package drawings to Microchip format Atmel 8735 Revision C (January 2015) Added the UDFN extended quantity option and update package outline drawings. Update the 8MA2 package drawing. Atmel 8735 Revision B (April 2013) Corrected Synchronous Data Timing figure and removed note. Updated TSSOP package option from 8A2 to 8X. Updated UDFN package option from 8Y6 to 8MA2. Updated template and Atmel logos. Atmel 8735 Revision A (January 2011) Initial document release. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 28 AT93C56B/AT93C66B The Microchip Website Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files and information easily available to customers. Some of the content available includes: • • • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip design partner program member listing Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Product Change Notification Service Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will receive email notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, go to http://www.microchip.com/pcn and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Embedded Solutions Engineer (ESE) Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: http://www.microchip.com/support © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 29 AT93C56B/AT93C66B Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. AT 9 3 C 5 6 B - S S H M - B Shipping Carrier Option B = Bulk T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Extended Quantity Option Product Family 93C = Microwire-compatible Three-Wire Serial EEPROM Operating Voltage M = 1.7V to 5.5V Device Density 56 = 2-Kilobit 66 = 4-Kilobit Package Device Grade or Wafer/Die Thickness H or U = Industrial Temperature Range (-40°C to +85°C) 11 = 11mil Wafer Thickness Device Revision Package Option SS = SOIC X = TSSOP MA = 2.0mm x 3.0mm UDFN ME = 1.5mm x 2.0mm XDFN C = VFBGA WWU = Wafer Unsawn Note: Refer to the automotive data sheet for automotive grade ordering information. Examples Package Package Drawing Code Package Option Shipping Carrier Option Device Grade AT93C56B‑SSHM‑B SOIC SN SS Bulk (Tubes) AT93C66B‑SSHM‑T SOIC SN SS Tape and Reel Industrial Temperature (-40°C to 85°C) AT93C66B‑XHM‑B TSSOP ST X Bulk (Tubes) AT93C56B‑XHM‑T TSSOP ST X Tape and Reel AT93C66B‑MAHM‑T UDFN Q4B MA Tape and Reel AT93C56B‑MAHM‑E UDFN Q4B MA Extended Qty., Tape and Reel AT93C56B‑MEHM‑T XDFN 8ME1 ME Tape and Reel VFBGA 8U3-1 C Tape and Reel Device AT93C56B‑CUM‑T Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 30 AT93C56B/AT93C66B • • Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-5168-6 © 2019 Microchip Technology Inc. Datasheet DS20006260A-page 31 AT93C56B/AT93C66B AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Quality Management System For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality. © 2019 Microchip Technology Inc. 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Datasheet DS20006260A-page 33