Features
• High Performance, Low Power Atmel AVR 8-bit Microcontroller
• Advanced RISC Architecture
– 123 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 16Kbyte of In-system Programmable (ISP) Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 512Bytes In-system Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512Bytes Internal SRAM
– Programming Lock for Self-programming Flash Program and EEPROM Data
Security
– Low Size LIN/UART Software In-system Programmable
• Peripheral Features
– LF-RFID Reader/Writer Front End
• Carrier Frequency fOSC = 100kHz to 150kHz
• Typical Data Rate up to 5Kbaud at 125kHz
• Suitable for Manchester anf Biphase Modulation
• Does not Require an External Crystal
• Power Supply from the Car Battery or from 5V Regulated Voltage
• Optimized for Car Immobilizer Applications
• Tuning Capability
– LIN 2.1 and 1.3 Controller or 8-bit UART
– 8-bit Asynchronous Timer/Counter 0:
• 10-bit Clock Prescaler
• 1 Output Compare or 8-bit PWM Channel
– 16-bit Synchronous Timer/Counter 1:
• 10-bit Clock Prescaler
• External Event Counter
• 2 Output Compares Units or 16-bit PWM Channels each Driving up to 4 Output
Pins
– Master/Slave SPI Serial Interface
– Universal Serial Interface (USI) with Start Condition Detector (Master/Slave SPI,
TWI, ...)
– 10-bit ADC:
• 11 Single-ended Channels
• 8 Differential ADC Channel Pairs with Programmable Gain (8x or 20x)
– On-chip Analog Comparator with Selectable Voltage Reference
– 100µA ±10% Current Source (LIN Node Identification)
– On-chip Temperature Sensor
– Programmable Watchdog Timer with Separate On-chip Oscillator
125kHz LF
Reader/Writer
with Integrated
Atmel AVR
Microcontroller
Atmel ATA5505
Preliminary
9219A–RFID–01/11
• Special Microcontroller Features
– Dynamic Clock Switching (External/Internal RC/Watchdog Clock) for Power Control, EMC Reduction
– DebugWIRE On-chip Debug (OCD) System
– Hardware In-System Programmable (ISP) via SPI Port
– External and Internal Interrupt Sources
– Interrupt and Wake-up on Pin Change
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated RC Oscillator 8MHz
– 4-16 MHz and 32 KHz Crystal/Ceramic Resonator Oscillators
• Operating Voltage:
– 7 to 16V
– 4.5 to 5.5V Internal Voltage Regulator available for Digital and Logic
• Operating Temperature: –40°C to +85°C
Applications
•
•
•
•
•
•
•
•
2
Access Control Units
Animal Identification
Component Authetication
Brand Protection
Automation
Industrial
Waste Management
Process Control
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
1. Description
The Atmel® ATA5505 is an Atmel AVR® microcontroller with LF-RFID reader/writer front end
and LIN interface for low cost network applications.
The Atmel ATA5505 incorporates the energy-transfer circuit for supplying the transponder. It
consists of an on-chip power supply, an oscillator, and a coil driver optimized for automotive-specific distances. It also includes all signal-processing circuits which are necessary to
transform the small input signal into a microcontroller-compatible signal.
The Atmel ATA5505 integrates a low-power CMOS 8-bit microcontroller based on the Atmel
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATA5505 achieves throughputs approaching 1 MIPS per MHz, allowing the system
designer to optimize power consumption versus processing speed.
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in a single instruction executed in one clock cycle. The
resulting architecture is more code-efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The Atmel ATA5505 provides the following features: 16K byte of in-system programmable
Flash, 512bytes EEPROM, 512bytes SRAM, 16 general purpose I/O lines, 32 general purpose
working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed
timer/counter, a universal serial interface, a LIN controller, internal and external interrupts, an
11-channel, 10-bit ADC, a programmable watchdog timer with internal oscillator, and three
software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, timer/counter, ADC, analog comparator, and interrupt system to continue functioning.
Power-down mode saves the register contents, disabling all chip functions until the next interrupt or hardware reset. To minimize switching noise during ADC conversions, ADC noise
reduction mode stops the CPU and all I/O modules except ADC,
The device is manufactured using Atmel’s high-density non-volatile memory technology. The
on-chip ISP Flash allows the program memory to be re-programmed in-system via an SPI
serial interface, by a conventional non-volatile memory programmer or by an on-chip boot
code running on the Atmel AVR core. The boot program can use any interface to download the
application program in the Flash memory. By combining an 8-bit RISC CPU with in-system
self-programmable Flash on a monolithic chip, the Atmel ATA5505 is a powerful microcontroller providing a highly flexible and cost-effective solution to many embedded control
applications.
The Atmel ATA5505 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debuggers/simulators, in-circuit
emulators, and evaluation kits.
3
9219A–RFID–01/11
1.1
System Block Diagram
The system block diagram for a stand alone reader application is shown in Figure 1-1. No
additional microcontroller is required..
Figure 1-1.
System Block Diagram - Stand Alone Reader
Atmel ATA5505
T/ATA5551
ATA5557/67
ATA5577
ATA5558
ATA5575
Q5
Osc
MCU
Core
SPI
Frontend
NF
Read Channel
Successor
Immobilizer
Stack
A system block diagram for a reader station application with a LIN transceiver IC is shown in
Figure 1-2. The reader is then communicating with a central unit.
Figure 1-2.
System Block Diagram - Reader with LIN Connection
Reader
Atmel ATA5505
T/ATA5551
ATA5557/67
ATA5577
ATA5558
ATA5575
Q5
Osc
MCU
Core
LIN
UART
LIN
Frontend
NF
Read Channel
Immobilizer
Stack
TRx
Central
Unit
Successor
All Atmel® LF-RFID tag ICs can be read by the ATA5505: e5530, TK5530, e5551, T5551,
TK5551, e5552, TK5552, e5554, T5555, Q5, T5557, ATA5567, ATA5558, T5561, TK5561,
ATA5577, ATA5575.
1.2
Block Diagram
In Figure 1-3 on page 5 the basic architecture of the Atmel ATA5505 consisting of the Atmel
AVR and the front end is shown. The Atmel AVR is a low-power CMOS 8-bit microcontroller
with RISC architecture. The Atmel AVR includes several features. The main features are
in-system programmable Flash, EEPROM, SRAM, Ports A and B as general purpose I/O
lines, a timer and a LIN controller. The details of the front end are shown in Figure 1-4 on page
5.
4
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 1-3.
Block Diagram
GND
VCC
Atmel ATA5505
Watchdog
Power / Reset
EEPROM
Flash
SRAM
AVCC
A/D
converter
Timer
AVR CPU
AGND
Input
Control (0 to 3)
SPI
Reader Frontend
Port B
Port A
PB (0 to 7)
PA (0 to 7)
COIL1
COIL2
DGND
Input
LIN / UART
Figure 1-4 shows the front end in more detail. The circuit block depicted consists of the
receiver, an internal oscillator and driver for the coil, and a power supply unit.
Figure 1-4.
Reader Front End Block Diagram
DVS
VEXT
VS
VBatt
Frontend
Standby
Power supply
Driver
=1
COIL1
MS
Control (0 to 3)
CFE
&
COIL2
Oscillator
Frequency
adjustment
RF
DGND
Output
Input
Lowpass filter
&
Schmitt trigger
OE
HIPASS
5
9219A–RFID–01/11
Pin Configuration
PA5
PA6
PA7
PB7/RST
PB6
PB5
PB4/XTAL
VDD
OUTPUT
OE
INPUT
MS
GND
GND
PA2
PA3
AVCC
Pinout Atmel® ATA5505 - QFN38 5 mm by 7 mm
PA4
Figure 1-5.
AGND
1.3
38 37 36 35 34 33 32
1
31
2
30
3
29
4
28
5
27
Atmel
ATA5505
6
7
26
25
8
24
9
23
10
22
11
21
12
20
GND
PA1
PA0
PB0
PB1
PB2
PB3
RF
GAIN
VS
STBY
VBAT
GND
DVS
VEXT
COIL1
Pin Description
Table 1-1.
6
COIL2
CFE
1.4
DGND
13 14 15 16 17 18 19
Pin Description
Pin
Symbol
Function
1
PA5
PCINT5
ADC5
T1
USCK
SCL
SCK
GPIO Port A – Pin 5
PCINT5 (Pin Change Interrupt 5)
ADC5 (ADC Input Channel 5)
T1 (Timer/Counter1 Clock Input)
USCK (Three-wire Mode USI Alternate Clock Input)
SCL (Two-wire Mode USI Alternate Clock Input)
SCK (SPI Master Clock)
2
PA6
PCINT6
ADC6
AIN0
SS
GPIO Port A – Pin 6
PCINT6 (Pin Change Interrupt 6)
ADC6 (ADC Input Channel 6)
AIN0 (Analog Comparator Negative Input)
SS (SPI Slave Select Input)
3
PA7
PCINT7
ADC7
AIN1
XREF
AREF
GPIO Port A – Pin 7
PCINT7 (Pin Change Interrupt 7)
ADC7 (ADC Input Channel 7)
AIN1 (Analog Comparator Positive Input)
XREF (Internal Voltage Reference Output)
AREF (External Voltage Reference Input)
4
PB7
PCINT15
ADC10
OC1BX
RESET
dW
GPIO Port B – Pin 7
PCINT15 (Pin Change Interrupt 15)
ADC10 (ADC Input Channel 10)
OC1BX (Output Compare and PWM Output B-X for Timer/Counter1)
RESET (Reset input pin)
dW (debugWIRE I/O)
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Table 1-1.
Pin Description
Pin
Symbol
Function
5
PB6
PCINT14
ADC9
OC1AX
INT0
GPIO Port B – Pin 6
PCINT14 (Pin Change Interrupt 14)
ADC9 (ADC Input Channel 9)
OC1AX (Output Compare and PWM Output A-X for Timer/Counter 1)
INT0 (External Interrupt0 Input)
6
PB5
PCINT13
ADC8
OC1BW
XTAL2
CLKO
GPIO Port B – Pin 5
PCINT13 (Pin Change Interrupt 13)
ADC8 (ADC Input Channel 8)
OC1BW (Output Compare and PWM Output B-W for Timer/Counter 1)
XTAL2 (Chip Clock Oscillator Pin 2)
CLKO (System Clock Output)
7
PB4
PCINT12
OC1AW
XTAL1
CLKI
GPIO Port B – Pin 4
PCINT12 (Pin Change Interrupt 12)
OC1AW (Output Compare and PWM Output A-W for Timer/Counter 1)
XTAL1 (Chip clock Oscillator pin 1)
CLKI (External Clock Input)
8
VDD
9
OUTPUT
10
OE
11
INPUT
12
MS
Atmel® AVR® Supply Voltage
Reader Data Output
Reader Station Data Output Enable
Reader Station Data Input
Reader Station Mode Select
13
CFE
14
DGND
Digital Ground (Driver Ground)
Reader Station: Carrier Frequency Enable
15
COIL 2
Reader Coil Driver 2
16
COIL 1
Reader Coil Driver 1
17
VEXT
Reader External Power Supply
18
DVS
Reader Driver Supply Voltage
19
GND
Ground
20
VBATT
21
STANDBY
Battery Voltage for Reader
Front End Standby Input
22
VS
23
HIPASS
Internal Power Supply (5V) for Reader
24
RF
25
PB3
PCINT11
OC1BV
GPIO Port B - Pin 3
PCINT11 (Pin Change Interrupt 11)
OC1BV (Output Compare and PWM Output B-V for Timer/Counter 1)
26
PB2
PCINT10
OC1AV
USCK
SCL
GPIO Port B – Pin 2
PCINT10 (Pin Change Interrupt 10)
OC1AV (Output Compare and PWM Output A-V for Timer/Counter 1)
USCK (Three-wire Mode USI Default Clock Input)
SCL (Two-wire Mode USI Default Clock Input)
27
PB1
PCINT9
OC1BU
DO
GPIO Port B – Pin 1
PCINT9 (Pin Change Interrupt 9)
OC1BU (Output Compare and PWM Output B-U for Timer/Counter 1)
DO (Three-wire Mode USI Default Data Output)
HIPASS DC Decoupling (Gain)
Frequency Adjustment
7
9219A–RFID–01/11
Table 1-1.
8
Pin Description
Pin
Symbol
Function
28
PB0
PCINT8
OC1AU
DI
SDA
GPIO Port B – Pin 0
PCINT8 (Pin Change Interrupt 8)
OC1AU (Output Compare and PWM Output A-U for Timer/Counter 1)
DI (Three-wire Mode USI Default Data Input)
SDA (Two-wire Mode USI Default Data Input / Output)
29
PA0
PCINT0
ADC0
RXD
RXLIN
GPIO Port A – Pin 0
PCINT0 (Pin Change Interrupt 0)
ADC0 (ADC Input Channel 0)
RXD (UART Receive Pin)
RXLIN (LIN Receive Pin)
30
PA1
PCINT1
ADC1
TXD
TXLIN
GPIO Port A – Pin 1
PCINT1 (Pin Change Interrupt 1)
ADC1 (ADC Input Channel 1)
TXD (UART Transmit Pin)
TXLIN (LIN Transmit Pin)
31
GND
Ground
32
GND
Ground
33
GND
Ground
34
PA2
PCINT2
ADC2
OCA0A
DO
MISO
GPIO Port A – Pin 2
PCINT2 (Pin Change Interrupt 2)
ADC2 (ADC Input Channel 2)
OC0A (Output Compare and PWM Output A for Timer/Counter 0)
DO (Three-wire Mode USI Alternate Data Output)
MISO (SPI Master Input/Slave Output)
35
PA3
PCINT3
ADC3
ISRC
INT1
GPIO Port A – Pin 3
PCINT3 (Pin Change Interrupt 3)
ADC3 (ADC Input Channel 3)
ISRC (Current Source Pin)
INT1 (External Interrupt1 Input)
36
AVCC
37
AGND
38
PA4
PCINT4
ADC4
ICP1
DI
SDA
MOSI
Analog Supply Voltage
Analog Ground
GPIO Port A – Pin 4
PCINT4 (Pin Change Interrupt 4)
ADC4 (ADC Input Channel 4)
ICP1 (Timer/Counter 1 Input Capture Trigger)
DI (Three-wire Mode USI Alternate Data Input)
SDA (Two-wire Mode USI Alternate Data Input/Output)
MOSI (SPI Master Output/Slave Input)
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
1.4.1
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
The Port A output buffers have symmetrical drive characteristics with both high sink and
source capability. As inputs, Port A pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running. Port A also serves the functions of various special features of the microcontroller.
1.4.2
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
The Port B output buffers have symmetrical drive characteristics with both high sink and
source capability. As inputs, Port B pins that are pulled low externally will source current if the
pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes
active, even if the clock is not running. Port B also serves the functions of various special features of the microcontroller.
1.4.3
RESET
Device reset
1.4.4
1.5
XTAL1 and XTAL2
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip oscillator. Either a quartz crystal or a ceramic resonator may
be used.
Atmel AVR Description
The microcontroller is a low-power CMOS 8-bit microcontroller based on the Atmel® AVR®
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
microcontroller achieves throughputs approaching 1MIPS per MHz, allowing the system
designer to optimize power consumption versus processing speed.
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in a single instruction executed in one clock cycle. The
resulting architecture is more code-efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The microcontroller provides the following features: 16K byte of in-system programmable
Flash, 512bytes EEPROM, 512bytes SRAM, 16 general purpose I/O lines, 32 general purpose
working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed
timer/counter, a universal serial interface, a LIN controller, internal and external interrupts, an
11-channel, 10-bit ADC, a programmable watchdog timer with internal oscillator, and three
software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, timer/counter, ADC, analog comparator, and interrupt system to continue functioning.
Power-down mode saves the register contents, disabling all chip functions until the next interrupt or hardware reset. To minimize switching noise during ADC conversions, ADC noise
reduction mode stops the CPU and all I/O modules except ADC.
9
9219A–RFID–01/11
The device is manufactured using Atmel®’s high- density non-volatile memory technology. The
on-chip ISP Flash allows the program memory to be re-programmed In-system through via an
SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot
code running on the Atmel AVR® core. The boot program can use any interface to download
the application program in the Flash memory. By combining an 8-bit RISC CPU with In-system
self-programmable Flash on a monolithic chip, the Atmel ATA5505 is a powerful microcontroller that provides a highly flexible and cost- effective solution to many embedded control
applications.
The embedded microcontroller is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debuggers/simulators,
in-circuit emulators, and evaluation kits.
1.6
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download at http://www.atmel.com/avr.
1.7
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts
of the device. These code examples assume that the part-specific header file is included
before compilation. Be aware that not all C compiler vendors include bit definitions in the
header files and interrupt handling in C is compiler-dependent. Please consult the C compiler
documentation for more details.
10
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
2. AVR CPU Core
2.1
Overview
This section discusses the Atmel® AVR® core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.
Figure 2-1.
Block Diagram of the Atmel AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
Interrupt
Unit
32 x 8
General
Purpose
Registrers
Instruction
Register
Instruction
Decoder
Indirect Addressing
A.D.C.
Direct Addressing
Control Lines
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the Atmel AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the
next instruction is pre-fetched from the Program memory. This concept enables instructions to
be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash
memory. The fast-access Register File contains 32 x 8-bit general purpose working registers
with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File, the
operation is executed, and the result is stored back in the Register File – in one clock cycle.
11
9219A–RFID–01/11
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant
and a register. Single register operations can also be executed in the ALU. After an arithmetic
operation, the Status Register is updated to reflect information about the result of the
operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most Atmel® AVR® instructions have a single 16-bit
word format. Every Program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on
the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the
Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are
executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM
can easily be accessed through the five different addressing modes supported in the Atmel
AVR architecture.
The memory spaces in the Atmel AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
2.2
ALU – Arithmetic Logic Unit
The high-performance Atmel AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. See the “Instruction Set” section for a detailed description.
2.3
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using
the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
12
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
2.3.1
SREG – Atmel AVR Status Register
The Atmel® AVR® Status Register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers. If the Global Interrupt
Enable Register is cleared, none of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and
is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and
cleared by the application with the SEI and CLI instructions, as described in the instruction set
reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by
the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by
the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
13
9219A–RFID–01/11
2.4
General Purpose Register File
The Register File is optimized for the Atmel® AVR® Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 2-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 2-2.
Atmel AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 2-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
2.4.1
14
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These
registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 2-3 on page 15.
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
Figure 2-3.
The X-, Y-, and Z-registers
15
X-register
XH
XL
7
0
R27 (0x1B)
YH
YL
7
0
R29 (0x1D)
Z-register
0
R26 (0x1A)
15
Y-register
0
7
0
7
0
R28 (0x1C)
15
ZH
7
0
ZL
0
7
R31 (0x1F)
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for
details).
2.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always
points to the top of the Stack. Note that the Stack is implemented as growing from higher
memory locations to lower memory locations. This implies that a Stack PUSH command
decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program
before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be
set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto
the Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by
one when data is popped from the Stack with the POP instruction, and it is incremented by two
when data is popped from the Stack with return from subroutine RET or return from interrupt
RETI.
The Atmel® AVR® Stack Pointer is implemented as two 8-bit registers in the I/O space. The
number of bits actually used is implementation dependent. Note that the data space in some
implementations of the Atmel AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present
2.5.1
SPH and SPL – Stack Pointer Register
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISRAM end (See Table 3-1 on page 19)
15
9219A–RFID–01/11
2.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The
Atmel® AVR® CPU is driven by the CPU clock clkCPU, directly generated from the selected
clock source for the chip. No internal clock division is used.
Figure 2-4 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 2-4.
The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 2-5 shows the internal timing concept for the Register File. In a single clock cycle an
ALU operation using two register operands is executed, and the result is stored back to the
destination register.
Figure 2-5.
Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
2.7
Reset and Interrupt Handling
The Atmel AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in Section 7. “Interrupts” on page 63.
The list also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
16
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
2.7.1
Interrupt behavior
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All
enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set
when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt
Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur
while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set
and remembered until the Global Interrupt Enable bit is set, and will then be executed by order
of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before
the interrupt is enabled, the interrupt will not be triggered.
When the Atmel® AVR® exits from an interrupt, it will always return to the main program and
execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine,
nor restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously
with the CLI instruction. The following example shows how this can be used to avoid interrupts
during the timed EEPROM write sequence.
Assembly Code Example
in
cli
r16, SREG
; store SREG value
; disable interrupts during timed sequence
sbi
EECR, EEMPE
sbi
EECR, EEPE
out
SREG, r16
; start EEPROM write
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
