Features
• Frequency Receiving Range of (3 Versions)
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•
•
•
•
•
•
•
•
•
•
•
•
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•
– f0 = 312.5 MHz to 317.5 MHz or
– f0 = 431.5 MHz to 436.5 MHz or
– f0 = 868 MHz to 870 MHz
30 dB Image Rejection
Receiving Bandwidth
– BIF = 300 kHz for 315 MHz/433 MHz Version
– BIF = 600 kHz for 868 MHz Version
Fully Integrated LC-VCO and PLL Loop Filter
Very High Sensitivity with Power Matched LNA
– ATA5723/ATA5724:
–107 dBm, FSK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
–113 dBm, ASK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
– ATA5728:
–105 dBm, FSK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
–111 dBm, ASK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3
High System IIP3
– –18 dBm at 868 MHz
– –23 dBm at 433 MHz
– –24 dBm at 315 MHz
System 1-dB Compression Point
– –27.7 dBm at 868 MHz
– –32.7 dBm at 433 MHz
– –33.7 dBm at 315 MHz
High Large-signal Capability at GSM Band (Blocking –33 dBm at +10 MHz,
IIP3 = –24 dBm at +20 MHz)
Logarithmic RSSI Output
XTO Start-up with Negative Resistor of 1.5 kΩ
5V to 20V Automotive Compatible Data Interface
Data Clock Available for Manchester and Bi-phase-coded Signals
Programmable Digital Noise Suppression
Low Power Consumption Due to Configurable Polling
Temperature Range –40°C to +105°C
ESD Protection 2 kV HBM, All Pins
Communication to Microcontroller Possible using a Single Bi-directional Data Line
Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements
Supply Voltage Range 4.5V to 5.5V
UHF ASK/FSK
Receiver
ATA5723
ATA5724
ATA5728
Benefits
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Low BOM List Due to High Integration
Use of Low-cost 13 MHz Crystal
Lowest Average Current Consumption for Application Due to Self Polling Feature
Reuse of ATA5743 Software
World-wide Coverage with One PCB Due to 3 Versions are Pin Compatible
9106E–RKE–07/08
1. Description
The ATA5723/ATA5724/ATA5728 is a multi-chip PLL receiver device supplied in an SSO20
package. It has been specially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBit/s to 10 kBbit/s in Manchester or Bi-phase code. Its main
applications are in the areas of keyless entry systems, tire pressure monitoring systems, telemetering, and security technology systems. It can be used in the frequency receiving range of
f0 = 312.5 MHz to 317.5 MHz, f0 = 431.5 MHz to 436.5 MHz or f0 = 868 MHz to 870 MHz for
ASK or FSK data transmission. All the statements made below refer to 315 MHz, 433 MHz and
868.3 MHz applications.
Figure 1-1.
System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
T5750/53/54
XTO
ATA5723/
ATA5724/
ATA5728 Demod.
Microcontroller
PLL
Antenna
IF Amp
Antenna
VCO
Power
amp.
2
1 to 5
Control
PLL
LNA
XTO
VCO
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 1-2.
Block Diagram
FSK/ASK
Demodulator
and Data Filter
CDEM
RSSI
RSSI
Dem_out
Data
Interface
Limiter out
RSSI
SENS
IF
Amp.
POLLING/_ON
Sensitivity
reduction
Polling Circuit
and Control Logic
AVCC
AGND
DATA_CLK
MODE
4. Order
f0 = 1 MHz
DGND
DATA
FE
CLK
DVCC
IC_ACTIVE
Standby
Logic
LPF
fg = 2.2 MHz
IF
Amp.
Loop
Filter
XTAL2
XTO
XTAL1
Poly-LPF
fg = 7 MHz
f
LC-VCO
:2
or :3
LNAREF
f
LNA_IN
LNAGND
LNA
f
:2
or :4
:128
or :64
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9106E–RKE–07/08
2. Pin Configuration
Figure 2-1.
Table 2-1.
Pin
4
Pinning SSO20
SENS
1
20 DATA
IC_ACTIVE
2
19 POLLING/_ON
CDEM
3
18 DGND
AVCC
4
17 DATA_CLK
TEST1
5
RSSI
6
AGND
7
14 XTAL2
LNAREF
8
13 XTAL1
LNA_IN
9
12 TEST3
LNAGND 10
11 TEST2
ATA5723/
ATA5724/
ATA5728
16 MODE
15 DVCC
Pin Description
Symbol
Function
1
SENS
2
IC_ACTIVE
Sensitivity-control resistor
3
CDEM
Lower cut-off frequency data filter
4
AVCC
Analog power supply
5
TEST 1
6
RSSI
RSSI output
7
AGND
Analog ground
8
LNAREF
High-frequency reference node LNA and mixer
RF input
IC condition indicator: Low = sleep mode, High = active mode
Test pin, during operation at GND
9
LNA_IN
10
LNAGND
11
TEST 2
Do not connect during operating
12
TEST 3
Test pin, during operation at GND
13
XTAL1
Crystal oscillator XTAL connection 1
14
XTAL2
Crystal oscillator XTAL connection 2
15
DVCC
Digital power supply
16
MODE
Selecting 315 MHz/other versions
Low: 315 MHz version (ATA5723)
High: 433 MHz/868 MHz versions (ATA5724/ATA5728)
17
DATA_CLK
18
DGND
19
POLLING/_ON
20
DATA
DC ground LNA and mixer
Bit clock of data stream
Digital ground
Selects polling or receiving mode; Low: receiving mode, High: polling mode
Data output/configuration input
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
3. RF Front-end
The RF front-end of the receiver is a low-IF heterodyne configuration that converts the input signal into about 1 MHz IF signal with a typical image rejection of 30 dB. According to Figure Figure
1-2 on page 3 the front-end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q
mixer, polyphase low-pass filter and an IF amplifier.
The PLL generates the drive frequency fLO for the mixer using a fully integrated synthesizer with
integrated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crystal oscillator) generates the reference frequency fREF = fXTO/2 (868 MHz and 433 MHz versions)
or fREF = fXTO/3 (315 MHz version). The integrated LC-VCO generates two or four times the
mixer drive frequency fVCO. The I/Q signals for the mixer are generated with a divide by two or
four circuit (fLO = fVCO/2 for 868 MHz version, fLO = fVCO/4 for 433 MHz and 315 MHz versions).
fVCO is divided by a factor of 128 or 64 and feeds into a phase frequency detector and is compared with fREF. The output of the phase frequency detector is fed into an integrated loop filter
and thereby generates the control voltage for the VCO. If fLO is determined, fXTO can be calculated using the following formula:
fREF = fLO/128 for 868 MHz band, fREF = fLO/64 for 433 MHz bands, fREF = fLO/64 for 315 MHz
bands.
The XTO is a two-pin oscillator that operates at the series resonance of the quartz crystal with
high current but low voltage signal, so that there is only a small voltage at the crystal oscillator
frequency at pins XTAL1 and XTAL2. According to Figure 3-1, the crystal should be connected
to GND with two capacitors CL1 and CL2 from XTAL1 and XTAL2 respectively. The value of
these capacitors are recommended by the crystal supplier. Due to an inductive impedance at
steady state oscillation and some PCB parasitics, a lower value of C L1 and CL2 is normally
necessary.
The value of CLx should be optimized for the individual board layout to achieve the exact value of
fXTO and hence of fLO. (The best way is to use a crystal with known load resonance frequency to
find the right value for this capacitor.) When designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered.
Figure 3-1.
XTO Peripherals
DVCC
VS
CL2
XTAL2
XTAL1
CL1
TEST3
TEST2
The nominal frequency fLO is determined by the RF input frequency fRF and the IF frequency fIF
using the following formula (low-side injection):
fLO = fRF – fIF
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9106E–RKE–07/08
To determine fLO, the construction of the IF filter must be considered. The nominal IF frequency
is fIF = 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by
the crystal frequency fXTO. This means that there is a fixed relationship between fIF and fLO.
fIF = fLO/318 for the 315 MHz band (ATA5723)
fIF = fLO/438 for the 433.92 MHz band (ATA5724)
fIF = fLO/915 for the 868.3 MHz band (ATA5728)
The relationship is designed to achieve the nominal IF frequency of:
fIF = 987 kHz for the 315 MHz and BIF = 300 kHz (ATA5723)
fIF = 987 kHz for the 433.92 MHz and BIF = 300 kHz (ATA5724)
fIF = 947.8 kHz for the 868.3 MHz and BIF = 600 kHz (ATA5728)
The RF input either from an antenna or from an RF generator must be transformed to the RF
input pin LNA_IN. The input impedance of this pin is provided in the electrical parameters. The
parasitic board inductances and capacitances influence the input matching. The RF receiver
ATA5723/ATA5724/ATA5728 exhibits its highest sensitivity if the LNA is power matched.
Because of this, matching to a SAW filter, a 50Ω or an antenna is easier.
Figure 14-1 on page 32 “Application Circuit” shows a typical input matching network for
fRF = 315 MHz, fRF = 433.92 MHz or fRF = 868.3 MHz to 50Ω. The input matching network shown
in Table 14-2 on page 32 is the reference network for the parameters given in the electrical
characteristics.
4. Analog Signal Processing
4.1
IF Filter
The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter.
The IF center frequency is:
fIF = 987 kHz for the 315 MHz and BIF = 300 kHz (ATA5723)
fIF = 987 kHz for the 433.92 MHz and BIF = 300 kHz (ATA5724)
fIF = 947.9 kHz for the 868.3 MHz and BIF = 600 kHz (ATA5728)
The nominal bandwidth is 300 kHz for ATA5723 and ATA5724 and 600 kHz for ATA5728.
4.2
Limiting RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into
the demodulator. The dynamic range of this amplifier is ΔRRSSI = 60 dB. If the RSSI amplifier is
operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic
range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum
RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the
RSSI amplifier is exceeded if the RF input signal is approximately 60 dB higher compared to the
RF input signal at full sensitivity.
The S/N ratio is not affected by the dynamic range of the RSSI amplifier in FSK mode because
only the hard limited signal from a high-gain limiting amplifier is used by the demodulator.
The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output
signal, the signal strength of different transmitters can be distinguished. The usable input power
range PRef is –100 dBm to –55 dBm.
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ATA5723/ATA5724/ATA5728
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ATA5723/ATA5724/ATA5728
Figure 4-1.
RSSI Characteristics ATA5724
RSSI Characteristics
3.5
4.5V -40˚C
5V -40˚C
3
5.5V -40˚C
V_RSSI (V)
4.5V 25˚C
5V 25˚C
2.5
5.5V 25˚C
4.5V 85˚C
2
5V 85˚C
5.5V 85˚C
4.5V 105˚C
1.5
5V 105˚C
5.5V 105˚C
1
-120
-110
-100
-90
-80
-70
-60
-50
-40
PIN (dBm)
The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red.
VTh_red is determined by the value of the external resistor RSens. RSens is connected between pin
SENS and GND or VS. The output of the comparator is fed into the digital control logic. By this
means, it is possible to operate the receiver at a lower sensitivity.
If RSens is connected to GND, the receiver switches to full sensitivity. It is also possible to connect the pin SENS directly to GND to get the maximum sensitivity.
If RSens is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is
defined by the value of RSens, and the maximum sensitivity is defined by the signal-to-noise ratio
of the LNA input. The reduced sensitivity depends on the signal strength at the output of the
RSSI amplifier.
Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This
matching is described and illustrated in Section 14. “Data Interface” on page 32.
RSens can be connected to VS or GND using a microcontroller. The receiver can be switched
from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver
does not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is
already active, the data stream at pin DATA disappears when the input signal is lower than
defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure
4-2 “Steady L State Limited DATA Output Pattern” is issued at pin DATA to indicate that the
receiver is still active (see Figure 13-2 on page 30 “Data Interface”).
Figure 4-2.
Steady L State Limited DATA Output Pattern
DATA
tDATA_min
tDATA_L_max
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4.3
FSK/ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK
demodulator. The operating mode of the demodulator is set using the bit ASK/_FSK in the
OPMODE register. Logic L sets the demodulator to FSK, applying H to ASK mode.
In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. This circuit also
implements the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10 dB the data signal can
be detected properly. However, better values are found for many modulation schemes of the
competing transmitter.
The FSK demodulator is intended to be used for an FSK deviation of 10 kHz ≤Δf ≤100 kHz. The
data signal in FSK mode can be detected if the S/N (ratio to suppress in-band noise signals)
exceeds about 2 dB. This value is valid for all modulation schemes of a disturber signal.
The output signal of the demodulator is filtered by the data filter before it is fed into the digital
signal processing circuit. The data filter improves the S/N ratio as its pass-band can be adopted
to the characteristics of the data signal. The data filter consists of a 1st order high-pass and a 2nd
order low-pass filter.
The high-pass filter cut-off frequency is defined by an external capacitor connected to pin
CDEM. The cut-off frequency of the high-pass filter is defined by the following formula:
1
fcu_DF = ------------------------------------------------------------2 × π × 30 kΩ × CDEM
In self-polling mode the data filter must settle very rapidly to achieve a low current consumption.
Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other
hand, CDEM must be large enough to meet the data filter requirements according to the data
signal. Recommended values for CDEM are given in the electrical characteristics.
The cut-off frequency of the low-pass filter is defined by the selected baud-rate range
(BR_Range). The BR_Range is defined in the OPMODE register (refer to Section 11. “Configuring the Receiver” on page 25). The BR_Range must be set in accordance to the baud-rate used.
The ATA5723/ATA5724/ATA5728 is designed to operate with data coding where the DC level of
the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain within the range of VDC_min = 33% and
VDC_max = 66%. The sensitivity may be reduced by up to 2 dB in that condition.
Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig).
These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.
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ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
5. Receiving Characteristics
The RF receiver ATA5723/ATA5724/ATA5728 can be operated with and without a SAW
front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving frequency response without a SAW front-end filter is
illustrated in Figure 5-1 “Narrow Band Receiving Frequency Response ATA5724”. This example
relates to ASK mode. FSK mode exhibits a similar behavior. The plots are printed relatively to
the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3 dB must be considered, but the overall selectivity is much better.
When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated, to be the
sum of the deviation of the crystal and the XTO deviation of the ATA5723/ATA5724/ATA5728.
Low-cost crystals are specified to be within ±90 ppm over tolerance, temperature, and aging.
The XTO deviation of the ATA5723/ATA5724/ATA5728 is an additional deviation due to the
XTO circuit. This deviation is specified to be ±10 ppm worst case for a crystal with CM = 7 fF. If
a crystal of ±90 ppm is used, the total deviation is ±100 ppm in that case. Note that the receiving
bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.
Figure 5-1.
Narrow Band Receiving Frequency Response ATA5724
Image Rejection versus RF Frequency
10
0
4.5V -40˚C
5V -40˚C
-10
5.5V -40˚C
(dB)
-20
4.5V 25˚C
-30
5V 25˚C
-40
4.5V 105˚C
5.5V 25˚C
5V 105˚C
-50
5.5V 105˚C
-60
-70
430
431
432
433
434
435
436
437
438
(MHz)
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9106E–RKE–07/08
6. Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved using the polling circuit. This circuit enables the signal
path periodically for a short time. During this time the bit-check logic verifies the presence of a
valid transmitter signal. Only if a valid signal is detected, the receiver remains active and transfers the data to the connected microcontroller. If there is no valid signal present, the receiver is
in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc.
The receiver is very flexible with regards to the number of connection wires to the microcontroller. It can be either operated by a single bi-directional line to save ports to the connected
microcontroller or it can be operated by up to five uni-directional ports.
7. Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. This
clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divide by 28 or
30 circuit. According to Section 3. “RF Front-end” on page 5, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of
the local oscillator (fLO). The basic clock cycle for ATA5724 and ATA5728 is TClk 28/fXTO giving
TClk = 2.066 µs for fRF = 868.3 MHz and TClk = 2.069 µs for fRF = 433.92 MHz. For ATA5723 the
basic clock cycle is TClk = 30/fREF giving TClk = 2.0382 µs for fRF = 315 MHz.
TClk controls the following application-relevant parameters:
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0)
Most applications are dominated by three transmission frequencies: fTransmit = 315 MHz is mainly
used in USA, fTransmit = 868.3 MHz and 433.92 MHz in Europe. All timings are based on TClk. For
the aforementioned frequencies, TClk is given as:
• Application 315 MHz band (fXTO = 14.71875 MHz, fLO = 314.13 MHz, TClk = 2.0382 µs)
• Application 868.3 MHz band (fXTO = 13.55234 MHz, fLO = 867.35 MHz, TClk = 2.066 µs)
• Application 433.92 MHz band (fXTO = 13.52875 MHz, fLO = 432.93 MHz, TClk = 2.0696 µs)
For calculation of TClk for applications using other frequency bands, see table in Section 18.
“Electrical Characteristics ATA5724, ATA5728” on page 37.
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ATA5723/ATA5724/ATA5728
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ATA5723/ATA5724/ATA5728
The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range),
which is defined in the OPMODE register. This clock cycle TXClk is defined by the following
formulas:
BR_Range =
BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
TXClk = 8 ×
TXClk = 4 ×
TXClk = 2 ×
TXClk = 1 ×
TClk
TClk
TClk
TClk
8. Polling Mode
According to Figure 8-1 on page 12, the receiver stays in polling mode in a continuous cycle of
three different modes. In sleep mode the signal processing circuitry is disabled for the time
period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming
data stream is analyzed bit-by-bit and compared with a valid transmitter signal. If no valid signal
is present, the receiver is set back to sleep mode after the period TBit-check. This period varies
according to each check as it is a statistical process. An average value for TBitcheck is given in the
electrical characteristics. During TStartup and TBit-check, the current consumption is IS = ISon. The
condition of the receiver is indicated on pin IC_ACTIVE. The average current consumption in
polling mode is dependent on the duty cycle of the active mode and can be calculated as:
I Soff × T Sleep + I Son × ( T Startup + T Bit-check )
I Spoll = --------------------------------------------------------------------------------------------------------------T Sleep + T Startup + T Bit-check
During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the
reception of a transmitted command, the transmitter must start the telegram with an adequate
preburst. The required length of the preburst depends on the polling parameters TSleep, TStartup,
TBit-check and the start-up time of a connected microcontroller, TStart_microcontroller. Thus, TBit-check
depends on the actual bit rate and the number of bits (NBit-check) to be tested.
The following formula indicates how to calculate the preburst length.
TPreburst ≥ TSleep + TStartup + TBit-check + TStart_microcontroller
8.1
Sleep Mode
The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep (according to Table 11-8 on page 27), and the basic clock cycle T Clk. It is
calculated to be:
TSleep = Sleep × XSleep × 1024 × TClk
The maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about
2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8.
XSleep can be set to 8 by bit XSleepStd to “1”.
Setting the configuration word Sleep to its maximal value puts the receiver into a permanent
sleep mode. The receiver remains in this state until another value for Sleep is programmed into
the OPMODE register. This is particularily useful when several devices share a single data line.
(It can also be used for microcontroller polling: using pin POLLING/_ON, the receiver can be
switched on and off.)
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9106E–RKE–07/08
Figure 8-1.
Polling Mode Flow Chart
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic are
enabled.
Output level on Pin IC_ACTIVE = > low
Sleep:
5-bit word defined by Sleep 0 to
Sleep 4 in OPMODE register
XSleep:
Extension factor defined by
XSleepStd according to Table 11-8
TClk:
Basic clock cycle defined by fXTO
and Pin MODE
TStartup:
Is defined by the selected baud rate
range and TClk. The baud-rate range
is defined by Baud 0 and Baud 1 in
the OPMODE register.
IS = ISoff
TSleep = Sleep × XSleep × 1024 × TClk
Start-up Mode:
The signal processing circuits are
enabled. After the start-up time (TStartup)
all circuits are in stable
condition and ready to receive.
Output level on Pin IC_ACTIVE = > high
IS = ISon
TStartup
Bit-check Mode:
The incoming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
Output level on Pin IC_ACTIVE = > high
IS = ISon
TBit-check
NO
Bit Check
OK ?
YES
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via Pin DATA or
Polling/_ON.
Output level on Pin IC_ACTIVE = > high
IS = ISon
TBit-check:
Depends on the result of the bit check
If the bit check is ok, TBit-check
depends on the number of bits to be
checked (NBit-check) and on the
data rate used.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on TClk. The baud-rate range is
defined by Baud 0 and Baud 1 in the
OPMODE register.
OFF Command
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ATA5723/ATA5724/ATA5728
8.2
Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum number of these edge-to-edge tests, before the
receiver switches to receiving mode, is also programmable.
8.3
Configuring the Bit Check
Assuming a modulation scheme that contains two edges per bit, two time frame checks verify
one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6, or 9 bits using the variable NBit-check in the
OPMODE register. This implies 0, 6, 12, and 18 edge-to-edge checks respectively. If NBit-check is
set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the
presence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower
value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 8-2 shows an
example where three bits are tested successfully and the data signal is transferred to pin DATA.
Figure 8-2.
Timing Diagram for Complete Successful Bit Check
Bit check ok
(Number of checked Bits: 3)
IC_ACTIVE
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Data_out (DATA)
TStart-up
TBit-check
Start-up mode
Start-check mode
Receiving mode
According to Figure 8-3, the time window for the bit check is defined by two separate time limits.
If the edge-to-edge time t ee is in between the lower bit-check limit T Lim_min and the upper
bit-check limit TLim_max, the check continues. If tee is smaller than TLim_min or tee exceeds TLim_max,
the bit check is terminated and the receiver switches to sleep mode.
Figure 8-3.
Valid Time Window for Bit Check
1/fSig
Dem_out
tee
TLim_min
TLim_max
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9106E–RKE–07/08
For best noise immunity using a low span between TLim_min and TLim_max is recommended. This is
achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A “11111...” or
a “10101...” sequence in Manchester or Bi-phase is suitable for this. A good compromise
between receiver sensitivity and susceptibility to noise is a time window of ±30% regarding the
expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to-edge time
periods, the bit-check limits must be programmed according to the required span.
The bit-check limits are determined by means of the formula below.
TLim_min = Lim_min × TXClk
TLim_max = (Lim_max – 1) × TXClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the required
TLim_min, TLim_max and TXClk. The time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the Section 8.6
“Digital Signal Processing” on page 16. The lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (NBit-check) to
prevent switching to receiving mode due to noise.
Figure 8-4, Figure 8-5, and Figure 8-6 illustrate the bit check for the bit-check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during TStartup. The output of the ASK/FSK demodulator (Dem_out) is undefined during
that period. When the bit check becomes active, the bit-check counter is clocked with the cycle
TXClk.
Figure 8-4 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 8-5 the bit
check fails as the value CV_Lim is lower than the limit Lim_min. The bit check also fails if
CV_Lim reaches Lim_max. This is illustrated in Figure 8-6.
Figure 8-4.
Timing Diagram During Bit Check
Bit check ok
(Lim_min = 14, Lim_max = 24)
Bit check ok
IC_ACTIVE
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Bit-check
counter
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4
TXClk
14
TStart-up
TBit-check
Start-up mode
Bit-check mode
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 8-5.
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
Bit check failed (CV_Lim_ < Lim_min)
IC_ACTIVE
Bit check
1/2 Bit
Dem_out
Bit-check
counter
Figure 8-6.
0
1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12
0
TStart-up
TBit-check
TSleep
Start-up mode
Bit-check mode
Sleep mode
Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
Bit check failed (CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
Bit check
1/2 Bit
Dem_out
Bit-check
counter
8.4
0
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0
TStart-up
TBit-check
TSleep
Start-up mode
Bit-check mode
Sleep mode
Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and TBit-check varies for each check.
Therefore, an average value for T Bit-check is given in the electrical characteristics. T Bit-check
depends on the selected baud-rate range and on TClk. A higher baud-rate range causes a lower
value for TBit-check resulting in a lower current consumption in polling mode.
In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the checked bits, NBit-check. A higher value for NBit-check thereby results in
a longer period for TBit-check requiring a higher value for the transmitter pre-burst TPreburst.
8.5
Receiving Mode
If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving
mode. According to Figure 8-2 on page 13, the internal data signal is switched to pin DATA in
that case, and the data clock is available after the start bit has been detected (see Figure 9-1 on
page 20). A connected microcontroller can be woken up by the negative edge at pin DATA or by
the data clock at pin DATA_CLK. The receiver stays in that condition until it is switched back to
polling mode explicitly.
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9106E–RKE–07/08
8.6
Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and
as a result converted into the output signal data. This processing depends on the selected
baud-rate range (BR_Range). Figure 8-7 illustrates how Dem_out is synchronized by the
extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its
state only after TXClk has elapsed. The edge-to-edge time period tee of the Data signal as a result
is always an integral multiple of TXClk.
The minimum time period between two edges of the data signal is limited to tee ≥ TDATA_min. This
implies an efficient suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected
microcontroller.
The maximum time period for DATA to stay low is limited to T DATA_L_max . This function is
employed to ensure a finite response time in programming or switching off the receiver via pin
DATA. TDATA_L_max is therefore longer than the maximum time period indicated by the transmitter
data stream. Figure 8-9 on page 17 gives an example where Dem_out remains Low after the
receiver has switched to receiving mode.
Figure 8-7.
Synchronization of the Demodulator Output
TXClk
Clock bit-check
counter
Dem_out
Data_out (DATA)
Figure 8-8.
tee
Debouncing of the Demodulator Output
Dem_out
Data_out (DATA)
tDATA_min
tDATA_min
tee
16
tDATA_min
tee
tee
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 8-9.
Steady L State Limited DATA Output Pattern After Transmission
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
tDATA_min
Start-up mode
Bit-check mode
tDATA_L_max
Receiving mode
After the end of a data transmission, the receiver remains active. Depending of the bit
Noise_Disable in the OPMODE register, the output signal at pin DATA is high or random noise
pulses appear at pin DATA (see Section 10. “Digital Noise Suppression” on page 23). The
edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher than
TDATA_min.
8.7
Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON.
When using pin DATA, this pin must be pulled to low by the connected microcontroller for the
period t1. Figure 8-10 on page 18 illustrates the timing of the OFF command (see Figure 13-2 on
page 30). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not
limited; however, exceeding the specified value to prevent erasing the reset marker is not recommended. Note also that an internal reset for the OPMODE and the LIMIT register is
generated if t1 exceeds the specified values. This item is explained in more detail in the Section
11. “Configuring the Receiver” on page 25. Setting the receiver to sleep mode via DATA is
achieved by programming bit 1 to “1” during the register configuration. Only one sync pulse (t3)
is issued.
The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time
TSleep elapses after the OFF command. Note that the capacitive load at pin DATA is limited (see
Section 14. “Data Interface” on page 32).
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9106E–RKE–07/08
Figure 8-10. Timing Diagram of the OFF Command using Pin DATA
IC_ACTIVE
t1
t2
t3
t5
t4
t10
t7
Out1
(microcontroller)
Data_out (DATA)
X
Serial bi-directional
data line
X
Bit 1
("1")
(Start Bit)
OFF-command
Receiving mode
TSleep
TStart-up
Sleep mode
Start-up mode
Figure 8-11. Timing Diagram of the OFF Command using Pin POLLING/_ON
IC_ACTIVE
ton2
Bit check ok
ton3
POLLING/_ON
Data_out (DATA)
X
X
Serial bi-directional
data line
X
X
Receiving mode
Sleep mode
Start-up mode
Bit-check mode
Receiving mode
Figure 8-12. Activating the Receiving Mode using Pin POLLING/_ON
IC_ACTIVE
ton1
POLLING/_ON
X
Data_out (DATA)
Serial bi-directional
data line
X
Sleep mode
18
Start-up mode
Receiving mode
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 8-11 “Timing Diagram of the OFF Command using Pin POLLING/_ON” illustrates how to
set the receiver back to polling mode using pin POLLING/_ON. The pin POLLING/_ON must be
held to low for the time period ton2. After the positive edge on pin POLLING/_ON and the delay
ton3, the polling mode is active and the sleep time TSleep elapses.
Using the POLLING/_ON command is faster than using pin DATA; however, this requires the
use of an additional connection to the microcontroller.
Figure 8-12 “Activating the Receiving Mode using Pin “POLLING/_ON” illustrates how to set the
receiver to receiving mode using the pin POLLING/_ON. The pin POLLING/_ON must be held to
low. After the delay ton1, the receiver changes from sleep mode to start-up mode regardless of
the programmed values for TSleep and NBit-check. As long as POLLING/_ON is held to low, the values for T Sleep and N Bit-check is ignored, but not deleted (see Section 10. “Digital Noise
Suppression” on page 23).
If the receiver is polled exclusively by a microcontroller, TSleep must be programmed to 31 (permanent sleep mode). In this case the receiver remains in sleep mode as long as POLLING/_ON
is held to high.
9. Data Clock
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock, a microcontroller can easily synchronize the data stream. This clock
can only be used for Manchester and Bi-phase coded signals.
9.1
Generation of the Data Clock
After a successful bit check, the receiver switches from polling mode to receiving mode and the
data stream is available at pin DATA. In receiving mode, the data clock control logic (Manchester/Bi-phase demodulator) is active and examines the incoming data stream. This is done,
as with the bit check, by subsequent time frame checks where the distance between two edges
is continuously compared to a programmable time window. As illustrated in Figure 9-1 on page
20, only two distances between two edges in Manchester and Bi-phase coded signals are valid
(T and 2T).
The limits for T are the same as used with the bit check. They can be programmed in the
LIMIT-register (Lim_min and Lim_max, see Table 11-10 on page 28 and Table 11-11 on page
28).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
Upper limit of 2T:
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
(If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it is rounded up.)
The data clock is available, after the data clock control logic has detected the distance 2T (Start
bit) and is issued with the delay tDelay after the edge on pin DATA (see Figure 9-1 on page 20).
If the data clock control logic detects a timing or logical error (Manchester code violation), as
illustrated in Figure 9-2 on page 20 and Figure 9-3 on page 21, it stops the output of the data
clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was
successful and the start bit has been detected, the data clock control logic starts again with the
generation of the data clock (see Figure 9-4 on page 21).
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9106E–RKE–07/08
Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recommended. If the bit check is set to 0 or the receiver is set to receiving mode using the pin
POLLING/_ON, the data clock is available if the data clock control logic has detected the distance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 9-1.
Timing Diagram of the Data Clock
Preburst
Data
Bit check ok
'1'
'1'
T
'1'
'1'
2T
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
Bit-check mode
tDelay
Start bit
tP_Data_Clk
Receiving mode,
data clock control logic active
Figure 9-2.
Data Clock Disappears Because of a Timing Error
Data
Timing error
Tee < TLim_min or TLim_max < Tee < TLim_min_2T or Tee > TLim_max_2T
Tee
'1'
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
Receiving mode,
data clock control
logic active
20
Receiving mode,
bit check active
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Figure 9-3.
Data Clock Disappears Because of a Logical Error
Data
Logical error (Manchester code violation)
'1'
'1'
'1'
'0'
'1'
'1'
'?'
'0'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
Receiving mode,
bit check active
Receiving mode,
data clock control
logic active
Figure 9-4.
Output of the Data Clock After a Successful Bit Check
Data
Bit check ok
'1'
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
Receiving mode,
bit check active
Start bit
Receiving mode,
data clock control
logic active
The delay of the data clock is calculated as follows: tDelay = tDelay1 + tDelay2
tDelay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1
depends on the capacitive load CL at pin DATA and the external pull-up resistor Rpup. For the
falling edge, tDelay1 depends additionally on the external voltage VX (see Figure 9-5, Figure 9-6
on page 22 and Figure 13-2 on page 30). When the level of Data_In is equal to the level of
Data_Out, the data clock is issued after an additional delay tDelay2.
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at
pin DATA is exceeded, the data clock disappears (see Section 14. “Data Interface” on page 32).
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9106E–RKE–07/08
Figure 9-5.
Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)
Data_Out
VX
VIH = 0.65 VS
Serial bi-directional
data line
VII = 0.35 VS
Data_In
DATA_CLK
tDelay1
tDelay2
tDelay tP_Data_Clk
Figure 9-6.
Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)
Data_Out
VX
VIH = 0.65 VS
VII = 0.35 VS
Serial bi-directional
data line
Data_In
DATA_CLK
tDelay1
tDelay2
tDelay tP_Data_Clk
22
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
10. Digital Noise Suppression
After a data transmission, digital noise appears on the data output (see Figure 10-1 “Output of
Digital Noise at the End of the Data Stream”). To prevent digital noise keeping the connected
microcontroller busy, it can be suppressed in two different ways:
• Automatic Noise Suppression
• Controlled Noise Suppression by the Microcontroller
10.1
Automatic Noise Suppression
The receiver changes to bit-check mode at the end of a valid data stream if the bit
Noise_Disable (Table 11-9 on page 27) in the OPMODE register is set to 1 (default). The digital
noise is suppressed, and the level at pin DATA is high. The receiver changes back to receiving
mode, if the bit check was successful.
This method of noise suppression is recommended if the data stream is Manchester or Bi-phase
coded and is active after power on.
Figure 10-3 “Occurrence of a Pulse at the End of the Data Stream” illustrates the behavior of the
data output at the end of a data stream. If the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the
selected baud-rate range.
Figure 10-1. Output of Digital Noise at the End of the Data Stream
Bit check ok
Bit check ok
Preburst
Data_out (DATA)
Data
Digital Noise
Digital Noise Preburst
Data
Digital Noise
DATA_CLK
Bit-check
mode
Receiving mode,
data clock control
logic active
Receiving mode,
bit check active
Receiving mode,
data clock control
logic active
Receiving mode,
bit check active
Figure 10-2. Automatic Noise Suppression
Bit check ok
Bit check ok
Preburst
Data_out (DATA)
Data
Preburst
Data
DATA_CLK
Bit-check
mode
Receiving mode,
data clock control
logic active
Bit-check
mode
Receiving mode,
data clock control
logic active
Bit-check
mode
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9106E–RKE–07/08
Figure 10-3. Occurrence of a Pulse at the End of the Data Stream
Timing error
tee < TLim_min or TLim_max < tee < tLim_min_2T or tee > TLim_max_2T
Tee
Data stream
'1'
'1'
Digital noise
'1'
Dem_out
Data_out (DATA)
Tpulse
DATA_CLK
Bit-check mode
Receiving mode,
data clock control
logic active
10.2
Controlled Noise Suppression by the Microcontroller
Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see Table 11-9
on page 27) in the OPMODE register is set to 0. To suppress the noise, the pin POLLING/_ON
must be set to low. The receiver remains in receiving mode. The OFF command then causes a
change to start-up mode. The programmed sleep time (see Table 11-7 on page 27) is not executed because the level at pin POLLING/_ON is low; however, the bit check is active in this
case. The OFF command also activates the bit check if the pin POLLING/_ON is held to low.
The receiver changes back to receiving mode if the bit check was successful. To activate the
polling mode at the end of the data transmission, the pin POLLING/_ON must be set to high.
This way of suppressing the noise is recommended if the data stream is not Manchester or
Bi-phase coded.
Figure 10-4. Controlled Noise Suppression
OFF-command
Bit check ok
Serial bi-directional
data line
Preburst
Data
Bit check ok
Digital Noise
Preburst
Data
Digital Noise
(DATA_CLK)
POLLING/_ON
Bit-check
mode
24
Receiving mode
Start-up Bit-check
mode
mode
Receiving mode
Sleep
mode
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
11. Configuring the Receiver
The ATA5723/ATA5724/ATA5728 receiver is configured using two 12-bit RAM registers called
OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA
port. If the register content has changed due to a voltage drop, this condition is indicated by a
the output pattern called reset marker (RM). If this occurs, the receiver must be reprogrammed.
After a Power-On Reset (POR), the registers are set to default mode. If the receiver is operated
in default mode, there is no need to program the registers. Table 11-3 on page 25 shows the
structure of the registers. According to Table 11-1, bit 1 defines whether the receiver is set back
to polling mode using the OFF command (see “Receiving Mode” on page 15) or whether it is
programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. For high programming reliability, bit 15 (Stop bit), at the end of the programming
operation, must be set to 0.
Table 11-1.
Effect of Bit 1 and Bit 2 on Programming the Registers
Bit 1
Bit 2
1
x
The receiver is set back to polling mode (OFF command)
0
1
The OPMODE register is programmed
0
0
The LIMIT register is programmed
Table 11-2.
Action
Effect of Bit 15 on Programming the Register
Bit 15
Table 11-3.
Bit 1
Bit 2
Action
0
The values are written into the register (OPMODE or LIMIT)
1
The values are not written into the register
Effect of the Configuration Words within the Registers
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
–
–
–
–
–
Bit 15
OFF command
1
–
–
–
–
–
–
–
BR_Range
0
–
–
OPMODE register
Modulation
NBit-check
1
Default
values of
Bit 3...14
Sleep
Noise
Suppression
Baud0
BitChk1
BitChk0
ASK/
_FSK
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
XSleepStd
Noise_
Disable
0
0
0
1
0
0
0
1
1
0
0
1
LIMIT register
0
Default
values of
Bit 3...14
0
–
–
Lim_min
0
XSleep
Baud1
–
–
–
Lim_max
–
Lim_
min5
Lim_
min4
Lim_
min3
Lim_
min2
Lim_
min1
Lim_
min0
Lim_
max5
Lim_
max4
Lim_
max3
Lim_
max2
Lim_
max1
Lim_
max0
0
0
1
0
1
0
1
1
0
1
0
0
1
–
25
9106E–RKE–07/08
The following tables illustrate the effect of the individual configuration words. The default configuration is highlighted for each word.
BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used
to define the bit-check limits TLim_min and TLim_max as shown in Table 11-10 on page 28 and Table
11-11 on page 28.
Table 11-4.
Effect of the configuration word BR_Range
BR_Range
Baud1
Baud0
0
0
BR_Range0
(BR_Range0 = 1.0 kBit/s to 1.8 kBit/s)
XLim = 8 (default)
0
1
BR_Range1
(BR_Range1 = 1.8 kBit/s to 3.2 kBit/s)
XLim = 4
1
0
BR_Range2
(BR_Range2 = 3.2 kBit/s to 5.6 kBit/s)
XLim = 2
1
1
BR_Range3
(BR_Range3 = 5.6 kBit/s to 10 kBit/s)
XLim = 1
Table 11-5.
Baud-rate Range/Extension Factor for Bit-check Limits (XLim)
Effect of the Configuration word NBit-check
NBit-check
BitChk1
BitChk0
Number of Bits to be Checked
0
0
0
0
1
3 (default)
1
0
6
1
1
9
Table 11-6.
Effect of the Configuration Bit Modulation
Modulation
26
Selected Modulation
ASK/_FSK
–
0
FSK (default)
1
ASK
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Table 11-7.
Effect of the Configuration Word Sleep
Sleep
Start Value for Sleep Counter
(TSleep = Sleep × XSleep × 1024 × TClk)
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
0
0
0
0
0
0 (Receiver polls continuously until a valid signal
occurs)
0
0
0
0
1
If XSleep = 1
TSleep = 2.11 ms for fRF = 868.3 MHz,
TSleep = 2.12 ms for fRF = 433.92 MHz
TSleep = 2.08 ms for fRF = 315 MHz
0
0
0
1
0
2
0
0
0
1
1
3
...
...
...
...
...
...
0
0
1
1
0
If XSleep = 1
TSleep = 12.69 ms for fRF = 868.3 MHz,
TSleep = 12.71 ms for fRF = 433.92 MHz
TSleep = 12.52 ms for fRF = 315 MHz
...
...
...
...
...
...
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31 (permanent sleep mode)
Table 11-8.
Effect of the Configuration Bit XSleep
XSleep
Table 11-9.
XSleepStd
Extension Factor for Sleep Time
(TSleep = Sleep × XSleep × 1024 × TClk)
0
1 (default)
1
8
Effect of the Configuration Bit Noise Suppression
Noise Suppression
Noise_Disable
Suppression of the Digital Noise at Pin DATA
0
Noise suppression is inactive
1
Noise suppression is active (default)
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9106E–RKE–07/08
Table 11-10. Effect of the Configuration Word Lim_min
Lim_min(1) (Lim_min < 10 is not Applicable)
Lower Limit Value for Bit Check
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(TLim_min = Lim_min × XLim × TClk)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
0
0
1
1
0
0
12
..
..
..
..
..
..
21 (default, BR_Range0)
(TLim_min = 347 µs for fRF = 868.3 MHz
TLim_min = 347 µs for fRF = 433.92 MHz
TLim_min = 342 µs for fRF = 315 MHz)
0
1
0
1
0
1
..
..
..
..
..
..
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
Note:
1. Lim_min is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 19).
Table 11-11. Effect of the Configuration Word Lim_max
Lim_max(1) (Lim_max < 12 is not applicable)
Upper Limit Value for Bit Check
Lim_max5
Lim_max4
Lim_max3
Lim_max2
Lim_max1
Lim_max0
(TLim_max = (Lim_max – 1) × XLim × TClk)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
0
0
1
1
1
0
14
..
..
..
..
..
..
Note:
28
41 (default, BR_Range0)
(TLim_max = 661 µs for fRF = 868.3 MHz
TLim_max = 662 µs for fRF = 433.92 MHz
TLim_max = 652 µs for fRF = 315 MHz)
1
0
1
0
0
1
..
..
..
..
..
..
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
1. Lim_max is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 19).
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
12. Conservation of the Register Information
The ATA5723/ATA5724 uses an integrated power-on reset and brown-out detection circuitry as
a mechanism to preserve the RAM register information.
According to Figure 12-1, a power-on reset (POR) is generated if the supply voltage VS drops
below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. The POR is cancelled after the minimum reset period tRst when VS
exceeds VThReset. A POR is also generated when the supply voltage of the receiver is turned on.
To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset.
The RM is represented by the fixed frequency fRM at a 50% duty-cycle. RM can be cancelled
using a low pulse t1 at pin DATA. The RM has the following characteristics:
• fRM is lower than the lowest feasible frequency of a data signal. Due to this, RM cannot be
misinterpreted by the connected microcontroller.
• If the receiver is set back to polling mode using pin DATA, RM cannot be cancelled
accidentally if t1 is applied as described in the proposal in Section 13. “Programming the
Configuration Register” on page 30.
Using this conservation mechanism, the receiver cannot lose its register information without
communicating this condition using the reset marker RM.
Figure 12-1. Generation of the Power-on Reset
VS
VThreset
POR
tRst
Data_out (DATA)
X
1/fRM
29
9106E–RKE–07/08
13. Programming the Configuration Register
Figure 13-1. Timing of the Register Programming
IC_ACTIVE
t1
t2
t3
t5
t9
t8
t4
t6
t7
Out1
(microcontroller)
Data_out (DATA)
X
Serial bi-directional
data line
X
Bit 1
("0")
(Start bit)
Bit 2
("1")
(Register
select)
Bit 14
("0")
(Poll 8)
Bit 15
("0")
(Stop bit)
TSleep TStart-up
Programming frame
Receiving
mode
Sleep Start-up
mode mode
Figure 13-2. Data Interface
VS = 4.5V to 5.5V
0V/5V
Data_in
VX = 5V to 20V
ATA5723
ATA5724
ATA5728
Input
Interface
0V to 20V
Microcontroller
Rpup
DATA
I/O
Serial bi-directional data line
ID
CL
Data_out
Out1 (microcontroller)
The configuration registers are serially programmed using the bi-directional data line as shown
in Figure 13-1 and Figure 13-2.
To start programming, the serial data line DATA is pulled to low by the microcontroller for the
time period t1. When DATA has been released, the receiver becomes the master device. When
the programming delay period t2 has elapsed, the receiver emits 15 subsequent synchronization
pulses with the pulse length t3. After each of these pulses, a programming window occurs. The
delay until the program window starts is determined by t4, the duration is defined by t5. The individual bits are set within the programming window. If the microcontroller pulls down pin DATA for
the time period t7 during t5, the corresponding bit is set to “0”. If no programming pulse t7 is
issued, this bit is set to “1”. All 15 bits are programmed this way. The time frame to program a bit
is defined by t6.
30
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
Bit 15 is followed by the equivalent time window t9. During this window, the equivalence
acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the
mode word that was already stored in that register. E_Ack should be used to verify that the
mode word was correctly transferred to the register. The register must be programmed twice in
that case.
A register can be programmed when the receiver is in both sleep-mode and active mode. During
programming, the LNA, LO, low-pass filter, IF-amplifier, and the FSK/MSK demodulator are disabled. The t1 pulse is used to start the programming or to switch the receiver back to polling
mode (OFF command). (The receiver is switched back to polling mode with the OFF command if
bit 1 is set to „1“.) The following convention should be considered for the length of the programming start pulse t1:
Using a t1 value of t1 (min) < t1 < 5632 TClk (where t1 (min) is the minimum specified value for
the relevant BR_Range) when the receiver is active i.e., not in reset mode initiates the programming or OFF command. However, if this t1 value is used when the receiver is in reset mode,
programming or OFF command is NOT initiated and RM remains present at pin DATA. Note, the
RM cannot be deleted when using this t1 value.
Using a t1 value of t1 > 7936 ´ TClk, programming or OFF command is initiated when the
receiver is in both reset mode and active mode. The registers PMODE and LIMIT are set to the
default values and the RM is deleted, if present. This t1 values can be used if the connected
microcontroller detects an RM. Additionally, this t1 value can generally be used if the receiver
operates in default mode.
Note that the capacitive load at pin DATA is limited.
31
9106E–RKE–07/08
14. Data Interface
The data interface (see Figure 13-2 on page 30) is designed for automotive requirements. It can
be connected using the pull-up resistor Rpup up to 20V and is short-circuit-protected.
The applicable pull-up resistor R pup depends on the load capacity C L at pin DATA and the
selected BR_range (see Table 14-1).
Table 14-1.
Applicable Rpup
-
BR_range
Applicable Rpup
B0
1.6 kΩ to 47 kΩ
B1
1.6 kΩ to 22 kΩ
B2
1.6 kΩ to 12 kΩ
B3
1.6 kΩ to 5.6 kΩ
B0
1.6 kΩ to 470 kΩ
CL ≤ 1nF
CL ≤ 100pF
B1
1.6 kΩ to 220 kΩ
B2
1.6 kΩ to 120 kΩ
B3
1.6 kΩ to 56 kΩ
Figure 14-1. Application Circuit: fRF = 315 MHz(1), 433.92 MHz or without SAW Filter
VS
RSSI
+
IC_ACTIVE
C7
4.7 µF
10%
R2
Sensitivity reduction
56 kΩ to 150 kΩ
VX = 5V to 20V
GND
C14
39 nF
5%
R3
1.6 kΩ
20
1
SENS
DATA
DATA
2
19
IC_ACTIVE
POLLING/_ON
POLLING/_ON
18
3
CDEM
DGND
17
DATA_CLK
DATA_CLK
16
4
AVCC
5
C13
10 nF
10%
ATA5723
ATA5724
ATA5728
TEST1
6
RSSI
7
AGND
RF_IN
14
13
LNAREF
XTAL1
LNA_IN
TEST3
LNAGND
TEST2
Note:
F
crystal
12
10
L1
CL2
XTAL2
9
C16
CL1
11
For 315 MHz application pin MODE must be connected to GND.
Table 14-2.
32
15
DVCC
8
C17
C12
10 nF
10%
MODE
Input Matching to 50Ω
LNA Matching
RF Frequency
(MHz)
C16 (pF)
C17 (pF)
L1 (nH)
Crystal Frequency
fXTAL (MHz)
315
Not connected
3
39
14.71875
433.92
Not connected
3
20
13.52875
868.3
1
3
6.8
13.55234
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
15. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Max.
Unit
Supply voltage
VS
6
V
Power dissipation
Ptot
1000
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
–55
+125
°C
Tamb
–40
+105
°C
10
dBm
Ambient temperature
Maximum input level, input matched to 50Ω
Pin_max
16. Thermal Resistance
Parameters
Junction ambient
Symbol
Value
Unit
RthJA
100
K/W
33
9106E–RKE–07/08
17. Electrical Characteristics ATA5723
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315 MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
No. Parameter
1
1.1
fRF = 315 MHz
14.71875 MHz Oscillator
Symbol
Basic clock
cycle
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Sleep and
XSleep are
defined in the
OPMODE
register
BR_Range0
Start-up time
BR_Range1
(see Figure
BR_Range2
2.2
8-1 and
BR_Range3
Figure 8-4)
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit Type*
TClk
2.0382
2.0382
30/fXTO
30/fXTO
µs
A
TXClk
16.3057
8.1528
4.0764
2.0382
16.3057
8.1528
4.0764
2.0382
8×
4×
2×
1×
8×
4×
2×
1×
µs
µs
µs
µs
A
TSleep
Sleep ×
XSleep ×
1024 ×
2.0382
Sleep ×
XSleep ×
1024 ×
2.0382
Sleep ×
XSleep ×
1024 ×
TClk
Sleep ×
XSleep ×
1024 × TClk
ms
A
1827
1044
1044
653
1827
1044
1044
653
896.5
512.5
512.5
320.5
× TClk
896.5
512.5
512.5
320.5
× TClk
µs
µs
µs
µs
µs
A
TStartup
Time for bit
2.3 check (see
Figure 8-1
Average
bit-check time
while polling,
no RF applied
(see Figure 8-5
TBit-check
and Figure 8-6)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Time for bit
2.4 check (see
Figure 8-1
Bit-check time
for a valid input
signal fSig (see
Figure 8-5)
NBit-check = 0
NBit-check = 3
NBit-check = 6
NBit-check = 9
3.1
Typ.
TClk
TClk
TClk
TClk
TClk
TClk
TClk
TClk
Polling Mode
Sleep time
(see
Figure 8-1,
2.1
Figure 8-10
and
Figure 13-1)
3
Min.
Variable Oscillator
Basic Clock Cycle of the Digital Circuitry
Extended
1.2 basic clock
cycle
2
Test
Conditions
TBit-check
C
ms
ms
ms
ms
0.45
0.24
0.14
0.08
0.45
0.24
0.14
0.08
C
1 × TXClk
3/fSig
6/fSig
9/fSig
1 × TXClk
3.5/fSig
6.5/fSig
9.5/fSig
1 × TXClk
3/fSig
6/fSig
9/fSig
1 × TClk
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
Receiving Mode
Intermediate
frequency
Baud-rate
3.2
range
fIF
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range
987
1.0
1.8
3.2
5.6
fIF = fLO/318
1.8
3.2
5.6
10.0
BR_Range0 ×
BR_Range1 ×
BR_Range2 ×
BR_Range3 ×
2 µs/TClk
2 µs/TClk
2 µs/TClk
2 µs/TClk
kHz
A
kBit/s
kBit/s
kBit/s
kBit/s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
34
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
17. Electrical Characteristics ATA5723 (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315 MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
No. Parameter
Minimum
time period
between
edges at pin
DATA
(see Figure
3.3 4-2 and
Figure 8-8,
Figure 8-9)
(With the
exception of
parameter
TPulse)
Maximum
Low period at
3.4 pin DATA
(see
Figure 4-2)
Test
Conditions
fRF = 315 MHz
14.71875 MHz Oscillator
Symbol
Min.
Typ.
Max.
Typ.
Max.
Min.
Typ.
Max.
Unit Type*
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
tDATA_min
tDATA_L_max
163.06
81.53
40.76
20.38
163.06
81.53
40.76
20.38
10 ×
10 ×
10 ×
10 ×
TXClk
TXClk
TXClk
TXClk
10 ×
10 ×
10 ×
10 ×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
2120
1060
530
265
2120
1060
530
265
130 ×
130 ×
130 ×
130 ×
TXClk
TXClk
TXClk
TXClk
130 ×
130 ×
130 ×
130 ×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
21.4
10.5 × TClk
µs
A
µs
A
µs
A
Delay to
activate the
3.5 start-up
mode (see
Figure 8-12)
Ton1
19.36
OFF
command at
pin
3.6
POLLING/
_ON (see
Figure 8-11)
Ton2
16.3
Delay to
activate the
3.7 sleep mode
(see
Figure 8-11)
Ton3
17.32
19.36
16.3
8.15
4.07
2.04
16.3
8.15
4.07
2.04
Pulse on pin
DATA at the
end of a data
3.8
stream
(see
Figure 10-3)
Variable Oscillator
Min.
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TPulse
9.5 × TClk
8 × TClk
8.5 × TClk
8×
4×
2×
1×
TClk
TClk
TClk
TClk
9.5 × TClk
8×
4×
2×
1×
TClk
TClk
TClk
TClk
µs
µs
µs
µs
A
A
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
35
9106E–RKE–07/08
17. Electrical Characteristics ATA5723 (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315 MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
No. Parameter
4
Test
Conditions
fRF = 315 MHz
14.71875 MHz Oscillator
Symbol
Min.
Typ.
Max.
Variable Oscillator
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit Type*
Configuration of the Receiver (see Figure 12-1 and Figure 13-1)
Frequency is
Frequency of
stable within
4.1 the reset
50 ms after
marker
POR
BR_Range =
BR_Range0
Programming BR_Range1
4.2
BR_Range2
start pulse
BR_Range3
after POR
fRM
t1
119.78
119.78
3310
2242
1708
1441
16175
11479
11479
11479
11479
1/
(4096 ×
TClk)
1624 ×
TClk
1100 ×
TClk
838 × TClk
707 × TClk
7936 ×
TClk
1/
(4096 ×
TClk)
5632 ×
5632 ×
5632 ×
5632 ×
TClk
TClk
TClk
TClk
Hz
µs
µs
µs
µs
µs
A
A
4.3
Programming
delay period
t2
783
785
384.5 ×
TClk
385.5 ×
TClk
µs
A
4.4
Synchronization pulse
t3
261
261
128 × TClk
128 × TClk
µs
A
Delay until of
the program
4.5
window
starts
t4
129
129
63.5 × TClk
63.5 × TClk
µs
A
4.6
Programming
window
t5
522
522
256 × TClk
256 × TClk
µs
A
4.7
Time frame
of a bit
t6
1044
1044
512 × TClk
512 × TClk
µs
A
4.8
Programming
pulse
t7
130.5
522
64 × TClk
256 × TClk
µs
C
Equivalent
4.9 acknowledge
pulse: E_Ack
t8
261
261
128 × TClk
128 × TClk
µs
A
t9
526
526
258 × TClk
258 × TClk
µs
A
t10
916
916
449.5 ×
TClk
449.5 ×
TClk
µs
A
0
0
0
0
16.3057
8.1528
4.0764
2.0382
0
0
0
0
1×
1×
1×
1×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
C
65.2
32.6
16.3
8.15
65.2
32.6
16.3
8.15
TXClk
TXClk
TXClk
TXClk
4×
4×
4×
4×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
4.10
Equivalent
time window
OFF-bit
4.11 programming
window
5
Data Clock (see Figure 9-1 and Figure 9-6)
Minimum
delay time
between
5.1
edge at DATA
and
DATA_CLK
Pulse width
of negative
5.2
pulse at pin
DATA_CLK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
tDelay2
tP_DATA_CLK
4×
4×
4×
4×
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
36
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
18. Electrical Characteristics ATA5724, ATA5728
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 868.3 MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
No. Parameter
6
6.1
Basic clock
cycle
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Sleep and
XSleep are
defined in the
OPMODE
register
BR_Range0
Start-up time
BR_Range1
(see Figure
BR_Range2
7.2
8-1 and
BR_Range3
Figure 8-4)
Time for bit
7.3 check (see
Figure 8-1
Time for bit
7.4 check (see
Figure 8-1
8.1
Typ.
Max.
Min.
Typ.
Variable Oscillator
Max.
Min.
Typ.
Max.
Unit Type*
TClk
2.0696
2.0696
2.066
2.066
28/fXTO
28/fXTO
µs
A
TXClk
16.557
8.278
4.139
2.069
16.557
8.278
4.139
2.069
16.528
8.264
4.132
2.066
16.528
8.264
4.132
2.066
8×
4×
2×
1×
8×
4×
2×
1×
µs
µs
µs
µs
A
TSleep
Sleep ×
XSleep ×
1024 ×
2.0696
Sleep ×
XSleep ×
1024 ×
2.0696
Sleep ×
XSleep ×
1024 ×
2.066
Sleep ×
XSleep ×
1024 ×
2.066
Sleep ×
XSleep ×
1024 ×
TClk
Sleep ×
XSleep ×
1024 × TClk
ms
A
1855
1060
1060
663
1855
1060
1060
663
1852
1058
1058
662
1852
1058
1058
662
896.5
512.5
512.5
320.5
× TClk
896.5
512.5
512.5
320.5
× TClk
µs
µs
µs
µs
µs
A
TClk
TClk
TClk
TClk
TClk
TClk
TClk
TClk
Polling Mode
Sleep time
(see
Figure 8-1,
7.1
Figure 8-10
and
Figure 13-1)
8
Min.
Symbol
Basic Clock Cycle of the Digital Circuitry
Extended
6.2 basic clock
cycle
7
Test
Conditions
fRF = 868.3 MHz,
fRF = 433.92 MHz
13.52875 MHz Oscillator 13.55234 MHz Oscillator
TStartup
Average
bit-check time
while polling,
no RF applied
(see Figure 8-8
on page 16
and Figure 8-9
on page 17)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TBit-check
Bit-check time
for a valid input
signal fSig (see
Figure 8-5 on
page 15)
NBit-check = 0
NBit-check = 3
NBit-check = 6
NBit-check = 9
TBit-check
C
ms
ms
ms
ms
0.45
0.24
0.14
0.08
0.45
0.24
0.14
0.08
0.45
0.24
0.14
0.08
C
1 × TXClk
3/fSig
6/fSig
9/fSig
1 × TXClk 1 × TXClk
3.5/fSig
3/fSig
6.5/fSig
6/fSig
9.5/fSig
9/fSig
1 × TXClk 1 × TXClk
3.5/fSig
3/fSig
6.5/fSig
6/fSig
9.5/fSig
9/fSig
1 × TClk
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
Receiving Mode
Intermediate
frequency
Baud-rate
8.2
range
fIF
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range
987
1.0
1.8
3.2
5.6
fIF = fLO/438 for the 433.92 MHz
band (ATA5724)
fIF = fLO/915 for the 868.3 MHz band
(ATA5728)
947.9
1.8
3.2
5.6
10.0
1.0
1.8
3.2
5.6
1.8
3.2
5.6
10.0
BR_Range0 ×
BR_Range1 ×
BR_Range2 ×
BR_Range3 ×
2 µs/TClk
2 µs/TClk
2 µs/TClk
2 µs/TClk
kHz
A
kBit/s
kBit/s
kBit/s
kBit/s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
37
9106E–RKE–07/08
18. Electrical Characteristics ATA5724, ATA5728 (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 868.3 MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
No. Parameter
Minimum
time period
between
edges at pin
DATA
(see Figure
8.3 4-2 and
Figure 8-8,
Figure 8-9)
(With the
exception of
parameter
TPulse)
Maximum
Low period at
8.4 pin DATA
(see
Figure 4-2)
Test
Conditions
fRF = 433.92 MHz
fRF = 868.3 MHz,
13.52875 MHz Oscillator 13.55234 MHz Oscillator
Symbol
Min.
Typ.
Typ.
Max.
Min.
Min.
Typ.
Max.
Unit Type*
165.5
82.8
41.4
20.7
165.5
82.8
41.4
20.7
165.3
82.6
41.3
20.6
165.3
82.6
41.3
20.6
10 ×
10 ×
10 ×
10 ×
TXClk
TXClk
TXClk
TXClk
10 ×
10 ×
10 ×
10 ×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
2152
1076
538
269
2152
1076
538
269
2148
1074
537
268.5
2148
1074
537
268.5
130 ×
130 ×
130 ×
130 ×
TXClk
TXClk
TXClk
TXClk
130 ×
130 ×
130 ×
130 ×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
21.7
19.6
21.7
10.5 × TClk
µs
A
µs
A
µs
A
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
tDATA_min
tDATA_L_max
Delay to
activate the
8.5 start-up
mode (see
Figure 8-12)
Ton1
19.6
OFF
command at
pin
8.6
POLLING/
_ON (see
Figure 8-11)
Ton2
16.5
Delay to
activate the
8.7 sleep mode
(see
Figure 8-11)
Ton3
17.6
19.6
17.6
19.6
16.557
8.278
4.139
2.069
16.557
8.278
4.139
2.069
16.528
8.264
4.132
2.066
16.528
8.264
4.132
2.066
Pulse on pin
DATA at the
end of a data
8.8
stream
(see
Figure 10-3)
Variable Oscillator
Max.
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
TPulse
9.5 × TClk
8 × TClk
16.5
8.5 × TClk
8×
4×
2×
1×
TClk
TClk
TClk
TClk
9.5 × TClk
8×
4×
2×
1×
TClk
TClk
TClk
TClk
µs
µs
µs
µs
A
A
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
38
ATA5723/ATA5724/ATA5728
9106E–RKE–07/08
ATA5723/ATA5724/ATA5728
18. Electrical Characteristics ATA5724, ATA5728 (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 868.3 MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
No. Parameter
9
Test
Conditions
fRF = 433.92 MHz
fRF = 868.3 MHz,
13.52875 MHz Oscillator 13.55234 MHz Oscillator
Symbol
Min.
Typ.
Max.
Min.
Typ.
Variable Oscillator
Max.
Min.
1/
(4096 ×
TClk)
Typ.
Max.
Unit Type*
Configuration of the Receiver (see Figure 12-1 and Figure 13-1)
Frequency is
Frequency of
stable within
9.1 the reset
50 ms after
marker
POR
BR_Range =
BR_Range0
Programming BR_Range1
9.2
BR_Range2
start pulse
BR_Range3
after POR
fRM
t1
117.9
117.9
118.2
118.2
3361
2276
1734
1463
16425
11656
11656
11656
11656
3355
2272
1731
1460
11636
11636
11636
11636
1624 ×
TClk
1100 ×
TClk
838 × TClk
707 × TClk
7936 ×
TClk
1/
(4096 ×
TClk)
5632 ×
5632 ×
5632 ×
5632 ×
TClk
TClk
TClk
TClk
Hz
µs
µs
µs
µs
µs
A
A
9.3
Programming
delay period
t2
796
798
794
796
384.5 ×
TClk
385.5 ×
TClk
µs
A
9.4
Synchronization pulse
t3
265
265
264
264
128 × TClk
128 × TClk
µs
A
Delay until of
9.5 the program
window starts
t4
131
131
131
131
63.5 × TClk
63.5 × TClk
µs
A
9.6
Programming
window
t5
530
530
529
529
256 × TClk
256 × TClk
µs
A
9.7
Time frame
of a bit
t6
1060
1060
1058
1058
512 × TClk
512 × TClk
µs
A
9.8
Programming
pulse
t7
132
530
132
529
64 × TClk
256 × TClk
µs
C
Equivalent
9.9 acknowledge
pulse: E_Ack
t8
265
265
264
264
128 × TClk
128 × TClk
µs
A
t9
534
534
533
533
258 × TClk
258 × TClk
µs
A
t10
930
930
929
929
449.5 ×
TClk
449.5 ×
TClk
µs
A
0
0
0
0
16.557
8.278
4.139
2.069
0
0
0
0
16.528
8.264
4.132
2.066
0
0
0
0
1×
1×
1×
1×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
C
66.2
33.1
16.5
8.3
62.2
33.1
16.5
8.3
66.1
33.0
16.5
8.25
66.1
33.0
16.5
8.25
TXClk
TXClk
TXClk
TXClk
4×
4×
4×
4×
TXClk
TXClk
TXClk
TXClk
µs
µs
µs
µs
9.10
Equivalent
time window
OFF-bit
9.11 programming
window
10 Data Clock (see Figure 9-1 and Figure 9-6)
Minimum
delay time
between
10.1
edge at DATA
and
DATA_CLK
Pulse width
of negative
10.2
pulse at pin
DATA_CLK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
tDelay2
tP_DATA_CLK
4×
4×
4×
4×
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
39
9106E–RKE–07/08
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