ATA5774C-PXQW-1

ATA5771C/73C/74C UHF ASK/FSK Transmitter with the Atmel AVR Microcontroller DATASHEET General Features ● Atmel® AVR® microcontroller and RF transmitter PLL in a single QFN24 5mm × 5mm package (pitch 0.65mm) ● Operating frequency ranges 310MHz to 350MHz, 429MHz to 439MHz and 868MHz to 928MHz ● Temperature range –40°C to +85°C ● Supply voltage 2.0V to 3.6V allowing usage of single Li-cell power supply ● Low power consumption ● Active mode: typical 9.8mA at 3.0V and 4MHz microcontroller-clock ● Power-down mode: Typical 200nA at 3.0V ● Modulation scheme ASK/FSK ● Integrated PLL loop filter ● Output power of 8dBm at 315MHz / 7.5dBm at 433.92MHz / 5.5dBm at 868.3MHz ● Easy to design-in due to excellent isolation of the PLL from the PA and power supply ● Single-ended antenna output with high efficient power amplifier ● Very robust ESD protection: HBM 2500V, MM100V, CDM 1000V ● High performance, low power AVR 8-bit microcontroller ● Advanced RISC architecture ● Non-volatile program and data memories ● 4Kbytes of in-system programmable program memory flash ● 256Bytes in-system programmable EEPROM ● 256Bytes internal SRAM ● Programming lock for self-programming flash program and EEPROM data security ● Peripheral features ● ● ● ● ● Two timer/counter, 8- and 16-bit counters with two PWM channels on both 10-bit ADC On-chip analog comparator Programmable watchdog timer with separate on-chip oscillator Universal serial interface (USI) 9137J-RKE-10/14 ● Special microcontroller features ● ● ● ● ● ● ● ● debugWIRE on-chip debug system In-system programmable via SPI port External and internal interrupt sources Pin change interrupt on 12 pins Enhanced power-on reset circuit Programmable brown-out detection circuit Internal calibrated oscillator On-chip temperature sensor ● 12 programmable I/O lines 2 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 1. General Description The Atmel® ATA5771C/73C/74C is a highly flexible programmable transmitter containing the Atmel AVR® microcontroller Atmel ATtiny44V and the UHF PLL transmitters in a small QFN24 5mm × 5mm package. This device is a member of a transmitter family covering several operating frequency ranges, which has been specifically developed for the demands of RF low-cost data transmission systems with data rates up to 32kBit/s using ASK or FSK modulation. Its primary applications are in the application of Remote Keyless-Entry (RKE), Passive Entry Go (PEG) System and Remote Start. The ATA5771 is designed for 868MHz application, whereas ATA5773 for 315MHZ application and ATA5774 for 434MHz application. Figure 1-1. ASK System Block Diagram UHF ASK/FSK Remote Control Transmitter Atmel ATA577x S1 PXY VDD S1 PXY GND S1 PXY PXY PXY PXY PXY PXY PXY PXY PXY PXY Power up/down CLK f/4 PLL VS ENABLE UHF ASK/FSK Remote Control Receiver GND_RF 1 to 6 Demod XTO VCO VCC_RF Control Microcontroller VS Antenna PA_ENABLE PLL XTO ANT2 PA Loop Antenna LNA ANT1 VCO VS ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 3 Figure 1-2. FSK System Block Diagram UHF ASK/FSK Remote Control Transmitter Atmel ATA577x S1 PXY VDD S1 PXY GND S1 PXY PXY PXY PXY PXY PXY PXY PXY PXY PXY Power up/down CLK f/4 PLL VS ENABLE UHF ASK/FSK Remote Control Receiver GND_RF 1 to 6 Control Demod XTO VCO VCC_RF VS Antenna PA_ENABLE PLL ANT2 PA Loop Antenna LNA ANT1 VS 4 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 VCO XTO Microcontroller Pin Configuration Table 2-1. GND ENABLE GND_RF VS_RF XTAL GND Figure 2-1. Pinning QFN24 5mm × 5mm 24 23 22 21 20 19 18 17 PA1 3 16 PA2 PB3/RESET 4 15 PA3/T0 PB2 5 14 PA4/USCK PA7 6 PA5/MISO 7 8 9 10 11 13 12 GND 2 PB1 ANT1 PB0 ANT2 PA0 PA_ENABLE 1 CLK VCC PA6/MOSI 2. Pin Description Pin Symbol 1 VCC Microcontroller supply voltage 2 PB0 Port B is a 4-bit bi-directional I/O port with internal pull-up resistor 3 PB1 Port B is a 4-bit bi-directional I/O port with internal pull-up resistor 4 PB3/RESET 5 PB2 Port B is a 4-bit bi-directional I/O port with internal pull-up resistor 6 PA7 Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 7 PA6 / MOSI Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 8 CLK 9 Function Port B is a 4-bit bi-directional I/O port with internal pull-up resistor/reset input Clock output signal for microcontroller. The clock output frequency is set by the crystal to fXTAL/4 PA_ENABLE Switches on power amplifier. Used for ASK modulation 10 ANT2 Emitter of antenna output stage 11 ANT1 Open collector antenna output 12 GND Ground 13 PA5/MISO Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 14 PA4/SCK Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 15 PA3/T0 Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 16 PA2 Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 17 PA1 Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 18 PA0 Port A is an 8-bit bi-directional I/O port with internal pull-up resistor 19 GND Microcontroller ground 20 XTAL Connection for crystal 21 VS_RF 22 GND_RF Transmitter ground 23 ENABLE Enable input 24 GND Ground GND Ground/backplane (exposed die pad) Transmitter supply voltage ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 5 2.1 Pin Configuration of RF Pins Table 2-2. Pin Pin Description Symbol Function Configuration VS Clock output signal for microcontroller. 8 CLK 100Ω CLK The clock output frequency is set by the crystal to fXTAL/4. 100Ω 9 PA_ENABLE Switches on power amplifier. PA_ENABLE UREF = 1.1V 50kΩ Used for ASK modulation. 20μA 10 ANT2 Emitter of antenna output stage. 11 ANT1 Open collector antenna output. ANT1 ANT2 VS VS 1.5kΩ 20 XTAL Connection for crystal. XTAL 182μA 6 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 1.2kΩ Table 2-2. Pin Description (Continued) Pin Symbol 21 VS 22 GND 23 ENABLE Function Configuration Supply voltage See ESD protection circuitry (see Figure 5-1 on page 155). Ground See ESD protection circuitry (see Figure 5-1 on page 155). Enable input ENABLE 200kΩ ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 7 3. Functional Description Figure 1-1 on page 3 and Figure 1-2 on page 4 show the interconnections between the microcontroller and the RF part for a typical application. In the recommended application circuits the clock output of the RF transmitter is connected to the microcontroller in order to be able to generate data rate with tolerance lower than 3%. The transmitter’s crystal oscillator (XTO), phase locked loop (PLL) and clock generation are started using pin ENABLE. The power amplifier (PA) is activated using the connection to the pin PA_ENABLE. The FSK modulation is performed due to pulling of the crystal load capacitance for this purpose the microcontroller out put port together with an external switch applies this modulation technique. For the ASK modulation the power amplifier will be switched on and of by modulating the PA_ENABLE pin due to the data. To wake up the system from standby mode at least one event is required, which will be performed by pushing tone button. After this event the microcontroller starts up with the internal RC oscillator. For the TX operation the user software must additionally control just 2 pins, the pin ENABLE and pin PA_ENABLE. In case of the FSK modulation one additional connection from microcontroller is necessary to perform the pulling of the crystal load capacitance. If ENABLE and PA_ENABLE are set to LOW the transmitter is in standby mode with the suitable mode setting of the microcontroller (MCU) the power consumption will be reduced. If ENABLE is set to HIGH and PA_ENABLE to LOW, the XTO, PLL, and the Clock driver of the RF transmitter are activated and the VCO frequency is 32 times the XTO frequency. The Atmel ATA5771 and Atmel ATA5774 require typically shorter than 1 ms until the PLL is locked and the transmitter’s clock output is stable, while the Atmel ATA5773 requires time shorter than 3 ms for this progress. If both ENABLE and PA_ENABLE are set to HIGH the whole RF transmitter (XTO, PLL, Clock driver and power Amplifier) is activated. The ASK modulation is achieved by switching on and off the power amplifier via pin PA_ENABLE. The FSK modulation is performed by pulling the crystal load capacitor which will change the reference frequency of the PLL due to the data. The microcontroller modulates the load capacitance of the crystal using an external switch. A MOS transistor with a low parasitic capacitance is recommended to be used for this purpose. During the FSK modulation is the PA_ENABLE pin set to HIGH. To generate the data for the telegram the internal RC oscillator of the microcontroller is not accurate enough because this will be affected by ambient temperature and operating voltage. To reduce the variation of the data rate lower than 3% the clock frequency generated by the RF transmitter should be used as a reference. The MCU has to wait at least longer than 3ms for ATA5773 after setting ENABLE to HIGH, before the clock output from the RF transmitter can be used. For ATA5771 and ATA5774 the MCU must wait longer than 1 ms until the clock output is stable. The clock output with the crystal tolerance is connected to the timer0 of the MCU. This timer clocks the USI to generate the data rate. In the Two serial synchronous data transfer modes will be provided by USI. This will be pass out with different physical I/O ports, two wire mode is used for ASK and the three wire mode for FSK. 3.1 Frequency Generation In Atmel ATA5773 and Atmel ATA5774 the VCO is locked to 32 times crystal frequency hence the following crystal is needed ● 9.8438MHz for 315MHz application ● 13.56MHz for 433.92MHz application The VCO of ATA5771 is locked to 64 times crystal frequency therefore the necessary crystal frequency is ● 13.5672MHz for 868.3MHz application ● 14.2969MHz for 915MHz application Due to the high integration the PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator that only one capacitor together with a crystal connected in series to GND are needed as external elements. Until the PLL and clock output is stable the following time can be expected ● 3ms for ATA5773 ● 1ms for ATA5771 and ATA5774 Therefore, a time delay of ≥ 3 ms for ATA5773 and ≥ 1ms for ATA5771/74 between activation of pin ENABLE and switching on the pin PA_ENABLE must be implemented in the software. 8 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 3.2 ASK Transmission The ASK modulation will performed by switching the power amplifier on and of due to the data to be transmitted. The transmitter’s XTO and PLL are activated by setting the pin ENABLE to HIGH. Between the activation of the pin ENABLE and the pin PA_ENABLE minimum 3ms time delay must be taken into account for the application with ATA5773, whereas a minimum 1ms time delay for an application using ATA5771 or ATA5774. After the mentioned time delay the generated clock frequency by the RF transmitter can be used as reference for the data generation of the microcontroller block. 3.3 FSK Transmission The transmitter’s XTO and PLL are activated by setting the pin ENABLE to HIGH. Like the ASK transmission a defined time delay must be taken into account between the activation of the pin ENABLE and the pin PA_ENABLE. After this time delay the clock frequency can be used as reference for the data rate generation and the data transmission using FSK modulation is ready. For this purpose an additional capacitor to the crystal’s load capacitor will be switched between the high impedance and ground due to the data rate. Thus the reference frequency, which is crystal frequency, of the RF transmitter will be modulated. This results also in the transmitted spectrum. It is important that the switching element must have a defined low parasitic capacitance. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered. Figure 3-1. Tolerances of Frequency Modulation VS CStray1 CStray2 LM C4 XTAL CM RS C0 Crystal equivalent circuit C5 CSwitch Using C4 = 8.2pF ±5%, C5 = 10pF ±5%, a switch port with CSwitch = 3pF ±10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1pF ±10%, a parallel capacitance of the crystal of C0 = 3.2pF ±10% and a crystal with CM = 13fF ±10%, results in a typical FSK deviation of ±21.5kHz with worst case tolerances of ±16.25kHz to ±28.01kHz. 3.4 CLK Output RF transmitter generated clock signal based on the devided crystal frequency. This will be available for the microcontroller as reference. The delivered signal is CMOS compatible if the load capacitance is lower than 10pF. 3.4.1 Clock Pulse Take-over The clock of the crystal oscillator can be used for clocking the microcontroller, which starts with an integrated RC-oscillator. After the generated clock signal of the RF transmitter is stable, the microcontroller will take over the clock signal and use it as reference generating the data rate, so that the message can be transmitted with crystal accuracy. ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 9 3.4.2 Output Matching and Power Setting The power amplifier is an open-collector output delivering a current pulse, which is nearly independent from the load impedance. Thus the delivered output power can be tuned via the load impedance of the antenna and the matching elements. This output configuration enables simple matching to any kind of antenna or to 50Ω which results in a high power efficiency {η = Pout/(IS,PA VS) }. The maximum output power can be achieved at 3V supply voltage when the load impedance is optimized to ● ZLoad = (255 + j192)Ω for the Atmel ATA5773 with the power efficiency of 40% ● ● ZLoad = (166 + j223)Ω for the Atmel ATA5774 with the power efficiency of 36% ● ● Background: The current pulse of the power amplifier is 9mA and the maximum output power is delivered to a resistive load of 400Ω if the 1.0pF output capacitance of the power amplifier is compensated by the load impedance. And thus the load impedance of ZLoad = 400Ω || j/(2 × π × f × 1.0pF) = (255 + j192)Ω is achieved for the maximum output power of 8dBm. Background: The current pulse of the power amplifier is 9mA and the maximum output power is delivered to a resistive load of 465Ω if the 1.0pF output capacitance of the power amplifier is compensated by the load impedance. And thus the load impedance of ZLoad = 465Ω || j/(2 × π × f × 1.0pF) = (166 + j223)Ω is achieved for the maximum output power of 7.5dBm. ZLoad = (166 + j226)Ω for the Atmel ATA5771 with the power efficiency of 24% ● Background: The current pulse of the power amplifier is 7.7mA and the maximum output power is delivered to a resistive load of 475Ω if the 0.53pF output capacitance of the power amplifier is compensated by the load impedance. And thus the load impedance of ZLoad = 475Ω || j/(2 × π × f × 0.53pF) = (166 + j226)Ω is achieved for the maximum output power of 5.5dBm. The load impedance is defined as the impedance seen from the power amplifier (pin ANT1 and pin ANT2) into the matching network. This large signal load impedance should not be mixed up with the small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC, instead of from the IC into the application. Please take note that there must be a low resistive path between the VS and the collector output of the PA to deliver the DC current. Reduced output power will be achieved by lowering the real parallel part of the load impedance where the parallel imaginary part should be kept constant. Output power measurement can be performed using the circuit shown in Figure 3-2. Note that the component values must be changed to compensate for the individual board parasitics until the RF power amplifier has the right load impedance. In addition, the damping of the cable used to measure the output power must be calibrated out. Figure 3-2. Output Power Measurement Atmel ATA5771C/73C/74C VS C1 = 1nF L1 = 47nH Z = 50Ω ANT1 ZLopt ANT2 10 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 Power meter C2 = 3.3pF Rin 50Ω 4. Microcontroller Block These data are referred to the data base of microcontroller Atmel ATtiny44V. 4.1 Overview The ATtiny44V is a low-power CMOS 8-bit microcontroller based on the Atmel AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny44V achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 4-1. Block Diagram VCC 8-bit Databus Internal Oscillator Internal Calibrated Oscillator Timing and Control GND Program Counter Stack Pointer Watchdog Timer Program Flash SRAM MCU Control Register Instruction Register General Purpose Registers MCU Status Register Timer/ Counter0 X Y Z Instruction Decoder Timer/ Counter1 Control Lines ALU Status Register Interrupt Unit Analog Comparator Programming Logic + - 4.2 ISP Interface Data Register Port A Data Direction Register Port A EEPROM ADC Oscillators Data Register Port B Data Register Port B Port A Drivers Port B Drivers PA7 to PA0 PB3 to PB0 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 11 The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATtiny44V provides the following features: 4K byte of In-System Programmable Flash, 256 bytes EEPROM, 256 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable watchdog timer with internal oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, analog comparator, and interrupt system to continue functioning. The powerdown mode saves the register contents, disabling all chip functions until the next interrupt or hardware reset. The ADC noise reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using the Atmel high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core. The ATtiny44V AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 4.3 Automotive Quality Grade The ATtiny44V have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949 grade 1. This datasheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the ATtiny44V have been verified during regular product qualification as per AEC-Q100. As indicated in the ordering information paragraph, the product is available in only one temperature grade. Table 4-1. 12 Temperature Grade Identification for Automotive Products Temperature Temperature Identifier –40°C; +125°C Z ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 Comments Full automotive temperature range 4.4 Pin Descriptions 4.4.1 VCC Supply voltage. 4.4.2 GND Ground. 4.4.3 Port B (PB3...PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the Atmel ATtiny44V as listed on Section 4.14.3 “Alternate Port Functions” on page 57. 4.4.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Figure 4-13 on page 39. Shorter pulses are not guaranteed to generate a reset. 4.4.5 Port A (PA7...PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in Section 4.14.3 “Alternate Port Functions” on page 57. 4.5 Resources A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4.6 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 13 4.7 CPU Core 4.7.1 Overview This section discusses the Atmel AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.7.2 Architectural Overview Figure 4-2. Block Diagram of the Atmel AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registers Control Lines Indirect Addressing Instruction Decoder Direct Addressing Instruction Register Interrupt Unit Watchdog Timer ALU Analog Comparator Timer/Counter0 Data SRAM Timer/Counter1 Universal Serial Interface EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable flash memory. The fast-access register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle. 14 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most Atmel AVR® instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the data space locations following those of the register File, 0x20 - 0x5F. 4.7.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 4.7.4 Status Register The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 15 4.7.4.1 SREG – AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0xSF) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕V The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The negative flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The zero flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 16 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 4.7.5 General Purpose Register File The register file is optimized for the Atmel® AVR® enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file: ● One 8-bit output operand and one 8-bit result input ● ● ● Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Figure 4-3 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-3. Atmel AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-3, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 17 4.7.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-4 on page 18. Figure 4-4. The X-, Y-, and Z-registers 15 X-register XH XL 7 R27 (0x1B) YH YL 7 0 0 7 R29 (0x1D) 0 R28 (0x1C) 15 Z-register 0 R26 (0x1A) 15 Y-register 0 0 7 ZH ZL 7 0 0 7 R31 (0x1F) 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the “Instruction Set Reference” for details). 4.7.6 Stack Pointer The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The stack pointer register always points to the top of the stack. Note that the stack is implemented as growing from higher memory locations to lower memory locations. This implies that a stack PUSH command decreases the stack pointer. The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above 0x60. The stack pointer is decremented by one when data is pushed onto the stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. The stack pointer is incremented by one when data is popped from the stack with the POP instruction, and it is incremented by two when data is popped from the stack with return from subroutine RET or return from interrupt RETI. The Atmel AVR® stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH register will not be present. 4.7.6.1 SPH and SPL – Stack Pointer High and Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value 18 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 4.7.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The Atmel® AVR® CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-6 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.7.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete list of vectors is shown in Section 4.12 “Interrupts” on page 47. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the external interrupt request 0. When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt flag. For these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. ATA5771C/73C/74C [DATASHEET] 9137J–RKE–10/14 19 The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the Atmel AVR® exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1