ATA6562/3
High-Speed CAN Transceiver with Standby Mode
Features
General Description
• Fully ISO 11898-2, ISO 11898-2: 2016 and
SAE J2962-2 Compliant
• CAN FD Ready
• Communication Speed up to 5 Mbps
• Low Electromagnetic Emission (EME) and High
Electromagnetic Immunity (EMI)
• Differential Receiver with Wide Common Mode
Range
• ATA6562: Silent Mode
• Remote Wake-Up Capability via CAN Bus Wake-Up on Pattern (WUP), as Specified in
ISO 11898-2: 2016, 3.8 µs Activity Filter Time
• Functional Behavior Predictable under All Supply
Conditions
• Transceiver Disengages from the Bus When Not
Powered Up
• RXD Recessive Clamping Detection
• High Electrostatic Discharge (ESD) Handling
Capability on the Bus Pins
• Bus Pins Protected Against Transients in
Automotive Environments
• Transmit Data (TXD) Dominant Time-Out
Function
• Undervoltage Detection on VCC and VIO Pins
• CANH/CANL Short-Circuit and Overtemperature
Protected
• Fulfills the OEM “Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive Applications, Rev. 1.3"
• Qualified According to AEC-Q100 and AEC-Q006
• Two Ambient Temperature Grades Available:
- ATA6562-GAQW1, ATA6563-GAQW1,
ATA6562-GBQW1 and ATA6563-GBQW1 up
to Tamb = +125°C
- ATA6562-GAQW0, ATA6563-GAQW0,
ATA6562-GBQW0 and ATA6563-GBQW0 up
to Tamb = +150°C
• Packages: SOIC8, VDFN8 with Wettable Flanks
(Moisture Sensitivity Level 1)
The ATA6562/ATA6563 is a high-speed CAN
transceiver that provides an interface between a
controller area network (CAN) protocol controller and
the physical two-wire CAN bus.
Applications
The transceiver is designed for high-speed (up to
5 Mbps) CAN applications in the automotive industry,
providing differential transmit and receive capability to
(a microcontroller with) a CAN protocol controller. It
offers improved electromagnetic compatibility (EMC)
and electrostatic discharge (ESD) performance, as well
as features such as:
• Ideal passive behavior to the CAN bus when the
supply voltage is off
• Direct interfacing to microcontrollers with supply
voltages from 3V to 5V (ATA6563)
Three operating modes together with the dedicated
fail-safe features make the ATA6562/ATA6563 an
excellent choice for all types of high-speed CAN
networks, especially in nodes requiring low-power
mode with wake-up capability via the CAN bus.
Package Types
ATA6562
SOIC
ATA6563
SOIC
TXD 1
8 STBY
TXD 1
8 STBY
GND 2
7 CANH
GND 2
7 CANH
VCC 3
6 CANL
VCC 3
6 CANL
RXD 4
5 NSIL
RXD 4
5 VIO
ATA6563
3 x 3 VDFN* with
wettable flanks
ATA6562
3 x 3 VDFN* with
wettable flanks
TXD
1
8
STBY
TXD
1
8
STBY
GND
2
7
CANH
GND
2
7
CANH
VCC
3
6
CANL
VCC
3
6
CANL
RXD
4
5
NSIL
RXD
4
5
VIO
*Includes Exposed Thermal Pad (EP); see Table 1-2.
Classical CAN and CAN FD networks in Automotive,
Industrial, Aerospace, Medical and Consumer
applications.
2017-2020 Microchip Technology Inc.
DS20005790D-page 1
ATA6562/3
ATA6562/ATA6563 Family Members
Device
VIO Pin
NSIL
Grade 0
ATA6562-GAQW0
X
X
ATA6562-GAQW1
X
ATA6562-GBQW0
X
ATA6562-GBQW1
X
ATA6563-GAQW0
X
ATA6563-GAQW1
X
ATA6563-GBQW0
X
ATA6563-GBQW1
X
Note:
Grade 1
VDFN8
X
X
X
X
Standby mode and Silent mode
X
Standby mode and Silent mode
X
Standby mode and Silent mode
Standby mode and Silent mode
X
X
Description
X
X
X
SOIC8
X
Standby mode, VIO - pin for
compatibility with 3.3V and 5V
microcontroller
X
Standby mode, VIO - pin for
compatibility with 3.3V and 5V
microcontroller
X
Standby mode, VIO-pin for
compatibility with 3.3V and 5V
microcontroller
X
Standby mode, VIO - pin for
compatibility with 3.3V and 5V
microcontroller
For ordering information, see the Product Identification System section.
DS20005790D-page 2
2017-2020 Microchip Technology Inc.
ATA6562/3
Functional Block Diagram
V,2
(1)
5
V&&
3
VCC
Temperature
Protection
VIO(1)
TXD
TXD
Time-OutTimer
1
7
Slope Control
and
Driver
6
VIO(1)
STBY
CANH
CANL
8
VIO(1)
Control Unit
(1)
NSIL
5
VIO(
HSC(2)
RXD
4
MUX
Wake-up
Filter
WUC(3)
2
GND
Notes: 1. Pin 5: ATA6563: VIO
ATA6562: NSIL (the VIO line and the VCC line are internally connected)
2. HSC: High-speed comparator
3. WUC: Wake-up comparator
2017-2020 Microchip Technology Inc.
DS20005790D-page 3
ATA6562/3
1.0
FUNCTIONAL DESCRIPTION
The ATA6562/ATA6563 is a stand-alone dual
high-speed CAN transceiver compliant with the
ISO 11898-2, ISO 11898-2: 2016, ISO 11898-5 and
SAE J2962-2 CAN standards. It provides a very low
current consumption in Standby mode and wake-up
capability via the CAN bus. There are two versions
available, only differing in the function of pin 5:
• ATA6562: The pin 5 is the control input for Silent
mode NSIL, allowing the ATA6562 to only receive
data but not send data via the bus. The output
driver stage is disabled. The VIO line and the
VCC line are internally connected, this sets the
signal levels of the TXD, RXD, STBY, and NSIL
pins to levels compatible with 5V microcontrollers.
FIGURE 1-1:
• ATA6563: The pin 5 is the VIO pin and should be
connected to the microcontroller supply voltage.
This allows direct interfacing to microcontrollers
with supply voltages down to 3V and adjusts the
signal levels of the TXD, RXD, and STBY pins to
the I/O levels of the microcontroller. The I/O ports
are supplied by the VIO pin.
1.1
Operating Modes
Each of the transceivers supports three operating
modes: Unpowered, Standby and Normal. The
ATA6562 additionally has the Silent mode. These
modes can be selected via the STBY and NSIL pin.
See Figure 1-1 and Table 1-1 for a description of the
operating modes.
OPERATING MODES
ATA6562
VCC < Vuvd(VCC)
ATA6563
VCC < Vuvd(VCC)
Unpowered
Mode
VCC < Vuvd(VCC)
VCC < Vuvd(VCC) or
VIO < Vuvd(VIO)
VCC < Vuvd(VCC) or
VIO < Vuvd(VIO)
VCC > Vuvd(VCC)
STBY = 1
STBY = 1
STBY = 1
Standby
Mode
STBY = 0 and
NSIL = 1 and
TXD = 1 and
Error = 0
NSIL = 1 and TXD = 1 and Error = 0
Silent
Mode
VCC > Vuvd(VCC) or
VIO > Vuvd(VIO)
STBY = 1
Standby
Mode
STBY = 0 and
(NSIL = 0 or
TXD = 0)
VCC < Vuvd(VCC) or
VIO < Vuvd(VIO)
Unpowered
Mode
STBY = 0 and
TXD = 0
Normal
Mode
STBY = 0 and
TXD = 1 and
Error = 0
TXD = 1 and Error = 0
Silent
Mode *
Normal
Mode
Error = 1
NSIL = 0 or Error = 1
* Silent Pode is externally not accessible
Note: For the ATA6563 NSIL is internally set to “1”.
TABLE 1-1:
OPERATING MODES
Mode
Unpowered
Standby
Inputs
STBY
X(3)
HIGH
NSIL
Outputs
CAN Driver
Pin RXD
X
(3)
X
Recessive
Recessive
X(3)
X(3)
Recessive
Active(4)
(3)
Recessive
Active(1)
(3)
PIN TXD
Silent (only for ATA6562)
LOW
LOW
Normal
LOW
HIGH(2)
LOW
Dominant
LOW
LOW
HIGH(2)
HIGH
Recessive
HIGH
Note 1:
2:
3:
4:
1.1.1
X
LOW if the CAN bus is dominant, HIGH if the CAN bus is recessive.
Internally pulled up if not bonded out.
Irrelevant
Reflects the bus only for wake-up
NORMAL MODE
A low level on the STBY pin together with a high level
on pin TXD selects the Normal mode. In this mode the
transceiver is able to transmit and receive data via the
DS20005790D-page 4
CANH and CANL bus lines (see Functional Block
Diagram). The output driver stage is active and drives
data from the TXD input to the CAN bus. The
high-speed comparator (HSC) converts the analog
2017-2020 Microchip Technology Inc.
ATA6562/3
data on the bus lines into digital data which is output to
pin RXD. The bus biasing is set to VVCC/2 and the
undervoltage monitoring of VCC is active.
Please note that the device cannot enter Normal mode
as long as TXD is at ground level.
The switching into Normal mode is depicted in the
following two figures.
The slope of the output signals on the bus lines is
controlled and optimized in a way that guarantees the
lowest possible electromagnetic emission (EME).
To switch the device in normal operating mode, set the
STBY pin to low and the TXD pin to high (see Table 1-1
and Figure 1-2). The STBY pin provides a pull-up
resistor to VIO, thus ensuring a defined level if the pin
is open.
FIGURE 1-2:
SWITCHING FROM STANDBY MODE TO NORMAL MODE (NSIL = HIGH)
/
/
) '*, "%//
.(/ +/
#$)! /
!/
/
) -/
!/
!& /
!/
FIGURE 1-3:
SWITCHING FROM SILENT MODE TO NORMAL MODE
0
0
0
- + $&) 0 0
0
'(-%#0
%0
1.1.2
#-0%0
SILENT MODE (ONLY WITH THE
ATA6562)
A low level on the NSIL pin (available on pin 5) and on
the STBY pin selects Silent mode. This receive-only
2017-2020 Microchip Technology Inc.
/,0".0
0
%*" 0 %0
mode can be used to test the connection of the bus
medium. In Silent mode the ATA6562 can still receive
data from the bus, but the transmitter is disabled and
therefore no data can be sent to the CAN bus. The bus
pins are released to recessive state. All other IC
DS20005790D-page 5
ATA6562/3
functions, including the high-speed comparator (HSC),
continue to operate as they do in Normal mode. Silent
mode can be used to prevent a faulty CAN controller
from disrupting all network communications.
1.1.3
STANDBY MODE
A high level on the STBY pin selects Standby mode. In
this mode the transceiver is not able to transmit or
correctly receive data via the bus lines. The transmitter
and the high-speed comparator (HSC) are switched off
to reduce current consumption.
For ATA6562 only: In the event the NSIL input pin is set
to low in Standby mode, the internal pull-up resistor
causes an additional quiescent current from VIO to
GND. Microchip recommends setting the NSIL pin to
high in Standby mode.
1.1.3.1
Remote Wake-up via the CAN Bus
In Standby mode the bus lines are biased to ground to
reduce current consumption to a minimum. The
ATA6562/ATA6563 monitors the bus lines for a valid
FIGURE 1-4:
wake-up pattern as specified in the ISO 11898-2: 2016.
This filtering helps to avoid spurious wake-up events,
which would be triggered by scenarios such as a
dominant clamped bus or by a dominant phase due to
noise, spikes on the bus, automotive transients or EMI.
The wake-up pattern consists of at least two
consecutive dominant bus levels for a duration of at
least tFilter, each separated by a recessive bus level
with a duration of at least tFilter. Dominant or recessive
bus levels shorter than tFilter are always being ignored.
The complete dominant-recessive-dominant pattern as
shown in Figure 1-4, must be received within the bus
wake-up time-out time tWake to be recognized as a valid
wake-up pattern. Otherwise, the internal wake-up logic
is reset and then the complete wake-up pattern must
be retransmitted to trigger a wake-up event. Pin RXD
remains at high level until a valid wake-up event has
been detected.
During Normal mode, at a VCC undervoltage condition
or when the complete wake-up pattern is not received
within tWake, no wake-up is signalled at the RXD pin.
TIMING OF THE BUS WAKE-UP PATTERN (WUP) IN STANDBY MODE
When a valid CAN wake-up pattern is detected on the
bus, the RXD pin switches to low to signal a wake-up
request. A transition to Normal mode is not triggered
until the STBY pin is forced back to low by the microcontroller.
1.2
1.2.1
Fail-safe Features
TXD DOMINANT TIME-OUT
FUNCTION
A TXD dominant time-out timer is started when the
TXD pin is set to low. If the low state on the TXD pin
persists for longer than tto(dom)TXD, the transmitter is
disabled, releasing the bus lines to recessive state.
This function prevents a hardware and/or software
DS20005790D-page 6
application failure from driving the bus lines to a
permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is
reset when the the TXD pin is set to high. If the low
state on the TXD pin was longer than tto(dom)TXD, then
the TXD pin has to be set to high longer 4 µs in order to
reset the TXD dominant time-out timer..
1.2.2
INTERNAL PULL-UP STRUCTURE
AT THE TXD AND STBY INPUT PINS
The TXD and STBY pins have an internal pull-up to
VIO. This ensures a safe, defined state in case one or
both pins are left floating. Pull-up currents flow in these
2017-2020 Microchip Technology Inc.
ATA6562/3
pins in all states, meaning all pins should be in high
state during Standby mode to minimize the current
consumption.
1.2.3
UNDERVOLTAGE DETECTION ON
PIN VCC
If VVCC or VVIO drops below its undervoltage detection
levels (Vuvd(VCC) and Vuvd(VIO))(see Section 2.0,
Electrical Characteristics), the transceiver switches off
and disengages from the bus until VVCC and VVIO has
recovered. The low-power wake-up comparator is only
switched off during a VCC and VIO undervoltage. The
logic state of the STBY pin is ignored until the VVCC
voltage or VVIO voltage has recovered.
1.2.4
BUS WAKE UP ONLY AT
DEDICATED WAKE-UP PATTERN
Due to the implementation of the wake-up filtering the
ATA6562/ATA6563 does not wake-up when the bus is
in a long dominant phase, it only wakes up at a
dedicated wake-up pattern as specified in the ISO
11898-2: 2016. This means for a valid wake-up at least
FIGURE 1-5:
two consecutive dominant bus levels for a duration of
at least tFilter, each separated by a recessive bus level
with a duration of at least tFilter must be received via the
bus. Dominant or recessive bus levels shorter than
tFilter are always being ignored. The complete
dominant-recessive-dominant pattern as shown in
Figure 1-4, must be received within the bus wake-up
time-out time tWake to be recognized as a valid wake-up
pattern. This filtering leads to a higher robustness
against EMI and transients and reduces therefore the
risk of an unwanted bus wake- up significantly.
1.2.5
OVERTEMPERATURE
PROTECTION
The
output
drivers
are
protected
against
overtemperature conditions. If the junction temperature
exceeds the shutdown junction temperature, TJsd, the
output drivers are disabled until the junction
temperature drops below TJsd and pin TXD is at high
level again. The TXD condition ensures that output
driver oscillations due to temperature drift are avoided.
RELEASE OF TRANSMISSION AFTER OVERTEMPERATURE CONDITION
Failure
Overtemp
OT
Overtemperature
t
TXD
VIO
GND
t
BUS VDIFF
(CANH-CANL)
D
R
D
R
D
R
tt
RXD
VIO
GND
t
1.2.6
SHORT-CIRCUIT PROTECTION OF
THE BUS PINS
The CANH and CANL bus outputs are short-circuit
protected, either against GND or a positive supply
voltage. A current-limiting circuit protects the
transceiver against damage. If the device is heating up
2017-2020 Microchip Technology Inc.
due to a continuous short on CANH or CANL, the
internal overtemperature protection switches the bus
transmitter off.
DS20005790D-page 7
ATA6562/3
1.2.7
RXD RECESSIVE CLAMPING
This fail-safe feature prevents the controller from
sending data on the bus if its RXD is clamped to HIGH
(e.g., recessive). That is, if the RXD pin cannot
signalize a dominant bus condition because it is e.g,
shorted
to
VCC,
the
transmitter
within
ATA6562/ATA6563 is disabled to avoid possible data
collisions on the bus. In Normal and Silent mode (only
ATA6562), the device permanently compares the state
FIGURE 1-6:
1.3
of the high-speed comparator (HSC) with the state of
the RXD pin. If the HSC indicates a dominant bus state
for more than tRC_det without the RXD pin doing the
same, a recessive clamping situation is detected and
the transceiver is forced into Silent mode. This
Fail-safe mode is released by either entering Standby
or Unpowered mode or if the RXD pin is showing a
dominant (e.g., low) level again.
RXD RECESSIVE CLAMPING DETECTION
Pin Description
The descriptions of the pins are listed in Table 1-2.
TABLE 1-2:
PIN FUNCTION TABLE
ATA6562
ATA6563
Pin Name
Description
SOIC8
VDFN8
SOIC8
VDFN8
1
1
1
1
TXD
Transmit data input
2
2
2
2
GND
Ground1 supply
3
3
3
3
VCC
Supply voltage
4
4
4
4
RXD
Receive data output; reads out data from the bus lines
—
—
5
5
VIO
Supply voltage for I/O level adapter
5
5
—
—
NSIL
Silent mode control input (low active);
6
6
6
6
CANL
Low-level CAN bus line
7
7
7
7
CANH
High-level CAN bus line
8
8
8
8
STBY
—
9
—
9
EP
DS20005790D-page 8
Standby mode control input
Exposed Thermal Pad: Heat slug, internally connected to the
GND pin.
2017-2020 Microchip Technology Inc.
ATA6562/3
1.4
Typical Application
Typical Application ATA6562
5V
22 µF
(1)
+
BAT
12V
100 nF
VCC
3
VDD
STBY
NSIL
8
7
CANH
CANH
5
Microcontroller
ATA6562
TXD
RXD
GND
1
4
6
CANL
CANL
2
GND
GND
(1) The size of this capacitor depends on the used external voltage regulator
Note: For VDFN8 package: EP (heatslug) must always be connected to GND.
Typical Application ATA6563
3.3V
BAT
12V
5V
(1)
22 µF +
100 nF
12V
100 nF
VIO
5
VDD
VCC
3
7
STBY
CANH
CANH
8
Microcontroller
ATA6563
TXD
RXD
GND
1
4
6
CANL
CANL
2
GND
GND
(1) The size of this capacitor depends on the used external voltage regulator
Note: For VDFN8 package: EP (heatslug) must always be connected to GND.
2017-2020 Microchip Technology Inc.
DS20005790D-page 9
ATA6562/3
2.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
DC Voltage at CANH, CANL (VCANH, VCANL) ................................................................................................–27 to +42V
Transient Voltage at CANH, CANL (according to ISO 7637 part 2) (VCANH, VCANL) .................................–150 to +100V
Max. differential bus voltage (VDiff) ..................................................................................................................–5 to +18V
DC voltage on all other pins (VX) .................................................................................................................–0.3 to +5.5V
ESD according to IBEE CAN EMC - Test specification following IEC 61000-4-2 — Pin CANH, CANL ..................±8 kV
ESD (HBM following STM5.1 with 1.5 kΩ/100 pF) - Pins CANH, CANL to GND .................................................... ±6 kV
Component Level ESD (HBM according to ANSI/ESD STM5.1, JESD22-A114, AEC-Q100 (002) .........................±4 kV
CDM ESD STM 5.3.1 ..............................................................................................................................................±750V
ESD machine model AEC-Q100-RevF(003) ...........................................................................................................±200V
Virtual Junction Temperature (TvJ) .............................................................................................................–40 to +175°C
Storage Temperature Range (Tstg) .........................................................................................................-55°C to +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 2-1:
ELECTRICAL CHARACTERISTICS
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Sym.
Min.
Typ.
Max.
Units
VVCC
4.5
—
5.5
V
IVCC_sil
1.9
2.5
3.2
mA
Conditions
Supply, Pin VCC
Supply Voltage
Supply Current in Silent
Mode
Supply Current in Normal
Mode
Supply Current in Standby
Mode
Undervoltage Detection
Threshold on Pin VCC
Silent mode, VTXD = VVIO
IVCC_rec
2
—
5
mA
recessive, VTXD = VVIO
IVCC_dom
30
50
70
mA
dominant, VTXD = 0V
IVCC_short
—
—
85
mA
short between CANH and
CANL(Note 1)
IVCC_STBY
—
—
12
µA
VCC = VIO,
VTXD = VNSIL = VVIO
IVCC_STBY
—
7
—
µA
Ta = 25°C (Note 3)
Vuvd(VCC)
2.75
—
4.5
V
I/O Level Adapter Supply, Pin VIO (only with the ATA6563)
Supply voltage on pin VIO
VVIO
2.8
—
5.5
V
Supply current on pin VIO
IVIO_rec
10
80
250
µA
Normal and Silent mode
recessive, VTXD = VVIO
IVIO_dom
50
350
500
µA
Normal and Silent mode
dominant, VTXD = 0V
IVIO_STBY
—
—
1
µA
Standby mode
Note 1:
2:
3:
100% correlation tested
Characterized on samples
Design parameter
DS20005790D-page 10
2017-2020 Microchip Technology Inc.
ATA6562/3
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Sym.
Min.
Typ.
Max.
Units
Vuvd(VIO)
1.3
—
2.7
V
VIH
0.7VVIO
—
VVIO+0.3
V
Low-level Input Voltage
VIL
–0.3
—
0.3VVIO
V
Pull- up Resistor to VCC
Rpu
75
125
175
kΩ
VSTBY = 0V, VNSIL = 0V
IL
–2
—
+2
µA
VSTBY = VVIO, VNSIL = VVIO
High-level Input Voltage
VIH
0.7VVIO
—
VVIO+0.3
V
Low-level Input Voltage
VIL
–0.3
—
0.3VVIO
V
Pull-up Resistor to VCC
RTXD
20
35
50
kΩ
VTXD = 0V
High-level Leakage Current
ITXD
–2
—
+2
µA
Normal mode, VTXD = VVIO
Input Capacitance
CTXD
—
5
10
pF
Note 3
Undervoltage detection
threshold on pin VIO
Conditions
Mode Control Input, Pin NSIL and STBY
High-level Input Voltage
High-level Leakage Current
CAN Transmit Data Input, Pin TXD
CAN Receive Data Output, Pin RXD
High-level Output Current
IOH
–8
—
–1
mA
Normal mode,
VRXD = VVIO – 0.4V,
VVIO = VVCC
Low-level Output Current,
Bus Dominant
IOL
2
—
12
mA
Normal mode,
VRXD = 0.4V, bus dominant
VO(dom)
2.75
3.5
4.5
V
VTXD = 0V, t < tto(dom)TXD
RL = 50Ω to 65Ω
pin CANH (Note 1)
0.5
1.5
2.25
V
VTXD = 0V, t < tto(dom)TXD
RL = 50Ω to 65Ω
pin CANL (Note 1)
Bus Lines, Pins CANH and CANL
Single Ended Dominant
Output Voltage
Transmitter Voltage
Symmetry
VSym
0.9
1.0
1.1
Bus Differential Output
Voltage
VDiff
1.5
—
3
V
VTXD = 0V, t < tto(dom)TXD
RL = 45Ω to 65Ω
1.5
—
3.3
V
RL = 70Ω (Note 3)
Single Ended Recessive
Output Voltage
VO(rec)
RL = 2240Ω (Note 3)
1.5
—
5
V
–50
—
+50
mV
Normal and Silent mode:
VVCC = 4.75V to 5.25V
VTXD = VVIO, recessive, no load
–200
—
+200
mV
Standby mode:
VVCC = 4.75V to 5.25V
VTXD = VVIO, recessive, no load
0.5*
3
V
Normal and Silent mode,
VTXD = VVIO, no load
+0.1
V
Standby mode,
VTXD = VVIO, no load
2
VVCC
VO(rec)
Note 1:
2:
3:
VSym = (VCANH + VCANL) / VVCC,
Split Termination, RL = 2 x 30,
CSplit = 4.7 nF (Note 3)
–0.1
—
100% correlation tested
Characterized on samples
Design parameter
2017-2020 Microchip Technology Inc.
DS20005790D-page 11
ATA6562/3
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Differential Receiver
Threshold Voltage
Differential Receiver
Hysteresis Voltage
Dominant Output Current
Sym.
Min.
Typ.
Max.
Units
Conditions
Vth(RX)dif
0.5
0.7
0.9
V
Normal and Silent mode (HSC),
Vcm(CAN) = –27V to +27V
Vth(RX)dif
0.4
0.7
1.1
V
Standby mode (WUC),
Vcm(CAN) = –27V to
+27V(Note 1)
Vhys(RX)dif
50
120
200
mV
Normal and Silent mode (HSC),
Vcm(CAN) = –27V to +27V
(Note 1)
IIO(dom)
–75
—
–35
mA
VTXD = 0V, t < tto(dom)TXD,
VVCC = 5V
pin CANH, VCANH = –5V
35
—
75
mA
VTXD = 0V, t < tto(dom)TXD,
VVCC = 5V
pin CANL, VCANL = +40V
Recessive Output Current
IIO(rec)
–5
—
+5
mA
Normal and Silent mode,
VTXD = VVIO, no load,
VCANH = VCANL = –27V to
+32V
Leakage Current
IIO(leak)
–5
0
+5
µA
VVCC = VVIO = 0V,
VCANH = VCANL = 5V
IIO(leak)
–5
0
+5
µA
VCC = VIO connected to GND
with R = 47kΩ
VCANH = VCANL = 5V(Note 3)
Ri
9
15
28
kΩ
VCANH = VCANL = 4V
Ri
9
15
28
kΩ
–2V ≤ VCANH ≤ +7V,
–2V ≤ VCANL ≤ +7V(Note 3)
ΔRi
–1
0
+1
%
Between CANH and CANL
VCANH = VCANL = 4V (Note 1)
ΔRi
–1
0
+1
%
Between CANH and CANL
–2V ≤ VCANH ≤ +7V,
–2V ≤ VCANL ≤ +7V (Note 3)
Ri(dif)
18
30
56
kΩ
VCANH = VCANL = 4V (Note 1)
Ri(dif)
18
30
56
kΩ
–2V ≤ VCANH ≤ +7V,
–2V ≤ VCANL ≤ +7V (Note 3)
Common-mode Input
Capacitance
Ci(cm)
—
—
20
pF
f = 500 kHz, CANH and CANL
referred to GND (Note 3)
Differential Input Capacitance
Ci(dif)
—
—
10
pF
f = 500kHz, between CANH
and CANL (Note 3)
VDiff_rec
–3
—
+0.5
V
Normal and Silent mode (HSC)
–27V ≤ VCANH ≤ +27V,
–27V ≤ VCANL ≤ +27V (Note 3)
VDiff_rec
–3
—
+0.4
V
Standby mode (WUC)
–27V ≤ VCANH ≤ +27V,
–27V ≤ VCANL ≤ +27V(Note 3)
Input Resistance
Input Resistance Deviation
Differential Input Resistance
Differential Bus Voltage
Range for RECESSIVE State
Detection
Note 1:
2:
3:
100% correlation tested
Characterized on samples
Design parameter
DS20005790D-page 12
2017-2020 Microchip Technology Inc.
ATA6562/3
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Differential Bus Voltage
Range for DOMINANT State
Detection
VDiff_dom
0.9
—
8.0
V
Normal and Silent mode (HSC)
–27V ≤ VCANH ≤ +27V,
–27V ≤ VCANL ≤ +27V (Note 3)
VDiff_dom
1.15
—
8.0
V
Standby mode (WUC)
–27V ≤ VCANH ≤ +27V,
–27V ≤ VCANL ≤ +27V (Note 3)
Transceiver Timing, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3
Delay Time from TXD to Bus
Dominant
td(TXD-busdom)
40
—
130
ns
Normal mode (Note 2)
Delay Time from TXD to Bus
Recessive
td(TXD-busrec)
40
—
130
ns
Normal mode (Note 2)
Delay Time from Bus
Dominant to RXD
td(busdom-RXD)
20
—
100
ns
Normal mode (Note 2)
Delay Time from Bus
Recessive to RXD
td(busrec-RXD)
20
—
100
ns
Normal mode (Note 2)
Propagation Delay from TXD
to RXD
tPD(TXD-RXD)
40
—
210
ns
Normal mode, Rising edge at
pin TXD
RL = 60Ω, CL = 100 pF
40
—
200
ns
Normal mode, Falling edge at
pin TXD
RL = 60Ω, CL = 100 pF
—
—
300
ns
Normal mode, Rising edge at
pin TXD
RL = 150Ω, CL = 100 pF
(Note 3)
—
—
300
ns
Normal mode, Falling edge at
pin TXD
RL = 150Ω, CL = 100pF
(Note 3)
tto(dom)TXD
0.8
—
3
ms
VTXD = 0V, Normal mode
Bus Wake-up Time-Out Time
tWake
0.8
—
3
ms
Standby mode
Min. Dominant/Recessive
Bus Wake-up Time
tFilter
0.5
3
3.8
µs
Standby mode
Delay Time for Standby
Mode to Normal Mode Transition
tdel(stby-norm)
—
—
47
µs
Falling edge at pin STBY
Delay Time for Normal Mode
to Standby Mode Transition
tdel(norm-stby)
—
—
5
µs
Rising edge at pin STBY
(Note 3)
Delay time for Normal mode
to Silent mode transition
tdel(norm-sil)
—
—
10
µs
Falling edge at pin NSIL
STBY = LOW (Note 3)
Delay time for Silent mode to
Normal mode transition
tdel(sil-norm)
—
—
10
µs
Rising edge at pin NSIL
STBY = LOW (Note 3)
tPD(TXD-RXD)
TXD Dominant Time-Out
Time
Note 1:
2:
3:
100% correlation tested
Characterized on samples
Design parameter
2017-2020 Microchip Technology Inc.
DS20005790D-page 13
ATA6562/3
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Sym.
Min.
Typ.
Max.
Units
Delay time for Silent mode to
Standby mode transition
tdel(sil-stby)
—
—
5
µs
Rising edge at pin STBY
NSIL = LOW (Note 3)
Delay time for Standby mode
to Silent mode transition
tdel(stby-sil)
—
—
47
µs
Rising edge at pin STBY
NSIL = LOW (Note 3)
tRC_det
—
90
—
ns
V(CANH-CANL) > 900mV
RXD = high (Note 3)
Debouncing Time for
Recessive Clamping State
Detection
Conditions
Transceiver Timing for higher Bit Rates, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3
Recessive Bit Time on Pin
RXD
Recessive Bit Time on the
Bus
Receiver Timing Symmetry
Note 1:
2:
3:
tBit(RXD)
tBit(Bus)
ΔtRec
400
—
550
ns
Normal mode, tBit(TXD) = 500 ns
RL = 60, CL = 100 pF (Note 1)
120
—
220
ns
Normal mode, tBit(TXD) = 200 ns
RL = 60, CL = 100 pF
435
—
530
ns
Normal mode, tBit(TXD) = 500 ns
RL = 60, CL = 100 pF (Note 1)
155
—
210
ns
Normal mode, tBit(TXD) = 200 ns
RL = 60, CL = 100 pF
–65
—
+40
ns
Normal mode, tBit(TXD) = 500 ns
ΔtRec = tBit(RXD)–tBit(Bus)
RL = 60, CL = 100 pF (Note 1)
–45
—
+15
ns
Normal mode, tBit(TXD) = 200 ns
ΔtRec = tBit(RXD)–tBit(Bus)
RL = 60, CL = 100 pF
100% correlation tested
Characterized on samples
Design parameter
TABLE 2-2:
TEMPERATURE SPECIFICATIONS
Parameters
Sym.
Min.
Typ.
Max.
Units
RthvJA
—
145
—
K/W
ATA6562-GAQW1, ATA6563-GAQW1 (Grade 1)
TVJsd
150
—
195
°C
ATA6562-GAQW0, ATA6563-GAQW0 (Grade 0)
TVJsd
170
—
195
°C
TvJsd_hys
—
15
—
°C
Thermal Resistance Virtual Junction to Heat Slug
RthvJC
—
10
—
K/W
Thermal Resistance Virtual Junction to Ambient,
where Heat Slug is soldered to PCB according to
JEDEC
RthvJA
—
50
—
K/W
ATA6562-GBQW1, ATA6563-GBQW1 (Grade 1)
TVJsd
150
—
195
°C
ATA6562-GBQW0, ATA6563-GBQW0 (Grade 0)
TVJsd
170
—
195
°C
TvJsd_hys
—
15
—
°C
Thermal Characteristics SOIC8
Thermal resistance Virtual Junction to Ambient
Thermal Shutdown of the Bus Drivers
Thermal Shutdown Hysteresis
Thermal Characteristics VDFN8
Thermal Shutdown of the Bus Drivers
Thermal Shutdown Hysteresis
DS20005790D-page 14
2017-2020 Microchip Technology Inc.
ATA6562/3
FIGURE 2-1:
TIMING TEST CIRCUIT FOR THE ATA6562/3 CAN TRANSCEIVER
FIGURE 2-2:
CAN TRANSCEIVER TIMING DIAGRAM 1
HIGH
TXD
LOW
CANH
CANL
dominant
0.9V
VDiff
0.5V
recessive
HIGH
0.7 VIO
RXD
0.3 V,2
LOW
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
tPD(TXD-RXD)
2017-2020 Microchip Technology Inc.
td(busrec-RXD)
tPD(TXD-RXD)
DS20005790D-page 15
ATA6562/3
FIGURE 2-3:
DS20005790D-page 16
CAN TRANSCEIVER TIMING DIAGRAM 2
2017-2020 Microchip Technology Inc.
ATA6562/3
3.0
PACKAGING INFORMATION
Package Marking Information
8-Lead SOIC
Example
ATA6562 Grade 0
721
721
ATA6562H
1729256
ATA6562
1729256
Example
ATA6563 Grade 0
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
ATA6562 Grade 1
Example
ATA6563 Grade 1
721
721
ATA6563H
1729256
ATA6563
1729256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2017-2020 Microchip Technology Inc.
DS20005790D-page 17
ATA6562/3
8-Lead 3 X 3 mm VDFN
Example
ATA6562 Grade 0
6562H
256
Example
ATA6563 Grade 0
6563H
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005790D-page 18
Example
ATA6562 Grade 1
6562
256
Example
ATA6563 Grade 1
6563
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2017-2020 Microchip Technology Inc.
ATA6562/3
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
2017-2020 Microchip Technology Inc.
DS20005790D-page 19
ATA6562/3
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2
DS20005790D-page 20
2017-2020 Microchip Technology Inc.
ATA6562/3
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev F
2017-2020 Microchip Technology Inc.
DS20005790D-page 21
ATA6562/3
8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]
With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.10 C
1
2
2X
TOP VIEW
0.10 C
0.10 C
C
A
A1
SEATING
PLANE
8X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
1
A
2
NOTE 1
0.10
A
C A B
E2
K
N
L
8X b
e
BOTTOM VIEW
0.10
0.05
C A B
C
Microchip Technology Drawing C04-21358 Rev B Sheet 1 of 2
DS20005790D-page 22
2017-2020 Microchip Technology Inc.
ATA6562/3
8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]
With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
A4
PARTIALLY
PLATED
E3
SECTION A–A
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
Wettable Flank Step Cut Depth
A4
E3
Wettable Flank Step Cut Width
MIN
0.80
0.00
2.30
1.50
0.25
0.35
0.20
0.10
-
MILLIMETERS
NOM
8
0.65 BSC
0.85
0.03
0.203 REF
3.00 BSC
2.40
3.00 BSC
1.60
0.30
0.40
0.13
-
MAX
0.90
0.05
2.50
1.70
0.35
0.45
0.15
0.04
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21358 Rev B Sheet 2 of 2
2017-2020 Microchip Technology Inc.
DS20005790D-page 23
ATA6562/3
8-Lead Very Thin Plastic Dual Flat, No Lead Package (Q8B) - 3x3 mm Body [VDFN]
With 2.40x1.60 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Y2
EV
8
ØV
C X2
EV
CH
G1
Y1
1
2
SILK SCREEN
X1
G2
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Contact Pad to Center Pad (X8)
G1
Contact Pad to Contact Pad (X6)
G2
Pin 1 Index Chamfer
CH
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
1.70
2.50
3.00
0.35
0.80
0.20
0.20
0.20
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23358 Rev B
DS20005790D-page 24
2017-2020 Microchip Technology Inc.
ATA6562/3
APPENDIX A:
REVISION HISTORY
Revision D (June 2020)
The following is the list of modifications:
1.
2.
3.
4.
Updated parameter “Supply Current in Silent
Mode” in Table 2-1: Electrical Characteristics.
Added test conditions at several parameters in
Table 2-1: Electrical Characteristics.
Added parameter “Bus Differential Output Voltage” in Standby mode in Table 2-1: Electrical
Characteristics.
Updated Package Marking Information
Revision C (August 2019)
The following is the list of modifications:
1.
2.
Updated TABLE 2-2: “Temperature Specifications”.
Added test conditions at several parameters in
TABLE 2-1: “Electrical Characteristics”.
Revision B (August 2017)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
7.
Added new devices ATA6562-GBQW0 and
ATA6563-GBQW0 and updated the related
information across the document.
Updated Features section.
Updated ATA6562/ATA6563 Family Members
section.
Updated Table 2-2: Temperature Specifications.
Updated Package Marking Information
Updated Product Identification System section.
Various typographical edits.
Revision A (June 2017)
• Original Release of this Document.
• This document replaces Atmel - 9389C11/16ATA6562/ATA6563
2017-2020 Microchip Technology Inc.
DS20005790D-page 25
ATA6562/ATA6563
NOTES:
DS20005790D-page 26
2017-2020 Microchip Technology Inc.
ATA6562/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device
[X](1)
XX
PART NO.
X
X
Examples:
a)
ATA6562-GAQW0:
Device:
ATA6562:
ATA6563:
Package:
GA
GB
=
=
High-speed CAN Transceiver with Standby
and Silent Mode CAN FD Ready
High-speed CAN Transceiver with Standby
Mode and VIO-pin CAN FD Ready
8-Lead SOIC
8-Lead VDFN
Tape and Reel
Option:
Q
=
330 mm diameter Tape and Reel
Package
directives
classification:
W
=
Package according to RoHS(2)
Temperature
Range:
0
1
ATA6562, 8-Lead SOIC,
Tape and Reel, Package
Package Tape and Reel Package directives Temperature
Option
classification
Range
according to RoHS,
Temperature Grade 0
b)
ATA6562-GAQW1:
ATA6562, 8-Lead SOIC,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
c) ATA6562-GBQW0:
ATA6562, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Temperature Grade 0
d)
ATA6562-GBQW1:
ATA6562, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
e)
ATA6563-GAQW0:
ATA6563, 8-Lead SOIC,
Tape and Reel, Package
=
=
Temperature Grade 0 (-40°C to +150°C)
Temperature Grade 1 (-40°C to +125°C)
according to RoHS,
Temperature Grade 0
f)
ATA6563-GAQW1:
ATA6563, 8-Lead SOIC,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
f)
ATA6563-GBQW0:
ATA6563, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Temperature Grade 0
g
ATA6563-GBQW1:
ATA6563, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
Note
2017-2020 Microchip Technology Inc.
1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2:
RoHS compliant, Maximum concentration
value of 0.09% (900 ppm) for Bromine (Br)
and Chlorine (Cl) and less than 0.15% (1500
ppm) total Bromine (Br) and Chlorine (Cl) in
any homogeneous material. Maximum
concentration value of 0.09% (900 ppm) for
Antimony (Sb) in any homogeneous material.
DS20005790D-page 27
ATA6562/3
NOTES:
DS20005790D-page 28
2017-2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2017-2020 Microchip Technology Inc.
ISBN: 978-1-5224-6283-5
DS20005790D-page 29
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DS20005790D-page 30
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02/28/20
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