ATA8510-EK1

ATA8510/ATA8515 UHF ASK/FSK Transceiver DATASHEET Features ● AVR® microcontroller core with 1Kbyte SRAM and 24Kbyte RF library in firmware (ROM) ● Atmel® ATA8515: No user memory — RF library in firmware only ● Atmel ATA8510: 20Kbyte of user Flash ● Supported frequency ranges ● Low-band 310MHz to 318MHz, 418MHz to 477MHz ● High-band 836MHz to 956MHz ● 315.00MHz/433.92MHz/868.30MHz and 915.00MHz with one 24.305MHz crystal ● Low current consumption ● 9.8mA for RXMode (low-band), 1.2mA for 21ms cycle three-channel polling ● 9.4mA/13.8mA for TXMode (low-band, Pout = 6dBm/10dBm) ● Typical OFFMode current of 5nA (maximum 600nA at VS = 3.6V and T = 85°C) ● Programmable output power –12dBm to +14.5dBm (0.4dB step) ● Supports the 0dBm class of ARIB STD-T96 ● ASK shaping to reduce spectral bandwidth of modulated PA output signal ● Input 1dB compression point ● –48dBm (full sensitivity level) ● –20dBm (active antenna damping) ● Programmable channel frequency with fractional-N PLL ● 93Hz resolution for low-band ● 185Hz resolution for high-band ● FSK deviation ±0.375kHz to ±93kHz ● FSK sensitivity (Manchester coded) at 433.92MHz ● ● ● ● –108.5dBm at 20Kbit/s –111dBm at 10Kbit/s –114dBm at 5Kbit/s –122.5dBm at 0.75Kbit/s f = ±20kHz f = ±10kHz f = ±5kHz f = ±0.75kHz BWIF = 165kHz BWIF = 165kHz BWIF = 165kHz BWIF = 25kHz ● ASK sensitivity (Manchester coded) at 433.92MHz ● –110.5dBm at 20Kbit/s ● –125dBm at 0.5Kbit/s BWIF = 80kHz BWIF = 25kHz ● Programmable Rx-IF bandwidth 25kHz to 366kHz (approximately 10% steps) 9315G-INDCO-08/15 ● ● ● ● ● Blocking (BWIF = 165kHz): 64dBc at frequency offset = 1MHz and 48dBc at 225kHz High image rejection: 55dB at 315MHz/433.92MHz and 47dB at 868.3MHz/915MHz without calibration Supported data rate in buffered mode 0.5Kbit/s to 80Kbit/s (120Kbit/s NRZ) Supports pattern-based wake-up and start of frame identification Flexible service configuration concept with on-the-fly (OTF) modification (in IDLEMode) of SRAM service parameters (data rate, …) ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Each service consists of ● One service-specific configuration part ● Three channel-specific configuration parts ● Three service configurations are located in EEPROM ● Two service configurations are located in SRAM and can be modified via SPI or embedded application software Digital RSSI with very high relative accuracy of ±1dB thanks to digitized IF processing Programmable clock output derived from crystal frequency 1024byte EEPROM data memory for transceiver configuration SPI interface for Rx/Tx data access and transceiver configuration 500Kbit SPI data rate for short periods on SPI bus and host controller On demand services (SPI or API) without polling or telegram reception Integrated temperature sensor Self check and calibration with temperature measurement Configurable EVENT signal indicates the status of the IC to an external microcontroller Automatic antenna tuning at Tx center frequency for loop antenna Automatic low-power channel polling Flexible polling configuration concerning timing, order and participating channels Fast Rx/Tx reaction time Power-up (typical 1.5ms OFFMode -> TXMode, OFFMode -> RXMode) RXMode TXMode switching (typical 500µs) Supports mixed ASK/FSK telegrams Non-byte aligned data reception and transmission Software customization Antenna diversity with external switch via GPIO control Antenna diversity with internal SPDT switch Supply voltage range 1.9V to 3.6V Temperature range –40°C to +85C ESD protection at all pins (±4kV HBM, ±200V MM, ±750V FCDM) Small 55mm QFN32 package/pitch 0.5mm Suitable for applications governed by EN 300 220 and FCC part 15, title 47 Applications ● ● ● ● ● ● ● 2 Remote Control System Home and Building Automation Wireless Sensor Networks Weather stations Battery operated remote controls Smoke detectors Wireless alarm and security systems ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 1. General Description 1.1 Introduction The Atmel® ATA8510/15 is a highly integrated, low-power UHF ASK/FSK RF transceiver with an integrated AVR® microcontroller. The Atmel ATA8510/15 is partitioned into three sections; an RF front end, a digital baseband and the low-power 8-bit AVR microcontroller. The product is designed for the ISM frequency bands in the ranges of 310MHz to 318MHz, 418MHz to 477MHz and 836MHz to 956MHz. The external part count is kept to a minimum due to the very high level of integration in this device. By combining outstanding RF performance with highly sophisticated baseband signal processing, robust wireless communication can be easily achieved. The receive path uses a low-IF architecture with an integrated double quadrature receiver and digitized IF processing. This results in high image rejection and excellent blocking performance. The transmit path uses a closed loop fractional-N modulator with Gauss shaping and pre-emphasis functionality for high data rates. In addition, highly flexible and configurable baseband signal processing allows the transceiver to operate in several scanning, wake-up and automatic self-polling scenarios. For example, during polling the IC can scan for specific message content (IDs) and save valid telegram data in the FIFO buffer for later retrieval. The device integrates two receive paths that enable a parallel search for two telegrams with different modulations, data rates, wake-up conditions, etc. The Atmel ATA8510/15 implements a flexible service configuration concept and supports up to 15 channels. The channels are grouped into five service configurations with three channels each. Three service configurations are located in the EEPROM. Two service configurations are located in the SRAM to allow on-the-fly modifications during IDLEMode via SPI commands or application software. The application software is located in the Flash for Atmel ATA8510. Highly configurable and autonomous scanning capability enables flexible polling scenarios with up to 15 channels. The configuration of the transceiver is stored in a 1024byte EEPROM. The SPI interface enables external control and device reconfiguration. Table 1-1. Program Memory Comparison of Atmel ATA8510/15 Devices Device Atmel Firmware ROM User Flash User ROM Atmel ATA8515 24Kbyte - - Atmel ATA8510 24Kbyte 20Kbyte - In the Atmel ATA8510 the internal microcontroller with 20Kbyte user flash can be used to add custom extensions to the Atmel firmware. The Atmel ATA8515 embeds only the firmware ROM without user memory. The debugWIRE and ISP interface are available for programming purposes. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 3 1.2 System Overview Figure 1-1. Circuit Overview SRC, FRC Oscillators Supply Reset AVR CPU EEPROM Tx DSP Flash RF_OUT ROM RF Front End SRAM AVR Peripherals Rx DSP RFIN DATA BUS XTO XTAL Port B (8) Port C (6) PB[7..0] (SPI) PC[5..0] Figure 1-1 shows an overview of the main functional blocks of the Atmel® ATA8510/15. External control of the Atmel ATA8510/15 is performed through the SPI pins SCK, MOSI, MISO, and NSS on port B. The configuration of the Atmel ATA8510/15 is stored in the EEPROM and a large portion of the functionality is defined by the firmware located in the ROM and processed by the AVR®. An SPI command can trigger the AVR to configure the hardware according to settings that are stored in the EEPROM and start up a given system mode (e.g., RXMode, TXMode or PollingMode). Internal events such as “Start of Telegram” or “FIFO empty” are signaled to an external microcontroller on pin 28 (PB6/EVENT). During the start-up of a service, the relevant part of the EEPROM content is copied to the SRAM. This allows faster access by the AVR during the subsequent processing steps and eliminates the need to write to the EEPROM during runtime because parameters can be modified directly in the SRAM. As a consequence the user does not need to observe the EEPROM read/write cycle limitations. It is important to note that all PWRON and NPWRON pins (PC1..5, PB4, PB7) are active in OFFMode. This means that even if the Atmel ATA8510/15 is in OFFMode and the DVCC voltage is switched off, the power management circuitry within the Atmel ATA8510/15 biases these pins with VS. AVR ports can be used as button inputs, external LNA supply voltage (RX_ACTIVE), LED drivers, EVENT pin, switching control for additional SPDT switches, general purpose digital inputs, or wake-up inputs, etc. Some functionality of these ports is already implemented in the firmware and can be activated by adequate EEPROM configurations. Other functionality is available only through custom software residing in the 20Kbyte flash program memory (Atmel ATA8510). 4 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 Pinning RFIN_LB ATEST_IO1 ATEST_IO2 AGND PB7 PB6 PB5 PB4 PB3 Figure 1-2. Pin Diagram 32 31 30 29 28 27 26 25 1 RFIN_HB 2 SPDT_RX 3 exposed die pad Atmel ATA8510 ATA8515 24 PB2 23 PB1 22 PB0 21 DGND 20 DVCC PC5 RF_OUT 7 18 PC4 VS_PA 8 17 PC3 9 10 11 12 13 14 15 16 PC2 19 PC1 6 PC0 SPDT_TX VS 5 AVCC ANT_TUNE XTAL2 4 XTAL1 SPDT_ANT TEST_EN 1.3 Note: The exposed die pad is connected to the internal die. Table 1-2. Pin Description Pin No. Pin Name Type 1 RFIN_LB Analog Equivalent Circuit Description RFIN_LB (Pin 1) LNA input for low-band frequency range (< 500MHz) GND 2 RFIN_HB Analog RFIN_HB (Pin 2) LNA input for high-band frequency range (> 500MHz) GND ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 5 Table 1-2. Pin Description (Continued) Pin No. Pin Name Type 3 SPDT_RX Analog Equivalent Circuit Description SPDT_ANT (Pin 4) SPDT_RX (Pin 3) 800kΩ 4 SPDT_ANT 85Ω Antenna input (RXMode) and output (TXMode) of the SPDT switch Analog 75Ω GND GND Rx switch output (damped signal output) 75Ω GND ANT_TUNE (Pin 5) 5 ANT_TUNE Analog Antenna tuning input GND GND See also circuit pin 3 and pin 4 6 SPDT_TX Analog 7 RF_OUT Analog SPDT_TX (Pin 6) SPDT_ANT (Pin 4) VS_PA (Pin 8) VS (Pin 13) 100kΩ REF (3V) TXMode input of the SPDT switch Power amplifier output RF_OUT (Pin 7) + - 8 VS_PA Analog Power amplifier supply, connect to VS VS_PA ON GND 6 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 GND Table 1-2. Pin No. Pin Description (Continued) Pin Name Type Equivalent Circuit TEST_EN (Pin 9) Description AVCC (Pin 12) DVCC (Pin 20) VS (Pin 13) 20kΩ 9 TEST_EN 20kΩ – Test enable, connected to GND in application 100kΩ GND 10 XTAL1 Analog GND XTAL1 (Pin 10) DGND DGND GND XTAL2 (Pin 11) Crystal oscillator pin 1 (input) 180kΩ 11 XTAL2 14pF Analog GND 12 AVCC 13 VS Analog See Section 4.1 on page 22 and pins 7, 8, and 9 Main supply voltage input Digital 15 PC1 Digital 16 PC2 Digital 18 19 PC4 PC5 GND RF front end supply regulator output PC0 PC3 GND Crystal oscillator pin 2 (output) Analog See Section 4.1 on page 22 14 17 14pF Digital Digital Digital Main : AVR Port C0 Alternate : PCINT8 / NRESET / DebugWIRE Main : AVR Port C1 Alternate : NPWRON1 / PCINT9 / EXT_CLK Main : AVR Port C2 Alternate : NPWRON2 / PCINT10 / TRPA Main : AVR Port C3 Alternate : NPWRON3 / PCINT11 / TMDO / TxD Main : AVR Port C4 Alternate : NPWRON4 / PCINT12 / INT0 / TMDI / RxD Main : AVR Port C5 Alternate : NPWRON5 / PCINT13 / TRPB / TMDO_CLK ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 7 Table 1-2. Pin No. Pin Name Type 20 DVCC 21 Equivalent Circuit Description – See Section 4.1 on page 22 Digital supply voltage regulator output DGND – See Section 4.1 on page 22 Digital ground 22 PB0 Digital 23 PB1 Digital 24 25 PB2 PB3 Digital Digital 26 PB4 Digital 27 PB5 Digital 28 8 Pin Description (Continued) PB6 Digital Main : AVR Port B0 Alternate : PCINT0 / CLK_OUT Main : AVR Port B1 Alternate : PCINT1 / SCK Main : AVR Port B2 Alternate : PCINT2 / MOSI (SPI Master Out Slave In) Main : AVR Port B3 Alternate : PCINT3 / MISO (SPI Master In Slave Out) Main : AVR Port B4 Alternate : PWRON / PCINT4 / LED1 (strong high side driver) Main : AVR Port B5 Alternate : PCINT5 / INT1 / NSS Main : AVR Port B6 Alternate : PCINT6 / EVENT (firmware controlled external microcontroller event flag) Main : AVR Port B7 Alternate : NPWRON6/ PCINT7/ RX_ACTIVE (strong high side driver) / LED0 (strong low side driver) 29 PB7 Digital 30 AGND – 31 ATEST_IO2 – RF front end test I/O 2 connected to GND in application 32 ATEST_IO1 – RF front end test I/O 1 connected to GND in application GND – See Section 4.1 on page 22 See Section 4.1 on page 22 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 Analog ground Ground/backplane on exposed die pad 1.4 Typical Applications 1.4.1 Typical 3V Application with External Microcontroller Figure 1-3. Typical 3V Application with External Microcontroller IRQ NSS MISO 25 PB3 26 PB4 27 24 PB2 23 2 Optional Harmonic Filter PB1 RFIN_HB 22 3 PB0 SPDT_RX Atmel ATA8510 ATA8515 4 SPDT_ANT 5 ANT_TUNE 20 DVCC SPDT_TX PC5 19 RF_OUT PC4 18 VS_PA PC3 17 9 11 12 13 14 15 PC2 PC1 PC0 VS AVCC XTAL2 XTAL1 10 CLK_IN DGND 7 TEST _EN SCK 21 6 8 MOSI Microcontroller RFIN_LB 28 PB5 ATEST ATEST _IO1 _IO2 29 PB6 30 PB7 1 31 AGND 32 16 Wake/Monitor VS = 3V VDD Figure 1-3 shows a typical application circuit with an external host microcontroller for the 315MHz or 433.92MHz band running from a 3V lithium cell. The Atmel® ATA8510/15 stays in OFFMode until NPWRON1 (PC1) is used to wake it up. In OFFMode the Atmel ATA8510/15 draws typically less than 5nA (600nA maximum at 3.6V/85°C). In OFFMode all Atmel ATA8510/15 AVR® ports PB0..PB7 and PC0..PC5 are switched to input. PC0..PC5 and PB7 have internal pull-up resistors ensuring that the voltage at these ports is VS. PB0..PB6 are tri-state inputs and require additional consideration. PB1, PB2, and PB5 have defined voltages since they are connected to the output of the external microcontroller. PB4 is connected to ground to avoid unwanted power-ups. PB0, PB3 and PB6 do not require external circuitry since the internal circuit avoids transverse currents in OFFMode. The external microcontroller has to tolerate the floating inputs. Otherwise additional pull-down resistors are required on these floating lines. Typically, the key fob buttons are connected to the external microcontroller and the Atmel ATA8510/15 wake-up is done by pulling NPWRON1 (pin 15) to ground. If there are not enough ports for button inputs on the microcontroller, it is possible to connect up to four additional buttons to the ports PC2..PC5. In this case, the occurrence of a port event (button pressed) generates an event on pin 28. The corresponding port event is available in the event registers. A PCB trace loop antenna is typically used in this type of application. An internal antenna tuning procedure tunes the resonant frequency of this loop antenna to the Tx frequency. This is accomplished with an integrated variable capacitor on the ANT_TUNE pin. RF_OUT and RF_IN are optimally matched to the SPDT_TX and SPDT_RX pins of the integrated Rx/Tx switch. The SPDT_ANT pin has an impedance of 50 for both the Rx and Tx functions. The DC output voltage of the power amplifier is required at the SPDT_TX pin for proper operation. Also, the RFIN pin needs a DC path to ground, which is easily achieved with the matching shunt inductor. The impedance of the loop antenna is transformed to 50 with three capacitors, two of them external and one built-in at the ANT_TUNE pin. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 9 Together with the fractional-N PLL within the Atmel® ATA8510/15, an external crystal is used to fix the Rx and Tx frequency. Accurate load capacitors for this crystal are integrated to reduce the system part count and cost. Only four supply blocking capacitors are needed to decouple the different supply voltages AVCC, DVCC, VS, and VS_PA of the Atmel ATA8510/15. The exposed die pad is the RF and analog ground of the Atmel ATA8510/15. It is connected directly to AGND via a fused lead. For applications operating in the 868.3MHz or 915MHz frequency bands a high-band RF input, RFIN_HB, is supplied and must be used instead of RFIN_LB. The Atmel ATA8510/15 is controlled using specific SPI commands via the SPI interface, and an internal EEPROM for application specific configurations. 1.4.2 Typical 3V Stand-Alone Application Figure 1-4. Typical 3V Stand-alone Application VS VS RFIN_LB 25 PB3 26 PB4 28 27 PB5 29 PB6 30 PB7 1 31 AGND 32 ATEST TEST _IO1 _IO2 24 PB2 2 23 RFIN_HB PB1 SPDT_RX PB0 3 4 21 Atmel ATA8510 SPDT_ANT 5 ANT_TUNE DGND 20 DVCC 6 19 SPDT_TX PC5 RF_OUT PC4 VS_PA PC3 7 18 9 10 11 12 13 14 15 PC2 PC1 PC0 VS AVCC TEST _EN XTAL2 17 XTAL1 8 22 16 VS VS = 3V Figure 1-4 shows a stand-alone key fob application circuit for 315MHz or 433.92MHz running from a 3V lithium cell. The Atmel ATA8510/15 stays in OFFMode until one of the NPWRON ports PC1..PC5 is pulled to ground level, waking up the circuit. The NPWRON ports PC1..PC5 have internal 50k pull-up resistors and can be left open if not used. The user application software within the 20Kbyte Flash (Atmel ATA8510) is used to control the Atmel ATA8510/15 transceiver together with the firmware in the 24Kbyte ROM. The Atmel ATA8515 is not suitable for this application. The RF and decoupling circuitry is similar to Figure 1-3 on page 9. In this application, an LED is connected to PB7. Alternatively, an additional wake-up button can be used on PB7 instead of an LED. An LED can also be connected to PB4. However, note the additional pull-down resistor connected in parallel that is needed to prevent transverse currents in OFFMode. This special case only applies to PB4 because of its active input characteristics (PWRON). 10 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 2. System Functional Description 2.1 Overview 2.1.1 Service-based Concept The Atmel® ATA8510/15 is a highly configurable UHF transceiver. The configuration is stored in an internal 1024-byte EEPROM. The master system control is performed by firmware. General chip-wide settings are loaded from the EEPROM to hardware registers during system initialization. During start-up of a transmit or receive mode the specific settings are loaded from the EEPROM or SRAM to the current service in the SRAM and from there to the corresponding hardware registers. A complete configuration set of the transceiver is called “service” and includes RF settings, demodulation settings, and telegram handling information. Each service contains three channels which differ in the RF receive or transmit frequencies. The Atmel ATA8510/15 supports five services which can be configured in various ways to meet customer requirements. Three service configurations are located in the EEPROM space. They are fixed configurations which should not be changed during runtime. Two service configurations are located in the SRAM space and can be modified by USER SW in a Flash application or by an SPI command during IDLEMode. A service consists of ● One service-specific configuration part ● Three channel-specific configuration parts Further configurations for PollingMode and RSSI are available and can be modified in IDLEMode via an SPI command and/or User SW. Figure 2-1 gives an overview on the service based-concept. Figure 2-1. Service-based Concept Overview EEPROM SRAM EEPROM Polling Configuration eepPollLoopConf System Initialization SRAM Polling Configuration pollConfig Service 0 eepServices [0] Channel 0 Channel 1 Service 3 sramServices [0] Channel 2 Channel 0 Service 1 eepServices [1] Channel 0 Channel 1 Channel 1 Channel 2 SPI Service 4 sramServices [1] Channel 2 Channel 0 Service 2 eepServices [2] Channel 0 Channel 1 Channel 1 Channel 2 RSSI Threshold Configuration for Each Channel rssiThreshold [][] Channel 2 Service S currentService Channel Atmel ATA8510/15 Hardware ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 11 2.1.2 Supported Telegrams 2.1.2.1 Telegram Structure The Atmel® ATA8510/15 supports the transmission and reception of a wide variety of telegrams and protocols. Generally no special structure is required from a telegram to be received or transmitted by the Atmel ATA8510/15. However, designated hardware and software features are built in for the blocks that are depicted in Figure 2-2. Using this structure or parts of it can increase the sensitivity and robustness of the broadcast. Figure 2-2. Telegram Structure Desync Preamble Data Payload Checksum Stop Sequence Desync: The de-synchronization is usually a coding violation with a length of several symbols that should provoke a defined restart of the receiver. The use of a de-synchronization leads to more deterministic receiver behavior, reducing the required preamble length. This can be favorable in timing-critical and energy-critical applications. Preamble: The preamble is a pattern that is sent before the actual data payload to synchronize the receiver and provide the starting point of the payload. A very regular pattern (e.g., 1-0-1-0...) is recommended for synchronization (“wake-up pattern, WUP”, sometimes also called “pre-burst”) while a unique, well-defined pattern of up to 32 symbols is required to mark the start of the data payload (“start frame identifier, SFID” or “start bit”). In polling scenarios the WUP can be tens or hundreds of ms long. Data Payload: The data payload contains the actual information content of the telegram. It can be NRZ or Manchester-coded. The length of the payload is application dependent, typically 1..64 bytes. Checksum: A checksum can be calculated across the data payload to verify that the data have been received correctly. A typical example is an 8-bit CRC checksum. Data bits at the beginning of the payload can be excluded from the CRC calculation. Stop Sequence: The stop sequence is a short data pattern (typically 2 to 6 symbols) to mark the end of the telegram. A coding violation can be used to prevent additional (non-deterministic) data from being received. 2.1.2.2 NRZ and Manchester Coding Within this document the following wording is used: The expression data “bit” describes the real information content that is to be broadcast. This information can be coded in “symbols” (sometimes also called “chips”) which are then physically transmitted from sender to receiver. The receiver has to decode the “symbols” back into data “bits” to access the information. The “symbol rate” is therefore always greater or equal to the “bit rate”. The Atmel ATA8510/15 supports two coding modes: Manchester coding and non-return-to-zero (NRZ) coding. NRZ coding is implemented in a straightforward manner: One bit is represented by one symbol. Manchester coding implements two symbols per data bit. There is always a transition between the two symbols of one data bit so that one data bit always consists of a “0” and a “1”. The polarity can be either way as shown in Figure 2-3 on page 13. 12 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 Figure 2-3. Manchester Code Clock Data 1 0 1 1 0 0 0 1 0 1 0 0 Manchester (e.g., IEEE 802.3) Manchester (inverse) Manchester coding has many advantages such as simple clock recovery, no DC component, and error detection by code violation. Drawbacks are the coding/decoding effort and the increased symbol rate which is twice the data rate. 2.2 Operating Modes Overview This section gives an overview of the operating modes supported by the Atmel® ATA8510/15 as shown in Figure 2-4. Figure 2-4. Operating Modes Overview OFFMode Power-on Invalid wake-up WDR EXTR Init fails System Initialization TCMode Init done System Error Loop IDLEMode PollingMode TXMode RXMode ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 13 After connecting the supply voltage to the VS pin, the Atmel ATA8510/15 always starts in OFFMode. All internal circuits are disconnected from the power supply. Therefore, no SPI communication is supported. The Atmel ATA8510/15 can be woken up by activating the PWRON pin or one of the NPWRONx pins. This triggers the power-on sequence. After the system initialization the Atmel ATA8510/15 reaches the IDLEMode. The IDLEMode is the basic system mode supporting SPI communication and transitions to all other operating modes. There are two options of the IDLEMode requiring configuration in the EEPROM settings: ● IDLEMode(RC) with low power consumption using the fast RC (FRC) oscillator for processing ● IDLEMode(XTO) with active crystal oscillator for high accuracy clock output or timing measurements The transmit mode (TXMode) enables data transmission using the selected service/channel configurations. It is usually enabled by the SPI command “Set System Mode”, or directly after power-on, when selected in the EEPROM setting. The receive mode (RXMode) provides data reception on the selected service/channel configuration. The precondition for data reception is a valid preamble. The receiver continuously scans for a valid telegram and receives the data if all preconfigured checks are successful. The RXMode is usually enabled by the SPI command “Set System Mode”, or directly after power-on, when selected in the EEPROM setting. In PollingMode the receiver is activated for a short period of time to check for a valid telegram on the selected service/channel configurations. The receiver is deactivated if no valid telegram is found and a sleep period with very low power consumption elapses. This process is repeated periodically in accordance with the polling configuration. The initial settings are stored in the EEPROM and copied during firmware initialization to the SRAM. This allows modification of the PollingMode timing and service/channel configuration during IDLEMode. The tune and check mode (TCMode) offers calibration and self-checking functionality for the VCO, and FRC oscillators as well as for antenna tuning, temperature measurement, and polling cycle accuracy. This mode is activated via the SPI command “Calibrate and Check”. When selected in the EEPROM settings, tune and check tasks are also used during system initialization after power-on. Furthermore, they can also be activated periodically during PollingMode. Table 2-1 shows the relations between the operating modes and their corresponding power supplies, clock sources, and sleep mode settings. Table 2-1. Operation Mode AVR Sleep Mode DVCC AVCC XTO OFFMode - IDLEMode(RC) Active mode Power-down(1) off off off off off off off off off on on on off IDLEMode(XTO) Active mode Power-down(1) on on on on on on off off TXMode Active mode on on on off RXMode Active mode on on on off PollingMode(RC) - Active period - Sleep period Active mode Power-down(1) on off on off on on on off PollingMode(XTO) - Active period - Sleep period Active mode Power-down(1) on on on on on on off off Notes: 14 Operating Modes versus Power Supplies and Oscillators 1. on SRC FRC During IDLEMode(RC) and IDLEMode(XTO) the AVR® microcontroller enters sleep mode to reduce current consumption. The sleep mode of the microcontroller section can be defined in the EEPROM. The power-down mode is recommended for keeping current consumption low. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 3. Hardware 3.1 Overview The Atmel® ATA8510/15 consists of an analog front end, digital signal processing blocks (DSP), an 8-bit AVR® sub-system and various supply modules such as oscillators and power regulators. A hardware block diagram of the Atmel ATA8510/15 is shown in Figure 3-1. Figure 3-1. Block Diagram AVCC Sequencer State Machine RF Front End Front-end Registers RFIN_LB LNA, Mixer IF AMP 16 Bit Sync Timer Damping ANT_TUNE Antenna Tuning VS_PA Voltage Monitor Clock Management Debug Wire Rx DSP Power Amplifier Support FIFO 8 Bit Async Timers 2x AVR CPU Data FIFO SPDT SPDT_ANT RF_OUT Supplies and Reset D Temp (ϑ) SPDT_TX Watchdog Timer DVCC AVR SubSystem A RFIN_HB SPDT_RX SRC, FRC Oscillators VS Tx Modulator NVM Controller 16 Bit Async Timers 2x ROM 24kB IRQ Fractional N-PLL Flash 20kB EEPROM 1152B SRAM 1kByte CRC Tx DSP DATA BUS XTO XTAL1 XTAL2 Port B (8) SPI Port C (6) PB[7:0] PC[5:0] Together with the fractional-N PLL, the crystal oscillator (XTO) generates the local oscillator (LO) signal for the mixer in RXMode. The RF signal comes either from the low-band input (RFIN_LB) or from the high-band input (RFIN_HB) and is amplified by the low-noise amplifier (LNA) and down-converted by the mixer to the intermediate frequency (IF) using the LO signal. A 10dB IF amplifier with low-pass filter characteristic is used to achieve enhanced system sensitivity without affecting blocking performance. After the mixer, the IF signal is sampled using a high-resolution analog-to-digital converter (ADC). Within the Rx digital signal processing (Rx DSP) the received signal from the ADC is filtered by a digital channel filter and demodulated. Two data receive paths, path A and path B, are included in the Rx DSP after the digital channel filter. In addition, the receive path can be configured to provide the digital output of an internal temperature sensor (Temp()). ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 15 In TXMode the fractional-N PLL generates the Tx frequency. The power amplifier (PA) generates an RF output power signal programmable from –10dBm to +14dBm at RF_OUT. The FSK modulation is performed by changing the frequency setting of the fractional-N PLL dynamically with Tx digital signal processing (Tx DSP). Digital preemphasis and digital Gauss filtering can be activated in the Tx DSP in order to achieve higher data rates or reduce occupied bandwidth. The ASK modulation is performed by switching the power amplifier on and off. An ASK shaping filter is available to reduce the transmitted bandwidth of the modulated PA output signal. The shaping filter can also be used at the start and end of an FSK transmission. With the single pole double throw (SPDT) switch the RF signal from the antenna is switched to RFIN in RXMode and from RF_OUT to the antenna in TXMode. An adjustable capacitor and an RF level detector on ANT_TUNE are used to tune the center frequency of loop antennas to reduce tolerances and capacitive proximity effects. The system is controlled by an AVR® CPU with 24KB firmware ROM and 20KB user flash for the Atmel® ATA8510. 1024-byte EEPROM, 1024-byte SRAM, and other peripherals are supporting the transceiver handling. Two GPIO ports, PB[7:0] and PC[5:0], are available for external digital connections, for example, as an alternate function the SPI interface is connected to port B. The Atmel ATA8510/15 is controlled by the EEPROM configuration and SPI commands and the functional behavior is mainly determined by firmware in the ROM. Much of the configuration can be modified by the EEPROM settings. The firmware running on the AVR gives access to the hardware functionality of the Atmel ATA8510/15. Extensions to this firmware can be added in the 20KB of Flash memory for the Atmel ATA8510. The Rx DSP and Tx DSP registers are addressed directly and accessible from the AVR. A set of sequencer state machines is included to perform Rx and Tx path operations (such as enable, disable, receive, transmit) which require a defined timing parallel to the AVR program execution. The power management contains low-dropout (LDO) regulators and reset circuits for the supply voltages VS, AVCC and DVCC, of the Atmel ATA8510/15. In OFFMode all the supply voltages AVCC and DVCC, are switched off to achieve very low current consumption. The Atmel ATA8510/15 can be powered up by activating the PWRON pin or one of the NPWRON[6:1] pins because they are still active in OFFMode. The AVCC domain can be switched on and off independently from DVCC. The Atmel ATA8510/15 includes two idle modes. In IDLEMode(RC) only the DVCC voltage regulator, the FRC and SRC oscillators are active and the AVR uses a power-down mode to achieve low current consumption. The same power-down mode can be used during the inactive phases of the PollingMode. In IDLEMode(XTO) the AVCC voltage domain as well as the XTO are additionally activated. An integrated watchdog timer is available to restart the Atmel ATA8510/15 when it is not served within the configured timeout period. 3.2 Receive Path 3.2.1 Overview The receive path consists of a low-noise amplifier (LNA), mixer, IF amplifier, analog-to-digital converter (ADC), and an Rx digital signal processor (Rx DSP). The fractional-N PLL and the XTO deliver the local oscillator frequency in RXMode. The receive path is controlled by the RF front-end registers. Two separate LNA inputs, one for low-band and one for high-band, are provided to obtain optimum performance matching for each frequency range and to allow multi-band applications. A radio frequency (RF) level detector at the LNA output and a switchable damping included into the single-pole double-trough (SPDT) switch is used in the presence of large blockers to achieve enhanced system blocking performance. The mixer converts the received RF signal to a low intermediate frequency (IF) of about 250kHz. A double-quadrature architecture is used for the mixer to achieve high image rejection. Additionally, the third-order suppression of the local oscillator (LO) harmonics makes receiving without a front-end SAW filter less critical, such as in a car key fob application. An IF amplifier provides additional gain and improves the receiver sensitivity by 2-3dB. Because of built-in filter function, the in-band compression is degraded by 10dB, while the out-of-band compression remains unchanged. The ADC converts the IF signal into the digital domain. Due to the high effective resolution of the ADC, the channel filter and received signal strength indicator (RSSI) can be realized in the digital signal domain. Therefore, no analog gain control (AGC) potentially leading to critical timing issues or analog filtering is required in front of the ADC. This leads to a receiver front end with excellent blocking performance up to the 1dB compression point of the LNA and mixer, and a steep digital channel filter can be used. The Rx DSP performs the channel filtering and converts the digital output signal of the ADC to the baseband for demodulation. Due to the digital realization of these functions the Rx DSP can be adapted to the needs of many different applications. Channel bandwidth, data rate, modulation type, wake-up criteria, signal checks, clock recovery, and many other properties are configurable. The RSSI value is realized completely in the digital signal domain, enabling very high relative and absolute accuracy that is only deteriorated by the gain errors of the LNA, mixer, and ADC. 16 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 Two independent receive paths A and B are integrated in the Rx DSP after the channel filter and allow the use of different data rates, modulation types, and protocols without the need to power up the receive path more than once to decide which signal should be received. This results in a reduced polling current in several applications. The integration of remote keyless entry (RKE), passive entry and go (PEG) and tire-pressure monitoring systems (TPM) into one module is simplified because completely different protocols can be supported and a low polling current is achieved. It is even possible to configure different receive RF bands for different applications by using the two LNA inputs. For example, a TPM receiver can be realized at 433.92MHz while a PEG system uses the 868MHz ISM band with multi-channel communication. 3.2.2 Rx Digital Signal Processing (Rx DSP) The Rx digital signal processing (DSP) block performs the digital filtering, decoding, checking, and byte-wise buffering of the Rx samples that are derived from the ADC as shown in Figure 3-2. The Rx DSP provides the following outputs: ● Raw demodulated data at the TRPA/B pins ● ● ● Decoded data at the TMDO and TMDO_CLK pins Buffered data bytes toward the data FIFO and ID check block Auxiliary information about the signal such as the received signal strength indication (RSSI) and the frequency offset of the received signal from the selected center frequency (RXFOA/B) Figure 3-2. Rx DSP Overview RXFOA ADC Data Channel Filter Demod & Check TRPA TMDO_A TMDO_CLK_A Frame Sync A Path A Rx Buffer A Data Byte = Data FIFO Frame Sync B Path B Rx Buffer B Data Byte = RSSI RXFOB RSSI Buffer TRPB Support FIFO TMDO_B TMDO_CLK_B ID Check = The channel filter determines the receiver bandwidth. Its output is used for both receiving paths A and B, making it necessary to configure the filter to match both paths. The receiving paths A and B are identical and consist of an ASK/FSK demodulator with attached signal checks, a frame synchronizer which supports pattern-based searches for the telegram start and a 1-byte hardware buffer with integrated CRC checker for the received data. Depending on the signal checks, one path is selected which writes the received data to the data FIFO and optionally to the ID check block. The RSSI values are determined by the demodulator and written via the RSSI buffer to the support FIFO where the latest 16 values are stored for further processing. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 17 3.3 Transmit Path The Atmel® ATA8510/15 integrates a transmitter that is capable of sending data with various options: ● Frequency bands 310MHz to 318MHz, 418MHz to 477MHz, 836MHz to 956MHz ● ● ● ● ● Data rates up to 80kBit/s Manchester or 120Ksym/s NRZ in buffered and transparent mode ASK or FSK modulation Transparent or buffered mode ASK shaping filter Gauss-shaping digital filter This section describes the hardware blocks that are integrated to perform the transmit functionality. Figure 3-3 shows a block diagram of the transmit data path. Figure 3-3. Transmit Data Path TX DSP Analog Frontend FFREQ2 FSCR. TXMOD Pin 18/ TMDI TX Modulator Configuration Registers 00 01 10 11 FSK ASK 1 0 1 Gauss Filter 0 0 CRC DFIFO Stop Sequ Shift Register Manch. Code Preemphasis Filter 1 PLL 0 Power Amp RFOUT FFREQ1 Control State Machine SFIFO 1 on/off 1 ASK Shaping Filter 0 The transmission data source can be selected from a register bit, the transparent input pin 18 (TMDI), and the Tx modulator that fetches the data from the DFIFO and SFIFO. If ASK/OOK modulation is selected, the data stream is used to directly switch the power amplifier on and off. The transmitted carrier frequency is set by the PLL frequency synthesizer. If FSK modulation is selected, the data stream is used to switch between two frequencies that are generated by the PLL frequency synthesizer. The power amplifier is constantly on. Power ramping (ASK shaping) can be used during on and off switching. To reduce the occupied bandwidth a digital Gauss-shaping filter can be enabled. For data rates above 20kHz Manchester or 40kHz NRZ-coding a digital preemphasis filter has to be enabled to compensate for the PLL loop filter. 18 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 3.4 AVR Controller 3.4.1 AVR Controller Sub-System The AVR® controller sub-system consists of the AVR CPU core, its program memory, and a data bus with data memory and peripheral blocks attached. The receive path and the transmit path also have their user interfaces connected to the data bus. CPU Core The main function of the CPU core is to ensure correct program execution. For this reason, the CPU core must be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 3-4. Overview of Architecture Data Bus 8-bit ROM Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registers Instruction Register Interrupt Unit SPI Unit Instruction Decoder Control Lines Indirect Addressing Watchdog Timer Direct Addressing 3.4.2 ALU Clock Management I/O Module 1 Data SRAM I/O Module n EEPROM PortN In order to maximize performance and parallelism, the AVR uses a Harvard architecture—with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is prefetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system reprogrammable Flash memory and ROM. The fast-access register file contains 32  8-bit general purpose working registers with a single clock cycle access time. This allows a single-cycle arithmetic and logic unit (ALU) operation. In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in the Flash program memory. Referred to as ‘X,’ ‘Y,’ and ‘Z’ registers, these higher 16-bit function registers are described later in this section. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 19 The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The program flow is provided by conditional and unconditional jump and call instructions which are able to directly address the entire address space. Most AVR® instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. The program memory space is divided in two sections, the boot program section and the application program section. Both sections have dedicated lock bits for write and read/write protection. The store program memory (SPM) instruction that writes into the application Flash memory section must reside in the boot program section. During interrupts and subroutine calls, the return address of the program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM—the stack size is thus only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the stack pointer (SP) in the reset routine before subroutines or interrupts are executed. The SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F. In addition, the circuit has extended I/O space from 0x60 - 0x1FF and SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 20 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 3.5 Power Management The IC has four power domains: 1. VS – Unregulated battery voltage input 2. DVCC – Internally regulated digital supply voltage. Typical value is 1.35V. 3. AVCC – Internally regulated RF front end and XTO supply. Typical value is 1.85V. ® The Atmel ATA8510/15 can be operated from VS= 1.9V to 3.6V. Figure 3-5. Power Supply Management 2.2µF 220nF 22nF AVCC VS DVCC Power Management (common reference, Voltage Monitor) VS_PA regulator DVCC regulator AVCC regulator Data Bus RFIN_LB RFIN_HB AVR CPU, AVR peripherals, Memories, RxDSP, TxDSP and FRC/SRC SPDT_RX SPDT_ANT ANT_TUNE RF front end and XTO SPDT_TX RF_OUT Port B PB7 XTAL1 ... Level shifter SPI PB4 XTAL2 VS Port C PC5 ... PC1 ... ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 21 4. Electrical Characteristics 4.1 ESD Protection Circuits GND is the exposed die pad of the Atmel® ATA8510/15 which is internally connected to AGND (pin 30). All zener diodes shown in Figure 4-1 (marked as power clamps) are realized with dynamic clamping circuits and not physical zener diodes. Therefore, DC currents are not clamped to the shown voltages. Figure 4-1. Atmel ATA8510/15 ESD Protection Circuit RFIN_LB (Pin 1) XTAL1 (Pin 10) RFIN_HB (Pin 2) XTAL2 (Pin 11) AVCC (Pin 12) VS (Pin 13) ATEST_IO2 (Pin 31) ATEST_IO1 (Pin 32) Power Clamp 1.8V AGND (Pin 30) GND GND GND GND GND VS_PA (Pin 8) GND VS (Pin 13) 125kΩ ANT_TUNE (Pin 5) SPDT_RX (Pin 3) SPDT_ANT (Pin 4) SPDT_TX (Pin 6) RF_OUT (Pin 7) Power Clamp 3.3V TEST_EN (Pin 9) Power Clamp 3.3V Power Clamp 3.3V GND VS (Pin 13) DVCC (Pin 20) Power Clamp 1.8V PC0 to PC5 (Pin 14 to Pin 19) DGND (Pin 21) 22 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 PB0 to PB7 (Pin 22 to Pin 29) Power Clamp 5.5V GND 4.2 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit +150 °C –55 +125 °C Junction temperature Tj Storage temperature Tstg Ambient temperature Tamb –40 +85 °C VVS –0.3 4.0 V Supply voltage PA (1.9..3.6V application) VVS_PA –0.3 4.0 V Maximum input level (input matched to 50Ω) Pin_max +10 dBm Supply voltage ESD (Human Body Model) all pins HBM –4 +4 kV ESD (Machine Model) all pins MM –200 +200 V FCDM –750 +750 V 4.0 Vp –0.3 VS + 0.3 V –0.3 VS + 0.3 V ESD (Field Induced Charged Device Model) all pins (1) Maximum RF amplitude at pin 5 (ANT_TUNE) Maximum peak voltage at pin 4 (SPDT_ANT) (1) ANTTUNE SPDTANT Maximum peak voltage at pin 6 (SPDT_TX)(1) SPDTTX Note: 1. Customer application needs to be designed properly 4.3 Thermal Resistance Parameters Thermal Resistance, Junction Ambient, Soldered according to JEDEC Symbol Value Unit Rth_JA 35 K/W ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 23 4.4 Supply Voltages and Current Consumption All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel® EEPROM settings are used unless marked with *1. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.00 Supply voltage range VS 3V application *1 13 VVS 1.9 3.0 3.6 V A 1.05 Supply voltage rise time 13 VVS_rise 1 V/µs D 1.10 Supply voltage range VS_PA 3V application *1 8 VVS_PA 3 3.6 V A 1.20 OFFMode Current consumption 3V application *1 Tamb = 25°C Tamb = 85°C 8, 13 IOFFMode_3V 5 150 600 nA nA B B 1.30 IDLEMode(RC) Current consumption SRC active, AVR in power-down mode, temperature range –40°C to +65°C 13 IIDLEMode(RC) 50 90 μA B 1.40 IDLEMode(XTO) Current consumption XTO active, AVR in power-down mode 13 IIDLEMode(XTO) 250 400 μA B IDLEMode(XTO) Current consumption With active CLK_OUT fXTO/6 = 4.05MHz CLOAD_CLK_OUT = 10pF VVS = 3.6V AVR running with fXTO/4 = 6.076MHz 13, 22 IIDLEMode(XTO) 1.3 2.5 mA B RXMode Current consumption AVR running with fXTO/4 fRF = 315MHz *1 fRF = 433.92MHz fRF = 868.3MHz *1 fRF = 915MHz *1 9.2 9.8 10.4 10.5 12.7 13.2 14.6 14.7 8.9 9.4 11.5 11.7 11 12 14.5 15 13.1 13.8 17.4 17.4 17 18.5 22.5 23 24.3 26.3 32.7 33.5 33 36 45 46 1.60 1.80 _CLK_OUT2 13 IRXMode1 VVS = 3V Pout = +6dBm fRF = 315MHz *1 fRF = 433.92MHz fRF = 868.3MHz *1 fRF = 915MHz *1 2.00 TXMode Current consumption Pout = +10dBm *1 fRF = 315MHz *1 fRF = 433.92MHz fRF = 868.3MHz *1 fRF = 915MHz *1 Pout = +14dBm *1 fRF = 315MHz *1 fRF = 433.92MHz fRF = 868.3MHz *1 fRF = 915MHz *1 1.9 (7), 8, 13 ITXMode mA B B B B mA *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Pin number in brackets mean, that they are measured matched to 50 on the application board. 24 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 B A A B B B B B B B B B 4.5 RF Receiving Characteristics All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Frequency Ranges and Frequency Resolution of PLL for RXMode, TXMode and PollingMode 3.00 RF operating frequency range 315MHz low-band FECR.LBNHB = ’1’ FECR.S4N3 = ’0’ 1, 7 fRange_LB1_315 310 315 318 MHz A 3.10 RF operating frequency range 433MHz low-band FECR.LBNHB = ’1’ FECR.S4N3 = ’1’ 1, 7 fRange_LB2_433 418 433.92 477 MHz B 3.30 RF operating frequency range High-band FECR.LBNHB = ’0’ FECR.S4N3 = ’0’ 2, 7 fRange_B4_868 836 868.3 956 MHz B 3.40 Frequency resolution PLL Low-band fXTO/218 High-band fXTO/217 1, 2, 7 DFPLL Hz B B kHz B Kbit/s B B B B B B 92.72 185.43 RXMode and PollingMode Receive Characteristics IF bandwidth specifications are examples usable for parameter extrapolation if other IF bandwidth values are used 4.00 Receiver 3dB bandwidth Programmable digital IF filter 4.10 at 25kHz IF-BW at 50kHz IF-BW ASK and FSK at 80kHz IF-BW transparent mode data at 165kHz IF-BW rate Manchester mode at 237kHz IF-BW at 366kHz IF-BW 1, 2 4.20 = frequency_deviation Modulation index FSK / symbol_rate recommended 1, 2 1, 2 BWIF 25 366 DRTM 0.25 7 14 20 50 80 80  0.5 0.75 1 360 1.25 B B ±9 ±18 ±26 ±60 ±93 ±93 B B B B B B Maximum usable frequency deviation is baseband clock dependant fDEV_Max = CLK_BB/8 4.30 Frequency deviation at 25kHz IF-BW at 50kHz IF-BW at 80kHz IF-BW at 165kHz IF-BW at 237kHz IF-BW at 366kHz IF-BW 1, 2 fDEV ±0.375 ±0.75 ±1.2 ±2.5 ±3.5 ±5.4 kHz *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Pin number in brackets mean, that they are measured matched to 50 on the application board. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 25 4.5 RF Receiving Characteristics (Continued) All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions Pin Symbol Min. 4.40 ASK and FSK transparent mode symbol rate NRZ mode Used to receive NRZ, Keyloq, PPM, 1/3 2/3 Coded telegrams at 25kHz IF-BW at 50kHz IF-BW at 80kHz IF-BW at 165kHz IF-BW at 237kHz IF-BW at 366kHz IF-BW 1, 2 SRTM_OPT 0.5 4.70 Data rate tolerance FSK and ASK Loss of sensitivity 10MHz 34 40 52 58 67 75 75 (1, 2) fdist. ≥ 150kHz fdist. ≥ 225kHz fdist. ≥ 450kHz fdist. ≥ 1MHz fdist. ≥ 4MHz fdist.>10MHz 39 46 52 62 68 68 (1, 2) fdist. ≥ 225kHz fdist. ≥ 450kHz fdist. ≥ 1MHz fdist. ≥ 4MHz fdist.>10MHz 42 48 58 65 65 (1, 2) fdist. ≥ 500kHz fdist. ≥ 1MHz fdist. ≥ 4MHz fdist.>10MHz (1, 2) (1, 2) Min. Typ. Max. Unit Type* dBc C C C C C C C dBc C C C C C C dBc C C C C C 49 58 65 65 dBc C C C C 45 38 55 47 dB dB A A 27 28 32 33 IMRED BLNfLO 37 38 dB 39 45 RxDSP property depends on nominal RF frequency and DIV_IF fIF = fRF / (DIV_IF*6) 7.90 Nominal IF frequency fIF 8.10 No AGC is used, therefore, the full System input referred dynamic is available compression point receiving signals at sensitivity level on pin (1, 2) ICP1dB 8.20 System input referred Low-band 3rd-order intercept High-band point (1, 2) IIP3 242 251 C C C C 276 kHz B –45 dBm B –35 –37 dBm C *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Pin number in brackets mean, that they are measured matched to 50 on the application board. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 29 4.5 RF Receiving Characteristics (Continued) All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions 8.30 System works from Max, useful RX input sensitivity level up to level without damping that level with BER = 10-3 8.40 Max. useful RX input level with damping System works from sensitivity level up to that level with BER = 10-3 Pin Symbol Min. Typ. (1, 2) PIn_max1 –10 4 PIn_max2 +5 Zin –20% Max. Unit Type* +10 dBm C +10 dBm C  pF  pF  pF  pF C C C C C C C C dBm B Measured on application board, RC parallel equivalent circuit 315MHz 8.50 8.60 8.70 1 Input impedance 433.92MHz 1 868.3MHz 2 915MHz 2 LNA amplitude detector switch level Firmware switches SPDT to damping on if a level above SGainswitch is present during start of RXMode (1, 2) PGainswitch SPDT switch RX insertion loss Damping off Sensitivity matching RF_IN with SPDT to 50 compared to matching RF_IN directly to 50 Low-band, 433.92MHz High-band, 868MHz (3, 4) ILSwitch_RX 870 2.9 400 2.9 340 1.4 330 1.4 +20% –39 0.7 1.0 1.1 1.4 dB dB C C 15 18 16 19 dB dB C C –60 –86 –50 –60 dBm C C Same matching as parameter no. 8.70 8.80 SPDT switch RX damping ON This influences the blocking behavior if measured at pin 4 (3, 4) Dswitch 14 17 Low-band High-band 8.90 LO spurious at LNA input freq > 1GHz freq < 1GHz (1, 2) PLO_LNA_IN *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Pin number in brackets mean, that they are measured matched to 50 on the application board. 30 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 4.5 RF Receiving Characteristics (Continued) All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions Pin Symbol Min. 9.00 RSSI accuracy PRFIN_LB(HB) = –70dBm Low-band High-band (1, 2), 4 RSSIABS_ACCU 9.10 RSSI relative accuracy Measurement range –100dBm to –50dBm (1, 2), 4 RSSIREL_ACCU 9.20 RSSI resolution DSP property (1, 2), 4 RSSIRES Typ. Max. Unit Type* –5.0 –5.5 +5.0 +5.5 dB B –1 +1 dB B dB/ value D 0.5 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Pin number in brackets mean, that they are measured matched to 50 on the application board. ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 31 4.6 RF Transmit Characteristics All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions Pin Symbol Min. Tamb = 25°C (7) PRange –12 Optimum load impedance for each power step. Up to two times higher steps for fixed load impedance. (7) ΔPOUT Tamb = 25°C using 6dBm matching FEPAC = 35 (low-band) FEPAC = 36 (high-band) (7) Pout_6dBm Output 2nd harmonic at 6dBm Tamb = 25°C using 6dBm matching 315MHz, FEPAC = 35 433.92MHz, FEPAC = 35 868.3MHz, FEPAC = 36 915MHz, FEPAC = 36 (7) HM26dBm Output 3rd harmonic at 6dBm Tamb = 25°C using 6dBm matching 315MHz, FEPAC = 35 433.92MHz, FEPAC = 35 868.3MHz, FEPAC = 36 915MHz, FEPAC = 36 (7) TXMode 10.50 current consumption at 6dBm 6dBm matching 315MHz, FEPAC = 35 433.92MHz, FEPAC = 35 868.3MHz, FEPAC = 36 915MHz, FEPAC = 36 (7), 8, 13 ITXMode_6dBm Output power 10.60 at 10dBm Tamb = 25°C using 10dBm matching FEPAC = 46 (low-band) FEPAC = 47 (high-band) (7) Pout_10dBm Output 2nd harmonic at 10dBm Tamb = 25°C using 10dBm matching 315MHz, FEPAC = 46 433.92MHz, FEPAC = 46 868.3MHz, FEPAC = 47 915MHz, FEPAC = 47 (7) HM210dBm Output 3rd harmonic at 10dBm Tamb = 25°C using 10dBm matching 315MHz, FEPAC = 46 433.92MHz, FEPAC = 46 868.3MHz, FEPAC = 47 915MHz, FEPAC = 47 (7) Typ. Max. Unit Type* +14.5 dBm B dB C dBm B dBc C C C C dBc C C C C Frequency Ranges and Frequency Resolution of PLL See parameters 3.00 to 3.40 on page 25 TXMode Transmit Characteristics 10.00 Output power range 10.10 Output power programming steps Output power 10.20 at 6dBm 10.30 10.40 10.70 10.80 0.4 –1.5dB +1.5dB –30 –36 –35 -35 –33 –41 –58 –58 HM36dBm HM310dBm 6 –1.5dB 8.7 9.1 11.5 11.7 11 12 14.5 15 mA B B B B 10 +1.5dB dBm B dBc C C C C dBc C C C C –24 –28 –24 –27 –25 –34 –50 –55 * Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = Characterized on samples, D = Design parameter. Pin numbers in brackets mean, that they are measured matched to 50 on the application board 32 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 4.6 RF Transmit Characteristics (Continued) All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions Pin Symbol TXMode 10.90 current consumption at 10dBm 10dBm matching 315MHz, FEPAC = 46 433.92MHz, FEPAC = 46 868.3MHz, FEPAC = 47 915MHz, FEPAC = 47 (7), 8, 13 ITXMode_10dBm Output power 11.00 at 14dBm Tamb = 25°C using 14dBm matching FEPAC = 56 (low-band) FEPAC = 57 (high-band) (7) Pout_14dBm Output 2nd harmonic at 14dBm Tamb = 25°C using 14dBm matching 315MHz, FEPAC = 56 433.92MHz, FEPAC = 56 868.3MHz, FEPAC = 57 915MHz, FEPAC = 57 (7) HM214dBm Output 3rd harmonic at 14dBm Tamb = 25°C using 14dBm matching 315MHz, FEPAC = 56 433.92MHz, FEPAC = 56 868.3MHz, FEPAC = 57 915MHz, FEPAC = 57 (7) TXMode 11.30 current consumption at 14dBm 14dBm matching 315MHz, FEPAC = 56 433.92MHz, FEPAC = 56 868.3MHz, FEPAC = 57 915MHz, FEPAC = 57 (7), 8, 13 ITXMode_14dBm Output power change 1 11.40 full temperature and supply voltage range Low-band, High-band 0 to ≤10dBm VVS = 3.0V VVS = 1.9V to 3.6V P = Pout + P (7) PTambVs1 Output power change 2 11.50 full temperature and supply voltage range High-band >10dBm to 14dBm VVS = 3.0V VVS = 2.1V to 3.6V P = Pout + P (7) PTambVs2 11.10 11.20 11.60 Spurious emission Low-band: at ±fXTO at ±fAVR (fXTO / 4) at ± fCLK_OUT (fXTO / 6) High-band: at ±fXTO at ±fAVR (fXTO / 4) at ± fCLK_OUT (fXTO / 6) Min. –1.5dB Typ. Max. 13.1 13.8 17.4 17.4 17 18.5 22.5 23 14 +1.5dB Type* mA B B B B dBm B dBc C C C C dBc C C C C 33 36 45 46 mA B B B B –1.5 –5.5 +1.5 +2.5 dB C C –3 –6 +1.5 +3 –30 –30 –24 –24 –30 –31 –50 –51 HM314dBm 24.3 26.3 32.7 33.5 –80 –85 –80 (7) Unit dB –65 –65 –65 SPTX C C B C C dBc –72 –85 –78 –60 –60 –60 B C C * Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = Characterized on samples, D = Design parameter. Pin numbers in brackets mean, that they are measured matched to 50 on the application board ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 33 4.6 RF Transmit Characteristics (Continued) All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions TX transparent data 11.70 rate in Manchester and NRZ mode Manchester mode NRZ mode pre-emphasis enabled for symbol rates higher than 40Kbit TX buffered data rate 11.80 in Manchester and NRZ mode Manchester mode NRZ mode TX buffered data rate programming step in 11.90 Manchester and NRZ mode AVR running with fXTO/4 Pin Symbol 18, 7 Min. Typ. Max. Unit Type* DRTX_TM_MAN DRTX_TM_NRZ 80 160 Kbit/s Ksym/s B B DRTX_BUF_NRZ DRTX_BUF_MAN 80 120 Kbit/s Ksym/s B B 7 DRBUF 1 % D 9 pF B Antenna Tuning and SPDT in TXMode 12.00 Antenna tuning capacitor range FEAT.ANTN(3:0) = 0 to 15 5 CTUNE_RANGE 12.10 Antenna tuning capacitor resolution 4bits controlled with RF front-end register FEAT.ANT(3:0) available 5 CTUNE_RES 0.16 0.2 pF C Antenna tuning series resistance The series resistance influences the quality factor of the loop antenna and causes radiated Tx power losses 5 CTUNE_SRESIST 2.5 4  C If higher levels occur in application an external capacitor to GND is needed to reduce the amplitude. 5 CTUNE_RFAMP_ 3 Vp D 1.1 1.2 dB dB C C –0.3 VS + 0.3 V D –0.3 VS + 0.3 V D 12.20 Antenna tuning 12.30 maximum RF amplitude 12.40 SPDT insertion loss TX Transmitted power using matching RF_OUT with SPDT to 50 compared to matching RF_OUT directly to 50 Low-band High-band 4 MAX (4, 6) ILSwitch_TX 0.5 0.7 Maximum peak 12.45 voltage on SPDT_ANT (pin 4) 4 Maximum peak 12.50 voltage on SPDT_TX (pin 6) 6 VPEAK_SPDT_ ANT VPEAK_SPDT_ TX * Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = Characterized on samples, D = Design parameter. Pin numbers in brackets mean, that they are measured matched to 50 on the application board 34 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 4.7 Oscillators and CLK_OUT All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances, quartz parameters Cm = 4fF and C0 = 1pF unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. 13.00 Parameters Test Conditions Pin Symbol CLK_OUT equivalent internal capacitance Used for current calculation 13, 22 Supply current 13.10 increase CLK_OUT active Calculation can be applied to all operation modes except OFFMode 13.30 XTO frequency range Min. Typ. Max. Unit Type* CCLK 7.5 10 pF C 13 ICLK (CCLK + CLOAD_CLK_OUT) x VVS x fOUT A C 10, 11 fxto 23.8 26.2 MHz C 24.305 XTO pulling due to 13.40 internal capacitance and XTO tolerance Cm = 4fF, Tamb = 25°C 10, 11  FXTO1 –10 +10 ppm B XTO pulling due to 13.50 temperature and supply voltage Cm = 4fF Tamb = –40°C to +85°C 10, 11  FXTO2 –4 +4 ppm B 13.60 Maximum C0 of XTAL XTAL parameter 10, 11 C0_max 1 2 pF D XTAL, Cm motional 13.70 capacitance XTAL parameter 10, 11 Cm 4 10 fF D 13.80 XTAL, real part of XTO Cm = 4fF, C0 = 1pF impedance at start-up 10, 11 Rm_start1 950  B 13.90 XTAL, real part of XTO Cm = 4fF, C0 = 1pF, impedance at start-up Tamb < 85°C 10, 11 Re_start2 1100  B 14.00 XTAL, maximum Rm after start-up XTAL parameter 10, 11 Rm_max 110  D 14.10 Internal load capacitors Including ESD and package capacitance. XTAL has to be specified for 7.5pF load capacitance (incl. 1pF PCB capacitance per pin) 10, 11 CL1, CL2 13.3 14 14.7 pF B 14.20 Slow RC oscillator frequency Polling cycle can be calibrated ±2% accurate with fXTO 22 fSRC –10% 125 +10% kHz A 14.30 Fast RC oscillator frequency FRC oscillator can be calibrated ±2% accurate with fXTO 22 fFRC –5% 6.36 +5% MHz A *) Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 35 4.8 I/O Characteristics for Ports PB0 to PB7 and PC0 to PC5 All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. Parameters Test Conditions Pin Symbol Min. –0.3 Typ. Max. Unit Type* 0.2 x VVS V A –1 µA A VVS + 0.3 V A 15.00 Input low voltage PC0 to PC5 PB0 to PB7 14-19 22-29 VIL Input low leakage current I/O pin PC0 to PC5 PB0 to PB7 14-19 22-29 IIL 15.10 Input high voltage PC0 to PC5 PB0 to PB7 14-19 22-29 VIH Input high leakage current I/O pin PC0 to PC5 PB0 to PB7 14-19 22-29 IIH 1 µA A 15.20 Output low voltage IOL = 0.2mA 14-19 22-29 VOL_3V 0.1 x VVS V A 15.30 Output high voltage IOH = –0.2mA 14-19 22-29 VOH_3V 0.9 x VVS V A 15.40 I/O pin pull-up resistor OFFMode: see port B and port C 14-19 22-29 RPU 30 70 k A Output low voltage for Configurable on pin 15.50 strong LED low-side PB7 driver (PB7) ILOAD = 1.5mA 29 VOL_STR1 0.1 x VVS V A Output high voltage for Configurable on pin 15.60 strong LED/LNA high- PB7 and PB4 side driver (PB7, PB4) ILOAD = –1.5mA 26, 29 VOH_STR1 V A Activated in ISP mode Output low voltage for IOL = 1.7mA, 15.70 strong ISP low-side VVs > 2.5V driver (PB3) Tamb = –40°C to +65°C 25 VOL_STR2 V V B B Activated in ISP mode Output high voltage for IOH = –1.7mA, 15.80 strong ISP high-side VVs > 2.5V driver (PB3) Tamb = –40°C to +65°C 25 VOH_STR2 V V B B 4.5 MHz B 55 % A 15.05 15.15 0.8 x VVS 50 0.9 x VVS 0.1 x VVS 0.1 x VVS 0.9 x VVS 0.9 x VVS CLK_OUT output 15.90 frequency XTO, FRC or SRC related clock fCLK_OUT = fOSC/(2*CLKOD) 22 fCLK_OUT 16.00 CLK_OUT duty cycle CLOAD_CLK_OUT = 10pF fCLK_OUT = 4.5MHz 22 DTYCLK_OUT 45 3V application CLoad = 10pF 14-19 22-29 Tdel_rise_3V 13.6 17.5 22.4 ns D 3V application CLoad = 10pF 14-19 22-29 Trise_3V 20.7 23.9 28.4 ns D I/O pin slew rate (rising 3V application edge) CLoad = 10pF 14-19 22-29 Tsr_rise_3V 0.115 0.100 0.084 V/ns D 16.10 I/O pin output delay time (rising edge) I/O pin rise time 16.20 (0.1  VVS to 0.9  VVS) 16.30 *) Type means: A = 100% tested at voltage and temperature limits, B = 100 % correlation tested, C = Characterized on samples, D = Design parameter 36 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 4.8 I/O Characteristics for Ports PB0 to PB7 and PC0 to PC5 (Continued) All parameters refer to GND (backplane) and are valid for Tamb = –40°C to +85°C, VVS = 1.9V to 3.6V over all process tolerances unless otherwise specified. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM settings are used unless marked with *1. No. 16.40 Parameters Test Conditions I/O pin output delay time (falling edge) I/O pin fall time 16.50 (0.9  VVS to 0.1  VVS) 16.60 I/O pin slew rate (falling edge) Pin Symbol Min. Typ. Max. Unit Type* 3V application CLoad = 10pF 14-19 22-29 Tdel_fall_3V 13.7 17.4 22.7 ns D 3V application CLoad = 10pF 14-19 22-29 Tfall_3V 16.2 19.2 22.5 ns D 3V application CLoad = 10pF 14-19 22-29 Tsr_fall_3V 0.148 0.125 0.106 V/ns D *) Type means: A = 100% tested at voltage and temperature limits, B = 100 % correlation tested, C = Characterized on samples, D = Design parameter 4.9 Hardware Timings All parameters refer to GND (backplane) and are valid for Tamb = –40°C to + 85°C, VVS =1.9V to 3.6V over all process tolerances. Typical values are given at VVS = 3V, Tamb = 25°C, and for a typical process unless otherwise specified. Crystal oscillator frequency fXTO = 24.305MHz. Standard Atmel EEPROM Settings are used if marked with *1. No. Parameters 17.00 Start-up Time XTO Test Conditions Pin Symbol AVCC already enabled and ready C0 < 1.5pF 4fF < Cm < 15fF Rm < 110 Rm < 800 10, 11 TStart_XTO Min. Typ. Max. Unit Type* 90 130 250 1500 µs µs B C 17.10 Erase and Write EEPROM using ISP commands or SPI command “Write EEPROM” 14, 23, 24, 25 TEE_ER_WR 10 ms B 17.20 Erase Only EEPROM using ISP commands 14, 23, 24, 25 TEE_ER 5 ms B 17.30 Write Only EEPROM using ISP commands 14, 23, 24, 25 TEE_WR 5 ms B PWRON = ‘1’ or System Initialisation NPWRON = ‘0’ to 17.50 Startup Time INTERNAL RESET removal 13,20 TSYSINIT1 200 µs B 80 *) Type means: A = 100% tested at voltage and temperature limits, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 37 5. Ordering Information Extended Type Number Package Remarks ATA8510-GHQW QFN32 5mm 5mm, 6k tape and reel, PB-free, 20Kbyte user Flash ATA8515-GHQW QFN32 5mm  5mm, 6k tape and reel, PB-free 6. Package Information Top View D 32 1 E technical drawings according to DIN specifications PIN 1 ID Dimensions in mm 8 A Side View A3 A1 Two Step Singulation process Partially Plated Surface Bottom View D2 9 16 17 8 COMMON DIMENSIONS E2 (Unit of Measure = mm) 1 SYMBOL MIN 24 32 Z 25 e L Z 10:1 NOM MAX A 0.8 0.85 0.9 A1 A3 0 0.16 0.035 0.21 0.05 0.26 D 4.9 5 5.1 D2 3.5 3.6 3.7 E 4.9 5 5.1 E2 3.5 3.6 3.7 L 0.35 0.4 0.45 b 0.2 0.25 0.3 e NOTE 0.5 b 10/18/13 TITLE Package Drawing Contact: packagedrawings@atmel.com 38 Package: VQFN_5x5_32L Exposed pad 3.6x3.6 ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 GPC DRAWING NO. REV. 6.543-5124.03-4 1 7. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9315G-INDCO-08/15 Section 2.2 “Operating Modes Overview” on pages 13 to 14 updated Section 4.4 “Supply Voltages and Current Consumption” on page 24 updated 9315F-INDCO-11/14 Section 4.8 “I/O Characteristics for Ports PB0 to PB7 and PC0 to PC5” on pages 36 to 37 updated Section 5 “Ordering Information” on page 38 updated 9315E-INDCO-09/14 Section 4.5 “RF Receiving Characteristics” on pages 25 to 31 updated Section 6 “Package Information” on page 38 updated Features on page 2 updated Section 1.3 “Pinning” on pages 5 to 6 updated Section 1.4 “Typical Applications” on pages 9 to 10 updated 9315D-INDCO-07/14 Section 2.2 “Operating Modes Overview” on page 15 updated Section 3 “Hardware” on pages 16 to 17 updated Section 3.5 “Power Management” on page 22 updated Section 4 “Electrical Characteristics” on pages 22, 23, 34 and 35 updated 9315C-INDCO-04/14 9315BX-INDCO-03/14 “Atmel Confidential” removed on all pages ATA8505 renamed to ATA8515 on all pages Section 5 “Ordering Information” on page 38 updated ATA8510/ATA8515 [DATASHEET] 9315G–INDCO–08/15 39 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: 9315G–INDCO–08/15 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. 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