General Features
• Transmitter with Microcontroller Consisting of an AVR® Microcontroller and RF
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Transmitter PLL in a Single QFN24 5 mm × 5 mm Package (Pitch 0.65 mm)
– f0 = 868 MHz to 928 MHz
Temperature Range –40°C to +85°C
Supply Voltage 2.0V to 4.0V Allowing Usage of Single Li-cell Power Supply
Low Power Consumption
– Active Mode: Typical 9.8 mA at 3.0V and 4 MHz Microcontroller-clock
– Power-down Mode: Typical 200 nA at 3.0V
Modulation Scheme ASK/FSK
Integrated PLL Loop Filter
Output Power of 5.5 dBm at 868.3 MHz
Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
Single-ended Antenna Output with High Efficient Power Amplifier
Very Robust ESD Protection: HBM 2500V, MM100V, CDM 1000V
High Performance, Low Power AVR 8-bit Microcontroller, Similar to Popular ATtiny44
Well Known and Market-accepted RISC Architecture
Non-volatile Program and Data Memories
– 4 KBytes of In-system Programmable Program Memory Flash
– 256 Bytes In-system Programmable EEPROM
– 256 Bytes Internal SRAM
Programming Lock for Self-programming Flash Program and EEPROM Data Security
Peripheral Features
– Two Timer/Counter, 8- and 16-bit Counters with Two PWM Channels on Both
– 10-bit ADC
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Universal Serial Interface (USI)
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-system Programmable via SPI Port
– External and Internal Interrupt Sources
– Pin Change Interrupt on 12 Pins
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– On-chip Temperature Sensor
12 Programmable I/O Lines
Microcontroller
with
UHF ASK/FSK
Transmitter
ATA8743
1. General Description
The ATA8743 is a highly flexible programmable transmitter containing the AVR microcontroller ATtiny44V and the UHF PLL transmitters in a small QFN24 5 mm × 5 mm
package. This device is a member of a transmitter family covering several operating
frequency ranges, which has been specifically developed for the demands of RF
low-cost data transmission systems with data rates of up to 32 kBit/s. Its primary applications are in the areas of industrial/aftermarket Remote Keyless-Entry (RKE)
systems, alarm, telemetering, energy metering systems, home automotion/entertainment and toys. The ATA8743 can be used in the frequency band of f0 = 868 MHz for
ASK or FSK data transmission.
9152B–INDCO–02/10
Figure 1-1.
ASK System Block Diagram
UHF ASK/FSK
Remote Control Transmitter
ATA8743
S1
PXY
S1
PXY
GND
S1
PXY
PXY
PXY
PXY
PXY
PXY
PXY
PXY
PXY
PXY
ATtiny44V
VDD
VS
ATA8403
Power
up/down
CLK
f/4
PLL
ENABLE
UHF ASK/FSK
Remote Control Receiver
ATA8205
GND_RF
1 to 6
Demod
XTO
VCO
VCC_RF
Control
Microcontroller
VS
Antenna
PA_ENABLE
PLL
XTO
ANT2
PA
Loop
Antenna
LNA
ANT1
VCO
VS
2
ATA8743
9152B–INDCO–02/10
ATA8743
Figure 1-2.
FSK System Block Diagram
UHF ASK/FSK
Remote Control Transmitter
ATA8743
S1
PXY
S1
PXY
GND
S1
PXY
PXY
PXY
PXY
PXY
PXY
PXY
PXY
PXY
PXY
ATtiny44V
VDD
VS
ATA8403
Power
up/down
CLK
f/4
PLL
ENABLE
UHF ASK/FSK
Remote Control Receiver
ATA8205
GND_RF
1 to 6
Demod
XTO
VCO
VCC_RF
Control
Microcontroller
VS
Antenna
PA_ENABLE
PLL
XTO
ANT2
PA
Loop
Antenna
LNA
ANT1
VCO
VS
3
9152B–INDCO–02/10
2. Pin Configuration
ENABLE
GND_RF
VS_RF
XTAL
GND
Pinning QFN24 5 mm x 5 mm
GND
24
23
22
21
20
19
18
2
17
PA1
PB1
3
16
PA2
PB3/RESET
4
15
PA3/T0
PB2
5
14
PA4/USCK
PA7
6
PA5/MISO
PA6/MOSI
7
Table 2-1.
4
8
9
10
11
13
12
GND
PB0
ANT1
PA0
ANT2
1
CLK
VCC
PA_ENABLE
Figure 2-1.
Pin Description
Pin
Symbol
Function
1
VCC
Microcontroller supply voltage
2
PB0
Port B is a 4-bit bi-directional I/O port with internal pull-up resistor
3
PB1
4
PB3/RESET
Port B is a 4-bit bi-directional I/O port with internal pull-up resistor
5
PB2
Port B is a 4-bit bi-directional I/O port with internal pull-up resistor
6
PA7
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
7
PA6 / MOSI
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
8
CLK
Port B is a 4-bit bi-directional I/O port with internal pull-up resistor/reset input
Clock output signal for microcontroller. The clock output frequency is set by the crystal to fXTAL/4
9
PA_ENABLE
10
ANT2
Switches on power amplifier. Used for ASK modulation
11
ANT1
Open collector antenna output
12
GND
Ground
13
PA5/MISO
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
14
PA4/SCK
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
15
PA3/T0
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
16
PA2
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
17
PA1
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
18
PA0
Port A is a 4-bit bi-directional I/O port with internal pull-up resistor
Emitter of antenna output stage
19
GND
Microcontroller ground
20
XTAL
Connection for crystal
21
VS_RF
22
GND_RF
Transmitter ground
Transmitter supply voltage
23
ENABLE
Enable input
24
GND
Ground
GND
Ground/backplane (exposed die pad)
ATA8743
9152B–INDCO–02/10
ATA8743
2.1
Pin Configuration of RF Pins
Table 2-2.
Pin
Pin Description
Symbol
Function
Configuration
VS
8
CLK
Clock output signal for micro con roller
The clock output frequency is set by the
crystal to fXTAL/4
100Ω
CLK
100Ω
PA_ENABLE
9
PA_ENABLE
50 kΩ
UREF = 1.1V
Switches on power amplifier.
Used for ASK modulation
20 µA
ANT1
10
ANT2
Emitter of antenna output stage.
11
ANT1
Open collector antenna output.
ANT2
VS
1.5 kΩ
20
XTAL
VS
1.2 kΩ
Connection for crystal.
XTAL
182 µA
5
9152B–INDCO–02/10
Table 2-2.
Pin Description (Continued)
Pin
Symbol
21
VS
22
GND
23
ENABLE
Function
Configuration
Supply voltage
See ESD protection circuitry (see Figure 8-1 on page 12).
Ground
See ESD protection circuitry (see Figure 8-1 on page 12).
ENABLE
6
200 kΩ
Enable input
ATA8743
9152B–INDCO–02/10
ATA8743
3. Functional Description
For a typical application 3 to 4 interconnections between the AVR and the transmitter are
required (see Figure 1-1 on page 2 and Figure 1-2 on page 3). The CLK line is used to allow the
microcontroller to generate an XTAL-based transmitter signal. The ENABLE line is used to start
the XTO, PLL, and clock output of the transmitter. The PA_ENABLE line is used to enable the
power amplifier in ASK and FSK mode. In FSK mode a fourth line is necessary to modulate the
load capacity of the XTAL. To wake up the system from standby mode at least one key input is
required. After pressing the key, the microcontroller starts up with the internal RC oscillator. For
TX operation user software must control ENABLE, PA_ENABLE, and XTAL load capacity as
described in the following section.
If ENABLE = L and PA_ENABLE = L the transmitter and the microcontroller (MCU) are in
standby mode, reducing the power consumption so that a lithium cell can be used as power supply for several years.
If ENABLE = H and PA_ENABLE = L, the XTO, PLL, and the CLK driver from the transmitter are
activated. The crystal oscillator together with the PLL from the RF transmitter typically requires
< 1 ms until the PLL is locked and the clock output (Pin 8) is stable.
If ENABLE = H and PA_ENABLE = H, the XTO, PLL, CLK driver, and the power amplifier (PA)
are switched on. ASK modulation is achieved by switching on and off the power amplifier via
PA_ENABLE. FSK modulation is achieved by switching on and off an additional capacitor
between the XTAL load capacitor and GND, thus changing the reference frequency of the PLL.
This is done using a MOS switch controlled by a microcontroller output. The power amplifier is
switched on via PA_ENABLE = H.
The MCU has to wait at least > 4 ms after setting ENABLE = H, before the external clock can be
used. The external clock is connected via the timer0 input pin that clocks the USI from the MCU
to achieve an accurate data transfer. The frequency of the internal RC oscillator is affected by
ambient temperature and operating voltage.
The USI provides two serial synchronous data transfer modes, with different physical I/O ports
for the data output. The two wire mode is used for ASK and the three wire mode is used for FSK.
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very
small amount of current, so that a lithium cell used as power supply can work for several years.
With ENABLE = H the XTO, PLL, and the CLK driver are switched on. If PA_ENABLE remains L
only the PLL and the XTO are running and the CLK signal is delivered to the microcontroller.
The VCO locks to 64 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are
on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform
the ASK modulation.
7
9152B–INDCO–02/10
3.1
Description of RF Transmitter
The integrated PLL transmitter is particularly suited to simple, low-cost applications. The VCO is
locked to 64 × fXTAL hence a 13.5672 MHz crystal is needed for a 868.3 MHz transmitter and a
14.2969 MHz crystal for a 915 MHz transmitter. All other PLL and VCO peripheral elements are
integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements.
The crystal oscillator together with the PLL typically need < 1 ms until the PLL is locked and the
CLK output is stable. There is a wait time of ≥ 4 ms must be used until the CLK is used for the
microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse, which is nearly independent from the load impedance. Thus, the delivered output power is controllable via the
connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50Ω. This
results in a high power efficiency of η= P out /(I S,PA × V S ) of 24% for the power amplifier at
868.3 MHz when an optimized load impedance of ZLoad = (166 + j226)Ω is used at 3V supply
voltage.
3.2
ASK Transmission
The RF TX block is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the
CLK signal is taken to clock the AVR and the output power can be modulated by means of pin
PA_ENABLE. After transmission, PA_ENABLE is switched to L and the microcontroller switches
back to internal clocking. The RF TX is switched back to standby mode with ENABLE = L.
3.3
FSK Transmission
The RF TX is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK
signal is taken to clock the AVR and the power amplifier is switched on with PA_ENABLE = H.
The chip is then ready for FSK modulation. The AVR starts to switch on and off the capacitor
between the XTAL load capacitor and GND with an open-drain output port, thus changing the
reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the
switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches
back to internal clocking. The RF TX is switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered.
Figure 3-1.
Tolerances of the Frequency Modulation
VS
CStray1
CStray2
LM
C4
XTAL
CM
RS
C0
Crystal equivalent circuit
8
C5
CSwitch
ATA8743
9152B–INDCO–02/10
ATA8743
Using C4 = 9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF ±10%, a parallel capacitance of the
crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an FSK deviation of ±21.5 kHz
typical with worst case tolerances of ±16.8 kHz to ±28.0 kHz results.
3.4
CLK Output
An output CLK signal is provided for the integrated AVR. The delivered signal is CMOS compatible if the load capacitance is lower than 10 pF.
3.4.1
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel®’s AVR
microcontroller starts with an integrated RC-oscillator to switch on the RF TX with ENABLE = H,
and after 4 ms assumes the clock signal of the transmission IC, so that the message can be sent
with crystal accuracy.
3.4.2
Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is
achieved with a load impedance of ZLoad,opt = (166 + j226)Ω at 868.3 MHz. There must be a low
resistive path to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 7.7 mA and the maximum output power is
delivered to a resistive load of 475Ω if the 0.53 pF output capacitance of the power amplifier is
compensated by the load impedance.
An optimum load impedance of:
Z Load = 475Ω || j/(2 × p × f × 0.53 pF) = (166 + j226)Ω is achieved for the maximum output
power of 5.5 dBm.
The load impedance is defined as the impedance seen from the RF TX’s ANT1, ANT2 into the
matching network. This large signal load impedance should not be confused with the small signal input impedance delivered as input characteristic of RF amplifiers and measured from the
application into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 475Ω where the parallel imaginary part should be kept constant.
Output power measurement can be done using the circuit shown in Figure 8-4 on page 16. Note
that the component values must be changed to compensate the individual board parasitics until
the RF TX has the right load impedance ZLoad,opt = (166 + j226)Ω at 868.3 MHz. In addition, the
damping of the cable used to measure the output power must be calibrated out.
4. Microcontroller Block
More detailed information about the microcontroller block can be found in the appendix.
9
9152B–INDCO–02/10
5. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Minimum
Maximum
Unit
Supply voltage
VS
5
V
Power dissipation
Ptot
100
mW
Junction temperature
Tj
150
°C
Storage temperature
Tstg
125
°C
Tamb
–55
125
°C
VmaxPA_ENABLE
–0.3
(VS + 0.3)(1)
V
Ambient temperature
Input voltage
Note:
–55
1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.
6. Thermal Resistance
Parameters
Junction ambient
Symbol
Value
Unit
RthJA
170
K/W
7. Electrical Characteristics
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Symbol
Supply current
Power down, microcontroller Watchdog
timer disabled
IS_Off
Supply current
Power up, 4 MHz internal RC oscillator
IS_Transmit
Output power
VS = 3.0V, Tamb = 25°C,
f = 868.3 MHz, ZLoad = (166 + j226)Ω
Output power variation for the full
temperature range
Tamb = 25°C,
VS = 3.0V
VS = 2.0V
Output power variation for the full
temperature range
Tamb = 25°C,
VS = 3.0V
VS = 2.0V,
POut = PRef + ΔPRef
Achievable output-power range
Selectable by load impedance
Spurious emission
fCLK = f0/128
Load capacitance at pin CLK = 10 pF
fO ±1 × fCLK
fO ±4 × fCLK
other spurious are lower
Oscillator frequency XTO
(= phase comparator frequency)
fXTO = f0/64
fXTAL = resonant frequency of the XTAL,
CM ≤ 10 fF, load capacitance selected
accordingly
Tamb = 25°C,
PRef
Note:
10
Typ.
Max.
Unit
24.35
nA
µA
210
9.3
3.5
5.5
mA
8
dBm
ΔPRef
ΔPRef
–1.5
–4.0
dB
dB
ΔPRef
ΔPRef
–2.0
–4.5
dB
dB
+5.5
dBm
POut_typ
PLL loop bandwidth
Min.
–3
–52
–52
dBc
dBc
fXTO
–30
fXTAL
250
+30
ppm
kHz
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
ATA8743
9152B–INDCO–02/10
ATA8743
7. Electrical Characteristics (Continued)
VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Phase noise of phase comparator
Symbol
Typ.
Max.
Unit
Referred to fPC = fXT0,
25 kHz distance to carrier
–116
–110
dBc/Hz
In-loop phase noise PLL
25 kHz distance to carrier
–80
–74
dBc/Hz
Phase noise VCO
at 1 MHz
at 36 MHz
–89
–120
–86
–117
dBc/Hz
dBc/Hz
928
MHz
Frequency range of VCO
fVCO
Min.
868
Clock output frequency (CMOS
microcontroller compatible)
Voltage swing at pin CLK
f0/256
CLoad ≤ 10 pF
Series resonance R of the crystal
V0h
V0l
VS × 0.8
Rs
Capacitive load at pin XT0
MHz
VS × 0.2
V
V
110
Ω
7
pF
FSK modulation frequency rate
Duty cycle of the modulation signal = 50%
0
32
kHz
ASK modulation frequency rate
Duty cycle of the modulation signal = 50%
0
32
kHz
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
ENABLE input
20
V
V
µA
PA_ENABLE input
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
VS(1)
5
V
V
µA
Note:
1.7
1.7
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
11
9152B–INDCO–02/10
8. Application
For the supply-voltage blocking capacitor C3, a value of 68 nF/X7R is recommended. C1 and C2
are used to match the loop antenna to the power amplifier, where C1 typically is 3.9 pF/NP0 and
C2 is 1 pF/NP0; for C2 two capacitors in series should be used to achieve a better tolerance
value and to have the possibility of realizing the ZLoad,opt by using standard valued capacitors.
Together with the pins of T5750 and the PCB board wires, C1 forms a series resonance loop that
suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally the
best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and
ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop
antenna is too high.
L1 (≈ 50 nH to 100 nH) can be printed on PCB. C4 should be selected so that the XTO runs on
the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF
load-capacitance crystal.
Figure 8-1.
ESD Protection Circuit
VS
ANT1
CLK
PA_ENABLE
ANT2
XTAL
ENABLE
GND
12
ATA8743
9152B–INDCO–02/10
ATA8743
Typical ASK Application ATA8743
VCC
C8
C5
VDD
C7
21
20
XTAL
ENABLE
1
22
VCC_RF
23
GND
24
GND_RF
VCC
Q1
19
SW1
GND
Figure 8-2.
18
PA0
2
C6
R3
SW2
17
PB0/XTAL1
PA1
PB1/XTAL2
PA2
3
16
ATA874x
4
SW3
15
PA3/T0
PB3/RESET
5
14
PA4/SCK
13
GND
ANT1
PA5/MISO
ANT2
CLK
PA7
ADC7
PA6
ADC6
6
PA_ENABLE
PB2
R2
7
8
9
10
11
12
C1
VCC
R4
R1
L1
L2
C2
Table 8-1.
C3
C4
Bill of Material
Component
Type/
Manufacturer Note
Value
315 MHz
433.92 MHz
868.3 MHz
L1
100 nH
82 nH
22 nH
LL1608-FSL/
TOKO
L2
39 nH
27 nH
2.2 nH
LL1608-FSL/
TOKO
C1
1 nF
1 nF
1 nF
GRM1885C/
Murata
C2
3.9 pF
2.7 pF
1.5 pF
GRM1885C/
Murata
This cap must be placed as close as possible to
the pin Ant1 and Ant2
C3
27 pF
16 pF
4.3 pF
GRM1885C/
Murata
On the demo board 2 capacitors in series are
used to reduce the tolerance
C4
3.9 pF
1.6 pF
0.3 pF
GRM1885C/
Murata
On the demo board 2 capacitors in series are
used to reduce the tolerance
C5
68 nF
68 nF
68 nF
GRM188R71C/ This cap must placed as close as possible to the
Murata
VCC_RF
C6
100 nF
100 nF
100nF
GRM188R71C / This cap must placed as close as possible to the
Murata
VDD
13
9152B–INDCO–02/10
Table 8-1.
Bill of Material (Continued)
Component
Type/
Manufacturer Note
Value
C7
100 nF
100 nF
100 nF
GRM188R71C /
Murata
C8
10 pF
12 pF
12 pF
GRM1885C/
Murata
Q1
9.843750 MHz
13.56 MHz
13.567187 MHz
DSX530GK/
KDS
R1
100 kΩ
100 kΩ
100 kΩ
R2
100 kΩ
100 kΩ
100 kΩ
R3
10 kΩ
10 kΩ
10 kΩ
R4
1.8 kΩ
1.8 kΩ
1.8 kΩ
Figure 8-3.
This resistor can be resigned if the ASK
modulation is performed using PA5 (MISO).
Typical FSK Application ATA8743
C8
VCC
T1
C5
VDD
20
19
SW1
GND
21
XTAL
22
Q1
VCC_RF
1
23
GND_RF
GND
24
ENABLE
VCC
C9
18
PA0
2
C7
C6
R3
SW2
17
PB0/XTAL1
PA1
PB1/XTAL2
PA2
3
16
ATA874x
4
SW3
15
PA3/T0
PB3/RESET
5
14
PA4/SCK
13
GND
ANT1
PA5/MISO
ANT2
PA6
ADC6
PA7
ADC7
CLK
6
PA_ENABLE
PB2
R2
7
8
9
10
11
12
C1
VCC
R1
L1
L2
C2
Note:
14
C3
C4
FSK Modulation is Achieved by Switching on/off an Additional Capacitor Between the XTAL Load
Capacitor and GND. This is Done Using a MOS Switch Controlled by a Microcontroller Output.
ATA8743
9152B–INDCO–02/10
ATA8743
Table 8-2.
Bill of Material
Component
Type/
Manufacturer Note
Value
315 MHz
433.92 MHz
868.3 MHz
L1
100 nH
82 nH
22 nH
LL1608-FSL/
TOKO
L2
39 nH
27 nH
2.2 nH
LL1608-FSL/
TOKO
C1
1 nF
1 nF
1 nF
GRM1885C/
Murata
C2
3.9 pF
2.7 pF
1.5 pF
GRM1885C/
Murata
This cap must be placed as close as possible to
the pin Ant1 and Ant2
C3
27 pF
16 pF
4.3 pF
GRM1885C/
Murata
On the demo board 2 capacitors in series are
used to reduce the tolerance
C4
3.9 pF
1.6 pF
0.3 pF
GRM1885C/
Murata
On the demo board 2 capacitors in series are
used to reduce the tolerance
C5
68 nF
68 nF
68 nF
GRM188R71C/ This cap must placed as close as possible to the
Murata
VCC_RF
C6
100 nF
100 nF
100nF
GRM188R71C / This cap must placed as close as possible to the
Murata
VDD
C7
100 nF
100 nF
100 nF
GRM188R71C /
Murata
C8
3.9 pF
4.7 pF
5.6 pF
GRM1885C/
Murata
Frequency deviation of ±16 kHz will be performed
using the combination of C8 and C9
C9
18 pF
8.2 pF
5.6 pF
GRM1885C/
Murata
Frequency deviation of ±16 kHz will be performed
using the combination of C8 and C9
T1
BSS83
Q1
9.843750 MHz
13.56 MHz
13.567187 MHz
R1
100 kΩ
100 kΩ
100 kΩ
R2
100 kΩ
100 kΩ
100 kΩ
R3
10 kΩ
10 kΩ
10 kΩ
R4
1.8 kΩ
1.8 kΩ
1.8 kΩ
DSX530GK/
KDS
15
9152B–INDCO–02/10
Table 8-3.
Note:
Transmitter Pin Cross Reference List
Pin Name
Pin Number ATA8401/02/03
Pin Number ATA8741/42/43
CLK
1
8
PA_ENABLE
2
9
ANT2
3
10
ANT1
4
11
XTAL
5
20
VS
6
21
GND
7
22
ENABLE
8
23
For the ATA8743, the following points differs from the datasheets:
- The temperature range is limited to –40°C to +85°C
- ESD protection: HBM 2500V, MM 100V, CDM 1000V
- Figure 8-4 on page 16: Two output power measurement
- For FSK modulation, an additional MOS switch is required
Figure 8-4.
Output Power Measurement ATA8743
VS
C1 = 1 nF
L1 = 10 nH
ANT1
Z = 50Ω
ZLopt
ANT2
16
Power
meter
C2 = 0.5 pF
Rin
50Ω
ATA8743
9152B–INDCO–02/10
ATA8743
Table 8-4.
Note:
Microcontroller Cross Reference List
Pin Name
Pin Number
ATtiny44V
Pin Number
ATA8741/ATA8742/ATA8743
VCC
1
1
PB0
2
2
PB1
3
3
PB3/NRESET
4
4
PB2
5
5
PA7
6
6
PA6/MOSI
7
7
PA5/MISO
8
13
PA4/USCK
9
14
PA3/T0
10
15
PA2
11
16
PA1
12
17
PA0
13
18
GND
14
19
For the ATA8741/ATA8742/ATA8743, the following points differs from the ATtiny44V data sheet:
- The temperature range is limited to –40°C to +85°C
- The supply voltage range is limited from 2.0V to 4.0V
17
9152B–INDCO–02/10
Appendix: Microcontroller ATtiny24/44/84
18
ATA8743
9152B–INDCO–02/10
ATA8743
9. Overview
The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
9.1
Block Diagram
Figure 9-1.
Block Diagram
VCC
8-BIT DATABUS
INTERNAL
OSCILLATOR
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
MCU STATUS
REGISTER
GENERAL
PURPOSE
REGISTERS
TIMER/
COUNTER0
X
Y
Z
INSTRUCTION
DECODER
TIMER/
COUNTER1
CONTROL
LINES
ALU
STATUS
REGISTER
INTERRUPT
UNIT
ANALOG
COMPARATOR
+
-
PROGRAMMING
LOGIC
EEPROM
ISP INTERFACE
DATA REGISTER
PORT A
DATA DIR.
REG.PORT A
PORT A DRIVERS
PA7-PA0
ADC
OSCILLATORS
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
PB3-PB0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
19
9152B–INDCO–02/10
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32
general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit
timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,
programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable
Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
9.2
Automotive Quality Grade
The ATtiny24/44/84 have been developed and manufactured according to the most stringent
requirements of the international standard ISO-TS-16949 grade 1. This data sheet contains limit
values extracted from the results of extensive characterization (Temperature and Voltage). The
quality and reliability of the ATtiny24/44/84 have been verified during regular product qualification as per AEC-Q100.
As indicated in the ordering information paragraph, the product is available in only one temperature grade,
Table 9-1.
Temperature
-40; +125
20
Temperature Grade Identification for Automotive Products
Temperature
Identifier
Z
Comments
Full Automotive Temperature Range
ATA8743
9152B–INDCO–02/10
ATA8743
9.3
9.3.1
Pin Descriptions
VCC
Supply voltage.
9.3.2
GND
Ground.
9.3.3
Port B (PB3...PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of
RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on
Section 19.3 “Alternate Port Functions” on page 77.
9.3.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Figure 16-1 on page
56. Shorter pulses are not guaranteed to generate a reset.
9.3.5
Port A (PA7...PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 77
21
9152B–INDCO–02/10
10. Resources
A comprehensive set of development tools, drivers and application notes, and datasheets are
available for download on http://www.atmel.com/avr.
11. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
22
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ATA8743
12. CPU Core
12.1
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
12.2
Architectural Overview
Figure 12-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
Watchdog
Timer
ALU
Analog
Comparator
Timer/Counter 0
Data
SRAM
Timer/Counter 1
Universal
Serial Interface
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
23
9152B–INDCO–02/10
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
12.3
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
12.4
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
24
ATA8743
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ATA8743
12.4.1
SREG – AVR Status Register
Bit
7
6
5
4
3
2
1
0
0x3F (0x5F)
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
25
9152B–INDCO–02/10
12.5
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 12-2 on page 26 shows the structure of the 32 general purpose working registers in the
CPU.
Figure 12-2. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 12-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
12.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 12-3 on page 27.
26
ATA8743
9152B–INDCO–02/10
ATA8743
Figure 12-3. The X-, Y-, and Z-registers
15
XH
XL
7
X-register
0
R27 (0x1B)
YH
YL
7
0
R29 (0x1D)
Z-register
0
R26 (0x1A)
15
Y-register
0
7
0
7
0
R28 (0x1C)
15
ZH
7
0
ZL
7
R31 (0x1F)
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
12.6
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
12.6.1
SPH and SPL – Stack Pointer High and Low
Bit
15
14
13
12
11
10
9
8
0x3E (0x5E)
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
0x3D (0x5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
27
9152B–INDCO–02/10
12.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 12-4 on page 28 shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks, and functions per power-unit.
Figure 12-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 12-5 on page 28 shows the internal timing concept for the Register File. In a single clock
cycle an ALU operation using two register operands is executed, and the result is stored back to
the destination register.
Figure 12-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
12.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 66. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0.
28
ATA8743
9152B–INDCO–02/10
ATA8743
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence..
Assembly Code Example
in r16, SREG
cli
; store SREG value
; disable interrupts during timed sequence
sbi EECR, EEMPE
; start EEPROM write
sbi EECR, EEPE
out SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
