ATmega808/809/1608/1609
ATmega808/809/1608/1609 Data Sheet
Introduction
The ATmega808/809/1608/1609 microcontrollers are part of the megaAVR® 0-series, which uses the AVR®
processor with hardware multiplier running at up to 20 MHz, and offers a wide range of Flash sizes up to 48 KB,
up to 6 KB of SRAM, and 256 bytes of EEPROM in 28-, 32-, 40-, or 48-pin packages. The series uses the latest
technologies from Microchip with a flexible and low-power architecture, including Event System and SleepWalking,
accurate analog features, and advanced peripherals.
The devices described in this data sheet offer 8 or 16 KB in a 28/32/48-pin package.
megaAVR® 0-series Overview
The figure below shows the megaAVR® 0-series devices, laying out pin count variants and memory sizes:
•
•
Vertical migration is possible without code modification, as these devices are fully pin and feature compatible
Horizontal migration to the left reduces the pin count and, therefore, the available features
Figure 1. megaAVR® 0-series Overview
Devices described in this data sheet
Devices described in other data sheets
Flash
48 KB
ATmega4808
ATmega4808
32 KB
ATmega3208
ATmega3208
ATmega3209
16 KB
ATmega1608
ATmega1608
ATmega1609
8 KB
ATmega808
ATmega808
ATmega809
28
32
ATmega4809
40
ATmega4809
48
Pins
Devices with different Flash memory sizes typically also have different SRAM and EEPROM.
The name of a device in the megaAVR 0-series is decoded as follows:
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Complete Datasheet
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ATmega808/809/1608/1609
Figure 2. megaAVR® Device Designations
ATmega4809 - MFR - VAO
Variant Suffix
AVR® product family
Flash size in KB
Series name
Pin count
VAO = Automotive
Blank = Industrial
Carrier Type
R = Tape & Reel
Blank = Tube or Tray
9 = 48 pins (PDIP: 40 pins)
8 = 32 pins (SSOP: 28 pins)
Temperature Range
F = -40°C to +125°C (extended)
U = -40°C to +85°C (industrial)
Package Type
A = TQFP
M = VQFN
P = PDIP
X = SSOP
Memory Overview
Table 1. Memory Overview
Memory Type
ATmega808,
ATmega809
ATmega1608,
ATmega1609
ATmega3208,
ATmega3209
ATmega4808,
ATmega4809
Flash
8 KB
16 KB
32 KB
48 KB
SRAM
1 KB
2 KB
4 KB
6 KB
EEPROM
256B
256B
256B
256B
User row
32B
32B
64B
64B
Peripheral Overview
Table 2. Peripheral Overview
Feature
ATmega808
ATmega1608
ATmega3208
ATmega4808
ATmega808
ATmega1608
ATmega3208
ATmega4808
ATmega4809
ATmega809
ATmega1609
ATmega3209
ATmega4809
Pins
28
32
40
48
Max. frequency
(MHz)
20
20
20
20
16-bit Timer/Counter
type A (TCA)
1
1
1
1
16-bit Timer/Counter
type B (TCB)
3
3
4
4
12-bit Timer/Counter
type D (TCD)
-
-
-
-
Real-Time Counter
(RTC)
1
1
1
1
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ATmega808/809/1608/1609
...........continued
Feature
ATmega808
ATmega1608
ATmega3208
ATmega4808
ATmega808
ATmega1608
ATmega3208
ATmega4808
ATmega4809
ATmega809
ATmega1609
ATmega3209
ATmega4809
Pins
28
32
40
48
USART
3
3
4
4
SPI
1
1
1
1
1(1)
1(1)
1(1)
1(1)
ADC (channels)
1 (8)
1 (12)
1 (16)
1 (16)
DAC (outputs)
-
-
-
-
AC (inputs)
1 (4p/3n)
1 (4p/3n)
1 (4p/3n)
1 (4p/3n)
Peripheral Touch
Controller (PTC)
(self-cap/mutual cap
channels)
-
-
-
-
Custom Logic (LUTs)
1 (4)
1 (4)
1 (4)
1 (4)
Window Watchdog
1
1
1
1
Event System
channels
6
6
8
8
General purpose I/O
23
27
33
41
PORT
PA[0:7], PC[0:3],
PD[0:7], PF[0,1,6]
PA[0:7], PC[0:3],
PD[0:7], PF[0:6]
PA[0:7], PC[0:5],
PD[0:7], PE[0:3],
PF[0:6]
PA[0:7], PB[0:5],
PC[0:7], PD[0:7],
PE[0:3], PF[0:6]
Asynchronous
external interrupts
6
7
8
10
CRCSCAN
1
1
1
1
Unified Program
and Debug Interface
(UPDI) activated by
dedicated pin
1
1
1
1
TWI
1.
(I2C)
TWI can operate as host and client at the same time on different pins.
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ATmega808/809/1608/1609
Features
•
•
•
•
AVR® CPU:
– Single-cycle I/O access
– Two-level interrupt controller
– Two-cycle hardware multiplier
Memories:
– 8 or 16 KB In-system self-programmable Flash memory
– 256B EEPROM
– 2 KB SRAM
– Write/Erase endurance:
• Flash 10,000 cycles
• EEPROM 100,000 cycles
– Data retention: 40 years at 55°C
System:
– Power-on Reset (POR) circuit
– Brown-out Detector (BOD)
– Clock options:
• 16/20 MHz low-power internal oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal oscillator
• 32.768 kHz external crystal oscillator
• External clock input
– Single-pin Unified Program Debug Interface (UPDI)
– Three sleep modes:
• Idle with all peripherals running for immediate wake-up
• Standby
– Configurable operation of selected peripherals
– SleepWalking peripherals
• Power-Down with limited wake-up functionality
Peripherals:
– One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three compare channels
– Up to four 16-bit Timer/Counters type B (TCB) with input capture
– One 16-bit Real-Time Counter (RTC) running from an external crystal or an internal RC oscillator
– Up to four USARTs with fractional baud rate generator, auto-baud, and start-of-frame detection
– Host/client Serial Peripheral Interface (SPI)
– Host/client TWI with dual address match
• Can operate simultaneously as host and client
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
– Event System for core independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with up to four programmable Look-up Tables (LUT)
– One Analog Comparator (AC) with a scalable reference input
– One 10-bit 150 ksps Analog-to-Digital Converter (ADC)
– Five selectable internal voltage references: 0.55V, 1.1V, 1.5V, 2.5V, and 4.3V
– CRC code memory scan hardware
• Optional automatic CRC scan before code execution is allowed
– Watchdog Timer (WDT) with Window mode, with a separate on-chip oscillator
– External interrupt on all general purpose pins
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ATmega808/809/1608/1609
•
•
•
•
•
•
I/O and Packages:
– Up to 41 programmable I/O lines
– 28-pin SSOP
– 32-pin VQFN 5x5 and TQFP 7x7
– 48-pin VQFN 6x6 and TQFP 7x7
Temperature Ranges:
– Industrial: -40°C to +85°C
– Extended: -40°C to +125°C
Speed Grades -40°C to +105°C:
– 0-5 MHz @ 1.8V – 5.5V
– 0-10 MHz @ 2.7V – 5.5V
– 0-20 MHz @ 4.5V – 5.5V
Speed Grades +105°C to +125°C:
– 0-8 MHz @ 2.7V - 5.5V
– 0-16 MHz @ 4.5V - 5.5V
Speed Grades -40°C to +125°C - Automotive Range Parts (-VAO):
– 0-8 MHz @ 2.7V - 5.5V
– 0-16 MHz @ 4.5V - 5.5V
VAO variants available: Designed, manufactured, tested, and qualified per the AEC-Q100 requirements for
automotive applications.
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ATmega808/809/1608/1609
Table of Contents
Introduction.....................................................................................................................................................1
megaAVR® 0-series Overview....................................................................................................................... 1
1.
2.
Memory Overview........................................................................................................................ 2
Peripheral Overview..................................................................................................................... 2
Features......................................................................................................................................................... 4
1.
Silicon Errata and Data Sheet Clarification Document..........................................................................12
2.
Block Diagram.......................................................................................................................................13
3.
Pinout.................................................................................................................................................... 14
3.1.
3.2.
3.3.
4.
I/O Multiplexing and Considerations..................................................................................................... 18
4.1.
5.
Features..................................................................................................................................... 25
Overview.................................................................................................................................... 25
Architecture................................................................................................................................ 25
Arithmetic Logic Unit (ALU)........................................................................................................ 27
Functional Description................................................................................................................27
Register Summary......................................................................................................................33
Register Description................................................................................................................... 33
Memories.............................................................................................................................................. 37
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
8.
Numerical Notation.....................................................................................................................20
Memory Size and Type...............................................................................................................20
Frequency and Time...................................................................................................................20
Registers and Bits...................................................................................................................... 21
ADC Parameter Definitions........................................................................................................ 22
AVR® CPU............................................................................................................................................ 25
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
7.
Multiplexed Signals.................................................................................................................... 18
Conventions.......................................................................................................................................... 20
5.1.
5.2.
5.3.
5.4.
5.5.
6.
28-Pin SSOP.............................................................................................................................. 14
32-Pin VQFN/TQFP................................................................................................................... 15
48-Pin VQFN/TQFP................................................................................................................... 16
Overview.................................................................................................................................... 37
Memory Map.............................................................................................................................. 37
In-System Reprogrammable Flash Program Memory................................................................38
SRAM Data Memory.................................................................................................................. 39
EEPROM Data Memory............................................................................................................. 39
User Row (USERROW)............................................................................................................. 39
Signature Row (SIGROW)......................................................................................................... 39
Fuses (FUSE).............................................................................................................................52
Memory Section Access from CPU and UPDI on Locked Device..............................................61
I/O Memory.................................................................................................................................62
Peripherals and Architecture.................................................................................................................65
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ATmega808/809/1608/1609
8.1.
8.2.
8.3.
9.
Peripheral Module Address Map................................................................................................ 65
Interrupt Vector Mapping............................................................................................................ 66
SYSCFG - System Configuration............................................................................................... 68
NVMCTRL - Nonvolatile Memory Controller......................................................................................... 71
9.1.
9.2.
9.3.
9.4.
9.5.
Features..................................................................................................................................... 71
Overview.................................................................................................................................... 71
Functional Description................................................................................................................72
Register Summary......................................................................................................................78
Register Description................................................................................................................... 78
10. CLKCTRL - Clock Controller................................................................................................................. 86
10.1.
10.2.
10.3.
10.4.
10.5.
Features..................................................................................................................................... 86
Overview.................................................................................................................................... 86
Functional Description................................................................................................................88
Register Summary......................................................................................................................92
Register Description................................................................................................................... 92
11. SLPCTRL - Sleep Controller............................................................................................................... 102
11.1.
11.2.
11.3.
11.4.
11.5.
Features................................................................................................................................... 102
Overview.................................................................................................................................. 102
Functional Description..............................................................................................................102
Register Summary....................................................................................................................106
Register Description................................................................................................................. 106
12. RSTCTRL - Reset Controller.............................................................................................................. 108
12.1.
12.2.
12.3.
12.4.
12.5.
Features................................................................................................................................... 108
Overview.................................................................................................................................. 108
Functional Description..............................................................................................................109
Register Summary....................................................................................................................113
Register Description................................................................................................................. 113
13. CPUINT - CPU Interrupt Controller..................................................................................................... 116
13.1.
13.2.
13.3.
13.4.
13.5.
Features................................................................................................................................... 116
Overview...................................................................................................................................116
Functional Description.............................................................................................................. 117
Register Summary ...................................................................................................................122
Register Description................................................................................................................. 122
14. EVSYS - Event System.......................................................................................................................127
14.1.
14.2.
14.3.
14.4.
14.5.
Features................................................................................................................................... 127
Overview.................................................................................................................................. 127
Functional Description..............................................................................................................128
Register Summary....................................................................................................................133
Register Description................................................................................................................. 133
15. PORTMUX - Port Multiplexer.............................................................................................................. 138
15.1. Overview.................................................................................................................................. 138
15.2. Register Summary - PORTMUX.............................................................................................. 139
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ATmega808/809/1608/1609
15.3. Register Description................................................................................................................. 139
16. PORT - I/O Pin Configuration..............................................................................................................146
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
Features................................................................................................................................... 146
Overview.................................................................................................................................. 146
Functional Description..............................................................................................................148
Register Summary - PORTx.....................................................................................................152
Register Description - PORTx.................................................................................................. 152
Register Summary - VPORTx.................................................................................................. 165
Register Description - VPORTx................................................................................................165
17. BOD - Brown-out Detector.................................................................................................................. 170
17.1.
17.2.
17.3.
17.4.
17.5.
Features................................................................................................................................... 170
Overview.................................................................................................................................. 170
Functional Description..............................................................................................................171
Register Summary....................................................................................................................173
Register Description................................................................................................................. 173
18. VREF - Voltage Reference..................................................................................................................180
18.1.
18.2.
18.3.
18.4.
18.5.
Features................................................................................................................................... 180
Overview.................................................................................................................................. 180
Functional Description..............................................................................................................180
Register Summary - VREF.......................................................................................................181
Register Description................................................................................................................. 181
19. WDT - Watchdog Timer.......................................................................................................................184
19.1.
19.2.
19.3.
19.4.
19.5.
Features................................................................................................................................... 184
Overview.................................................................................................................................. 184
Functional Description..............................................................................................................185
Register Summary - WDT........................................................................................................ 188
Register Description................................................................................................................. 188
20. TCA - 16-bit Timer/Counter Type A.....................................................................................................191
20.1.
20.2.
20.3.
20.4.
20.5.
20.6.
20.7.
Features................................................................................................................................... 191
Overview.................................................................................................................................. 191
Functional Description..............................................................................................................193
Register Summary - Normal Mode...........................................................................................204
Register Description - Normal Mode........................................................................................ 204
Register Summary - Split Mode............................................................................................... 223
Register Description - Split Mode.............................................................................................223
21. TCB - 16-Bit Timer/Counter Type B.................................................................................................... 239
21.1.
21.2.
21.3.
21.4.
21.5.
Features................................................................................................................................... 239
Overview.................................................................................................................................. 239
Functional Description..............................................................................................................241
Register Summary....................................................................................................................249
Register Description................................................................................................................. 249
22. RTC - Real-Time Counter................................................................................................................... 260
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ATmega808/809/1608/1609
22.1. Features................................................................................................................................... 260
22.2. Overview.................................................................................................................................. 260
22.3. Clocks.......................................................................................................................................261
22.4. RTC Functional Description..................................................................................................... 261
22.5. PIT Functional Description....................................................................................................... 262
22.6. Crystal Error Correction............................................................................................................264
22.7. Events...................................................................................................................................... 264
22.8. Interrupts.................................................................................................................................. 265
22.9. Sleep Mode Operation............................................................................................................. 266
22.10. Synchronization........................................................................................................................266
22.11. Debug Operation...................................................................................................................... 266
22.12. Register Summary................................................................................................................... 267
22.13. Register Description.................................................................................................................267
23. USART - Universal Synchronous and Asynchronous Receiver and Transmitter................................284
23.1.
23.2.
23.3.
23.4.
23.5.
Features................................................................................................................................... 284
Overview.................................................................................................................................. 284
Functional Description..............................................................................................................285
Register Summary....................................................................................................................300
Register Description................................................................................................................. 300
24. SPI - Serial Peripheral Interface..........................................................................................................318
24.1.
24.2.
24.3.
24.4.
24.5.
Features................................................................................................................................... 318
Overview.................................................................................................................................. 318
Functional Description..............................................................................................................319
Register Summary....................................................................................................................326
Register Description................................................................................................................. 326
25. TWI - Two-Wire Interface.................................................................................................................... 333
25.1.
25.2.
25.3.
25.4.
25.5.
Features................................................................................................................................... 333
Overview.................................................................................................................................. 333
Functional Description..............................................................................................................334
Register Summary....................................................................................................................345
Register Description................................................................................................................. 345
26. CRCSCAN - Cyclic Redundancy Check Memory Scan...................................................................... 363
26.1.
26.2.
26.3.
26.4.
26.5.
Features................................................................................................................................... 363
Overview.................................................................................................................................. 363
Functional Description..............................................................................................................364
Register Summary - CRCSCAN...............................................................................................367
Register Description................................................................................................................. 367
27. CCL - Configurable Custom Logic...................................................................................................... 371
27.1.
27.2.
27.3.
27.4.
27.5.
Features................................................................................................................................... 371
Overview.................................................................................................................................. 371
Functional Description..............................................................................................................373
Register Summary ...................................................................................................................381
Register Description................................................................................................................. 381
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ATmega808/809/1608/1609
28. AC - Analog Comparator.....................................................................................................................391
28.1.
28.2.
28.3.
28.4.
28.5.
Features................................................................................................................................... 391
Overview.................................................................................................................................. 391
Functional Description..............................................................................................................392
Register Summary....................................................................................................................394
Register Description................................................................................................................. 394
29. ADC - Analog-to-Digital Converter...................................................................................................... 400
29.1.
29.2.
29.3.
29.4.
29.5.
Features................................................................................................................................... 400
Overview.................................................................................................................................. 400
Functional Description..............................................................................................................401
Register Summary - ADCn.......................................................................................................408
Register Description................................................................................................................. 408
30. UPDI - Unified Program and Debug Interface.....................................................................................426
30.1.
30.2.
30.3.
30.4.
30.5.
Features................................................................................................................................... 426
Overview.................................................................................................................................. 426
Functional Description..............................................................................................................428
Register Summary....................................................................................................................446
Register Description................................................................................................................. 446
31. Instruction Set Summary.....................................................................................................................458
32. Electrical Characteristics.....................................................................................................................459
32.1. Disclaimer.................................................................................................................................459
32.2. Absolute Maximum Ratings .....................................................................................................459
32.3. General Operating Ratings ......................................................................................................459
32.4. Power Considerations.............................................................................................................. 461
32.5. Power Consumption................................................................................................................. 462
32.6. Wake-Up Time..........................................................................................................................464
32.7. Peripherals Power Consumption..............................................................................................465
32.8. BOD and POR Characteristics................................................................................................. 466
32.9. External Reset Characteristics................................................................................................. 467
32.10. Oscillators and Clocks..............................................................................................................467
32.11. I/O Pin Characteristics..............................................................................................................469
32.12. USART..................................................................................................................................... 470
32.13. SPI........................................................................................................................................... 471
32.14. TWI...........................................................................................................................................472
32.15. VREF........................................................................................................................................475
32.16. ADC..........................................................................................................................................476
32.17. TEMPSENSE........................................................................................................................... 479
32.18. AC............................................................................................................................................ 480
32.19. UPDI.........................................................................................................................................481
32.20. Programming Time...................................................................................................................482
33. Typical Characteristics........................................................................................................................ 483
33.1. Power Consumption................................................................................................................. 483
33.2. GPIO........................................................................................................................................ 492
33.3. VREF Characteristics............................................................................................................... 499
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ATmega808/809/1608/1609
33.4.
33.5.
33.6.
33.7.
33.8.
33.9.
BOD Characteristics.................................................................................................................501
ADC Characteristics................................................................................................................. 504
TEMPSENSE Characteristics.................................................................................................. 514
AC Characteristics....................................................................................................................515
OSC20M Characteristics..........................................................................................................517
OSCULP32K Characteristics................................................................................................... 519
34. Ordering Information........................................................................................................................... 520
35. Package Drawings.............................................................................................................................. 522
35.1.
35.2.
35.3.
35.4.
35.5.
35.6.
35.7.
Package Marking Information...................................................................................................522
Online Package Drawings........................................................................................................ 523
28-Pin SSOP............................................................................................................................ 525
32-Pin TQFP............................................................................................................................ 528
32-Pin VQFN............................................................................................................................ 531
48-Pin TQFP............................................................................................................................ 534
48-Pin VQFN............................................................................................................................ 537
36. Data Sheet Revision History............................................................................................................... 540
36.1.
36.2.
36.3.
36.4.
Rev. C - 03/2021...................................................................................................................... 540
Rev. B - 06/2020.......................................................................................................................545
Rev. A - 01/2020.......................................................................................................................545
Appendix - Obsolete Revision History......................................................................................546
The Microchip Website...............................................................................................................................549
Product Change Notification Service..........................................................................................................549
Customer Support...................................................................................................................................... 549
Product Identification System.....................................................................................................................550
Microchip Devices Code Protection Feature.............................................................................................. 550
Legal Notice............................................................................................................................................... 550
Trademarks................................................................................................................................................ 551
Quality Management System..................................................................................................................... 551
Worldwide Sales and Service.....................................................................................................................552
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ATmega808/809/1608/1609
Silicon Errata and Data Sheet Clarification ...
1.
Silicon Errata and Data Sheet Clarification Document
We intend to provide our customers with the best documentation possible to ensure the successful use of Microchip
products. Between data sheet updates, a Silicon Errata and Data Sheet Clarification Document will contain the most
recent information for the data sheet. The ATmega808/809/1608/1609 Silicon Errata and Data Sheet Clarification
Document (microchip.com/DS80000868) is available at the device product page on www.microchip.com.
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ATmega808/809/1608/1609
Block Diagram
2.
Block Diagram
UPDI
UPDI
CRC
CPU
OCD
Flash
SRAM
BUS Matrix
EEPROM
NVMCTRL
AINPn
AINNn
OUT
AINn
VREFA
EVOUTx
LUTn-INn
LUTn-OUT
WOn
WO
PORTS
ACn
GPIOR
ADCn
EVSYS
CCL
TCAn
TCBn
RXD
TXD
XCK
XDIR
USARTn
MISO
MOSI
SCK
SS
SPIn
SDA (host)
SCL (host)
SDA (client)
SCL (client)
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
CPUINT
I
N
/
O
U
T
D
A
T
A
B
U
S
System
Management
RSTCTRL
PAn
PBn
PCn
PDn
PEn
PFn
Detectors/
References
RESET
RST
POR
Bandgap
BOD/
VLM
CLKCTRL
SLPCTRL
Clock Generation
CLKOUT
WDT
OSC20M
EXTCLK
OSC32K
RTC
TOSC1
XOSC32K
TOSC2
TWIn
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ATmega808/809/1608/1609
Pinout
3.
Pinout
3.1
28-Pin SSOP
PA7
1
28
PA6
PC0
2
27
PA5
PC1
3
26
PA4
PC2
4
25
PA3
PC3
5
24
PA2
PD0
6
23
PA1
PD1
7
22
PA0 (EXTCLK)
PD2
8
21
GND
PD3
9
20
VDD
PD4
10
19
UPDI
PD5
11
18
PF6 (RESET)
PD6
12
17
PF1 (TOSC2)
PD7
13
16
PF0 (TOSC1)
AVDD
14
15
GND
Power
Functionality
Input supply
Programming, debug
Ground
Clock, crystal
GPIO on VDD power domain
TWI
GPIO on AVDD power domain
Digital functions only
Analog functions
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ATmega808/809/1608/1609
Pinout
PA2
PA1
PA0 (EXTCLK)
GND
VDD
UPDI
PF6 (RESET)
PF5
32
31
30
29
28
27
26
25
32-Pin VQFN/TQFP
PF1 (TOSC2)
PA7
5
20
PF0 (TOSC1)
PC0
6
19
GND
PC1
7
18
AVDD
PC2
8
17
PD7
16
21
PD6
4
15
PA6
PD5
PF2
14
22
PD4
3
13
PA5
PD3
PF3
12
23
PD2
2
11
PA4
PD1
PF4
10
24
PD0
1
9
PA3
PC3
3.2
Power
Functionality
Input supply
Programming, debug
Ground
Clock, crystal
GPIO on VDD power domain
TWI
GPIO on AVDD power domain
Digital functions only
Analog functions
Note: The center pad underneath the QFN packages can be connected to PCB ground or left electrically
unconnected. Solder or glue it to the board to ensure good mechanical stability. If the center pad is not attached, the
package might loosen from the board.
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ATmega808/809/1608/1609
Pinout
PA4
PA3
PA2
PA1
PA0 (EXTCLK)
GND
VDD
UPDI
PF6 (RESET)
PF5
PF4
PF3
48
47
46
45
44
43
42
41
40
39
38
37
48-Pin VQFN/TQFP
PE1
PB3
7
30
PE0
PB4
8
29
GND
PB5
9
28
AVDD
PC0
10
27
PD7
PC1
11
26
PD6
PC2
12
25
PD5
24
31
PD4
6
23
PB2
PD3
PE2
22
32
PD2
5
21
PB1
PD1
PE3
20
33
PD0
4
19
PB0
PC7
PF0 (TOSC1)
18
34
PC6
3
17
PA7
PC5
PF1 (TOSC2)
16
35
PC4
2
15
PA6
GND
PF2
14
36
VDD
1
13
PA5
PC3
3.3
Power
Functionality
Input supply
Programming, debug
Ground
Clock, crystal
GPIO on VDD power domain
TWI
GPIO on AVDD power domain
Digital functions only
Analog functions
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Complete Datasheet
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ATmega808/809/1608/1609
Pinout
Note: The center pad underneath the QFN packages can be connected to PCB ground or left electrically
unconnected. Solder or glue it to the board to ensure good mechanical stability. If the center pad is not attached, the
package might loosen from the board.
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Complete Datasheet
DS40002172C-page 17
ATmega808/809/1608/1609
I/O Multiplexing and Considerations
4.
I/O Multiplexing and Considerations
4.1
Multiplexed Signals
TQFP48/
VQFN48
TQFP32/
VQFN32
SSOP28
Pin name(1,2)
Special
44
30
22
PA0
EXTCLK
45
31
23
PA1
46
32
24
PA2
TWI
0,XCK
SDA(MS)
0-WO2
0-WO
47
1
25
PA3
TWI
0,XDIR
SCL(MS)
0-WO3
1-WO
48
2
26
PA4
0,TxD(3)
MOSI
0-WO4
1
3
27
PA5
0,RxD(3)
MISO
0-WO5
2
4
28
PA6
0,XCK(3)
SCK
3
5
1
PA7
0,XDIR(3)
SS
ADC0
CLKOUT
AC0
OUT
USARTn
SPI0
TWI0
TCA0
0,TxD
0-WO0
0,RxD
0-WO1
TCBn
EVSYS
CCL-LUTn
0-IN0
0-IN1
EVOUTA
0-IN2
0-OUT
0-OUT(3)
EVOUTA(3)
4
PB0
3,TxD
0-WO0(3)
5
PB1
3,RxD
0-WO1(3)
6
PB2
3,XCK
0-WO2(3)
7
PB3
3,XDIR
0-WO3(3)
8
PB4
3,TxD(3)
0-WO4(3)
2-WO(3)
0-WO5(3)
3-WO
EVOUTB
PB5
3,RxD(3)
10
6
2
PC0
1,TxD
MOSI(3)
0-WO0(3)
2-WO
1-IN0
11
7
3
PC1
1,RxD
MISO(3)
0-WO1(3)
3-WO(3)
1-IN1
SDA(MS)(3)
0-WO2(3)
SCL(MS)(3)
0-WO3(3)
9
12
8
4
PC2
TWI
1,XCK
SCK(3)
13
9
5
PC3
TWI
1,XDIR
SS(3)
14
VDD
15
GND
16
PC4
1,TxD(3)
0-WO4(3)
17
PC5
1,RxD(3)
0-WO5(3)
18
PC6
1,XCK(3)
19
PC7
1,XDIR(3)
1-OUT(3)
0-WO0(3)
10
6
PD0
AIN0
21
11
7
PD1
AIN1
P3
0-WO1(3)
22
12
8
PD2
AIN2
P0
0-WO2(3)
23
13
9
PD3
AIN3
N0
0-WO3(3)
24
14
10
PD4
AIN4
P1
0-WO4(3)
25
15
11
PD5
AIN5
N1
0-WO5(3)
26
16
12
PD6
27
17
13
PD7
28
18
14
AVDD
29
19
15
GND
AIN6
P2
AIN7
N2
PE0
AIN8
MOSI(3)
0-WO0(3)
PE1
AIN9
MISO(3)
0-WO1(3)
AIN10
SCK(3)
0-WO2(3)
AIN11
SS(3)
0-WO3(3)
33
PE3
2-IN1
EVOUTD
2-IN2
2-OUT
2-OUT(3)
31
PE2
2-IN0
EVOUTD(3)
30
32
1-IN2
1-OUT
EVOUTC(3)
20
VREFA
EVOUTC
EVOUTE
34
20
16
PF0
TOSC1
2,TxD
0-WO0(3)
3-IN0
35
21
17
PF1
TOSC2
2,RxD
0-WO1(3)
3-IN1
36
22
PF2
TWI
AIN12
2,XCK
SDA(S)(3)
37
23
PF3
TWI
AIN13
2,XDIR
SCL(S)(3)
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Complete Datasheet
0-WO2(3)
0-WO3(3)
EVOUTF
3-IN2
3-OUT
DS40002172C-page 18
ATmega808/809/1608/1609
I/O Multiplexing and Considerations
...........continued
SSOP28
Pin name(1,2)
TQFP48/
VQFN48
TQFP32/
VQFN32
38
24
PF4
AIN14
39
25
PF5
AIN15
40
26
18
PF6
41
27
19
UPDI
42
28
20
VDD
43
29
21
GND
Special
RESET
ADC0
AC0
USARTn
SPI0
TWI0
TCA0
TCBn
2,TxD(3)
0-WO4(3)
0-WO(3)
2,RxD(3)
0-WO5(3)
1-WO(3)
EVSYS
2,XCK(3)
CCL-LUTn
3-OUT(3)
Notes:
1. Pin names are of type Pxn, with x being the PORT instance (A,B,C, ...) and n the pin number. Notation for
signals is PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to the PORTMUX documentation.
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ATmega808/809/1608/1609
Conventions
5.
Conventions
5.1
Numerical Notation
Table 5-1. Numerical Notation
5.2
Symbol
Description
165
Decimal number
0b0101
Binary number
‘0101’
Binary numbers are given without prefix if unambiguous
0x3B24
Hexadecimal number
X
Represents an unknown or do not care value
Z
Represents a high-impedance (floating) state for either a
signal or a bus
Memory Size and Type
Table 5-2. Memory Size and Bit Rate
5.3
Symbol
Description
KB
kilobyte (210B = 1024B)
MB
megabyte (220B = 1024 KB)
GB
gigabyte (230B = 1024 MB)
b
bit (binary ‘0’ or ‘1’)
B
byte (8 bits)
1 kbit/s
1,000 bit/s rate
1 Mbit/s
1,000,000 bit/s rate
1 Gbit/s
1,000,000,000 bit/s rate
word
16-bit
Frequency and Time
Table 5-3. Frequency and Time
Symbol
Description
kHz
1 kHz = 103 Hz = 1,000 Hz
MHz
1 MHz = 106 Hz = 1,000,000 Hz
GHz
1 GHz = 109 Hz = 1,000,000,000 Hz
ms
1 ms = 10-3s = 0.001s
µs
1 µs = 10-6s = 0.000001s
ns
1 ns = 10-9s = 0.000000001s
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ATmega808/809/1608/1609
Conventions
5.4
Registers and Bits
Table 5-4. Register and Bit Mnemonics
Symbol
Description
R/W
Read/Write accessible register bit. The user can read from and write to this bit.
R
Read-only accessible register bit. The user can only read this bit. Writes will be ignored.
W
Write-only accessible register bit. The user can only write this bit. Reading this bit will return an
undefined value.
BITFIELD
Bitfield names are shown in uppercase. Example: INTMODE.
BITFIELD[n:m]
A set of bits from bit n down to m. Example: PINA[3:0] = {PINA3, PINA2, PINA1, PINA0}.
Reserved
Reserved bits, bit fields, and bit field values are unused and reserved for future use. For
compatibility with future devices, always write reserved bits to ‘0’ when the register is written.
Reserved bits will always return zero when read.
PERIPHERALn
If several instances of the peripheral exist, the peripheral name is followed by a single number to
identify one instance. Example: USARTn is the collection of all instances of the USART module,
while USART3 is one specific instance of the USART module.
PERIPHERALx
If several instances of the peripheral exist, the peripheral name is followed by a single capital
letter (A-Z) to identify one instance. Example: PORTx is the collection of all instances of the
PORT module, while PORTB is one specific instance of the PORT module.
Reset
Value of a register after a Power-on Reset. This is also the value of registers in a peripheral after
performing a software Reset of the peripheral, except for the Debug Control registers.
SET/CLR/TGL
Registers with SET/CLR/TGL suffix allow the user to clear and set bits in a register without doing
a read-modify-write operation.
Each SET/CLR/TGL register is paired with the register it is affecting. Both registers in a register
pair return the same value when read.
Example: In the PORT peripheral, the OUT and OUTSET registers form such a register pair. The
contents of OUT will be modified by a write to OUTSET. Reading OUT and OUTSET will return
the same value.
Writing a ‘1’ to a bit in the CLR register will clear the corresponding bit in both registers.
Writing a ‘1’ to a bit in the SET register will set the corresponding bit in both registers.
Writing a ‘1’ to a bit in the TGL register will toggle the corresponding bit in both registers.
5.4.1
Addressing Registers from Header Files
In order to address registers in the supplied C header files, the following rules apply:
1.
2.
3.
4.
A register is identified by ., e.g., CPU.SREG, USART2.CTRLA,
or PORTB.DIR.
The peripheral name is given in the “Peripheral Address Map” in the “Peripherals and Architecture” section.
is obtained by substituting any n or x in the peripheral name with the correct
instance identifier.
When assigning a predefined value to a peripheral register, the value is constructed following the rule:
___gc
is , but remove any instance identifier.
can be found in the “Name” column in the tables in the Register Description sections
describing the bit fields of the peripheral registers.
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ATmega808/809/1608/1609
Conventions
Example 5-1. Register Assignments
// EVSYS channel 0 is driven by TCB3 OVF event
EVSYS.CHANNEL0 = EVSYS_CHANNEL0_TCB3_OVF_gc;
// USART0 RXMODE uses Double Transmission Speed
USART0.CTRLB = USART_RXMODE_CLK2X_gc;
Note: For peripherals with different register sets in different modes, and
must be followed by a mode name, for example:
// TCA0 in Normal Mode (SINGLE) uses waveform generator in frequency mode
TCA0.SINGLE.CTRL=TCA_SINGLE_WGMODE_FRQ_gc;
5.5
ADC Parameter Definitions
An ideal n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSb). The lowest
code is read as ‘0’, and the highest code is read as ‘2n-1’. Several parameters describe the deviation from the ideal
behavior:
Offset Error
The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5
LSb). Ideal value: 0 LSb.
Figure 5-1. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
Gain Error
VREF Input Voltage
After adjusting for offset, the gain error is found as the deviation of the last transition (e.g.,
0x3FE to 0x3FF for a 10-bit ADC) compared to the ideal transition (at 1.5 LSb below
maximum). Ideal value: 0 LSb.
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ATmega808/809/1608/1609
Conventions
Figure 5-2. Gain Error
Gain
Error
Output Code
Ideal ADC
Actual ADC
VREF
Integral
Nonlinearity (INL)
Input Voltage
After adjusting for offset and gain error, the INL is the maximum deviation of an actual
transition compared to an ideal transition for any code. Ideal value: 0 LSb.
Figure 5-3. Integral Nonlinearity
Output Code
INL
Ideal ADC
Actual ADC
VREF
Differential
Nonlinearity (DNL)
Input Voltage
The maximum deviation of the actual code width (the interval between two adjacent
transitions) from the ideal code width (1 LSb). Ideal value: 0 LSb.
Figure 5-4. Differential Nonlinearity
Output Code
0x3FF
1 LSb
DNL
0x000
0
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Input Voltage
DS40002172C-page 23
ATmega808/809/1608/1609
Conventions
Quantization Error
Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSb wide) will code to the same value. Always ±0.5 LSb.
Absolute Accuracy The maximum deviation of an actual (unadjusted) transition compared to an ideal transition
for any code. This is the compound effect of all errors mentioned before. Ideal value: ±0.5
LSb.
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Complete Datasheet
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ATmega808/809/1608/1609
AVR® CPU
6.
AVR® CPU
6.1
Features
•
•
•
•
•
•
•
•
6.2
8-Bit, High-Performance AVR RISC CPU:
– 135 instructions
– Hardware multiplier
32 8-Bit Registers Directly Connected to the ALU
Stack in RAM
Stack Pointer Accessible in I/O Memory Space
Direct Addressing of up to 64 KB of Unified Memory
Efficient Support for 8-, 16-, and 32-Bit Arithmetic
Configuration Change Protection for System-Critical Features
Native On-Chip Debugging (OCD) Support:
– Two hardware breakpoints
– Change of flow, interrupt, and software breakpoints
– Run-time read-out of Stack Pointer (SP) register, Program Counter (PC), and Status Register (SREG)
– Register file read- and writable in Stopped mode
Overview
All AVR devices use the AVR 8-bit CPU. The CPU is able to access memories, perform calculations, control
peripherals, and execute instructions in the program memory. Interrupt handling is described in a separate section.
6.3
Architecture
To maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses for
program and data. The instructions in the program memory are executed with a single-level pipeline. While one
instruction is being executed, the next instruction is prefetched from the program memory. This enables instructions
to be executed on every clock cycle.
Refer to the Instruction Set Summary section for a summary of all AVR instructions.
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ATmega808/809/1608/1609
AVR® CPU
Figure 6-1. AVR® CPU Architecture
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R18
R16
R14
R12
R10
R8
R6
R4
R2
R0
Program
Counter
Flash Program
Memory
Instruction
Register
Instruction
Decode
Data Memory
Stack
Pointer
Status
Register
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ALU
Complete Datasheet
DS40002172C-page 26
ATmega808/809/1608/1609
AVR® CPU
6.4
Arithmetic Logic Unit (ALU)
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between working registers, or between a
constant and a working register. Also, single-register operations can be executed.
The ALU operates in a direct connection with all the 32 general purpose working registers in the register file.
The arithmetic operations between working registers or between a working register and an immediate operand are
executed in a single clock cycle, and the result is stored in the register file. After an arithmetic or logic operation, the
Status Register (CPU.SREG) is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic are supported, and the instruction set allows for an efficient implementation of the 32-bit arithmetic. The
hardware multiplier supports signed and unsigned multiplication and fractional formats.
6.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports
different variations of signed and unsigned integer and fractional numbers:
•
•
•
•
Multiplication of signed/unsigned integers
Multiplication of signed/unsigned fractional numbers
Multiplication of a signed integer with an unsigned integer
Multiplication of a signed fractional number with an unsigned fractional number
A multiplication takes two CPU clock cycles.
6.5
6.5.1
Functional Description
Program Flow
After being reset, the CPU will execute instructions from the lowest address in the Flash program memory, 0x0000.
The Program Counter (PC) addresses the next instruction to be fetched.
The CPU supports instructions that can change the program flow conditionally or unconditionally and are capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format, and a limited number
use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack as a word pointer. The stack is
allocated in the general data SRAM, and consequently, the stack size is only limited by the total SRAM size and the
usage of the SRAM. After the Stack Pointer (SP) is reset, it points to the highest address in the internal SRAM. The
SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas.
The data SRAM can easily be accessed through the five different Addressing modes supported by the AVR CPU.
6.5.2
Instruction Execution Timing
The AVR CPU is clocked by the CPU clock, CLK_CPU. No internal clock division is applied. The figure below shows
the parallel instruction fetches and executions enabled by the Harvard architecture and the fast-access register file
concept. This is the basic pipelining concept enabling up to 1 MIPS/MHz performance with high efficiency.
Figure 6-2. The Parallel Instruction Fetches and Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU operation
using two register operands is executed, and the result is stored in the destination register.
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Complete Datasheet
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ATmega808/809/1608/1609
AVR® CPU
Figure 6-3. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
6.5.3
Status Register
The Status Register (CPU.SREG) contains information about the result of the most recently executed arithmetic or
logic instructions. This information can be used for altering the program flow to perform conditional operations.
CPU.SREG is updated after all ALU operations, as specified in the Instruction Set Summary section. This will, in
many cases, remove the need for using the dedicated compare instructions, resulting in a faster and more compact
code. CPU.SREG is not automatically stored or restored when entering or returning from an Interrupt Service
Routine (ISR). Therefore, maintaining the Status Register between context switches must be handled by user-defined
software. CPU.SREG is accessible in the I/O memory space.
6.5.4
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. Also, it can be used for storing
temporary data. The Stack Pointer (SP) always points to the top of the stack. The address pointed to by the SP is
stored in the Stack Pointer (CPU.SP) register. The CPU.SP is implemented as two 8-bit registers that are accessible
in the I/O memory space.
Data are pushed and popped from the stack using the instructions given in Table 6-1, or by executing interrupts.
The stack grows from higher to lower memory locations. This means that when pushing data onto the stack, the
SP decreases, and when popping data off the stack, the SP increases. The SP is automatically set to the highest
address of the internal SRAM after being reset. If the stack is changed, it must be set to point above the SRAM
start address (see the SRAM Data Memory topic in the Memories section for the SRAM start address), and it must
be defined before any subroutine calls are executed and before interrupts are enabled. See the table below for SP
details.
Table 6-1. Stack Pointer Instructions
Instruction
Stack Pointer
Description
PUSH
Decremented by 1 Data are pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2 A return address is pushed onto the stack with a subroutine call or interrupt
POP
Incremented by 1
Data are popped from the stack
RET
RETI
Incremented by 2
A return address is popped from the stack with a return from subroutine or return
from interrupt
During interrupts or subroutine calls, the return address is automatically pushed on the stack as a word, and the SP is
decremented by two. The return address consists of two bytes and the Least Significant Byte (LSB) is pushed on the
stack first (at the higher address). As an example, a byte pointer return address of 0x0006 is saved on the stack as
0x0003 (shifted one bit to the right), pointing to the fourth 16-bit instruction word in the program memory. The return
address is popped off the stack with RETI (when returning from interrupts) and RET (when returning from subroutine
calls), and the SP is incremented by two.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by
one when data are popped off the stack using the POP instruction.
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ATmega808/809/1608/1609
AVR® CPU
To prevent corruption when updating the SP from software, a write to SPL will automatically disable interrupts for up
to four instructions or until the next I/O memory write, whichever comes first.
6.5.5
Register File
The register file consists of 32 8-bit general purpose working registers used by the CPU. The register file is located in
a separate address space from the data memory.
All CPU instructions that operate on working registers have direct and single-cycle access to the register file. Some
limitations apply to which working registers can be accessed by an instruction, like the constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, ORI and LDI. These instructions apply to the second half of the working
registers in the register file, R16 to R31. See the AVR Instruction Set Manual for further details.
Figure 6-4. AVR® CPU General Purpose Working Registers
0 Addr.
7
0x00
R0
0x01
R1
0x02
R2
...
R13
R14
R15
R16
R17
0x0D
0x0E
0x0F
0x10
0x11
R26
R27
R28
R29
R30
R31
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
...
6.5.5.1
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
The X-, Y-, and Z-Registers
Working registers R26...R31 have added functions besides their general purpose usage.
These registers can form 16-bit Address Pointers for indirect addressing of data memory. These three address
registers are called the X-register, Y-register, and Z-register. The Z-register can also be used as Address Pointer for
program memory.
Figure 6-5. The X-, Y-, and Z-Registers
Bit (individually)
7
X-register
15
Bit (individually)
7
Y-register
Bit (individually)
7
R29
15
7
R31
8
7
0
7
0
0
R28
0
YL
8
7
0
7
8
7
ZH
15
R26
XL
YH
Z-register
Bit (Z-register)
0
XH
Bit (X-register)
Bit (Y-register)
R27
0
R30
0
ZL
0
The lowest register address holds the Least Significant Byte (LSB), and the highest register address holds the
Most Significant Byte (MSB). These address registers can function as fixed displacement, automatic increment, and
automatic decrement, with different LD*/ST* instructions. See the Instruction Set Summary section for details.
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ATmega808/809/1608/1609
AVR® CPU
6.5.6
Accessing 16-Bit Registers
Most of the registers for the ATmega808/809/1608/1609 devices are 8-bit registers, but the devices also feature a
few 16-bit registers. As the AVR data bus has a width of eight bits, accessing the 16-bit requires two read or write
operations. All the 16-bit registers of the ATmega808/809/1608/1609 devices are connected to the 8-bit bus through
a temporary (TEMP) register.
Figure 6-6. 16-Bit Register Write Operation
DATAH
TEMP
DATAL
Write Low Byte
A
V
R
D
A
T
A
B
U
S
DATAH
TEMP
DATAL
A
V
R
D
A
T
A
B
U
S
Write High Byte
For a 16-bit write operation, the low byte register (e.g., DATAL) of the 16-bit register must be written before the high
byte register (e.g., DATAH). Writing the low byte register will result in a write to the temporary (TEMP) register instead
of the low byte register, as shown in the left side of the figure above. When the high byte register of the 16-bit register
is written, TEMP will be copied into the low byte of the 16-bit register in the same clock cycle, as shown on the right
side of the same figure.
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ATmega808/809/1608/1609
AVR® CPU
Figure 6-7. 16-Bit Register Read Operation
DATAH
TEMP
DATAL
A
V
R
DATAH
D
A
T
A
B
U
S
TEMP
DATAL
A
V
R
D
A
T
A
B
U
S
Read High Byte
Read Low Byte
For a 16-bit read operation, the low byte register (e.g., DATAL) of the 16-bit register must be read before the high
byte register (e.g., DATAH). When the low byte register is read, the high byte register of the 16-bit register is copied
into the temporary (TEMP) register in the same clock cycle, as shown on the left side of the figure above. Reading
the high byte register will result in a read from TEMP instead of the high byte register, as shown on the right side of
the same figure.
The described mechanism ensures that the low and high bytes of 16-bit registers are always accessed
simultaneously when reading or writing the registers.
Interrupts can corrupt the timed sequence if an interrupt is triggered during a 16-bit read/write operation, and a 16-bit
register within the same peripheral is accessed in the interrupt service routine. To prevent this, interrupts should
be disabled when writing or reading 16-bit registers. Alternatively, the temporary register can be read before and
restored after the 16-bit access in the interrupt service routine.
6.5.7
Configuration Change Protection (CCP)
System critical I/O register settings are protected from accidental modification. Flash self-programming (via store
to NVM controller) is protected from accidental execution. This is handled globally by the Configuration Change
Protection (CCP) register.
Changes to the protected I/O registers or bits, or execution of protected instructions, are only possible after the
CPU writes a signature to the CCP register. The different signatures are listed in the description of the CCP register
(CPU.CCP).
There are two modes of operation: One for protected I/O registers, and one for protected self-programming.
6.5.7.1
Sequence for Write Operation to Configuration Change Protected I/O Registers
In order to write to registers protected by CCP, these steps are required:
1.
2.
The software writes the signature that enables change of protected I/O registers to the CCP bit field in the
CPU.CCP register.
Within four instructions, the software must write the appropriate data to the protected register.
Most protected registers also contain a Write Enable/Change Enable/Lock bit. This bit must be written to ‘1’ in
the same operation as the data are written.
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ATmega808/809/1608/1609
AVR® CPU
The protected change is immediately disabled if the CPU performs write operations to the I/O register or data
memory, if load or store accesses to Flash, NVMCTRL, or EEPROM are conducted, or if the SLEEP instruction
is executed.
6.5.7.2
Sequence for Execution of Self-Programming
In order to execute self-programming (the execution of writes to the NVM controller’s command register), the
following steps are required:
1.
2.
The software temporarily enables self-programming by writing the SPM signature to the CCP register
(CPU.CCP).
Within four instructions, the software must execute the appropriate instruction. The protected change is
immediately disabled if the CPU performs accesses to the Flash, NVMCTRL, or EEPROM, or if the SLEEP
instruction is executed.
Once the correct signature is written by the CPU, interrupts will be ignored for the duration of the configuration
change enable period. Any interrupt request (including non-maskable interrupts) during the CCP period will set the
corresponding Interrupt flag as normal, and the request is kept pending. After the CCP period is completed, any
pending interrupts are executed according to their level and priority.
6.5.8
On-Chip Debug Capabilities
The AVR CPU includes native On-Chip Debug (OCD) support. It includes some powerful debug capabilities to
enable profiling and detailed information about the CPU state. It is possible to alter the CPU state and resume code
execution. Also, normal debug capabilities like hardware Program Counter breakpoints, breakpoints on change of
flow instructions, breakpoints on interrupts, and software breakpoints (BREAK instruction) are present. Refer to the
Unified Program and Debug Interface section for details about OCD.
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ATmega808/809/1608/1609
AVR® CPU
6.6
Offset
0x00
...
0x03
0x04
0x05
...
0x0C
Register Summary
Name
7
6
5
4
3
2
1
0
V
N
Z
C
Reserved
CCP
7:0
CCP[7:0]
7:0
15:8
7:0
SP[7:0]
SP[15:8]
Reserved
0x0D
SP
0x0F
SREG
6.7
Bit Pos.
I
T
H
S
Register Description
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ATmega808/809/1608/1609
AVR® CPU
6.7.1
Configuration Change Protection
Name:
Offset:
Reset:
Property:
Bit
7
CCP
0x04
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CCP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CCP[7:0] Configuration Change Protection
Writing the correct signature to this bit field allows changing protected I/O registers or executing protected
instructions within the next four CPU instructions executed.
All interrupts are ignored during these cycles. After these cycles are completed, the interrupts will automatically be
handled again by the CPU, and any pending interrupts will be executed according to their level and priority.
When the protected I/O register signature is written, CCP[0] will read as ‘1’ as long as the CCP feature is enabled.
When the protected self-programming signature is written, CCP[1] will read as ‘1’ as long as the CCP feature is
enabled.
CCP[7:2] will always read as ‘0’.
Value
Name
Description
0x9D
SPM
Allow Self-Programming
0xD8
IOREG
Unlock protected I/O registers
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ATmega808/809/1608/1609
AVR® CPU
6.7.2
Stack Pointer
Name:
Offset:
Reset:
Property:
SP
0x0D
Top of stack
-
The CPU.SP register holds the Stack Pointer (SP) that points to the top of the stack. After being reset, the SP points
to the highest internal SRAM address.
Only the number of bits required to address the available data memory, including external memory (up to 64 KB), is
implemented for each device. Unused bits will always read as ‘0’.
The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
To prevent corruption when updating the SP from software, a write to CPU.SPL will automatically disable interrupts
for the next four instructions or until the next I/O memory write, whichever comes first.
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
3
2
1
0
R/W
R/W
R/W
R/W
SP[15:8]
Access
Reset
Bit
R/W
R/W
R/W
R/W
7
6
5
4
SP[7:0]
Access
Reset
R/W
R/W
R/W
R/W
Bits 15:8 – SP[15:8] Stack Pointer High Byte
These bits hold the MSB of the 16-bit register.
Bits 7:0 – SP[7:0] Stack Pointer Low Byte
These bits hold the LSB of the 16-bit register.
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ATmega808/809/1608/1609
AVR® CPU
6.7.3
Status Register
Name:
Offset:
Reset:
Property:
SREG
0x0F
0x00
-
The Status Register contains information about the result of the most recently executed arithmetic or logic
instructions. For details about the bits in this register and how they are influenced by different instructions, see
the Instruction Set Summary section.
Bit
Access
Reset
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
Bit 7 – I Global Interrupt Enable Bit
Writing a ‘1’ to this bit enables interrupts on the device.
Writing a ‘0’ to this bit disables interrupts on the device, independent of the individual interrupt enable settings of the
peripherals.
This bit is not cleared by hardware while entering an Interrupt Service Routine (ISR) or set when the RETI instruction
is executed.
This bit can be set and cleared by software with the SEI and CLI instructions.
Changing the I bit through the I/O register results in a one-cycle Wait state on the access.
Bit 6 – T Transfer Bit
The bit copy instructions, Bit Load (BLD) and Bit Store (BST), use the T bit as source or destination for the operated
bit.
Bit 5 – H Half Carry Flag
This flag is set when there is a half carry in arithmetic operations that support this, and is cleared otherwise. Half
carry is useful in BCD arithmetic.
Bit 4 – S Sign Flag
This flag is always an Exclusive Or (XOR) between the Negative flag (N) and the Two’s Complement Overflow flag
(V).
Bit 3 – V Two’s Complement Overflow Flag
This flag is set when there is an overflow in arithmetic operations that support this, and is cleared otherwise.
Bit 2 – N Negative Flag
This flag is set when there is a negative result in an arithmetic or logic operation, and is cleared otherwise.
Bit 1 – Z Zero Flag
This flag is set when there is a zero result in an arithmetic or logic operation, and is cleared otherwise.
Bit 0 – C Carry Flag
This flag is set when there is a carry in an arithmetic or logic operation, and is cleared otherwise.
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ATmega808/809/1608/1609
Memories
7.
Memories
7.1
Overview
The main memories of the ATmega808/809/1608/1609 are SRAM data memory, EEPROM data memory, and Flash
program memory. Also, the peripheral registers are located in the I/O memory space.
7.2
Memory Map
The figure below shows the memory map for the largest device in the megaAVR 0-series. Refer to the subsequent
subsections for details on memory sizes and start addresses for devices with smaller memory sizes.
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ATmega808/809/1608/1609
Memories
Figure 7-1. Memory Map: Flash 48 KB, Internal SRAM 6 KB, EEPROM 256B
Code space
0x0000
Data space
64 I/O Registers
0x0000 – 0x003F
960 Ext. /IO Registers
0x0040 – 0x0FFF
NVM I/O Registers and
data
0x1000 – 0x13FF
0x1400
EEPROM 256B
0x1500
(Reserved)
0x2800
Flash code
48 KB
Internal SRAM
6 KB
0x3FFF
0x4000
Flash code
48 KB
0xFFFF
7.3
In-System Reprogrammable Flash Program Memory
The ATmega808/809/1608/1609 contains 8 or 16 KB On-Chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized with a 16-bit data
width. For write protection, the Flash program memory space can be divided into three sections: Bootloader section,
application code section, and application data section. Code placed in one section may be restricted from writing to
addresses in other sections. See the NVMCTRL documentation for more details.
The Program Counter can address the whole program memory. The procedure for writing Flash memory is described
in detail in the documentation of the Nonvolatile Memory Controller (NVMCTRL) peripheral.
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ATmega808/809/1608/1609
Memories
The Flash memory is mapped into the data space and is accessible with normal LD/ST instructions. For LD/ST
instructions, the Flash is mapped from address 0x4000. The Flash memory can be read with the LPM instruction. For
the LPM instruction, the Flash start address is 0x0000.
The ATmega808/809/1608/1609 has a CRC module that is a host on the bus.
Table 7-1. Physical Properties of Flash Memory
7.4
Property
ATmega808 ATmega809
ATmega1608 ATmega1609
Size
8 KB
16 KB
Page size
64B
64B
Number of pages
128
256
Start address in Data Space
0x4000
0x4000
Start address in Code Space
0x0000
0x0000
SRAM Data Memory
The primary task of the SRAM memory is to store application data. It is not possible to execute code from SRAM.
Table 7-2. Physical Properties of SRAM
7.5
Property
ATmega808 ATmega809
ATmega1608 ATmega1609
Size
1 KB
2 KB
Start address
0x3C00
0x3800
EEPROM Data Memory
The primary task of the EEPROM memory is to store nonvolatile application data. The EEPROM memory supports
single-byte read and write. The EEPROM is controlled by the Nonvolatile Memory Controller (NVMCTRL).
Table 7-3. Physical Properties of EEPROM
7.6
Property
ATmega808 ATmega809
ATmega1608 ATmega1609
Size
256B
256B
Page size
32B
32B
Number of pages
8
8
Start address
0x1400
0x1400
User Row (USERROW)
In addition to the EEPROM, the ATmega808/809/1608/1609 has one extra page of EEPROM memory that can be
used for firmware settings, the User Row (USERROW). This memory supports single-byte read and write as the
normal EEPROM. The CPU can write and read this memory as normal EEPROM, and the UPDI can write and read it
as a normal EEPROM memory if the part is unlocked. The User Row can also be written by the UPDI when the part
is locked. USERROW is not affected by a chip erase. The USERROW can be used for the final configuration without
having programming or debugging capabilities enabled.
7.7
Signature Row (SIGROW)
The content of the Signature Row fuses (SIGROW) is preprogrammed and cannot be altered. SIGROW holds
information such as device ID, serial number, and factory calibration values.
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ATmega808/809/1608/1609
Memories
All AVR microcontrollers have a three-byte device ID that identifies the device. This device ID can be read in both
serial and parallel mode, also when the device is locked. The three bytes reside in the Signature Row. The signature
bytes are given in the following table.
Table 7-4. Device ID
Device Name
Signature Bytes Address
0x00
0x01
0x02
ATmega1609
0x1E
0x94
0x26
ATmega1608
0x1E
0x94
0x27
ATmega809
0x1E
0x93
0x2A
ATmega808
0x1E
0x93
0x26
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ATmega808/809/1608/1609
Memories
7.7.1
Signature Row Summary
Offset
Name
Bit Pos.
0x00
DEVICEID0
7:0
DEVICEID[7:0]
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
...
0x17
0x18
0x19
0x1A
0x1B
0x1C
...
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
DEVICEID1
DEVICEID2
SERNUM0
SERNUM1
SERNUM2
SERNUM3
SERNUM4
SERNUM5
SERNUM6
SERNUM7
SERNUM8
SERNUM9
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
DEVICEID[7:0]
DEVICEID[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
7.7.2
7
6
5
4
3
2
1
0
Reserved
OSCCAL16M0
OSCCAL16M1
OSCCAL20M0
OSCCAL20M1
7:0
7:0
7:0
7:0
OSCCAL16M[6:0]
OSCCAL16MTCAL[3:0]
OSCCAL20M[6:0]
OSCCAL20MTCAL[3:0]
Reserved
TEMPSENSE0
TEMPSENSE1
OSC16ERR3V
OSC16ERR5V
OSC20ERR3V
OSC20ERR5V
7:0
7:0
7:0
7:0
7:0
7:0
TEMPSENSE[7:0]
TEMPSENSE[7:0]
OSC16ERR3V[7:0]
OSC16ERR5V[7:0]
OSC20ERR3V[7:0]
OSC20ERR5V[7:0]
Signature Row Description
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ATmega808/809/1608/1609
Memories
7.7.2.1
Device ID n
Name:
Offset:
Reset:
Property:
DEVICEIDn
0x00 + n*0x01 [n=0..2]
[Device ID]
-
Each device has a device ID identifying the device and its properties; such as memory sizes, pin count, and die
revision. This can be used to identify a device and hence, the available features by software. The Device ID consists
of three bytes: SIGROW.DEVICEID[2:0].
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
DEVICEID[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – DEVICEID[7:0] Byte n of the Device ID
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ATmega808/809/1608/1609
Memories
7.7.2.2
Serial Number Byte n
Name:
Offset:
Reset:
Property:
SERNUMn
0x03 + n*0x01 [n=0..9]
[device serial number]
-
Each device has an individual serial number, representing a unique ID. This can be used to identify a specific device
in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].
Bit
7
6
5
4
3
2
1
0
R
x
R
x
R
x
R
x
SERNUM[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 7:0 – SERNUM[7:0] Serial Number Byte n
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ATmega808/809/1608/1609
Memories
7.7.2.3
OSC16 Calibration byte
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
OSCCAL16M0
0x18
[Factory oscillator calibration value]
-
6
5
4
R
x
R
x
R
x
3
OSCCAL16M[6:0]
R
x
2
1
0
R
x
R
x
R
x
Bits 6:0 – OSCCAL16M[6:0] OSC16 Calibration
These bits contains factory calibration values for the internal 16 MHz oscillator. If the OSCCFG fuse is configured to
run the device at 16 MHz, this byte is automatically copied to the OSC20MCALIBA register during Reset to calibrate
the internal 16 MHz RC Oscillator.
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Memories
7.7.2.4
OSC16 Temperature Calibration byte
Name:
Offset:
Reset:
Property:
Bit
7
OSCCAL16M1
0x19
[Factory oscillator temperature calibration value]
-
6
Access
Reset
5
4
3
R
x
2
1
OSCCAL16MTCAL[3:0]
R
R
x
x
0
R
x
Bits 3:0 – OSCCAL16MTCAL[3:0] OSC16 Temperature Calibration
These bits contain factory temperature calibration values for the internal 16 MHz oscillator. If the OSCCFG fuse is
configured to run the device at 16 MHz, this byte is automatically written into the OSC20MCALIBB register during
Reset to ensure correct frequency of the calibrated RC Oscillator.
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ATmega808/809/1608/1609
Memories
7.7.2.5
OSC20 Calibration byte
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
OSCCAL20M0
0x1A
[Factory oscillator calibration value]
-
6
5
4
R
x
R
x
R
x
3
OSCCAL20M[6:0]
R
x
2
1
0
R
x
R
x
R
x
Bits 6:0 – OSCCAL20M[6:0] OSC20 Calibration
These bits contain factory calibration values for the internal 20 MHz oscillator. If the OSCCFG fuse is configured to
run the device at 20 MHz, this byte is automatically written into the OSC20MCALIBA register during Reset to ensure
correct frequency of the calibrated RC Oscillator.
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ATmega808/809/1608/1609
Memories
7.7.2.6
OSC20 Temperature Calibration byte
Name:
Offset:
Reset:
Property:
Bit
7
OSCCAL20M1
0x1B
[Factory oscillator temperature calibration value]
-
6
Access
Reset
5
4
3
R
x
2
1
OSCCAL20MTCAL[3:0]
R
R
x
x
0
R
x
Bits 3:0 – OSCCAL20MTCAL[3:0] OSC20 Temperature Calibration
These bits contain factory temperature calibration values for the internal 20 MHz oscillator. If the OSCCFG fuse is
configured to run the device at 20 MHz, this byte is automatically written into the OSC20MCALIBB register during
Reset to ensure correct frequency of the calibrated RC Oscillator.
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ATmega808/809/1608/1609
Memories
7.7.2.7
Temperature Sensor Calibration n
Name:
Offset:
Reset:
Property:
TEMPSENSEn
0x20 + n*0x01 [n=0..1]
[Temperature sensor calibration value]
-
These bytes contain correction factors for temperature measurements by the ADC. SIGROW.TEMPSENSE0 is a
correction factor for the gain/slope (unsigned), and SIGROW.TEMPSENSE1 is a correction factor for the offset
(signed).
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
TEMPSENSE[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – TEMPSENSE[7:0] Temperature Sensor Calibration Byte n
Refer to the ADC section for a description of how to use this register.
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ATmega808/809/1608/1609
Memories
7.7.2.8
OSC16 Error at 3V
Name:
Offset:
Reset:
Property:
OSC16ERR3V
0x22
[Oscillator frequency error value]
-
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
OSC16ERR3V[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – OSC16ERR3V[7:0] OSC16 Error at 3V
This byte contains the signed oscillator frequency error value when running at internal 16 MHz at 3V, as measured
during production.
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ATmega808/809/1608/1609
Memories
7.7.2.9
OSC16 Error at 5V
Name:
Offset:
Reset:
Property:
OSC16ERR5V
0x23
[Oscillator frequency error value]
-
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
OSC16ERR5V[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – OSC16ERR5V[7:0] OSC16 Error at 5V
This byte contains the signed oscillator frequency error value when running at internal 16 MHz at 5V, as measured
during production.
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ATmega808/809/1608/1609
Memories
7.7.2.10 OSC20 Error at 3V
Name:
Offset:
Reset:
Property:
OSC20ERR3V
0x24
[Oscillator frequency error value]
-
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
OSC20ERR3V[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – OSC20ERR3V[7:0] OSC20 Error at 3V
This byte contains the signed oscillator frequency error value when running at internal 20 MHz at 3V, as measured
during production.
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ATmega808/809/1608/1609
Memories
7.7.2.11 OSC20 Error at 5V
Name:
Offset:
Reset:
Property:
OSC20ERR5V
0x25
[Oscillator frequency error value]
-
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
OSC20ERR5V[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – OSC20ERR5V[7:0] OSC20 Error at 5V
This byte contains the signed oscillator frequency error value when running at internal 20 MHz at 5V, as measured
during production.
7.8
Fuses (FUSE)
Fuses hold the device configuration and are a part of the nonvolatile memory. The fuses are available from device
power-up. The fuses can be read by the CPU or the UPDI but can only be programmed or cleared by the UPDI.
The configuration values stored in the fuses are copied to their respective target registers at the end of the start-up
sequence.
The fuses are preprogrammed but can be altered by the user. Altered fuse values will be effective only after a Reset.
Note: All reserved bits must be written to ‘1’ when writing the fuses.
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ATmega808/809/1608/1609
Memories
7.8.1
Fuse Summary - FUSE
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
...
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
WDTCFG
BODCFG
OSCCFG
7:0
7:0
7:0
7.8.2
7
6
5
WINDOW[3:0]
LVL[2:0]
4
3
2
1
0
PERIOD[3:0]
SAMPFREQ
ACTIVE[1:0]
OSCLOCK
SLEEP[1:0]
FREQSEL[1:0]
Reserved
SYSCFG0
SYSCFG1
APPEND
BOOTEND
Reserved
LOCKBIT
7:0
7:0
7:0
7:0
7:0
CRCSRC[1:0]
RSTPINCFG
EESAVE
SUT[2:0]
APPEND[7:0]
BOOTEND[7:0]
LOCKBIT[7:0]
Fuse Description
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ATmega808/809/1608/1609
Memories
7.8.2.1
Watchdog Configuration
Name:
Offset:
Default:
Property:
WDTCFG
0x00
0x00
-
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
7
6
5
4
3
2
WINDOW[3:0]
Access
Default
R
0
R
0
1
0
R
0
R
0
PERIOD[3:0]
R
0
R
0
R
0
R
0
Bits 7:4 – WINDOW[3:0] Watchdog Window Time-out Period
This value is loaded into the WINDOW bit field of the Watchdog Control A (WDT.CTRLA) register during Reset.
Bits 3:0 – PERIOD[3:0] Watchdog Time-out Period
This value is loaded into the PERIOD bit field of the Watchdog Control A (WDT.CTRLA) register during Reset.
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ATmega808/809/1608/1609
Memories
7.8.2.2
BOD Configuration
Name:
Offset:
Default:
Property:
BODCFG
0x01
0x00
-
The bit values of this fuse register are written to the corresponding BOD configuration registers at the start-up.
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
Access
Default
7
R
0
6
LVL[2:0]
R
0
5
R
0
4
SAMPFREQ
R
0
3
2
1
ACTIVE[1:0]
R
0
0
SLEEP[1:0]
R
0
R
0
R
0
Bits 7:5 – LVL[2:0] BOD Level
This value is loaded into the LVL bit field of the BOD Control B (BOD.CTRLB) register during Reset.
Value
Name
Description
0x0
BODLEVEL0
1.8V
0x2
BODLEVEL2
2.6V
0x7
BODLEVEL7
4.3V
Other
Reserved
Notes:
• Refer to BOD and POR Characteristics in the Electrical Characteristics section for further details
• Values in the description are typical values
Bit 4 – SAMPFREQ BOD Sample Frequency
This value is loaded into the SAMPFREQ bit of the BOD Control A (BOD.CTRLA) register during Reset.
Value
Description
0x0
Sample frequency is 1 kHz
0x1
Sample frequency is 125 Hz
Bits 3:2 – ACTIVE[1:0] BOD Operation Mode in Active and Idle
This value is loaded into the ACTIVE bit field of the BOD Control A (BOD.CTRLA) register during Reset.
Value
Description
0x0
Disabled
0x1
Enabled
0x2
Sampled
0x3
Enabled with wake-up halted until BOD is ready
Bits 1:0 – SLEEP[1:0] BOD Operation Mode in Sleep
This value is loaded into the SLEEP bit field of the BOD Control A (BOD.CTRLA) register during Reset.
Value
Description
0x0
Disabled
0x1
Enabled
0x2
Sampled
0x3
Reserved
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ATmega808/809/1608/1609
Memories
7.8.2.3
Oscillator Configuration
Name:
Offset:
Default:
Property:
OSCCFG
0x02
0x02
-
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
Access
Default
7
OSCLOCK
R
0
6
5
4
3
2
1
0
FREQSEL[1:0]
R
R
1
0
Bit 7 – OSCLOCK Oscillator Lock
This fuse bit is loaded to LOCK in CLKCTRL.OSC20MCALIBB during Reset.
Value
Description
0x0
Calibration registers of the 20 MHz oscillator can be modified at run-time
0x1
Calibration registers of the 20 MHz oscillator are locked at run-time
Bits 1:0 – FREQSEL[1:0] Frequency Select
These bits select the operation frequency of the internal RC Oscillator (OSC20M) and determine the respective
factory calibration values to be written to CAL20M in CLKCTRL.OSC20MCALIBA and TEMPCAL20M in
CLKCTRL.OSC20MCALIBB.
Value
Description
0x0
Reserved
0x1
Run at 16 MHz
0x2
Run at 20 MHz
0x3
Reserved
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ATmega808/809/1608/1609
Memories
7.8.2.4
System Configuration 0
Name:
Offset:
Default:
Property:
SYSCFG0
0x05
0xE4
-
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
7
6
5
4
CRCSRC[1:0]
Access
Default
R
1
R
1
3
RSTPINCFG
R
0
2
1
0
EESAVE
R
0
Bits 7:6 – CRCSRC[1:0] CRC Source
This bit field control which section of the Flash will be checked by the CRCSCAN peripheral during Reset
Initialization.
Value
Name
Description
0x0
FLASH
CRC of full Flash (boot, application code, and application data)
0x1
BOOT
CRC of boot section
0x2
BOOTAPP
CRC of application code and boot sections
0x3
NOCRC
No CRC
Bit 3 – RSTPINCFG Reset Pin Configuration
This bit selects the pin configuration for the Reset pin.
Value
Description
0x0
GPIO
0x1
RESET
Bit 0 – EESAVE EEPROM Save During Chip Erase
If the device is locked, the EEPROM is always erased by a chip erase, regardless of this bit.
Value
Description
0x0
EEPROM erased by chip erase
0x1
EEPROM not erased by chip erase
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ATmega808/809/1608/1609
Memories
7.8.2.5
System Configuration 1
Name:
Offset:
Default:
Property:
SYSCFG1
0x06
0x07
-
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
7
6
5
4
3
Access
Default
2
R
1
1
SUT[2:0]
R
1
0
R
1
Bits 2:0 – SUT[2:0] Start-Up Time Setting
These bits select the start-up time between power-on and code execution.
Value
Description
0x0
0 ms
0x1
1 ms
0x2
2 ms
0x3
4 ms
0x4
8 ms
0x5
16 ms
0x6
32 ms
0x7
64 ms
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ATmega808/809/1608/1609
Memories
7.8.2.6
Application Code End
Name:
Offset:
Default:
Property:
APPEND
0x07
0x00
-
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
APPEND[7:0]
Access
Default
R
0
R
0
R
0
R
0
Bits 7:0 – APPEND[7:0] Application Code Section End
These bits set the end of the application code section in blocks of 256 bytes. The end of the application code
section should be set as the BOOT size plus application code size. The remaining Flash will be application data.
A value of 0x00 defines the Flash from BOOTEND*256 to the end of Flash as the application code section. When
FUSE.BOOTEND is 0x00, the entire Flash is the BOOT section.
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ATmega808/809/1608/1609
Memories
7.8.2.7
Boot End
Name:
Offset:
Default:
Property:
BOOTEND
0x08
0x00
-
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
7
6
5
Access
Default
R
0
R
0
R
0
4
3
BOOTEND[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 7:0 – BOOTEND[7:0] Boot Section End
These bits set the end of the boot section in blocks of 256 bytes. A value of 0x00 defines the whole Flash as the
BOOT section.
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ATmega808/809/1608/1609
Memories
7.8.2.8
Lockbits
Name:
Offset:
Default:
Property:
LOCKBIT
0x0A
0xC5
-
The default value given in this fuse description is the factory-programmed value and should not be mistaken for the
Reset value.
Bit
7
6
5
4
3
2
1
0
R
0
R
1
R
0
R
1
LOCKBIT[7:0]
Access
Default
R
1
R
1
R
0
R
0
Bits 7:0 – LOCKBIT[7:0] Lockbits
The UPDI cannot access the system bus when the part is locked. The UPDI can then only read the internal Control
and Status (CS) space of the UPDI and the Asynchronous System Interface (ASI). Refer to the UPDI section for
additional details.
Value
Description
0xC5
Valid key - the device is open
other
Invalid key - the device is locked
7.9
Memory Section Access from CPU and UPDI on Locked Device
The device can be locked so that the memories cannot be read using the UPDI. The locking protects both the Flash
(all BOOT, APPCODE, and APPDATA sections), SRAM, and the EEPROM including the FUSE data. This prevents
successful reading of application data or code using the debugger interface. Regular memory access from within the
application still is enabled.
The device is locked by writing any invalid key to the LOCKBIT bit field in FUSE.LOCKBIT.
Table 7-5. Memory Access in Unlocked Mode (FUSE.LOCKBIT Valid)(1)
Memory Section
CPU Access
UPDI Access
Read
Write
Read
Write
SRAM
Yes
Yes
Yes
Yes
Registers
Yes
Yes
Yes
Yes
Flash
Yes
Yes
Yes
Yes
EEPROM
Yes
Yes
Yes
Yes
USERROW
Yes
Yes
Yes
Yes
SIGROW
Yes
No
Yes
No
Other Fuses
Yes
No
Yes
Yes
Table 7-6. Memory Access in Locked Mode (FUSE.LOCKBIT Invalid)(1)
Memory Section
CPU Access
UPDI Access
Read
Write
Read
Write
SRAM
Yes
Yes
No
No
Registers
Yes
Yes
No
No
Flash
Yes
Yes
No
No
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ATmega808/809/1608/1609
Memories
...........continued
Memory Section
CPU Access
UPDI Access
Read
Write
Read
Write
EEPROM
Yes
Yes
No
No
USERROW
Yes
Yes
No
Yes(2)
SIGROW
Yes
No
No
No
Other Fuses
Yes
No
No
No
Notes:
1. Read operations marked No in the tables may appear to be successful, but the data is corrupt. Hence, any
attempt of code validation through the UPDI will fail on these memory sections.
2. In Locked mode, the USERROW can be written blindly using the Fuse Write command, but the current
USERROW values cannot be read out.
Important: The only way to unlock a device is a CHIPERASE, which will erase all device memories to
factory default so that no application data is retained.
7.10
I/O Memory
All ATmega808/809/1608/1609 I/Os and peripherals are located in the I/O space. The I/O address range from 0x00
to 0x3F can be accessed in a single cycle using IN and OUT instructions. The extended I/O space from 0x0040
- 0x0FFF can be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
Instruction Set section for more details.
For compatibility with future devices, reserved bits should be written to ‘0’ if accessed. Reserved I/O memory
addresses should never be written.
Some of the interrupt flags are cleared by writing a ‘1’ to them. On ATmega808/809/1608/1609 devices, the CBI
and SBI instructions will only operate on the specified bit, and can, therefore, be used on registers containing such
interrupt flags. The CBI and SBI instructions work with registers 0x00 - 0x1F only.
General Purpose I/O Registers
The ATmega808/809/1608/1609 devices provide four General Purpose I/O Registers. These registers can be used
for storing any information, and they are particularly useful for storing global variables and interrupt flags. General
Purpose I/O Registers, which reside in the address range 0x1C - 0x1F, are directly bit-accessible using the SBI, CBI,
SBIS, and SBIC instructions.
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ATmega808/809/1608/1609
Memories
7.10.1
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
GPIOR0
GPIOR1
GPIOR2
GPIOR3
7:0
7:0
7:0
7:0
7.10.2
7
6
5
4
3
2
1
0
GPIOR[7:0]
GPIOR[7:0]
GPIOR[7:0]
GPIOR[7:0]
Register Description
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ATmega808/809/1608/1609
Memories
7.10.2.1 General Purpose I/O Register n
Name:
Offset:
Reset:
Property:
GPIOR
0x00 + n*0x01 [n=0..3]
0x00
-
These are general purpose registers that can be used to store data, such as global variables and flags, in the bit
accessible I/O memory space.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
GPIOR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – GPIOR[7:0] GPIO Register Byte
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ATmega808/809/1608/1609
Peripherals and Architecture
8.
Peripherals and Architecture
8.1
Peripheral Module Address Map
The address map shows the base address for each peripheral. For a complete register description and summary for
each peripheral module, refer to the respective module section.
Table 8-1. Peripheral Module Address Map
Base
Address
Name
Description
28-Pin
32-Pin
48-Pin
0x0000
VPORTA
Virtual Port A
X
X
X
0x0004
VPORTB
Virtual Port B
0x0008
VPORTC
Virtual Port C
X
X
X
0x000C
VPORTD
Virtual Port D
X
X
X
0x0010
VPORTE
Virtual Port E
0x0014
VPORTF
Virtual Port F
X
X
X
0x001C
GPIO
General Purpose I/O registers
X
X
X
0x0030
CPU
CPU
X
X
X
0x0040
RSTCTRL
Reset Controller
X
X
X
0x0050
SLPCTRL
Sleep Controller
X
X
X
0x0060
CLKCTRL
Clock Controller
X
X
X
0x0080
BOD
Brown-out Detector
X
X
X
0x00A0
VREF
Voltage Reference
X
X
X
0x0100
WDT
Watchdog Timer
X
X
X
0x0110
CPUINT
Interrupt Controller
X
X
X
0x0120
CRCSCAN
Cyclic Redundancy Check Memory Scan
X
X
X
0x0140
RTC
Real-Time Counter
X
X
X
0x0180
EVSYS
Event System
X
X
X
0x01C0
CCL
Configurable Custom Logic
X
X
X
0x0400
PORTA
Port A Configuration
X
X
X
0x0420
PORTB
Port B Configuration
0x0440
PORTC
Port C Configuration
X
X
X
0x0460
PORTD
Port D Configuration
X
X
X
0x0480
PORTE
Port E Configuration
0x04A0
PORTF
Port F Configuration
X
X
X
0x05E0
PORTMUX
Port Multiplexer
X
X
X
0x0600
ADC0
Analog-to-Digital Converter
X
X
X
0x0680
AC0
Analog Comparator 0
X
X
X
© 2021 Microchip Technology Inc.
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X
X
X
Complete Datasheet
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ATmega808/809/1608/1609
Peripherals and Architecture
...........continued
Base
Address
Name
Description
28-Pin
32-Pin
48-Pin
0x0800
USART0
Universal Synchronous Asynchronous Receiver Transmitter 0
X
X
X
0x0820
USART1
Universal Synchronous Asynchronous Receiver Transmitter 1
X
X
X
0x0840
USART2
Universal Synchronous Asynchronous Receiver Transmitter 2
X
X
X
0x0860
USART3
Universal Synchronous Asynchronous Receiver Transmitter 3
0x08A0
TWI0
Two-Wire Interface
X
X
X
0x08C0
SPI0
Serial Peripheral Interface
X
X
X
0x0A00
TCA0
Timer/Counter Type A instance 0
X
X
X
0x0A80
TCB0
Timer/Counter Type B instance 0
X
X
X
0x0A90
TCB1
Timer/Counter Type B instance 1
X
X
X
0x0AA0
TCB2
Timer/Counter Type B instance 2
X
X
X
0x0AB0
TCB3
Timer/Counter Type B instance 3
0x0F00
SYSCFG
System Configuration
X
X
X
0x1000
NVMCTRL
Nonvolatile Memory Controller
X
X
X
0x1100
SIGROW
Signature Row
X
X
X
0x1280
FUSE
Device-specific fuses
X
X
X
0x1300
USERROW
User Row
X
X
X
8.2
X
X
Interrupt Vector Mapping
Each of the interrupt vectors is connected to one peripheral instance, as shown in the table below. A peripheral
can have one or more interrupt sources. See the ‘Interrupts’ section in the ‘Functional Description’ of the respective
peripheral for more details on the available interrupt sources.
When the interrupt condition occurs, an Interrupt Flag is set in the Interrupt Flags register of the peripheral
(peripheral.INTFLAGS).
An interrupt is enabled or disabled by writing to the corresponding Interrupt Enable bit in the peripheral's Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt is enabled, and the Interrupt Flag is set. The
interrupt request remains active until the Interrupt Flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear Interrupt Flags.
Note: Interrupts must be enabled globally for interrupt requests to be generated.
Table 8-2. Interrupt Vector Mapping
Program Peripheral
Vector
Address Source
Number
(word) (name)
28- 32- 48Pin Pin Pin
Description
0
0x00
RESET
X
X
X
1
0x02
CRCSCAN_NMI Non-Maskable Interrupt available for CRCSCAN
X
X
X
2
0x04
BOD_VLM
Voltage Level Monitor interrupt
X
X
X
3
0x06
RTC_CNT
Real Time Counter - Overflow or compare match interrupt
X
X
X
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ATmega808/809/1608/1609
Peripherals and Architecture
...........continued
Program Peripheral
Vector
Address Source
Number
(word) (name)
28- 32- 48Pin Pin Pin
Description
4
0x08
RTC_PIT
Real Time Counter - Periodic Interrupt Timer interrupt
X
X
X
5
0x0A
CCL_CCL
Configurable Custom Logic interrupt
X
X
X
6
0x0C
PORTA_PORT
Port A - External interrupt
X
X
X
7
0x0E
TCA0_OVF
TCA0_LUNF
Normal: Timer/Counter Type A Overflow interrupt
Split: Timer/Counter Type A Low Underflow interrupt
X
X
X
8
0x10
TCA0_HUNF
Split: Timer/Counter Type A High Underflow interrupt
X
X
X
9
0x12
TCA0_CMP0
TCA0_LCMP0
Normal: Timer/Counter Type A Compare Channel 0 interrupt
Split: Timer/Counter Type A Low Compare Channel 0 interrupt
X
X
X
10
0x14
TCA0_CMP1
TCA0_LCMP1
Normal: Timer/Counter Type A Compare Channel 1 interrupt
Split: Timer/Counter Type A Low Compare Channel 1 interrupt
X
X
X
11
0x16
TCA0_CMP2
TCA0_LCMP2
Normal: Timer/Counter Type A Compare Channel 2 interrupt
Split: Timer/Counter Type A Low Compare Channel 2 interrupt
X
X
X
12
0x18
TCB0_INT
Timer/Counter Type B Capture interrupt
X
X
X
13
0x1A
TCB1_INT
Timer/Counter Type B Capture interrupt
X
X
X
14
0x1C
TWI0_TWIS
Two Wire Interface - Client interrupt
X
X
X
15
0x1E
TWI0_TWIM
Two Wire Interface - Host interrupt
X
X
X
16
0x20
SPI0_INT
Serial Peripheral Interface interrupt
X
X
X
17
0x22
USART0_RCX
Universal Synchronous Asynchronous Receiver Transmitter - Receive
Complete interrupt
X
X
X
18
0x24
USART0_DRE
Universal Synchronous Asynchronous Receiver Transmitter - Data Register
Empty interrupt
X
X
X
19
0x26
USART0_TCX
Universal Synchronous Asynchronous Receiver Transmitter - Transmit
Complete interrupt
X
X
X
20
0x28
PORTD_PORT
Port D - External interrupt
X
X
X
21
0x2A
AC0_AC
Analog Comparator - Compare interrupt
X
X
X
22
0x2C
ADC0_RESRDY Analog-to-Digital Converter - Result Ready interrupt
X
X
X
23
0x2E
ADC0_WCOMP Analog-to-Digital Converter - Window Compare interrupt
X
X
X
24
0x30
PORTC_PORT
Port C - External interrupt
X
X
X
25
0x32
TCB2_INT
Timer/Counter Type B Capture interrupt
X
X
X
26
0x34
USART1_RCX
Universal Synchronous Asynchronous Receiver Transmitter - Receive
Complete interrupt
X
X
X
27
0x36
USART1_DRE
Universal Synchronous Asynchronous Receiver Transmitter - Data Register
Empty interrupt
X
X
X
28
0x38
USART1_TCX
Universal Synchronous Asynchronous Receiver Transmitter - Transmit
Complete interrupt
X
X
X
29
0x3A
PORTF_PORT
Port F - External interrupt
X
X
X
30
0x3C
NVMCTRL_EE
Non-Volatile Memory Controller - Ready interrupt
X
X
X
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Peripherals and Architecture
...........continued
Program Peripheral
Vector
Address Source
Number
(word) (name)
28- 32- 48Pin Pin Pin
Description
31
0x3E
USART2_RCX
Universal Synchronous Asynchronous Receiver Transmitter - Receive
Complete interrupt
X
X
X
32
0x40
USART2_DRE
Universal Synchronous Asynchronous Receiver Transmitter - Data Register
Empty interrupt
X
X
X
33
0x42
USART2_TCX
Universal Synchronous Asynchronous Receiver Transmitter - Transmit
Complete interrupt
X
X
X
34
0x44
PORTB
Port B - External interrupt
X
35
0x46
PORTE
Port E - External interrupt
X
36
0x48
TCB3_INT
Timer/Counter Type B Capture interrupt
X
37
0x4A
USART3_RCX
Universal Synchronous Asynchronous Receiver Transmitter - Receive
Complete interrupt
X
38
0x4C
USART3_DRE
Universal Synchronous Asynchronous Receiver Transmitter - Data Register
Empty interrupt
X
39
0x4E
USART3_TCX
8.3
Universal Synchronous Asynchronous Receiver Transmitter - Transmit
Complete interrupt
SYSCFG - System Configuration
The system configuration contains the revision ID of the part. The revision ID is readable from the CPU, making it
useful for implementing application changes between part revisions.
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X
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Peripherals and Architecture
8.3.1
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
Reserved
REVID
7:0
8.3.2
7
6
5
4
3
2
1
0
REVID[7:0]
Register Description
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Peripherals and Architecture
8.3.2.1
Device Revision ID Register
Name:
Offset:
Reset:
Property:
REVID
0x01
[revision ID]
-
This register is read-only and displays the device revision ID.
Bit
7
6
5
4
3
2
1
0
R
R
R
R
REVID[7:0]
Access
Reset
R
R
R
R
Bits 7:0 – REVID[7:0] Revision ID
These bits contain the device revision. 0x00 = A, 0x01 = B, and so on.
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NVMCTRL - Nonvolatile Memory Controller
9.
NVMCTRL - Nonvolatile Memory Controller
9.1
Features
•
•
•
•
•
•
9.2
Unified Memory
In-System Programmable
Self-Programming and Boot Loader Support
Configurable Sections for Write Protection:
– Boot section for boot loader code or application code
– Application code section for application code
– Application data section for application code or data storage
Signature Row for Factory-Programmed Data:
– ID for each device type
– Serial number for each device
– Calibration bytes for factory-calibrated peripherals
User Row for Application Data:
– Can be read and written from software
– Can be written from UPDI on a locked device
– Content is kept after chip erase
Overview
The NVM Controller (NVMCTRL) is the interface between the CPU and Nonvolatile Memories (Flash, EEPROM,
Signature Row, User Row, and fuses). These are reprogrammable memory blocks that retain their values when they
are not powered. The Flash is mainly used for program storage and can also be used for data storage, while the
EEPROM, Signature Row, User Row, and fuses are used for data storage.
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NVMCTRL - Nonvolatile Memory Controller
9.2.1
Block Diagram
Figure 9-1. NVMCTRL Block Diagram
Nonvolatile
Memory Block
Program Memory Bus
`
Flash
EEPROM
Data Memory Bus
Signature Row
User Row
Fuses
Register access
NVMCTRL
9.3
Functional Description
9.3.1
Memory Organization
9.3.1.1
Flash
The Flash is divided into a set of pages. A page is the basic unit addressed when programming the Flash. It is only
possible to write or erase a whole page at a time. One page consists of several words.
The Flash can be divided into three sections in blocks of 256 bytes for different security. The three different sections
are BOOT, Application Code (APPCODE), and Application Data (APPDATA).
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NVMCTRL - Nonvolatile Memory Controller
Figure 9-2. Flash Sections
FLASHSTART : 0x4000
BOOT
BOOTEND>0: 0x4000+BOOTEND*256
APPLICATION
CODE
APPEND>0: 0x4000+APPEND*256
APPLICATION
DATA
Section Sizes
The sizes of these sections are set by the Boot Section End (FUSE.BOOTEND) fuse and the Application Code
Section End (FUSE.APPEND) fuse.
The fuses select the section sizes in blocks of 256 bytes. The BOOT section stretches from the start of the Flash until
BOOTEND. The APPCODE section runs from BOOTEND until APPEND, and the remaining area is the APPDATA
section.
Table 9-1. Setting Up Flash Sections
BOOTEND
APPEND
BOOT Section
0
—
0 to FLASHEND
> 0
0
0 to 256*BOOTEND
> 0
≤ BOOTEND 0 to 256*BOOTEND
> 0
> BOOTEND 0 to 256*BOOTEND
APPCODE Section
APPDATA Section
—
—
256*BOOTEND to
FLASHEND
—
256*BOOTEND to
256*APPEND
—
256*BOOTEND to
FLASHEND
256*APPEND to
FLASHEND
If BOOTEND is written to ‘0’, the entire Flash is regarded as the BOOT section. If APPEND is written to ‘0’ and
BOOTEND > 0, the APPCODE section runs from BOOTEND to the end of Flash (no APPDATA section). When
APPEND ≤ BOOTEND, the APPCODE section is removed, and the APPDATA runs from BOOTEND to the end of
Flash. When APPEND > BOOTEND, the APPCODE section spreads from BOOTEND until APPEND. The remaining
area is the APPDATA section.
If there is no boot loader software, it is recommended to use the BOOT section for Application Code.
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NVMCTRL - Nonvolatile Memory Controller
Notes:
1. After Reset, the default vector table location is at the start of the APPCODE section. The peripheral interrupts
can be used in the code running in the BOOT section by relocating the interrupt vector table at the beginning
of this section. That is done by setting the IVSEL bit in the CPUINT.CTRLA register. Refer to the CPUINT
section for details.
2. If BOOTEND/APPEND, as resulted from BOOTEND and APPEND fuse setting, exceed the device
FLASHEND, the corresponding fuse setting is ignored, and the default value is used. Refer to “Fuse” in
the Memories section for default values.
Example 9-1. Size of Flash Sections
If FUSE.BOOTEND is written to 0x04 and FUSE.APPEND is written to 0x08, the first 4*256 bytes
will be BOOT, the next 4*256 bytes will be APPCODE, and the remaining Flash will be APPDATA.
Inter-Section Write Protection
Between the three Flash sections, directional write protection is implemented:
• The code in the BOOT section can write to APPCODE and APPDATA
• The code in APPCODE can write to APPDATA
• The code in APPDATA cannot write to Flash or EEPROM
Boot Section Lock and Application Code Section Write Protection
Additional to the inter-section write protection, the NVMCTRL provides a security mechanism to avoid unwanted
access to the Flash memory sections. Even if the CPU can never write to the BOOT section, a Boot Section Lock
(BOOTLOCK) bit in the Control B (NVMCTRL.CTRLB) register is provided to prevent the read and execution of code
from the BOOT section. This bit can be set only from the code executed in the BOOT section and has effect only
when leaving the BOOT section.
The Application Code Section Write Protection (APCWP) bit in the Control B (NVMCTRL.CTRLB) register can be set
to prevent further updates of the APPCODE section.
9.3.1.2
EEPROM
The EEPROM is divided into a set of pages where one page consists of multiple bytes. The EEPROM has byte
granularity on the erase/write. Within one page, only the bytes marked to be updated will be erased/written. The byte
is marked by writing a new value to the page buffer for that address location.
9.3.1.3
User Row
The User Row is one extra page of EEPROM. This page can be used to store various data, such as calibration/
configuration data and serial numbers. This page is not erased by a chip erase. The User Row is written as normal
EEPROM, but also, it can be written through UPDI on a locked device.
9.3.2
Memory Access
9.3.2.1
Read
Reading of the Flash and EEPROM is done by using load instructions with an address according to the memory map.
Reading any of the arrays while a write or erase is in progress will result in a bus wait, and the instruction will be
suspended until the ongoing operation is complete.
9.3.2.2
Page Buffer Load
The page buffer is loaded by writing directly to the memories as defined in the memory map. The Flash, EEPROM,
and User Row share the same page buffer, so only one section can be programmed at a time. The Least Significant
bits (LSb) of the address are used to select where in the page buffer data are written. The resulting data will be a
binary AND operation between the new and the previous content of the page buffer. The page buffer will automatically
be erased (all bits set) after:
• A device Reset
• Any page write or erase operation
• A Clear Page Buffer command
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NVMCTRL - Nonvolatile Memory Controller
•
9.3.2.3
A device wake-up from any sleep mode
Programming
For page programming, filling the page buffer and writing the page buffer into Flash, User Row, and EEPROM are
two separate operations.
Before programming a Flash page with the data in the page buffer, the Flash page must be erased. The page buffer
is also erased when the device enters a sleep mode. Programming an unerased Flash page will corrupt its content.
The Flash can either be written with the erase and write separately, or one command handling both:
Alternative 1:
1. Fill the page buffer.
2. Write the page buffer to Flash with the Erase and Write Page (ERWP) command.
Alternative 2:
1. Write to a location on the page to set up the address.
2. Perform an Erase Page (ER) command.
3. Fill the page buffer.
4. Perform a Write Page (WP) command.
The NVM command set supports both a single erase and write operation, and split Erase Page (ER) and Write
Page (WP) commands. This split commands enable shorter programming time for each command, and the erase
operations can be done during non-time-critical programming execution.
The EEPROM programming is similar, but only the bytes updated in the page buffer will be written or erased in the
EEPROM.
9.3.2.4
Commands
Reading the Flash/EEPROM and writing the page buffer is handled with normal load/store instructions. Other
operations, such as writing and erasing the memory arrays, are handled by commands in the NVM.
To execute a command in the NVM:
1. Confirm that any previous operation is completed by reading the Busy (EEBUSY and FBUSY) Flags in the
NVMCTRL.STATUS register.
2. Write the appropriate key to the Configuration Change Protection (CPU.CCP) register to unlock the NVM
Control A (NVMCTRL.CTRLA) register.
3. Write the desired command value to the CMD bit field in the Control A (NVMCTRL.CTRLA) register within the
next four instructions.
9.3.2.4.1 Write Page Command
The Write Page (WP) command of the Flash controller writes the content of the page buffer to the Flash or EEPROM.
If the write is to the Flash, the CPU will stop executing code as long as the Flash is busy with the write operation. If
the write is to the EEPROM, the CPU can continue to execute code while the operation is ongoing.
The page buffer will automatically be cleared after the operation is finished.
9.3.2.4.2 Erase Page Command
The Erase Page (ER) command erases the current page. There must be one byte written in the page buffer for the
Erase Page (ER) command to take effect.
For erasing the Flash, first, write to one address on the desired page, then execute the command. The whole page in
the Flash will then be erased. The CPU will be halted while the erase is ongoing.
For the EEPROM, only the bytes written in the page buffer will be erased when the command is executed. To erase a
specific byte, write to its corresponding address before executing the command. To erase a whole page, all the bytes
in the page buffer have to be updated before executing the command. The CPU can continue running code while the
operation is ongoing.
The page buffer will automatically be cleared after the operation is finished.
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NVMCTRL - Nonvolatile Memory Controller
9.3.2.4.3 Erase/Write Page Command
The Erase and Write Page (ERWP) command is a combination of the Erase Page and Write Page commands, but
without clearing the page buffer after the Erase Page command: The erase/write operation first erases the selected
page, then it writes the content of the page buffer to the same page.
When executed on the Flash, the CPU will be halted when the operations are ongoing. When executed on EEPROM,
the CPU can continue to execute code.
The page buffer will automatically be cleared after the operation is finished.
9.3.2.4.4 Page Buffer Clear Command
The Page Buffer Clear (PBC) command clears the page buffer. The contents of the page buffer will be all ‘1’s after
the operation. The CPU will be halted when the operation executes (seven CPU cycles).
9.3.2.4.5 Chip Erase Command
The Chip Erase (CHER) command erases the Flash and the EEPROM. The EEPROM is unaltered if the EEPROM
Save During Chip Erase (EESAVE) fuse in FUSE.SYSCFG0 is set. The Flash will not be protected by Boot Section
Lock (BOOTLOCK) bit or Application Code Section Write Protection (APCWP) bit in NVMCTRL.CTRLB register. The
memory will be all ‘1’s after the operation.
9.3.2.4.6 EEPROM Erase Command
The EEPROM Erase (EEER) command erases the EEPROM. The EEPROM will be all ‘1’s after the operation. The
CPU will be halted while the EEPROM is being erased.
9.3.2.4.7 Write Fuse Command
The Write Fuse (WFU) command writes the fuses. It can only be used by the UPDI; the CPU cannot start this
command.
Follow this procedure to use the Write Fuse command:
1. Write the address of the fuse to the Address (NVMCTRL.ADDR) register.
2. Write the data to be written to the fuse to the Data (NVMCTRL.DATA) register.
3. Execute the Write Fuse command.
4. After the fuse is written, a Reset is required for the updated value to take effect.
For reading fuses, use a regular read on the memory location.
9.3.2.5
Write Access after Reset
After a Power-on Reset (POR), the NVMCTRL rejects any write attempts to the NVM for a given time. During this
period, the Flash Busy (FBUSY) and the EEPROM Busy (EEBUSY) bit field in the NVMCTRL.STATUS register will
read ‘1’. EEBUSY and FBUSY bit field must read ‘0’ before the page buffer can be filled, or NVM commands can be
issued.
This time-out period is disabled either by writing the Time-Out Disable (TOUTDIS) bit in the System Configuration 0
(FUSE.SYSCFG0) fuse to ‘0’ or by configuring the RSTPINCFG bit field in FUSE.SYSCFG0 fuse to UPDI.
9.3.3
Preventing Flash/EEPROM Corruption
During periods of low VDD, the Flash program or EEPROM data can be corrupted if the supply voltage is too low
for the CPU and the Flash/EEPROM to operate properly. These issues are the same on-board level systems using
Flash/EEPROM, and the same design solutions may be applied.
A Flash/EEPROM corruption can be caused by two situations when the voltage is too low:
1. A regular write sequence to the Flash, which requires a minimum voltage to operate correctly.
2. The CPU itself can execute instructions incorrectly when the supply voltage is too low.
See the Electrical Characteristics section for Maximum Frequency vs. VDD.
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NVMCTRL - Nonvolatile Memory Controller
Attention: Flash/EEPROM corruption can be avoided by taking these measures:
1. Keep the device in Reset during periods of any insufficient power supply voltage. Do this by
enabling the internal Brown-out Detector (BOD).
2. The voltage level monitor in the BOD can be used to prevent starting a write to the EEPROM close
to the BOD level.
3. If the detection levels of the internal BOD do not match the required detection level, an external low
VDD Reset protection circuit can be used. If a Reset occurs while a write operation is ongoing, the
write operation will be aborted.
9.3.4
Interrupts
Table 9-2. Available Interrupt Vectors and Sources
Offset
Name
Vector Description
Conditions
0x00
EEREADY
NVM
The EEPROM is ready for new write/erase operations.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags
(NVMCTRL.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding bit in the Interrupt Control
(NVMCTRL.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the NVMCTRL.INTFLAGS register for
details on how to clear interrupt flags.
9.3.5
Sleep Mode Operation
If there is no ongoing write operation, the NVMCTRL will enter a sleep mode when the system enters a sleep mode.
If a write operation is ongoing when the system enters a sleep mode, the NVM block, the NVM Controller, and the
system clock will remain ON until the write is finished. This is valid for all sleep modes, including Power-Down sleep
mode.
The EEPROM Ready interrupt will wake up the device only from Idle sleep mode.
The page buffer is cleared when waking up from sleep.
9.3.6
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). To write to these registers, a
certain key must first be written to the CPU.CCP register, followed by a write access to the protected bits within four
CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves the
protected register unchanged.
The following registers are under CCP:
Table 9-3. NVMCTRL - Registers under Configuration Change Protection
Register
Key
NVMCTRL.CTRLA
SPM
NVMCTRL.CTRLB
IOREG
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NVMCTRL - Nonvolatile Memory Controller
9.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
CTRLA
CTRLB
STATUS
INTCTRL
INTFLAGS
Reserved
7:0
7:0
7:0
7:0
7:0
0x06
DATA
0x08
ADDR
9.5
7
7:0
15:8
7:0
15:8
6
5
4
3
2
1
WRERROR
CMD[2:0]
BOOTLOCK
EEBUSY
0
APCWP
FBUSY
EEREADY
EEREADY
DATA[7:0]
DATA[15:8]
ADDR[7:0]
ADDR[15:8]
Register Description
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NVMCTRL - Nonvolatile Memory Controller
9.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
Configuration Change Protection
6
5
4
3
Access
Reset
2
R/W
0
1
CMD[2:0]
R/W
0
0
R/W
0
Bits 2:0 – CMD[2:0] Command
Write this bit field to issue a command. The Configuration Change Protection key for self-programming (SPM) has to
be written within four instructions before this write.
Value
Name
Description
0x0
No command
0x1
WP
Write page buffer to memory (NVMCTRL.ADDR selects which memory)
0x2
ER
Erase page (NVMCTRL.ADDR selects which memory)
0x3
ERWP Erase and write page (NVMCTRL.ADDR selects which memory)
0x4
PBC
Page buffer clear
0x5
CHER Chip erase: Erase Flash and EEPROM (unless EESAVE in FUSE.SYSCFG is ‘1’)
0x6
EEER
EEPROM Erase
0x7
WFU
Write fuse (only accessible through UPDI)
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NVMCTRL - Nonvolatile Memory Controller
9.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
Configuration Change Protection
6
5
4
3
Access
Reset
2
1
BOOTLOCK
R/W
0
0
APCWP
R/W
0
Bit 1 – BOOTLOCK Boot Section Lock
Writing this bit to ‘1’ locks the BOOT section from reading and instruction fetching.
If this bit is ‘1’, a read from the BOOT section will return ‘0’. A fetch from the BOOT section will also return ‘0’ as
instruction.
This bit can be written from the BOOT section only. It can only be cleared to ‘0’ by a Reset.
This bit will take effect only when the BOOT section is left the first time after the bit is written.
Bit 0 – APCWP Application Code Section Write Protection
Writing this bit to ‘1’ prevents further updates to the Application Code section.
This bit can only be written to ‘1’. It is cleared to ‘0’ only by Reset.
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NVMCTRL - Nonvolatile Memory Controller
9.5.3
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x02
0x00
-
6
5
4
3
Access
Reset
2
WRERROR
R
0
1
EEBUSY
R
0
0
FBUSY
R
0
Bit 2 – WRERROR Write Error
This bit will read ‘1’ when a write error has happened. A write error could be writing to different sections before doing
a page write or writing to a protected area. This bit is valid for the last operation.
Bit 1 – EEBUSY EEPROM Busy
This bit will read ‘1’ when the EEPROM is busy with a command.
Bit 0 – FBUSY Flash Busy
This bit will read ‘1’ when the Flash is busy with a command.
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NVMCTRL - Nonvolatile Memory Controller
9.5.4
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
0
EEREADY
R/W
0
Bit 0 – EEREADY EEPROM Ready Interrupt
Writing a ‘1’ to this bit enables the interrupt, which indicates that the EEPROM is ready for new write/erase
operations.
This is a level interrupt that will be triggered only when the EEREADY flag in the INTFLAGS register is set to ‘0’.
Thus, the interrupt must not be enabled before triggering an NVM command, as the EEREADY flag will not be set
before the NVM command is issued. The interrupt may be disabled in the interrupt handler.
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NVMCTRL - Nonvolatile Memory Controller
9.5.5
Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x04
0x00
-
6
5
4
3
2
1
0
EEREADY
R/W
0
Access
Reset
Bit 0 – EEREADY EEREADY Interrupt Flag
This flag is set continuously as long as the EEPROM is not busy. This flag is cleared by writing a ‘1’ to it.
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NVMCTRL - Nonvolatile Memory Controller
9.5.6
Data
Name:
Offset:
Reset:
Property:
DATA
0x06
0x00
-
The NVMCTRL.DATAL and NVMCTRL.DATAH register pair represents the 16-bit value, NVMCTRL.DATA. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DATA[15:0] Data Register
This register is used by the UPDI for fuse write operations.
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NVMCTRL - Nonvolatile Memory Controller
9.5.7
Address
Name:
Offset:
Reset:
Property:
ADDR
0x08
0x00
-
The NVMCTRL.ADDRL and NVMCTRL.ADDRH register pair represents the 16-bit value, NVMCTRL.ADDR. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADDR[15:0] Address
The Address register contains the address to the last memory location that has been updated.
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CLKCTRL - Clock Controller
10.
CLKCTRL - Clock Controller
10.1
Features
•
•
•
•
10.2
All Clocks and Clock Sources are Automatically Enabled when Requested by Peripherals
Internal Oscillators:
– 16/20 MHz oscillator (OSC20M)
– 32.768 kHz ultra low-power oscillator (OSCULP32K)
External Clock Options:
– 32.768 kHz crystal oscillator (XOSC32K)
– External clock
Main Clock Features:
– Safe run-time switching
– Prescaler with 1x to 64x division in 12 different settings
Overview
The Clock Controller (CLKCTRL) controls, distributes and prescales the clock signals from the available oscillators,
and supports internal and external clock sources.
The CLKCTRL is based on an automatic clock request system, implemented in all peripherals on the device. The
peripherals will automatically request the clocks needed. The request is routed to the correct clock source if multiple
clock sources are available.
The Main Clock (CLK_MAIN) is used by the CPU, RAM, and all peripherals connected to the I/O bus. The main clock
source can be selected and prescaled. Some peripherals can share the same clock source as the main clock or run
asynchronously to the main clock domain.
10.2.1
Block Diagram - CLKCTRL
Figure 10-1. CLKCTRL Block Diagram
With XOS32K and CLKOUT
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
NVM
RAM
CPU
CLK_CPU
Other
Peripherals
CLKOUT
CLK_PER
RTC
WDT
INT
BOD
PRESCALER
CLK_RTC
CLK_WDT
CLK_BOD
Main Clock Prescaler
CLK_MAIN
RTC
CLKSEL
Main Clock Switch
DIV32
XOSC32K
OSCULP32K
OSC20M
XOSC32K
SEL
OSC20M
Int. Oscillator
32.768 kHz ULP
Int. Oscillator
32.768 kHz
Ext. Crystal Oscillator
TOSC2
TOSC1
EXTCLK
The clock system consists of the main clock and other asynchronous clocks:
• Main Clock
This clock is used by the CPU, RAM, Flash, the I/O bus, and all peripherals connected to the I/O bus. It is
always running in Active and Idle sleep mode and can be running in Standby sleep mode if requested.
•
The main clock CLK_MAIN is prescaled and distributed by the clock controller:
• CLK_CPU is used by the CPU, SRAM, and the NVMCTRL peripheral to access the nonvolatile memory
• CLK_PER is used by all peripherals that are not listed under asynchronous clocks
Clocks running asynchronously to the main clock domain:
– CLK_RTC is used by the RTC/PIT. It will be requested when the RTC/PIT is enabled. The clock source for
CLK_RTC may only be changed if the peripheral is disabled.
– CLK_WDT is used by the WDT. It will be requested when the WDT is enabled.
– CLK_BOD is used by the BOD. It will be requested when the BOD is enabled in Sampled mode.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
The clock source for the for the main clock domain is configured by writing to the Clock Select (CLKSEL) bits in
the Main Clock Control A (CLKCTRL.MCLKCTRLA) register. The asynchronous clock sources are configured by
registers in the respective peripheral.
10.2.2
Signal Description
Signal
Type
Description
CLKOUT
Digital output
CLK_PER output
10.3
Functional Description
10.3.1
Sleep Mode Operation
When a clock source is not used or requested, it will stop. It is possible to request a clock source directly by writing a
‘1’ to the Run Standby (RUNSTDBY) bit in the respective oscillator’s Control A (CLKCTRL.[osc]CTRLA) register. This
will cause the oscillator to run constantly, except for Power-Down sleep mode. Additionally, when this bit is written to
‘1’, the oscillator start-up time is eliminated when the clock source is requested by a peripheral.
The main clock will always run in Active and Idle sleep modes. In Standby sleep mode, the main clock will run only
if any peripheral is requesting it, or the Run in Standby (RUNSTDBY) bit in the respective oscillator’s Control A
(CLKCTRL.[osc]CTRLA) register is written to ‘1’.
In Power-Down sleep mode, the main clock will stop after all NVM operations are completed. Refer to the Sleep
Controller section for more details on sleep mode operation.
10.3.2
Main Clock Selection and Prescaler
All internal oscillators can be used as the main clock source for CLK_MAIN. The main clock source is selectable from
software and can be safely changed during normal operation.
Built-in hardware protection prevents unsafe clock switching:
Upon selection of an external clock source, a switch to the chosen clock source will only occur if edges are detected.
Until a sufficient number of clock edges are detected the switch will not occur, and it will not be possible to change to
another clock source again without executing a Reset.
An ongoing clock source switch is indicated by the System Oscillator Changing (SOSC) flag in the Main Clock Status
(CLKCTRL.MCLKSTATUS) register. The stability of the external clock sources is indicated by the respective status
(EXTS and XOSC32KS in CLKCTRL.MCLKSTATUS) flags.
CAUTION
1.
2.
If an external clock source fails while used as the CLK_MAIN source, only the WDT can provide a
mechanism to switch back via System Reset.
Do not alter the properties of the external clock source while used as the CLK_MAIN source. This
can be interpreted as a clock failure.
CLK_MAIN is fed into a prescaler before it is used by the peripherals (CLK_PER) in the device. The prescaler divide
CLK_MAIN by a factor from 1 to 64.
Figure 10-2. Main Clock and Prescaler
OSC20M
32.768 kHz Osc.
32.768 kHz crystal Osc.
External clock
© 2021 Microchip Technology Inc.
CLK_MAIN
Main Clock Prescaler
(Div 1, 2, 4, 8, 16, 32,
64, 6, 10, 24, 48)
Complete Datasheet
CLK_PER
DS40002172C-page 88
ATmega808/809/1608/1609
CLKCTRL - Clock Controller
The Main Clock and Prescaler configuration (CLKCTRL.MCLKCTRLA, CLKCTRL.MCLKCTRLB) registers are
protected by the Configuration Change Protection Mechanism, employing a timed write procedure for changing these
registers.
10.3.3
Main Clock After Reset
After any Reset, CLK_MAIN is provided by the 16/20 MHz oscillator (OSC20M) and with a prescaler division
factor of 6. The actual frequency of the OSC20M is determined by the Frequency Select (FREQSEL) bits of the
Oscillator Configuration (FUSE.OSCCFG) fuse. Refer to the description of FUSE.OSCCFG for details of the possible
frequencies after Reset.
10.3.4
Clock Sources
The clock sources are divided into two main groups: internal oscillators and external clock sources. All the internal
clock sources are automatically enabled when they are requested by a peripheral.
The crystal oscillator must be enabled by writing a ‘1’ to the ENABLE bit in the 32.768 kHz Crystal Oscillator Control
A (CLKCTRL.XOSC32KCTRLA) register before it can serve as a clock source.
After Reset, the device starts running from the internal high-frequency oscillator or the internal 32.768 kHz oscillator.
The respective Oscillator Status bits in the Main Clock Status (CLKCTRL.MCLKSTATUS) register indicate if the clock
source is running and stable.
10.3.4.1 Internal Oscillators
The internal oscillators do not require any external components to run. See the related links for accuracy and
electrical characteristics.
10.3.4.1.1 16/20 MHz Oscillator (OSC20M)
This oscillator can operate at multiple frequencies, selected by the value of the Frequency Select (FREQSEL) bits in
the Oscillator Configuration (FUSE.OSCCFG) fuse.
After a system Reset, FUSE.OSCCFG determines the initial frequency of CLK_MAIN.
During Reset, the calibration values for the OSC20M are loaded from fuses. There are two different calibration
bit fields. The Calibration bit field (CAL20M) in the Calibration A (CLKCTRL.OSC20MCALIBA) register enables
calibration around the current center frequency. The Oscillator Temperature Coefficient Calibration (TEMPCAL20M)
bit field in the Calibration B (CLKCTRL.OSC20MCALIBB) register enables adjustment of the slope of the temperature
drift compensation.
For applications requiring more fine-tuned frequency than provided by the oscillator calibration, the remaining
oscillator frequency error measured during calibration is available in the Signature Row (SIGROW) for additional
compensation.
The oscillator calibration can be locked by the Oscillator Lock (OSCLOCK in FUSE.OSCCFG) fuse. When this fuse
is ‘1’, it is not possible to change the calibration. The calibration is locked if this oscillator is used as the main clock
source and the Lock Enable (LOCKEN) bit in the Control B (CLKCTRL.OSC20MCALIBB) register is ‘1’.
The calibration bits are protected by the Configuration Change Protection Mechanism, requiring a timed write
procedure for changing the main clock and prescaler settings.
Refer to the Electrical Characteristics section for the start-up time.
OSC20M Stored Frequency Error Compensation
This oscillator can operate at multiple frequencies, selected by the value of the Frequency Select (FREQSEL) bits in
the Oscillator Configuration (FUSE.OSCCFG) fuse at Reset. As previously mentioned, appropriate calibration values
are loaded to adjust to center frequency (OSC20M), and temperature drift compensation (TEMPCAL20M), meeting
the specifications defined in the internal oscillator characteristics. For applications requiring a wider operating range,
the relative factory stored frequency error after calibrations can be used. The four errors are measured at different
settings and are available in the signature row as signed byte values.
•
•
•
SIGROW.OSC16ERR3V is the frequency error from 16 MHz measured at 3V
SIGROW.OSC16ERR5V is the frequency error from 16 MHz measured at 5V
SIGROW.OSC20ERR3V is the frequency error from 20 MHz measured at 3V
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
•
SIGROW.OSC20ERR5V is the frequency error from 20 MHz measured at 5V
The error is stored as a compressed Q1.10 fixed point 8-bit value in order not to lose resolution, where the MSb is the
sign bit and the seven LSb the lower bits of the Q1.10.
BAUDactual = BAUDideal +
BAUDideal * SigRowError
1024
The minimum legal BAUD register value is 0x40. The target BAUD register value may therefore not be lower
than 0x4A to ensure that the compensated BAUD value stays within the legal range, even for parts with negative
compensation values. The example code below demonstrates how to apply this value for a more accurate USART
baud rate:
#include
/* Baud rate compensated with factory stored frequency error */
/* Asynchronous communication without Auto-baud (Sync ) */
/* 16MHz Clock, 3V and 600 BAUD
*/
int8_t sigrow_val
int32_t baud_reg_val
= SIGROW.OSC16ERR3V;
= 600;
assert (baud_reg_val >= 0x4A);
max neg comp
baud_reg_val *= (1024 + sigrow_val);
baud_reg_val /= 1024;
USART0.BAUD = (int16_t) baud_reg_val;
// read signed error
// ideal BAUD register value
// Verify legal min BAUD register value with
// sum resolution + error
// divide by resolution
// set adjusted baud rate
10.3.4.1.2 32.768 kHz Oscillator (OSCULP32K)
The 32.768 kHz oscillator is optimized for Ultra Low-Power (ULP) operation. Power consumption is decreased at the
cost of decreased accuracy compared to an external crystal oscillator.
This oscillator provides the 1.024 kHz signal for the Real-Time Counter (RTC), the Watchdog Timer (WDT), and the
Brown-out Detector (BOD).
The start-up time of this oscillator is the oscillator start-up time plus four oscillator cycles. Refer to section Electrical
Characteristics for the start-up time.
10.3.4.2 External Clock Sources
These external clock sources are available:
• External Clock from a pin (EXTCLK).
• The TOSC1 and TOSC2 pins are dedicated to driving a 32.768 kHz crystal oscillator (XOSC32K).
• Instead of a crystal oscillator, TOSC1 can be configured to accept an external clock source.
10.3.4.2.1 32.768 kHz Crystal Oscillator (XOSC32K)
This oscillator supports two input options: Either a crystal is connected to the pins TOSC1 and TOSC2, or an external
clock running at 32.768 kHz is connected to TOSC1. The input option must be configured by writing the Source
Select (SEL) bit in the XOSC32K Control A (CLKCTRL.XOSC32KCTRLA) register.
The XOSC32K is enabled by writing a ‘1’ to its ENABLE bit in CLKCTRL.XOSC32KCTRLA. When enabled, the
configuration of the GPIO pins used by the XOSC32K is overridden as TOSC1 and TOSC2 pins. The Enable bit
needs to be set for the oscillator to start running when requested.
The start-up time of a given crystal oscillator can be accommodated by writing to the Crystal Start-up Time bits
(CSUT) in CLKCTRL.XOSC32KCTRLA.
When XOSC32K is configured to use an external clock on TOSC1, the start-up time is fixed to two cycles.
10.3.4.2.2 External Clock (EXTCLK)
The EXTCLK is taken directly from the pin. This GPIO pin is automatically configured for EXTCLK if any peripheral is
requesting this clock.
This clock source has a start-up time of two cycles when first requested.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.3.5
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). To write to these registers, a
certain key must first be written to the CPU.CCP register, followed by a write access to the protected bits within four
CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves the
protected register unchanged.
The following registers are under CCP:
Table 10-1. CLKCTRL - Registers Under Configuration Change Protection
Register
Key
CLKCTRL.MCLKCTRLB
IOREG
CLKCTRL.MCLKLOCK
IOREG
CLKCTRL.XOSC32KCTRLA
IOREG
CLKCTRL.MCLKCTRLA
IOREG
CLKCTRL.OSC20MCTRLA
IOREG
CLKCTRL.OSC20MCALIBA
IOREG
CLKCTRL.OSC20MCALIBB
IOREG
CLKCTRL.OSC32KCTRLA
IOREG
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.4
Register Summary
Offset
Name
Bit Pos.
7
0x00
0x01
0x02
0x03
0x04
...
0x0F
0x10
0x11
0x12
0x13
...
0x17
0x18
0x19
...
0x1B
0x1C
MCLKCTRLA
MCLKCTRLB
MCLKLOCK
MCLKSTATUS
7:0
7:0
7:0
7:0
CLKOUT
10.5
6
5
4
3
2
XOSC32KS
OSC32KS
0
CLKSEL[1:0]
PEN
LOCKEN
SOSC
PDIV[3:0]
EXTS
1
OSC20MS
Reserved
OSC20MCTRLA
OSC20MCALIBA
OSC20MCALIBB
7:0
7:0
7:0
RUNSTDBY
CAL20M[6:0]
LOCK
TEMPCAL20M[3:0]
Reserved
OSC32KCTRLA
7:0
RUNSTDBY
Reserved
XOSC32KCTRLA
7:0
CSUT[1:0]
SEL
RUNSTDBY
ENABLE
Register Description
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.1
Main Clock Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CLKOUT
R/W
0
MCLKCTRLA
0x00
0x00
Configuration Change Protection
6
5
4
3
2
1
0
CLKSEL[1:0]
R/W
R/W
0
0
Bit 7 – CLKOUT System Clock Out
When this bit is written to ‘1’, the system clock is output to the CLKOUT pin.
When the device is in a sleep mode, there is no clock output unless a peripheral is using the system clock.
Bits 1:0 – CLKSEL[1:0] Clock Select
This bit field selects the source for the Main Clock (CLK_MAIN).
Value
Name
Description
0x0
OSC20M
16/20 MHz internal oscillator
0x1
OSCULP32K
32.768 kHz internal ultra low-power oscillator
0x2
XOSC32K
32.768 kHz external crystal oscillator
0x3
EXTCLK
External clock
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.2
Main Clock Control B
Name:
Offset:
Reset:
Property:
Bit
7
MCLKCTRLB
0x01
0x11
Configuration Change Protection
6
5
4
3
2
1
R/W
0
R/W
0
PDIV[3:0]
Access
Reset
R/W
1
R/W
0
0
PEN
R/W
1
Bits 4:1 – PDIV[3:0] Prescaler Division
If the Prescaler Enable (PEN) bit is written to ‘1’, these bits define the division ratio of the main clock prescaler.
These bits can be written during run-time to vary the clock frequency of the system to suit the application
requirements.
The user software must ensure a correct configuration of the input frequency (CLK_MAIN) and prescaler settings, so
that the resulting frequency of CLK_PER never exceeds the allowed maximum (see Electrical Characteristics).
Value
Name
Description
0x0
DIV2
CLK_MAIN divided by 2
0x1
DIV4
CLK_MAIN divided by 4
0x2
DIV8
CLK_MAIN divided by 8
0x3
DIV16
CLK_MAIN divided by 16
0x4
DIV32
CLK_MAIN divided by 32
0x5
DIV64
CLK_MAIN divided by 64
0x6-0x7 Reserved
0x8
DIV6
CLK_MAIN divided by 6
0x9
DIV10
CLK_MAIN divided by 10
0xA
DIV12
CLK_MAIN divided by 12
0xB
DIV24
CLK_MAIN divided by 24
0xC
DIV48
CLK_MAIN divided by 48
other
Reserved
Bit 0 – PEN Prescaler Enable
This bit must be written to ‘1’ to enable the prescaler. When enabled, the division ratio is selected by the PDIV bit
field.
When this bit is written to ‘0’, the main clock will pass through undivided (CLK_PER = CLK_MAIN), regardless of the
value of PDIV.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.3
Main Clock Lock
Name:
Offset:
Reset:
Property:
Bit
7
MCLKLOCK
0x02
Based on OSCLOCK in FUSE.OSCCFG
Configuration Change Protection
6
5
4
3
Access
Reset
2
1
0
LOCKEN
R/W
x
Bit 0 – LOCKEN Lock Enable
Writing this bit to ‘1’ will lock the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers, and, if applicable,
the calibration settings for the current main clock source from further software updates. Once locked, the
CLKCTRL.MCLKLOCK registers cannot be accessed until the next hardware Reset.
This provides protection for the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers and calibration
settings for the main clock source from unintentional modification by software.
At Reset, the LOCKEN bit is loaded based on the OSCLOCK bit in FUSE.OSCCFG.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.4
Main Clock Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
EXTS
R
0
MCLKSTATUS
0x03
0x00
-
6
XOSC32KS
R
0
5
OSC32KS
R
0
4
OSC20MS
R
0
3
2
1
0
SOSC
R
0
Bit 7 – EXTS External Clock Status
Value
Description
0
EXTCLK has not started
1
EXTCLK has started
Bit 6 – XOSC32KS XOSC32K Status
The Status bit will only be available if the source is requested as the main clock or by another module. If the oscillator
RUNSTDBY bit is set and the oscillator is unused/not requested, this bit will be ‘0’.
Value
Description
0
XOSC32K is not stable
1
XOSC32K is stable
Bit 5 – OSC32KS OSCULP32K Status
The Status bit will only be available if the source is requested as the main clock or by another module. If the oscillator
RUNSTDBY bit is set and the oscillator is unused/not requested, this bit will be ‘0’.
Value
Description
0
OSCULP32K is not stable
1
OSCULP32K is stable
Bit 4 – OSC20MS OSC20M Status
The Status bit will only be available if the source is requested as the main clock or by another module. If the oscillator
RUNSTDBY bit is set and the oscillator is unused/not requested, this bit will be ‘0’.
Value
Description
0
OSC20M is not stable
1
OSC20M is stable
Bit 0 – SOSC Main Clock Oscillator Changing
Value
Description
0
The clock source for CLK_MAIN is not undergoing a switch
1
The clock source for CLK_MAIN is undergoing a switch and will change as soon as the new source is
stable
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Complete Datasheet
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.5
16/20 MHz Oscillator Control A
Name:
Offset:
Reset:
Property:
Bit
7
OSC20MCTRLA
0x10
0x00
Configuration Change Protection
6
5
4
3
Access
Reset
2
1
RUNSTDBY
R/W
0
0
Bit 1 – RUNSTDBY Run Standby
This bit forces the oscillator ON in all modes, even when unused by the system. In Standby sleep mode this can be
used to ensure immediate wake-up and not waiting for oscillator start-up time.
When not requested by peripherals, no oscillator output is provided.
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up time will be
removed when this bit is set.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.6
16/20 MHz Oscillator Calibration A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
OSC20MCALIBA
0x11
Based on FREQSEL in FUSE.OSCCFG
Configuration Change Protection
6
5
4
R/W
x
R/W
x
R/W
x
3
CAL20M[6:0]
R/W
x
2
1
0
R/W
x
R/W
x
R/W
x
Bits 6:0 – CAL20M[6:0] Calibration
These bits change the frequency around the current center frequency of the OSC20M for fine-tuning.
At Reset, the factory-calibrated values are loaded based on the FREQSEL bit in FUSE.OSCCFG.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.7
16/20 MHz Oscillator Calibration B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
LOCK
R
x
OSC20MCALIBB
0x12
Based on FUSE.OSCCFG
Configuration Change Protection
6
5
4
3
R/W
x
2
1
TEMPCAL20M[3:0]
R/W
R/W
x
x
0
R/W
x
Bit 7 – LOCK Oscillator Calibration Locked by Fuse
When this bit is set, the calibration settings in CLKCTRL.OSC20MCALIBA and CLKCTRL.OSC20MCALIBB cannot
be changed.
The Reset value is loaded from the OSCLOCK bit in the Oscillator Configuration (FUSE.OSCCFG) fuse.
Bits 3:0 – TEMPCAL20M[3:0] Oscillator Temperature Coefficient Calibration
These bits tune the slope of the temperature compensation.
At Reset, the factory-calibrated values are loaded based on the FREQSEL bits in FUSE.OSCCFG.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.8
32.768 kHz Oscillator Control A
Name:
Offset:
Reset:
Property:
Bit
7
OSC32KCTRLA
0x18
0x00
Configuration Change Protection
6
5
4
3
Access
Reset
2
1
RUNSTDBY
R/W
0
0
Bit 1 – RUNSTDBY Run Standby
This bit forces the oscillator ON in all modes, even when unused by the system. In Standby sleep mode this can be
used to ensure immediate wake-up and not waiting for the oscillator start-up time.
When not requested by peripherals, no oscillator output is provided.
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up time will be
removed when this bit is set.
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ATmega808/809/1608/1609
CLKCTRL - Clock Controller
10.5.9
32.768 kHz Crystal Oscillator Control A
Name:
Offset:
Reset:
Property:
XOSC32KCTRLA
0x1C
0x00
Configuration Change Protection
The SEL and CSUT bits cannot be changed as long as the ENABLE bit is set or the XOSC32K Stable (XOSC32KS)
bit in CLKCTRL.MCLKSTATUS is high.
To change settings safely: Write a ‘0’ to the ENABLE bit and wait until XOSC32KS is ‘0’ before re-enabling the
XOSC32K with new settings.
Bit
7
6
5
4
3
CSUT[1:0]
Access
Reset
R/W
0
R/W
0
2
SEL
R/W
0
1
RUNSTDBY
R/W
0
0
ENABLE
R/W
0
Bits 5:4 – CSUT[1:0] Crystal Start-Up Time
These bits select the start-up time for the XOSC32K. It is write-protected when the oscillator is enabled (ENABLE =
1).
If SEL = 1, the start-up time will not be applied.
Value
Name
Description
0x0
1K
1k cycles
0x1
16K
16k cycles
0x2
32K
32k cycles
0x3
64K
64k cycles
Bit 2 – SEL Source Select
This bit selects the external source type. It is write-protected when the oscillator is enabled (ENABLE = 1).
Value
Description
0
External crystal
1
External clock on TOSC1 pin
Bit 1 – RUNSTDBY Run Standby
Writing this bit to ‘1’ starts the crystal oscillator and forces the oscillator ON in all modes, even when unused by the
system if the ENABLE bit is set. In Standby sleep mode, this can be used to ensure immediate wake-up and not
waiting for oscillator start-up time. When this bit is ‘0’, the crystal oscillator is only running when requested and the
ENABLE bit is set.
The output of XOSC32K is not sent to other peripherals unless it is requested by one or more peripherals.
When the RUNSTDBY bit is set, there will only be a delay of two to three crystal oscillator cycles after a request until
the oscillator output is received, if the initial crystal start-up time has already completed.
According to RUNSTDBY bit, the oscillator will be turned ON all the time if the device is in Active, Idle, or Standby
sleep mode, or only be enabled when requested.
This bit is I/O protected to prevent any unintentional enabling of the oscillator.
Bit 0 – ENABLE Enable
When this bit is written to ‘1’, the configuration of the respective input pins is overridden to TOSC1 and TOSC2. Also,
the Source Select (SEL) bit and Crystal Start-Up Time (CSUT) become read-only.
This bit is I/O protected to prevent any unintentional enabling of the oscillator.
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ATmega808/809/1608/1609
SLPCTRL - Sleep Controller
11.
SLPCTRL - Sleep Controller
11.1
Features
•
•
•
11.2
Power Management for Adjusting Power Consumption and Functions
Three Sleep Modes:
– Idle
– Standby
– Power-Down
Configurable Standby Mode where Peripherals Can Be Configured as ON or OFF
Overview
Sleep modes are used to shut down peripherals and clock domains in the device in order to save power. The Sleep
Controller (SLPCTRL) controls and handles the transitions between Active and sleep modes.
There are four modes available: One Active mode in which software is executed, and three sleep modes. The
available sleep modes are Idle, Standby and Power-Down.
All sleep modes are available and can be entered from the Active mode. In Active mode, the CPU is executing
application code. When the device enters sleep mode, the program execution is stopped. The application code
decides which sleep mode to enter and when.
Interrupts are used to wake the device from sleep. The available interrupt wake-up sources depend on the configured
sleep mode. When an interrupt occurs, the device will wake up and execute the Interrupt Service Routine before
continuing normal program execution from the first instruction after the SLEEP instruction. Any Reset will take the
device out of sleep mode.
The content of the register file, SRAM and registers, is kept during sleep. If a Reset occurs during sleep, the device
will reset, start and execute from the Reset vector.
11.2.1
Block Diagram
Figure 11-1. Sleep Controller in the System
SLEEP Instruction
SLPCTRL
Interrupt Request
CPU
Sleep State
Interrupt Request
Peripheral
11.3
11.3.1
Functional Description
Initialization
To put the device into a sleep mode, follow these steps:
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SLPCTRL - Sleep Controller
1.
Configure and enable the interrupts that are able to wake the device from sleep.
Also, enable global interrupts.
WARNING
2.
If there are no interrupts enabled when going to sleep, the device cannot wake up again. Only a
Reset will allow the device to continue operation.
Select which sleep mode to enter and enable the Sleep Controller by writing to the Sleep Mode (SMODE) bit
field and the Enable (SEN) bit in the Control A (SLPCTRL.CTRLA) register.
The SLEEP instruction must be executed to make the device go to sleep.
11.3.2
Operation
11.3.2.1 Sleep Modes
In addition to Active mode, there are three different sleep modes with decreasing power consumption and
functionality.
Idle
Standby
PowerDown
The CPU stops executing code. No peripherals are disabled, and all interrupt sources can wake the
device.
The user can configure peripherals to be enabled or not, using the respective RUNSTBY bit. This
means that the power consumption is highly dependent on what functionality is enabled, and thus may
vary between the Idle and Power-Down levels.
SleepWalking is available for the ADC module.
BOD, WDT, and PIT (a component of the RTC) are active.
The only wake-up sources are the pin change interrupt, PIT, VLM, TWI address match, and CCL.
Table 11-1. Sleep Mode Activity Overview for Peripherals
Peripheral
Active in Sleep Mode
Idle
Standby
Power-Down
CPU
RTC
X
X(1,2)
X(2)
WDT
X
X
X
BOD
X
X
X
EVSYS
X
X
X
CCL
X
X(1)
ACn
ADCn
TCBn
All other peripherals
X
Notes:
1. For the peripheral to run in Standby sleep mode, the RUNSTDBY bit of the corresponding peripheral must be
set.
2. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY bit to be set.
In Power-Down sleep mode, only the PIT functionality is available.
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SLPCTRL - Sleep Controller
Table 11-2. Sleep Mode Activity Overview for Clock Sources
Clock Source
Active in Sleep Mode
Idle
Standby
Power-Down
Main Clock Source
X
X(1)
RTC Clock Source
X
X(1,2)
X(2)
WDT Oscillator
X
X
X
BOD Oscillator(3)
X
X
X
X
X(1)
CCL clock source
Notes:
1. For the clock source to run in Standby sleep mode, the RUNSTDBY bit of the corresponding peripheral must
be set.
2. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY bit to be set.
In Power-Down sleep mode, only the PIT functionality is available.
3. The Sampled mode only.
Table 11-3. Sleep Mode Wake-Up Sources
Wake-Up Source
Active in Sleep Mode
Idle
Standby
Power-Down
PORT Pin interrupt
X
X
X(1)
TWI Address Match interrupt
X
X
X
BOD VLM interrupt
X
X
X
CCL interrupts
X
X(2,3)
X(3)
RTC interrupts
X
X(2,4)
X(4)
USART interrupts
X(5)
X(6)
-
TCAn interrupts
X
X(2)
X
-
TCBn interrupts
ADCn interrupts
ACn Compare interrupt
All other interrupts
-
Notes:
1. The I/O pin has to be configured according to Asynchronous Sensing Pin Properties in the PORT section.
2. RUNSTDBY bit of the corresponding peripheral must be set to enter an active state.
3. CCL can wake up the device if the path through LUTn is asynchronous (FILTSEL=0x0 and EDGEDET=0x0 in
LUTnCTRLA register).
4. In Standby sleep mode, only the RTC functionality requires the RUNSTDBY to be set to enter an active state.
In Power-Down sleep mode, only the PIT functionality is available.
5. Start-of-Frame interrupt is only available in Standby Sleep Mode.
6. In Standby Sleep Mode only the Start-of-Frame interrupt will trigger Wake-Up from USART.
11.3.2.2 Wake-up Time
The normal wake-up time for the device is six main clock cycles (CLK_PER), plus the time it takes to start the main
clock source:
• In Idle sleep mode, the main clock source is kept running to eliminate additional wake-up time.
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SLPCTRL - Sleep Controller
•
•
In Standby sleep mode, the main clock might be running depending on the peripheral configuration.
In Power-Down sleep mode, only the ULP 32.768 kHz oscillator and the RTC clock may be running if it is used
by the BOD or WDT. All other clock sources will be OFF.
Table 11-4. Sleep Modes and Start-up Time
Sleep Mode
Start-up Time
IDLE
6 CLK
Standby
6 CLK + OSC start-up
Power-Down
6 CLK + OSC start-up
The start-up time for the different clock sources is described in the Clock Controller (CLKCTRL) section.
In addition to the normal wake-up time, it is possible to make the device wait until the BOD is ready before
executing code. This is done by writing 0x3 to the BOD Operation mode in Active and Idle bits (ACTIVE) in the BOD
Configuration fuse (FUSE.BODCFG). If the BOD is ready before the normal wake-up time, the total wake-up time will
be the same. If the BOD takes longer than the normal wake-up time, the wake-up time will be extended until the BOD
is ready. This ensures correct supply voltage whenever code is executed.
11.3.3
Debug Operation
During run-time debugging, this peripheral will continue normal operation. The SLPCTRL is only affected by a break
in the debug operation: If the SLPCTRL is in a sleep mode when a break occurs, the device will wake up, and the
SLPCTRL will go to Active mode, even if there are no pending interrupt requests.
If the peripheral is configured to require periodic service by the CPU through interrupts or similar, improper operation
or data loss may result during halted debugging.
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SLPCTRL - Sleep Controller
11.4
Register Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
11.5
7
6
5
4
3
2
1
SMODE[1:0]
0
SEN
Register Description
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SLPCTRL - Sleep Controller
11.5.1
Control A
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x00
-
Bit
7
6
5
4
3
Access
Reset
R
0
R
0
R
0
R
0
R
0
2
1
SMODE[1:0]
R/W
R/W
0
0
0
SEN
R/W
0
Bits 2:1 – SMODE[1:0] Sleep Mode
Writing these bits selects which sleep mode to enter when the Sleep Enable (SEN) bit is written to ‘1’ and the SLEEP
instruction is executed.
Value
Name
Description
0x0
IDLE
Idle sleep mode enabled
0x1
STANDBY
Standby sleep mode enabled
0x2
PDOWN
Power-Down sleep mode enabled
other
Reserved
Bit 0 – SEN Sleep Enable
This bit must be written to ‘1’ before the SLEEP instruction is executed to make the MCU enter the selected Sleep
mode.
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RSTCTRL - Reset Controller
12.
RSTCTRL - Reset Controller
12.1
Features
•
•
•
•
12.2
Returns the Device to an Initial State after a Reset
Identifies the Previous Reset Source
Power Supply Reset Sources:
– Power-on Reset (POR)
– Brown-out Detector (BOD) Reset
User Reset Sources:
– External Reset (RESET)
– Watchdog Timer (WDT) Reset
– Software Reset (SWRST)
– Unified Program and Debug Interface (UPDI) Reset
Overview
The Reset Controller (RSTCTRL) manages the Reset of the device. It issues a device Reset, sets the device to its
initial state, and allows the Reset source to be identified by software.
12.2.1
Block Diagram
Figure 12-1. Reset System Overview
RESET SOURCES
VDD
RESET CONTROLLER
POR
Pull-up
resistor
BOD
UPDI
External Reset
RESET
WDT
All other
peripherals
UPDI
CPU (SW)
12.2.2
Signal Description
Signal
Description
Type
RESET
External Reset (active-low)
Digital input
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RSTCTRL - Reset Controller
12.3
Functional Description
12.3.1
Initialization
The RSTCTRL is always enabled, but some of the Reset sources must be enabled individually (either by Fuses or by
software) before they can request a Reset.
After a Reset from any source, the registers in the device with automatic loading from the Fuses or from the
Signature Row are updated.
12.3.2
Operation
12.3.2.1 Reset Sources
After any Reset, the source that caused the Reset is found in the Reset Flag (RSTCTRL.RSTFR) register. The user
can identify the previous Reset source by reading this register in the software application.
There are two types of Resets based on the source:
• Power Supply Reset Sources:
– Power-on Reset (POR)
– Brown-out Detector (BOD) Reset
• User Reset Sources:
– External Reset (RESET)
– Watchdog Timer (WDT) Reset
– Software Reset (SWRST)
– Unified Program and Debug Interface (UPDI) Reset
12.3.2.1.1 Power-on Reset (POR)
The purpose of the Power-on Reset (POR) is to ensure a safe start-up of logic and memories. It is generated by an
on-chip detection circuit and is always enabled. The POR is activated when the VDD rises and gives active reset as
long as VDD is below the POR threshold voltage (VPOR+). The reset will last until the Start-up and reset initialization
sequence is finished. The Start-up Time (SUT) is determined by fuses. Reset is activated again, without any delay,
when VDD falls below the detection level (VPOR-).
Figure 12-2. MCU Start-Up, RESET Tied to VDD
tSUT
VDD
DEVICE
STATE
tINIT
VPOR-
VPOR+
OFF
Active
Reset
Start-up
Initialization
Running
Active
Reset
INTERNAL
RESET
12.3.2.1.2 Brown-out Detector (BOD) Reset
The on-chip Brown-out Detector (BOD) circuit will monitor the VDD level during operation by comparing it to a fixed
trigger level. The trigger level for the BOD can be selected by fuses. If BOD is unused in the application, it is forced to
a minimum level in order to ensure a safe operation during internal Reset and chip erase.
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RSTCTRL - Reset Controller
Figure 12-3. Brown-out Detector Reset
tBOD
tSUT
tINIT
VBOD+
VDD
VBOD-
DEVICE
STATE
Active
Reset
Running
Initialization
Start-up
Running
INTERNAL
RESET
12.3.2.1.3 External Reset
The external Reset is enabled by a fuse, see the RSTPINCFG field in FUSE.SYSCFG0.
When enabled, the external Reset requests a Reset as long as the RESET pin is low. The device will stay in Reset
until RESET is high again.
Figure 12-4. External Reset Characteristics
tRST
tINIT
VDD
VRST+
RESET
DEVICE
STATE
VRST-
Running
Active
Reset
Initialization
Running
INTERNAL
RESET
12.3.2.1.4 Watchdog Reset
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset
from software according to the programmed time-out period, a Watchdog Reset will be issued. See the WDT Watchdog Timer section for further details.
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RSTCTRL - Reset Controller
Figure 12-5. Watchdog Reset
tWDTR
tINIT
VDD
WDT
TIME-OUT
DEVICE
STATE
Running
Active
Reset
Initialization
Running
INTERNAL
RESET
Note: The time tWDTR is approximately 50 ns.
12.3.2.1.5 Software Reset
The software Reset makes it possible to issue a system Reset from software. The Reset is generated by writing a ‘1’
to the Software Reset Enable (SWRE) bit in the Software Reset (RSTCTRL.SWRR) register.
The Reset will take place immediately after the bit is written, and the device will be kept in Reset until the Reset
sequence is completed.
Figure 12-6. Software Reset
tSWR
tINIT
VDD
SWRST
DEVICE
STATE
Running
Active
Reset
Initialization
Running
INTERNAL
RESET
Note: The time tSWR is approximately 50 ns.
12.3.2.1.6 Unified Program and Debug Interface (UPDI) Reset
The Unified Program and Debug Interface (UPDI) contains a separate Reset source used to reset the device
during external programming and debugging. The Reset source is accessible only from external debuggers and
programmers. More details can be found in the UPDI - Unified Program and Debug Interface section.
12.3.2.1.7 Domains Affected By Reset
The following logic domains are affected by the various Resets:
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RSTCTRL - Reset Controller
Table 12-1. Logic Domains Affected by Various Resets
Reset Type
POR
BOD
Software Reset
External Reset
Watchdog Reset
UPDI Reset
Fuses are Reloaded
X
X
X
X
X
X
Reset of UPDI
X
X
Reset of Other Volatile Logic
X
X
X
X
X
X
12.3.2.2 Reset Time
The Reset time can be split into two parts.
The first part is when any of the Reset sources are active. This part depends on the input to the Reset sources. The
external Reset is active as long as the RESET pin is low. The Power-on Reset (POR) and the Brown-out Detector
(BOD) are active as long as the supply voltage is below the Reset source threshold.
The second part is when all the Reset sources are released, and an internal Reset initialization of the device is done.
This time will be increased with the start-up time given by the Start-Up Time Setting (SUT) bit field in the System
Configuration 1 (FUSE.SYSCFG1) fuse when the reset is caused by a Power Supply Reset Source. The internal
Reset initialization time will also increase if the Cyclic Redundancy Check Memory Scan (CRCSCAN) is configured to
run at start-up. This configuration can be changed in the CRC Source (CRCSRC) bit field in the System Configuration
0 (FUSE.SYSCFG0) fuse.
12.3.3
Sleep Mode Operation
The RSTCTRL operates in Active mode and in all sleep modes.
12.3.4
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). To write to these registers, a
certain key must first be written to the CPU.CCP register, followed by a write access to the protected bits within four
CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves the
protected register unchanged.
The following registers are under CCP:
Table 12-2. RSTCTRL - Registers Under Configuration Change Protection
Register
Key
RSTCTRL.SWRR
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RSTCTRL - Reset Controller
12.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
RSTFR
SWRR
7:0
7:0
12.5
7
6
5
4
3
2
1
0
UPDIRF
SWRF
WDRF
EXTRF
BORF
PORF
SWRE
Register Description
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RSTCTRL - Reset Controller
12.5.1
Reset Flag Register
Name:
Offset:
Reset:
Property:
RSTFR
0x00
0xXX
-
All flags are cleared by writing a ‘1’ to them. They are also cleared by a Power-on Reset (POR), except for the
Power-on Reset Flag (PORF).
Bit
7
6
Access
Reset
5
UPDIRF
R/W
x
4
SWRF
R/W
x
3
WDRF
R/W
x
2
EXTRF
R/W
x
1
BORF
R/W
x
0
PORF
R/W
x
Bit 5 – UPDIRF UPDI Reset Flag
This bit is set if a UPDI Reset occurs.
Bit 4 – SWRF Software Reset Flag
This bit is set if a Software Reset occurs.
Bit 3 – WDRF Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs.
Bit 2 – EXTRF External Reset Flag
This bit is set if an External Reset occurs.
Bit 1 – BORF Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs.
Bit 0 – PORF Power-on Reset Flag
This bit is set if a POR occurs.
After a POR, only the POR flag is set and all the other flags are cleared. No other flags can be set before a full
system boot is run after the POR.
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RSTCTRL - Reset Controller
12.5.2
Software Reset Register
Name:
Offset:
Reset:
Property:
Bit
7
SWRR
0x01
0x00
Configuration Change Protection
6
5
4
3
Access
Reset
2
1
0
SWRE
R/W
0
Bit 0 – SWRE Software Reset Enable
When this bit is written to ‘1’, a software Reset will occur.
This bit will always read as ‘0’.
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CPUINT - CPU Interrupt Controller
13.
CPUINT - CPU Interrupt Controller
13.1
Features
•
•
•
•
•
•
•
13.2
Short and Predictable Interrupt Response Time
Separate Interrupt Configuration and Vector Address for Each Interrupt
Interrupt Prioritizing by Level and Vector Address
Non-Maskable Interrupts (NMI) for Critical Functions
Two Interrupt Priority Levels: 0 (Normal) and 1 (High):
– One of the interrupt requests can optionally be assigned as a priority level 1 interrupt
– Optional round robin priority scheme for priority level 0 interrupts
Interrupt Vectors Optionally Placed in the Application Section or the Boot Loader Section
Selectable Compact Vector Table (CVT)
Overview
An interrupt request signals a change of state inside a peripheral and can be used to alter the program execution.
The peripherals can have one or more interrupts. All interrupts are individually enabled and configured. When an
interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition occurs.
The CPU Interrupt Controller (CPUINT) handles and prioritizes the interrupt requests. When an interrupt is enabled
and the interrupt condition occurs, the CPUINT will receive the interrupt request. Based on the interrupt's priority level
and the priority level of any ongoing interrupt, the interrupt request is either acknowledged or kept pending until it
has priority. After returning from the interrupt handler, the program execution continues from where it was before the
interrupt occurred, and any pending interrupts are served after one instruction is executed.
The CPUINT offers NMI for critical functions, one selectable high-priority interrupt and an optional round robin
scheduling scheme for normal-priority interrupts. The round robin scheduling ensures that all interrupts are serviced
within a certain amount of time.
13.2.1
Block Diagram
Figure 13-1. CPUINT Block Diagram
Interrupt Controller
Priority
Decoder
Peripheral 1
INT REQ
CPU RETI
CPU INT ACK
CPU
CPU INT REQ
Peripheral n
INT REQ
STATUS
LVL0PRI
LVL1VEC
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CPUINT - CPU Interrupt Controller
13.3
Functional Description
13.3.1
Initialization
An interrupt must be initialized in the following order:
1.
2.
3.
13.3.2
Configure the CPUINT if the default configuration is not adequate (optional):
– Vector handling is configured by writing to the respective bits (IVSEL and CVT) in the Control A
(CPUINT.CTRLA) register.
– Vector prioritizing by round robin is enabled by writing a ‘1’ to the Round Robin Priority Enable (LVL0RR)
bit in CPUINT.CTRLA.
– Select the Priority Level 1 vector by writing the interrupt vector number to the Interrupt Vector with Priority
Level 1 (CPUINT.LVL1VEC) register.
Configure the interrupt conditions within the peripheral and enable the peripheral’s interrupt.
Enable interrupts globally by writing a ‘1’ to the Global Interrupt Enable (I) bit in the CPU Status (CPU.SREG)
register.
Operation
13.3.2.1 Enabling, Disabling and Resetting
The global enabling of interrupts is done by writing a ‘1’ to the Global Interrupt Enable (I) bit in the CPU Status
(CPU.SREG) register. To disable interrupts globally, write a ‘0’ to the I bit in CPU.SREG.
The desired interrupt lines must also be enabled in the respective peripheral by writing to the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
The interrupt flags are not automatically cleared after the interrupt is executed. The respective INTFLAGS register
descriptions provide information on how to clear specific flags.
13.3.2.2 Interrupt Vector Locations
The interrupt vector placement is dependent on the value of the Interrupt Vector Select (IVSEL) bit in the Control A
(CPUINT.CTRLA) register. Refer to the IVSEL description in CPUINT.CTRLA for the possible locations.
If the program never enables an interrupt source, the interrupt vectors are not used, and the regular program code
can be placed at these locations.
13.3.2.3 Interrupt Response Time
The minimum interrupt response time is represented in the following table.
Table 13-1. Minimum Interrupt Response Time
Flash Size > 8 KB
Flash Size ≤ 8 KB
Finish ongoing instruction
One cycle
One cycle
Store PC to stack
Two cycles
Two cycles
Jump to interrupt handler
Three cycles (jmp)
Two cycles (rjmp)
After the Program Counter is pushed on the stack, the program vector for the interrupt is executed. See the following
figure.
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CPUINT - CPU Interrupt Controller
Figure 13-2. Interrupt Execution of Single-Cycle Instruction
Clock
Program Counter
"Instruction"
(1)
INT REQ
INT ACK
If an interrupt occurs during the execution of a multi-cycle instruction, the instruction is completed before the interrupt
is served, as shown in the following figure.
Figure 13-3. Interrupt Execution of Multi-Cycle Instruction
Clock
Program Counter
"Instruction"
(1)
INT REQ
INT ACK
If an interrupt occurs when the device is in a sleep mode, the interrupt execution response time is increased by five
clock cycles, as shown in the figure below. Also, the response time is increased by the start-up time from the selected
sleep mode.
Figure 13-4. Interrupt Execution From Sleep
Clock
Program Counter
(1)
"Instruction"
INT REQ
INT ACK
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the Program
Counter. During these clock cycles, the Program Counter is popped from the stack, and the Stack Pointer is
incremented.
Note:
1. Devices with 8 KB of Flash or less use RJMP instead of JMP, which takes only two clock cycles.
13.3.2.4 Interrupt Priority
All interrupt vectors are assigned to one of three possible priority levels, as shown in the table below. An interrupt
request from a high-priority source will interrupt any ongoing interrupt handler from a normal-priority source. When
returning from the high-priority interrupt handler, the execution of the normal-priority interrupt handler will resume.
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CPUINT - CPU Interrupt Controller
Table 13-2. Interrupt Priority Levels
Priority
Level
Source
Highest
Non-Maskable Interrupt
Device-dependent and statically assigned
...
Level 1 (high priority)
One vector is optionally user selectable as level 1
Lowest
Level 0 (normal priority)
The remaining interrupt vectors
13.3.2.4.1 Non-Maskable Interrupts
A Non-Maskable Interrupt (NMI) will be executed regardless of the I bit setting in CPU.SREG. An NMI will never
change the I bit. No other interrupt can interrupt an NMI handler. If more than one NMI is requested at the same time,
the priority is static according to the interrupt vector address, where the lowest address has the highest priority.
Which interrupts are non-maskable is device-dependent and not subject to configuration. Non-maskable interrupts
must be enabled before they can be used. Refer to the Interrupt Vector Mapping table of the device for available NMI
sources.
13.3.2.4.2 High-Priority Interrupt
It is possible to assign one interrupt request to level 1 (high priority) by writing its interrupt vector number to the
CPUINT.LVL1VEC register. This interrupt request will have a higher priority than the other (normal priority) interrupt
requests. The priority level 1 interrupts will interrupt the level 0 interrupt handlers.
13.3.2.4.3 Normal-Priority Interrupts
All interrupt vectors other than NMI are assigned to priority level 0 (normal) by default. The user may override this by
assigning one of these vectors as a high-priority vector. The device will have many normal-priority vectors, and some
of these may be pending at the same time. Two different scheduling schemes are available to choose which of the
pending normal-priority interrupts to service first: Static or round robin.
IVEC is the interrupt vector mapping, as listed in the Peripherals and Architecture section. The following sections
use IVEC to explain the scheduling schemes. IVEC0 is the Reset vector, IVEC1 is the NMI vector, and so on. In a
vector table with n+1 elements, the vector with the highest vector number is denoted IVECn. Reset, non-maskable
interrupts, and high-level interrupts are included in the IVEC map, but will always be prioritized over the normalpriority interrupts.
Static Scheduling
If several level 0 interrupt requests are pending at the same time, the one with the highest priority is scheduled for
execution first. The following figure illustrates the default configuration, where the interrupt vector with the lowest
address has the highest priority.
Figure 13-5. Default Static Scheduling
Lowest Address
IVEC 0
Highest Priority
IVEC 1
:
:
:
Highest Address
IVEC n
Lowest Priority
Modified Static Scheduling
The default priority can be changed by writing a vector number to the CPUINT.LVL0PRI register. This vector number
will be assigned the lowest priority. The next interrupt vector in the IVEC will have the highest priority among the LVL0
interrupts, as shown in the following figure.
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CPUINT - CPU Interrupt Controller
Figure 13-6. Static Scheduling when CPUINT.LVL0PRI is Different From Zero
Lowest Address
IVEC 0
RESET
IVEC 1
NMI
:
:
:
IVEC Y
Lowest Priority
IVEC Y+1
Highest Priority
:
:
:
Highest Address
IVEC n
Here, value Y has been written to CPUINT.LVL0PRI, so that interrupt vector Y+1 has the highest priority. Note that, in
this case, the priorities will wrap so that the lowest address no longer has the highest priority. This does not include
RESET and NMI, which will always have the highest priority.
Refer to the interrupt vector mapping of the device for available interrupt requests and their interrupt vector number.
Round Robin Scheduling
The static scheduling may prevent some interrupt requests from being serviced. To avoid this, the CPUINT offers
round robin scheduling for normal-priority (LVL0) interrupts. In the round robin scheduling, the CPUINT.LVL0PRI
register stores the last acknowledged interrupt vector number. This register ensures that the last acknowledged
interrupt vector gets the lowest priority and is automatically updated by the hardware. The following figure illustrates
the priority order after acknowledging IVEC Y and after acknowledging IVEC Y+1.
Figure 13-7. Round Robin Scheduling
IVEC Y was the last acknowledged
interrupt
IVEC Y+1 was the last acknowledged
interrupt
IVEC 0
RESET
IVEC 0
RESET
IVEC 1
NMI
IVEC 1
NMI
:
:
:
:
:
:
IVEC Y
Lowest Priority
IVEC Y
IVEC Y+1
Highest Priority
IVEC Y+1
Lowest Priority
IVEC Y+2
Highest Priority
:
:
:
IVEC n
:
:
:
IVEC n
The round robin scheduling for LVL0 interrupt requests is enabled by writing a ‘1’ to the Round Robin Priority Enable
(LVL0RR) bit in the Control A (CPUINT.CTRLA) register.
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CPUINT - CPU Interrupt Controller
13.3.2.5 Compact Vector Table
The Compact Vector Table (CVT) is a feature to allow writing of compact code by having all level 0 interrupts share
the same interrupt vector number. Thus, the interrupts share the same Interrupt Service Routine (ISR). This reduces
the number of interrupt handlers and thereby frees up memory that can be used for the application code.
When CVT is enabled by writing a ‘1’ to the CVT bit in the Control A (CPUINT.CTRLA) register, the vector table
contains these three interrupt vectors:
1. The non-maskable interrupts (NMI) at vector address 1.
2. The Priority Level 1 (LVL1) interrupt at vector address 2.
3. All priority level 0 (LVL0) interrupts at vector address 3.
This feature is most suitable for devices with limited memory and applications using a small number of interrupt
generators.
13.3.3
Debug Operation
When using a level 1 priority interrupt, it is important to make sure the Interrupt Service Routine is configured
correctly as it may cause the application to be stuck in an interrupt loop with level 1 priority.
By reading the CPUINT STATUS (CPUINT.STATUS) register, it is possible to see if the application has executed the
correct RETI (interrupt return) instruction. The CPUINT.STATUS register contains state information, which ensures
that the CPUINT returns to the correct interrupt level when the RETI instruction is executed at the end of an interrupt
handler. Returning from an interrupt will return the CPUINT to the state it had before entering the interrupt.
13.3.4
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). To write to these registers, a
certain key must first be written to the CPU.CCP register, followed by a write access to the protected bits within four
CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves the
protected register unchanged.
The following registers are under CCP:
Table 13-3. CPUINT - Registers under Configuration Change Protection
Register
Key
IVSEL in CPUINT.CTRLA
IOREG
CVT in CPUINT.CTRLA
IOREG
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CPUINT - CPU Interrupt Controller
13.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
CTRLA
STATUS
LVL0PRI
LVL1VEC
7:0
7:0
7:0
7:0
13.5
7
6
5
IVSEL
CVT
4
3
NMIEX
2
1
0
LVL1EX
LVL0RR
LVL0EX
LVL0PRI[7:0]
LVL1VEC[7:0]
Register Description
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CPUINT - CPU Interrupt Controller
13.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
Configuration Change Protection
6
IVSEL
R/W
0
5
CVT
R/W
0
4
3
2
1
0
LVL0RR
R/W
0
Bit 6 – IVSEL Interrupt Vector Select
This bit is protected by the Configuration Change Protection mechanism.
Value
Description
0
Interrupt vectors are placed after the BOOT section of the Flash(1)
1
Interrupt vectors are placed at the start of the BOOT section of the Flash
Note:
1. When the entire Flash is configured as a BOOT section, this bit will be ignored.
Bit 5 – CVT Compact Vector Table
This bit is protected by the Configuration Change Protection mechanism.
Value
Description
0
Compact Vector Table function is disabled
1
Compact Vector Table function is enabled
Bit 0 – LVL0RR Round Robin Priority Enable
This bit is not protected by the Configuration Change Protection mechanism.
Value
Description
0
Priority is fixed for priority level 0 interrupt requests: The lowest interrupt vector address has the
highest priority.
1
The round robin priority scheme is enabled for priority level 0 interrupt requests
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CPUINT - CPU Interrupt Controller
13.5.2
Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
NMIEX
R
0
STATUS
0x01
0x00
-
6
5
4
3
2
1
LVL1EX
R
0
0
LVL0EX
R
0
Bit 7 – NMIEX Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag is cleared when returning (RETI) from the interrupt
handler.
Bit 1 – LVL1EX Level 1 Interrupt Executing
This flag is set when a priority level 1 interrupt is executing, or when the interrupt handler has been interrupted by an
NMI. The flag is cleared when returning (RETI) from the interrupt handler.
Bit 0 – LVL0EX Level 0 Interrupt Executing
This flag is set when a priority level 0 interrupt is executing, or when the interrupt handler has been interrupted by a
priority level 1 interrupt or an NMI. The flag is cleared when returning (RETI) from the interrupt handler.
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CPUINT - CPU Interrupt Controller
13.5.3
Interrupt Priority Level 0
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
LVL0PRI
0x02
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
LVL0PRI[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LVL0PRI[7:0] Interrupt Priority Level 0
This register is used to modify the priority of the LVL0 interrupts. See the section Normal-Priority Interrupts for more
information.
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CPUINT - CPU Interrupt Controller
13.5.4
Interrupt Vector with Priority Level 1
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
LVL1VEC
0x03
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
LVL1VEC[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LVL1VEC[7:0] Interrupt Vector with Priority Level 1
This bit field contains the number of the single vector with increased priority level 1 (LVL1). If this bit field has the
value 0x00, no vector has LVL1. Consequently, the LVL1 interrupt is disabled.
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EVSYS - Event System
14.
EVSYS - Event System
14.1
Features
•
•
•
•
•
•
•
14.2
System for Direct Peripheral-to-Peripheral Signaling
Peripherals Can Directly Produce, Use and React to Peripheral Events
Short and Predictable Response Time
Up to 8 Parallel Event Channels Available
Each Channel is Driven by One Event Generator and Can Have Multiple Event Users
Events Can be Sent and/or Received by Most Peripherals and by Software
The Event System Works in Active, Idle, and Standby Sleep Modes
Overview
The Event System (EVSYS) enables direct peripheral-to-peripheral signaling. It allows a change in one peripheral
(the event generator) to trigger actions in other peripherals (the event users) through event channels, without
using the CPU. It is designed to provide short and predictable response times between peripherals, allowing for
autonomous peripheral control and interaction, and also for synchronized timing of actions in several peripheral
modules. It is thus a powerful tool for reducing the complexity, size, and execution time of the software.
A change of the event generator's state is referred to as an event and usually corresponds to one of the peripheral's
interrupt conditions. Events can be directly forwarded to other peripherals using the dedicated event routing network.
The routing of each channel is configured in software, including event generation and use.
Only one event signal can be routed on each channel. Multiple peripherals can use events from the same channel.
The EVSYS can directly connect analog-to-digital converters, analog comparators, I/O port pins, real-time counter,
timer/counters, and configurable custom logic peripheral. Events can also be generated from the software.
14.2.1
Block Diagram
Figure 14-1. Block Diagram
Event Channel n
STROBEx[n]
From Event
Generators
.
.
.
0
D QD Q
CLK_PER
CHANNELn
To Channel
MUX for Async
Event User
1
Is
Async?
To Channel
MUX for Sync
Event User
EVOUTx pin
The block diagram shows the operation of an event channel. A multiplexer controlled by Channel n Generator
Selection (EVSYS.CHANNELn) register at the input selects which of the event sources to route onto the event
channel. Each event channel has two subchannels: One asynchronous and one synchronous. A synchronous user
will listen to the synchronous subchannel, and an asynchronous user will listen to the asynchronous subchannel.
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EVSYS - Event System
Before being routed to the synchronous subchannel, an event signal from an asynchronous source will be
synchronized by the Event System. An asynchronous event signal to be used by a synchronous consumer must
last for at least one peripheral clock cycle to ensure that it will propagate through the synchronizer. The synchronizer
will delay, such as an event between two and three clock cycles, depending on when the event occurs.
Figure 14-2. Example of Event Source, Generator, User, and Action
Event Generator
Event User
Timer/Counter
ADC
Compare Match
Channel Sweep
Event
Routing
Network
Over-/Underflow
|
Single
Conversion
Error
Event Action Selection
Event Source
14.2.2
Event Action
Signal Description
Signal
EVOUTx
Type
Digital output
14.3
Functional Description
14.3.1
Initialization
Description
Event output, one output per I/O Port
The Event System, the generating peripheral, and the peripheral(s) using the event must be set up accordingly to
utilize events:
1.
2.
3.
4.
14.3.2
Configure the generating peripheral appropriately. For example, if the generating peripheral is a timer, set the
prescaling, the Compare register, etc., so that the desired event is generated.
Configure the event user peripheral(s) appropriately. For example, if the ADC is the event user, set the ADC
prescaler, resolution, conversion time, etc., as desired, and configure the ADC conversion to start on the
reception of an event.
Configure the Event System to route the desired source. In this case, the Timer/Compare match to the desired
event channel, which may for example, be channel 0, which is accomplished by writing to the Channel 0
Generator Selection (EVSYS.CHANNEL0) register.
Configure the ADC to listen to this channel by writing to the corresponding User x Channel MUX
(EVSYS.USERx) register.
Operation
14.3.2.1 Event User Multiplexer Setup
Each event user has one dedicated event user multiplexer selecting which event channel to listen to. The application
configures these multiplexers by writing to the corresponding EVSYS.USERx register.
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EVSYS - Event System
14.3.2.2 Event System Channel
An event channel can be connected to one of the event generators.
The source for each event channel is configured by writing to the respective Channel n Generator Selection
(EVSYS.CHANNELn) register.
14.3.2.3 Event Generators
Each event channel has several possible event generators, but only one can be selected at a time. The event
generator for a channel is selected by writing to the respective Channel n Generator Selection (EVSYS.CHANNELn)
register. By default, the channels are not connected to any event generator. For details on event generation, refer to
the documentation of the corresponding peripheral.
A generated event is either synchronous or asynchronous to the device peripheral clock (CLK_PER). Asynchronous
events can be generated outside the normal edges of the peripheral clock, making the system respond faster than
the selected clock frequency would suggest. Asynchronous events can also be generated while the device is in a
Sleep mode when the peripheral clock is not running.
Any generated event is classified as either a pulse event or a level event. In both cases, the event can be either
synchronous or asynchronous, with properties according to the table below.
Table 14-1. Properties of Generated Events
Event Type
Pulse
Level
Sync/Async
Description
Sync
An event generated from CLK_PER that lasts one clock cycle
Async
An event generated from a clock other than CLK_PER lasting
one clock cycle
Sync
An event generated from CLK_PER that lasts multiple clock
cycles
Async
An event generated without a clock (for example, a pin or a
comparator), or an event generated from a clock, other than
CLK_PER that lasts multiple clock cycles
The properties of both the generated event and the intended event user must be considered to ensure reliable and
predictable operation.
The table below shows the available event generators for this device family.
Table 14-2. Event Generators
Generator Event
Generating Clock Length of Event
Domain
UPDI
SYNC character
CLK_PDI
Waveform: SYNC char
Synchronizing clock in user
on PDI RX input
must be fast enough to ensure
synchronized to CLK_PDI that the event is seen by the
user
RTC
Overflow
CLK_RTC
Pulse: 1 * CLK_RTC
Compare Match
CLK_RTC
Pulse: 1 * CLK_RTC
PIT
RTC Prescaled clock CLK_RTC
Level
CCL-LUT
LUT output
Depends on CCL
configuration
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Asynchronous
Complete Datasheet
Constraints for Synchronous
User
None
The clock source used for CCL
must be slower or equal to
CLK_PER or input signals to
CCL are stable for at least
Tclk_per
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EVSYS - Event System
...........continued
Generator Event
Generating Clock Length of Event
Domain
Constraints for Synchronous
User
AC
Comparator result
Asynchronous
Level: Typically ≥1 us
The frequency of input signals
to AC must be ≤fclk_per to
ensure that the event is seen
by the synchronous user
ADC
Result ready
CLK_ADC
Pulse: 1 * CLK_PER
None
PORT
Pin input
Asynchronous
Level: Externally
controlled
The input signal must be stable
for longer than fclk_per
USART
USART Baud clock
TXCLK
Level
None
SPI
SPI Host clock
SCK
Level
None
TCA
Overflow
CLK_PER
Pulse: 1 * CLK_PER
None
Underflow in split
mode
CLK_PER
Pulse: 1 * CLK_PER
Compare match ch 0 CLK_PER
Pulse: 1 * CLK_PER
Compare match ch 1 CLK_PER
Pulse: 1 * CLK_PER
Compare match ch 2 CLK_PER
Pulse: 1 * CLK_PER
CAPT interrupt flag
set
Pulse: 1 * CLK_PER
TCB
CLK_PER
None
14.3.2.4 Event Users
The event channel to listen to is selected by configuring the event user. An event user may require the event signal to
be either synchronous or asynchronous to the peripheral clock. An asynchronous event user can respond to events
in Sleep modes when clocks are not running. Such events can be responded to outside the normal edges of the
peripheral clock, making the event user respond faster than the clock frequency would suggest. For details on the
requirements of each peripheral, refer to the documentation of the corresponding peripheral.
Most event users implement edge or level detection to trigger actions in the corresponding peripheral based on the
incoming event signal. In both cases, a user can either be synchronous, which requires that the incoming event is
generated from the peripheral clock (CLK_PER), or asynchronous, if not. Some asynchronous event users do not
apply event input detection but use the event signal directly.
The different event user properties are described in the table below.
Table 14-3. Properties of Event Users
Input Detection
Edge
Level
No detection
Async/Sync
Description
Sync
An event user is triggered by an event edge and requires that the
incoming event is generated from CLK_PER
Async
An event user is triggered by an event edge and has
asynchronous detection or an internal synchronizer
Sync
An event user is triggered by an event level and requires that the
incoming event is generated from CLK_PER
Async
An event user is triggered by an event level and has
asynchronous detection or an internal synchronizer
Async
An event user will use the event signal directly
The table below shows the available event users for this device family.
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EVSYS - Event System
Table 14-4. Event Users
User
Module/Event Mode
Input Format
Asynchronous
TCAn
CNT_POSEDGE
Edge
No
CNT_ANYEDGE
Edge
No
CNT_HIGHLVL
Level
No
UPDOWN
Level
No
Time-out check
Edge
No
Input Capture on Event
Edge
No
Input Capture Frequency Measurement
Edge
No
Input Capture Pulse-Width Measurement
Edge
No
Input Capture Frequency and Pulse Width Measurement
Edge
No
Single-Shot
Edge
Yes
USARTn
IrDA Mode
Level
No
CCLLUTnx
LUTn input x or clock signal
Level
Yes
ADCn
ADC start on event
Edge
Yes
EVOUTx
Forward event signal to pin
Level
Yes
TCBn
14.3.2.5 Synchronization
Events can be either synchronous or asynchronous to the peripheral clock. Each Event System channel has two
subchannels: One asynchronous and one synchronous.
The asynchronous subchannel is identical to the event output from the generator. If the event generator generates a
signal asynchronous to the peripheral clock, the signal on the asynchronous subchannel will be asynchronous. If the
event generator generates a signal synchronous to the peripheral clock, the signal on the asynchronous subchannel
will also be synchronous.
The synchronous subchannel is identical to the event output from the generator if the event generator generates a
signal that is synchronous to the peripheral clock. If the event generator generates a signal that is asynchronous
to the peripheral clock, this signal is first synchronized before being routed onto the synchronous subchannel.
Depending on when it occurs, synchronization will delay the event by two to three clock cycles. The Event System
automatically performs this synchronization if an asynchronous generator is selected for an event channel.
14.3.2.6 Software Event
The application can generate a software event. Software events on Channel n are issued by writing a ‘1’ to the
STROBE[n] bit in the EVSYS.STROBEx register. A software event appears as a pulse on the Event System channel,
inverting the current event signal for one clock cycle.
Event users see software events as no different from those produced by event generating peripherals.
14.3.3
Sleep Mode Operation
When configured, the Event System will work in all sleep modes. Software events represent one exception since they
require a peripheral clock.
Asynchronous event users can respond to an event without their clock running in Standby sleep mode. Synchronous
event users require their clock to be running to be able to respond to events. Such users will only work in Idle sleep
mode or Standby sleep mode, if configured to run in Standby mode by setting the RUNSTDBY bit in the appropriate
register.
Asynchronous event generators can generate an event without their clock running, that is, in Standby sleep mode.
Synchronous event generators require their clock to be running to be able to generate events. Such generators will
only work in Idle sleep mode or Standby sleep mode, if configured to run in Standby mode by setting the RUNSTDBY
bit in the appropriate register.
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EVSYS - Event System
14.3.4
Debug Operation
This peripheral is unaffected by entering Debug mode.
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EVSYS - Event System
14.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
...
0x1F
0x20
...
0x37
STROBEx
7:0
STROBE[7:0]
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
GENERATOR[7:0]
GENERATOR[7:0]
GENERATOR[7:0]
GENERATOR[7:0]
GENERATOR[7:0]
GENERATOR[7:0]
GENERATOR[7:0]
GENERATOR[7:0]
USER0
7:0
CHANNEL[7:0]
USER23
7:0
CHANNEL[7:0]
14.5
7
6
5
4
3
2
1
0
Reserved
CHANNEL0
CHANNEL1
CHANNEL2
CHANNEL3
CHANNEL4
CHANNEL5
CHANNEL6
CHANNEL7
Reserved
Register Description
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EVSYS - Event System
14.5.1
Channel Strobe
Name:
Offset:
Reset:
Property:
STROBEx
0x00
0x00
-
Software Events
Write bits in this register to create software events.
Refer to the Peripheral Overview section for the available number of Event System channels.
Bit
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
STROBE[7:0]
Access
Reset
W
0
W
0
W
0
W
0
Bits 7:0 – STROBE[7:0] Channel Strobe
If the strobe (EVSYS.STROBEx) register location is written, each event channel will be inverted for one peripheral
clock cycle (i.e., a single event is generated).
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EVSYS - Event System
14.5.2
Channel n Generator Selection
Name:
Offset:
Reset:
Property:
CHANNEL
0x10 + n*0x01 [n=0..7]
0x00
-
Each channel can be connected to one event generator. Not all generators can be connected to all channels. Refer
to the table below to see which generator sources can be routed onto each channel and the generator value to
be written to EVSYS.CHANNELn to achieve this routing. Writing the value 0x00 to EVSYS.CHANNELn turns the
channel off.
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
GENERATOR[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – GENERATOR[7:0] Channel Generator Selection
GENERATOR
binary
INPUT
Async/Sync
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
hex
0000_0001
0x01
UPDI
Sync
0000_0110
0x06
RTC_OVF
Async
UPDI
OVF
0000_0111
0x07
RTC_CMP
Async
CMP
0000_1000
0x08
RTC_PIT0
Async
DIV8192
DIV512
DIV8192
DIV512
DIV8192
DIV512
DIV8192
DIV512
0000_1001
0x09
RTC_PIT1
Async
DIV4096
DIV256
DIV4096
DIV256
DIV4096
DIV256
DIV4096
DIV256
0000_1010
0x0A
RTC_PIT2
Async
DIV2048
DIV128
DIV2048
DIV128
DIV2048
DIV128
DIV2048
DIV128
0000_1011
0x0B
RTC_PIT3
Async
DIV1024
DIV64
DIV1024
DIV64
DIV1024
DIV64
DIV1024
DIV64
0001_00nn
0x10-0x13
CCL_LUTn
Async
LUTn
0010_0000
0x20
AC0
Async
OUT
0010_0100
0x24
ADC0
Sync
RESRDY
0100_0nnn
0x40-0x47
PORT0_PINn
Async
PORTA_PINn
PORTC_PINn
0100_1nnn
0x48-0x4F
PORT1_PINn
Async
PORTB_PINn
PORTD_PINn
PORTE_PINn
0110_0nnn
0x60-0x67
USARTn
Sync
0110_1000
0x68
SPI0
Sync
SCK
1000_0000
0x80
TCA0_OVF_LUNF
Sync
OVF/LUNF
PORTF_PINn
XCK
1000_0001
0x81
TCA0_HUNF
Sync
HUNF
1000_0100
0x84
TCA0_CMP0
Sync
CMP0
1000_0101
0x85
TCA0_CMP1
Sync
CMP1
1000_0110
0x86
TCA0_CMP2
Sync
CMP2
1010_nnn0
0xA0-0xAE
TCBn
Sync
CAPT
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EVSYS - Event System
14.5.3
User Channel Mux
Name:
Offset:
Reset:
Property:
USER
0x20 + n*0x01 [n=0..23]
0x00
-
Each event user can be connected to one channel, and several users can be connected to the same channel. The
following table lists all Event System users with their corresponding user ID number and name. This ID number
corresponds to the USER register index, e.g., the EVSYS.USER2 register controls the user with ID 2.
Bit
Access
Reset
USER #
User Name
Async/Sync
Description
0
CCLLUT0A
Async
CCL LUT0 event input A
1
CCLLUT0B
Async
CCL LUT0 event input B
2
CCLLUT1A
Async
CCL LUT1 event input A
3
CCLLUT1B
Async
CCL LUT1 event input B
4
CCLLUT2A
Async
CCL LUT2 event input A
5
CCLLUT2B
Async
CCL LUT2 event input B
6
CCLLUT3A
Async
CCL LUT3 event input A
7
CCLLUT3B
Async
CCL LUT3 event input B
8
ADC0
Async
ADC0 Trigger
9
EVOUTA
Async
EVSYS pin output A
10
EVOUTB
Async
EVSYS pin output B
11
EVOUTC
Async
EVSYS pin output C
12
EVOUTD
Async
EVSYS pin output D
13
EVOUTE
Async
EVSYS pin output E
14
EVOUTF
Async
EVSYS pin output F
15
USART0
Sync
USART0 event input
16
USART1
Sync
USART1 event input
17
USART2
Sync
USART2 event input
18
USART3
Sync
USART3 event input
19
TCA0
Sync
TCA0 event input
20
TCB0
Both
TCB0 event input
21
TCB1
Both
TCB1 event input
22
TCB2
Both
TCB2 event input
23
TCB3
Both
TCB3 event input
7
6
5
R/W
0
R/W
0
R/W
0
4
3
CHANNEL[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CHANNEL[7:0] User Channel Selection
Describes which Event System channel the user is connected to.
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EVSYS - Event System
Value
0
n
Description
OFF, no channel is connected to this Event System user
Event user is connected to CHANNEL(n-1)
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PORTMUX - Port Multiplexer
15.
PORTMUX - Port Multiplexer
15.1
Overview
The Port Multiplexer (PORTMUX) can either enable or disable functionality of pins, or change between default and
alternative pin positions. Available options are described in detail in the PORTMUX register map and depend on the
actual pin and its properties.
For available pins and functionalities, refer to the “I/O Multiplexing and Considerations” section.
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PORTMUX - Port Multiplexer
15.2
Register Summary - PORTMUX
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
EVSYSROUTEA
CCLROUTEA
USARTROUTEA
TWISPIROUTEA
TCAROUTEA
TCBROUTEA
7:0
7:0
7:0
7:0
7:0
7:0
15.3
7
6
USART3[1:0]
5
4
EVOUTF
EVOUTE
USART2[1:0]
TWI0[1:0]
3
2
EVOUTD
EVOUTC
LUT3
LUT2
USART1[1:0]
TCB3
TCB2
1
0
EVOUTB
EVOUTA
LUT1
LUT0
USART0[1:0]
SPI0[1:0]
TCA0[2:0]
TCB1
TCB0
Register Description
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PORTMUX - Port Multiplexer
15.3.1
PORTMUX Control for Event System
Name:
Offset:
Reset:
Property:
Bit
7
EVSYSROUTEA
0x00
0x00
-
6
Access
Reset
5
EVOUTF
R/W
0
4
EVOUTE
R/W
0
3
EVOUTD
R/W
0
2
EVOUTC
R/W
0
1
EVOUTB
R/W
0
0
EVOUTA
R/W
0
Bit 5 – EVOUTF Event Output F
Write this bit to ‘1’ to select alternative pin location for Event Output F.
Value
Name
Description
0x0
DEFAULT
EVOUTF on PF2
0x1
Reserved
Bit 4 – EVOUTE Event Output E
Write this bit to ‘1’ to select alternative pin location for Event Output E.
Value
Name
Description
0x0
DEFAULT
EVOUTE on PE2
0x1
Reserved
Bit 3 – EVOUTD Event Output D
Write this bit to ‘1’ to select alternative pin location for Event Output D.
Value
Name
Description
0x0
DEFAULT
EVOUTD on PD2
0x1
ALT1
EVOUTD on PD7
Bit 2 – EVOUTC Event Output C
Write this bit to ‘1’ to select alternative pin location for Event Output C.
Value
Name
Description
0x0
DEFAULT
EVOUTC on PC2
0x1
ALT1
EVOUTC on PC7
Bit 1 – EVOUTB Event Output A
Write this bit to ‘1’ to select alternative pin location for Event Output B.
Value
Name
Description
0x0
DEFAULT
EVOUTB on PB2
0x1
Reserved
Bit 0 – EVOUTA Event Output A
Write this bit to ‘1’ to select alternative pin location for Event Output A.
Value
Name
Description
0x0
DEFAULT
EVOUTA on PA2
0x1
ALT1
EVOUTA on PA7
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PORTMUX - Port Multiplexer
15.3.2
PORTMUX Control for CCL
Name:
Offset:
Reset:
Property:
Bit
7
CCLROUTEA
0x01
0x00
-
6
Access
Reset
5
4
3
LUT3
R/W
0
2
LUT2
R/W
0
1
LUT1
R/W
0
0
LUT0
R/W
0
Bit 3 – LUT3 CCL LUT 3 Output
Write this bit to ‘1’ to select alternative pin location for CCL LUT 3.
Value
Name
Description
0x0
DEFAULT
CCL LUT3 on PF[3]
0x1
ALT1
CCL LUT3 on PF[6]
Bit 2 – LUT2 CCL LUT 2 Output
Write this bit to ‘1’ to select alternative pin location for CCL LUT 2.
Value
Name
Description
0x0
DEFAULT
CCL LUT2 on PD[3]
0x1
ALT1
CCL LUT2 on PD[6]
Bit 1 – LUT1 CCL LUT 1 Output
Write this bit to ‘1’ to select alternative pin location for CCL LUT 1.
Value
Name
Description
0x0
DEFAULT
CCL LUT1 on PC[3]
0x1
ALT1
CCL LUT1 on PC[6]
Bit 0 – LUT0 CCL LUT 0 Output
Write this bit to ‘1’ to select alternative pin location for CCL LUT 0.
Value
Name
Description
0x0
DEFAULT
CCL LUT0 on PA[3]
0x1
ALT1
CCL LUT0 on PA[6]
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PORTMUX - Port Multiplexer
15.3.3
PORTMUX Control for USART
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
USARTROUTEA
0x02
0x00
-
7
6
USART3[1:0]
R/W
R/W
0
0
5
4
USART2[1:0]
R/W
R/W
0
0
3
2
USART1[1:0]
R/W
R/W
0
0
1
0
USART0[1:0]
R/W
R/W
0
0
Bits 7:6 – USART3[1:0] USART 3 Communication
Write these bits to select alternative communication pins for USART 3.
Value
Name
Description
0x0
DEFAULT
USART3 on PB[3:0]
0x1
ALT1
USART3 on PB[5:4]
0x2
Reserved
0x3
NONE
Not connected to any pins
Bits 5:4 – USART2[1:0] USART 2 Communication
Write these bits to select alternative communication pins for USART 2.
Value
Name
Description
0x0
DEFAULT
USART2 on PF[3:0]
0x1
ALT1
USART2 on PF[6:4]
0x2
Reserved
0x3
NONE
Not connected to any pins
Bits 3:2 – USART1[1:0] USART 1 Communication
Write these bits to select alternative communication pins for USART 1.
Value
Name
Description
0x0
DEFAULT
USART1 on PC[3:0]
0x1
ALT1
USART1 on PC[7:4]
0x2
Reserved
0x3
NONE
Not connected to any pins
Bits 1:0 – USART0[1:0] USART 0 Communication
Write these bits to select alternative communication pins for USART 0.
Value
Name
Description
0x0
DEFAULT
USART0 on PA[3:0]
0x1
ALT1
USART0 on PA[7:4]
0x2
Reserved
0x3
NONE
Not connected to any pins
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PORTMUX - Port Multiplexer
15.3.4
PORTMUX Control for TWI and SPI
Name:
Offset:
Reset:
Property:
Bit
7
TWISPIROUTEA
0x03
0x00
-
6
5
4
3
2
1
0
TWI0[1:0]
Access
Reset
R/W
0
SPI0[1:0]
R/W
0
R/W
0
R/W
0
Bits 5:4 – TWI0[1:0] TWI 0 Communication
Write these bits to select alternative communication pins for TWI 0.
Value
Name
Description
0x0
DEFAULT
SCL/SDA on PA[3:2], Client mode on PC[3:2] in dual TWI mode
0x1
ALT1
SCL/SDA on PA[3:2], Client mode on PF[3:2] in dual TWI mode
0x2
ALT2
SCL/SDA on PC[3:2], Client mode on PF[3:2] in dual TWI mode
0x3
Reserved
Bits 1:0 – SPI0[1:0] SPI 0 Communication
Write these bits to select alternative communication pins for SPI 0.
Value
Name
Description
0x0
DEFAULT
SPI on PA[7:4]
0x1
ALT1
SPI on PC[3:0]
0x2
ALT2
SPI on PE[3:0]
0x3
NONE
Not connected to any pins
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PORTMUX - Port Multiplexer
15.3.5
PORTMUX Control for TCA
Name:
Offset:
Reset:
Property:
Bit
7
TCAROUTEA
0x04
0x00
-
6
5
4
3
Access
Reset
2
R/W
0
1
TCA0[2:0]
R/W
0
0
R/W
0
Bits 2:0 – TCA0[2:0] TCA0 Output
Write these bits to select alternative output pins for TCA0.
Value
Name
Description
0x0
PORTA
TCA0 pins on PA[5:0]
0x1
PORTB
TCA0 pins on PB[5:0]
0x2
PORTC
TCA0 pins on PC[5:0]
0x3
PORTD
TCA0 pins on PD[5:0]
0x4
PORTE
TCA0 pins on PE[5:0]
0x5
PORTF
TCA0 pins on PF[5:0]
Other
Reserved
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PORTMUX - Port Multiplexer
15.3.6
PORTMUX Control for TCB
Name:
Offset:
Reset:
Property:
Bit
7
TCBROUTEA
0x05
0x00
-
6
Access
Reset
5
4
3
TCB3
R/W
0
2
TCB2
R/W
0
1
TCB1
R/W
0
0
TCB0
R/W
0
Bit 3 – TCB3 TCB3 Output
Write this bit to ‘1’ to select alternative output pin for 16-bit timer/counter B 3.
Value
Name
Description
0x0
DEFAULT
TCB3 on PB5
0x1
ALT1
TCB3 on PC1
Bit 2 – TCB2 TCB2 Output
Write this bit to ‘1’ to select alternative output pin for 16-bit timer/counter B 2.
Value
Name
Description
0x0
DEFAULT
TCB2 on PC0
0x1
ALT1
TCB2 on PB4
Bit 1 – TCB1 TCB1 Output
Write this bit to ‘1’ to select alternative output pin for 16-bit timer/counter B 1.
Value
Name
Description
0x0
DEFAULT
TCB1 on PA3
0x1
ALT1
TCB1 on PF5
Bit 0 – TCB0 TCB0 Output
Write this bit to ‘1’ to select alternative output pin for 16-bit timer/counter B 0.
Value
Name
Description
0x0
DEFAULT
TCB0 on PA2
0x1
ALT1
TCB0 on PF4
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PORT - I/O Pin Configuration
16.
PORT - I/O Pin Configuration
16.1
Features
•
•
•
•
•
16.2
General Purpose Input and Output Pins with Individual Configuration:
– Pull-up
– Inverted I/O
Interrupts and Events:
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
Optional Slew Rate Control per I/O Port
Asynchronous Pin Change Sensing that Can Wake the Device From all Sleep Modes
Efficient and Safe Access to Port Pins
– Hardware Read-Modify-Write (RMW) through dedicated toggle/clear/set registers
– Mapping of often-used PORT registers into bit-accessible I/O memory space (virtual ports)
Overview
The I/O pins of the device are controlled by instances of the PORT peripheral registers. Each PORT instance
has up to eight I/O pins. The PORTs are named PORTA, PORTB, PORTC, etc. Refer to the I/O Multiplexing and
Considerations section to see which pins are controlled by what instance of PORT. The base addresses of the PORT
instances and the corresponding Virtual PORT instances are listed in the Peripherals and Architecture section.
Each PORT pin has a corresponding bit in the Data Direction (PORTx.DIR) and Data Output Value (PORTx.OUT)
registers to enable that pin as an output and to define the output state. For example, pin PA3 is controlled by DIR[3]
and OUT[3] of the PORTA instance.
The input value of a PORT pin is synchronized to the Peripheral Clock (CLK_PER) and then made accessible as the
data input value (PORTx.IN). The value of the pin can be read whether the pin is configured as input or output.
The PORT also supports asynchronous input sensing with interrupts and events for selectable pin change conditions.
Asynchronous pin change sensing means that a pin change can trigger an interrupt and wake the device from sleep,
including sleep modes where CLK_PER is stopped.
All pin functions are individually configurable per pin. The pins have hardware Read-Modify-Write functionality for a
safe and correct change of the drive values and/or input and sense configuration.
The PORT pin configuration controls input and output selection of other device functions.
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PORT - I/O Pin Configuration
16.2.1
Block Diagram
Figure 16-1. PORT Block Diagram
Pull-up Enable
DIRn
Q
D
Peripheral Override
R
OUTn
Q
D
Pxn
Peripheral Override
R
Invert Enable
Synchronizer
INn
Synchronous
Input
Q
D Q
R
D
R
Sense Configuration
Interrupt
Generator
Interrupt
Asynchronous
Input/Event
Input Disable
Peripheral Override
Analog
Input/Output
16.2.2
Signal Description
Signal
Type
Description
Pxn
I/O pin
I/O pin n on PORTx
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PORT - I/O Pin Configuration
16.3
Functional Description
16.3.1
Initialization
After Reset, all outputs are tri-stated, and digital input buffers enabled even if there is no clock running.
The following steps are all optional when initializing PORT operation:
•
•
•
•
Enable or disable the output driver for pin Pxn by respectively writing ‘1’ to bit n in the PORTx.DIRSET or
PORTx.DIRCLR register
Set the output driver for pin Pxn to high or low level respectively by writing ‘1’ to bit n in the PORTx.OUTSET or
PORTx.OUTCLR register
Read the input of pin Pxn by reading bit n in the PORTx.IN register
Configure the individual pin configurations and interrupt control for pin Pxn in PORTx.PINnCTRL
Important: For lowest power consumption, disable the digital input buffer of unused pins and pins that
are used as analog inputs or outputs.
Specific pins, such as those used to connect a debugger, may be configured differently, as required by their special
function.
16.3.2
Operation
16.3.2.1 Basic Functions
Each pin group x has its own set of PORT registers. I/O pin Pxn can be controlled by the registers in PORTx.
To use pin number n as an output, write bit n of the PORTx.DIR register to ‘1’. This can be done by writing bit n in the
PORTx.DIRSET register to ‘1’, which will avoid disturbing the configuration of other pins in that group. The nth bit in
the PORTx.OUT register must be written to the desired output value.
Similarly, writing a PORTx.OUTSET bit to ‘1’ will set the corresponding bit in the PORTx.OUT register to ‘1’. Writing a
bit in PORTx.OUTCLR to ‘1’ will clear that bit in PORTx.OUT to ‘0’. Writing a bit in PORTx.OUTTGL or PORTx.IN to
‘1’ will toggle that bit in PORTx.OUT.
To use pin n as an input, bit n in the PORTx.DIR register must be written to ‘0’ to disable the output driver. This can
be done by writing bit n in the PORTx.DIRCLR register to ‘1’, which will avoid disturbing the configuration of other
pins in that group. The input value can be read from bit n in the PORTx.IN register as long as the ISC bit is not set to
INPUT_DISABLE.
Writing a bit to ‘1’ in PORTx.DIRTGL will toggle that bit in PORTx.DIR and toggle the direction of the corresponding
pin.
16.3.2.2 Port Configuration
The Port Control (PORTx.PORTCTRL) register is used to configure the slew rate limitation for all the PORTx pins.
The slew rate limitation is enabled by writing a ‘1’ to the Slew Rate Limit Enable (SLR) bit in PORTx.PORTCTRL.
Refer to the Electrical Characteristics section for further details.
16.3.2.3 Pin Configuration
The Pin n Control (PORTx.PINnCTRL) register is used to configure inverted I/O, pull-up, and input sensing of a pin.
The control register for pin n is at the byte address PORTx + 0x10 + n.
All input and output on the respective pin n can be inverted by writing a ‘1’ to the Inverted I/O Enable (INVEN)
bit in PORTx.PINnCTRL. When INVEN is ‘1’, the PORTx.IN/OUT/OUTSET/OUTTGL registers will have an inverted
operation for this pin.
Toggling the INVEN bit causes an edge on the pin, which can be detected by all peripherals using this pin, and is
seen by interrupts or events if enabled.
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PORT - I/O Pin Configuration
The input pull-up of pin n is enabled by writing a ‘1’ to the Pull-up Enable (PULLUPEN) bit in PORTx.PINnCTRL. The
pull-up is disconnected when the pin is configured as an output, even if PULLUPEN is ‘1’.
Pin interrupts can be enabled for pin n by writing to the Input/Sense Configuration (ISC) bit field in
PORTx.PINnCTRL. Refer to 16.3.3 Interrupts for further details.
The digital input buffer for pin n can be disabled by writing the INPUT_DISABLE setting to ISC. This can reduce
power consumption and may reduce noise if the pin is used as analog input. While configured to INPUT_DISABLE,
bit n in PORTx.IN will not change since the input synchronizer is disabled.
16.3.2.4 Virtual Ports
The Virtual PORT registers map the most frequently used regular PORT registers into the I/O Register space with
single-cycle bit access. Access to the Virtual PORT registers has the same outcome as access to the regular
registers but allows for memory specific instructions, such as bit manipulation instructions, which cannot be used in
the extended I/O Register space where the regular PORT registers reside. The following table shows the mapping
between the PORT and VPORT registers.
Table 16-1. Virtual Port Mapping
Regular PORT Register
Mapped to Virtual PORT Register
PORTx.DIR
VPORTx.DIR
PORTx.OUT
VPORTx.OUT
PORTx.IN
VPORTx.IN
PORTx.INTFLAGS
VPORTx.INTFLAGS
16.3.2.5 Peripheral Override
Peripherals such as USARTs, ADCs and timers may be connected to I/O pins. Such peripherals will usually have
a primary and, optionally, one or more alternate I/O pin connections, selectable by PORTMUX or a multiplexer
inside the peripheral. By configuring and enabling such peripherals, the general purpose I/O pin behavior normally
controlled by PORT will be overridden in a peripheral dependent way. Some peripherals may not override all the
PORT registers, leaving the PORT module to control some aspects of the I/O pin operation.
Refer to the description of each peripheral for information on the peripheral override. Any pin in a PORT that is not
overridden by a peripheral will continue to operate as a general purpose I/O pin.
16.3.3
Interrupts
Table 16-2. Available Interrupt Vectors and Sources
Name
Vector Description Conditions
PORTx PORT interrupt
INTn in PORTx.INTFLAGS is raised as configured by the Input/Sense Configuration
(ISC) bit in PORTx.PINnCTRL
Each PORT pin n can be configured as an interrupt source. Each interrupt can be individually enabled or disabled by
writing to ISC in PORTx.PINnCTRL.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for
details on how to clear interrupt flags.
When setting or changing interrupt settings, take these points into account:
• If an Inverted I/O Enable (INVEN) bit is toggled in the same cycle as ISC is changed, the edge caused by the
inversion toggling may not cause an interrupt request
• If an input is disabled by writing to ISC while synchronizing an interrupt, that interrupt may be requested on
re-enabling the input, even if it is re-enabled with a different interrupt setting
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PORT - I/O Pin Configuration
•
If the interrupt setting is changed by writing to ISC while synchronizing an interrupt, that interrupt may not be
requested
16.3.3.1 Asynchronous Sensing Pin Properties
All PORT pins support asynchronous input sensing with interrupts for selectable pin change conditions. Fully
asynchronous pin change sensing can trigger an interrupt and wake the device from all sleep modes, including
modes where the Peripheral Clock (CLK_PER) is stopped, while partially asynchronous pin change sensing is limited
as per the table below. See the I/O Multiplexing and Considerations section for further details on which pins support
fully asynchronous pin change sensing.
Table 16-3. Behavior Comparison of Sense Pins
Property
Partially Asynchronous Pins
Waking the device from sleep
modes with CLK_PER running
From all interrupt sense configurations
Waking the device from sleep
modes with CLK_PER stopped
Only from BOTHEDGES or LEVEL
interrupt sense configurations
Minimum pulse-width to trigger an
interrupt with CLK_PER running
Minimum one CLK_PER cycle
Minimum pulse-width to trigger an
interrupt with CLK_PER stopped
The pin value must be kept until
CLK_PER has restarted(1)
Interrupt “dead-time”
No new interrupt for three CLK_PER
cycles after the previous
Fully Asynchronous Pins
From all interrupt sense
configurations
Less than one CLK_PER cycle
Note:
1. If a partially asynchronous input pin is used for wake-up from sleep with CLK_PER stopped, the required level
must be held long enough for the MCU to complete the wake-up to trigger the interrupt. If the level disappears,
the MCU can wake up without any interrupt generated.
16.3.4
Events
PORT can generate the following events:
Table 16-4. Event Generators in PORTx
Generator Name
Peripheral
Event
PORTx
PINn
Description
Event Type
Generating Clock Domain
Length of Event
Pin level
Level
Asynchronous
Given by pin level
All PORT pins are asynchronous event system generators. PORT has as many event generators as there are PORT
pins in the device. Each event system output from PORT is the value present on the corresponding pin if the digital
input buffer is enabled. If a pin input buffer is disabled, the corresponding event system output is zero.
PORT has no event inputs. Refer to the Event System (EVSYS) section for more details regarding event types and
Event System configuration.
16.3.5
Sleep Mode Operation
Except for interrupts and input synchronization, all pin configurations are independent of sleep modes. All pins can
wake the device from sleep, see the PORT Interrupt section for further details.
Peripherals connected to the PORTs can be affected by sleep modes, described in the respective peripherals’ data
sheet section.
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PORT - I/O Pin Configuration
Important: The PORTs will always use the Peripheral Clock (CLK_PER). Input synchronization will halt
when this clock stops.
16.3.6
Debug Operation
When the CPU is halted in Debug mode, the PORT continues normal operation. If the PORT is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
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PORT - I/O Pin Configuration
16.4
Register Summary - PORTx
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
...
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
DIR
DIRSET
DIRCLR
DIRTGL
OUT
OUTSET
OUTCLR
OUTTGL
IN
INTFLAGS
PORTCTRL
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
16.5
7
6
5
4
3
2
1
0
DIR[7:0]
DIRSET[7:0]
DIRCLR[7:0]
DIRTGL[7:0]
OUT[7:0]
OUTSET[7:0]
OUTCLR[7:0]
OUTTGL[7:0]
IN[7:0]
INT[7:0]
SRL
Reserved
PIN0CTRL
PIN1CTRL
PIN2CTRL
PIN3CTRL
PIN4CTRL
PIN5CTRL
PIN6CTRL
PIN7CTRL
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
Register Description - PORTx
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ATmega808/809/1608/1609
PORT - I/O Pin Configuration
16.5.1
Data Direction
Name:
Offset:
Reset:
Property:
Bit
7
DIR
0x00
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DIR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIR[7:0] Data Direction
This bit field controls the output driver for each PORTx pin.
This bit field does not control the digital input buffer. The digital input buffer for pin n (Pxn) can be configured in the
Input/Sense Configuration (ISC) bit field in the Pin n Control (PORTx.PINnCTRL) register.
The available configuration for each bit n in this bit field is shown in the table below.
Value
Description
0
Pxn is configured as an input-only pin, and the output driver is disabled
1
Pxn is configured as an output pin, and the output driver is enabled
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PORT - I/O Pin Configuration
16.5.2
Data Direction Set
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
DIRSET
0x01
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
DIRSET[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIRSET[7:0] Data Direction Set
This bit field controls the output driver for each PORTx pin, without using a read-modify-write operation.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will set the corresponding bit in PORTx.DIR, which will configure pin n (Pxn) as an
output pin and enable the output driver.
Reading this bit field will return the value of PORTx.DIR.
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PORT - I/O Pin Configuration
16.5.3
Data Direction Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
DIRCLR
0x02
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
DIRCLR[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIRCLR[7:0] Data Direction Clear
This bit field controls the output driver for each PORTx pin, without using a read-modify-write operation.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will clear the corresponding bit in PORTx.DIR, which will configure pin n (Pxn) as
an input-only pin and disable the output driver.
Reading this bit field will return the value of PORTx.DIR.
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PORT - I/O Pin Configuration
16.5.4
Data Direction Toggle
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
DIRTGL
0x03
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
DIRTGL[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIRTGL[7:0] Data Direction Toggle
This bit field controls the output driver for each PORTx pin, without using a read-modify-write operation.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will toggle the corresponding bit in PORTx.DIR.
Reading this bit field will return the value of PORTx.DIR.
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PORT - I/O Pin Configuration
16.5.5
Output Value
Name:
Offset:
Reset:
Property:
Bit
7
OUT
0x04
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
OUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUT[7:0] Output Value
This bit field controls the output driver level for each PORTx pin.
This configuration only has an effect when the output driver (PORTx.DIR) is enabled for the corresponding pin.
The available configuration for each bit n in this bit field is shown in the table below.
Value
Description
0
The pin n (Pxn) output is driven low
1
The Pxn output is driven high
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PORT - I/O Pin Configuration
16.5.6
Output Value Set
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
OUTSET
0x05
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
OUTSET[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUTSET[7:0] Output Value Set
This bit field controls the output driver level for each PORTx pin, without using a read-modify-write operation.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will set the corresponding bit in PORTx.OUT, which will configure the output for pin
n (Pxn) to be driven high.
Reading this bit field will return the value of PORTx.OUT.
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PORT - I/O Pin Configuration
16.5.7
Output Value Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
OUTCLR
0x06
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
OUTCLR[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUTCLR[7:0] Output Value Clear
This bit field controls the output driver level for each PORTx pin, without using a read-modify-write operation.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will clear the corresponding bit in PORTx.OUT, which will configure the output for
pin n (Pxn) to be driven low.
Reading this bit field will return the value of PORTx.OUT.
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PORT - I/O Pin Configuration
16.5.8
Output Value Toggle
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
OUTTGL
0x07
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
OUTTGL[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUTTGL[7:0] Output Value Toggle
This bit field controls the output driver level for each PORTx pin, without using a read-modify-write operation.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will toggle the corresponding bit in PORTx.OUT.
Reading this bit field will return the value of PORTx.OUT.
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PORT - I/O Pin Configuration
16.5.9
Input Value
Name:
Offset:
Reset:
Property:
Bit
7
IN
0x08
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – IN[7:0] Input Value
This bit field shows the state of the PORTx pins when the digital input buffer is enabled.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will toggle the corresponding bit in PORTx.OUT.
If the digital input buffer is disabled, the input is not sampled, and the bit value will not change. The digital input
buffer for pin n (Pxn) can be configured in the Input/Sense Configuration (ISC) bit field in the Pin n Control
(PORTx.PINnCTRL) register.
The available states of each bit n in this bit field is shown in the table below.
Value
Description
0
The voltage level on Pxn is low
1
The voltage level on Pxn is high
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PORT - I/O Pin Configuration
16.5.10 Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x09
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
INT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – INT[7:0] Pin Interrupt Flag
Pin interrupt flag n is cleared by writing a ‘1’ to it.
Pin interrupt flag n is set when the change or state of pin n (Pxn) matches the pin's Input/Sense Configuration (ISC)
in PORTx.PINnCTRL.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will clear Pin interrupt flag n.
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PORT - I/O Pin Configuration
16.5.11 Port Control
Name:
Offset:
Reset:
Property:
PORTCTRL
0x0A
0x00
-
This register contains the slew rate limit enable bit for this port.
Bit
7
6
5
4
3
Access
Reset
2
1
0
SRL
R/W
0
Bit 0 – SRL Slew Rate Limit Enable
This bit controls slew rate limitation for all pins in PORTx.
Value
Description
0
Slew rate limitation is disabled for all pins in PORTx
1
Slew rate limitation is enabled for all pins in PORTx
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PORT - I/O Pin Configuration
16.5.12 Pin n Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INVEN
R/W
0
PINnCTRL
0x10 + n*0x01 [n=0..7]
0x00
-
6
5
4
3
PULLUPEN
R/W
0
2
R/W
0
1
ISC[2:0]
R/W
0
0
R/W
0
Bit 7 – INVEN Inverted I/O Enable
This bit controls whether the input and output for pin n are inverted or not.
Value
Description
0
Input and output values are not inverted
1
Input and output values are inverted
Bit 3 – PULLUPEN Pull-up Enable
This bit controls whether the internal pull-up of pin n is enabled or not when the pin is configured as input-only.
Value
Description
0
Pull-up disabled
1
Pull-up enabled
Bits 2:0 – ISC[2:0] Input/Sense Configuration
This bit field controls the input and sense configuration of pin n. The sense configuration determines how a port
interrupt can be triggered.
Value
Name
Description
0x0
INTDISABLE
Interrupt disabled but input buffer enabled
0x1
BOTHEDGES
Interrupt enabled with sense on both edges
0x2
RISING
Interrupt enabled with sense on rising edge
0x3
FALLING
Interrupt enabled with sense on falling edge
0x4
INPUT_DISABLE
Interrupt and digital input buffer disabled(1)
0x5
LEVEL
Interrupt enabled with sense on low level
other
—
Reserved
Note:
1. If the digital input buffer for pin n is disabled, bit n in the Input Value (PORTx.IN) register will not be updated.
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PORT - I/O Pin Configuration
16.6
Register Summary - VPORTx
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
DIR
OUT
IN
INTFLAGS
7:0
7:0
7:0
7:0
16.7
7
6
5
4
3
2
1
0
DIR[7:0]
OUT[7:0]
IN[7:0]
INT[7:0]
Register Description - VPORTx
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PORT - I/O Pin Configuration
16.7.1
Data Direction
Name:
Offset:
Reset:
Property:
DIR
0x00
0x00
-
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DIR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIR[7:0] Data Direction
This bit field controls the output driver for each PORTx pin.
This bit field does not control the digital input buffer. The digital input buffer for pin n (Pxn) can be configured in the
Input/Sense Configuration (ISC) bit field in the Pin n Control (PORTx.PINnCTRL) register.
The available configuration for each bit n in this bit field is shown in the table below.
Value
Description
0
Pxn is configured as an input-only pin, and the output driver is disabled
1
Pxn is configured as an output pin, and the output driver is enabled
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PORT - I/O Pin Configuration
16.7.2
Output Value
Name:
Offset:
Reset:
Property:
OUT
0x01
0x00
-
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
OUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUT[7:0] Output Value
This bit field controls the output driver level for each PORTx pin.
This configuration only has an effect when the output driver (PORTx.DIR) is enabled for the corresponding pin.
The available configuration for each bit n in this bit field is shown in the table below.
Value
Description
0
The pin n (Pxn) output is driven low
1
The Pxn output is driven high
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PORT - I/O Pin Configuration
16.7.3
Input Value
Name:
Offset:
Reset:
Property:
IN
0x02
0x00
-
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – IN[7:0] Input Value
This bit field shows the state of the PORTx pins when the digital input buffer is enabled.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will toggle the corresponding bit in PORTx.OUT.
If the digital input buffer is disabled, the input is not sampled, and the bit value will not change. The digital input
buffer for pin n (Pxn) can be configured in the Input/Sense Configuration (ISC) bit field in the Pin n Control
(PORTx.PINnCTRL) register.
The available states of each bit n in this bit field is shown in the table below.
Value
Description
0
The voltage level on Pxn is low
1
The voltage level on Pxn is high
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PORT - I/O Pin Configuration
16.7.4
Interrupt Flags
Name:
Offset:
Reset:
Property:
INTFLAGS
0x03
0x00
-
Access to the Virtual PORT registers has the same outcome as access to the regular registers but allows for memory
specific instructions, such as bit manipulation instructions, which cannot be used in the extended I/O Register space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
INT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – INT[7:0] Pin Interrupt Flag
Pin interrupt flag n is cleared by writing a ‘1’ to it.
Pin interrupt flag n is set when the change or state of pin n (Pxn) matches the pin's Input/Sense Configuration (ISC)
in PORTx.PINnCTRL.
Writing a ‘0’ to bit n in this bit field has no effect.
Writing a ‘1’ to bit n in this bit field will clear Pin interrupt flag n.
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ATmega808/809/1608/1609
BOD - Brown-out Detector
17.
BOD - Brown-out Detector
17.1
Features
•
•
•
•
•
17.2
Brown-out Detector Monitors the Power Supply to Avoid Operation Below a Programmable Level
Three Available Modes:
– Enabled mode (continuously active)
– Sampled mode
– Disabled
Separate Selection of Mode for Active and Sleep Modes
Voltage Level Monitor (VLM) with Interrupt
Programmable VLM Level Relative to the BOD Level
Overview
The Brown-out Detector (BOD) monitors the power supply and compares the supply voltage with the programmable
brown-out threshold level. The brown-out threshold level defines when to generate a System Reset. The Voltage
Level Monitor (VLM) monitors the power supply and compares it to a threshold higher than the BOD threshold. The
VLM can then generate an interrupt as an “early warning” when the supply voltage is approaching the BOD threshold.
The VLM threshold level is expressed as a percentage above the BOD threshold level.
The BOD is controlled mainly by fuses and has to be enabled by the user. The mode used in Standby sleep mode
and Power-Down sleep mode can be altered in normal program execution. The VLM is controlled by I/O registers as
well.
When activated, the BOD can operate in Enabled mode, where the BOD is continuously active, or in Sampled mode,
where the BOD is activated briefly at a given period to check the supply voltage level.
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BOD - Brown-out Detector
17.2.1
Block Diagram
Figure 17-1. BOD Block Diagram
VDD
BOD
+
BOD
Reset
-
BOD Threshold
VLM
+
VLM
Interrupt
-
VLM Threshold
17.3
Functional Description
17.3.1
Initialization
The BOD settings are loaded from fuses during Reset. The BOD level and operating mode in Active and Idle sleep
mode are set by fuses and cannot be changed by software. The operating mode in Standby and Power-Down sleep
mode is loaded from fuses and can be changed by software.
The Voltage Level Monitor function can be enabled by writing a ‘1’ to the VLM Interrupt Enable (VLMIE) bit in
the Interrupt Control (BOD.INTCTRL) register. The VLM interrupt is configured by writing the VLM Configuration
(VLMCFG) bits in BOD.INTCTRL. An interrupt is requested when the supply voltage crosses the VLM threshold
either from above, below, or any direction.
The VLM functionality will follow the BOD mode. If the BOD is disabled, the VLM will not be enabled, even if the
VLMIE is ‘1’. If the BOD is using Sampled mode, the VLM will also be sampled. When the VLM interrupt is enabled,
the interrupt flag will be set according to VLMCFG when the voltage level is crossing the VLM level.
The VLM threshold is defined by writing the VLM Level (VLMLVL) bits in the Control A (BOD.VLMCTRLA) register.
17.3.2
Interrupts
Table 17-1. Available Interrupt Vectors and Sources
Name Vector Description
VLM
Conditions
Voltage Level Monitor Supply voltage crossing the VLM threshold as configured by the VLM Configuration
(VLMCFG) bit field in the Interrupt Control (BOD.INTCTRL) register
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BOD - Brown-out Detector
The VLM interrupt will not be executed if the CPU is halted in Debug mode.
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
17.3.3
Sleep Mode Operation
The BOD configuration in the different sleep modes is defined by fuses. The mode used in Active mode and Idle
sleep mode is defined by the ACTIVE fuses in FUSE.BODCFG, which is loaded into the ACTIVE bit field in the
Control A (BOD.CTRLA) register. The mode used in Standby sleep mode and Power-Down sleep mode is defined by
SLEEP in FUSE.BODCFG, which is loaded into the SLEEP bit field in the Control A (BOD.CTRLA) register.
The operating mode in Active mode and Idle sleep mode (i.e., ACTIVE in BOD.CTRLA) cannot be altered by
software. The operating mode in Standby sleep mode and Power-Down sleep mode can be altered by writing to the
SLEEP bit field in the Control A (BOD.CTRLA) register.
When the device is going into Standby or Power-Down sleep mode, the BOD will change the operation mode as
defined by SLEEP in BOD.CTRLA. When the device is waking up from Standby or Power-Down sleep mode, the
BOD will operate in the mode defined by the ACTIVE bit field in the Control A (BOD.CTRLA) register.
17.3.4
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). To write to these registers, a
certain key must first be written to the CPU.CCP register, followed by a write access to the protected bits within four
CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves the
protected register unchanged.
The following registers are under CCP:
Table 17-2. Registers Under Configuration Change Protection
Register
Key
SLEEP in BOD.CTRLA
IOREG
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BOD - Brown-out Detector
17.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
...
0x07
0x08
0x09
0x0A
0x0B
CTRLA
CTRLB
7:0
7:0
17.5
7
6
5
4
SAMPFREQ
3
2
ACTIVE[1:0]
1
0
SLEEP[1:0]
LVL[2:0]
Reserved
VLMCTRLA
INTCTRL
INTFLAGS
STATUS
7:0
7:0
7:0
7:0
VLMCFG[1:0]
VLMLVL[1:0]
VLMIE
VLMIF
VLMS
Register Description
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BOD - Brown-out Detector
17.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
Loaded from fuse
Configuration Change Protection
6
Access
Reset
5
4
SAMPFREQ
R
x
3
2
1
0
ACTIVE[1:0]
R
x
SLEEP[1:0]
R
x
R/W
x
R/W
x
Bit 4 – SAMPFREQ Sample Frequency
This bit controls the BOD sample frequency.
The Reset value is loaded from the SAMPFREQ bit in FUSE.BODCFG.
This bit is not under Configuration Change Protection (CCP).
Value
Description
0x0
Sample frequency is 1 kHz
0x1
Sample frequency is 125 Hz
Bits 3:2 – ACTIVE[1:0] Active
These bits select the BOD operation mode when the device is in Active or Idle mode.
The Reset value is loaded from the ACTIVE bit field in FUSE.BODCFG.
This bit field is not under Configuration Change Protection (CCP).
Value
Name
Description
0x0
DIS
Disabled
0x1
ENABLED Enabled in continuous mode
0x2
SAMPLED Enabled in sampled mode
0x3
ENWAKE
Enabled in continuous mode. Execution is halted at wake-up until BOD is running
Bits 1:0 – SLEEP[1:0] Sleep
These bits select the BOD operation mode when the device is in Standby or Power-Down sleep mode. The Reset
value is loaded from the SLEEP bit field in FUSE.BODCFG.
Value
Name
Description
0x0
DIS
Disabled
0x1
ENABLED
Enabled in continuous mode
0x2
SAMPLED
Enabled in sampled mode
0x3
Reserved
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ATmega808/809/1608/1609
BOD - Brown-out Detector
17.5.2
Control B
Name:
Offset:
Reset:
Property:
CTRLB
0x01
Loaded from fuse
-
Bit
7
6
5
4
3
2
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
x
1
LVL[2:0]
R
x
0
R
x
Bits 2:0 – LVL[2:0] BOD Level
This bit field controls the BOD threshold level.
The Reset value is loaded from the BOD Level (LVL) bits in the BOD Configuration Fuse (FUSE.BODCFG).
Value
Name
Description
0x2
BODLEVEL2
2.6V
0x7
BODLEVEL7
4.2V
Notes:
• Refer to the BOD and POR Characteristics in Electrical Characteristics for further details
• Values in the description are typical values
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ATmega808/809/1608/1609
BOD - Brown-out Detector
17.5.3
VLM Control A
Name:
Offset:
Reset:
Property:
Bit
7
VLMCTRLA
0x08
0x00
-
6
5
4
3
2
Access
Reset
1
0
VLMLVL[1:0]
R/W
R/W
0
0
Bits 1:0 – VLMLVL[1:0] VLM Level
These bits select the VLM threshold relative to the BOD threshold (LVL in BOD.CTRLB).
Value
Description
0x0
VLM threshold 5% above BOD threshold
0x1
VLM threshold 15% above BOD threshold
0x2
VLM threshold 25% above BOD threshold
other
Reserved
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ATmega808/809/1608/1609
BOD - Brown-out Detector
17.5.4
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x09
0x00
-
6
5
4
3
Access
Reset
2
1
VLMCFG[1:0]
R/W
R/W
0
0
0
VLMIE
R/W
0
Bits 2:1 – VLMCFG[1:0] VLM Configuration
These bits select which incidents will trigger a VLM interrupt.
Value
Name
Description
0x0
BELOW
VDD falls below VLM threshold
0x1
ABOVE
VDD rises above VLM threshold
0x2
CROSS
VDD crosses VLM threshold
Other
Reserved
Bit 0 – VLMIE VLM Interrupt Enable
Writing a ‘1’ to this bit enables the VLM interrupt.
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ATmega808/809/1608/1609
BOD - Brown-out Detector
17.5.5
VLM Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x0A
0x00
-
6
5
4
3
Access
Reset
2
1
0
VLMIF
R/W
0
Bit 0 – VLMIF VLM Interrupt Flag
This flag is set when a trigger from the VLM is given, as configured by the VLMCFG bit in the BOD.INTCTRL register.
The flag is only updated when the BOD is enabled.
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Complete Datasheet
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ATmega808/809/1608/1609
BOD - Brown-out Detector
17.5.6
VLM Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x0B
0x00
-
6
5
4
3
Access
Reset
2
1
0
VLMS
R
0
Bit 0 – VLMS VLM Status
This bit is only valid when the BOD is enabled.
Value
Description
0
The voltage is above the VLM threshold level
1
The voltage is below the VLM threshold level
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Complete Datasheet
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ATmega808/809/1608/1609
VREF - Voltage Reference
18.
VREF - Voltage Reference
18.1
Features
•
•
18.2
Programmable Voltage Reference Sources:
– For ADC0 peripheral
– For AC0 peripheral
Each Reference Source Supports Different Voltages:
– 0.55V
– 1.1V
– 1.5V
– 2.5V
– 4.3V
– AVDD
Overview
The Voltage Reference buffer (VREF) provides control registers for selecting between multiple internal reference
levels. The internal references are generated from the internal bandgap.
When a peripheral that requires a voltage reference is enabled the corresponding voltage reference buffer and
bandgap is automatically enabled.
18.2.1
Block Diagram
Figure 18-1. VREF Block Diagram
Reference reque st
Reference enable
Reference se lect
Bandgap
Reference
Gen erator
Ban dgap
ena ble
18.3
18.3.1
0.55V
1.1V
1.5V
2.5V
4.3V
BUF
Inte rnal
Reference
Functional Description
Initialization
The output level from the reference buffer should be selected (ADC0REFSEL and AC0REFSEL in VREF.CTRLA)
before the respective modules are enabled. The reference buffer is then automatically enabled when requested by a
peripheral. Changing the reference while these modules are enabled could lead to unpredictable behavior.
The VREF module and reference voltage sources can be forced to be ON, independent of being required
by a peripheral, by writing to the respective Force Enable bits (ADC0REFEN, AC0REFEN) in the Control B
(VREF.CTRLB) register. This can be used to remove the reference start-up time, at the cost of increased power
consumption.
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Complete Datasheet
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ATmega808/809/1608/1609
VREF - Voltage Reference
18.4
Register Summary - VREF
Offset
Name
Bit Pos.
0x00
0x01
CTRLA
CTRLB
7:0
7:0
18.5
7
6
5
4
ADC0REFSEL[2:0]
3
2
1
0
AC0REFSEL[2:0]
ADC0REFEN AC0REFEN
Register Description
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Complete Datasheet
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ATmega808/809/1608/1609
VREF - Voltage Reference
18.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
-
6
R/W
0
5
ADC0REFSEL[2:0]
R/W
0
4
3
R/W
0
2
R/W
0
1
AC0REFSEL[2:0]
R/W
0
0
R/W
0
Bits 6:4 – ADC0REFSEL[2:0] ADC0 Reference Select
These bits select the reference voltage for ADC0.
Value
Name
Description
0x0
0V55
0.55V internal reference
0x1
1V1
1.1V internal reference
0x2
2V5
2.5V internal reference
0x3
4V3
4.3V internal reference
0x4
1V5
1.5V internal reference
Other
Reserved
Note: Refer to VREF in the Electrical Characteristics section for further details.
Bits 2:0 – AC0REFSEL[2:0] AC0 Reference Select
These bits select the reference voltage for AC0.
Value
Name
Description
0x0
0V55
0.55V internal reference
0x1
1V1
1.1V internal reference
0x2
2V5
2.5V internal reference
0x3
4V3
4.3V internal reference
0x4
1V5
1.5V internal reference
0x5
Reserved
0x6
Reserved
0x7
AVDD
AVDD
Note: Refer to VREF in the Electrical Characteristics section for further details.
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Complete Datasheet
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ATmega808/809/1608/1609
VREF - Voltage Reference
18.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
-
6
5
4
3
Access
Reset
2
1
ADC0REFEN
R/W
0
0
AC0REFEN
R/W
0
Bit 1 – ADC0REFEN ADC0 Reference Force Enable
Writing a ‘1’ to this bit forces the voltage reference for ADC0 to be enabled, even if it is not requested.
Writing a ‘0’ to this bit allows to automatic enable/disable the reference source when not requested.
Bit 0 – AC0REFEN AC0 DACREF Reference Force Enable
Writing a ‘1’ to this bit forces the voltage reference for AC0 DACREF to be enabled, even if it is not requested.
Writing a ‘0’ to this bit allows to automatic enable/disable the reference source when not requested.
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Complete Datasheet
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ATmega808/809/1608/1609
WDT - Watchdog Timer
19.
WDT - Watchdog Timer
19.1
Features
•
•
•
•
•
•
•
19.2
Issues a System Reset if the Watchdog Timer is not Cleared Before its Time-out Period
Operating Asynchronously from System Clock Using an Independent Oscillator
Using the 1.024 kHz Output of the 32.768 kHz Ultra Low-Power Oscillator (OSCULP32K)
11 Selectable Time-out Periods, from 8 ms to 8s
Two Operation Modes:
– Normal mode
– Window mode
Configuration Lock to Prevent Unwanted Changes
Closed Period Timer Activation After First WDT Instruction for Easy Setup
Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It allows the system
to recover from situations such as runaway or deadlocked code by issuing a Reset. When enabled, the WDT is
a constantly running timer configured to a predefined time-out period. If the WDT is not reset within the time-out
period, it will issue a system Reset. The WDT is reset by executing the Watchdog Timer Reset (WDR) instruction from
software.
The WDT has two modes of operation: Normal mode and Window mode. The settings in the Control A (WDT.CTRLA)
register determine the mode of operation.
A Window mode defines a time slot or "window" inside the time-out period during which the WDT must be reset. If the
WDT is reset outside this window, either too early or too late, a system Reset will be issued. Compared to the Normal
mode, the Window mode can catch situations where a code error causes constant WDR execution.
When enabled, the WDT will run in Active mode and all sleep modes. It is asynchronous (i.e., running from a CPU
independent clock source). For this reason, it will continue to operate and be able to issue a system Reset even if the
main clock fails.
The CCP mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a
configuration for locking the WDT settings is available.
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 184
ATmega808/809/1608/1609
WDT - Watchdog Timer
19.2.1
Block Diagram
Figure 19-1. WDT Block Diagram
"Inside closed window"
CTRLA
WINDOW
CLK_WDT
=
"Enable
open window
and clear count"
COUNT
PERIOD
=
System
Reset
CTRLA
WDR
(instruction)
19.2.2
Signal Description
Not applicable.
19.3
Functional Description
19.3.1
Initialization
•
•
The WDT is enabled when a non-zero value is written to the Period (PERIOD) bits in the Control A
(WDT.CTRLA) register
Optional: Write a non-zero value to the Window (WINDOW) bits in WDT.CTRLA to enable the Window mode
operation.
All bits in the Control A register and the Lock (LOCK) bit in the STATUS (WDT.STATUS) register are write-protected
by the Configuration Change Protection mechanism.
The Reset value of WDT.CTRLA is defined by a fuse (FUSE.WDTCFG), so the WDT can be enabled at boot time. If
this is the case, the LOCK bit in WDT.STATUS is set at boot time.
19.3.2
Clocks
A 1.024 kHz Oscillator Clock (CLK_WDT_OSC) is sourced from the internal Ultra Low-Power Oscillator,
OSCULP32K. Due to the ultra low-power design, the oscillator is not very accurate, and so the exact time-out period
may vary from device to device. This variation must be kept in mind when designing software that uses the WDT to
ensure that the time-out periods used are valid for all devices.
The 1.024 kHz Oscillator Clock, CLK_WDT_OSC, is asynchronous to the system clock. Due to this asynchronicity,
writing to the WDT Control register will require synchronization between the clock domains.
19.3.3
Operation
19.3.3.1 Normal Mode
In Normal mode operation, a single time-out period is set for the WDT. If the WDT is not reset from software using the
WDR any time before the time-out occurs, the WDT will issue a system Reset.
A new WDT time-out period will be started each time the WDT is reset by WDR.
There are 11 possible WDT time-out periods (TOWDT), selectable from 8 ms to 8s by writing to the Period (PERIOD)
bit field in the Control A (WDT.CTRLA) register.
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Complete Datasheet
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ATmega808/809/1608/1609
WDT - Watchdog Timer
Figure 19-2. Normal Mode Operation
WDT Count
Timely WDT Reset (WDR)
WDT Timeout
System Reset
Here:
TO WDT = 16 ms
5
10
15
20
25
30
TOWDT
35
t [ms]
Normal mode is enabled as long as the WINDOW bit field in the Control A (WDT.CTRLA) register is 0x0.
19.3.3.2 Window Mode
In Window mode operation, the WDT uses two different time-out periods: A closed Window Time-out period
(TOWDTW) and the normal time-out period (TOWDT):
• The closed window time-out period defines a duration from 8 ms to 8s, where the WDT cannot be reset. If the
WDT is reset during this period, the WDT will issue a system Reset.
• The normal WDT time-out period, which is also 8 ms to 8s, defines the duration of the open period during which
the WDT can (and needs to) be reset. The open period will always follow the closed period, so the total duration
of the time-out period is the sum of the closed window and the open window time-out periods.
When enabling Window mode or when going out of Debug mode, the first closed period is activated after the first WDR
instruction.
If a second WDR is issued while a previous WDR is being synchronized, the second one will be ignored.
Figure 19-3. Window Mode Operation
WDT Count
Open
Timely WDT Reset (WDR)
Closed
WDR too early:
System Reset
Here:
TOWDTW =TOWDT = 8 ms
5
10
15
20
TOWDTW
25
30
TOWDT
35
t [ms]
The Window mode is enabled by writing a non-zero value to the WINDOW bit field in the Control A (WDT.CTRLA)
register, and disabled by writing it to 0x0.
19.3.3.3 Configuration Protection and Lock
The WDT provides two security mechanisms to avoid unintentional changes to the WDT settings.
The first mechanism is the Configuration Change Protection mechanism, employing a timed-write procedure for
changing the WDT control registers.
The second mechanism locks the configuration by writing a ‘1’ to the LOCK bit in the STATUS (WDT.STATUS)
register. When this bit is ‘1’, the Control A (WDT.CTRLA) register cannot be changed. Consequently, the WDT cannot
be disabled from the software.
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Complete Datasheet
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ATmega808/809/1608/1609
WDT - Watchdog Timer
LOCK in WDT.STATUS can only be written to ‘1’. It can only be cleared in Debug mode.
If the WDT configuration is loaded from fuses, LOCK is automatically set in WDT.STATUS.
19.3.4
Sleep Mode Operation
The WDT will continue to operate in any sleep mode where the source clock is Active.
19.3.5
Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt the normal operation of the peripheral.
When halting the CPU in Debug mode, the WDT counter is reset.
When starting the CPU again and the WDT is operating in Window mode, the first closed window time-out period will
be disabled, and a Normal mode time-out period is executed.
19.3.6
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A (WDT.CTRLA)
register is synchronized when written. The Synchronization Busy (SYNCBUSY) flag in the STATUS (WDT.STATUS)
register indicates if there is an ongoing synchronization.
Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.
The following registers are synchronized when written:
• PERIOD bits in Control A (WDT.CTRLA) register
• Window Period (WINDOW) bits in WDT.CTRLA
The WDR instruction will need two to three cycles of the WDT clock to be synchronized. Issuing a new WDR instruction
while a WDR instruction is being synchronized will be ignored.
19.3.7
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). To write to these registers, a
certain key must first be written to the CPU.CCP register, followed by a write access to the protected bits within four
CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves the
protected register unchanged.
The following registers are under CCP:
Table 19-1. WDT - Registers Under Configuration Change Protection
Register
Key
WDT.CTRLA
IOREG
LOCK bit in WDT.STATUS
IOREG
List of bits/registers protected by CCP:
•
•
•
Period bits in Control A (CTRLA.PERIOD) register
Window Period bits in Control A (CTRLA.WINDOW) register
LOCK bit in STATUS (STATUS.LOCK) register
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ATmega808/809/1608/1609
WDT - Watchdog Timer
19.4
Register Summary - WDT
Offset
Name
Bit Pos.
7
0x00
0x01
CTRLA
STATUS
7:0
7:0
LOCK
19.5
6
5
4
WINDOW[3:0]
3
2
1
0
PERIOD[3:0]
SYNCBUSY
Register Description
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Complete Datasheet
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ATmega808/809/1608/1609
WDT - Watchdog Timer
19.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
Access
Reset
R/W
x
CTRLA
0x00
From FUSE.WDTCFG
Configuration Change Protection
6
5
WINDOW[3:0]
R/W
R/W
x
x
4
3
R/W
x
R/W
x
2
1
PERIOD[3:0]
R/W
R/W
x
x
0
R/W
x
Bits 7:4 – WINDOW[3:0] Window
Writing a non-zero value to these bits enables the Window mode, and selects the duration of the closed period
accordingly.
The bits are optionally lock-protected:
• If LOCK bit in WDT.STATUS is ‘1’, all bits are change-protected (Access = R)
•
If LOCK bit in WDT.STATUS is ‘0’, all bits can be changed (Access = R/W)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
other
Name
OFF
8CLK
16CLK
32CLK
64CLK
128CLK
256CLK
512CLK
1KCLK
2KCLK
4KCLK
8KCLK
-
Description
0.008s
0.016s
0.031s
0.063s
0.125s
0.25s
0.5s
1s
2s
4s
8s
Reserved
Bits 3:0 – PERIOD[3:0] Period
Writing a non-zero value to this bit enables the WDT, and selects the time-out period in Normal mode accordingly. In
Window mode, these bits select the duration of the open window.
The bits are optionally lock-protected:
• If LOCK in WDT.STATUS is ‘1’, all bits are change-protected (Access = R)
•
If LOCK in WDT.STATUS is ‘0’, all bits can be changed (Access = R/W)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
other
Name
OFF
8CLK
16CLK
32CLK
64CLK
128CLK
256CLK
512CLK
1KCLK
2KCLK
4KCLK
8KCLK
-
© 2021 Microchip Technology Inc.
Description
0.008s
0.016s
0.031s
0.063s
0.125s
0.25s
0.5s
1s
2s
4s
8s
Reserved
Complete Datasheet
DS40002172C-page 189
ATmega808/809/1608/1609
WDT - Watchdog Timer
19.5.2
Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
LOCK
R/W
0
STATUS
0x01
0x00
Configuration Change Protection
6
5
4
3
2
1
0
SYNCBUSY
R
0
Bit 7 – LOCK Lock
Writing this bit to ‘1’ write-protects the WDT.CTRLA register.
It is only possible to write this bit to ‘1’. This bit can be cleared in Debug mode only.
If the PERIOD bits in WDT.CTRLA are different from zero after boot code, the lock will be automatically set.
This bit is under CCP.
Bit 0 – SYNCBUSY Synchronization Busy
This bit is set after writing to the WDT.CTRLA register, while the data is being synchronized from the system clock
domain to the WDT clock domain.
This bit is cleared by the system after the synchronization is finished.
This bit is not under CCP.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.
TCA - 16-bit Timer/Counter Type A
20.1
Features
•
•
•
•
•
•
•
•
•
20.2
16-Bit Timer/Counter
Three Compare Channels
Double-Buffered Timer Period Setting
Double-Buffered Compare Channels
Waveform Generation:
– Frequency generation
– Single-slope PWM (Pulse-Width Modulation)
– Dual-slope PWM
Count on Event
Timer Overflow Interrupts/Events
One Compare Match per Compare Channel
Two 8-Bit Timer/Counters in Split Mode
Overview
The flexible 16-bit PWM Timer/Counter type A (TCA) provides accurate program execution timing, frequency and
waveform generation, and command execution.
A TCA consists of a base counter and a set of compare channels. The base counter can be used to count clock
cycles or events or let events control how it counts clock cycles. It has direction control and period setting that can
be used for timing. The compare channels can be used together with the base counter to perform a compare match
control, frequency generation, and pulse-width waveform modulation.
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each timer/
counter clock or event input.
A timer/counter can be clocked and timed from the peripheral clock, with optional prescaling, or from the Event
System. The Event System can also be used for direction control or to synchronize operations.
By default, the TCA is a 16-bit timer/counter. The timer/counter has a Split mode feature that splits it into two 8-bit
timer/counters with three compare channels each.
A block diagram of the 16-bit timer/counter with closely related peripheral modules (in grey) is shown in the figure
below.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
Figure 20-1. 16-bit Timer/Counter and Closely Related Peripherals
Timer/Counter
Base Counter
Timer Period
Counter
Prescaler
Control Logic
Event
System
Waveform
Generation
Buffer
Block Diagram
The figure below shows a detailed block diagram of the timer/counter.
Figure 20-2. Timer/Counter Block Diagram
Base Counter
CTRL A
BV
PERBUF
CTRL B
PER
EVCTRL
Clock Select
Mode
Event
Action
‘‘count’’
‘‘clear’’
‘‘load’’
‘‘direction’’
Counter
CNT
=
=0
OVF
(INT Req. and Event)
Control Logic
Event
TOP
BOTTOM
UPDATE
20.2.1
PORTS
Compare Channel 0
Compare Channel 1
Compare Channel 2
Comparator
CLK_PER
Compare Unit n
BV
Control Logic
CMPnBUF
CMPn
=
© 2021 Microchip Technology Inc.
Waveform
Generation
‘‘match’’
Complete Datasheet
WOn Out
CMPn
(INT Req. and Event)
DS40002172C-page 192
ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
The Counter (TCAn.CNT) register, Period and Compare (TCAn.PER and TCAn.CMPn) registers, and their
corresponding buffer registers (TCAn.PERBUF and TCAn.CMPnBUF) are 16-bit registers. All buffer registers have a
Buffer Valid (BV) flag that indicates when the buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value to
determine whether the counter has reached TOP or BOTTOM. The counter value can also be compared to the
TCAn.CMPn registers.
The timer/counter can generate interrupt requests, events, or change the waveform output after being triggered by
the Counter (TCAn.CNT) register reaching TOP, BOTTOM, or CMPn. The interrupt requests, events, or waveform
output changes will occur on the next CLK_TCA cycle after the triggering.
CLK_TCA is either the prescaled peripheral clock or events from the Event System, as shown in the figure below.
Figure 20-3. Timer/Counter Clock Logic
CLK_TCA
CLK_PER
CNT
‘‘Count
Enable’’
Prescaler
Event
Logic
CLKSEL
Event
‘‘Count
Direction’’
DIR
EVACT
CNTxEI
20.2.2
Signal Description
Signal
Description
Type
WOn
Digital output
Waveform output
20.3
Functional Description
20.3.1
Definitions
The following definitions are used throughout the documentation:
Table 20-1. Timer/Counter Definitions
Name
Description
BOTTOM The counter reaches BOTTOM when it becomes 0x0000
MAX
The counter reaches MAXimum when it becomes all ones
TOP
The counter reaches TOP when it becomes equal to the highest value in the count sequence
The update condition is met when the timer/counter reaches BOTTOM or TOP, depending on the
UPDATE Waveform Generator mode. Buffered registers with valid buffer values will be updated unless the Lock
Update (LUPD) bit in the TCAn.CTRLE register has been set.
CNT
Counter register value
CMP
Compare register value
PER
Period register value
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In general, the term timer is used when the timer/counter is counting periodic clock ticks. The term counter is used
when the input signal has sporadic or irregular ticks. The latter can be the case when counting events.
20.3.2
Initialization
To start using the timer/counter in basic mode, follow these steps:
1. Write a TOP value to the Period (TCAn.PER) register.
2. Enable the peripheral by writing a ‘1’ to the ENABLE bit in the Control A (TCAn.CTRLA) register.
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bit
field in the TCAn.CTRLA register.
3. Optional: By writing a ‘1’ to the Enable Count on Event Input (CNTEI) bit in the Event Control (TCAn.EVCTRL)
register, events are counted instead of clock ticks.
4. The counter value can be read from the Counter (CNT) bit field in the Counter (TCAn.CNT) register.
20.3.3
Operation
20.3.3.1 Normal Operation
In normal operation the counter is counting clock ticks in the direction selected by the Direction (DIR) bit in the
Control E (TCAn.CTRLE) register until it reaches TOP or BOTTOM. The clock ticks are given by the peripheral clock
(CLK_PER), prescaled according to the Clock Select (CLKSEL) bit field in the Control A (TCAn.CTRLA) register.
When TOP is reached while the counter is counting up, the counter will wrap to ‘0’ at the next clock tick. When
counting down, the counter is reloaded with the Period (TCAn.PER) register value when the BOTTOM is reached.
Figure 20-4. Normal Operation
CNT written
MAX
‘‘update’’
CNT
TOP
BOTTOM
DIR
It is possible to change the counter value in the Counter (TCAn.CNT) register when the counter is running. The write
access to TCAn.CNT register has higher priority than count, clear or reload, and will be immediate. The direction
of the counter can also be changed during normal operation by writing to the Direction (DIR) bit in the Control E
(TCAn.CTRLE) register.
20.3.3.2 Double Buffering
The Period (TCAn.PER) register value and the Compare n (TCAn.CMPn) register values are all double-buffered
(TCAn.PERBUF and TCAn.CMPnBUF).
Each buffer register has a Buffer Valid (BV) flag (PERBV, CMPnBV) in the Control F (TCAn.CTRLF) register, which
indicates that the buffer register contains a valid (new) value that can be copied into the corresponding Period or
Compare register. When the Period register and Compare n registers are used for a compare operation, the BV flag
is set when data are written to the buffer register and cleared on an UPDATE condition. This is shown for a Compare
(CMPn) register in the figure below.
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Figure 20-5. Period and Compare Double Buffering
‘‘write enable’’
BV
EN
EN
UPDATE
‘‘data write’’
CMPnBUF
CMPn
CNT
=
‘‘match’’
Both the TCAn.CMPn and TCAn.CMPnBUF registers are available as I/O registers. This allows the initialization and
bypassing of the buffer register and the double-buffering function.
20.3.3.3 Changing the Period
The Counter period is changed by writing a new TOP value to the Period (TCAn.PER) register.
No Buffering: If double-buffering is not used, any period update is immediate.
Figure 20-6. Changing the Period Without Buffering
Counter wrap-around
MAX
‘‘update’’
‘‘write’’
CNT
BOTTOM
New TOP written to
New TOP written to
PER that is higher
PER that is lower
than current CNT.
than current CNT.
A counter wrap-around can occur in any mode of operation when counting up without buffering, as the TCAn.CNT
and TCAn.PER registers are continuously compared. If a new TOP value is written to TCAn.PER that is lower than
the current TCAn.CNT, the counter will wrap first, before a compare match occurs.
Figure 20-7. Unbuffered Dual-Slope Operation
Counter wrap-around
MAX
‘‘update’’
‘‘write’’
CNT
BOTTOM
New TOP written to
PER that is higher
than current CNT.
New TOP written to
PER that is lower
than current CNT.
With Buffering: When double-buffering is used, the buffer can be written at any time and still maintain the correct
operation. The TCAn.PER is always updated on the UPDATE condition, as shown for dual-slope operation in the
figure below. This prevents wrap-around and the generation of odd waveforms.
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Figure 20-8. Changing the Period Using Buffering
MAX
‘‘update’’
‘‘write’’
CNT
BOTTOM
New Period written to
PERB that is higher
than current CNT.
New Period written to
PERB that is lower
than current CNT.
New PER is updated
with PERB value.
Note: Buffering is used in figures illustrating TCA operation if not otherwise specified.
20.3.3.4 Compare Channel
Each Compare Channel n continuously compares the counter value (TCAn.CNT) with the Compare n (TCAn.CMPn)
register. If TCAn.CNT equals TCAn.CMPn the Comparator n signals a match. The match will set the Compare
Channel’s interrupt flag at the next timer clock cycle, and the optional interrupt is generated.
The Compare n Buffer (TCAn.CMPnBUF) register provides double-buffer capability equivalent to that for the period
buffer. The double-buffering synchronizes the update of the TCAn.CMPn register with the buffer value to either the
TOP or BOTTOM of the counting sequence, according to the UPDATE condition. The synchronization prevents the
occurrence of odd-length, non-symmetrical pulses for glitch-free output.
The value in CMPnBUF is moved to CMPn at the UPDATE condition and is compared to the counter value
(TCAn.CNT) from the next count.
20.3.3.4.1 Waveform Generation
The compare channels can be used for waveform generation on the corresponding port pins. The following
requirements must be met to make the waveform visible on the connected port pin:
1.
2.
3.
4.
A Waveform Generation mode must be selected by writing the Waveform Generation Mode (WGMODE) bit
field in the TCAn.CTRLB register.
The compare channels used must be enabled (CMPnEN = 1 in TCAn.CTRLB). This will override the output
value for the corresponding pin. An alternative pin can be selected by configuring the Port Multiplexer
(PORTMUX). Refer to the PORTMUX section for details.
The direction for the associated port pin n must be configured in the Port peripheral as an output.
Optional: Enable the inverted waveform output for the associated port pin n. Refer to the PORT section for
details.
20.3.3.4.2 Frequency (FRQ) Waveform Generation
For frequency generation, the period time (T) is controlled by the TCAn.CMP0 register instead of the Period
(TCAn.PER) register. The corresponding waveform generator output is toggled on each compare match between
the TCAn.CNT and TCAn.CMPn registers.
Figure 20-9. Frequency Waveform Generation
Period (T)
Direction change
CNT written
MAX
‘‘update’’
CNT
TOP
BOTTOM
Waveform Output
The following equation defines the waveform frequency (fFRQ):
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fFRQ =
f CLK_PER
2N CMP0+1
where N represents the prescaler divider used (see the CLKSEL bit field in the TCAn.CTRLA register), and fCLK_PER
is the peripheral clock frequency.
The maximum frequency of the waveform generated is half of the peripheral clock frequency (fCLK_PER/2) when
TCAn.CMP0 is written to 0x0000 and no prescaling is used (N = 1, CLKSEL = 0x0 in TCAn.CTRLA).
Use the TCAn.CMP1 and TCAn.CMP2 registers to get additional waveform outputs WOn. The waveforms WOn can
either be identical or offset to WO0. The offset can be influenced by TCAn.CMPn, TCAn.CNT and the count direction.
The offset in seconds tOffset can be calculated using the equations in the table below. The equations are only valid
when CMPnCNT and CMPn>CNT
WOn trailing WO0
UP
CMPn TOP will produce a static high signal on
WOn.
Figure 20-12. Single-Slope Pulse-Width Modulation
Period (T)
CMPn=BOTTOM
CMPn>TOP
MAX
TOP
‘‘update’’
‘‘match’’
CNT
CMPn
BOTTOM
Waveform Output
Notes:
1. The representation in the figure above is valid when CMPn is updated using CMPnBUF.
2. For single-slope Pulse-Width Modulation (PWM) generation, the counter counting from TOP to BOTTOM is not
supported.
The TCAn.PER register defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER = 0x0003), and
the maximum resolution is 16 bits (TCAn.PER = MAX).
The following equation calculates the exact resolution in bits for single-slope PWM (RPWM_SS):
RPWM_SS =
log PER+1
log 2
fPWM_SS =
fCLK_PER
N PER+1
The single-slope PWM frequency (fPWM_SS) depends on the period setting (TCAn.PER), the peripheral clock
frequency fCLK_PER and the TCA prescaler (the CLKSEL bit field in the TCAn.CTRLA register). It is calculated by
the following equation where N represents the prescaler divider used:
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20.3.3.4.4 Dual-Slope PWM
For the dual-slope PWM generation, the period (T) is controlled by TCAn.PER, while the values of TCAn.CMPn
control the duty cycle of the WG output.
The figure below shows how, for dual-slope PWM, the counter repeatedly counts from BOTTOM to TOP and
then from TOP to BOTTOM. The waveform generator output is set at BOTTOM, cleared on compare match when
up-counting, and set on compare match when down-counting.
CMPn = BOTTOM produces a static low signal on WOn, while CMPn = TOP produces a static high signal on WOn.
Figure 20-13. Dual-Slope Pulse-Width Modulation
Period (T)
CMPn=BOTTOM
CMPn=TOP
‘‘update’’
‘‘match’’
MAX
CMPn
CNT
TOP
BOTTOM
Waveform Output
Note: The representation in the figure above is valid when CMPn is updated using CMPnBUF.
The Period (TCAn.PER) register defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER =
0x0003), and the maximum resolution is 16 bits (TCAn.PER = MAX).
The following equation calculates the exact resolution in bits for dual-slope PWM (RPWM_DS):
RPWM_DS =
log PER+1
log 2
fPWM_DS =
fCLK_PER
2N ⋅ PER
The PWM frequency depends on the period setting in the TCAn.PER register, the peripheral clock frequency
(fCLK_PER), and the prescaler divider selected in the CLKSEL bit field in the TCAn.CTRLA register. It is calculated by
the following equation:
N represents the prescaler divider used.
Using dual-slope PWM results in approximately half the maximum operation frequency compared to single-slope
PWM operation, due to twice the number of timer increments per period.
20.3.3.4.5 Port Override for Waveform Generation
To make the waveform generation available on the port pins, the corresponding port pin direction must be set
as output (PORTx.DIR[n] = 1). The TCA will override the port pin values when the compare channel is enabled
(CMPnEN = 1 in the TCAn.CTRLB register), and a Waveform Generation mode is selected.
The figure below shows the port override for TCA. The timer/counter compare channel will override the port pin
output value (PORTx.OUT) on the corresponding port pin. Enabling inverted I/O on the port pin (INVEN = 1 in the
PORTx.PINnCTRL register) inverts the corresponding WG output.
Figure 20-14. Port Override for Timer/Counter Type A
OUT
WOn
Waveform
CMPnEN
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20.3.3.5 Timer/Counter Commands
A set of commands can be issued by software to immediately change the state of the peripheral. These commands
give direct control of the UPDATE, RESTART and RESET signals. A command is issued by writing the respective
value to the Command (CMD) bit field in the Control E (TCAn.CTRLESET) register.
An UPDATE command has the same effect as when an UPDATE condition occurs, except that the UPDATE
command is not affected by the state of the Lock Update (LUPD) bit in the Control E (TCAn.CTRLE) register.
The software can force a restart of the current waveform period by issuing a RESTART command. In this case, the
counter, direction, and all compare outputs are set to ‘0’.
A RESET command will set all timer/counter registers to their initial values. A RESET command can be issued only
when the timer/counter is not running (ENABLE = 0 in the TCAn.CTRLA register).
20.3.3.6 Split Mode - Two 8-Bit Timer/Counters
Split Mode Overview
To double the number of timers and PWM channels in the TCA, a Split mode is provided. In this Split mode, the 16-bit
timer/counter acts as two separate 8-bit timers, which each have three compare channels for PWM generation. The
Split mode will only work with single-slope down-count. Event controlled operation is not supported in Split mode.
The figure below shows single-slope PWM generation in Split mode. The waveform generator output is cleared at
BOTTOM, and set on compare match between the counter value (TCAn.CNT) and the Compare n (TCAn.CMPn)
register.
Figure 20-15. Single-Slope Pulse-Width Modulation in Split mode
Period (T)
CMPn=BOTTOM
CMPn>TOP
‘‘update’’
‘‘match’’
MA X
TOP
CNT
CMPn
B OTTOM
Waveform Output
Note: The maximum duty-cycle of the waveform output is TOP/(TOP+1)
Activating Split mode results in changes to the functionality of some registers and register bits. The modifications are
described in a separate register map (see 20.6 Register Summary - Split Mode).
Split Mode Differences Compared to Normal Mode
• Count:
– Down-count only
– Low Byte Timer Counter (TCAn.LCNT) register and High Byte Timer Counter (TCAn.HCNT) register are
independent
• Waveform generation:
– Single-slope PWM only (WGMODE = SINGLESLOPE in the TCAn.CTRLB register)
• Interrupt:
– No change for Low Byte Timer Counter (TCAn.LCNT) register
– Underflow interrupt for High Byte Timer Counter (TCAn.HCNT) register
– No compare interrupt or flag for High Byte Compare n (TCAn.HCMPn) register
• Event Actions: Not compatible
• Buffer registers and buffer valid flags: Unused
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•
Register Access: Byte access to all registers
Block Diagram
Figure 20-16. Timer/Counter Block Diagram Split Mode
Base Counter
HPER
LPER
Clock Select
CTRLA
‘‘count high’’
‘‘load high’’
Counter
HCNT
‘‘count low’’
‘‘load low’’
LCNT
HUNF
Control Logic
(INT Req. and Event)
LUNF
(INT Req. and Event)
=0
BOTTOML
BOTTOMH
=0
Compare Unit n
LCMPn
=
Waveform
Generation
WOn Out
LCMPn
‘‘match’’
(INT Req. and Event)
Compare Unit n
HCMPn
=
Waveform
Generation
WO[n+3] Out
‘‘match’’
Split Mode Initialization
When shifting between Normal mode and Split mode, the functionality of some registers and bits changes, but their
values do not. For this reason, disabling the peripheral (ENABLE = 0 in the TCAn.CTRLA register) and doing a
hard Reset (CMD = RESET in the TCAn.CTRLESET register) is recommended when changing the mode to avoid
unexpected behavior.
To start using the timer/counter in basic Split mode after a hard Reset, follow these steps:
1. Enable Split mode by writing a ‘1’ to the Split mode enable (SPLITM) bit in the Control D (TCAn.CTRLD)
register.
2. Write a TOP value to the Period (TCAn.PER) registers.
3. Enable the peripheral by writing a ‘1’ to the Enable (ENABLE) bit in the Control A (TCAn.CTRLA) register.
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bit
field in the TCAn.CTRLA register.
4. The counter values can be read from the Counter bit field in the Counter (TCAn.CNT) registers.
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20.3.4
Events
The TCA can generate the events described in the table below. All event generators except TCAn_HUNF are shared
between Normal mode and Split mode operation.
Table 20-3. Event Generators in TCA
Generator Name
Peripheral
Description
Event
OVF_LUNF
HUNF
CMP0
TCAn
CMP1
CMP2
Normal mode: Overflow
Split mode: Low byte timer underflow
Normal mode: Not available
Split mode: High byte timer underflow
Normal mode: Compare Channel 0
match
Split mode: Low byte timer Compare
Channel 0 match
Normal mode: Compare Channel 1
match
Split mode: Low byte timer Compare
Channel 1 match
Normal mode: Compare Channel 2
match
Split mode: Low byte timer Compare
Channel 2 match
Event
Type
Generating
Clock Domain
Pulse
CLK_PER
One CLK_PER
period
Pulse
CLK_PER
One CLK_PER
period
Pulse
CLK_PER
One CLK_PER
period
Pulse
CLK_PER
One CLK_PER
period
Pulse
CLK_PER
One CLK_PER
period
Length of Event
Note: The conditions for generating an event are identical to those that will raise the corresponding interrupt flag in
the TCAn.INTFLAGS register for both Normal mode and Split mode.
The TCA has one event user for detecting and acting upon input events. The table below describes the event user
and the associated functionality.
Table 20-4. Event User in TCA
User Name
Description
Peripheral Input
TCAn
Input Detection Async/Sync
Count on a positive event edge
Edge
Sync
Count on any event edge
Edge
Sync
Level
Sync
Level
Sync
CNT Count while the event signal is high
The event level controls the count direction, up when low and
down when high
Notes:
1. Event inputs are not used in Split mode.
2. Event actions with level input detection only work reliably if the event frequency is less than the timer’s
frequency.
The specific actions described in the table above are selected by writing to the Event Action (EVACT) bit field in the
Event Control (TCAn.EVCTRL) register. Input events are enabled by writing a ‘1’ to the Enable Count on Event Input
(CNTEI) bit in the Event Control (TCAn.EVCTRL) register.
Refer to the Event System (EVSYS) chapter for more details regarding event types and Event System configuration.
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20.3.5
Interrupts
Table 20-5. Available Interrupt Vectors and Sources in Normal Mode
Name
OVF
Vector Description
Overflow or underflow interrupt
Conditions
The counter has reached TOP or BOTTOM
CMP0 Compare Channel 0 interrupt
Match between the counter value and the Compare 0 register
CMP1 Compare Channel 1 interrupt
Match between the counter value and the Compare 1 register
CMP2 Compare Channel 2 interrupt
Match between the counter value and the Compare 2 register
Table 20-6. Available Interrupt Vectors and Sources in Split Mode
Name
Vector Description
Conditions
LUNF
Low-byte Underflow interrupt Low byte timer reaches BOTTOM
HUNF
High-byte Underflow interrupt High byte timer reaches BOTTOM
LCMP0 Compare Channel 0 interrupt
Match between the counter value and the low byte of the Compare 0
register
LCMP1 Compare Channel 1 interrupt
Match between the counter value and the low byte of the Compare 1
register
LCMP2 Compare Channel 2 interrupt
Match between the counter value and the low byte of the Compare 2
register
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
20.3.6
Sleep Mode Operation
The timer/counter will continue operation in Idle sleep mode.
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20.4
Register Summary - Normal Mode
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
...
0x0D
0x0E
0x0F
0x10
...
0x1F
CTRLA
CTRLB
CTRLC
CTRLD
CTRLECLR
CTRLESET
CTRLFCLR
CTRLFSET
Reserved
EVCTRL
INTCTRL
INTFLAGS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0x20
CNT
0x22
...
0x25
Reserved
0x26
PER
0x28
CMP0
0x2A
CMP1
0x2C
CMP2
0x2E
...
0x35
Reserved
0x36
PERBUF
0x38
CMP0BUF
0x3A
CMP1BUF
0x3C
CMP2BUF
20.5
7
7:0
7:0
7:0
6
5
4
3
CMP2EN
CMP1EN
CMP0EN
ALUPD
2
1
CLKSEL[2:0]
CMP2OV
CMD[1:0]
CMD[1:0]
CMP2BV
CMP1BV
CMP2BV
CMP1BV
EVACT[2:0]
CMP2
CMP2
CMP1
CMP1
CMP0
CMP0
0
ENABLE
WGMODE[2:0]
CMP1OV
LUPD
LUPD
CMP0BV
CMP0BV
CMP0OV
SPLITM
DIR
DIR
PERBV
PERBV
CNTEI
OVF
OVF
Reserved
DBGCTRL
TEMP
7:0
7:0
TEMP[7:0]
DBGRUN
7:0
15:8
CNT[7:0]
CNT[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
PER[7:0]
PER[15:8]
CMP[7:0]
CMP[15:8]
CMP[7:0]
CMP[15:8]
CMP[7:0]
CMP[15:8]
Reserved
7:0
PERBUF[7:0]
15:8
7:0
15:8
7:0
15:8
7:0
15:8
PERBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
Register Description - Normal Mode
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20.5.1
Control A - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
-
6
5
Access
Reset
4
3
R/W
0
2
CLKSEL[2:0]
R/W
0
1
R/W
0
0
ENABLE
R/W
0
Bits 3:1 – CLKSEL[2:0] Clock Select
This bit field selects the clock frequency for the timer/counter.
Value
Name
Description
0x0
DIV1
fTCA = fCLK_PER
0x1
DIV2
fTCA = fCLK_PER/2
0x2
DIV4
fTCA = fCLK_PER/4
0x3
DIV8
fTCA = fCLK_PER/8
0x4
DIV16
fTCA = fCLK_PER/16
0x5
DIV64
fTCA = fCLK_PER/64
0x6
DIV256
fTCA = fCLK_PER/256
0x7
DIV1024
fTCA = fCLK_PER/1024
Bit 0 – ENABLE Enable
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
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20.5.2
Control B - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
7
Access
Reset
CTRLB
0x01
0x00
-
6
CMP2EN
R/W
0
5
CMP1EN
R/W
0
4
CMP0EN
R/W
0
3
ALUPD
R/W
0
2
R/W
0
1
WGMODE[2:0]
R/W
0
0
R/W
0
Bits 4, 5, 6 – CMPEN Compare n Enable
In the FRQ and PWM Waveform Generation modes, the Compare n Enable (CMPnEN) bits will make the waveform
output available on the pin corresponding to WOn, overriding the value in the corresponding PORT output register.
The corresponding pin direction must be configured as an output in the PORT peripheral.
Value
Description
0
Waveform output WOn will not be available on the corresponding pin
1
Waveform output WOn will override the output value of the corresponding pin
Bit 3 – ALUPD Auto-Lock Update
The Auto-Lock Update bit controls the Lock Update (LUPD) bit in the TCAn.CTRLE register. When ALUPD is written
to ‘1’, the LUPD bit will be set to ‘1’ until the Buffer Valid (CMPnBV) bits of all enabled compare channels are ‘1’. This
condition will clear the LUPD bit.
It will remain cleared until the next UPDATE condition, where the buffer values will be transferred to the CMPn
registers, and the LUPD bit will be set to ‘1’ again. This makes sure that the CMPnBUF register values are not
transferred to the CMPn registers until all enabled compare buffers are written.
Value
Description
0
LUPD bit in the TCAn.CTRLE register is not altered by the system
1
LUPD bit in the TCAn.CTRLE register is set and cleared automatically
Bits 2:0 – WGMODE[2:0] Waveform Generation Mode
This bit field selects the Waveform Generation mode and controls the counting sequence of the counter, TOP value,
UPDATE condition, Interrupt condition, and the type of waveform generated.
No waveform generation is performed in the Normal mode of operation. For all other modes, the waveform generator
output will only be directed to the port pins if the corresponding CMPnEN bit has been set. The port pin direction must
be set as output.
Table 20-7. Timer Waveform Generation Mode
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Group Configuration
NORMAL
FRQ
SINGLESLOPE
DSTOP
DSBOTH
DSBOTTOM
Mode of Operation
Normal
Frequency
Reserved
Single-slope PWM
Reserved
Dual-slope PWM
Dual-slope PWM
Dual-slope PWM
TOP
UPDATE
OVF
PER
CMP0
PER
PER
PER
PER
TOP(1)
TOP(1)
TOP(1)
BOTTOM
TOP
TOP and BOTTOM
BOTTOM
TOP(1)
BOTTOM
BOTTOM
BOTTOM
BOTTOM
Note:
1. When counting up.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.3
Control C - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
7
CTRLC
0x02
0x00
-
6
5
4
3
Access
Reset
2
CMP2OV
R/W
0
1
CMP1OV
R/W
0
0
CMP0OV
R/W
0
Bit 2 – CMP2OV Compare Output Value 2
See CMP0OV.
Bit 1 – CMP1OV Compare Output Value 1
See CMP0OV.
Bit 0 – CMP0OV Compare Output Value 0
The CMPnOV bits allow direct access to the waveform generator’s output compare value when the timer/counter is
not enabled. This is used to set or clear the WG output value when the timer/counter is not running.
Note: When the output is connected to the pad, overriding these bits will not work unless the CMPnEN bits in
the TCAn.CTRLB register have been set. If the output is connected to CCL, the CMPnEN bits in the TCAn.CTRLB
register are bypassed.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.4
Control D - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
7
CTRLD
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
0
SPLITM
R/W
0
Bit 0 – SPLITM Enable Split Mode
This bit sets the timer/counter in Split mode operation and will work as two 8-bit timer/counters. The register map will
change compared to the normal 16-bit mode.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.5
Control Register E Clear - Normal Mode
Name:
Offset:
Reset:
Property:
CTRLECLR
0x04
0x00
-
Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 3:2 – CMD[1:0] Command
This bit field is used for software control of update, restart, and Reset of the timer/counter. The command bit field is
always read as ‘0’.
Value
Name
Description
0x0
NONE
No command
0x1
UPDATE
Force update
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if the timer/counter is enabled)
Bit 1 – LUPD Lock Update
Lock update can be used to ensure that all buffers are valid before an update is performed.
Value
Description
0
The buffered registers are updated as soon as an UPDATE condition has occurred
1
No update of the buffered registers is performed, even though an UPDATE condition has occurred.
This setting will not prevent an update issued by the Command bit field.
Bit 0 – DIR Counter Direction
Normally this bit is controlled in hardware by the Waveform Generation mode or by event actions, but can also be
changed from the software.
Value
Description
0
The counter is counting up (incrementing)
1
The counter is counting down (decrementing)
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.6
Control Register E Set - Normal Mode
Name:
Offset:
Reset:
Property:
CTRLESET
0x05
0x00
-
Use this register instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit location.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 3:2 – CMD[1:0] Command
This bit field is used for software control of update, restart, and Reset of the timer/counter. The command bit field is
always read as ‘0’.
Value
Name
Description
0x0
NONE
No command
0x1
UPDATE
Force update
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if the timer/counter is enabled)
Bit 1 – LUPD Lock Update
Locking the update ensures that all buffers are valid before an update is performed.
Value
Description
0
The buffered registers are updated as soon as an UPDATE condition has occurred
1
No update of the buffered registers is performed, even though an UPDATE condition has occurred.
This setting will not prevent an update issued by the Command bit field.
Bit 0 – DIR Counter Direction
Normally this bit is controlled in hardware by the Waveform Generation mode or by event actions, but can also be
changed from the software.
Value
Description
0
The counter is counting up (incrementing)
1
The counter is counting down (decrementing)
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.7
Control Register F Clear
Name:
Offset:
Reset:
Property:
CTRLFCLR
0x06
0x00
-
Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.
Bit
7
6
5
Access
Reset
4
3
CMP2BV
R/W
0
2
CMP1BV
R/W
0
1
CMP0BV
R/W
0
0
PERBV
R/W
0
Bit 3 – CMP2BV Compare 2 Buffer Valid
See CMP0BV.
Bit 2 – CMP1BV Compare 1 Buffer Valid
See CMP0BV.
Bit 1 – CMP0BV Compare 0 Buffer Valid
The CMPnBV bits are set when a new value is written to the corresponding TCAn.CMPnBUF register. These bits are
automatically cleared on an UPDATE condition.
Bit 0 – PERBV Period Buffer Valid
This bit is set when a new value is written to the TCAn.PERBUF register. This bit is automatically cleared on an
UPDATE condition.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.8
Control Register F Set
Name:
Offset:
Reset:
Property:
CTRLFSET
0x07
0x00
-
Use this register instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit location.
Bit
7
6
5
Access
Reset
4
3
CMP2BV
R/W
0
2
CMP1BV
R/W
0
1
CMP0BV
R/W
0
0
PERBV
R/W
0
Bit 3 – CMP2BV Compare 2 Buffer Valid
See CMP0BV.
Bit 2 – CMP1BV Compare 1 Buffer Valid
See CMP0BV.
Bit 1 – CMP0BV Compare 0 Buffer Valid
The CMPnBV bits are set when a new value is written to the corresponding TCAn.CMPnBUF register. These bits are
automatically cleared on an UPDATE condition.
Bit 0 – PERBV Period Buffer Valid
This bit is set when a new value is written to the TCAn.PERBUF register. This bit is automatically cleared on an
UPDATE condition.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x09
0x00
-
6
Access
Reset
5
4
3
R/W
0
2
EVACT[2:0]
R/W
0
1
R/W
0
0
CNTEI
R/W
0
Bits 3:1 – EVACT[2:0] Event Action
This bit field defines what action the counter will take upon certain event conditions.
Value
Name
Description
0x0
EVACT_POSEDGE Count on positive event edge
0x1
EVACT_ANYEDGE Count on any event edge
0x2
EVACT_HIGHLVL Count prescaled clock cycles while the event signal is high
0x3
EVACT_UPDOWN Count prescaled clock cycles. The event signal controls the count direction, up
when low and down when high. The direction is latched when the counter counts.
Other
Reserved
Bit 0 – CNTEI Enable Count on Event Input
Value
Description
0
Count on Event input is disabled
1
Count on Event input is enabled according to EVACT bit field
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.10 Interrupt Control Register - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INTCTRL
0x0A
0x00
-
6
CMP2
R/W
0
5
CMP1
R/W
0
4
CMP0
R/W
0
3
2
1
0
OVF
R/W
0
Bit 6 – CMP2 Compare Channel 2 Interrupt Enable
See CMP0.
Bit 5 – CMP1 Compare Channel 1 Interrupt Enable
See CMP0.
Bit 4 – CMP0 Compare Channel 0 Interrupt Enable
Writing the CMPn bit to ‘1’ enables the interrupt from Compare Channel n.
Bit 0 – OVF Timer Overflow/Underflow Interrupt Enable
Writing the OVF bit to ‘1’ enables the overflow/underflow interrupt.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.11 Interrupt Flag Register - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INTFLAGS
0x0B
0x00
-
6
CMP2
R/W
0
5
CMP1
R/W
0
4
CMP0
R/W
0
3
2
1
0
OVF
R/W
0
Bit 6 – CMP2 Compare Channel 2 Interrupt Flag
See the CMP0 flag description.
Bit 5 – CMP1 Compare Channel 1 Interrupt Flag
See the CMP0 flag description.
Bit 4 – CMP0 Compare Channel 0 Interrupt Flag
The Compare Interrupt (CMPn) flag is set on a compare match on the corresponding compare channel.
For all modes of operation, the CMPn flag will be set when a compare match occurs between the Count (TCAn.CNT)
register and the corresponding Compare n (TCAn.CMPn) register. The CMPn flag is not cleared automatically. It will
be cleared only by writing a ‘1’ to its bit location.
Bit 0 – OVF Overflow/Underflow Interrupt Flag
This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting.
The OVF flag is not cleared automatically. It will be cleared only by writing a ‘1’ to its bit location.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.12 Debug Control Register - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0E
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Run in Debug
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.13 Temporary Bits for 16-Bit Access
Name:
Offset:
Reset:
Property:
TEMP
0x0F
0x00
-
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary Bits for 16-bit Access
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.14 Counter Register - Normal Mode
Name:
Offset:
Reset:
Property:
CNT
0x20
0x00
-
The TCAn.CNTL and TCAn.CNTH register pair represents the 16-bit value, TCAn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CNT[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CNT[15:8] Counter High Byte
This bit field holds the MSB of the 16-bit Counter register.
Bits 7:0 – CNT[7:0] Counter Low Byte
This bit field holds the LSB of the 16-bit Counter register.
© 2021 Microchip Technology Inc.
Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.15 Period Register - Normal Mode
Name:
Offset:
Reset:
Property:
PER
0x26
0xFFFF
-
The TCAn.PER register contains the 16-bit TOP value in the timer/counter in all modes of operation, except
Frequency Waveform Generation (FRQ).
The TCAn.PERL and TCAn.PERH register pair represents the 16-bit value, TCAn.PER. The low byte [7:0] (suffix L)
is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PER[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
PER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:8 – PER[15:8] Periodic High Byte
This bit field holds the MSB of the 16-bit Period register.
Bits 7:0 – PER[7:0] Periodic Low Byte
This bit field holds the LSB of the 16-bit Period register.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.16 Compare n Register - Normal Mode
Name:
Offset:
Reset:
Property:
CMPn
0x28 + n*0x02 [n=0..2]
0x00
-
This register is continuously compared to the counter value. Normally, the outputs from the comparators are used to
generate waveforms.
The TCAn.CMPn registers are updated with the buffer value from their corresponding TCAn.CMPnBUF register when
an UPDATE condition occurs.
The TCAn.CMPnL and TCAn.CMPnH register pair represents the 16-bit value, TCAn.CMPn. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CMP[15:8] Compare High Byte
This bit field holds the MSB of the 16-bit Compare register.
Bits 7:0 – CMP[7:0] Compare Low Byte
This bit filed holds the LSB of the 16-bit Compare register.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.17 Period Buffer Register
Name:
Offset:
Reset:
Property:
PERBUF
0x36
0xFFFF
-
This register serves as the buffer for the Period (TCAn.PER) register. Writing to this register from the CPU or UPDI
will set the Period Buffer Valid (PERBV) bit in the TCAn.CTRLF register.
The TCAn.PERBUFL and TCAn.PERBUFH register pair represents the 16-bit value, TCAn.PERBUF. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
12
11
PERBUF[15:8]
R/W
R/W
1
1
4
3
PERBUF[7:0]
R/W
R/W
1
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 15:8 – PERBUF[15:8] Period Buffer High Byte
This bit field holds the MSB of the 16-bit Period Buffer register.
Bits 7:0 – PERBUF[7:0] Period Buffer Low Byte
This bit field holds the LSB of the 16-bit Period Buffer register.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.5.18 Compare n Buffer Register
Name:
Offset:
Reset:
Property:
CMPnBUF
0x38 + n*0x02 [n=0..2]
0x00
-
This register serves as the buffer for the associated Compare n (TCAn.CMPn) register. Writing to this register from
the CPU or UPDI will set the Compare Buffer valid (CMPnBV) bit in the TCAn.CTRLF register.
The TCAn.CMPnBUFL and TCAn.CMPnBUFH register pair represents the 16-bit value, TCAn.CMPnBUF. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset +
0x01.
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
CMPBUF[15:8]
R/W
R/W
0
0
4
3
CMPBUF[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CMPBUF[15:8] Compare High Byte
This bit field holds the MSB of the 16-bit Compare Buffer register.
Bits 7:0 – CMPBUF[7:0] Compare Low Byte
This bit field holds the LSB of the 16-bit Compare Buffer register.
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.6
Register Summary - Split Mode
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
...
0x09
0x0A
0x0B
0x0C
...
0x0D
0x0E
0x0F
...
0x1F
0x20
0x21
0x22
...
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
CTRLA
CTRLB
CTRLC
CTRLD
CTRLECLR
CTRLESET
7:0
7:0
7:0
7:0
7:0
7:0
20.7
7
6
5
4
3
HCMP2EN
HCMP2OV
HCMP1EN
HCMP1OV
HCMP0EN
HCMP0OV
2
1
CLKSEL[2:0]
LCMP2EN
LCMP2OV
LCMP1EN
LCMP1OV
CMD[1:0]
CMD[1:0]
0
ENABLE
LCMP0EN
LCMP0OV
SPLITM
CMDEN[1:0]
CMDEN[1:0]
Reserved
INTCTRL
INTFLAGS
7:0
7:0
LCMP2
LCMP2
LCMP1
LCMP1
LCMP0
LCMP0
HUNF
HUNF
LUNF
LUNF
Reserved
DBGCTRL
7:0
DBGRUN
Reserved
LCNT
HCNT
7:0
7:0
LCNT[7:0]
HCNT[7:0]
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
LPER[7:0]
HPER[7:0]
LCMP[7:0]
HCMP[7:0]
LCMP[7:0]
HCMP[7:0]
LCMP[7:0]
HCMP[7:0]
Reserved
LPER
HPER
LCMP0
HCMP0
LCMP1
HCMP1
LCMP2
HCMP2
Register Description - Split Mode
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Complete Datasheet
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.7.1
Control A - Split Mode
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
-
6
5
Access
Reset
4
3
R/W
0
2
CLKSEL[2:0]
R/W
0
1
R/W
0
0
ENABLE
R/W
0
Bits 3:1 – CLKSEL[2:0] Clock Select
This bit field selects the clock frequency for the timer/counter.
Value
Name
Description
0x0
DIV1
fTCA = fCLK_PER
0x1
DIV2
fTCA = fCLK_PER/2
0x2
DIV4
fTCA = fCLK_PER/4
0x3
DIV8
fTCA = fCLK_PER/8
0x4
DIV16
fTCA = fCLK_PER/16
0x5
DIV64
fTCA = fCLK_PER/64
0x6
DIV256
fTCA = fCLK_PER/256
0x7
DIV1024
fTCA = fCLK_PER/1024
Bit 0 – ENABLE Enable
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
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ATmega808/809/1608/1609
TCA - 16-bit Timer/Counter Type A
20.7.2
Control B - Split Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLB
0x01
0x00
-
6
HCMP2EN
R/W
0
5
HCMP1EN
R/W
0
4
HCMP0EN
R/W
0
3
2
LCMP2EN
R/W
0
1
LCMP1EN
R/W
0
0
LCMP0EN
R/W
0
Bit 6 – HCMP2EN High byte Compare 2 Enable
See HCMP0EN.
Bit 5 – HCMP1EN High byte Compare 1 Enable
See HCMP0EN.
Bit 4 – HCMP0EN High byte Compare 0 Enable
Setting the HCMPnEN bit in the FRQ or PWM Waveform Generation mode of operation will override the port output
register for the corresponding WO[n+3] pin.
Bit 2 – LCMP2EN Low byte Compare 2 Enable
See LCMP0EN.
Bit 1 – LCMP1EN Low byte Compare 1 Enable
See LCMP0EN.
Bit 0 – LCMP0EN Low byte Compare 0 Enable
Setting the LCMPnEN bit in the FRQ or PWM Waveform Generation mode of operation will override the port output
register for the corresponding WOn pin.
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TCA - 16-bit Timer/Counter Type A
20.7.3
Control C - Split Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLC
0x02
0x00
-
6
HCMP2OV
R/W
0
5
HCMP1OV
R/W
0
4
HCMP0OV
R/W
0
3
2
LCMP2OV
R/W
0
1
LCMP1OV
R/W
0
0
LCMP0OV
R/W
0
Bit 6 – HCMP2OV High byte Compare 2 Output Value
See HCMP0OV.
Bit 5 – HCMP1OV High byte Compare 1 Output Value
See HCMP0OV.
Bit 4 – HCMP0OV High byte Compare 0 Output Value
The HCMPnOV bit allows direct access to the output compare value of the waveform generator when the timer/
counter is not enabled. This is used to set or clear the WO[n+3] output value when the timer/counter is not running.
Bit 2 – LCMP2OV Low byte Compare 2 Output Value
See LCMP0OV.
Bit 1 – LCMP1OV Low byte Compare 1 Output Value
See LCMP0OV.
Bit 0 – LCMP0OV Low byte Compare 0 Output Value
The LCMPnOV bit allows direct access to the output compare value of the waveform generator when the timer/
counter is not enabled. This is used to set or clear the WOn output value when the timer/counter is not running.
Note: When the output is connected to the pad, overriding these bits will not work unless the xCMPnEN bits in
the TCAn.CTRLB register have been set. If the output is connected to CCL, the xCMPnEN bits in the TCAn.CTRLB
register are bypassed.
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TCA - 16-bit Timer/Counter Type A
20.7.4
Control D - Split Mode
Name:
Offset:
Reset:
Property:
Bit
7
CTRLD
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
0
SPLITM
R/W
0
Bit 0 – SPLITM Enable Split Mode
This bit sets the timer/counter in Split mode operation and will work as two 8-bit timer/counters. The register map will
change compared to the normal 16-bit mode.
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TCA - 16-bit Timer/Counter Type A
20.7.5
Control Register E Clear - Split Mode
Name:
Offset:
Reset:
Property:
CTRLECLR
0x04
0x00
-
Use this register instead of a Read-Modify-Write (RMW) to clear individual bits by writing a ‘1’ to its bit location.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
0
CMDEN[1:0]
R/W
R/W
0
0
Bits 3:2 – CMD[1:0] Command
This bit field is used for software control of restart and reset of the timer/counter. The command bit field is always
read as ‘0’.
Value
Name
Description
0x0
NONE
No command
0x1
Reserved
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if the timer/counter is enabled)
Bits 1:0 – CMDEN[1:0] Command Enable
This bit field configures what timer/counters the command given by the CMD-bits will be applied to.
Value
Name
Description
0x0
NONE None
0x1
Reserved
0x2
Reserved
0x3
BOTH
Command (CMD) will be applied to both low byte and high byte timer/counter
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TCA - 16-bit Timer/Counter Type A
20.7.6
Control Register E Set - Split Mode
Name:
Offset:
Reset:
Property:
CTRLESET
0x05
0x00
-
Use this register instead of a Read-Modify-Write (RMW) to set individual bits by writing a ‘1’ to its bit location.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
0
CMDEN[1:0]
R/W
R/W
0
0
Bits 3:2 – CMD[1:0] Command
This bit field is used for software control of restart and reset of the timer/counter. The command bit field is always
read as ‘0’. The CMD bit field must be used together with the Command Enable (CMDEN) bits. Using the RESET
command requires that both low byte and high byte timer/counter are selected with CMDEN.
Value
Name
Description
0x0
NONE
No command
0x1
Reserved
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if the timer/counter is enabled)
Bits 1:0 – CMDEN[1:0] Command Enable
This bit field configures what timer/counters the command given by the CMD-bits will be applied to.
Value
Name
Description
0x0
NONE None
0x1
Reserved
0x2
Reserved
0x3
BOTH
Command (CMD) will be applied to both low byte and high byte timer/counter
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TCA - 16-bit Timer/Counter Type A
20.7.7
Interrupt Control Register - Split Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INTCTRL
0x0A
0x00
-
6
LCMP2
R/W
0
5
LCMP1
R/W
0
4
LCMP0
R/W
0
3
2
1
HUNF
R/W
0
0
LUNF
R/W
0
Bit 6 – LCMP2 Low byte Compare Channel 2 Interrupt Enable
See LCMP0.
Bit 5 – LCMP1 Low byte Compare Channel 1 Interrupt Enable
See LCMP0.
Bit 4 – LCMP0 Low byte Compare Channel 0 Interrupt Enable
Writing the LCMPn bit to ‘1’ enables the low byte Compare Channel n interrupt.
Bit 1 – HUNF High byte Underflow Interrupt Enable
Writing the HUNF bit to ‘1’ enables the high byte underflow interrupt.
Bit 0 – LUNF Low byte Underflow Interrupt Enable
Writing the LUNF bit to ‘1’ enables the low byte underflow interrupt.
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TCA - 16-bit Timer/Counter Type A
20.7.8
Interrupt Flag Register - Split Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INTFLAGS
0x0B
0x00
-
6
LCMP2
R/W
0
5
LCMP1
R/W
0
4
LCMP0
R/W
0
3
2
1
HUNF
R/W
0
0
LUNF
R/W
0
Bit 6 – LCMP2 Low byte Compare Channel 2 Interrupt Flag
See LCMP0 flag description.
Bit 5 – LCMP1 Low byte Compare Channel 1 Interrupt Flag
See LCMP0 flag description.
Bit 4 – LCMP0 Low byte Compare Channel 0 Interrupt Flag
The Low byte Compare Interrupt (LCMPn) flag is set on a compare match on the corresponding compare channel in
the low byte timer.
For all modes of operation, the LCMPn flag will be set when a compare match occurs between the Low Byte Timer
Counter (TCAn.LCNT) register and the corresponding Compare n (TCAn.LCMPn) register. The LCMPn flag will not
be cleared automatically and has to be cleared by software. This is done by writing a ‘1’ to its bit location.
Bit 1 – HUNF High byte Underflow Interrupt Flag
This flag is set on a high byte timer BOTTOM (underflow) condition. HUNF is not automatically cleared and needs to
be cleared by software. This is done by writing a ‘1’ to its bit location.
Bit 0 – LUNF Low byte Underflow Interrupt Flag
This flag is set on a low byte timer BOTTOM (underflow) condition. LUNF is not automatically cleared and needs to
be cleared by software. This is done by writing a ‘1’ to its bit location.
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TCA - 16-bit Timer/Counter Type A
20.7.9
Debug Control Register - Split Mode
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0E
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Run in Debug
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
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TCA - 16-bit Timer/Counter Type A
20.7.10 Low Byte Timer Counter Register - Split Mode
Name:
Offset:
Reset:
Property:
LCNT
0x20
0x00
-
The TCAn.LCNT register contains the counter value for the low byte timer. CPU and UPDI write access has priority
over count, clear or reload of the counter.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LCNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LCNT[7:0] Counter Value for Low Byte Timer
This bit field defines the counter value of the low byte timer.
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TCA - 16-bit Timer/Counter Type A
20.7.11 High Byte Timer Counter Register - Split Mode
Name:
Offset:
Reset:
Property:
HCNT
0x21
0x00
-
The TCAn.HCNT register contains the counter value for the high byte timer. CPU and UPDI write access has priority
over count, clear or reload of the counter.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
HCNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – HCNT[7:0] Counter Value for High Byte Timer
This bit field defines the counter value in high byte timer.
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TCA - 16-bit Timer/Counter Type A
20.7.12 Low Byte Timer Period Register - Split Mode
Name:
Offset:
Reset:
Property:
LPER
0x26
0xFF
-
The TCAn.LPER register contains the TOP value for the low byte timer.
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
LPER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – LPER[7:0] Period Value Low Byte Timer
This bit field holds the TOP value for the low byte timer.
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TCA - 16-bit Timer/Counter Type A
20.7.13 High Byte Period Register - Split Mode
Name:
Offset:
Reset:
Property:
HPER
0x27
0xFF
-
The TCAn.HPER register contains the TOP value for the high byte timer.
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
HPER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – HPER[7:0] Period Value High Byte Timer
This bit field holds the TOP value for the high byte timer.
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TCA - 16-bit Timer/Counter Type A
20.7.14 Compare Register n For Low Byte Timer - Split Mode
Name:
Offset:
Reset:
Property:
LCMPn
0x28 + n*0x02 [n=0..2]
0x00
-
The TCAn.LCMPn register represents the compare value of Compare Channel n for the low byte timer. This register
is continuously compared to the counter value of the low byte timer, TCAn.LCNT. Normally, the outputs from the
comparators are then used to generate waveforms.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LCMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LCMP[7:0] Compare Value of Channel n
This bit field holds the compare value of channel n that is compared to TCAn.LCNT.
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TCA - 16-bit Timer/Counter Type A
20.7.15 High Byte Compare Register n - Split Mode
Name:
Offset:
Reset:
Property:
HCMPn
0x29 + n*0x02 [n=0..2]
0x00
-
The TCAn.HCMPn register represents the compare value of Compare Channel n for the high byte timer. This register
is continuously compared to the counter value of the high byte timer, TCAn.HCNT. Normally, the outputs from the
comparators are then used to generate waveforms.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
HCMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – HCMP[7:0] Compare Value of Channel n
This bit field holds the compare value of channel n that is compared to TCAn.HCNT.
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TCB - 16-Bit Timer/Counter Type B
21.
TCB - 16-Bit Timer/Counter Type B
21.1
Features
•
•
•
21.2
16-Bit Counter Operation Modes:
– Periodic interrupt
– Time-out check
– Input capture
• On event
• Frequency measurement
• Pulse-width measurement
• Frequency and pulse-width measurement
– Single-shot
– 8-bit Pulse-Width Modulation (PWM)
Noise Canceler on Event Input
Synchronize Operation with TCAn
Overview
The capabilities of the 16-bit Timer/Counter type B (TCB) include frequency and waveform generation and input
capture on event with time and frequency measurement of digital signals. The TCB consists of a base counter and
control logic that can be set in one of eight different modes, each mode providing unique functionality. The base
counter is clocked by the peripheral clock with optional prescaling.
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TCB - 16-Bit Timer/Counter Type B
21.2.1
Block Diagram
Figure 21-1. Timer/Counter Type B Block
Clock Select
CTRLA
Mode
CTRLB
EVCTRL
Event Action
Count
Counter
CNT
Events
Control
Logic
Clear
CAPT
(Interrupt Request
and Events)
BOTTOM
=0
CCMP
=
Waveform
Generation
Match
WO
The timer/counter can be clocked from the Peripheral Clock (CLK_PER) or a 16-bit Timer/Counter type A
(CLK_TCAn).
Figure 21-2. Timer/Counter Clock Logic
CTRLA
CLK_PER
DIV2
CLK_TCB
CNT
CLK_TCAn
Control
Logic
Events
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TCB - 16-Bit Timer/Counter Type B
The Clock Select (CLKSEL) bit field in the Control A (TCBn.CTRLA) register selects one of the prescaler outputs
directly as the clock (CLK_TCB) input.
Setting the timer/counter to use the clock from a TCAn allows the timer/counter to run in sync with that TCAn.
By using the EVSYS, any event source, such as an external clock signal on any I/O pin, may be used as a control
logic input. When an event action controlled operation is used, the clock selection must be set to use an event
channel as the counter input.
21.2.2
Signal Description
Signal
Description
Type
WO
Digital Asynchronous Output
Waveform Output
21.3
Functional Description
21.3.1
Definitions
The following definitions are used throughout the documentation:
Table 21-1. Timer/Counter Definitions
Name
Description
BOTTOM
The counter reaches BOTTOM when it becomes 0x0000
MAX
The counter reaches the maximum when it becomes 0xFFFF
TOP
The counter reaches TOP when it becomes equal to the highest value in the count sequence
CNT
Count (TCBn.CNT) register value
CCMP
Capture/Compare (TCBn.CCMP) register value
Note: In general, the term ‘timer’ is used when the timer/counter is counting periodic clock ticks. The term ‘counter’
is used when the input signal has sporadic or irregular ticks.
21.3.2
Initialization
By default, the TCB is in Periodic Interrupt mode. Follow these steps to start using it:
1. Write a TOP value to the Compare/Capture (TCBn.CCMP) register.
2. Optional: Write the Compare/Capture Output Enable (CCMPEN) bit in the Control B (TCBn.CTRLB) register
to ‘1’. This will make the waveform output available on the corresponding pin, overriding the value in the
corresponding PORT output register.
3. Enable the counter by writing a ‘1’ to the ENABLE bit in the Control A (TCBn.CTRLA) register.
The counter will start counting clock ticks according to the prescaler setting in the Clock Select (CLKSEL) bit
field in the Control A (TCBn.CTRLA) register.
4. The counter value can be read from the Count (TCBn.CNT) register. The peripheral will generate a CAPT
interrupt and event when the CNT value reaches TOP.
4.1.
If the Compare/Capture register is modified to a value lower than the current Count register, the
peripheral will count to MAX and wrap around.
21.3.3
Operation
21.3.3.1 Modes
The timer can be configured to run in one of the eight different modes described in the sections below. The event
pulse needs to be longer than one system clock cycle to ensure edge detection.
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TCB - 16-Bit Timer/Counter Type B
21.3.3.1.1 Periodic Interrupt Mode
In the Periodic Interrupt mode, the counter counts to the capture value and restarts from BOTTOM. A CAPT interrupt
and event is generated when the counter is equal to TOP. If TOP is updated to a value lower than count upon
reaching MAX, the counter restarts from BOTTOM.
Figure 21-3. Periodic Interrupt Mode
CAPT
(Interrupt Request
MAX
and Event)
TOP
CNT
BOTTOM
TOP changed to
a value lower than CNT
CNT set to BOTTOM
21.3.3.1.2 Time-Out Check Mode
In the Time-Out Check mode, the peripheral starts counting on the first signal edge and stops on the next signal
edge detected on the event input channel. Start or Stop edge is determined by the Event Edge (EDGE) bit in the
Event Control (TCBn.EVCTRL) register. If the Count (TCBn.CNT) register reaches TOP before the second edge, a
CAPT interrupt and event will be generated. In Freeze state, after a Stop edge is detected, the counter will restart
on a new Start edge. If TOP is updated to a value lower than the Count (TCBn.CNT) register upon reaching MAX
the counter restarts from BOTTOM. Reading the Count (TCBn.CNT) register or Compare/Capture (TCBn.CCMP)
register, or writing the Run (RUN) bit in the Status (TCBn.STATUS) register in Freeze state will have no effect.
This mode requires TCB to be configured as an event user and is explained in the Events section.
Figure 21-4. Time-Out Check Mode
Event Input
CAPT
(Interrupt Request
and Event)
Event Detector
MAX
TOP
CNT
BOTTOM
TOP changed to a value lower
than CNT
CNT set to
BOTTOM
21.3.3.1.3 Input Capture on Event Mode
In the Input Capture on Event mode, the counter will count from BOTTOM to MAX continuously. When an event is
detected, the Count (TCBn.CNT) register value is transferred to the Compare/Capture (TCBn.CCMP) register, and a
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TCB - 16-Bit Timer/Counter Type B
CAPT interrupt and event is generated. The Event edge detector that can be configured to trigger a capture on either
rising or falling edges.
This mode requires TCB to be configured as an event user and is explained in the Events section.
The figure below shows the input capture unit configured to capture on the falling edge of the event input signal. The
CAPT Interrupt flag is automatically cleared after the low byte of the Compare/Capture (TCBn.CCMP) register has
been read.
Figure 21-5. Input Capture on Event
Event Input
CAPT
(Interrupt Request
and Event)
Event Detector
MAX
CNT
BOTTOM
Copy CNT to
CCMP and CAPT
CNT set to
BOTTOM
Copy CNT to
CCMP and CAPT
Important: It is recommended to write 0x0000 to the Count (TCBn.CNT) register when entering this
mode from any other mode.
21.3.3.1.4 Input Capture Frequency Measurement Mode
In the Input Capture Frequency Measurement mode, the TCB captures the counter value and restarts on either a
positive or negative edge of the event input signal.
The CAPT Interrupt flag is automatically cleared after the low byte of the Compare/Capture (TCBn.CCMP) register
has been read.
The figure below illustrates this mode when configured to act on the rising edge.
This mode requires TCB to be configured as an event user and is explained in the Events section.
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TCB - 16-Bit Timer/Counter Type B
Figure 21-6. Input Capture Frequency Measurement
CAPT
(Interrupt Request
Event Input
and Event)
Event Detector
MAX
CNT
BOTTOM
CNT set to
BOTTOM
Copy CNT to CCMP,
CAPT and restart
Copy CNT to CCMP,
CAPT and restart
21.3.3.1.5 Input Capture Pulse-Width Measurement Mode
In the Input Capture Pulse-Width Measurement mode, the input capture pulse-width measurement will restart the
counter on a positive edge and capture on the next falling edge before an interrupt request is generated. The CAPT
Interrupt flag is automatically cleared after the low byte of the Compare/Capture (TCBn.CCMP) register has been
read. The timer will automatically switch between rising and falling edge detection, but a minimum edge separation of
two clock cycles is required for correct behavior.
This mode requires TCB to be configured as an event user and is explained in the Events section.
Figure 21-7. Input Capture Pulse-Width Measurement
CAPT
Event Input
(Interrupt Request
and Event)
Edge Detector
MAX
CNT
BOTTOM
Start counter
Copy CNT to
CCMP and CAPT
Restart
counter
Copy CNT to
CCMP and CAPT
CNT set to
BOTTOM
21.3.3.1.6 Input Capture Frequency and Pulse-Width Measurement Mode
In the Input Capture Frequency and Pulse-Width Measurement mode, the timer will start counting when a positive
edge is detected on the event input signal. The count value is captured on the following falling edge. The counter
stops when the second rising edge of the event input signal is detected, which will set the interrupt flag.
The CAPT Interrupt flag is automatically cleared after the low byte of the Compare/Capture (TCBn.CCMP) register
has been read, and the timer/counter is ready for a new capture sequence. Therefore, the Count (TCBn.CNT)
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TCB - 16-Bit Timer/Counter Type B
register must be read before the Compare/Capture (TCBn.CCMP) register since it is reset to BOTTOM at the next
positive edge of the event input signal.
This mode requires TCB to be configured as an event user and is explained in the Events section.
Figure 21-8. Input Capture Frequency and Pulse-Width Measurement
Ignored until CPU
reads CCMP register
Trigger next capture
sequence
CAPT
(Interrupt Request
Event Input
and Event)
Event Detector
MAX
CNT
BOTTOM
Start
counter
Copy CNT to
CCMP
Stop counter and
CAPT
CPU reads the
CCMP register
21.3.3.1.7 Single-Shot Mode
The Single-Shot mode can be used to generate a pulse with a duration defined by the Compare (TCBn.CCMP)
register every time a rising or falling edge is observed on a connected event channel.
When the counter is stopped, the output pin is driven to low. If an event is detected on the connected event channel,
the timer will reset and start counting from BOTTOM to TOP while driving its output high. The RUN bit in the Status
(TCBn.STATUS) register can be read to see if the counter is counting or not. When the Counter register reaches the
CCMP register value, the counter will stop, and the output pin will go low for at least one prescaler cycle. A new event
arriving during this time will be ignored. There is a two clock-cycle delay from when the event is received until the
output is set high. When the EDGE bit of the TCB.EVCTRL register is written to ‘1’, any edge can trigger the start of
the counter. If the EDGE bit is ‘0’, only positive edges trigger the start.
The counter will start counting as soon as the module is enabled, even without triggering an event. This is prevented
by writing TOP to the Counter register. Similar behavior is seen if the Event Edge (EDGE) bit in the Event Control
(TCBn.EVCTRL) register is ‘1’ while the module is enabled. Writing TOP to the Counter register prevents this as well.
If the Event Asynchronous (ASYNC) bit in the Control B (TCBn.CTRLB) register is written to ‘1’, the timer will react
asynchronously to an incoming event. An edge on the event will immediately cause the output signal to be set. The
counter will still start counting two clock cycles after the event is received.
This mode requires TCB to be configured as an event user and is explained in the Events section.
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TCB - 16-Bit Timer/Counter Type B
Figure 21-9. Single-Shot Mode
Ignored
Ignored
CAPT
(Interrupt Request
and Event)
Edge Detector
TOP
CNT
BOTTOM
Output
Event starts
counter
Counter reaches
TOP value
Event starts
counter
Counter reaches
TOP value
21.3.3.1.8 8-Bit PWM Mode
The TCB can be configured to run in 8-bit PWM mode, where each of the register pairs in the 16-bit Compare/
Capture (TCBn.CCMPH and TCBn.CCMPL) register are used as individual Compare registers. The period (T) is
controlled by CCMPL, while CCMPH controls the duty cycle of the waveform. The counter will continuously count
from BOTTOM to CCMPL, and the output will be set at BOTTOM and cleared when the counter reaches CCMPH.
CCMPH is the number of cycles for which the output will be driven high. CCMPL+1 is the period of the output pulse.
Figure 21-10. 8-Bit PWM Mode
Period (T)
CCMPH=BOTTOM
CCMPH=TOP
CCMPH>TOP
CAPT
(Interrupt Request
and Event)
MAX
TOP
CNT
CCMPL
CCMPH
BOTTOM
Output
21.3.3.2 Output
Timer synchronization and output logic level are dependent on the selected Timer Mode (CNTMODE) bit field in
Control B (TCBn.CTRLB) register. In Single-Shot mode, the timer/counter can be configured so that the signal
generation happens asynchronously to an incoming event (ASYNC = 1 in TCBn.CTRLB). The output signal is then
set immediately at the incoming event instead of being synchronized to the TCB clock. Even though the output is
immediately set, it will take two to three CLK_TCB cycles before the counter starts counting.
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ATmega808/809/1608/1609
TCB - 16-Bit Timer/Counter Type B
Writing the Compare/Capture Output Enable (CCMPEN) bit in TCBn.CTRLB to ‘1’ enables the waveform output,
which will make the waveform output available on the corresponding pin, overriding the value in the corresponding
PORT output register.
The different configurations and their impact on the output are listed in the table below.
Table 21-2. Output Configuration
CCMPEN
CNTMODE
ASYNC
0
The output is high when
the counter starts, and the
output is low when the
counter stops
1
The output is high when
the event arrives, and the
output is low when the
counter stops
Single-Shot mode
1
0
Output
8-bit PWM mode
Not applicable
8-bit PWM mode
Other modes
Not applicable
The output initial level sets
the CCMPINIT bit in the
TCBn.CTRLB register
Not applicable
Not applicable
No output
It is not recommended to change modes while the peripheral is enabled, as this can produce an unpredictable
output. There is a possibility that an interrupt flag is set during the timer configuration. It is recommended to clear the
Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register after configuring the peripheral.
21.3.3.3 Noise Canceler
The Noise Canceler improves noise immunity by using a simple digital filter scheme. When the Noise Filter (FILTER)
bit in the Event Control (TCBn.EVCTRL) register is enabled, the peripheral monitors the event channel and keeps a
record of the last four observed samples. If four consecutive samples are equal, the input is considered to be stable,
and the signal is fed to the edge detector.
When enabled, the Noise Canceler introduces an additional delay of four system clock cycles between a change
applied to the input and the update of the Input Compare register.
The Noise Canceler uses the system clock and is, therefore, not affected by the prescaler.
21.3.3.4 Synchronized with Timer/Counter Type A
The TCB can be configured to use the clock (CLK_TCA) of a Timer/Counter type A (TCAn) by writing to the Clock
Select (CLKSEL) bit field in the Control A register (TCBn.CTRLA). In this setting, the TCB will count on the same
clock source as selected in TCAn.
When the Synchronize Update (SYNCUPD) bit in the Control A (TCBn.CTRLA) register is written to ‘1’, the TCB
counter will restart when the TCAn counter restarts.
21.3.4
Events
The TCB can generate the events described in the following table:
Table 21-3. Event Generators in TCB
Generator Name
Peripheral
TCBn
Event
Description
CAPT CAPT flag set
Event Type
Generating Clock Domain
Pulse
CLK_PER
Length of Event
One CLK_PER period
The conditions for generating the CAPT event are identical to those that will raise the corresponding interrupt flag
in the Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register. Refer to the Event System section for more details
regarding event users and Event System configuration.
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TCB - 16-Bit Timer/Counter Type B
The TCB can receive the events described in the following table:
Table 21-4. Event Users and Available Event Actions in TCB
User Name
Description
Peripheral Input
Input Detection Async/Sync
Time-Out Check Count mode
Input Capture on Event Count mode
Input Capture Frequency Measurement Count mode
TCBn
CAPT Input Capture Pulse-Width Measurement Count mode
Edge
Sync
Input Capture Frequency and Pulse-Width Measurement
Count mode
Single-Shot Count mode
Both
If the Capture Event Input Enable (CAPTEI) bit in the Event Control (TCBn.EVCTRL) register is written to ‘1’,
incoming events will result in an event action as defined by the Event Edge (EDGE) bit in the Event Control
(TCBn.EVCTRL) register and the Timer Mode (CNTMODE) bit field in Control B (TCBn.CTRLB) register. The event
needs to last for at least one CLK_PER cycle to be recognized.
If the Asynchronous mode is enabled for Single-Shot mode, the event is edge-triggered and will capture changes on
the event input shorter than one system clock cycle.
21.3.5
Interrupts
Table 21-5. Available Interrupt Vectors and Sources
Name Vector Description Conditions
CAPT TCB interrupt
Depending on the operating mode. See the description of the CAPT bit in the
TCBn.INTFLAG register.
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
21.3.6
Sleep Mode Operation
TCBn is, by default, disabled in Standby sleep mode. It will be halted as soon as the sleep mode is entered.
The module can stay fully operational in the Standby sleep mode if the Run Standby (RUNSTDBY) bit in the
TCBn.CTRLA register is written to ‘1’.
All operations are halted in Power-Down sleep mode.
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TCB - 16-Bit Timer/Counter Type B
21.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
...
0x03
0x04
0x05
0x06
0x07
0x08
0x09
CTRLA
CTRLB
EVCTRL
INTCTRL
INTFLAGS
STATUS
DBGCTRL
TEMP
0x0A
CNT
0x0C
CCMP
21.5
7
6
5
4
3
7:0
7:0
RUNSTDBY
ASYNC
CCMPINIT
SYNCUPD
CCMPEN
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
FILTER
2
1
CLKSEL[1:0]
CNTMODE[2:0]
0
ENABLE
Reserved
EDGE
CAPTEI
CAPT
CAPT
RUN
DBGRUN
TEMP[7:0]
CNT[7:0]
CNT[15:8]
CCMP[7:0]
CCMP[15:8]
Register Description
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TCB - 16-Bit Timer/Counter Type B
21.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
Access
Reset
CTRLA
0x00
0x00
-
6
RUNSTDBY
R/W
0
5
4
SYNCUPD
R/W
0
3
2
1
CLKSEL[1:0]
R/W
R/W
0
0
0
ENABLE
R/W
0
Bit 6 – RUNSTDBY Run in Standby
Writing a ‘1’ to this bit will enable the peripheral to run in Standby Sleep mode. Not applicable when CLKSEL is set to
0x2 (CLK_TCA).
Bit 4 – SYNCUPD Synchronize Update
When this bit is written to ‘1’, the TCB will restart whenever TCA0 is restarted or overflows. This can be used to
synchronize capture with the PWM period.
Bits 2:1 – CLKSEL[1:0] Clock Select
Writing these bits selects the clock source for this peripheral.
Value
Name
Description
0x0
0x1
0x2
0x3
CLKDIV1
CLKDIV2
CLKTCA
CLK_PER
CLK_PER / 2
Use CLK_TCA from TCA0
Reserved
Bit 0 – ENABLE Enable
Writing this bit to ‘1’ enables the Timer/Counter type B peripheral.
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TCB - 16-Bit Timer/Counter Type B
21.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLB
0x01
0x00
-
6
ASYNC
R/W
0
5
CCMPINIT
R/W
0
4
CCMPEN
R/W
0
3
2
R/W
0
1
CNTMODE[2:0]
R/W
0
0
R/W
0
Bit 6 – ASYNC Asynchronous Enable
Writing this bit to ‘1’ will allow asynchronous updates of the TCB output signal in Single-Shot mode.
Value
Description
0
The output will go HIGH when the counter starts after synchronization
1
The output will go HIGH when an event arrives
Bit 5 – CCMPINIT Compare/Capture Pin Initial Value
This bit is used to set the initial output value of the pin when a pin output is used. This bit has no effect in 8-bit PWM
mode and Single-Shot mode.
Value
Description
0
Initial pin state is LOW
1
Initial pin state is HIGH
Bit 4 – CCMPEN Compare/Capture Output Enable
Writing this bit to ‘1’ enables the waveform output. This will make the waveform output available on the corresponding
pin, overriding the value in the corresponding PORT output register. The corresponding pin direction must be
configured as an output in the PORT peripheral.
Value
Description
0
Waveform output is not enabled on the corresponding pin
1
Waveform output will override the output value of the corresponding pin
Bits 2:0 – CNTMODE[2:0] Timer Mode
Writing these bits selects the Timer mode.
Value
Name
Description
0x0
INT
Periodic Interrupt mode
0x1
TIMEOUT
Time-out Check mode
0x2
CAPT
Input Capture on Event mode
0x3
FRQ
Input Capture Frequency Measurement mode
0x4
PW
Input Capture Pulse-Width Measurement mode
0x5
FRQPW
Input Capture Frequency and Pulse-Width Measurement mode
0x6
SINGLE
Single-Shot mode
0x7
PWM8
8-Bit PWM mode
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TCB - 16-Bit Timer/Counter Type B
21.5.3
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x04
0x00
-
7
Access
Reset
6
FILTER
R/W
0
5
4
EDGE
R/W
0
3
2
1
0
CAPTEI
R/W
0
Bit 6 – FILTER Input Capture Noise Cancellation Filter
Writing this bit to ‘1’ enables the Input Capture Noise Cancellation unit.
Bit 4 – EDGE Event Edge
This bit is used to select the event edge. The effect of this bit is dependent on the selected Count Mode (CNTMODE)
bit field in TCBn.CTRLB. “—” means that an event or edge does not affect this mode.
Count Mode
Periodic Interrupt mode
Timeout Check mode
Input Capture on Event mode
Input Capture Frequency
Measurement mode
Input Capture Pulse-Width
Measurement mode
EDGE Positive Edge
Negative Edge
0
1
0
1
0
1
—
—
Stop counter
Start counter
—
Input Capture, interrupt
0
1
0
1
0
Input Capture Frequency and PulseWidth Measurement mode
1
Single-Shot mode
8-Bit PWM mode
0
1
0
1
—
—
Start counter
Stop counter
Input Capture, interrupt
—
Input Capture, clear and restart
counter, interrupt
—
Input Capture, clear and restart
counter, interrupt
Clear and restart counter
Input Capture, interrupt
Input Capture, interrupt
Clear and restart counter
• On the 1st Positive: Clear and restart counter
• On the following Negative: Input Capture
• On the 2nd Positive: Stop counter, interrupt
• On the 1st Negative: Clear and restart counter
• On the following Positive: Input Capture
• On the 2nd Negative: Stop counter, interrupt
Start counter
—
Start counter
Start counter
—
—
—
—
—
Bit 0 – CAPTEI Capture Event Input Enable
Writing this bit to ‘1’ enables the input capture event.
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TCB - 16-Bit Timer/Counter Type B
21.5.4
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x05
0x00
-
6
5
4
3
Access
Reset
2
1
0
CAPT
R/W
0
Bit 0 – CAPT Capture Interrupt Enable
Writing this bit to ‘1’ enables interrupt on capture.
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TCB - 16-Bit Timer/Counter Type B
21.5.5
Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
INTFLAGS
0x06
0x00
-
7
6
5
4
3
2
1
0
CAPT
R/W
0
Access
Reset
Bit 0 – CAPT Capture Interrupt Flag
This bit is set when a capture interrupt occurs. The interrupt conditions are dependent on the Counter Mode
(CNTMODE) bit field in the Control B (TCBn.CTRLB) register.
This bit is cleared by writing a ‘1’ to it or when the Capture register is read in Capture mode.
Table 21-6. Interrupt Sources Set Conditions by Counter Mode
Counter Mode
Interrupt Set Condition
TOP
Value
CAPT
Periodic Interrupt mode
Timeout Check mode
Single-Shot mode
Set when the counter reaches TOP
Set when the counter reaches TOP
Set when the counter reaches TOP
CCMP
CNT == TOP
Input Capture Frequency
Measurement mode
Set on edge when the Capture register is
loaded, and the counter restarts; the flag
clears when the capture is read
Set when an event occurs and the Capture
register is loaded; the flag clears when the
capture is read
-Set on edge when the Capture register is
Input Capture Pulse-Width
loaded; the previous edge initialized the count;
Measurement mode
the flag clears when the capture is read
Input Capture Frequency Set on the second edge (positive or negative)
and Pulse-Width
when the counter is stopped; the flag clears
Measurement mode
when the capture is read
8-Bit PWM mode
Set when the counter reaches CCML
CCML
On Event, copy CNT
to CCMP, and restart
counting (CNT ==
BOTTOM)
Input Capture on Event
mode
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On Event, copy CNT
to CCMP, and continue
counting
CNT == CCML
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ATmega808/809/1608/1609
TCB - 16-Bit Timer/Counter Type B
21.5.6
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x07
0x00
-
6
5
4
3
2
1
0
RUN
R
0
Access
Reset
Bit 0 – RUN Run
When the counter is running, this bit is set to ‘1’. When the counter is stopped, this bit is cleared to ‘0’.
The bit is read-only and cannot be set by UPDI.
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TCB - 16-Bit Timer/Counter Type B
21.5.7
Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x08
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
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TCB - 16-Bit Timer/Counter Type B
21.5.8
Temporary Value
Name:
Offset:
Reset:
Property:
TEMP
0x09
0x00
-
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary Value
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TCB - 16-Bit Timer/Counter Type B
21.5.9
Count
Name:
Offset:
Reset:
Property:
CNT
0x0A
0x00
-
The TCBn.CNTL and TCBn.CNTH register pair represents the 16-bit value TCBn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
CPU and UPDI write access has priority over internal updates of the register.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CNT[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CNT[15:8] Count Value High
These bits hold the MSB of the 16-bit Counter register.
Bits 7:0 – CNT[7:0] Count Value Low
These bits hold the LSB of the 16-bit Counter register.
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TCB - 16-Bit Timer/Counter Type B
21.5.10 Capture/Compare
Name:
Offset:
Reset:
Property:
CCMP
0x0C
0x00
-
The TCBn.CCMPL and TCBn.CCMPH register pair represents the 16-bit value TCBn.CCMP. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
This register has different functions depending on the mode of operation:
• For Capture operation, these registers contain the captured value of the counter at the time the capture occurs
• In Periodic Interrupt/Time-Out and Single-Shot mode, this register acts as the TOP value
• In 8-bit PWM mode, TCBn.CCMPL and TCBn.CCMPH act as two independent registers: The period of the
waveform is controlled by CCMPL, while CCMPH controls the duty cycle.
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
CCMP[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CCMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CCMP[15:8] Capture/Compare Value High Byte
These bits hold the MSB of the 16-bit compare, capture, and top value.
Bits 7:0 – CCMP[7:0] Capture/Compare Value Low Byte
These bits hold the LSB of the 16-bit compare, capture, and top value.
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ATmega808/809/1608/1609
RTC - Real-Time Counter
22.
RTC - Real-Time Counter
22.1
Features
•
•
•
•
•
•
•
•
•
22.2
16-bit Resolution
Selectable Clock Sources
Programmable 15-bit Clock Prescaling
One Compare Register
One Period Register
Clear Timer on Period Overflow
Optional Interrupt/Event on Overflow and Compare Match
Periodic Interrupt and Event
Crystal Error Correction
Overview
The RTC peripheral offers two timing functions: The Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
The PIT functionality can be enabled independently of the RTC functionality.
RTC - Real-Time Counter
The RTC counts (prescaled) clock cycles in a Counter register and compares the content of the Counter register to a
Period register and a Compare register.
The RTC can generate both interrupts and events on compare match or overflow. It will generate a compare interrupt
and/or event at the first count after the counter value equals the Compare register value, and an overflow interrupt
and/or event at the first count after the counter value equals the Period register value. The overflow will reset the
counter value to zero.
The RTC peripheral typically runs continuously, including in Low-Power sleep modes, to keep track of time. It can
wake up the device from sleep modes, and/or interrupt the device at regular intervals.
The reference clock is typically the 32.768 kHz output from an external crystal. The RTC can also be clocked from an
external clock signal, the 32 kHz Internal Ultra Low-Power Oscillator (OSCULP32K), or the OSCULP32K divided by
32.
The RTC peripheral includes a 15-bit programmable prescaler that can scale down the reference clock before it
reaches the counter. A wide range of resolutions and time-out periods can be configured for the RTC. With a 32.768
kHz clock source, the maximum resolution is 30.5 μs, and time-out periods can be up to two seconds. With a
resolution of 1s, the maximum time-out period is more than 18 hours (65536 seconds).
The RTC also supports crystal error correction when operated using external crystal selection. An externally
calibrated value will be used for correction. The RTC can be adjusted by software with an accuracy of ±1 PPM,
and the maximum adjustment is ±127 PPM. The RTC correction operation will either speed up (by skipping count) or
slow down (by adding extra count) the prescaler to account for the crystal error.
PIT - Periodic Interrupt Timer
The PIT uses the same clock source (CLK_RTC) as the RTC function and can generate an interrupt request or a
level event on every nth clock period. The n can be selected from {4, 8, 16,... 32768} for interrupts, and from {64, 128,
256,... 8192} for events.
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RTC - Real-Time Counter
22.2.1
Block Diagram
Figure 22-1. RTC Block Diagram
EXTCLK
TOSC1
TOSC2
External Clock
32.768 kHz Crystal Osc.
32.768 kHz Int. Osc.
DIV32
PER
CLK_RTC
Correction
counter
RTC
15-bit
prescaler
PIT
=
Overflow
=
Compare
CNT
CMP
Period
22.3
Clocks
The peripheral clock (CLK_PER) is required to be at least four times faster than the RTC clock (CLK_RTC) for
reading the counter value, regardless of the prescaler setting.
A 32.768 kHz crystal can be connected to the TOSC1 or TOSC2 pins, along with any required load capacitors.
Alternatively, an external digital clock can be connected to the TOSC1 pin.
22.4
RTC Functional Description
The RTC peripheral offers two timing functions: The Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
This subsection describes the RTC.
22.4.1
Initialization
Before enabling the RTC peripheral and the desired actions (interrupt requests and output events), the source clock
for the RTC counter must be configured to operate the RTC.
22.4.1.1 Configure the Clock CLK_RTC
To configure the CLK_RTC, follow these steps:
1.
2.
Configure the desired oscillator to operate as required, in the Clock Controller (CLKCTRL) peripheral.
Write the Clock Select (CLKSEL) bit field in the Clock Selection (RTC.CLKSEL) register accordingly.
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RTC - Real-Time Counter
The CLK_RTC clock configuration is used by both RTC and PIT functionalities.
22.4.1.2 Configure RTC
To operate the RTC, follow these steps:
1.
2.
3.
4.
Set the compare value in the Compare (RTC.CMP) register, and/or the overflow value in the Period
(RTC.PER) register.
Enable the desired interrupts by writing to the respective interrupt enable bits (CMP, OVF) in the Interrupt
Control (RTC.INTCTRL) register.
Configure the RTC internal prescaler by writing the desired value to the Prescaler (PRESCALER) bit field in
the Control A (RTC.CTRLA) register.
Enable the RTC by writing a ‘1’ to the RTC Peripheral Enable (RTCEN) bit in the RTC.CTRLA register.
Note: The RTC peripheral is used internally during device start-up. Always check the Synchronization Busy bits
in the Status (RTC.STATUS) and Periodic Interrupt Timer Status (RTC.PITSTATUS) registers, and on the initial
configuration.
22.4.2
Operation - RTC
22.4.2.1 Enabling and Disabling
The RTC is enabled by writing the RTC Peripheral Enable (RTCEN) bit in the Control A (RTC.CTRLA) register to ‘1’.
The RTC is disabled by writing the RTC Peripheral Enable (RTCEN) bit in RTC.CTRLA to ‘0’.
22.5
PIT Functional Description
The RTC peripheral offers two timing functions: The Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
This subsection describes the PIT.
22.5.1
Initialization
To operate the PIT, follow these steps:
1. Configure the RTC clock CLK_RTC as described in section 22.4.1.1 Configure the Clock CLK_RTC.
2. Enable the interrupt by writing a ‘1’ to the Periodic Interrupt (PI) bit in the PIT Interrupt Control
(RTC.PITINTCTRL) register.
3. Select the period for the interrupt by writing the desired value to the Period (PERIOD) bit field in the Periodic
Interrupt Timer Control A (RTC.PITCTRLA) register.
4. Enable the PIT by writing a ‘1’ to the Periodic Interrupt Timer Enable (PITEN) bit in the RTC.PITCTRLA
register.
Note: The RTC peripheral is used internally during device start-up. Always check the Synchronization Busy bits in
the RTC.STATUS and RTC.PITSTATUS registers, and on the initial configuration.
22.5.2
Operation - PIT
22.5.2.1 Enabling and Disabling
The PIT is enabled by writing the Periodic Interrupt Timer Enable (PITEN) bit in the Periodic Interrupt Timer Control
A (RTC.PITCTRLA) register to ‘1’. The PIT is disabled by writing the Periodic Interrupt Timer Enable (PITEN) bit in
RTC.PITCTRLA to ‘0’.
22.5.2.2 PIT Interrupt Timing
Timing of the First Interrupt
Both PIT and RTC functions are running from the same counter inside the prescaler and can be configured as
described below:
• The RTC interrupt period is configured by writing the Period (RTC.PER) register
• The PIT interrupt period is configured by writing the Period (PERIOD) bit field in Periodic Interrupt Timer Control
A (RTC.PITCTRLA) register
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The prescaler is OFF when both functions are OFF (RTC Peripheral Enable (RTCEN) bit in RTC.CTRLA and the
Periodic Interrupt Timer Enable (PITEN) bit in RTC.PITCTRLA are ‘0’), but it is running (that is, its internal counter is
counting) when either function is enabled. For this reason, the timing of the first PIT interrupt and the first RTC count
tick will be unknown (anytime between enabling and a full period).
Continuous Operation
After the first interrupt, the PIT will continue toggling every ½ PIT period resulting in a full PIT period signal.
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Example 22-1. PIT Timing Diagram for PERIOD = CYC16
For PERIOD = CYC16 in RTC.PITCTRLA, the PIT output effectively follows the state of the
prescaler counter bit 3, so the resulting interrupt output has a period of 16 CLK_RTC cycles.
The time between writing PITEN to ‘1’ and the first PIT interrupt can vary between virtually zero
and a full PIT period of 16 CLK_RTC cycles. The precise delay between enabling the PIT and its
first output depends on the prescaler’s counting phase: The first interrupt shown below is produced
by writing PITEN to ‘1’ at any time inside the leading time window.
Figure 22-2. Timing Between PIT Enable and First Interrupt
Prescaler
counter
value (LSB)
..000000
..000001
..000010
..000011
..000100
..000101
..000110
..000111
..001000
..001001
..001010
..001011
..001100
..001101
..001110
..001111
..010000
..010001
..010010
..010011
..010100
..010101
..010110
..010111
..011000
..011001
..011010
..011011
..011100
..011101
..011110
..011111
..100000
..100001
..100010
..100011
..100100
..100101
..100110
..100111
..101000
..101001
..101010
..101011
..101100
..101101
..101110
..101111
CLK_RTC
Prescaler bit 3
(CYC16)
Continuous Operation
PITENABLE = 0
PIT output
Time window for writing
PITENABLE = 1
First PIT output
22.6
Crystal Error Correction
The prescaler for the RTC and PIT can do internal frequency correction of the crystal clock by using the PPM error
value from the Crystal Frequency Calibration (CALIB) register when the Frequency Correction Enable (CORREN) bit
in the RTC.CTRLA register is ‘1’.
The CALIB register must be written by the user, based on the information about the frequency error. The correction
operation is performed by adding or removing a number of cycles equal to the value given in the Error Correction
Value (ERROR) bit field in the CALIB register spread throughout a million-cycle interval.
The correction of the clock will be reflected in the RTC count value available through the Count (RTC.CNT) registers
or in the PIT intervals.
If disabling the correction feature, an ongoing correction cycle will be completed before the function is disabled.
Note: If using this feature with a negative correction, the minimum prescaler configuration is DIV2.
22.7
Events
The RTC can generate the events described in the following table:
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Table 22-1. Event Generators in RTC
Generator Name
Description
Event
Type
Generating
Clock Domain
Length of Event
OVF
Overflow
Pulse
CLK_RTC
One CLK_RTC period
CMP
Compare Match
Peripheral Event
RTC
PIT_DIV8192 Prescaled RTC clock
divided by 8192
Level
Given by prescaled RTC
clock divided by 8192
PIT_DIV4096 Prescaled RTC clock
divided by 4096
Given by prescaled RTC
clock divided by 4096
PIT_DIV2048 Prescaled RTC clock
divided by 2048
Given by prescaled RTC
clock divided by 2048
PIT_DIV1024 Prescaled RTC clock
divided by 1024
Given by prescaled RTC
clock divided by 1024
PIT_DIV512
Prescaled RTC clock
divided by 512
Given by prescaled RTC
clock divided by 512
PIT_DIV256
Prescaled RTC clock
divided by 256
Given by prescaled RTC
clock divided by 256
PIT_DIV128
Prescaled RTC clock
divided by 128
Given by prescaled RTC
clock divided by 128
PIT_DIV64
Prescaled RTC clock
divided by 64
Given by prescaled RTC
clock divided by 64
The conditions for generating the OVF and CMP events are identical to those that will raise the corresponding
interrupt flags in the RTC.INTFLAGS register.
Refer to the Event System (EVSYS) section for more details regarding event users and Event System configuration.
22.8
Interrupts
Table 22-2. Available Interrupt Vectors and Sources
Name Vector Description
RTC
PIT
Real-Time Counter overflow
and compare match
interrupt
Periodic Interrupt Timer
interrupt
Conditions
•
•
Overflow (OVF): The counter has reached the value from the RTC.PER
register and wrapped to zero
Compare (CMP): Match between the value from the Counter (RTC.CNT)
register and the value from the Compare (RTC.CMP) register
A time period has passed, as configured by the PERIOD bit field in
RTC.PITCTRLA
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
Note that:
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•
•
22.9
The RTC has two INTFLAGS registers: RTC.INTFLAGS and RTC.PITINTFLAGS.
The RTC has two INTCTRL registers: RTC.INTCTRL and RTC.PITINTCTRL.
Sleep Mode Operation
The RTC will continue to operate in Idle sleep mode. It will run in Standby sleep mode if the Run in Standby
(RUNSTDBY) bit in RTC.CTRLA is set.
The PIT will continue to operate in any sleep mode.
22.10
Synchronization
Both the RTC and the PIT are asynchronous, operating from a different clock source (CLK_RTC) independently of
the peripheral clock (CLK_PER). For Control and Count register updates, it will take some RTC and/or peripheral
clock cycles before an updated register value is available in a register or until a configuration change affects the RTC
or PIT, respectively. This synchronization time is described for each register in the Register Description section.
For some RTC registers, a Synchronization Busy (CMPBUSY, PERBUSY, CNTBUSY, CTRLABUSY) flag is available
in the Status (RTC.STATUS) register.
For the RTC.PITCTRLA register, a Synchronization Busy (CTRLBUSY) flag is available in the Periodic Interrupt
Timer Status (RTC.PITSTATUS) register.
Check these flags before writing to the mentioned registers.
22.11
Debug Operation
If the Debug Run (DBGRUN) bit in the Debug Control (RTC.DBGCTRL) register is ‘1’, the RTC will continue normal
operation. If DBGRUN is ‘0’ and the CPU is halted, the RTC will halt the operation and ignore any incoming events.
If the Debug Run (DBGRUN) bit in the Periodic Interrupt Timer Debug Control (RTC.PITDBGCTRL) register is ‘1’, the
PIT will continue normal operation. If DBGRUN is ‘0’ in the Debug mode and the CPU is halted, the PIT output will
be low. When the PIT output is high at the time, a new positive edge occurs to set the interrupt flag when restarting
from a break. The result is an additional PIT interrupt that does not happen during normal operation. If the PIT output
is low at the break, the PIT will resume low without additional interrupt.
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22.12
Register Summary
Offset
Name
Bit Pos.
7
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
STATUS
INTCTRL
INTFLAGS
TEMP
DBGCTRL
CALIB
CLKSEL
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
RUNSTDBY
0x08
CNT
0x0A
PER
0x0C
CMP
0x0E
...
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
22.13
6
5
4
3
2
CMPBUSY
CORREN
PERBUSY
PRESCALER[3:0]
1
0
CNTBUSY
CMP
CMP
RTCEN
CTRLABUSY
OVF
OVF
TEMP[7:0]
DBGRUN
SIGN
ERROR[6:0]
CLKSEL[1:0]
CNT[7:0]
CNT[15:8]
PER[7:0]
PER[15:8]
CMP[7:0]
CMP[15:8]
Reserved
PITCTRLA
PITSTATUS
PITINTCTRL
PITINTFLAGS
Reserved
PITDBGCTRL
7:0
7:0
7:0
7:0
PERIOD[3:0]
7:0
PITEN
CTRLBUSY
PI
PI
DBGRUN
Register Description
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22.13.1 Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RUNSTDBY
R/W
0
CTRLA
0x00
0x00
-
6
R/W
0
5
4
PRESCALER[3:0]
R/W
R/W
0
0
3
R/W
0
2
CORREN
R/W
0
1
0
RTCEN
R/W
0
Bit 7 – RUNSTDBY Run in Standby
Value
Description
0
RTC disabled in Standby sleep mode
1
RTC enabled in Standby sleep mode
Bits 6:3 – PRESCALER[3:0] Prescaler
These bits define the prescaling of the CLK_RTC clock signal. Due to synchronization between the RTC clock and
the peripheral clock, there is a latency of two RTC clock cycles from updating the register until this has an effect.
Application software needs to check that the CTRLABUSY flag in the RTC.STATUS register is cleared before writing
to this register.
Value
Name
Description
0x0
DIV1
RTC clock/1 (no prescaling)
0x1
DIV2
RTC clock/2
0x2
DIV4
RTC clock/4
0x3
DIV8
RTC clock/8
0x4
DIV16
RTC clock/16
0x5
DIV32
RTC clock/32
0x6
DIV64
RTC clock/64
0x7
DIV128
RTC clock/128
0x8
DIV256
RTC clock/256
0x9
DIV512
RTC clock/512
0xA
DIV1024
RTC clock/1024
0xB
DIV2048
RTC clock/2048
0xC
DIV4096
RTC clock/4096
0xD
DIV8192
RTC clock/8192
0xE
DIV16384
RTC clock/16384
0xF
DIV32768
RTC clock/32768
Bit 2 – CORREN Frequency Correction Enable
Value
Description
0
Frequency correction is disabled
1
Frequency correction is enabled
Bit 0 – RTCEN RTC Peripheral Enable
Value
Description
0
RTC peripheral is disabled
1
RTC peripheral is enabled
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22.13.2 Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x01
0x00
-
6
Access
Reset
5
4
3
CMPBUSY
R
0
2
PERBUSY
R
0
1
CNTBUSY
R
0
0
CTRLABUSY
R
0
Bit 3 – CMPBUSY Compare Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing the Compare (RTC.CMP) register in the RTC clock domain.
Bit 2 – PERBUSY Period Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing the Period (RTC.PER) register in the RTC clock domain.
Bit 1 – CNTBUSY Counter Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing the Count (RTC.CNT) register in the RTC clock domain.
Bit 0 – CTRLABUSY Control A Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing the Control A (RTC.CTRLA) register in the RTC clock domain.
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22.13.3 Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x02
0x00
-
6
5
4
3
Access
Reset
2
1
CMP
R/W
0
0
OVF
R/W
0
Bit 1 – CMP Compare Match Interrupt Enable
Enable interrupt-on-compare match (that is, when the value from the Count (RTC.CNT) register matches the value
from the Compare (RTC.CMP) register).
Value
Description
0
The compare match interrupt is disabled
1
The compare match interrupt is enabled
Bit 0 – OVF Overflow Interrupt Enable
Enable interrupt-on-counter overflow (that is, when the value from the Count (RTC.CNT) register matched the value
from the Period (RTC.PER) register and wraps around to zero).
Value
Description
0
The overflow interrupt is disabled
1
The overflow interrupt is enabled
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22.13.4 Interrupt Flag
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
CMP
R/W
0
0
OVF
R/W
0
Bit 1 – CMP Compare Match Interrupt Flag
This flag is set when the value from the Count (RTC.CNT) register matches the value from the Compare (RTC.CMP)
register.
Writing a ‘1’ to this bit clears the flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set when the value from the Count (RTC.CNT) register has reached the value from the Period (RTC.PER)
register and wrapped to zero.
Writing a ‘1’ to this bit clears the flag.
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22.13.5 Temporary
Name:
Offset:
Reset:
Property:
TEMP
0x4
0x00
-
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary
Temporary register for read/write operations in 16-bit registers.
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22.13.6 Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x05
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
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22.13.7 Crystal Frequency Calibration
Name:
Offset:
Reset:
Property:
CALIB
0x06
0x00
-
This register stores the error value and the type of correction to be done. The register is written by software with an
error value based on external calibration and/or temperature correction/s.
Bit
Access
Reset
7
SIGN
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
3
ERROR[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 7 – SIGN Error Correction Sign Bit
This bit shows the direction of the correction.
Value
Description
0x0
0x1
Positive correction causing the prescaler to count slower
Negative correction causing the prescaler to count faster. This requires that the
minimum prescaler configuration is DIV2
Bits 6:0 – ERROR[6:0] Error Correction Value
The number of correction clocks for each million RTC clock cycles interval (PPM).
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22.13.8 Clock Selection
Name:
Offset:
Reset:
Property:
Bit
7
CLKSEL
0x07
0x00
-
6
5
4
3
Access
Reset
2
1
0
CLKSEL[1:0]
R/W
R/W
0
0
Bits 1:0 – CLKSEL[1:0] Clock Select
Writing these bits select the source for the RTC clock (CLK_RTC).
Value
Name
Description
0x00
0x01
0x02
0x03
INT32K
INT1K
TOSC32K
EXTCLK
Internal 32.768 kHz oscillator
Internal 1.024 kHz oscillator
32.768 kHz crystal oscillator
External clock from EXTCLK pin
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22.13.9 Count
Name:
Offset:
Reset:
Property:
CNT
0x08
0x0000
-
The RTC.CNTL and RTC.CNTH register pair represents the 16-bit value, RTC.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to the synchronization between the RTC clock and main clock domains, there is a latency of two RTC clock
cycles from updating the register until this has an effect. The application software needs to check that the CNTBUSY
flag in RTC.STATUS is cleared before writing to this register.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CNT[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CNT[15:8] Counter High Byte
These bits hold the MSB of the 16-bit Counter register.
Bits 7:0 – CNT[7:0] Counter Low Byte
These bits hold the LSB of the 16-bit Counter register.
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22.13.10 Period
Name:
Offset:
Reset:
Property:
PER
0x0A
0xFFFF
-
The RTC.PERL and RTC.PERH register pair represents the 16-bit value, RTC.PER. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to the synchronization between the RTC clock and main clock domains, there is a latency of two RTC clock
cycles from updating the register until this has an effect. The application software needs to check that the PERBUSY
flag in RTC.STATUS is cleared before writing to this register.
Bit
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PER[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
PER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:8 – PER[15:8] Period High Byte
These bits hold the MSB of the 16-bit Period register.
Bits 7:0 – PER[7:0] Period Low Byte
These bits hold the LSB of the 16-bit Period register.
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22.13.11 Compare
Name:
Offset:
Reset:
Property:
CMP
0x0C
0x0000
-
The RTC.CMPL and RTC.CMPH register pair represents the 16-bit value, RTC.CMP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CMP[15:8] Compare High Byte
These bits hold the MSB of the 16-bit Compare register.
Bits 7:0 – CMP[7:0] Compare Low Byte
These bits hold the LSB of the 16-bit Compare register.
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22.13.12 Periodic Interrupt Timer Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
PITCTRLA
0x10
0x00
-
6
R/W
0
5
4
PERIOD[3:0]
R/W
R/W
0
0
3
2
R/W
0
1
0
PITEN
R/W
0
Bits 6:3 – PERIOD[3:0] Period
Writing this bit field selects the number of RTC clock cycles between each interrupt.
Value
Name
Description
0x0
OFF
No interrupt
0x1
CYC4
4 cycles
0x2
CYC8
8 cycles
0x3
CYC16
16 cycles
0x4
CYC32
32 cycles
0x5
CYC64
64 cycles
0x6
CYC128
128 cycles
0x7
CYC256
256 cycles
0x8
CYC512
512 cycles
0x9
CYC1024
1024 cycles
0xA
CYC2048
2048 cycles
0xB
CYC4096
4096 cycles
0xC
CYC8192
8192 cycles
0xD
CYC16384
16384 cycles
0xE
CYC32768
32768 cycles
0xF
Reserved
Bit 0 – PITEN Periodic Interrupt Timer Enable
Value
Description
0
Periodic Interrupt Timer disabled
1
Periodic Interrupt Timer enabled
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22.13.13 Periodic Interrupt Timer Status
Name:
Offset:
Reset:
Property:
Bit
7
PITSTATUS
0x11
0x00
-
6
5
4
3
Access
Reset
2
1
0
CTRLBUSY
R
0
Bit 0 – CTRLBUSY PITCTRLA Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing the Periodic Interrupt Timer Control A (RTC.PITCTRLA) register in
the RTC clock domain.
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22.13.14 PIT Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
PITINTCTRL
0x12
0x00
-
6
5
4
3
Access
Reset
2
1
0
PI
R/W
0
Bit 0 – PI Periodic Interrupt
Value
Description
0
The periodic interrupt is disabled
1
The periodic interrupt is enabled
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22.13.15 PIT Interrupt Flag
Name:
Offset:
Reset:
Property:
Bit
7
PITINTFLAGS
0x13
0x00
-
6
5
4
3
Access
Reset
2
1
0
PI
R/W
0
Bit 0 – PI Periodic Interrupt Flag
This flag is set when a periodic interrupt is issued.
Writing a ‘1’ clears the flag.
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RTC - Real-Time Counter
22.13.16 Periodic Interrupt Timer Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
PITDBGCTRL
0x15
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
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23.
USART - Universal Synchronous and Asynchronous Receiver and
Transmitter
23.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
23.2
Full-Duplex Operation
Half-Duplex Operation:
– One-Wire mode
– RS-485 mode
Asynchronous or Synchronous Operation
Supports Serial Frames with Five, Six, Seven, Eight or Nine Data Bits and One or Two Stop Bits
Fractional Baud Rate Generator:
– Can generate the desired baud rate from any peripheral clock frequency
– No need for an external oscillator
Built-In Error Detection and Correction Schemes:
– Odd or even parity generation and parity check
– Buffer overflow and frame error detection
– Noise filtering including false Start bit detection and digital low-pass filter
Separate Interrupts for:
– Transmit complete
– Transmit Data register empty
– Receive complete
Host SPI Mode
Multiprocessor Communication Mode
Start-of-Frame Detection
IRCOM Module for IrDA® Compliant Pulse Modulation/Demodulation
LIN Client Support
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a fast and flexible serial
communication peripheral. The USART supports several different modes of operation that can accommodate multiple
types of applications and communication devices. For example, the One-Wire Half-Duplex mode is useful when low
pin count applications are desired. The communication is frame-based, and the frame format can be customized to
support a wide range of standards.
The USART is buffered in both directions, enabling continued data transmission without any delay between frames.
Separate interrupts for receive and transmit completion allow fully interrupt-driven communication.
The transmitter consists of a two-level write buffer, a Shift register, and control logic for different frame formats. The
receiver consists of a two-level receive buffer and a Shift register. The status information of the received data is
available for error checking. Data and clock recovery units ensure robust synchronization and noise filtering during
asynchronous data reception.
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23.2.1
Block Diagram
Figure 23-1. USART Block Diagram
CLOCK GENERATOR
BAUD
Baud Rate Generator
XCK
TRANSMITTER
XDIR
TX Shift Register
TX Buffer
TXD
TXDATA
RECEIVER
RX Shift Register
RX Buffer
RXD
RXDATA
23.2.2
Signal Description
Signal
Type
Description
XCK
Output/input
Clock for synchronous operation
XDIR
Output
Transmit enable for RS-485
TxD
Output/input
Transmitting line (and receiving line in One-Wire mode)
RxD
Input
Receiving line
23.3
Functional Description
23.3.1
Initialization
Full-Duplex Mode:
1.
2.
3.
4.
Set the baud rate (USARTn.BAUD).
Set the frame format and mode of operation (USARTn.CTRLC).
Configure the TXD pin as an output.
Enable the transmitter and the receiver (USARTn.CTRLB).
Notes:
• For interrupt-driven USART operation, global interrupts must be disabled during the initialization
• Before doing a reinitialization with a changed baud rate or frame format, be sure that there are no ongoing
transmissions while the registers are changed
One-Wire Half-Duplex Mode:
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1.
2.
3.
4.
5.
6.
Internally connect the TXD to the USART receiver (the LBME bit in the USARTn.CTRLA register).
Enable internal pull-up for the RX/TX pin (the PULLUPEN bit in the PORTx.PINnCTRL register).
Enable Open-Drain mode (the ODME bit in the USARTn.CTRLB register).
Set the baud rate (USARTn.BAUD).
Set the frame format and mode of operation (USARTn.CTRLC).
Enable the transmitter and the receiver (USARTn.CTRLB).
Notes:
• When Open-Drain mode is enabled, the TXD pin is automatically set to output by hardware
• For interrupt-driven USART operation, global interrupts must be disabled during the initialization
• Before doing a reinitialization with a changed baud rate or frame format, be sure that there are no ongoing
transmissions while the registers are changed
23.3.2
Operation
23.3.2.1 Frame Formats
The USART data transfer is frame-based. A frame starts with a Start bit followed by one character of data bits. If
enabled, the Parity bit is inserted after the data bits and before the first Stop bit. After the Stop bit(s) of a frame, either
the next frame can follow immediately, or the communication line can return to the Idle (high) state. The USART
accepts all combinations of the following as valid frame formats:
•
•
•
•
1 Start bit
5, 6, 7, 8, or 9 data bits
No, even, or odd Parity bit
1 or 2 Stop bits
The figure below illustrates the possible combinations of frame formats. Bits inside brackets are optional.
Figure 23-2. Frame Formats
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
St
Start bit, always low
(n)
Data bits (0 to 8)
P
Parity bit, may be odd or even
Sp
Stop bit, always high
IDLE
No transfer on the communication line (RxD or TxD). The Idle state is always high.
(St/IDLE)
23.3.2.2 Clock Generation
The clock used for shifting and sampling data bits is generated internally by the fractional baud rate generator or
externally from the Transfer Clock (XCK) pin.
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Figure 23-3. Clock Generation Logic Block Diagram
CLOCK GENERATOR
Sync
Register
Edge
Detector
CLK_PER
Fractional Baud Rate
Generator
BAUD
XCK
XCKO
Transmitter
TXCLK
Receiver
RXCLK
23.3.2.2.1 The Fractional Baud Rate Generator
In modes where the USART is not using the XCK input as a clock source, the fractional Baud Rate Generator is
used to generate the clock. Baud rate is given in terms of bits per second (bps) and is configured by writing the
USARTn.BAUD register. The baud rate (fBAUD) is generated by dividing the peripheral clock (fCLK_PER) by a division
factor decided by the BAUD register.
The fractional Baud Rate Generator features hardware that accommodates cases where fCLK_PER is not divisible by
fBAUD. Usually, this situation would lead to a rounding error. The fractional Baud Rate Generator expects the BAUD
register to contain the desired division factor left shifted by six bits, as implemented by the equations in Table 23-1.
The six Least Significant bits (LSbs) will then hold the fractional part of the desired divisor. Use the fractional part of
the BAUD register to dynamically adjust fBAUD to achieve a closer approximation to the desired baud rate.
Since the baud rate cannot be higher than fCLK_PER, the integer part of the BAUD register needs to be at least 1.
Since the result is left shifted by six bits, the corresponding minimum value of the BAUD register is 64. The valid
range is, therefore, 64 to 65535.
In Synchronous mode, only the 10-bit integer part of the BAUD register (BAUD[15:6]) determines the baud rate, and
the fractional part (BAUD[5:0]) must, therefore, be written to zero.
The table below lists equations for translating baud rates into input values for the BAUD register. The equations
consider fractional interpretation, so the BAUD values calculated with these equations can be written directly to
USARTn.BAUD without any additional scaling.
Table 23-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Asynchronous
Synchronous Host
Conditions
Baud Rate (Bits Per Seconds) USART.BAUD Register Value
Calculation
fBAUD ≤
fCLK_PER
64 × fCLK_PER
fBAUD =
S
S × BAUD
BAUD =
fBAUD ≤
fCLK_PER
fCLK_PER
fBAUD =
S
S × BAUD 15: 6
BAUD 15: 6 =
USART.BAUD ≥ 64
USART.BAUD ≥ 64
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64 × fCLK_PER
S × fBAUD
fCLK_PER
S × fBAUD
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S is the number of samples per bit
• Asynchronous Normal mode: S = 16
• Asynchronous Double-Speed mode: S = 8
• Synchronous mode: S = 2
23.3.2.3 Data Transmission
The USART transmitter sends data by periodically driving the transmission line low. The data transmission is initiated
by loading the Transmit Data (USARTn.TXDATAL and USARTn.TXDATAH) registers with the data to be sent. The
data in the Transmit Data registers are moved to the TX Buffer once it is empty and onwards to the Shift register
once it is empty and ready to send a new frame. After the Shift register is loaded with data, the data frame will be
transmitted.
When the entire frame in the Shift register has been shifted out, and there are no new data present in the Transmit
Data registers or the TX Buffer, the Transmit Complete Interrupt Flag (the TXCIF bit in the USARTn.STATUS register)
is set, and the interrupt is generated if it is enabled.
The Transmit Data registers can only be written when the Data Register Empty Interrupt Flag (the DREIF bit in the
USARTn.STATUS register) is set, indicating that they are empty and ready for new data.
When using frames with fewer than eight bits, the Most Significant bits (MSb) written to the Transmit Data registers
are ignored. When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured
to 9-bit (low byte first), the Transmit Data Register Low Byte (TXDATAL) must be written before the Transmit Data
Register High Byte (TXDATAH). When CHSIZE is configured to 9-bit (high byte first), TXDATAH must be written
before TXDATAL.
23.3.2.3.1 Disabling the Transmitter
When disabling the transmitter, the operation will not become effective until ongoing and pending transmissions are
completed. That is, when the Transmit Shift register, Transmit Data (USARTn.TXDATAL and USARTn.TXDATAH)
registers, and TX Buffer register do not contain data to be transmitted. When the transmitter is disabled, it will no
longer override the TXD pin, and the PORT module regains control of the pin. The pin is automatically configured as
an input by hardware regardless of its previous setting. The pin can now be used as a normal I/O pin with no port
override from the USART.
23.3.2.4 Data Reception
The USART receiver samples the reception line to detect and interpret the received data. The direction of the pin
must, therefore, be configured as an input by writing a ‘0’ to the corresponding bit in the Data Direction (PORTx.DIR)
register.
The receiver accepts data when a valid Start bit is detected. Each bit that follows the Start bit will be sampled at
the baud rate or XCK clock and shifted into the Receive Shift register until the first Stop bit of a frame is received.
A second Stop bit will be ignored by the receiver. When the first Stop bit is received, and a complete serial frame
is present in the Receive Shift register, the contents of the Shift register will be moved into the receive buffer.
The Receive Complete Interrupt Flag (the RXCIF bit in the USARTn.STATUS register) is set, and the interrupt is
generated if enabled.
The RXDATA registers are the part of the double-buffered RX buffer that can be read by the application software
when RXCIF is set. If only one frame has been received, the data and status bits for that frame are pushed to the
RXDATA registers directly. If two frames are present in the RX buffer, the RXDATA registers contain the data for the
oldest frame.
The buffer shifts out the data either when RXDATAL or RXDATAH is read, depending on the configuration. The
register, which does not lead to data being shifted, must be read first to be able to read both bytes before shifting.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low
byte first), a read of RXDATAH shifts the receive buffer. Otherwise, RXDATAL shifts the buffer.
23.3.2.4.1 Receiver Error Flags
The USART receiver features error detection mechanisms that uncover any corruption of the transmission. These
mechanisms include the following:
• Frame Error detection - controls whether the received frame is valid
• Buffer Overflow detection - indicates data loss due to the receiver buffer being full and overwritten by the new
data
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•
Parity Error detection - checks the validity of the incoming frame by calculating its parity and comparing it to the
Parity bit
Each error detection mechanism controls one error flag that can be read in the RXDATAH register:
• Frame Error (FERR)
• Buffer Overflow (BUFOVF)
• Parity Error (PERR)
The error flags are located in the RX buffer together with their corresponding frame. The RXDATAH register that
contains the error flags must be read before the RXDATAL register since reading the RXDATAL register will trigger
the RX buffer to shift out the RXDATA bytes.
Note: If the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is set to nine bits, low
byte first (9BITL), the RXDATAH register will, instead of the RXDATAL register, trigger the RX buffer to shift out the
RXDATA bytes. The RXDATAL register must, in that case, be read before the RXDATAH register.
23.3.2.4.2 Disabling the Receiver
When disabling the receiver, the operation is immediate. The receiver buffer will be flushed, and data from ongoing
receptions will be lost.
23.3.2.4.3 Flushing the Receive Buffer
If the RX buffer has to be flushed during normal operation, repeatedly read the DATA location (USARTn.RXDATAH
and USARTn.RXDATAL registers) until the Receive Complete Interrupt Flag (the RXCIF bit in the
USARTn.RXDATAH register) is cleared.
23.3.3
Communication Modes
The USART is a flexible peripheral that supports multiple different communication protocols. The available modes of
operation can be split into two groups: Synchronous and asynchronous communication.
The synchronous communication relies on one device on the bus to be the host, providing the rest of the devices with
a clock signal through the XCK pin. All the devices use this common clock signal for both transmission and reception,
requiring no additional synchronization mechanism.
The device can be configured to run either as a host or a client on the synchronous bus.
The asynchronous communication does not use a common clock signal. Instead, it relies on the communicating
devices to be configured with the same baud rate. When receiving a transmission, the hardware synchronization
mechanisms are used to align the incoming transmission with the receiving device peripheral clock.
Four different modes of reception are available when communicating asynchronously. One of these modes can
receive transmissions at twice the normal speed, sampling only eight times per bit instead of the normal 16. The
other three operating modes use variations of synchronization logic, all receiving at normal speed.
23.3.3.1 Synchronous Operation
23.3.3.1.1 Clock Operation
The XCK pin direction controls whether the transmission clock is an input (Client mode) or an output (Host mode).
The corresponding port pin direction must be set to output for Host mode or input for Client mode (PORTx.DIRn). The
data input (on RXD) is sampled at the XCK clock edge, which is opposite the edge where data are transmitted (on
TXD), as shown in the figure below.
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Figure 23-4. Synchronous Mode XCK Timing
XCK
INVEN = 0
Data transmit (TxD)
Data sample (RxD)
XCK
INVEN = 1
Data transmit (TxD)
Data sample (RxD)
The I/O pin can be inverted by writing a ‘1’ to the Inverted I/O Enable (INVEN) bit in the Pin n Control register of the
port peripheral (PORTx.PINnCTRL). When using the inverted I/O setting for the corresponding XCK port pin, the XCK
clock edges used for sampling RxD and transmitting on TxD can be selected. If the inverted I/O is disabled (INVEN
= 0), the rising XCK clock edge represents the start of a new data bit, and the received data will be sampled at the
falling XCK clock edge. If inverted I/O is enabled (INVEN = 1), the falling XCK clock edge represents the start of a
new data bit, and the received data will be sampled at the rising XCK clock edge.
23.3.3.1.2 External Clock Limitations
When the USART is configured in Synchronous Client mode, the XCK signal must be provided externally by the
host device. Since the clock is provided externally, configuring the BAUD register will have no impact on the transfer
speed. Successful clock recovery requires the clock signal to be sampled at least twice for each rising and falling
edge. The maximum XCK speed in Synchronous Operation mode, fClient_XCK, is therefore limited by:
fClient_XCK<
fCLK_PER
4
If the XCK clock has jitter, or if the high/low period duty cycle is not 50/50, the maximum XCK clock speed must be
reduced accordingly to ensure that XCK is sampled a minimum of two times for each edge.
23.3.3.1.3 USART in Host SPI Mode
The USART may be configured to function with multiple different communication interfaces, and one of these is the
Serial Peripheral Interface (SPI), where it can work as the host device. The SPI is a four-wire interface that enables a
host device to communicate with one or multiple clients.
Frame Formats
The serial frame for the USART in Host SPI mode always contains eight Data bits. The Data bits can be configured
to be transmitted with either the LSb or MSb first by writing to the Data Order (UDORD) bit in the Control C
(USARTn.CTRLC) register.
SPI does not use Start, Stop, or Parity bits, so the transmission frame can only consist of the Data bits.
Clock Generation
Being a host device in a synchronous communication interface, the USART in Host SPI mode must generate the
interface clock to be shared with the client devices. The interface clock is generated using the fractional Baud Rate
Generator, which is described in 23.3.2.2.1 The Fractional Baud Rate Generator.
Each Data bit is transmitted by pulling the data line high or low for one full clock period. The receiver will sample bits
in the middle of the transmitter hold period, as shown in the figure below. It also shows how the timing scheme can be
configured using the Inverted I/O Enable (INVEN) bit in the PORTx.PINnCTRL register and the USART Clock Phase
(UCPHA) bit in the USARTn.CTRLC register.
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UCPHA = 1
UCPHA = 0
Figure 23-5. Data Transfer Timing Diagrams
INVEN = 0
INVEN = 1
XCK
XCK
Data transmit (TxD)
Data transmit (TxD)
Data sample (RxD)
Data sample (RxD)
XCK
XCK
Data transmit (TxD)
Data transmit (TxD)
Data sample (RxD)
Data sample (RxD)
The table below further explains the figure above.
Table 23-2. Functionality of the INVEN and UCPHA Bits
INVEN
UCPHA
Leading Edge (1)
Trailing Edge (1)
0
0
Rising, sample
Falling, transmit
0
1
Rising, transmit
Falling, sample
1
0
Falling, sample
Rising, transmit
1
1
Falling, transmit
Rising, sample
Note:
1. The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock
cycle.
Data Transmission
Data transmission in Host SPI mode is functionally identical to the general USART operation, as described in
the Operation section. The transmitter interrupt flags and corresponding USART interrupts are also identical. See
23.3.2.3 Data Transmission for further description.
Data Reception
Data reception in Host SPI mode is identical in function to general USART operation as described in the Operation
section. The receiver interrupt flags and the corresponding USART interrupts are also identical, except for the
receiver error flags that are not in use and always read as ‘0’. See 23.3.2.4 Data Reception for further description.
USART in Host SPI Mode vs. SPI
The USART in Host SPI mode is fully compatible with a stand-alone SPI peripheral. Their data frame and timing
configurations are identical. Some SPI specific special features are, however, not supported with the USART in Host
SPI mode:
• Write Collision Flag Protection
• Double-Speed mode
• Multi-Host support
A comparison of the pins used with USART in Host SPI mode and with SPI is shown in the table below.
Table 23-3. Comparison of USART in Host SPI Mode and SPI Pins
USART
SPI
Comment
TXD
MOSI
Host out
RXD
MISO
Host in
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...........continued
USART
SPI
Comment
XCK
SCK
Functionally identical
-
SS
Not supported by USART in Host SPI mode(1)
Note:
1. For the stand-alone SPI peripheral, this pin is used with the Multi-Host function or as a dedicated Client Select
pin. The Multi-Host function is not available with the USART in Host SPI mode, and no dedicated Client Select
pin is available.
23.3.3.2 Asynchronous Operation
23.3.3.2.1 Clock Recovery
Since there is no common clock signal when using Asynchronous mode, each communicating device generates
separate clock signals. These clock signals must be configured to run at the same baud rate for the communication
to take place. The devices, therefore, run at the same speed, but their timing is skewed in relation to each
other. To accommodate this, the USART features a hardware clock recovery unit which synchronizes the incoming
asynchronous serial frames with the internally generated baud rate clock.
The figure below illustrates the sampling process for the Start bit of an incoming frame. It shows the timing
scheme for both Normal and Double-Speed mode (the RXMODE bit field in the USARTn.CTRLB register configured
respectively to 0x00 and 0x01). The sample rate for Normal mode is 16 times the baud rate, while the sample rate
for Double-Speed mode is eight times the baud rate (see 23.3.3.2.4 Double-Speed Operation for more details). The
horizontal arrows show the maximum synchronization error. Note that the maximum synchronization error is larger in
Double-Speed mode.
Figure 23-6. Start Bit Sampling
RxD
IDLE
START
BIT 0
Sample
(RXMODE = 0x0 )
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Sample
(RXMODE = 0x1 )
0
1
2
3
4
5
6
7
8
1
2
When the clock recovery logic detects a falling edge from the Idle (high) state to the Start bit (low), the Start
bit detection sequence is initiated. In the figure above, sample 1 denotes the first sample reading ‘0’. The clock
recovery logic then uses three subsequent samples (samples 8, 9, and 10 in Normal mode, and samples 4, 5, 6
in Double-Speed mode) to decide if a valid Start bit is received. If two or three samples read ‘0’, the Start bit is
accepted. The clock recovery unit is synchronized, and the data recovery can begin. If less than two samples read
‘0’, the Start bit is rejected. This process is repeated for each Start bit.
23.3.3.2.2 Data Recovery
As with clock recovery, the data recovery unit samples at a rate 8 or 16 times faster than the baud rate depending on
whether it is running in Double-Speed or Normal mode, respectively. The figure below shows the sampling process
for reading a bit in a received frame.
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Figure 23-7. Sampling of Data and Parity Bits
RxD
BIT n
Sample
1
(CLK2X = 0)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Sample
1
(CLK2X = 1)
2
3
4
5
6
7
8
1
A majority voting technique is, like with clock recovery, used on the three center samples for deciding the logic level
of the received bit. The process is repeated for each bit until a complete frame is received.
The data recovery unit will only receive the first Stop bit while ignoring the rest if there are more. If the sampled Stop
bit is read ‘0’, the Frame Error flag will be set. The figure below shows the sampling of a Stop bit. It also shows the
earliest possible beginning of the next frame's Start bit.
Figure 23-8. Stop Bit and Next Start Bit Sampling
RxD
STOP 1
(A)
(B)
(C)
Sample
1
(CLK2X = 0)
2
3
4
5
6
7
8
9
10
0/1
0/1
0/1
Sample
1
(CLK2X = 1)
2
3
4
5
6
0/1
A new high-to-low transition indicating the Start bit of a new frame can come right after the last of the bits used
for majority voting. For Normal-Speed mode, the first low-level sample can be at the point marked (A) in the figure
above. For Double-Speed mode, the first low level must be delayed to point (B), being the first sample after the
majority vote samples. Point (C) marks a Stop bit of full length at the nominal baud rate.
23.3.3.2.3 Error Tolerance
The speed of the internally generated baud rate and the externally received data rate has to be identical, but, due
to natural clock source error, this is usually not the case. The USART is tolerant of such error, and the limits of this
tolerance make up what is sometimes known as the Operational Range.
The following tables list the operational range of the USART, being the maximum receiver baud rate error that can be
tolerated. Note that Normal-Speed mode has higher toleration of baud rate variations than Double-Speed mode.
Table 23-4. Recommended Maximum Receiver Baud Rate Error for Normal-Speed Mode
D
Rslow [%]
Rfast [%]
Maximum Total Error [%]
Recommended Max. Receiver Error [%]
5
93.20
106.67
-6.80/+6.67
±3.0
6
94.12
105.79
-5.88/+5.79
±2.5
7
94.81
105.11
-5.19/+5.11
±2.0
8
95.36
104.58
-4.54/+4.58
±2.0
9
95.81
104.14
-4.19/+4.14
±1.5
10
96.17
103.78
-3.83/+3.78
±1.5
Notes:
• D: The sum of character size and parity size (D = 5 to 10 bits)
• RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
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Table 23-5. Recommended Maximum Receiver Baud Rate Error for Double-Speed Mode
D
Rslow [%]
Rfast [%]
Maximum Total Error [%]
Recommended Max. Receiver Error [%]
5
94.12
105.66
-5.88/+5.66
±2.5
6
94.92
104.92
-5.08/+4.92
±2.0
7
95.52
104.35
-4.48/+4.35
±1.5
8
96.00
103.90
-4.00/+3.90
±1.5
9
96.39
103.53
-3.61/+3.53
±1.5
10
96.70
103.23
-3.30/+3.23
±1.0
Notes:
• D: The sum of character size and parity size (D = 5 to 10 bits)
• RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
• RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
The recommendations of the maximum receiver baud rate error were made under the assumption that the receiver
and transmitter equally divide the maximum total error.
The following equations are used to calculate the maximum ratio of the incoming data rate and the internal receiver
baud rate.
RSLOW =
•
•
•
•
•
•
S D+1
S D + 1 + SF − 1
RFAST =
S D+2
S D + 1 + SM
D: The sum of character size and parity size (D = 5 to 10 bits)
S: Samples per bit. S = 16 for Normal-Speed mode and S = 8 for Double-Speed mode.
SF: First sample number used for majority voting. SF = 8 for Normal-Speed mode and SF = 4 for Double-Speed
mode.
SM: Middle sample number used for majority voting. SM = 9 for Normal-Speed mode and SM = 5 for DoubleSpeed mode.
RSLOW: The ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate
RFAST: The ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate
23.3.3.2.4 Double-Speed Operation
The double-speed operation allows for higher baud rates under asynchronous operation with lower peripheral clock
frequencies. This operation mode is enabled by writing the RXMODE bit field in the Control B (USARTn.CTRLB)
register to 0x01.
When enabled, the baud rate for a given asynchronous baud rate setting will be doubled, as shown in the equations
in 23.3.2.2.1 The Fractional Baud Rate Generator. In this mode, the receiver will use half the number of samples
(reduced from 16 to 8) for data sampling and clock recovery. This requires a more accurate baud rate setting and
peripheral clock. See 23.3.3.2.3 Error Tolerance for more details.
23.3.3.2.5 Auto-Baud
The auto-baud feature lets the USART configure its BAUD register based on input from a communication device,
which allows the device to communicate autonomously with multiple devices communicating with different baud
rates. The USART peripheral features two auto-baud modes: Generic Auto-Baud mode and LIN Constrained AutoBaud mode.
Both auto-baud modes must receive an auto-baud frame, as seen in the figure below.
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Figure 23-9. Auto-Baud Timing
Break Field
Sync Field
Tbit
8 Tbit
The break field is detected when 12 or more consecutive low cycles are sampled and notifies the USART that it
is about to receive the synchronization field. After the break field, when the Start bit of the synchronization field is
detected, a counter running at the peripheral clock speed is started. The counter is then incremented for the next
eight Tbit of the synchronization field. When all eight bits are sampled, the counter is stopped. The resulting counter
value is in effect the new BAUD register value.
When the USART Receive mode is set to GENAUTO (the RXMODE bit field in the USARTn.CTRLB register), the
Generic Auto-Baud mode is enabled. In this mode, one can set the Wait For Break (WFB) bit in the USARTn.STATUS
register to enable detection of a break field of any length (that is, also shorter than 12 cycles). This makes it possible
to set an arbitrary new baud rate without knowing the current baud rate. If the measured sync field results in a valid
BAUD value (0x0064 - 0xFFFF), the BAUD register is updated.
When USART Receive mode is set to LINAUTO mode (the RXMODE bit field in the USARTn.CTRLB register),
it follows the LIN format. The WFB functionality of the Generic Auto-Baud mode is not compatible with the
LIN Constrained Auto-Baud mode, which means that the received signal must be low for 12 peripheral clock
cycles or more for a break field to be valid. When a break field has been detected, the USART expects the
following synchronization field character to be 0x55. The tolerance for the difference in baud rates between the
two synchronizing devices can be configured using the Auto-baud Window Size (ABW) bit field in the Control D
(USARTn.CTRLD) register. If any of these conditions are not met, the Inconsistent Sync Field Error Flag (the ISFIF
bit in the USARTn.STATUS register) is set, and the baud rate is unchanged.
23.3.3.2.6 Half-Duplex Operation
Half-duplex is a type of communication where two or more devices may communicate with each other, but only one at
a time. The USART can be configured to operate in the following half-duplex modes:
• One-Wire mode
• RS-485 mode
One-Wire Mode
One-Wire mode is enabled by setting the Loop-Back Mode Enable (LBME) bit in the USARTn.CTRLA register. This
will enable an internal connection between the TXD pin and the USART receiver, making the TXD pin a combined
TxD/RxD line. The RXD pin will be disconnected from the USART receiver and may be controlled by a different
peripheral.
In One-Wire mode, multiple devices can manipulate the TxD/RxD line at the same time. In the case where one
device drives the pin to a logical high level (VCC), and another device pulls the line low (GND), a short will occur. To
accommodate this, the USART features an Open-Drain mode (the ODME bit in the USARTn.CTRLB register), which
prevents the transmitter from driving a pin to a logical high level, thereby constraining it to only be able to pull it low.
Combining this function with the internal pull-up feature (the PULLUPEN bit in the PORTx.PINnCTRL register) will
let the line be held high through a pull-up resistor, allowing any device to pull it low. When the line is pulled low, the
current from VCC to GND will be limited by the pull-up resistor. The TXD pin is automatically set to output by hardware
when the Open-Drain mode is enabled.
When the USART is transmitting to the TxD/RxD line, it will also receive its transmission. This can be used to detect
overlapping transmissions by checking if the received data are the same as the transmitted data.
RS-485 Mode
RS-485 is a communication standard supported by the USART peripheral. It is a physical interface that defines the
setup of a communication circuit. Data are transmitted using differential signaling, making communication robust
against noise. RS-485 is enabled by writing to the RS485 bit field in the USARTn.CTRLA register.
The RS-485 mode supports external line driver devices that convert a single USART transmission into corresponding
differential pair signals. Writing RS485[0] to ‘1’ enables the automatic control of the XDIR pin that can be used to
enable transmission or reception for the line driver device. The USART automatically drives the XDIR pin high while
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the USART is transmitting and pulls it low when the transmission is complete. An example of such a circuit is shown
in the figure below.
Figure 23-10. RS-485 Bus Connection
Line Driver
TXD
TX Driver
XDIR
Differential Bus
+
-
USART
RX Driver
RXD
The XDIR pin goes high one baud clock cycle in advance of data being shifted out to allow some guard time to
enable the external line driver. The XDIR pin will remain high for the complete frame, including Stop bit(s).
Figure 23-11. XDIR Drive Timing
TxD
St
0
1
2
3
4
5
6
7
Sp1
XDIR
Guard
time
Stop
Writing RS485[1] to ‘1’ enables the RS-485 mode, which automatically sets the TXD pin to output one clock cycle
before starting transmission and sets it back to input when the transmission is complete.
RS-485 mode is compatible with One-Wire mode. One-Wire mode enables an internal connection between the TXD
pin and the USART receiver, making the TXD pin a combined TxD/RxD line. The RXD pin will be disconnected from
the USART receiver and may be controlled by a different peripheral. An example of such a circuit is shown in the
figure below.
Figure 23-12. RS-485 with Loop-Back Mode Connection
TXD
Line Driver
TX Driver
XDIR
Differential Bus
+
-
USART
RXD
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23.3.3.2.7 IRCOM Mode of Operation
The USART peripheral can be configured in Infrared Communication mode (IRCOM), which is IrDA® 1.4 compatible
with baud rates up to 115.2 kbps. When enabled, the IRCOM mode enables infrared pulse encoding/decoding for the
USART.
Figure 23-13. Block Diagram
IRCOM
Event System
Events
Encoded RxD
Pulse
Decoding
Decoded RxD
USART
Pulse
Encoding
RXD
TXD
Decoded RxD
Encoded RxD
The USART is set in IRCOM mode by writing 0x02 to the CMODE bit field in the USARTn.CTRLC register. The data
on the TXD/RXD pins are the inverted values of the transmitted/received infrared pulse. It is also possible to select an
event channel from the Event System as an input for the IRCOM receiver. This enables the IRCOM to receive input
from the I/O pins or sources other than the corresponding RXD pin, which will disable the RxD input from the USART
pin.
For transmission, three pulse modulation schemes are available:
•
•
•
3/16 of the baud rate period
Fixed programmable pulse time based on the peripheral clock frequency
Pulse modulation disabled
For the reception, a fixed programmable minimum high-level pulse-width for the pulse to be decoded as a logical ‘0’
is used. Shorter pulses will then be discarded, and the bit will be decoded to logical ‘1’ as if no pulse was received.
Double-Speed mode cannot be used for the USART when IRCOM mode is enabled.
23.3.4
Additional Features
23.3.4.1 Parity
Parity bits can be used by the USART to check the validity of a data frame. The Parity bit is set by the transmitter
based on the number of bits with the value of ‘1’ in a transmission and controlled by the receiver upon reception.
If the Parity bit is inconsistent with the transmission frame, the receiver may assume that the data frame has been
corrupted.
Even or odd parity can be selected for error checking by writing the Parity Mode (PMODE) bit field in the
USARTn.CTRLC register. If even parity is selected, the Parity bit is set to ‘1’ if the number of Data bits with value ‘1’
is odd (making the total number of bits with value ‘1’ even). If odd parity is selected, the Parity bit is set to ‘1’ if the
number of data bits with value ‘1’ is even (making the total number of bits with value ‘1’ odd).
When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result
with the Parity bit of the corresponding frame. If a parity error is detected, the Parity Error flag (the PERR bit in the
USARTn.RXDATAH register) is set.
If LIN Constrained Auto-Baud mode is enabled (RXMODE = 0x03 in the USARTn.CTRLB register), a parity check
is performed only on the protected identifier field. A parity error is detected if one of the equations below is not true,
which sets the Parity Error flag.
P0 = ID0 XOR ID1 XOR ID2 XOR ID4
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P1 = NOT ID1 XOR ID3 XOR ID4 XOR ID5
Figure 23-14. Protected Identifier Field and Mapping of Identifier and Parity Bits
St
Protected identifier field
ID0 ID1 ID2 ID3 ID4 ID5 P0
P1
Sp
23.3.4.2 Start-of-Frame Detection
The Start-of-Frame Detection feature enables the USART to wake up from Standby sleep mode upon data reception.
When a high-to-low transition is detected on the RXD pin, the oscillator is powered up, and the USART peripheral
clock is enabled. After start-up, the rest of the data frame can be received, provided that the baud rate is slow enough
concerning the oscillator start-up time. The start-up time of the oscillators varies with supply voltage and temperature.
For details on oscillator start-up time characteristics, refer to the Electrical Characteristics section.
If a false Start bit is detected, the device will, if another wake-up source has not been triggered, go back into the
Standby sleep mode.
The Start-of-Frame detection works in Asynchronous mode only. It is enabled by writing the Start-of-Frame Detection
Enable (SFDEN) bit in the USARTn.CTRLB register. If a Start bit is detected while the device is in Standby sleep
mode, the USART Receive Start Interrupt Flag (RXSIF) bit is set.
The USART Receive Complete Interrupt Flag (RXCIF) bit and the RXSIF bit share the same interrupt line, but each
has its dedicated interrupt settings. The table below shows the USART Start Frame Detection modes, depending on
the interrupt setting.
Table 23-6. USART Start Frame Detection Modes
SFDEN RXSIF Interrupt RXCIF Interrupt Comment
0
x
x
Standard mode
1
Disabled
Disabled
Only the oscillator is powered during the frame reception. If the
interrupts are disabled and buffer overflow is ignored, all incoming
frames will be lost
1
Disabled
Enabled
System/all clocks are awakened on Receive Complete interrupt
1
Enabled
x
System/all clocks are awakened when a Start bit is detected
Note: The SLEEP instruction will not shut down the oscillator if there is ongoing communication.
23.3.4.3 Multiprocessor Communication
The Multiprocessor Communication mode (MPCM) effectively reduces the number of incoming frames that have
to be handled by the receiver in a system with multiple microcontrollers communicating via the same serial bus.
This mode is enabled by writing a ‘1’ to the MPCM bit in the Control B (USARTn.CTRLB) register. In this mode, a
dedicated bit in the frames is used to indicate whether the frame is an address or data frame type.
If the receiver is set up to receive frames that contain five to eight data bits, the first Stop bit is used to indicate the
frame type. If the receiver is set up for frames with nine data bits, the ninth bit is used to indicate frame type. When
the frame type bit is ‘1’, the frame contains an address. When the frame type bit is ‘0’, the frame is a data frame. If 5to 8-bit character frames are used, the transmitter must be set to use two Stop bits since the first Stop bit is used for
indicating the frame type.
If a particular client MCU has been addressed, it will receive the following data frames as usual, while the other client
MCUs will ignore the frames until another address frame is received.
23.3.4.3.1 Using Multiprocessor Communication
Use the following procedure to exchange data in Multiprocessor Communication mode (MPCM):
1.
2.
All client MCUs are in Multiprocessor Communication mode.
The host MCU sends an address frame, and all clients receive and read this frame.
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3.
4.
Each client MCU determines if it has been selected.
The addressed MCU will disable MPCM and receive all data frames. The other client MCUs will ignore the
data frames.
When the addressed MCU has received the last data frame, it must enable MPCM again and wait for a new
address frame from the host.
5.
The process then repeats from step 2.
23.3.5
Events
The USART can generate the events described in the table below.
Table 23-7. Event Generators in USART
Generator Name
Description
Peripheral Event
USARTn
XCK
The clock signal in SPI Host mode
and Synchronous USART Host
mode
Event Type
Generating Clock
Domain
Length of Event
Pulse
CLK_PER
One XCK period
The table below describes the event user and its associated functionality.
Table 23-8. Event Users in USART
User Name
23.3.6
Peripheral
Input
USARTn
IREI
Description
USARTn IrDA event input
Input Detection
Async/Sync
Pulse
Sync
Interrupts
Table 23-9. Available Interrupt Vectors and Sources
Name Vector Description
Conditions
RXC
Receive Complete interrupt
•
•
•
There is unread data in the receive buffer (RXCIE)
Receive of Start-of-Frame detected (RXSIE)
Auto-Baud Error/ISFIF flag set (ABEIE)
DRE
Data Register Empty
interrupt
The transmit buffer is empty/ready to receive new data (DREIE)
TXC
Transmit Complete
interrupt
The entire frame in the Transmit Shift register has been shifted out and there
are no new data in the transmit buffer (TXCIE)
When an Interrupt condition occurs, the corresponding Interrupt flag is set in the STATUS (USARTn.STATUS)
register.
An interrupt source is enabled or disabled by writing to the corresponding bit in the Control A (USARTn.CTRLA)
register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the Interrupt flag is set.
The interrupt request remains active until the Interrupt flag is cleared. See the USARTn.STATUS register for details
on how to clear Interrupt flags.
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23.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x07
RXDATAL
RXDATAH
TXDATAL
TXDATAH
STATUS
CTRLA
CTRLB
CTRLC
CTRLC
0x08
BAUD
0x0A
0x0B
0x0C
0x0D
0x0E
CTRLD
DBGCTRL
EVCTRL
TXPLCTRL
RXPLCTRL
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
23.5
7
6
RXCIF
BUFOVF
5
4
3
2
1
0
FERR
PERR
DATA[8]
DATA[7:0]
DATA[7:0]
RXCIF
TXCIF
RXCIE
TXCIE
RXEN
TXEN
CMODE[1:0]
CMODE[1:0]
DREIF
DREIE
RXSIF
RXSIE
SFDEN
PMODE[1:0]
ISFIF
LBME
ODME
SBMODE
DATA[8]
BDF
WFB
ABEIE
RS485[1:0]
RXMODE[1:0]
MPCM
CHSIZE[2:0]
UDORD
UCPHA
BAUD[7:0]
BAUD[15:8]
ABW[1:0]
DBGRUN
IREI
TXPL[7:0]
RXPL[6:0]
Register Description
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23.5.1
Receiver Data Register Low Byte
Name:
Offset:
Reset:
Property:
RXDATAL
0x00
0x00
-
This register contains the eight LSbs of the data received by the USART receiver. The USART receiver is doublebuffered, and this register always represents the data for the oldest received frame. If the data for only one frame is
present in the receive buffer, this register contains that data.
The buffer shifts out the data either when RXDATAL or RXDATAH is read, depending on the configuration. The
register, which does not lead to data being shifted, must be read first to be able to read both bytes before shifting.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low
byte first), a read of RXDATAH shifts the receive buffer, or else, RXDATAL shifts the buffer.
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
DATA[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – DATA[7:0] Receiver Data Register
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23.5.2
Receiver Data Register High Byte
Name:
Offset:
Reset:
Property:
RXDATAH
0x01
0x00
-
This register contains the MSb of the data received by the USART receiver, as well as status bits reflecting the status
of the received data frame. The USART receiver is double-buffered, and this register always represents the data and
status bits for the oldest received frame. If the data and status bits for only one frame is present in the receive buffer,
this register contains that data.
The buffer shifts out the data either when RXDATAL or RXDATAH is read, depending on the configuration. The
register, which does not lead to data being shifted, must be read first to be able to read both bytes before shifting.
When the Character Size (CHSIZE) bits in the Control C (USARTn.CTRLC) register is configured to 9-bit (low byte
first), a read of RXDATAH shifts the receive buffer, or else, RXDATAL shifts the buffer.
Bit
Access
Reset
7
RXCIF
R
0
6
BUFOVF
R
0
5
4
3
2
FERR
R
0
1
PERR
R
0
0
DATA[8]
R
0
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty.
Bit 6 – BUFOVF Buffer Overflow
This flag is set if a buffer overflow is detected. A buffer overflow occurs when the receive buffer is full, a new frame
is waiting in the receive shift register, and a new Start bit is detected. This flag is cleared when the Receiver Data
(USARTn.RXDATAL and USARTn.RXDATAH) registers are read.
This flag is not used in the Host SPI mode of operation.
Bit 2 – FERR Frame Error
This flag is set if the first Stop bit is ‘0’ and cleared when it is correctly read as ‘1’.
This flag is not used in the Host SPI mode of operation.
Bit 1 – PERR Parity Error
This flag is set if parity checking is enabled and the received data has a parity error, or else, this flag cleared. For
details on parity calculation, refer to 23.3.4.1 Parity.
This flag is not used in the Host SPI mode of operation.
Bit 0 – DATA[8] Receiver Data Register
When using a 9-bit frame size, this bit holds the ninth bit (MSb) of the received data.
When the Receiver Mode (RXMODE) bit field in the Control B (USARTn.CTRLB) register is configured to LIN
Constrained Auto-Baud (LINAUTO) mode, this bit indicates if the received data are within the response space of a
LIN frame. This bit is cleared if the received data are in the protected identifier field and is otherwise set.
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23.5.3
Transmit Data Register Low Byte
Name:
Offset:
Reset:
Property:
TXDATAL
0x02
0x00
-
The data written to this register is automatically loaded into the TX Buffer and through to the dedicated Shift register.
The shift register outputs each of the bits serially to the TXD pin.
When using a 9-bit frame size, the ninth bit (MSb) must be written to the Transmit Data Register High Byte
(USARTn.TXDATAH). In that case, the buffer shifts data either when the Transmit Data Register Low Byte
(USARTn.TXDATAL) or the Transmit Data Register High Byte (USARTn.TXDATAH) is written, depending on the
configuration. The register, which does not lead to data being shifted, must be written first to be able to write both
registers before shifting.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low
byte first), a write of the Transmit Data Register High Byte shifts the transmit buffer. Otherwise, the Transmit Data
Register Low Byte shifts the buffer.
This register may only be written when the Data Register Empty Interrupt Flag (DREIF) in the Status
(USARTn.STATUS) register is set.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Transmit Data Register Low Byte
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23.5.4
Transmit Data Register High Byte
Name:
Offset:
Reset:
Property:
TXDATAH
0x03
0x00
-
The data written to this register is automatically loaded into the TX Buffer and through to the dedicated Shift register.
The shift register outputs each of the bits serially to the TXD pin.
When using a 9-bit frame size, the ninth bit (MSb) must be written to the Transmit Data Register High Byte
(USARTn.TXDATAH). In that case, the buffer shifts data either when the Transmit Data Register Low Byte
(USARTn.TXDATAL) or the Transmit Data Register High Byte (USARTn.TXDATAH) is written, depending on the
configuration. The register, which does not lead to data being shifted, must be written first to be able to write both
registers before shifting.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low
byte first), a write of the Transmit Data Register High Byte shifts the transmit buffer. Otherwise, the Transmit Data
Register Low Byte shifts the buffer.
This register may only be written when the Data Register Empty Interrupt Flag (DREIF) in the Status
(USARTn.STATUS) register is set.
Bit
7
6
5
4
3
Access
Reset
2
1
0
DATA[8]
R/W
0
Bit 0 – DATA[8] Transmit Data Register High Byte
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23.5.5
USART Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIF
R
0
STATUS
0x04
0x00
-
6
TXCIF
R/W
0
5
DREIF
R
1
4
RXSIF
R/W
0
3
ISFIF
R/W
0
2
1
BDF
R/W
0
0
WFB
W
0
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty.
Bit 6 – TXCIF USART Transmit Complete Interrupt Flag
This flag is set when the entire frame in the Transmit Shift register has been shifted out, and there are no new data in
the transmit buffer (TXDATAL and TXDATAH) registers. It is cleared by writing a ‘1’ to it.
Bit 5 – DREIF USART Data Register Empty Interrupt Flag
This flag is set when the Transmit Data (USARTn.TXDATAL and USARTn.TXDATAH) registers are empty and
cleared when they contain data that has not yet been moved into the transmit shift register.
Bit 4 – RXSIF USART Receive Start Interrupt Flag
This flag is set when Start-of-Frame detection is enabled, the device is in Standby sleep mode, and a valid start bit is
detected. It is cleared by writing a ‘1’ to it.
This flag is not used in the Host SPI mode operation.
Bit 3 – ISFIF Inconsistent Synchronization Field Interrupt Flag
This flag is set if an auto-baud mode is enabled, and the synchronization field is too short or too long to give a valid
baud setting. It will also be set when USART is set to LINAUTO mode, and the SYNC character differs from data
value 0x55. This flag is cleared by writing a ‘1’ to it. See the Auto-Baud section for more information.
Bit 1 – BDF Break Detected Flag
This flag is set if an auto-baud mode is enabled and a valid break and synchronization character is detected, and is
cleared when the next data are received. It can also be cleared by writing a ‘1’ to it. See the Auto-Baud section for
more information.
Bit 0 – WFB Wait For Break
This bit controls whether the Wait For Break feature is enabled or not. Refer to the Auto-Baud section for more
information.
Value
Description
0
Wait For Break is disabled
1
Wait For Break is enabled
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23.5.6
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIE
R/W
0
CTRLA
0x05
0x00
-
6
TXCIE
R/W
0
5
DREIE
R/W
0
4
RXSIE
R/W
0
3
LBME
R/W
0
2
ABEIE
R/W
0
1
0
RS485[1:0]
R/W
0
R/W
0
Bit 7 – RXCIE Receive Complete Interrupt Enable
This bit controls whether the Receive Complete Interrupt is enabled or not. When enabled, the interrupt will be
triggered when the RXCIF bit in the USARTn.STATUS register is set.
Value
Description
0
The Receive Complete Interrupt is disabled
1
The Receive Complete Interrupt is enabled
Bit 6 – TXCIE Transmit Complete Interrupt Enable
This bit controls whether the Transmit Complete Interrupt is enabled or not. When enabled, the interrupt will be
triggered when the TXCIF bit in the USARTn.STATUS register is set.
Value
Description
0
The Transmit Complete Interrupt is disabled
1
The Transmit Complete Interrupt is enabled
Bit 5 – DREIE Data Register Empty Interrupt Enable
This bit controls whether the Data Register Empty Interrupt is enabled or not. When enabled, the interrupt will be
triggered when the DREIF bit in the USARTn.STATUS register is set.
Value
Description
0
The Data Register Empty Interrupt is disabled
1
The Data Register Empty Interrupt is enabled
Bit 4 – RXSIE Receiver Start Frame Interrupt Enable
This bit controls whether the Receiver Start Frame Interrupt is enabled or not. When enabled, the interrupt will be
triggered when the RXSIF bit in the USARTn.STATUS register is set.
Value
Description
0
The Receiver Start Frame Interrupt is disabled
1
The Receiver Start Frame Interrupt is enabled
Bit 3 – LBME Loop-Back Mode Enable
This bit controls whether the Loop-back mode is enabled or not. When enabled, an internal connection between the
TXD pin and the USART receiver is created, and the input from the RXD pin to the USART receiver is disconnected.
Value
Description
0
Loop-back mode is disabled
1
Loop-back mode is enabled
Bit 2 – ABEIE Auto-Baud Error Interrupt Enable
This bit controls whether the Auto-baud Error Interrupt is enabled or not. When enabled, the interrupt will be triggered
when the ISFIF bit in the USARTn.STATUS register is set.
Value
Description
0
The Auto-Baud Error Interrupt is disabled
1
The Auto-Baud Error Interrupt is enabled
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Bits 1:0 – RS485[1:0] RS-485 Mode
This bit field enables the RS-485 and selects the operation mode. Writing RS485[0] to ‘1’ enables the RS-485 mode,
which automatically drives the XDIR pin high one clock cycle before starting transmission and pulls it low again when
the transmission is complete. Writing RS485[1] to ‘1’ enables the RS-485 mode, which automatically sets the TXD pin
to output one clock cycle before starting transmission and sets it back to input when the transmission is complete.
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23.5.7
Control B
Name:
Offset:
Reset:
Property:
Bit
7
RXEN
R/W
0
Access
Reset
CTRLB
0x06
0x00
-
6
TXEN
R/W
0
5
4
SFDEN
R/W
0
3
ODME
R/W
0
2
1
RXMODE[1:0]
R/W
R/W
0
0
0
MPCM
R/W
0
Bit 7 – RXEN Receiver Enable
This bit controls whether the USART receiver is enabled or not. Refer to 23.3.2.4.2 Disabling the Receiver for more
information.
Value
Description
0
The USART receiver is disabled
1
The USART receiver is enabled
Bit 6 – TXEN Transmitter Enable
This bit controls whether the USART transmitter is enabled or not. Refer to 23.3.2.3.1 Disabling the Transmitter for
more information.
Value
Description
0
The USART transmitter is disabled
1
The USART transmitter is enabled
Bit 4 – SFDEN Start-of-Frame Detection Enable
This bit controls whether the USART Start-of-Frame Detection mode is enabled or not. Refer to 23.3.4.2 Start-ofFrame Detection for more information.
Value
Description
0
The USART Start-of-Frame Detection mode is disabled
1
The USART Start-of-Frame Detection mode is enabled
Bit 3 – ODME Open Drain Mode Enable
This bit controls whether Open Drain mode is enabled or not. See the One-Wire Mode section for more information.
Value
Description
0
Open Drain mode is disabled
1
Open Drain mode is enabled
Bits 2:1 – RXMODE[1:0] Receiver Mode
Writing this bit field selects the receiver mode of the USART.
• Writing the bits to 0x00 enables Normal-Speed (NORMAL) mode. When the USART Communication Mode
(CMODE) bit field in the Control C (USARTn.CTRLC) register is configured to Asynchronous USART
(ASYNCHRONOUS) or Infrared Communication (IRCOM), always write the RXMODE bit field to 0x00.
•
•
•
Writing the bits to 0x01 enables Double-Speed (CLK2X) mode. Refer to 23.3.3.2.4 Double-Speed Operation for
more information.
Writing the bits to 0x02 enables Generic Auto-Baud (GENAUTO) mode. Refer to the Auto-Baud section for
more information.
Writing the bits to 0x03 enables Lin Constrained Auto-Baud (LINAUTO) mode. Refer to the Auto-Baud section
for more information.
Value
0x00
0x01
0x02
0x03
Name
NORMAL
CLK2X
GENAUTO
LINAUTO
© 2021 Microchip Technology Inc.
Description
Normal-Speed mode
Double-Speed mode
Generic Auto-Baud mode
LIN Constrained Auto-Baud mode
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Bit 0 – MPCM Multi-Processor Communication Mode
This bit controls whether the Multi-Processor Communication mode is enabled or not. Refer to
23.3.4.3 Multiprocessor Communication for more information.
Value
Description
0
Multi-Processor Communication mode is disabled
1
Multi-Processor Communication mode is enabled
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23.5.8
Control C - Normal Mode
Name:
Offset:
Reset:
Property:
CTRLC
0x07
0x03
-
This register description is valid for all modes except the Host SPI mode. When the USART Communication Mode
(CMODE) bit field in this register is written to ‘MSPI’, see CTRLC - Host SPI mode for the correct description.
Bit
Access
Reset
7
6
CMODE[1:0]
R/W
R/W
0
0
5
4
PMODE[1:0]
R/W
R/W
0
0
3
SBMODE
R/W
0
2
R/W
0
1
CHSIZE[2:0]
R/W
1
0
R/W
1
Bits 7:6 – CMODE[1:0] USART Communication Mode
This bit field selects the communication mode of the USART.
Writing a 0x03 to these bits alters the available bit fields in this register. See CTRLC - Host SPI mode.
Value
Name
Description
0x00
ASYNCHRONOUS
Asynchronous USART
0x01
SYNCHRONOUS
Synchronous USART
0x02
IRCOM
Infrared Communication
0x03
MSPI
Host SPI
Bits 5:4 – PMODE[1:0] Parity Mode
This bit field enables and selects the type of parity generation. See 23.3.4.1 Parity for more information.
Value
Name
Description
0x0
DISABLED
Disabled
0x1
Reserved
0x2
EVEN
Enabled, even parity
0x3
ODD
Enabled, odd parity
Bit 3 – SBMODE Stop Bit Mode
This bit selects the number of Stop bits to be inserted by the transmitter.
The receiver ignores this setting.
Value
Description
0
1 Stop bit
1
2 Stop bits
Bits 2:0 – CHSIZE[2:0] Character Size
This bit field selects the number of data bits in a frame. The receiver and transmitter use the same setting. For
9BIT character size, the order of which byte to read or write first, low or high byte of RXDATA or TXDATA, can be
configured.
Value
Name
Description
0x00
5BIT
5-bit
0x01
6BIT
6-bit
0x02
7BIT
7-bit
0x03
8BIT
8-bit
0x04
Reserved
0x05
Reserved
0x06
9BITL
9-bit (Low byte first)
0x07
9BITH
9-bit (High byte first)
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23.5.9
Control C - Host SPI Mode
Name:
Offset:
Reset:
Property:
CTRLC
0x07
0x00
-
This register description is valid only when the USART is in Host SPI mode (CMODE written to MSPI). For other
CMODE values, see CTRLC - Normal Mode.
See 23.3.3.1.3 USART in Host SPI Mode for a full description of the Host SPI mode operation.
Bit
Access
Reset
7
6
CMODE[1:0]
R/W
R/W
0
0
5
4
3
2
UDORD
R/W
0
1
UCPHA
R/W
0
0
Bits 7:6 – CMODE[1:0] USART Communication Mode
This bit field selects the communication mode of the USART.
Writing a value different than 0x03 to these bits alters the available bit fields in this register. See CTRLC - Normal
Mode.
Value
Name
Description
0x00
ASYNCHRONOUS
Asynchronous USART
0x01
SYNCHRONOUS
Synchronous USART
0x02
IRCOM
Infrared Communication
0x03
MSPI
Host SPI
Bit 2 – UDORD USART Data Order
This bit controls the frame format. The receiver and transmitter use the same setting. Changing the setting of the
UDORD bit will corrupt all ongoing communication for both the receiver and the transmitter.
Value
Description
0
MSb of the data word is transmitted first
1
LSb of the data word is transmitted first
Bit 1 – UCPHA USART Clock Phase
This bit controls the phase of the interface clock. Refer to the Clock Generation section for more information.
Value
Description
0
Data are sampled on the leading (first) edge
1
Data are sampled on the trailing (last) edge
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23.5.10 Baud Register
Name:
Offset:
Reset:
Property:
BAUD
0x08
0x00
-
The USARTn.BAUDL and USARTn.BAUDH register pair represents the 16-bit value, USARTn.BAUD. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Ongoing transmissions of the transmitter and receiver will be corrupted if the baud rate is changed. Writing to this
register will trigger an immediate update of the baud rate prescaler. For more information on how to set the baud rate,
see Table 23-1.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BAUD[15:8] USART Baud Rate High Byte
This bit field holds the MSB of the 16-bit Baud register.
Bits 7:0 – BAUD[7:0] USART Baud Rate Low Byte
This bit field holds the LSB of the 16-bit Baud register.
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23.5.11 Control D
Name:
Offset:
Reset:
Property:
Bit
CTRLD
0x0A
0x00
-
7
6
5
4
3
2
1
0
ABW[1:0]
Access
Reset
R/W
0
R/W
0
Bits 7:6 – ABW[1:0] Auto-Baud Window Size
These bits control the tolerance for the difference between the baud rates between the two synchronizing devices
when using Lin Constrained Auto-baud mode. The tolerance is based on the number of baud samples between every
two bits. When baud rates are identical, there must be 32 baud samples between each bit pair since each bit is
sampled 16 times.
Value
Name
Description
0x00
WDW0
32±6 (18% tolerance)
0x01
WDW1
32±5 (15% tolerance)
0x02
WDW2
32±7 (21% tolerance)
0x03
WDW3
32±8 (25% tolerance)
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23.5.12 Debug Control Register
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0B
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
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23.5.13 IrDA Control Register
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x0C
0x00
-
6
5
4
3
Access
Reset
2
1
0
IREI
R/W
0
Bit 0 – IREI IrDA Event Input Enable
This bit controls whether the IrDA event input is enabled or not. See 23.3.3.2.7 IRCOM Mode of Operation for more
information.
Value
Description
0
IrDA Event input is enabled
1
IrDA Event input is disabled
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23.5.14 IRCOM Transmitter Pulse Length Control Register
Name:
Offset:
Reset:
Property:
Bit
7
TXPLCTRL
0x0D
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TXPL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TXPL[7:0] Transmitter Pulse Length
This 8-bit value sets the pulse modulation scheme for the transmitter. Setting this register will only have an effect if
IRCOM mode is selected by the USART, and it must be configured before the USART transmitter is enabled (TXEN).
Value
Description
0x00
3/16 of the baud rate period pulse modulation is used
0x01Fixed pulse length coding is used. The 8-bit value sets the number of peripheral clock periods for the
0xFE
pulse. The start of the pulse will be synchronized with the rising edge of the baud rate clock.
0xFF
Pulse coding disabled. RX and TX signals pass through the IRCOM module unaltered. This enables
other features through the IRCOM module, such as half-duplex USART, loop-back testing, and USART
RX input from an event channel.
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23.5.15 IRCOM Receiver Pulse Length Control Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXPLCTRL
0x0E
0x00
-
6
5
4
R/W
0
R/W
0
R/W
0
3
RXPL[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 6:0 – RXPL[6:0] Receiver Pulse Length
This 7-bit value sets the filter coefficient for the IRCOM transceiver. Setting this register will only have an effect if
IRCOM mode is selected by a USART, and it must be configured before the USART receiver is enabled (RXEN).
Value
Description
0x00
Filtering disabled
0x01Filtering enabled. The value of RXPL+1 represents the number of samples required for a received
0x7F
pulse to be accepted.
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SPI - Serial Peripheral Interface
24.
SPI - Serial Peripheral Interface
24.1
Features
•
•
•
•
•
•
•
•
24.2
Full Duplex, Three-Wire Synchronous Data Transfer
Host or Client Operation
LSb First or MSb First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double-Speed (CK/2) Host SPI Mode
Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four
pins. It allows full-duplex communication between an AVR® device and peripheral devices or between several
microcontrollers. The SPI peripheral can be configured as either host or client. The host initiates and controls all data
transactions.
The interconnection between host and client devices with SPI is shown in the block diagram. The system consists of
two shift registers and a server clock generator. The SPI host initiates the communication cycle by pulling the desired
client’s Client Select (SS) signal low. The host and client prepare the data to be sent to their respective shift registers,
and the host generates the required clock pulses on the SCK line to exchange data. Data are always shifted from
host to client on the host output, client input (MOSI) line, and from client to host on the host input, client output
(MISO) line.
24.2.1
Block Diagram
Figure 24-1. SPI Block Diagram
CLIENT
HOST
DATA
DATA
Transmit Data
Buffer
Transmit Data
Buffer
Buffer
mode
Buffer
mode
LSb
MSb
MISO
MISO
MOSI
MOSI
8-bit Shift Register
LSb
MSb
8-bit Shift Register
SPI CLOCK
GENERATOR
SCK
SCK
SS
SS
Receive Data
Receive Data
Receive Data
Buffer
Receive Data
Buffer
Buffer
mode
Buffer
mode
DATA
DATA
The SPI is built around an 8-bit shift register that will shift data out and in at the same time. The Transmit Data
register and the Receive Data register are not physical registers but are mapped to other registers when written or
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read: Writing the Transmit Data (SPIn.DATA) register will write the shift register in Normal mode and the Transmit
Buffer register in Buffer mode. Reading the Receive Data (SPIn.DATA) register will read the Receive Data register in
Normal mode and the Receive Data Buffer in Buffer mode.
In Host mode, the SPI has a clock generator to generate the SCK clock. In Client mode, the received SCK clock is
synchronized and sampled to trigger the shifting of data in the shift register.
24.2.2
Signal Description
Table 24-1. Signals in Host and Client Mode
Signal
Pin Configuration
Description
Host Mode
defined(1)
Client Mode
MOSI
Host Out Client In
User
MISO
Host In Client Out
Input
SCK
Serial Clock
User defined(1)
Input
Client Select
defined(1)
Input
SS
User
Input
User defined(1,2)
Notes:
1. If the pin data direction is configured as output, the pin level is controlled by the SPI.
2. If the SPI is in Client mode and the MISO pin data direction is configured as output, the SS pin controls the
MISO pin output in the following way:
– If the SS pin is driven low, the MISO pin is controlled by the SPI
– If the SS pin is driven high, the MISO pin is tri-stated
When the SPI module is enabled, the pin data direction for the signals marked with “Input” in Table 24-1 is
overridden.
24.3
Functional Description
24.3.1
Initialization
Initialize the SPI to a basic functional state by following these steps:
1. Configure the SS pin in the port peripheral.
2. Select the SPI host/client operation by writing the Host/Client Select (MASTER) bit in the Control A
(SPIn.CTRLA) register.
3. In Host mode, select the clock speed by writing the Prescaler (PRESC) bits and the Clock Double (CLK2X) bit
in SPIn.CTRLA.
4. Optional: Select the Data Transfer mode by writing to the MODE bits in the Control B (SPIn.CTRLB) register.
5. Optional: Write the Data Order (DORD) bit in SPIn.CTRLA.
6. Optional: Set up the Buffer mode by writing the BUFEN and BUFWR bits in the Control B (SPIn.CTRLB)
register.
7. Optional: To disable the multi-host support in Host mode, write ‘1’ to the Client Select Disable (SSD) bit in
SPIn.CTRLB.
8. Enable the SPI by writing a ‘1’ to the ENABLE bit in SPIn.CTRLA.
24.3.2
Operation
24.3.2.1 Host Mode Operation
When the SPI is configured in Host mode, a write to the SPIn.DATA register will start a new transfer. The SPI host
can operate in two modes, Normal and Buffer, as explained below.
24.3.2.1.1 Normal Mode
In Normal mode, the system is single-buffered in the transmit direction and double-buffered in the receive direction.
This influences the data handling in the following ways:
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1.
New bytes to be sent cannot be written to the DATA (SPIn.DATA) register before the entire transfer has been
completed. A premature write will cause corruption of the transmitted data, and the Write Collision (WRCOL)
flag in SPIn.INTFLAGS will be set.
Received bytes are written to the Receive Data Buffer register immediately after the transmission is
completed.
The Receive Data Buffer register has to be read before the next transmission is completed, or the data will be
lost. This register is read by reading SPIn.DATA.
The Transmit Data Buffer and Receive Data Buffer registers are not used in Normal mode.
2.
3.
4.
After a transfer has been completed, the Interrupt Flag (IF) will be set in the Interrupt Flags (SPIn.INTFLAGS)
register. This will cause the corresponding interrupt to be executed if this interrupt and the global interrupts are
enabled. Setting the Interrupt Enable (IE) bit in the Interrupt Control (SPIn.INTCTRL) register will enable the interrupt.
24.3.2.1.2 Buffer Mode
The Buffer mode is enabled by writing the BUFEN bit in the SPIn.CTRLB register to ‘1’. The BUFWR bit in
SPIn.CTRLB does not affect Host mode. In Buffer mode, the system is double-buffered in the transmit direction
and triple-buffered in the receive direction. This influences the data handling in the following ways:
1. New bytes can be written to the DATA (SPIn.DATA) register as long as the Data Register Empty Interrupt Flag
(DREIF) in the Interrupt Flag (SPIn.INTFLAGS) register is set. The first write will be transmitted right away, and
the following write will go to the Transmit Data Buffer register.
2. A received byte is placed in a two-entry Receive First-In, First-Out (RX FIFO) queue comprised of the Receive
Data register and Receive Data Buffer immediately after the transmission is completed.
3. The DATA register is used to read from the RX FIFO. The RX FIFO must be read at least every second
transfer to avoid any loss of data.
When both the shift register and the Transmit Data Buffer register become empty, the Transfer Complete Interrupt
Flag (TXCIF) in the Interrupt Flags (SPIn.INTFLAGS) register will be set. This will cause the corresponding interrupt
to be executed if this interrupt and the global interrupts are enabled. Setting the Transfer Complete Interrupt Enable
(TXCIE) in the Interrupt Control (SPIn.INTCTRL) register enables the Transfer Complete Interrupt.
24.3.2.1.3 SS Pin Functionality in Host Mode - Multi-Host Support
In Host mode, the Client Select Disable (SSD) bit in the Control B (SPIn.CTRLB) register controls how the SPI uses
the SS pin.
•
•
•
If SSD in SPIn.CTRLB is ‘0’, the SPI can use the SS pin to transition from Host to Client mode. This allows
multiple SPI hosts on the same SPI bus.
If SSD in SPIn.CTRLB is ‘0’, and the SS pin is configured as an output pin, it can be used as a regular I/O pin or
by other peripheral modules and will not affect the SPI system
If SSD in SPIn.CTRLB is ‘1’, the SPI does not use the SS pin. It can be used as a regular I/O pin or by other
peripheral modules.
If the SSD bit in SPIn.CTRLB is ‘0’, and the SS is configured as an input pin, the SS pin must be held high to ensure
Host SPI operation. A low level will be interpreted as another Host is trying to take control of the bus. This will switch
the SPI into Client mode, and the hardware of the SPI will perform the following actions:
1. The Host (MASTER) bit in the SPI Control A (SPIn.CTRLA) register is cleared, and the SPI system becomes a
client. The direction of the SPI pins will be switched when the conditions in Table 24-2 are met.
2. The Interrupt Flag (IF) bit in the Interrupt Flags (SPIn.INTFLAGS) register will be set. If the interrupt is enabled
and the global interrupts are enabled, the interrupt routine will be executed.
Table 24-2. Overview of the SS Pin Functionality when the SSD Bit in SPIn.CTRLB is ‘0’
SS Configuration
Input
Output
© 2021 Microchip Technology Inc.
SS Pin-Level
Description
High
Host activated (selected)
Low
Host deactivated, switched to Client
mode
High
Host activated (selected)
Low
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Note: If the device is in Host mode and it cannot be ensured that the SS pin will stay high between two
transmissions, the status of the Host (MASTER) bit in SPIn.CTRLA has to be checked before a new byte is written.
After the Host bit has been cleared by a low level on the SS line, it must be set by the application to re-enable the SPI
Host mode.
24.3.2.2 Client Mode
In Client mode, the SPI peripheral receives SPI clock and Client Select from a Host. Client mode supports three
operational modes: One Normal mode and two configurations for the Buffered mode. In Client mode, the control logic
will sample the incoming signal on the SCK pin. To ensure correct sampling of this clock signal, the minimum low and
high periods must each be longer than two peripheral clock cycles.
24.3.2.2.1 Normal Mode
In Normal mode, the SPI peripheral will remain Idle as long as the SS pin is driven high. In this state, the software
may update the contents of the DATA register, but the data will not be shifted out by incoming clock pulses on the
SCK pin until the SS pin is driven low. If the SS pin is driven low, the client will start to shift out data on the first SCK
clock pulse. When one byte has been completely shifted, the SPI Interrupt Flag (IF) in SPIn.INTFLAGS is set.
The user application may continue placing new data to be sent into the DATA register before reading the incoming
data. New bytes to be sent cannot be written to the DATA register before the entire transfer has been completed. A
premature write will be ignored, and the hardware will set the Write Collision (WRCOL) flag in SPIn.INTFLAGS.
When the SS pin is driven high, the SPI logic is halted, and the SPI client will not receive any new data. Any partially
received packet in the shift register will be lost.
Figure 24-2 shows a transmission sequence in Normal mode. Notice how the value 0x45 is written to the DATA
register but never transmitted.
Figure 24-2. SPI Timing Diagram in Normal Mode (Buffer Mode Not Enabled)
SS
SCK
Write DATA
Write value
0x43
0x44
0x45
0x46
WRCOL
IF
Shift Register
Data sent
0x43
0x43
0x44
0x44
0x46
0x46
The figure above shows three transfers and one write to the DATA register while the SPI is busy with a transfer. This
write will be ignored, and the Write Collision (WRCOL) flag in SPIn.INTFLAGS is set.
24.3.2.2.2 Buffer Mode
To avoid data collisions, the SPI peripheral can be configured in Buffered mode by writing a ‘1’ to the Buffer Mode
Enable (BUFEN) bit in the Control B (SPIn.CTRLB) register. In this mode, the SPI has additional interrupt flags
and extra buffers. The extra buffers are shown in Figure 24-1. There are two different modes for the Buffer mode,
selected with the Buffer mode Wait for Receive (BUFWR) bit. The two different modes are described below with
timing diagrams.
Client Buffer Mode with Wait for Receive Bit Written to ‘0’
In Client mode, if the Buffer mode Wait for Receive (BUFWR) bit in SPIn.CTRLB is written to ‘0’, a dummy byte
will be sent before the transmission of user data starts. Figure 24-3 shows a transmission sequence with this
configuration. Notice how the value 0x45 is written to the Data (SPIn.DATA) register but never transmitted.
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SPI - Serial Peripheral Interface
Figure 24-3. SPI Timing Diagram in Buffer Mode with BUFWR in SPIn.CTRLB Written to ‘0’
SS
SCK
Write DATA
Write value
0x43
0x44
0x45
0x46
DREIF
TXCIF
RXCIF
Transmit Buffer
Shift Register
Data sent
0x43
Dummy
Dummy
0x46
0x44
0x44
0x43
0x43
0x44
0x46
0x46
When the Wait for Receive (BUFWR) bit in SPIn.CTRLB is written to ‘0’, all writes to the Data (SPIn.DATA)
register go to the Transmit Data Buffer register. The figure above shows that the value 0x43 is written to the Data
(SPIn.DATA) register but not immediately transferred to the shift register, so the first byte sent will be a dummy byte.
The value of the dummy byte equals the values that were in the shift register at the same time. After the first dummy
transfer is completed, the value 0x43 is transferred to the shift register. Then 0x44 is written to the Data (SPIn.DATA)
register and goes to the Transmit Data Buffer register. A new transfer is started, and 0x43 will be sent. The value
0x45 is written to the Data (SPIn.DATA) register, but the Transmit Data Buffer register is not updated since it is
already full containing 0x44 and the Data Register Empty Interrupt Flag (DREIF) in SPIn.INTFLAGS is low. The value
0x45 will be lost. After the transfer, the value 0x44 is moved to the shift register. During the next transfer, 0x46 is
written to the Data (SPIn.DATA) register, and 0x44 is sent out. After the transfer is complete, 0x46 is copied into the
shift register and sent out in the next transfer.
The DREIF goes low every time the Transmit Data Buffer register is written and goes high after a transfer when the
previous value in the Transmit Data Buffer register is copied into the shift register. The Receive Complete Interrupt
Flag (RXCIF) in SPIn.INTFLAGS is set one cycle after the DREIF goes high. The Transfer Complete Interrupt Flag
is set one cycle after the Receive Complete Interrupt Flag is set when both the value in the shift register and in the
Transmit Data Buffer register has been sent.
Client Buffer Mode with Wait for Receive Bit Written to ‘1’
In Client mode, if the Buffer mode Wait for Receive (BUFWR) bit in SPIn.CRTLB is written to ‘1’, the transmission
of user data starts as soon as the SS pin is driven low. Figure 24-4 shows a transmission sequence with this
configuration. Notice how the value 0x45 is written to the Data (SPIn.DATA) register but never transmitted.
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SPI - Serial Peripheral Interface
Figure 24-4. SPI Timing Diagram in Buffer Mode with CTRLB.BUFWR Written to ‘1’
SS
SCK
Write DATA
Write value
0x43
0x44
0x45
0x46
DREIF
TXCIF
RXCIF
Transmit Buffer
Shift Register
0x46
0x44
0x43
0x43
Data sent
0x46
0x44
0x43
0x44
0x46
All writes to the Data (SPIn.DATA) register go to the Transmit Data Buffer register. The figure above shows that the
value 0x43 is written to the Data (SPIn.DATA) register, and since the SS pin is high, it is copied to the shift register
in the next cycle. The next write (0x44) will go to the Transmit Data Buffer register. During the first transfer, the
value 0x43 will be shifted out. In the figure above, the value 0x45 is written to the Data (SPIn.DATA) register, but the
Transmit Data Buffer register is not updated since the DREIF is low. After the transfer is completed, the value 0x44
from the Transmit Data Buffer register is copied to the shift register. The value 0x46 is written to the Transmit Data
Buffer register. During the next two transfers, 0x44 and 0x46 are shifted out. The flags behave identically to the Buffer
Mode Wait for Receive (BUFWR) bit in SPIn.CTRLB set to ‘0’.
24.3.2.2.3 SS Pin Functionality in Client Mode
The Client Select (SS) pin plays a central role in the operation of the SPI. Depending on the SPI mode and the
configuration of this pin, it can be used to activate or deactivate devices. The SS pin is used as a Chip Select pin.
In Client mode, the SS, MOSI, and SCK are always inputs. The behavior of the MISO pin depends on the configured
data direction of the pin in the port peripheral and the value of SS. When the SS pin is driven low, the SPI is activated
and will respond to received SCK pulses by clocking data out on MISO if the user has configured the data direction
of the MISO pin as an output. When the SS pin is driven high, the SPI is deactivated, meaning that it will not receive
incoming data. If the MISO pin data direction is configured as an output, the MISO pin will be tri-stated. Table 24-3
shows an overview of the SS pin functionality.
Table 24-3. Overview of the SS Pin Functionality
MISO Pin Mode
SS Configuration
SS Pin-Level
Description
Port Direction =
Output
Port Direction =
Input
High
Client deactivated
(deselected)
Tri-stated
Input
Low
Client activated
(selected)
Output
Input
Always Input
Note: In Client mode, the SPI state machine will be reset when the SS pin is driven high. If the SS pin is driven
high during a transmission, the SPI will stop sending and receiving data immediately and both data received and data
sent must be considered lost. As the SS pin is used to signal the start and end of a transfer, it is useful for achieving
packet/byte synchronization and keeping the Client bit counter synchronized with the host clock generator.
24.3.2.3 Data Modes
There are four combinations of SCK phase and polarity concerning the serial data. The desired combination is
selected by writing to the MODE bits in the Control B (SPIn.CTRLB) register.
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SPI - Serial Peripheral Interface
The SPI data transfer formats are shown below. Data bits are shifted out and latched in on opposite edges of the
SCK signal, ensuring sufficient time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
Figure 24-5. SPI Data Transfer Modes
1
2
3
4
5
6
7
8
MISO
1
2
3
4
5
6
7
8
MOSI
1
2
3
4
5
6
7
8
SPI Mode 0
Cycle #
SS
SCK
Sampling
SPI Mode 1
Cycle #
1
2
3
4
5
6
7
8
MISO
1
2
3
4
5
6
7
8
MOSI
1
2
3
4
5
6
7
8
SS
SCK
Sampling
SPI Mode 2
Cycle #
1
2
3
4
5
6
7
8
MISO
1
2
3
4
5
6
7
8
MOSI
1
2
3
4
5
6
7
8
SS
SCK
Sampling
SPI Mode 3
Cycle #
1
2
3
4
5
6
7
8
MISO
1
2
3
4
5
6
7
8
MOSI
1
2
3
4
5
6
7
8
SS
SCK
Sampling
24.3.2.4 Events
The SPI can generate the following events:
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SPI - Serial Peripheral Interface
Table 24-4. Event Generators in SPI
Generator Name
Module
Event
SPIn
SCK
Description
Event Type
SPI Host clock
Level
Generating
Clock
Domain
CLK_PER
Length of Event
Minimum two CLK_PER periods
The SPI has no event users.
Refer to the Event System section for more details regarding event types and Event System configuration.
24.3.2.5 Interrupts
Table 24-5. Available Interrupt Vectors and Sources
Name
SPIn
Conditions
Vector Description
SPI interrupt
Normal Mode
•
•
IF: Interrupt Flag interrupt
WRCOL: Write Collision interrupt
Buffer Mode
•
•
•
•
SSI: Client Select Trigger Interrupt
DRE: Data Register Empty interrupt
TXC: Transfer Complete interrupt
RXC: Receive Complete interrupt
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
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SPI - Serial Peripheral Interface
24.4
Register Summary
Offset
Name
Bit Pos.
7
6
5
4
0x00
0x01
0x02
0x03
0x03
0x04
CTRLA
CTRLB
INTCTRL
INTFLAGS
INTFLAGS
DATA
7:0
7:0
7:0
7:0
7:0
7:0
DORD
BUFWR
TXCIE
WRCOL
TXCIF
MASTER
CLK2X
BUFEN
RXCIE
IF
RXCIF
DREIE
SSIE
DREIF
SSIF
DATA[7:0]
24.5
3
2
1
PRESC[1:0]
SSD
0
ENABLE
MODE[1:0]
IE
BUFOVF
Register Description
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SPI - Serial Peripheral Interface
24.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
-
6
DORD
R/W
0
5
MASTER
R/W
0
4
CLK2X
R/W
0
3
2
1
PRESC[1:0]
R/W
R/W
0
0
0
ENABLE
R/W
0
Bit 6 – DORD Data Order
Value
Description
0
The MSb of the data word is transmitted first
1
The LSb of the data word is transmitted first
Bit 5 – MASTER Host/Client Select
This bit selects the desired SPI mode.
If SS is configured as input and driven low while this bit is ‘1’, then this bit is cleared, and the IF in SPIn.INTFLAGS is
set. The user has to write MASTER = 1 again to re-enable SPI Host mode.
This behavior is controlled by the Client Select Disable (SSD) bit in SPIn.CTRLB.
Value
Description
0
SPI Client mode selected
1
SPI Host mode selected
Bit 4 – CLK2X Clock Double
When this bit is written to ‘1’, the SPI speed (SCK frequency, after internal prescaler) is doubled in Host mode.
Value
Description
0
SPI speed (SCK frequency) is not doubled
1
SPI speed (SCK frequency) is doubled in Host mode
Bits 2:1 – PRESC[1:0] Prescaler
This bit field controls the SPI clock rate configured in Host mode. These bits have no effect in Client mode. The
relationship between SCK and the peripheral clock frequency (fCLK_PER) is shown below.
The output of the SPI prescaler can be doubled by writing the CLK2X bit to ‘1’.
Value
Name
Description
0x0
DIV4
CLK_PER/4
0x1
DIV16
CLK_PER/16
0x2
DIV64
CLK_PER/64
0x3
DIV128
CLK_PER/128
Bit 0 – ENABLE SPI Enable
Value
Description
0
SPI is disabled
1
SPI is enabled
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SPI - Serial Peripheral Interface
24.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BUFEN
R/W
0
CTRLB
0x01
0x00
-
6
BUFWR
R/W
0
5
4
3
2
SSD
R/W
0
1
0
MODE[1:0]
R/W
0
R/W
0
Bit 7 – BUFEN Buffer Mode Enable
Writing this bit to ‘1’ enables Buffer mode. This will enable two receive buffers and one transmit buffer. Both will have
separate interrupt flags, transmit complete and receive complete.
Bit 6 – BUFWR Buffer Mode Wait for Receive
When writing this bit to ‘0’, the first data transferred will be a dummy sample.
Value
Description
0
One SPI transfer must be completed before the data are copied into the shift register
1
If writing to the Data register when the SPI is enabled and SS is high, the first write will go directly to
the shift register
Bit 2 – SSD Client Select Disable
If this bit is set when operating as SPI Host (MASTER = 1 in SPIn.CTRLA), SS does not disable Host mode.
Value
Description
0
Enable the Client Select line when operating as SPI host
1
Disable the Client Select line when operating as SPI host
Bits 1:0 – MODE[1:0] Mode
These bits select the Transfer mode. The four combinations of SCK phase and polarity concerning the serial data are
shown below. These bits decide whether the first edge of a clock cycle (leading edge) is rising or falling and whether
data setup and sample occur on the leading or trailing edge. When the leading edge is rising, the SCK signal is low
when idle, and when the leading edge is falling, the SCK signal is high when idle.
Value
Name
Description
0x0
0
Leading edge: Rising, sample
Trailing edge: Falling, setup
0x1
1
Leading edge: Rising, setup
Trailing edge: Falling, sample
0x2
2
Leading edge: Falling, sample
Trailing edge: Rising, setup
0x3
3
Leading edge: Falling, setup
Trailing edge: Rising, sample
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SPI - Serial Peripheral Interface
24.5.3
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIE
R/W
0
INTCTRL
0x02
0x00
-
6
TXCIE
R/W
0
5
DREIE
R/W
0
4
SSIE
R/W
0
3
2
1
0
IE
R/W
0
Bit 7 – RXCIE Receive Complete Interrupt Enable
In Buffer mode, this bit enables the Receive Complete interrupt. The enabled interrupt will be triggered when the
RXCIF in the SPIn.INTFLAGS register is set. In the Non-Buffer mode, this bit is ‘0’.
Bit 6 – TXCIE Transfer Complete Interrupt Enable
In Buffer mode, this bit enables the Transfer Complete interrupt. The enabled interrupt will be triggered when the
TXCIF in the SPIn.INTFLAGS register is set. In the Non-Buffer mode, this bit is ‘0’.
Bit 5 – DREIE Data Register Empty Interrupt Enable
In Buffer mode, this bit enables the Data Register Empty interrupt. The enabled interrupt will be triggered when the
DREIF in the SPIn.INTFLAGS register is set. In the Non-Buffer mode, this bit is ‘0’.
Bit 4 – SSIE Client Select Trigger Interrupt Enable
In Buffer mode, this bit enables the Client Select interrupt. The enabled interrupt will be triggered when the SSIF in
the SPIn.INTFLAGS register is set. In the Non-Buffer mode, this bit is ‘0’.
Bit 0 – IE Interrupt Enable
This bit enables the SPI interrupt when the SPI is not in Buffer mode. The enabled interrupt will be triggered when
RXCIF/IF is set in the SPIn.INTFLAGS register.
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SPI - Serial Peripheral Interface
24.5.4
Interrupt Flags - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
IF
R/W
0
INTFLAGS
0x03
0x00
-
6
WRCOL
R/W
0
5
4
3
2
1
0
Bit 7 – IF Interrupt Flag
This flag is set when a serial transfer is complete, and one byte is completely shifted in/out of the SPIn.DATA register.
If SS is configured as input and is driven low when the SPI is in Host mode, this will also set this flag. The IF is
cleared by hardware when executing the corresponding interrupt vector. Alternatively, the IF can be cleared by first
reading the SPIn.INTFLAGS register when IF is set and then accessing the SPIn.DATA register.
Bit 6 – WRCOL Write Collision
The WRCOL flag is set if the SPIn.DATA register is written before a complete byte has been shifted out. This flag is
cleared by first reading the SPIn.INTFLAGS register when WRCOL is set and then accessing the SPIn.DATA register.
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SPI - Serial Peripheral Interface
24.5.5
Interrupt Flags - Buffer Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIF
R/W
0
INTFLAGS
0x03
0x00
-
6
TXCIF
R/W
0
5
DREIF
R/W
0
4
SSIF
R/W
0
3
2
1
0
BUFOVF
R/W
0
Bit 7 – RXCIF Receive Complete Interrupt Flag
This flag is set when there are unread data in the Receive Data Buffer register and cleared when the Receive Data
Buffer register is empty (that is, it does not contain any unread data).
When interrupt-driven data reception is used, the Receive Complete Interrupt routine must read the received data
from the DATA register to clear RXCIF. If not, a new interrupt will occur directly after the return from the current
interrupt. This flag can also be cleared by writing a ‘1’ to its bit location.
Bit 6 – TXCIF Transfer Complete Interrupt Flag
This flag is set when all the data in the Transmit shift register has been shifted out, and there is no new data in the
transmit buffer (SPIn.DATA). The flag is cleared by writing a ‘1’ to its bit location.
Bit 5 – DREIF Data Register Empty Interrupt Flag
This flag indicates whether the Transmit Data Buffer register is ready to receive new data. The flag is ‘1’ when the
transmit buffer is empty and ‘0’ when the transmit buffer contains data to be transmitted that has not yet been moved
into the shift register. The DREIF is cleared after a Reset to indicate that the transmitter is ready.
The DREIF is cleared by writing to DATA. When interrupt-driven data transmission is used, the Data Register Empty
Interrupt routine must either write new data to DATA to clear DREIF or disable the Data Register Empty interrupt. If
not, a new interrupt will occur directly after the return from the current interrupt.
Bit 4 – SSIF Client Select Trigger Interrupt Flag
This flag indicates that the SPI has been in Host mode, and the SS pin has been pulled low externally, so the SPI
is now working in Client mode. The flag will only be set if the Client Select Disable (SSD) bit is not ‘1’. The flag is
cleared by writing a ‘1’ to its bit location.
Bit 0 – BUFOVF Buffer Overflow
This flag indicates data loss due to a Receive Data Buffer full condition. This flag is set if a Buffer Overflow condition
is detected. A Buffer Overflow occurs when the receive buffer is full (two bytes), and a third byte has been received
in the shift register. If there is no transmit data, the Buffer Overflow will not be set before the start of a new serial
transfer. This flag is cleared when the DATA register is read or by writing a ‘1’ to its bit location.
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SPI - Serial Peripheral Interface
24.5.6
Data
Name:
Offset:
Reset:
Property:
Bit
7
DATA
0x04
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] SPI Data
The DATA register is used for sending and receiving data. Writing to the register initiates the data transmission when
in Host mode while preparing data for sending in Client mode. The byte written to the register shifts out on the SPI
output line when a transaction is initiated.
The SPIn.DATA register is not a physical register. Depending on what mode is configured, it is mapped to other
registers, as described below.
• Normal mode:
– Writing the DATA register will write the shift register
– Reading from DATA will read from the Receive Data register
• Buffer mode:
– Writing the DATA register will write to the Transmit Data Buffer register
– Reading from DATA will read from the Receive Data Buffer register. The contents of the Receive Data
register will then be moved to the Receive Data Buffer register.
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ATmega808/809/1608/1609
TWI - Two-Wire Interface
25.
TWI - Two-Wire Interface
25.1
Features
•
•
•
•
•
•
•
25.2
Two-Wire Communication Interface
Philips I2C Compatible
– Standard mode
– Fast mode
– Fast mode Plus
System Management Bus (SMBus) 2.0 Compatible
– Support arbitration between Start/repeated Start and data bit
– Client arbitration allows support for the Address Resolution Protocol (ARP) in software
– Configurable SMBus Layer 1 time-outs in hardware
– Independent time-outs for Dual mode
Independent Host and Client Operation
– Combined (same pins) or Dual mode (separate pins)
– Single or multi-host bus operation with full arbitration support
Hardware Support for Client Address Match
– Operates in all sleep modes
– 7-bit address recognition
– General Call Address recognition
– Support for address range masking or secondary address match
Input Filter for Bus Noise Suppression
Smart Mode Support
Overview
The Two-Wire Interface (TWI) is a bidirectional, two-wire communication interface (bus) with a Serial Data Line (SDA)
and a Serial Clock Line (SCL).
The TWI bus connects one or several client devices to one or several host devices. Any device connected to the
bus can act as a host, a client, or both. The host generates the SCL by using a Baud Rate Generator (BRG) and
initiates data transactions by addressing one client and telling whether it wants to transmit or receive data. The BRG
is capable of generating the Standard mode (Sm) and Fast mode (Fm, Fm+) bus frequencies from 100 kHz up to 1
MHz.
The TWI will detect Start and Stop conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and
clock hold are also detected and indicated in separate status flags available in both Host and Client modes.
The TWI supports multi-host bus operation and arbitration. An arbitration scheme handles the case where more
than one host tries to transmit data at the same time. The TWI also supports Smart mode, which can auto-trigger
operations and thus reduce software complexity. The TWI supports Dual mode with simultaneous host and client
operations, which are implemented as independent units with separate enabling and configuration. The TWI supports
Quick Command mode, where the host can address a client without exchanging data.
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TWI - Two-Wire Interface
25.2.1
Block Diagram
Figure 25-1. TWI Block Diagram
Host
BAUD
TxDATA
0
Baud Rate Generator
Client
TxDATA
SCL
SCL Hold Low
0
SCL Hold Low
shift register
shift register
0
SDA
0
RxDATA
25.2.2
ADDR/ADDRMASK
RxDATA
==
Signal Description
Signal
Description
Type
SCL
Serial Clock Line
Digital I/O
SDA
Serial Data Line
Digital I/O
25.3
Functional Description
25.3.1
General TWI Bus Concepts
The TWI provides a simple, bidirectional, two-wire communication bus consisting of:
• Serial Data Line (SDA) for packet transfer
• Serial Clock Line (SCL) for the bus clock
The two lines are open-collector lines (wired-AND).
The TWI bus topology is a simple and efficient method of interconnecting multiple devices on a serial bus. A device
connected to the bus can be a host or a client. Only host devices can control the bus and the bus communication.
A unique address is assigned to each client device connected to the bus, and the host will use it to control the client
and initiate a transaction. Several hosts can be connected to the same bus. This is called a multi-host environment.
An arbitration mechanism is provided for resolving bus ownership among hosts since only one host device may own
the bus at any given time.
A host indicates the start of a transaction by issuing a Start condition (S) on the bus. The host provides the clock
signal for the transaction. An address packet with a 7-bit client address (ADDRESS) and a direction bit, representing
whether the host wishes to read or write data (R/W), are then sent.
The addressed I2C client will then acknowledge (ACK) the address, and data packet transactions can begin. Every
9-bit data packet consists of eight data bits followed by a 1-bit reply indicating whether the data was acknowledged or
not by the receiver.
After all the data packets (DATA) are transferred, the host issues a Stop condition (P) on the bus to end the
transaction.
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TWI - Two-Wire Interface
Figure 25-2. Basic TWI Transaction Diagram Topology for a 7-bit Address Bus
SDA
SCL
6 ... 0
S
7 ... 0
ADDRESS
S
ADDRESS
R/W
R/W
ACK
7 ... 0
DATA
ACK
DATA
A
A
DATA
P
ACK/NACK
DATA
A/A
P
Direction
Address Packet
Data Packet #0
Data Packet #1
Transaction
Bus Driver
Host driving bus
S
START condition
Client driving bus
Sr
repeated START condition
Either Host or Client driving bus
P
STOP condition
Data Package Direction
R
Host Read
W
Acknowledge
A
Acknowledge (ACK)
'0'
'1'
Host Write
'0'
25.3.2
Special Bus Conditions
A
Not Acknowledge (NACK)
'1'
TWI Basic Operation
25.3.2.1 Initialization
If used, the following bits must be configured before enabling the TWI device:
• The SDA Hold Time (SDAHOLD) bit field from the Control A (TWIn.CTRLA) register
• The FM Plus Enable (FMPEN) bit from the Control A (TWIn.CTRLA) register
25.3.2.1.1 Host Initialization
Write the Host Baud Rate (TWIn.MBAUD) register to a value that will result in a valid TWI bus clock frequency.
Writing a ‘1’ to the Enable TWI Host (ENABLE) bit in the Host Control A (TWIn.MCTRLA) register will enable the TWI
host. The Bus State (BUSSTATE) bit field from the Host Status (TWIn.MSTATUS) register must be set to 0x1 to force
the bus state to Idle.
25.3.2.1.2 Client Initialization
Follow these steps to initialize the client:
1.
2.
3.
Before enabling the TWI device, configure the SDA Setup Time (SDASETUP) bit from the Control A
(TWIn.CTRLA) register.
Write the address of the client to the Client Address (TWIn.SADDR) register.
Write a ‘1’ to the Enable TWI Client (ENABLE) bit in the Client Control A (TWIn.SCTRLA) register to enable
the TWI client.
The client device will now wait for a host device to issue a Start condition and the matching client address.
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25.3.2.2 TWI Host Operation
The TWI host is byte-oriented, with an optional interrupt after each byte. There are separate interrupt flags for the
host write and read operation. Interrupt flags can also be used for polled operation. There are dedicated status flags
for indicating ACK/NACK received, bus error, arbitration lost, clock hold, and bus state.
When an interrupt flag is set to ‘1’, the SCL is forced low. This will give the host time to respond or handle any data
and will, in most cases, require software interaction. Clearing the interrupt flags releases the SCL. The number of
interrupts generated is kept to a minimum by automatic handling of most conditions.
25.3.2.2.1 Clock Generation
The TWI supports several transmission modes with different frequency limitations:
• Standard mode (Sm) up to 100 kHz
• Fast mode (Fm) up to 400 kHz
• Fast mode Plus (Fm+) up to 1 MHz
Write the Host Baud Rate (TWIn.MBAUD) register to a value that will result in a TWI bus clock frequency equal to, or
less than, those frequency limits, depending on the transmission mode.
The low (tLOW) and high (tHIGH) times are determined by the Host Baud Rate (TWIn.MBAUD) register, while the rise
(tR) and fall (tOF) times are determined by the bus topology.
Figure 25-3. SCL Timing
SCL
tHD;STA
tSU;STA
tLOW
tHIGH
tOF
tSP
tHD;DAT
tSU;DAT
tR
tBUF
tSU;STO
SDA
S
•
•
•
•
P
S
tLOW is the low period of SCL clock
tHIGH is the high period of SCL clock
tR is determined by the bus impedance; for internal pull-ups. Refer to the Electrical Characteristics section for
details.
tOF is the output fall time and is determined by the open-drain current limit and bus impedance. Refer to the
Electrical Characteristics section for details.
Properties of the SCL Clock
The SCL frequency is given by:
Equation 25-1. SCL Frequency
1
fSCL = t
[Hz]
LOW + tHIGH + tOF + tR
The SCL clock is designed to have a 50/50 duty cycle, where the low period of the duty cycle comprises of tOF and
tLOW. tHIGH will not start until a high state of SCL has been detected. The BAUD bit field in the TWIn.MBAUD register
and the SCL frequency are related by the following formula:
Equation 25-2. SCL Frequency
fSCL =
fCLK_PER
10 + 2 × BAUD + fCLK_PER × tR
Equation 25-2 can be transformed to express BAUD:
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Equation 25-3. BAUD
BAUD =
fCLK_PER
fCLK_PER × tR
− 5+
2
2 × fSCL
Calculation of the BAUD Value
To ensure operation within the specifications of the desired speed mode (Sm, Fm, Fm+), follow these steps:
1. Calculate a value for the BAUD bit field using Equation 25-3.
2. Calculate tLOW using the BAUD value from step 1:
3.
Equation 25-4. tLOW
tLOW = BAUD + 5 − tOF
fCLK_PER
Check if tLOW from Equation 25-4 is above the specified minimum of the desired mode (tLOW_Sm = 4700 ns,
tLOW_Fm = 1300 ns, tLOW_Fm+ = 500 ns).
– If the calculated tLOW is above the limit, use the BAUD value from Equation 25-3
– If the limit is not met, calculate a new BAUD value using Equation 25-5 below, where tLOW_mode is either
tLOW_Sm, tLOW_Fm, or tLOW_Fm+ from the mode specifications:
Equation 25-5. BAUD
BAUD = fCLK_PER × (tLOW_mode + tOF) − 5
25.3.2.2.2 TWI Bus State Logic
The bus state logic continuously monitors the activity on the TWI bus when the host is enabled. It continues to
operate in all sleep modes, including Power-Down.
The bus state logic includes Start and Stop condition detectors, collision detection, inactive bus time-out detection,
and a bit counter. These are used to determine the bus state. The software can get the current bus state by reading
the Bus State (BUSSTATE) bit field in the Host Status (TWIn.MSTATUS) register.
The bus state can be Unknown, Idle, Busy or Owner, and it is determined according to the state diagram shown
below.
Figure 25-4. Bus State Diagram
RESET
UNKNOWN
(0b00)
Time-out or Stop Condition
External Start Condition
IDLE
(0b01)
Time-out or Stop Condition
BUSY
(0b11)
Write ADDR to generate
Start Condition
OWNER
(0b10)
Lost Arbitration
External Repeated
Start Condition
Stop Condition
Write ADDR to generate
Repeated Start Condition
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1.
2.
3.
4.
Unknown: The bus state machine is active when the TWI host is enabled. After the TWI host has been
enabled, the bus state is Unknown. The bus state will also be set to Unknown after a system Reset is
performed or after the TWI host is disabled.
Idle: The bus state machine can be forced to enter the Idle state by writing 0x1 to the Bus State (BUSSTATE)
bit field. The bus state logic cannot be forced into any other state. If no state is set by the application
software, the bus state will become Idle when the first Stop condition is detected. If the Inactive Bus Time-Out
(TIMEOUT) bit field from the Host Control A (TWIn.MCTRLA) register is configured to a nonzero value, the
bus state will change to Idle on the occurrence of a time-out. When the bus is Idle, it is ready for a new
transaction.
Busy: If a Start condition, generated externally, is detected when the bus is Idle, the bus state becomes Busy.
The bus state changes back to Idle when a Stop condition is detected or when a time-out, if configured, is set.
Owner: If a Start condition is generated internally when the bus is Idle, the bus state becomes Owner. If the
complete transaction is performed without interference, the host issues a Stop condition, and the bus state
changes back to Idle. If a collision is detected, the arbitration is lost, and the bus state becomes Busy until a
Stop condition is detected.
25.3.2.2.3 Transmitting Address Packets
The host starts performing a bus transaction when the Host Address (TWIn.MADDR) register is written with the client
address and the R/W direction bit. The value of the MADDR register is then copied into the Host Data (TWIn.MDATA)
register. If the bus state is Busy, the TWI host will wait until the bus state becomes Idle before issuing the Start
condition. The TWI will issue a Start condition, and the shift register performs a byte transmit operation on the bus.
Depending on the arbitration and the R/W direction bit, one of four cases (M1 to M4) arises after the transmission of
the address packet.
Figure 25-5. TWI Host Operation
M4
HOST DATA INTERRUPT
P
P
A
Sr
BUSY
P
IDLE
S
ADDRESS
W
OWNER
M3
A
Sr
A
IF
M1
DATA
Sr
A
M4
M4
IF
A
The host provides data
on the bus
Mn
P
P
R
BUSY
BUSY
Interrupt flag raised
Addressed client provides
data on the bus
BUSY
OWNER
M3
A
Sr
A
DATA
IF
M2
Sr
A
Diagram cases
Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’
If a client device responds to the address packet with an ACK, the Write Interrupt Flag (WIF) is set to ‘1’, the
Received Acknowledge (RXACK) flag is set to ‘0’, and the Clock Hold (CLKHOLD) flag is set to ‘1’. The WIF, RXACK
and CLKHOLD flags are located in the Host Status (TWIn.MSTATUS) register.
The clock hold is active at this point, forcing the SCL low. This will stretch the low period of the clock to slow down the
overall clock frequency, forcing delays required to process the data and preventing further activity on the bus.
The software can prepare to:
• Transmit data packets to the client
Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’
If a client device responds to the address packet with an ACK, the RXACK flag is set to ‘0’, and the client can start
sending data to the host without any delays because the client owns the bus at this moment. The clock hold is active
at this point, forcing the SCL low.
The software can prepare to:
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•
Read the received data packet from the client
Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client
If no client device responds to the address packet, the WIF and the RXACK flags will be set to ‘1’. The clock hold is
active at this point, forcing the SCL low.
The missing ACK response can indicate that the I2C client is busy with other tasks, or it is in a sleep mode, and it is
not able to respond.
The software can prepare to take one of the following actions:
• Retransmit the address packet
• Complete the transaction by issuing a Stop condition in the Command (MCMD) bit field from the Host Control B
(TWIn.MCTRLB) register, which is the recommended action
Case M4: Arbitration Lost or Bus Error
If the arbitration is lost, both the WIF and the Arbitration Lost (ARBLOST) flags in the Host Status (TWIn.MSTATUS)
register are set to ‘1’. The SDA is disabled, and the SCL is released. The bus state changes to Busy, and the host is
no longer allowed to perform any operation on the bus until the bus state is changed back to Idle.
A bus error will behave similarly to the arbitration lost condition. In this case, the Bus Error (BUSERR) flag in the Host
Status (TWIn.MSTATUS) register is set to ‘1’, in addition to the WIF and ARBLOST flags.
The software can prepare to:
• Abort the operation and wait until the bus state changes to Idle by reading the Bus State (BUSSTATE) bit field in
the Host Status (TWIn.MSTATUS) register
25.3.2.2.4 Transmitting Data Packets
Assuming the above M1 case, the TWI host can start transmitting data by writing to the Host Data (TWIn.MDATA)
register, which will also clear the Write Interrupt Flag (WIF). During the data transfer, the host is continuously
monitoring the bus for collisions and errors. The WIF flag will be set to ‘1’ after the data packet transfer has been
completed.
If the transmission is successful and the host receives an ACK bit from the client, the Received Acknowledge
(RXACK) flag will be set to ‘0’, meaning that the client is ready to receive new data packets.
The software can prepare to take one of the following actions:
• Transmit a new data packet
• Transmit a new address packet
• Complete the transaction by issuing a Stop condition in the Command (MCMD) bit field from the Host Control B
(TWIn.MCTRLB) register
If the transmission is successful and the host receives a NACK bit from the client, the RXACK flag will be set to ‘1’,
meaning that the client is not able to or does not need to receive more data.
The software can prepare to take one of the following actions:
• Transmit a new address packet
• Complete the transaction by issuing a Stop condition in the Command (MCMD) bit field from the Host Control B
(TWIn.MCTRLB) register
The RXACK status is valid only if the WIF flag is set to ‘1’ and the Arbitration Lost (ARBLOST) and Bus Error
(BUSERR) flags are set to ‘0’.
The transmission can be unsuccessful if a collision is detected. Then, the host will lose the arbitration, the Arbitration
Lost (ARBLOST) flag will be set to ‘1’, and the bus state changes to Busy. An arbitration lost during the sending of
the data packet is treated the same way as the above M4 case.
The WIF, ARBLOST, BUSERR and RXACK flags are all located in the Host Status (TWIn.MSTATUS) register.
25.3.2.2.5 Receiving Data Packets
Assuming the M2 case above, the clock is released for one byte, allowing the client to put one byte of data on the
bus. The host will receive one byte of data from the client, and the Read Interrupt Flag (RIF) will be set to ‘1’ together
with the Clock Hold (CLKHOLD) flag. The action selected by the Acknowledge Action (ACKACT) bit in the Host
Control B (TWIn.MCTRLB) register is automatically sent on the bus when a command is written to the Command
(MCMD) bit field in the TWIn.MCTRLB register.
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The software can prepare to take one of the following actions:
• Respond with an ACK by writing ‘0’ to the ACKACT bit in the TWIn.MCTRLB register and prepare to receive a
new data packet
• Respond with a NACK by writing ‘1’ to the ACKACT bit and then transmit a new address packet
•
Respond with a NACK by writing ‘1’ to the ACKACT bit and then complete the transaction by issuing a Stop
condition in the MCMD bit field from the TWIn.MCTRLB register
A NACK response might not be successfully executed, as the arbitration can be lost during the transmission. If a
collision is detected, the host loses the arbitration, the Arbitration Lost (ARBLOST) flag is set to ‘1’, and the bus state
changes to Busy. The Host Write Interrupt Flag (WIF) is set if the arbitration was lost when sending a NACK or a bus
error occurred during the procedure. An arbitration lost during the sending of the data packet is treated in the same
way as the above M4 case.
The RIF, CLKHOLD, ARBLOST and WIF flags are all located in the Host Status (TWIn.MSTATUS) register.
Note: The RIF and WIF flags are mutually exclusive and cannot be set simultaneously.
25.3.2.3 TWI Client Operation
The TWI client is byte-oriented with optional interrupts after each byte. There are separate interrupt flags for the client
data and address/Stop recognition. Interrupt flags can also be used for polled operation. There are dedicated status
flags for indicating ACK/NACK received, clock hold, collision, bus error, and R/W direction bit.
When an interrupt flag is set to ‘1’, the SCL is forced low. This will give the client time to respond or handle any data
and will, in most cases, require software interaction. The number of interrupts generated is kept to a minimum by
automatic handling of most conditions.
The Permissive Mode Enable (PMEN) bit in the Client Control A (TWIn.SCTRLA) register can be configured to allow
the client to respond to all received addresses.
25.3.2.3.1 Receiving Address Packets
When the TWI is configured as a client, it will wait for a Start condition to be detected. When this happens, the
successive address packet will be received and checked by the address match logic. The client will ACK a correct
address and store the address in the Client Data (TWIn.SDATA) register. If the received address is not a match, the
client will not acknowledge or store the address but wait for a new Start condition.
The Address or Stop Interrupt Flag (APIF) in the Client Status (TWIn.SSTATUS) register is set to ‘1’ when a Start
condition is succeeded by one of the following:
•
•
A valid address match with the address stored in the Address (ADDR[7:1]) bit field in the Client Address
(TWIn.SADDR) register
The General Call Address 0x00 and the Address (ADDR[0]) bit in the Client Address (TWIn.SADDR) register
are set to ‘1’
•
A valid address match with the secondary address stored in the Address Mask (ADDRMASK) bit field and the
Address Mask Enable (ADDREN) bit is set to ‘1’ in the Client Address Mask (TWIn.SADDRMASK) register
•
Any address if the Permissive Mode Enable (PMEN) bit in the Client Control A (TWIn.SCTRLA) register is set to
‘1’
Depending on the Read/Write Direction (DIR) bit in the Client Status (TWIn.SSTATUS) register and the bus condition,
one of four distinct cases (S1 to S4) arises after the reception of the address packet.
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Figure 25-6. TWI Client Operation
CLIENT ADDRESS INTERRUPT
S4
S3
IF
S
A
ADDRESS
R
IF
Interrupt flag raised
Addressed client provides
data on the bus
W
IF
Interrupton STOP
Condition Enabled
IF
P
S3
Sr
S4
S3
Sr
S4
A
S3
Sr
S4
P
S3
A
Sr
S4
A
Sr
S4
A
IF
P
P
S3
P
A
A
The host provides data
on the bus
Sn
CLIENT DATA INTERRUPT
S2
DATA
A
S3
P
DATA
IF
S1
Diagram cases
Case S1: Address Packet Accepted - Direction Bit Set to ‘0’
If an ACK is sent by the client after the address packet is received, and the Read/Write Direction (DIR) bit in the
Client Status (TWIn.SSTATUS) register is set to ‘0’, the host indicates a write operation.
The clock hold is active at this point, forcing the SCL low. This will stretch the low period of the clock to slow down the
overall clock frequency, forcing delays required to process the data and preventing further activity on the bus.
The software can prepare to:
• Read the received data packet from the host
Case S2: Address Packet Accepted - Direction Bit Set to ‘1’
If an ACK is sent by the client after the address packet is received, and the DIR bit is set to ‘1’, the host indicates a
read operation, and the Data Interrupt Flag (DIF) in the Client Status (TWIn.SSTATUS) register will be set to ‘1’.
The clock hold is active at this point, forcing the SCL low.
The software can prepare to:
• Transmit data packets to the host
Case S3: Stop Condition Received
When the Stop condition is received, the Address or Stop (AP) flag will be set to ‘0’, indicating that a Stop condition,
and not an address match, activated the Address or Stop Interrupt Flag (APIF).
The AP and APIF flags are located in the Client Status (TWIn.SSTATUS) register.
The software can prepare to:
• Wait until a new address packet has been addressed to it
Case S4: Collision
If the client is not able to send a high-level data bit or a NACK, the Collision (COLL) bit in the Client Status
(TWIn.SSTATUS) register is set to ‘1’. The client will commence its operation as normal, except no low values will
be shifted out on the SDA. The data and acknowledge output from the client logic will be disabled. The clock hold is
released. A Start or repeated Start condition will be accepted.
The COLL bit is intended for systems where the Address Resolution Protocol (ARP) is employed. A detected collision
in non-ARP situations indicates that there has been a protocol violation and must be treated as a bus error.
25.3.2.3.2 Receiving Data Packets
Assuming the above S1 case, the client must be ready to receive data. When a data packet is received, the
Data Interrupt Flag (DIF) in the Client Status (TWIn.SSTATUS) register is set to ‘1’. The action selected by the
Acknowledge Action (ACKACT) bit in the Client Control B (TWIn.SCTRLB) register is automatically sent on the bus
when a command is written to the Command (SCMD) bit field in the TWIn.SCTRLB register.
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The software can prepare to take one of the following actions:
• Respond with an ACK by writing ‘0’ to the ACKACT bit in the TWIn.SCTRLB register, indicating that the client is
ready to receive more data
• Respond with a NACK by writing ‘1’ to the ACKACT bit, indicating that the client cannot receive any more data
and the host must issue a Stop or repeated Start condition
25.3.2.3.3 Transmitting Data Packets
Assuming the above S2 case, the client can start transmitting data by writing to the Client Data (TWIn.SDATA)
register. When a data packet transmission is completed, the Data Interrupt Flag (DIF) in the Client Status
(TWIn.SSTATUS) register is set to ‘1’.
The software can prepare to take one of the following actions:
• Check if the host responded with an ACK by reading the Received Acknowledge (RXACK) bit from the Client
Status (TWIn.SSTATUS) register, and start transmitting new data packets
• Check if the host responded with a NACK by reading the RXACK bit, and stop transmitting data packets. The
host must send a Stop or repeated Start condition after the NACK.
25.3.3
Additional Features
25.3.3.1 SMBus
If the TWI is used in an SMBus environment, the Inactive Bus Time-Out (TIMEOUT) bit field from the Host Control
A (TWIn.MCTRLA) register must be configured. It is recommended to write to the Host Baud Rate (TWIn.MBAUD)
register before setting the time-out because it is dependent on the baud rate setting.
A frequency of 100 kHz can be used for the SMBus environment. For the Standard mode (Sm) and Fast mode (Fm),
the operating frequency has slew rate limited output, while for the Fast mode Plus (Fm+), it has x10 output drive
strength.
The TWI also allows for an SMBus compatible SDA hold time configured in the SDA Hold Time (SDAHOLD) bit field
from the Control A (TWIn.CTRLA) register.
25.3.3.2 Multi-Host
A host can start a bus transaction only if it has detected that the bus is in the Idle state. As the TWI bus is a multi-host
bus, more devices may try to initiate a transaction at the same time. This results in multiple hosts owning the bus
simultaneously. The TWI solves this problem by using an arbitration scheme where the host loses control of the bus
if it is not able to transmit a high-level data bit on the SDA and the Bus State (BUSSTATE) bit field from the Host
Status (TWIn.MSTATUS) register will be changed to Busy. The hosts that lose the arbitration must wait until the bus
becomes Idle before attempting to reacquire the bus ownership.
Both devices can issue a Start condition, but DEVICE1 loses arbitration when attempting to transmit a high-level (bit
5) while DEVICE2 is transmitting a low-level.
Figure 25-7. TWI Arbitration
DEVICE1 Loses arbitration
DEVICE1_SDA
DEVICE2_SDA
SDA
(wired-AND)
bit 7
bit 6
bit 5
bit 4
SCL
S
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25.3.3.3 Smart Mode
The TWI interface has a Smart mode that simplifies the application code and minimizes the user interaction needed
to adhere to the I2C protocol.
For the TWI host, the Smart mode will automatically send the ACK action as soon as the Host Data (TWIn.MDATA)
register is read. This feature is only active when the Acknowledge Action (ACKACT) bit in the Host Control B
(TWIn.MCTRLB) register is set to ACK. If the ACKACT bit is set to NACK, the TWI host will not generate a NACK
after the MDATA register is read. This feature is enabled when the Smart Mode Enable (SMEN) bit in the Host
Control A (TWIn.MCTRLA) register is set to ‘1’.
For the TWI client, the Smart mode will automatically send the ACK action as soon as the Client Data (TWIn.SDATA)
register is read. The Smart mode will automatically set the Data Interrupt Flag (DIF) to ‘0’ in the Client Status
(TWIn.SSTATUS) register if the TWIn.SDATA register is read or written. This feature is enabled when the Smart
Mode Enable (SMEN) bit in the Client Control A (TWIn.SCTRLA) register is set to ‘1’.
25.3.3.4 Dual Mode
The TWI supports Dual mode operation where the host and the client will operate simultaneously and independently.
In this case, the Control A (TWIn.CTRLA) register will configure the host device, and the Dual Mode Control
(TWIn.DUALCTRL) register will configure the client device. See the 25.3.2.1 Initialization section for more details
about the host configuration.
If used, the following bits must be configured before enabling the TWI Dual mode:
• The SDA Hold Time (SDAHOLD) bit field in the DUALCTRL register
• The FM Plus Enable (FMPEN) bit from the DUALCTRL register
The Dual mode can be enabled by writing a ‘1’ to the Dual Control Enable (ENABLE) bit in the DUALCTRL register.
25.3.3.5 Quick Command Mode
With Quick Command mode, the R/W bit from the address packet denotes the command. This mode is enabled by
writing ‘1’ to the Quick Command Enable (QCEN) bit in the Host Control A (TWIn.MCTRLA) register. There are no
data sent or received.
The Quick Command mode is SMBus specific, where the R/W bit can be used to turn a device function on/off or
to enable/disable a low-power Standby mode. This mode can be enabled to auto-trigger operations and reduce
software complexity.
After the host receives an ACK from the client, either the Read Interrupt Flag (RIF) or Write Interrupt Flag (WIF)
will be set, depending on the value of the R/W bit. When either the RIF or WIF flag is set after issuing a Quick
Command, the TWI will accept a Stop command by writing the Command (MCMD) bit field in the Host Control B
(TWIn.MCTRLB) register.
The RIF and WIF flags, together with the value of the last Received Acknowledge (RXACK) flag, are all located in the
Host Status (TWIn.MSTATUS) register.
Figure 25-8. Quick Command Frame Format
BUSY
P
BUSY
IDLE
S
ADDRESS
R/W
OWNER
A
P
The host provides data
on the bus
Addressed client provides
data on the bus
25.3.3.6 10-bit Address
Regardless of whether the transaction is a read or write, the host must start by sending the 10-bit address with the
R/W direction bit set to ‘0’.
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The client address match logic supports recognition of 7-bit addresses and General Call Address. The Client Address
(TWIn.SADDR) register is used by the client address match logic to determine if a host device has addressed the
TWI client.
The TWI client address match logic only supports recognition of the first byte of a 10-bit address, and the second
byte must be handled in software. The first byte of the 10-bit address will be recognized if the upper five bits of the
Client Address (TWIn.SADDR) register are 0b11110. Thus, the first byte will consist of five indication bits, the two
Most Significant bits (MSb) of the 10-bits address, and the R/W direction bit. The Least Significant Byte (LSB) of the
address that follows from the host will come in the form of a data packet.
Figure 25-9. 10-bit Address Transmission
S
SW
1
1
1
0
1
A9
A8
W
A
A7 A6
A5
A4
A3
A2
A1
A0
A
S
W
Software interaction
The host provides data
on the bus
Addressed client provides
data on the bus
25.3.4
Interrupts
Table 25-1. Available Interrupt Vectors and Sources
Name
Vector Description
Client
TWI Client interrupt
Host
TWI Host interrupt
Conditions
•
DIF: Data Interrupt Flag in TWIn.SSTATUS is set to ‘1’
•
APIF: Address or Stop Interrupt Flag in TWIn.SSTATUS is set to ‘1’
•
RIF: Read Interrupt Flag in TWIn.MSTATUS is set to ‘1’
•
WIF: Write Interrupt Flag in TWIn.MSTATUS is set to ‘1’
When an interrupt condition occurs, the corresponding interrupt flag is set in the Host Status (TWIn.MSTATUS)
register or the Client Status (TWIn.SSTATUS) register.
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed
together into one combined interrupt request to the interrupt controller. The user must read the interrupt flags from the
TWIn.MSTATUS register or the TWIn.SSTATUS register to determine which of the interrupt conditions are present.
25.3.5
Sleep Mode Operation
The bus state logic and the address recognition hardware continue to operate in all sleep modes. If a client device
is in a sleep mode and a Start condition followed by the address of the client is detected, clock stretching is active
during the wake-up period until the main clock is available. The host will stop operation in all sleep modes. When the
Dual mode is active, the device will wake up only when the Start condition is sent on the bus of the client.
25.3.6
Debug Operation
During run-time debugging, the TWI will continue normal operation. Halting the CPU in Debugging mode will halt the
normal operation of the TWI. The TWI can be forced to operate with a halted CPU by writing a ‘1’ to the Debug Run
(DBGRUN) bit in the Debug Control (TWIn.DBGCTRL) register. When the CPU is halted in Debug mode, and the
DBGRUN bit is ‘1’, reading or writing the Host Data (TWIn.MDATA) register or the Client Data (TWIn.SDATA) register
will neither trigger a bus operation nor cause transmit and clear flags. If the TWI is configured to require periodical
service by the CPU through interrupts or similar, improper operation or data loss may result during halted debugging.
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TWI - Two-Wire Interface
25.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
CTRLA
DUALCTRL
DBGCTRL
MCTRLA
MCTRLB
MSTATUS
MBAUD
MADDR
MDATA
SCTRLA
SCTRLB
SSTATUS
SADDR
SDATA
SADDRMASK
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
25.5
7
6
5
4
SDASETUP
RIEN
WIEN
RIF
WIF
DIEN
APIEN
DIF
APIF
QCEN
3
2
SDAHOLD[1:0]
SDAHOLD[1:0]
TIMEOUT[1:0]
FLUSH
ACKACT
CLKHOLD
RXACK
ARBLOST
BUSERR
BAUD[7:0]
ADDR[7:0]
DATA[7:0]
PIEN
PMEN
ACKACT
CLKHOLD
RXACK
COLL
BUSERR
ADDR[7:0]
DATA[7:0]
ADDRMASK[6:0]
1
0
FMPEN
FMPEN
ENABLE
DBGRUN
SMEN
ENABLE
MCMD[1:0]
BUSSTATE[1:0]
SMEN
ENABLE
SCMD[1:0]
DIR
AP
ADDREN
Register Description
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25.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
-
6
Access
Reset
5
4
SDASETUP
R/W
0
3
2
SDAHOLD[1:0]
R/W
R/W
0
0
1
FMPEN
R/W
0
0
Bit 4 – SDASETUP SDA Setup Time
This bit is used in TWI Client mode to select the clock hold time to ensure minimum setup time on the SDA out signal.
By default, there are four clock cycles of setup time on the SDA out signal while reading from the client part of the
TWI module. Writing this bit to ‘1’ will change the setup time to eight clock cycles.
Value
Name
Description
0
4CYC
SDA setup time is four clock cycles
1
8CYC
SDA setup time is eight clock cycles
Bits 3:2 – SDAHOLD[1:0] SDA Hold Time
Writing this bit field selects the SDA hold time for the TWI. See the Electrical Characteristics section for details.
Value
Name
Description
0x0
OFF
Hold time OFF
0x1
50NS
Short hold time
0x2
300NS
Meets the SMBus 2.0 specifications under typical conditions
0x3
500NS
Meets the SMBus 2.0 specifications across all corners
Bit 1 – FMPEN FM Plus Enable
Writing a ‘1’ to this bit selects the 1 MHz bus speed (Fast mode plus, Fm+) for the TWI in default configuration or TWI
Host in Dual mode configuration.
Value
Description
0
Operating in Standard mode or Fast mode
1
Operating in Fast mode plus
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25.5.2
Dual Mode Control Configuration
Name:
Offset:
Reset:
Property:
Bit
7
DUALCTRL
0x01
0x00
-
6
5
Access
Reset
4
3
2
SDAHOLD[1:0]
R/W
R/W
0
0
1
FMPEN
R/W
0
0
ENABLE
R/W
0
Bits 3:2 – SDAHOLD[1:0] SDA Hold Time
These bits select the SDA hold time for the TWI Client.
This bit field is ignored when the dual control is disabled.
Value
Name
Description
0x0
OFF
Hold time OFF
0x1
50NS
Short hold time
0x2
300NS
Meets the SMBus 2.0 specifications under typical conditions
0x3
500NS
Meets the SMBus 2.0 specifications across all corners
Bit 1 – FMPEN FM Plus Enable
This bit selects the 1 MHz bus speed for the TWI Client. This bit is ignored when dual control is disabled.
Bit 0 – ENABLE Dual Control Enable
Writing this bit to ‘1’ enables the TWI dual control.
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TWI - Two-Wire Interface
25.5.3
Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x02
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Refer to the Debug Operation section for details.
Value
Description
0
The TWI is halted in Break Debug mode and ignores events
1
The TWI will continue to run in Break Debug mode when the CPU is halted
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TWI - Two-Wire Interface
25.5.4
Host Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RIEN
R/W
0
MCTRLA
0x03
0x00
-
6
WIEN
R/W
0
5
4
QCEN
R/W
0
3
2
TIMEOUT[1:0]
R/W
R/W
0
0
1
SMEN
R/W
0
0
ENABLE
R/W
0
Bit 7 – RIEN Read Interrupt Enable
A TWI host read interrupt will be generated only if this bit and the Global Interrupt Enable (I) bit in the Status
(CPU.SREG) register are set to ‘1’.
Writing a ‘1’ to this bit enables the interrupt on the Read Interrupt Flag (RIF) in the Host Status (TWIn.MSTATUS)
register. When the host read interrupt occurs, the RIF flag is set to ‘1’.
Bit 6 – WIEN Write Interrupt Enable
A TWI host write interrupt will be generated only if this bit and the Global Interrupt Enable (I) bit in the Status
(CPU.SREG) register are set to ‘1’.
Writing a ‘1’ to this bit enables the interrupt on the Write Interrupt Flag (WIF) in the Host Status (TWIn.MSTATUS)
register. When the host write interrupt occurs, the WIF flag is set to ‘1’.
Bit 4 – QCEN Quick Command Enable
Writing a ‘1’ to this bit enables the Quick Command mode. If the Quick Command mode is enabled and a client
acknowledges the address, the corresponding Read Interrupt Flag (RIF) or Write Interrupt Flag (WIF) will be set
depending on the value of the R/W bit.
The software must issue a Stop command by writing to the Command (MCMD) bit field in the Host Control B
(TWIn.MCTRLB) register.
Bits 3:2 – TIMEOUT[1:0] Inactive Bus Time-Out
Setting this bit field to a nonzero value will enable the inactive bus time-out supervisor. If the bus is inactive for longer
than the TIMEOUT setting, the bus state logic will enter the Idle state.
Value
Name
Description
0x0
DISABLED
Bus time-out disabled - I2C
0x1
50US
50 µs - SMBus (assume the baud rate is set to 100 kHz)
0x2
100US
100 µs (assume the baud rate is set to 100 kHz)
0x3
200US
200 µs (assume the baud rate is set to 100 kHz)
Bit 1 – SMEN Smart Mode Enable
Writing a ‘1’ to this bit enables the Host Smart mode. When the Smart mode is enabled, the existing value in
the Acknowledge Action (ACKACT) bit from the Host Control B (TWIn.MCTRLB) register is sent immediately after
reading the Host Data (TWIn.MDATA) register.
Bit 0 – ENABLE Enable TWI Host
Writing a ‘1’ to this bit enables the TWI as host.
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TWI - Two-Wire Interface
25.5.5
Host Control B
Name:
Offset:
Reset:
Property:
Bit
MCTRLB
0x04
0x00
-
7
6
5
4
Access
Reset
3
FLUSH
R/W
0
2
ACKACT
R/W
0
1
0
MCMD[1:0]
R/W
0
R/W
0
Bit 3 – FLUSH Flush
This bit clears the internal state of the host and the bus states changes to Idle. The TWI will transmit invalid data if
the Host Data (TWIn.MDATA) register is written before the Host Address (TWIn.MADDR) register.
Writing a ‘1’ to this bit generates a strobe for one clock cycle, disabling the host and then re-enabling the host. Writing
a ‘0’ to this bit has no effect.
Bit 2 – ACKACT Acknowledge Action
The ACKACT(1) bit represents the behavior in the Host mode under certain conditions defined by the bus state and
the software interaction. If the Smart Mode Enable (SMEN) bit in the Host Control A (TWIn.MCTRLA) register is set
to ‘1’, the acknowledge action is performed when the Host Data (TWIn.MDATA) register is read, else a command
must be written to the Command (MCDM) bit field in the Host Control B (TWIn.MCTRLB) register.
The acknowledge action is not performed when the Host Data (TWIn.MDATA) register is written since the host is
sending data.
Value
Name
Description
0
ACK
Send ACK
1
NACK
Send NACK
Bits 1:0 – MCMD[1:0] Command
The MCMD(1) bit field is a strobe. This bit field is always read as ‘0’.
Writing to this bit field triggers a host operation, as defined by the table below.
Table 25-2. Command Settings
MCMD[1:0]
Group
Configuration
DIR
Description
0x0
NOACT
X
Reserved
0x1
REPSTART
0x2
RECVTRANS
0x3
STOP
X
Execute Acknowledge Action followed by repeated Start condition
W
Execute Acknowledge Action (no action) followed by a byte write operation(2)
R
Execute Acknowledge Action followed by a byte read operation
X
Execute Acknowledge Action followed by issuing a Stop condition
Notes:
1. The ACKACT bit and the MCMD bit field can be written at the same time.
2. For a host write operation, the TWI will wait for new data to be written to the Host Data (TWIn.MDATA) register.
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TWI - Two-Wire Interface
25.5.6
Host Status
Name:
Offset:
Reset:
Property:
Bit
7
RIF
R/W
0
Access
Reset
MSTATUS
0x05
0x00
-
6
WIF
R/W
0
5
CLKHOLD
R/W
0
4
RXACK
R
0
3
ARBLOST
R/W
0
2
BUSERR
R/W
0
1
0
BUSSTATE[1:0]
R/W
R/W
0
0
Bit 7 – RIF Read Interrupt Flag
This flag is set to ‘1’ when the host byte read operation is completed.
The RIF flag can be used for a host read interrupt. More information can be found in the Read Interrupt Enable
(RIEN) bit from the Host Control A (TWIn.MCTRLA) register.
This flag is automatically cleared when accessing several other TWI registers. The RIF flag can be cleared by
choosing one of the following methods:
1. Writing a ‘1’ to it.
2.
3.
4.
Writing to the Host Address (TWIn.MADDR) register.
Writing/Reading the Host Data (TWIn.MDATA) register.
Writing to the Command (MCMD) bit field from the Host Control B (TWIn.MCTRLB) register.
Bit 6 – WIF Write Interrupt Flag
This flag is set to ‘1’ when a host transmit address or byte write operation is completed, regardless of the occurrence
of a bus error or arbitration lost condition.
The WIF flag can be used for a host write interrupt. More information can be found from the Write Interrupt Enable
(WIEN) bit in the Host Control A (TWIn.MCTRLA) register.
This flag can be cleared by choosing one of the methods described for the RIF flag.
Bit 5 – CLKHOLD Clock Hold
When this bit is read as ‘1’, it indicates that the host is currently holding the SCL low, stretching the TWI clock period.
This bit can be cleared by choosing one of the methods described for the RIF flag.
Bit 4 – RXACK Received Acknowledge
When this flag is read as ‘0’, it indicates that the most recent Acknowledge bit from the client was ACK, and the client
is ready for more data.
When this flag is read as ‘1’, it indicates that the most recent Acknowledge bit from the client was NACK, and the
client is not able to or does not need to receive more data.
Bit 3 – ARBLOST Arbitration Lost
When this bit is read as ‘1’, it indicates that the host has lost arbitration. This can happen in one of the following
cases:
1. While transmitting a high data bit.
2. While transmitting a NACK bit.
3. While issuing a Start condition (S).
4. While issuing a repeated Start (Sr).
This flag can be cleared by choosing one of the methods described for the RIF flag.
Bit 2 – BUSERR Bus Error
The BUSERR flag indicates that an illegal bus operation has occurred. An illegal bus operation is detected if a
protocol violating the Start (S), repeated Start (Sr), or Stop (P) conditions is detected on the TWI bus lines. A Start
condition directly followed by a Stop condition is one example of a protocol violation.
The BUSERR flag can be cleared by choosing one of the following methods:
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TWI - Two-Wire Interface
1.
Writing a ‘1’ to it.
2.
Writing to the Host Address (TWIn.MADDR) register.
The TWI bus error detector is part of the TWI host circuitry. For the bus errors to be detected, the TWI host must
be enabled (ENABLE bit in TWIn.MCTRLA is ‘1’), and the main clock frequency must be at least four times the SCL
frequency.
Bits 1:0 – BUSSTATE[1:0] Bus State
This bit field indicates the current TWI bus state.
Value
Name
Description
0x0
UNKNOWN
Unknown bus state
0x1
IDLE
Idle bus state
0x2
OWNER
This TWI controls the bus
0x3
BUSY
Busy bus state
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TWI - Two-Wire Interface
25.5.7
Host Baud Rate
Name:
Offset:
Reset:
Property:
Bit
7
MBAUD
0x06
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BAUD[7:0] Baud Rate
This bit field is used to derive the SCL high and low time. It must be written while the host is disabled. The host can
be disabled by writing ‘0’ to the Enable TWI Host (ENABLE) bit from the Host Control A (TWIn.MCTRLA) register.
Refer to the Clock Generation section for more information on how to calculate the frequency of the SCL.
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25.5.8
Host Address
Name:
Offset:
Reset:
Property:
Bit
7
MADDR
0x07
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ADDR[7:0] Address
This register contains the address of the external client device. When this bit field is written, the TWI will issue a Start
condition, and the shift register performs a byte transmit operation on the bus depending on the bus state.
This register can be read at any time without interfering with the ongoing bus activity since a read access does not
trigger the host logic to perform any bus protocol related operations.
The host control logic uses the bit 0 of this register as the R/W direction bit.
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25.5.9
Host Data
Name:
Offset:
Reset:
Property:
Bit
7
MDATA
0x08
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Data
This bit field provides direct access to the host’s physical shift register, which is used to shift out data on the bus
(transmit) and to shift in data received from the bus (receive). The direct access implies that the MDATA register
cannot be accessed during byte transmissions.
Reading valid data or writing data to be transmitted can only be successful when the CLKHOLD bit is read as ‘1’ or
when an interrupt occurs.
A write access to the MDATA register will command the host to perform a byte transmit operation on the bus, directly
followed by receiving the Acknowledge bit from the client. This is independent of the Acknowledge Action (ACKACT)
bit from the Host Control B (TWIn.MCTRLB) register. The write operation is performed regardless of winning or losing
arbitration before the Write Interrupt Flag (WIF) is set to ‘1’.
If the Smart Mode Enable (SMEN) bit in the Host Control A (TWIn.MCTRLA) register is set to ‘1’, a read access to
the MDATA register will command the host to perform an acknowledge action. This is dependent on the setting of the
Acknowledge Action (ACKACT) bit from the Host Control B (TWIn.MCTRLB) register.
Notes:
1. The WIF and RIF flags are cleared automatically if the MDATA register is read while ACKACT is set to ‘1’.
2.
3.
The ARBLOST and BUSEER flags are left unchanged.
The WIF, RIF, ARBLOST, and BUSERR flags together with the Clock Hold (CLKHOLD) bit are all located in
the Host Status (TWIn.MSTATUS) register.
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25.5.10 Client Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
DIEN
R/W
0
SCTRLA
0x09
0x00
-
6
APIEN
R/W
0
5
PIEN
R/W
0
4
3
2
PMEN
R/W
0
1
SMEN
R/W
0
0
ENABLE
R/W
0
Bit 7 – DIEN Data Interrupt Enable
Writing this bit to ‘1’ enables an interrupt on the Data Interrupt Flag (DIF) from the Client Status (TWIn.SSTATUS)
register.
A TWI client data interrupt will be generated only if this bit, the DIF flag, and the Global Interrupt Enable (I) bit in the
Status (CPU.SREG) register are all ‘1’.
Bit 6 – APIEN Address or Stop Interrupt Enable
Writing this bit to ‘1’ enables an interrupt on the Address or Stop Interrupt Flag (APIF) from the Client Status
(TWIn.SSTATUS) register.
A TWI client address or stop interrupt will be generated only if this bit, the APIF flag, and the Global Interrupt Enable
(I) bit in the Status (CPU.SREG) register are all ‘1’.
Notes:
1. The client stop interrupt shares the interrupt flag and vector with the client address interrupt.
2. The Stop Interrupt Enable (PIEN) bit in the Client Control A (TWIn.SCTRLA) register must be written to ‘1’ for
the APIF to be set on a Stop condition.
3. When the interrupt occurs, the Address or Stop (AP) bit in the Client Status (TWIn.SSTATUS) register will
determine whether an address match or a Stop condition caused the interrupt.
Bit 5 – PIEN Stop Interrupt Enable
Writing this bit to ‘1’ allows the Address or Stop Interrupt Flag (APIF) in the Client Status (TWIn.SSTATUS) register to
be set when a Stop condition occurs. The main clock frequency must be at least four times the SCL frequency to use
this feature.
Bit 2 – PMEN Permissive Mode Enable
If this bit is written to ‘1’, the client address match logic responds to all received addresses.
If this bit is written to ‘0’, the address match logic uses the Client Address (TWIn.SADDR) register to determine which
address to recognize as the client’s address.
Bit 1 – SMEN Smart Mode Enable
Writing this bit to ‘1’ enables the client Smart mode. When the Smart mode is enabled, issuing a command by
writing to the Command (SCMD) bit field in the Client Control B (TWIn.SCTRLB) register or accessing the Client Data
(TWIn.SDATA) register resets the interrupt, and the operation continues. If the Smart mode is disabled, the client
always waits for a new client command before continuing.
Bit 0 – ENABLE Enable TWI Client
Writing this bit to ‘1’ enables the TWI client.
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TWI - Two-Wire Interface
25.5.11 Client Control B
Name:
Offset:
Reset:
Property:
Bit
SCTRLB
0x0A
0x00
-
7
6
5
4
3
Access
Reset
2
ACKACT
R/W
0
1
0
SCMD[1:0]
R/W
0
R/W
0
Bit 2 – ACKACT Acknowledge Action
The ACKACT(1) bit represents the behavior of the client device under certain conditions defined by the bus protocol
state and the software interaction. If the Smart Mode Enable (SMEN) bit in the Client Control A (TWIn.SCTRLA)
register is set to ‘1’, the acknowledge action is performed when the Client Data (TWIn.SDATA) register is read, else a
command must be written to the Command (SCMD) bit field in the Client Control B (TWIn.SCTRLB) register.
The acknowledge action is not performed when the Client Data (TWIn.SDATA) register is written since the client is
sending data.
Value
Name
Description
0
ACK
Send ACK
1
NACK
Send NACK
Bits 1:0 – SCMD[1:0] Command
The SCMD(1) bit field is a strobe. This bit field is always read as ‘0’.
Writing to this bit field triggers a client operation as defined by the table below.
Table 25-3. Command Settings
Value Name
0x0
0x1
NOACT
—
0x2
COMPTRANS
DIR Description
X
X
W
R
W
0x3
RESPONSE
R
No action
Reserved
Execute Acknowledge Action succeeded by waiting
for any Start (S/Sr) condition
Used to complete a transaction
Wait for any Start (S/Sr) condition
Execute Acknowledge Action succeeded by reception of next byte
Used in response to an address interrupt (APIF): Execute Acknowledge Action
succeeded by client data interrupt.
Used in response to a data interrupt (DIF): Execute a byte read operation followed by
Acknowledge Action.
Note: 1. The ACKACT bit and the SCMD bit field can be written at the same time. The ACKACT will be updated
before the command is triggered.
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TWI - Two-Wire Interface
25.5.12 Client Status
Name:
Offset:
Reset:
Property:
Bit
7
DIF
R/W
0
Access
Reset
SSTATUS
0x0B
0x00
-
6
APIF
R/W
0
5
CLKHOLD
R
0
4
RXACK
R
0
3
COLL
R/W
0
2
BUSERR
R/W
0
1
DIR
R
0
0
AP
R
0
Bit 7 – DIF Data Interrupt Flag
This flag is set to ‘1’ when the client byte transmit or receive operation is completed without any bus errors. This flag
can be set to ‘1’ with an unsuccessful transaction in case of collision detection. More information can be found in the
Collision (COLL) bit description.
The DIF flag can generate a client data interrupt. More information can be found in Data Interrupt Enable (DIEN) bit
from the Client Control A (TWIn.SCTRLA) register.
This flag is automatically cleared when accessing several other TWI registers. The DIF flag can be cleared by
choosing one of the following methods:
1. Writing/Reading the Client Data (TWIn.SDATA) register.
2. Writing to the Command (SCMD) bit field from the Client Control B (TWIn.SCTRLB) register.
Bit 6 – APIF Address or Stop Interrupt Flag
This flag is set to ‘1’ when the client address has been received or by a Stop condition.
The APIF flag can generate a client address or stop interrupt. More information can be found in the Address or Stop
Interrupt Enable (APIEN) bit from the Client Control A (TWIn.SCTRLA) register.
This flag can be cleared by choosing one of the methods described for the DIF flag.
Bit 5 – CLKHOLD Clock Hold
When this bit is read as ‘1’, it indicates that the client is currently holding the SCL low, stretching the TWI clock
period.
This bit is set to ‘1’ when an address or data interrupt occurs. Resetting the corresponding interrupt will indirectly set
this bit to ‘0’.
Bit 4 – RXACK Received Acknowledge
When this flag is read as ‘0’, it indicates that the most recent Acknowledge bit from the host was ACK.
When this flag is read as ‘1’, it indicates that the most recent Acknowledge bit from the host was NACK.
Bit 3 – COLL Collision
When this bit is read as ‘1’, it indicates that the client has not been able to do one of the following:
1.
2.
Transmit high bits on the SDA. The Data Interrupt Flag (DIF) will be set to ‘1’ at the end as a result of the
internal completion of an unsuccessful transaction.
Transmit the NACK bit. The collision occurs because the client address match already took place, and the
APIF flag is set to ‘1’ as a result.
Writing a ‘1’ to this bit will clear the COLL flag. The flag is automatically cleared if any Start condition (S/Sr) is
detected.
Note: The APIF and DIF flags can only generate interrupts whose handlers can be used to check for the collision.
Bit 2 – BUSERR Bus Error
The BUSERR flag indicates that an illegal bus operation has occurred. An illegal bus operation is detected if a
protocol violating the Start (S), repeated Start (Sr), or Stop (P) conditions is detected on the TWI bus lines. A Start
condition directly followed by a Stop condition is one example of a protocol violation.
Writing a ‘1’ to this bit will clear the BUSERR flag.
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TWI - Two-Wire Interface
The TWI bus error detector is part of the TWI Host circuitry. For the bus errors to be detected by the client, the
TWI Host and the TWI Dual mode must both be enabled, and the main clock frequency must be at least four times
the SCL frequency. The TWI Dual mode can be enabled by writing ‘1’ to the ENABLE bit in the TWIn.DUALCTRL
register, and the TWI Host can be enabled by writing ‘1’ to the ENABLE bit in the TWIn.MCTRLA register.
Bit 1 – DIR Read/Write Direction
This bit indicates the current TWI bus direction. The DIR bit reflects the direction bit value from the last address
packet received from a host TWI device.
When this bit is read as ‘1’, it indicates that a host read operation is in progress.
When this bit is read as ‘0’, it indicates that a host write operation is in progress.
Bit 0 – AP Address or Stop
When the TWI client Address or Stop Interrupt Flag (APIF) is set ‘1’, this bit determines whether the interrupt is due
to an address detection or a Stop condition.
Value
Name
Description
0
STOP
A Stop condition generated the interrupt on the APIF flag
1
ADR
Address detection generated the interrupt on the APIF flag
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TWI - Two-Wire Interface
25.5.13 Client Address
Name:
Offset:
Reset:
Property:
Bit
7
SADDR
0x0C
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ADDR[7:0] Address
The Client Address (TWIn.SADDR) register is used by the client address match logic to determine if a host device
has addressed the TWI client. The Address or Stop Interrupt Flag (APIF) and the Address or Stop (AP) bit in the
Client Status (TWIn.SSTATUS) register are set to ‘1’ if an address packet is received.
The upper seven bits (ADDR[7:1]) of the TWIn.SADDR register represent the main client address.
The Least Significant bit (ADDR[0]) of the TWIn.SADDR register is used for the recognition of the General Call
Address (0x00) of the I2C protocol. This feature is enabled when this bit is set to ‘1’.
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TWI - Two-Wire Interface
25.5.14 Client Data
Name:
Offset:
Reset:
Property:
Bit
7
SDATA
0x0D
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Data
This bit field provides access to the client data register.
Reading valid data or writing data to be transmitted can only be achieved when the SCL is held low by the client (i.e.,
when the client CLKHOLD bit is set to ‘1’). It is not necessary to check the Clock Hold (CLKHOLD) bit from the Client
Status (TWIn.SSTATUS) register in software before accessing the SDATA register if the software keeps track of the
present protocol state by using interrupts or observing the interrupt flags.
If the Smart Mode Enable (SMEN) bit in the Client Control A (TWIn.SCTRLA) register is set to ‘1’, a read access
to the SDATA register, when the clock hold is active, auto-triggers bus operations and will command the client to
perform an acknowledge action. This is dependent on the setting of the Acknowledge Action (ACKACT) bit from the
Client Control B (TWIn.SCTRLB) register.
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TWI - Two-Wire Interface
25.5.15 Client Address Mask
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
SADDRMASK
0x0E
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
ADDRMASK[6:0]
R/W
0
3
2
1
R/W
0
R/W
0
R/W
0
0
ADDREN
R/W
0
Bits 7:1 – ADDRMASK[6:0] Address Mask
The ADDRMASK bit field acts as a second address match or an address mask register depending on the ADDREN
bit.
If the ADDREN bit is written to ‘0’, the ADDRMASK bit field can be loaded with a 7-bit Client Address mask. Each
of the bits in the Client Address Mask (TWIn.SADDRMASK) register can mask (disable) the corresponding address
bits in the TWI Client Address (TWIn.SADDR) register. When a bit from the mask is written to ‘1’, the address match
logic ignores the comparison between the incoming address bit and the corresponding bit in the Client Address
(TWIn.SADDR) register. In other words, masked bits will always match, making it possible to recognize the ranges of
addresses.
If the ADDREN bit is written to ‘1’, the Client Address Mask (TWIn.SADDRMASK) register can be loaded with a
second client address in addition to the Client Address (TWIn.SADDR) register. In this mode, the client will have two
unique addresses, one in the Client Address (TWIn.SADDR) register and the other one in the Client Address Mask
(TWIn.SADDRMASK) register.
Bit 0 – ADDREN Address Mask Enable
If this bit is written to ‘0’, the TWIn.SADDRMASK register acts as a mask to the TWIn.SADDR register.
If this bit is written to ‘1’, the client address match logic responds to the two unique addresses in the client
TWIn.SADDR and TWIn.SADDRMASK registers.
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
26.
CRCSCAN - Cyclic Redundancy Check Memory Scan
26.1
Features
•
•
•
•
26.2
CRC-16-CCITT
Check of the Entire Flash Section, Application Code, and/or Boot Section
Selectable NMI Trigger on Failure
User-Configurable Check During Internal Reset Initialization
Overview
A Cyclic Redundancy Check (CRC) takes a data stream of bytes from the NVM (either the entire Flash, only the Boot
section, or both the Boot section and the application code section) and generates a checksum. The CRC peripheral
(CRCSCAN) can be used to detect errors in the program memory.
The last location in the section to check has to contain the correct pre-calculated 16-bit checksum for comparison.
If the checksum calculated by the CRCSCAN and the pre-calculated checksums match, a status bit is set. If they
do not match, the Status register (CRCSCAN.STATUS) will indicate that it failed. The user can choose to let the
CRCSCAN generate a Non-Maskable Interrupt (NMI) if the checksums do not match.
An n-bit CRC applied to a data block of arbitrary length will detect any single alteration (error burst) up to n bits in
length. For longer error bursts a fraction 1-2-n will be detected.
The CRC generator supports CRC-16-CCITT.
Polynomial:
•
CRC-16-CCITT: x16 + x12 + x5 + 1
The CRC reads byte-by-byte the content of the section(s) it is set up to check, starting with byte 0, and generates a
new checksum per byte. The byte is sent through a shift register as depicted below, starting with the Most Significant
bit. If the last bytes in the section contain the correct checksum, the CRC will pass. See 26.3.2.1 Checksum for how
to place the checksum. The initial value of the Checksum register is 0xFFFF.
Figure 26-1. CRC Implementation Description
data
15
x14
x13
x12
x11
x10
x9
x8
x7
x6
x5
x4
x3
x2
x1
x0
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
x
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
26.2.1
Block Diagram
Figure 26-2. Cyclic Redundancy Check Block Diagram
Memory
(Boot, App,
Flash)
CTRLB
CTRLA
Source
Enable,
Reset
BUSY
CRC
calculation
STATUS
CRC OK
CHECKSUM
26.3
Functional Description
26.3.1
Initialization
NMI Req
To enable a CRC in software (or via the debugger):
1. Write the Source (SRC) bit field of the Control B register (CRCSCAN.CTRLB) to select the desired mode and
source settings.
2. Enable the CRCSCAN by writing a ‘1’ to the ENABLE bit in the Control A register (CRCSCAN.CTRLA).
3.
The CRC will start after three cycles. The CPU will continue executing during these three cycles.
The CRCSCAN can be configured to perform a code memory scan before the device leaves Reset. If this check fails,
the CPU is not allowed to start normal code execution. This feature is enabled and controlled by the CRCSRC field in
FUSE.SYSCFG0, see the Fuses chapter for more information.
If this feature is enabled, a successful CRC check will have the following outcome:
• Normal code execution starts
• The ENABLE bit in CRCSCAN.CTRLA will be ‘1’
•
•
The SRC bit field in CRCSCAN.CTRLB will reflect the checked section(s)
The OK flag in CRCSCAN.STATUS will be ‘1’
If this feature is enabled, a non-successful CRC check will have the following outcome:
• Normal code execution does not start, the CPU will hang executing no code
• The ENABLE bit in CRCSCAN.CTRLA will be ‘1’
26.3.2
•
•
The SRC bit field in CRCSCAN.CTRLB will reflect the checked section(s)
The OK flag in CRCSCAN.STATUS will be ‘0’
•
This condition may be observed using the debug interface
Operation
When the CRC is operating in Priority mode, the CRC peripheral has priority access to the Flash and will stall the
CPU until completed.
In Priority mode the CRC fetches a new word (16-bit) on every third main clock cycle, or when the CRC peripheral is
configured to do a scan from start-up.
26.3.2.1 Checksum
The pre-calculated checksum must be present in the last location of the section to be checked. If the BOOT section
is to be checked, the checksum must be saved in the last bytes of the BOOT section, and similarly for APPLICATION
and the entire Flash. Table 26-1 shows explicitly how the checksum must be stored for the different sections. Also,
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
see the CRCSCAN.CTRLB register description for how to configure which section to check and the device fuse
description for how to configure the BOOTEND and APPEND fuses.
Table 26-1. Placement of the Pre-Calculated Checksum in Flash
26.3.3
Section to Check
CHECKSUM[15:8]
CHECKSUM[7:0]
BOOT
FUSE_BOOTEND*256-2
FUSE_BOOTEND*256-1
BOOT and APPLICATION
FUSE_APPEND*256-2
FUSE_APPEND*256-1
Full Flash
FLASHEND-1
FLASHEND
Interrupts
Table 26-2. Available Interrupt Vectors and Sources
Name
Vector Description
Conditions
NMI
Non-Maskable Interrupt
CRC failure
When the interrupt condition occurs the OK flag in the Status (CRCSCAN.STATUS) register is cleared to ‘0’.
A Non-Maskable Interrupt (NMI) is enabled by writing a ‘1’ to the respective Enable (NMIEN) bit in the Control A
(CRCSCAN.CTRLA) register, but can only be disabled with a System Reset. An NMI is generated when the OK
flag in the CRCSCAN.STATUS register is cleared, and the NMIEN bit is ‘1’. The NMI request remains active until a
System Reset and cannot be disabled.
An NMI can be triggered even if interrupts are not globally enabled.
26.3.4
Sleep Mode Operation
CRCSCAN is halted in all Sleep modes. In all CPU Sleep modes, the CRCSCAN peripheral is halted and will resume
operation when the CPU wakes up.
The CRCSCAN starts operation three cycles after writing the EN bit in CRCSCAN.CTRLA. During these three cycles,
it is possible to enter Sleep mode. In this case:
1. The CRCSCAN will not start until the CPU is woken up.
2. Any interrupt handler will execute after CRCSCAN has finished.
26.3.5
Debug Operation
Whenever the debugger reads or writes a peripheral or memory location, the CRCSCAN will be disabled.
If the CRCSCAN is busy when the debugger accesses the device, the CRCSCAN will restart the ongoing operation
when the debugger accesses an internal register or when the debugger disconnects.
The BUSY bit in the Status (CRCSCAN.STATUS) register will read ‘1’ if the CRCSCAN was busy when the debugger
caused it to disable, but it will not actively check any section as long as the debugger keeps it disabled. There are
synchronized CRC status bits in the debugger's internal register space, which can be read by the debugger without
disabling the CRCSCAN. Reading the debugger's internal CRC status bits will make sure that the CRCSCAN is
enabled.
It is possible to write the CRCSCAN.STATUS register directly from the debugger:
• BUSY bit in CRCSCAN.STATUS:
– Writing the BUSY bit to ‘0’ will stop the ongoing CRC operation (so that the CRCSCAN does not restart its
operation when the debugger allows it).
– Writing the BUSY bit to ‘1’ will make the CRC start a single check with the settings in the Control B
(CRCSCAN.CTRLB) register, but not until the debugger allows it.
•
As long as the BUSY bit in CRCSCAN.STATUS is ‘1’, CRCSCAN.CTRLB and the Non-Maskable Interrupt
Enable (NMIEN) bit in the Control A (CRCSCAN.CTRLA) register cannot be altered.
OK bit in CRCSCAN.STATUS:
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
– Writing the OK bit to ‘0’ can trigger a Non-Maskable Interrupt (NMI) if the NMIEN bit in CRCSCAN.CTRLA
is ‘1’. If an NMI has been triggered, no writes to the CRCSCAN are allowed.
– Writing the OK bit to ‘1’ will make the OK bit read as ‘1’ when the BUSY bit in CRCSCAN.STATUS is ‘0’.
Writes to CRCSCAN.CTRLA and CRCSCAN.CTRLB from the debugger are treated in the same way as writes from
the CPU.
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
26.4
Register Summary - CRCSCAN
Offset
Name
Bit Pos.
7
0x00
0x01
0x02
CTRLA
CTRLB
STATUS
7:0
7:0
7:0
RESET
26.5
6
5
4
MODE[1:0]
3
2
1
0
NMIEN
ENABLE
SRC[1:0]
OK
BUSY
Register Description
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
26.5.1
Control A
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x00
-
If an NMI has been triggered this register is not writable.
Bit
Access
Reset
7
RESET
R/W
0
6
5
4
3
2
1
NMIEN
R/W
0
0
ENABLE
R/W
0
Bit 7 – RESET Reset CRCSCAN
Writing this bit to ‘1’ resets the CRCSCAN peripheral. The CRCSCAN Control registers and Status register
(CRCSCAN.CTRLA, CRCSCAN.CTRLB, CRCSCAN.STATUS) will be cleared one clock cycle after the RESET bit is
written to ‘1’.
If NMIEN is ‘0’, this bit is writable both when the CRCSCAN is busy (the BUSY bit in CRCSCAN.STATUS is ‘1’) and
not busy (the BUSY bit is ‘0’), and will take effect immediately.
If NMIEN is ‘1’, this bit is only writable when the CRCSCAN is not busy (the BUSY bit in CRCSCAN.STATUS is ‘0’).
The RESET bit is a strobe bit.
Bit 1 – NMIEN Enable NMI Trigger
When this bit is written to ‘1’, any CRC failure will trigger an NMI.
This bit can only be cleared by a system Reset - it is not cleared by a write to the RESET bit.
This bit can only be written to ‘1’ when the CRCSCAN is not busy (the BUSY bit in CRCSCAN.STATUS is ‘0’).
Bit 0 – ENABLE Enable CRCSCAN
Writing this bit to ‘1’ enables the CRCSCAN peripheral with the current settings. It will stay ‘1’ even after a CRC
check has completed, but writing it to ‘1’ again will start a new check.
Writing the bit to ‘0’ has no effect
The CRCSCAN can be configured to run a scan during the MCU start-up sequence to verify the Flash sections
before letting the CPU start normal code execution (see the 26.3.1 Initialization section). If this feature is enabled,
the ENABLE bit will read as ‘1’ when normal code execution starts.
To see whether the CRCSCAN peripheral is busy with an ongoing check, poll the BUSY bit in the Status register
(CRCSCAN.STATUS).
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
26.5.2
Control B
Name:
Offset:
Reset:
Property:
CTRLB
0x01
0x00
-
The CRCSCAN.CTRLB register contains the mode and source settings for the CRC. It is not writable when the CRC
is busy, or when an NMI has been triggered.
Bit
7
6
5
4
3
2
1
0
MODE[1:0]
Access
Reset
R/W
0
SRC[1:0]
R/W
0
R/W
0
R/W
0
Bits 5:4 – MODE[1:0] CRC Flash Access Mode
The CRC can be enabled during internal Reset initialization to verify Flash sections before letting the CPU start
(see the device data sheet fuse description). If the CRC is enabled during internal Reset initialization, the MODE bit
field will read out non-zero when normal code execution starts. To ensure proper operation of the CRC under code
execution, write the MODE bit to 0x0 again.
Value
Name
Description
0x0
PRIORITY The CRC module runs a single check with priority to Flash. The CPU is halted until the
CRC completes.
other
Reserved
Bits 1:0 – SRC[1:0] CRC Source
The SRC bit field selects which section of the Flash the CRC module will check. To set up section sizes, refer to the
fuse description.
The CRC can be enabled during internal Reset initialization to verify Flash sections before letting the CPU start (see
the Fuses chapter). If the CRC is enabled during internal Reset initialization, the SRC bit field will read out as FLASH,
BOOTAPP, or BOOT when normal code execution starts (depending on the configuration).
Value
Name
Description
0x0
FLASH
The CRC is performed on the entire Flash (boot, application code, and application data
sections).
0x1
BOOTAPP The CRC is performed on the boot and application code sections of Flash.
0x2
BOOT
The CRC is performed on the boot section of Flash.
0x3
Reserved.
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CRCSCAN - Cyclic Redundancy Check Memory Sca...
26.5.3
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x02
0x02
-
6
5
4
3
Access
Reset
2
1
OK
R
1
0
BUSY
R
0
Bit 1 – OK CRC OK
When this bit is read as ‘1’, the previous CRC completed successfully. The bit is set to ‘1’ by default before a CRC
scan is run. The bit is not valid unless BUSY is ‘0’.
Bit 0 – BUSY CRC Busy
When this bit is read as ‘1’, the CRCSCAN is busy. As long as the module is busy, the access to the control registers
is limited.
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CCL - Configurable Custom Logic
27.
CCL - Configurable Custom Logic
27.1
Features
•
•
•
•
•
•
•
•
•
27.2
Glue Logic for General Purpose PCB Design
4 Programmable Look-Up Tables (LUTs)
Combinatorial Logic Functions: Any Logic Expression which is a Function of up to Three Inputs.
Sequencer Logic Functions:
– Gated D flip-flop
– JK flip-flop
– Gated D latch
– RS latch
Flexible LUT Input Selection:
– I/Os
– Events
– Subsequent LUT output
– Internal peripherals such as:
• Analog comparator
• Timers/Counters
• USART
• SPI
Clocked by a System Clock or other Peripherals
Output can be Connected to I/O Pins or an Event System
Optional Synchronizer, Filter, or Edge Detector Available on Each LUT Output
Optional Interrupt Generation from Each LUT Output:
– Rising edge
– Falling edge
– Both edges
Overview
The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device
pins, to events, or to other internal peripherals. The CCL can serve as ‘glue logic’ between the device peripherals
and external devices. The CCL can eliminate the need for external logic components, and can also help the designer
to overcome real-time constraints by combining Core Independent Peripherals (CIPs) to handle the most time-critical
parts of the application independent of the CPU.
The CCL peripheral provides a number of Look-up Tables (LUTs). Each LUT consists of three inputs, a truth table, a
synchronizer/filter, and an edge detector. Each LUT can generate an output as a user programmable logic expression
with three inputs. The output is generated from the inputs using the combinatorial logic and can be filtered to remove
spikes. The CCL can be configured to generate an interrupt request on changes in the LUT outputs.
Neighboring LUTs can be combined to perform specific operations. A sequencer can be used for generating complex
waveforms.
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CCL - Configurable Custom Logic
27.2.1
Block Diagram
Figure 27-1. Configurable Custom Logic
Even LUT n
INSEL
Internal
Events
I/O
Peripherals
FILTSEL
LUTn-TRUTHSEL[2:0]
Filter/
Synch
TRUTH
CLKSRC
Edge
Detector
LUTn-OUT
CLK_LUTn
Clock Sources
LUTn-TRUTHSEL[2]
Sequencer
Odd LUT n+1
INSEL
Internal
Events
I/O
Peripherals
FILTSEL
LUTn+1-TRUTHSEL[2:0]
Filter/
Synch
TRUTH
CLKSRC
SEQSEL
EDGEDET
EDGEDET
LUTn+1-OUT
Edge
Detector
CLK_LUTn+1
Clock Sources
LUTn+1-TRUTHSEL[2]
Table 27-2. Sequencer and LUT Connection
27.2.2
Sequencer
Even and Odd LUT
SEQ0
LUT0 and LUT1
SEQ1
LUT2 and LUT3
Signal Description
Name
Type
Description
LUTn-OUT
Digital output
Output from the look-up table
LUTn-IN[2:0]
Digital input
Input to the look-up table. LUTn-IN[2] can serve as CLK_LUTn.
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped to several pins.
27.2.2.1 CCL Input Selection MUX
The following peripherals outputs are available as inputs into the CCL LUT.
Value
Input Source
0x00
MASK
None
0x01
FEEDBACK
LUTn
0x02
LINK
0x03
EVENTA
Event input source A
0x04
EVENTB
Event input source B
0x05
IO
0x06
AC
0x07
-
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INSEL0
INSEL1
INSEL2
LUT(n+1)
IN0
IN1
IN2
AC0 OUT
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CCL - Configurable Custom Logic
...........continued
Value
Input Source
0x08
USART
0x09
SPI
0x0A
TCA0
0x0B
-
0x0C
TCB
Other
-
INSEL0
INSEL1
INSEL2
USART0 TXD
USART1 TXD
USART2 TXD
SPI0 MOSI
SPI0 MOSI
SPI0 SCK
WO0
WO1
WO2
TCB0 WO
TCB1 WO
TCB2 WO
Notes:
• SPI connections to the CCL work only in Host SPI mode
• USART connections to the CCL work only in asynchronous/synchronous USART Host mode
27.3
Functional Description
27.3.1
Operation
27.3.1.1 Enable-Protected Configuration
The configuration of the LUTs and sequencers is enable-protected, meaning that they can only be configured when
the corresponding even LUT is disabled (ENABLE=‘0’ in the LUT n Control A (CCL.LUTnCTRLA) register). This is a
mechanism to suppress the undesired output from the CCL under (re-)configuration.
The following bits and registers are enable-protected:
•
•
Sequencer Selection (SEQSEL) in the Sequencer Control n (CCL.SEQCTRLn) register
LUT n Control x (CCL.LUTnCTRLx) registers, except the ENABLE bit in CCL.LUTnCTRLA
The enable-protected bits in the CCL.LUTnCTRLx registers can be written at the same time as ENABLE in
CCL.LUTnCTRLA is written to ‘1’, but not at the same time as ENABLE is written to ‘0’.
The enable protection is denoted by the enable-protected property in the register description.
27.3.1.2 Enabling, Disabling, and Resetting
The CCL is enabled by writing a ‘1’ to the ENABLE bit in the Control A (CCL.CTRLA) register. The CCL is disabled
by writing a ‘0’ to that ENABLE bit.
Each LUT is enabled by writing a ‘1’ to the LUT Enable (ENABLE) bit in the LUT n Control A (CCL.LUTnCTRLA)
register. Each LUT is disabled by writing a ‘0’ to the ENABLE bit in CCL.LUTnCTRLA.
27.3.1.3 Truth Table Logic
The truth table in each LUT unit can generate a combinational logic output as a function of up to three inputs
(LUTn-TRUTHSEL[2:0]). It is possible to realize any 3-input boolean logic function using one LUT.
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CCL - Configurable Custom Logic
Figure 27-2. Truth Table Output Value Selection of a LUT
TRUTHn[0]
TRUTHn[1]
TRUTHn[2]
TRUTHn[3]
TRUTHn[4]
TRUTHn[5]
TRUTHn[6]
TRUTHn[7]
OUT
LUTn-TRUTHSEL[2:0]
The truth table inputs (LUTn-TRUTHSEL[2:0]) are configured by writing the Input Source Selection bit fields in the
LUT Control registers:
• INSEL0 in CCL.LUTnCTRLB
• INSEL1 in CCL.LUTnCTRLB
• INSEL2 in CCL.LUTnCTRLC
Each combination of the input bits (LUTn-TRUTHSEL[2:0]) corresponds to one bit in the CCL.TRUTHn register, as
shown in the table below:
Table 27-3. Truth Table of a LUT
LUTn-TRUTHSEL[2]
LUTn-TRUTHSEL[1]
LUTn-TRUTHSEL[0]
OUT
0
0
0
TRUTHn[0]
0
0
1
TRUTHn[1]
0
1
0
TRUTHn[2]
0
1
1
TRUTHn[3]
1
0
0
TRUTHn[4]
1
0
1
TRUTHn[5]
1
1
0
TRUTHn[6]
1
1
1
TRUTHn[7]
Important: Consider the unused inputs turned off (tied low) when logic functions are created.
Example 27-1. LUT Output for CCL.TRUTHn = 0x42
If CCL.TRUTHn is configured to 0x42, the LUT output will be 1 when the inputs are 'b001 or
'b110 and 0 for any other combination of inputs.
27.3.1.4 Truth Table Inputs Selection
Input Overview
The inputs can be individually:
•
•
OFF
Driven by peripherals
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•
•
•
Driven by internal events from the Event System
Driven by I/O pin inputs
Driven by other LUTs
Internal Feedback Inputs (FEEDBACK)
The output from a sequencer can be used as an input source for the two LUTs it is connected to.
Figure 27-3. Feedback Input Selection
Even LUT
Sequencer
Odd LUT
When selected (INSELy=FEEDBACK in LUTnCTRLx), the sequencer (SEQ) output is used as input for the
corresponding LUTs.
Linked LUT (LINK)
When selecting the LINK input option, the next LUT’s direct output is used as LUT input. In general, LUT[n+1] is
linked to the input of LUT[n]. LUT0 is linked to the input of the last LUT.
Example 27-2. Linking all LUTs on a Device with Four LUTs
•
•
•
•
LUT1 is the input for LUT0
LUT2 is the input for LUT1
LUT3 is the input for LUT2
LUT0 is the input for LUT3 (wrap-around)
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Figure 27-4. Linked LUT Input Selection
LUT0
SEQ0
LUT1
LUT2
SEQ1
LUT3
Event Input Selection (EVENTx)
Events from the Event System can be used as inputs to the LUTs by writing to the INSELn bit groups in the LUT n
Control B and C registers.
I/O Pin Inputs (IO)
When selecting the IO option, the LUT input will be connected to its corresponding I/O pin. Refer to the I/O
Multiplexing section in the data sheet for more details about where the LUTn-INy pins are located.
Peripherals
The different peripherals on the three input lines of each LUT are selected by writing to the Input Select (INSEL) bits
in the LUT Control (LUTnCTRLB and LUTnCTRLC) registers.
27.3.1.5 Filter
By default, the LUT output is a combinational function of the LUT inputs. This may cause some short glitches when
the inputs change the value. These glitches can be removed by clocking through filters if demanded by application
needs.
The Filter Selection (FILTSEL) bits in the LUT n Control A (CCL.LUTnCTRLA) registers define the digital filter
options.
When FILTSEL=SYNCH, the output is synchronized with CLK_LUTn. The output will be delayed by two positive
CLK_LUTn edges.
When FILTSEL=FILTER, only the input that is persistent for more than two positive CLK_LUTn edges will pass
through the gated flip-flop to the output. The output will be delayed by four positive CLK_LUTn edges.
One clock cycle later, after the corresponding LUT is disabled, all internal filter logic is cleared.
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Figure 27-5. Filter
FILTSEL
DISABLE
Input
SYNCH
OUT
Q
D
R
Q
D
R
Q
D
R
D
EN
Q
FILTER
R
CLK_LUTn
CLR
27.3.1.6 Edge Detector
The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a falling edge,
the TRUTH table can be programmed to provide an inverted output.
The edge detector is enabled by writing ‘1’ to the Edge Detection (EDGEDET) bit in the LUTn Control A
(CCL.LUTnCTRLA) register. To avoid unpredictable behavior, a valid filter option must be enabled.
The edge detection is disabled by writing a ‘0’ to EDGEDET in CCL.LUTnCTRLA. After disabling a LUT, the
corresponding internal edge detector logic is cleared one clock cycle later.
Figure 27-6. Edge Detector
EDGEDET
CLK_LUTn
27.3.1.7 Sequencer Logic
Each LUT pair can be connected to a sequencer. The sequencer can function as either D flip-flop, JK flip-flop,
gated D latch, or RS latch. The function is selected by writing the Sequencer Selection (SEQSEL) bit group in the
Sequencer Control (CCL.SEQCTRLn) register.
The sequencer receives its input from either the LUT, filter or edge detector, depending on the configuration.
A sequencer is clocked by the same clock as the corresponding even LUT. The clock source is selected by the Clock
Source (CLKSRC) bit group in the LUT n Control A (CCL.LUTnCTRLA) register.
The flip-flop output (OUT) is refreshed on the rising edge of the clock. When the even LUT is disabled, the latch is
cleared asynchronously. The flip-flop Reset signal (R) is kept enabled for one clock cycle.
Gated D Flip-Flop (DFF)
The D input is driven by the even LUT output, and the G input is driven by the odd LUT output.
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Figure 27-7. D Flip-Flop
Even LUT
CLK_LUTn
Odd LUT
Table 27-4. DFF Characteristics
R
G
D
OUT
1
X
X
Clear
0
1
1
Set
0
1
0
Clear
0
0
X
Hold state (no change)
JK Flip-Flop (JK)
The J input is driven by the even LUT output, and the K input is driven by the odd LUT output.
Figure 27-8. JK Flip-Flop
Even LUT
CLK_LUTn
Odd LUT
Table 27-5. JK Characteristics
R
J
K
OUT
1
X
X
Clear
0
0
0
Hold state (no change)
0
0
1
Clear
0
1
0
Set
0
1
1
Toggle
Gated D Latch (DLATCH)
The D input is driven by the even LUT output, and the G input is driven by the odd LUT output.
Figure 27-9. D Latch
Even LUT
D
Odd LUT
G
Q
OUT
Table 27-6. D Latch Characteristics
G
D
OUT
0
X
Hold state (no change)
1
0
Clear
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...........continued
G
D
OUT
1
1
Set
RS Latch (RS)
The S input is driven by the even LUT output, and the R input is driven by the odd LUT output.
Figure 27-10. RS Latch
Even LUT
S
Odd LUT
R
Q
OUT
Table 27-7. RS Latch Characteristics
S
R
OUT
0
0
Hold state (no change)
0
1
Clear
1
0
Set
1
1
Forbidden state
27.3.1.8 Clock Source Settings
The filter, edge detector, and sequencer are, by default, clocked by the peripheral clock (CLK_PER). It is also
possible to use other clock inputs (CLK_LUTn) to clock these blocks. This is configured by writing the Clock Source
(CLKSRC) bits in the LUT Control A register.
Figure 27-11. Clock Source Settings
Edge
detector
CLK_PER
IN[2]
OSC20M
OSCULP32K
OSCULP1K
Filter
Sequential
logic
CLKSRC
LUTn
When the Clock Source (CLKSRC) bit is written to 0x1, LUTn-TRUTHSEL[2] is used to clock the corresponding filter
and edge detector (CLK_LUTn). The sequencer is clocked by the CLK_LUTn of the even LUT in the pair. When
CLKSRC is written to 0x1, LUTn-TRUTHSEL[2] is treated as OFF (low) in the TRUTH table.
The CCL peripheral must be disabled while changing the clock source to avoid undefined outputs from the peripheral.
27.3.2
Interrupts
Table 27-8. Available Interrupt Vectors and Sources
Name Vector Description Conditions
CCL
CCL interrupt
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CCL.INTCTRLn register
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When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed
together into one combined interrupt request to the interrupt controller. The user must read the peripheral’s
INTFLAGS register to determine which of the interrupt conditions are present.
27.3.3
Events
The CCL can generate the events shown in the table below.
Table 27-9. Event Generators in the CCL
Generator Name
Description
Event Type Generating Clock Domain Length of Event
Peripheral Event
CCL
LUTn
LUT output level Level
Asynchronous
Depends on the CCL
configuration
The CCL has the event users below for detecting and acting upon input events.
Table 27-10. Event Users in the CCL
User Name
Peripheral
Input
CCL
LUTnx
Description
Input Detection
Async/Sync
LUTn input x or clock signal
No detection
Async
The event signals are passed directly to the LUTs without synchronization or input detection logic.
Two event users are available for each LUT. They can be selected as LUTn inputs by writing to the INSELn bit groups
in the LUT n Control B and Control C (CCL.LUTnCTRLB or LUTnCTRLC) registers.
Refer to the Event System (EVSYS) section for more details regarding the event types and the EVSYS configuration.
27.3.4
Sleep Mode Operation
Writing the Run In Standby (RUNSTDBY) bit in the Control A (CCL.CTRLA) register to ‘1’ will allow the selected
clock source to be enabled in Standby sleep mode.
If RUNSTDBY is ‘0’, the peripheral clock will be disabled in Standby sleep mode. If the filter, edge detector, and/or
sequencer are enabled, the LUT output will be forced to ‘0’ in Standby sleep mode. In Idle sleep mode, the
TRUTH table decoder will continue the operation, and the LUT output will be refreshed accordingly, regardless of the
RUNSTDBY bit.
If the Clock Source (CLKSRC) bit in the LUT n Control A (CCL.LUTnCTRLA) register is written to ‘1’, the LUTnTRUTHSEL[2] will always clock the filter, edge detector, and sequencer. The availability of the LUTn-TRUTHSEL[2]
clock in sleep modes will depend on the sleep settings of the peripheral used.
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27.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
...
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
CTRLA
SEQCTRL0
SEQCTRL1
7:0
7:0
7:0
27.5
7
6
5
4
3
2
1
RUNSTDBY
0
ENABLE
SEQSEL0[3:0]
SEQSEL1[3:0]
Reserved
INTCTRL0
Reserved
INTFLAGS
LUT0CTRLA
LUT0CTRLB
LUT0CTRLC
TRUTH0
LUT1CTRLA
LUT1CTRLB
LUT1CTRLC
TRUTH1
LUT2CTRLA
LUT2CTRLB
LUT2CTRLC
TRUTH2
LUT3CTRLA
LUT3CTRLB
LUT3CTRLC
TRUTH3
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
INTMODE3[1:0]
INTMODE2[1:0]
INTMODE1[1:0]
INT3
EDGEDET
OUTEN
INSEL1[3:0]
FILTSEL[1:0]
EDGEDET
OUTEN
INSEL1[3:0]
FILTSEL[1:0]
EDGEDET
OUTEN
INSEL1[3:0]
FILTSEL[1:0]
EDGEDET
OUTEN
INSEL1[3:0]
FILTSEL[1:0]
INTMODE0[1:0]
INT2
INT1
CLKSRC[2:0]
INSEL0[3:0]
INSEL2[3:0]
INT0
ENABLE
CLKSRC[2:0]
INSEL0[3:0]
INSEL2[3:0]
ENABLE
CLKSRC[2:0]
INSEL0[3:0]
INSEL2[3:0]
ENABLE
CLKSRC[2:0]
INSEL0[3:0]
INSEL2[3:0]
ENABLE
TRUTH0[7:0]
TRUTH1[7:0]
TRUTH2[7:0]
TRUTH3[7:0]
Register Description
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27.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
-
6
RUNSTDBY
R/W
0
5
4
3
2
1
0
ENABLE
R/W
0
Bit 6 – RUNSTDBY Run in Standby
Writing this bit to ‘1’ will enable the peripheral to run in Standby sleep mode.
Value
Description
0
The CCL will not run in Standby sleep mode
1
The CCL will run in Standby sleep mode
Bit 0 – ENABLE Enable
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
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27.5.2
Sequencer Control 0
Name:
Offset:
Reset:
Property:
Bit
7
SEQCTRL0
0x01
0x00
Enable-Protected
6
Access
Reset
5
4
3
R/W
0
2
1
SEQSEL0[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – SEQSEL0[3:0] Sequencer Selection
This bit group selects the sequencer configuration for LUT0 and LUT1.
Value
Name
Description
0x0
DISABLE
The sequencer is disabled
0x1
DFF
D flip-flop
0x2
JK
JK flip-flop
0x3
LATCH
D latch
0x4
RS
RS latch
Other
Reserved
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27.5.3
Sequencer Control 1
Name:
Offset:
Reset:
Property:
Bit
7
SEQCTRL1
0x02
0x00
Enable-Protected
6
Access
Reset
5
4
3
R/W
0
2
1
SEQSEL1[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – SEQSEL1[3:0] Sequencer Selection
This bit group selects the sequencer configuration for LUT2 and LUT3.
Value
Name
Description
0x0
DISABLE
The sequencer is disabled
0x1
DFF
D flip-flop
0x2
JK
JK flip-flop
0x3
LATCH
D latch
0x4
RS
RS latch
Other
Reserved
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27.5.4
Interrupt Control 0
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
INTCTRL0
0x05
0x00
-
7
6
INTMODE3[1:0]
R/W
R/W
0
0
5
4
INTMODE2[1:0]
R/W
R/W
0
0
3
2
INTMODE1[1:0]
R/W
R/W
0
0
1
0
INTMODE0[1:0]
R/W
R/W
0
0
Bits 0:1, 2:3, 4:5, 6:7 – INTMODE
The bits in INTMODEn select the interrupt sense configuration for LUTn-OUT.
Value
Name
Description
0x0
INTDISABLE
Interrupt disabled
0x1
RISING
Sense rising edge
0x2
FALLING
Sense falling edge
0x3
BOTH
Sense both edges
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27.5.5
Interrupt Flag
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x07
0x00
-
6
Access
Reset
5
4
3
INT3
R/W
0
2
INT2
R/W
0
1
INT1
R/W
0
0
INT0
R/W
0
Bits 0, 1, 2, 3 – INT Interrupt Flag
The INTn flag is set when the LUTn output change matches the Interrupt Sense mode as defined in CCL.INTCTRLn.
Writing a ‘1’ to this flag’s bit location will clear the flag.
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27.5.6
LUT n Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
EDGEDET
R/W
0
LUTnCTRLA
0x08 + n*0x04 [n=0..3]
0x00
Enable-Protected
6
OUTEN
R/W
0
5
4
FILTSEL[1:0]
R/W
R/W
0
0
3
R/W
0
2
CLKSRC[2:0]
R/W
0
1
R/W
0
0
ENABLE
R/W
0
Bit 7 – EDGEDET Edge Detection
Value
Description
0
Edge detector is disabled
1
Edge detector is enabled
Bit 6 – OUTEN Output Enable
This bit enables the LUT output to the LUTn OUT pin. When written to ‘1’, the pin configuration of the PORT
I/O-Controller is overridden.
Value
Description
0
Output to pin disabled
1
Output to pin enabled
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options.
Value
Name
0x0
DISABLE
0x1
SYNCH
0x2
FILTER
0x3
-
Description
Filter disabled
Synchronizer enabled
Filter enabled
Reserved
Bits 3:1 – CLKSRC[2:0] Clock Source Selection
This bit selects between various clock sources to be used as the clock (CLK_LUTn) for a LUT.
The CLK_LUTn of the even LUT is used for clocking the sequencer of a LUT pair.
Value
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
CLKPER
IN2
OSC20M
OSCULP32K
OSCULP1K
-
CLK_PER is clocking the LUT
LUT input 2 is clocking the LUT
Reserved
Reserved
16/20 MHz oscillator before prescaler is clocking the LUT
32.768 kHz internal oscillator is clocking the LUT
1.024 kHz (OSCKULP32K after DIV32) is clocking the LUT
Reserved
Bit 0 – ENABLE LUT Enable
Value
Description
0
The LUT is disabled
1
The LUT is enabled
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27.5.7
LUT n Control B
Name:
Offset:
Reset:
Property:
LUTnCTRLB
0x09 + n*0x04 [n=0..3]
0x00
Enable-Protected
Notes:
1. SPI connections to the CCL work in Host SPI mode only.
2. USART connections to the CCL work only when the USART is in one of the following modes:
– Asynchronous USART
– Synchronous USART host
Bit
Access
Reset
7
6
5
INSEL1[3:0]
R/W
R/W
0
0
R/W
0
4
3
R/W
0
R/W
0
2
1
INSEL0[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 7:4 – INSEL1[3:0] LUT n Input 1 Source Selection
These bits select the source for input 1 of LUT n.
Value
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
Other
MASK
FEEDBACK
LINK
EVENTA
EVENTB
IO
AC0
USART1
SPI0
TCA0
TCB1
-
None (masked)
Feedback input
Output from LUTn+1
Event input source A
Event input source B
I/O-pin LUTn-IN1
AC0 out
Reserved
USART1 TXD
SPI0 MOSI
TCA0 WO1
Reserved
TCB1 WO
Reserved
Bits 3:0 – INSEL0[3:0] LUT n Input 0 Source Selection
These bits select the source for input 0 of LUT n.
Value
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
Other
MASK
FEEDBACK
LINK
EVENTA
EVENTB
IO
AC0
USART0
SPI0
TCA0
TCB0
-
None (masked)
Feedback input
Output from LUTn+1
Event input source A
Event input source B
I/O-pin LUTn-IN0
AC0 out
Reserved
USART0 TXD
SPI0 MOSI
TCA0 WO0
Reserved
TCB0 WO
Reserved
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27.5.8
LUT n Control C
Name:
Offset:
Reset:
Property:
Bit
LUTnCTRLC
0x0A + n*0x04 [n=0..3]
0x00
Enable-Protected
7
6
5
4
Access
Reset
3
R/W
0
2
1
INSEL2[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – INSEL2[3:0] LUT n Input 2 Source Selection
These bits select the source for input 2 of LUT n.
Value
Name
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
Other
MASK
FEEDBACK
LINK
EVENTA
EVENTB
IO
AC0
USART2
SPI0
TCA0
TCB2
-
None (masked)
Feedback input
Output from LUTn+1
Event input source A
Event input source B
I/O-pin LUTn-IN2
AC0 out
Reserved
USART2 TXD
SPI0 SCK
TCA0 WO2
Reserved
TCB2 WO
Reserved
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27.5.9
TRUTHn
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
TRUTHn
0x0B + n*0x04 [n=0..3]
0x00
Enable-Protected
7
6
5
R/W
0
R/W
0
R/W
0
4
3
TRUTHn[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TRUTHn[7:0] Truth Table
These bits determine the output of LUTn according to the LUTn-TRUTHSEL[2:0] inputs.
Bit Name
TRUTHn[0]
TRUTHn[1]
TRUTHn[2]
TRUTHn[3]
TRUTHn[4]
TRUTHn[5]
TRUTHn[6]
TRUTHn[7]
Value
Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The output of LUTn is 0 when the inputs are 'b000
The output of LUTn is 1 when the inputs are 'b000
The output of LUTn is 0 when the inputs are 'b001
The output of LUTn is 1 when the inputs are 'b001
The output of LUTn is 0 when the inputs are 'b010
The output of LUTn is 1 when the inputs are 'b010
The output of LUTn is 0 when the inputs are 'b011
The output of LUTn is 1 when the inputs are 'b011
The output of LUTn is 0 when the inputs are 'b100
The output of LUTn is 1 when the inputs are 'b100
The output of LUTn is 0 when the inputs are 'b101
The output of LUTn is 1 when the inputs are 'b101
The output of LUTn is 0 when the inputs are 'b110
The output of LUTn is 1 when the inputs are 'b110
The output of LUTn is 0 when the inputs are 'b111
The output of LUTn is 1 when the inputs are 'b111
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AC - Analog Comparator
28.
AC - Analog Comparator
28.1
Features
•
•
•
•
•
•
•
28.2
Selectable Response Time
Selectable Hysteresis
Analog Comparator Output Available on Pin
Comparator Output Inversion Available
Flexible Input Selection:
– Four Positive pins
– Three Negative pins
– Internal reference voltage generator (DACREF)
Interrupt Generation on:
– Rising edge
– Falling edge
– Both edges
Event Generation on:
– Comparator output
Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on
this comparison. The AC can be configured to generate interrupt requests and/or events upon several different
combinations of input change.
The dynamic behavior of the AC can be adjusted by a hysteresis feature. The hysteresis can be customized to
optimize the operation for each application.
The input selection includes analog port pins and internally generated inputs. The analog comparator output state
can also be the output on a pin for use by external devices.
An AC has one positive input and one negative input. The digital output from the comparator is '1' when the
difference between the positive and the negative input voltage is positive, and '0' otherwise.
Block Diagram
Figure 28-1. Analog Comparator
AINP0
.
.
.
+
AINPn
VREF
.
..
Voltage
divider
-
Controller
logic
Invert
AINNn
AC
Hysteresis
AINN0
Enable
28.2.1
CMP
(Int. Req)
OUT
Event out
CTRLA
DACREF
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AC - Analog Comparator
28.2.2
Signal Description
Signal
Description
Type
AINNn
Negative Input n
Analog
AINPn
Positive Input n
Analog
OUT
Comparator Output for AC
Digital
28.3
Functional Description
28.3.1
Initialization
For a basic operation, follow these steps:
• Configure the desired input pins in the port peripheral
• Select the positive and negative input sources by writing the Positive and Negative Input MUX Selection
(MUXPOS and MUXNEG) bit fields in the MUX Control A (ACn.MUXCTRLA) register
• Optional: Enable the output to pin by writing a '1' to the Output Pad Enable (OUTEN) bit in the Control A
(ACn.CTRLA) register
• Enable the AC by writing a '1' to the ENABLE bit in ACn.CTRLA
During the start-up time after enabling the AC, the output of the AC may be invalid.
The start-up time of the AC by itself is at most 2.5 µs. If an internal reference is used, the reference start-up time is
normally longer than the AC start-up time.
To avoid the pin being tri-stated when the AC is disabled, the OUT pin must be configured as output in PORTx.DIR.
28.3.2
Operation
28.3.2.1 Input Hysteresis
Applying an input hysteresis helps to prevent constant toggling of the output when the noise-afflicted input signals are
close to each other.
The input hysteresis can either be disabled or have one of three levels. The hysteresis is configured by writing to the
Hysteresis Mode Select (HYSMODE) bit field in the Control A (ACn.CTRLA) register.
28.3.2.2 Input Sources
An AC has one positive and one negative input. The inputs can be pins and internal sources, such as a voltage
reference.
Each input is selected by writing to the Positive and Negative Input MUX Selection (MUXPOS and MUXNEG) bit field
in the MUX Control A (ACn.MUXCTRLA) register.
28.3.2.2.1 Pin Inputs
The following analog input pins on the port can be selected as input to the analog comparator:
•
•
•
•
•
•
•
AINN0
AINN1
AINN2
AINP0
AINP1
AINP2
AINP3
28.3.2.2.2 Internal Inputs
The AC has the following internal inputs:
•
Internal reference voltage generator (DACREF)
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AC - Analog Comparator
28.3.2.3 Power Modes
For power sensitive applications, the AC provides a low-power mode with lower power consumption and increased
propagation delay. The low-power mode is selected by writing the Low Power Mode (LPMODE) bit in the Control A
(ACn.CTRLA) register to ‘1’.
28.3.2.4 Signal Compare and Interrupt
After the successful initialization of the AC and after configuring the desired properties, the result of the comparison is
continuously updated and is available for the application software, for the Event System, or on a pin.
The AC can generate a comparator interrupt, COMP, and can request this interrupt on either rising, falling, or both
edges of the toggling comparator output. This is configured by writing to the Interrupt Modes (INTMODE) bit field in
the Control A (ACn.CTRLA) register.
The interrupt is enabled by writing a ‘1’ to the Analog Comparator Interrupt Enable (COMP) bit in the Interrupt Control
(ACn.INTCTRL) register.
28.3.3
Events
The AC can generate the events described in the table below.
Table 28-1. Event Generators in AC
Generator Name
Description
Peripheral Event
ACn
OUT
Event Type Generating Clock Domain
Comparator output level
Level
Asynchronous
Length of Event
Given by AC output level
The AC has no event inputs.
28.3.4
Interrupts
Table 28-2. Available Interrupt Vectors and Sources
Name
Vector Description
Conditions
COMP
Analog comparator interrupt
AC output is toggling as configured by INTMODE in ACn.CTRLA
When an interrupt condition occurs, the corresponding Interrupt flag is set in the Status (ACn.STATUS) register.
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt Control
(ACn.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled and the Interrupt flag is set.
The interrupt request remains active until the Interrupt flag is cleared. See the ACn.STATUS register description for
details on how to clear the Interrupt flags.
28.3.5
Sleep Mode Operation
In Idle sleep mode the AC will continue to operate as normal.
In Standby sleep mode the AC is disabled by default. If the Run in Standby (RUNSTDBY) bit in the Control A
(ACn.CTRLA) register is written to '1', the AC will continue to operate as normal with event, interrupt and AC output
on pad even if the CLK_PER is not running in Standby sleep mode.
In Power-Down sleep mode the AC and the output to the pad are disabled.
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AC - Analog Comparator
28.4
Register Summary
Offset
Name
Bit Pos.
7
6
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
Reserved
MUXCTRLA
Reserved
DACREF
Reserved
INTCTRL
STATUS
7:0
RUNSTDBY
OUTEN
7:0
INVERT
28.5
7:0
7:0
7:0
5
4
3
INTMODE[1:0]
LPMODE
MUXPOS[1:0]
2
1
HYSMODE[1:0]
0
ENABLE
MUXNEG[1:0]
DACREF[7:0]
STATE
CMP
CMP
Register Description
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AC - Analog Comparator
28.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RUNSTDBY
R/W
0
CTRLA
0x00
0x00
-
6
OUTEN
R/W
0
5
4
INTMODE[1:0]
R/W
R/W
0
0
3
LPMODE
R/W
0
2
1
HYSMODE[1:0]
R/W
R/W
0
0
0
ENABLE
R/W
0
Bit 7 – RUNSTDBY Run in Standby Mode
Writing a '1' to this bit allows the AC to continue operation in Standby sleep mode. Since the clock is stopped,
interrupts and Status flags are not updated.
Value
Description
0
In Standby sleep mode, the peripheral is halted
1
In Standby sleep mode, the peripheral continues operation
Bit 6 – OUTEN Analog Comparator Output Pad Enable
Writing this bit to '1' makes the OUT signal available on the pin.
Bits 5:4 – INTMODE[1:0] Interrupt Modes
Writing to these bits selects which edges of the AC output triggers an interrupt request.
Value
Name
Description
0x0
BOTHEDGE
Both negative and positive edge
0x1
Reserved
0x2
NEGEDGE
Negative edge
0x3
POSEDGE
Positive edge
Bit 3 – LPMODE Low-Power Mode
Writing a '1' to this bit reduces the current through the comparator. This reduces the power consumption, but
increases the reaction time of the AC.
Value
Description
0
Low-Power mode disabled
1
Low-Power mode enabled
Bits 2:1 – HYSMODE[1:0] Hysteresis Mode Select
Writing these bits selects the Hysteresis mode for the AC input.
Value
Name
Description
0x0
NONE
No hysteresis
0x1
SMALL
Small hysteresis
0x2
MEDIUM
Medium hysteresis
0x3
LARGE
Large hysteresis
Bit 0 – ENABLE Enable AC
Writing this bit to '1' enables the AC.
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AC - Analog Comparator
28.5.2
MUX Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
MUXCTRLA
0x02
0x00
-
7
INVERT
R/W
0
6
5
4
3
MUXPOS[1:0]
R/W
R/W
0
0
2
1
0
MUXNEG[1:0]
R/W
R/W
0
0
Bit 7 – INVERT Invert AC Output
Writing this bit to ‘1’ enables inversion of the output of the AC. This inversion has to be taken into account when using
the AC output signal as an input signal to other peripherals or parts of the system.
Bits 4:3 – MUXPOS[1:0] Positive Input MUX Selection
Writing to this bit field selects the input signal to the positive input of the AC.
Value
Name
Description
0x0
0x1
0x2
0x3
AINP0
AINP1
AINP2
AINP3
Positive pin 0
Positive pin 1
Positive pin 2
Positive pin 3
Bits 1:0 – MUXNEG[1:0] Negative Input MUX Selection
Writing to this bit field selects the input signal to the negative input of the AC.
Value
Name
Description
0x0
0x1
0x2
0x3
AINN0
AINN1
AINN2
DACREF
Negative pin 0
Negative pin 1
Negative pin 2
Internal DAC reference
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AC - Analog Comparator
28.5.3
DAC Voltage Reference
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
DACREF
0x04
0xFF
R/W
7
6
5
R/W
1
R/W
1
R/W
1
4
3
DACREF[7:0]
R/W
R/W
1
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 7:0 – DACREF[7:0] DACREF Data Value
These bits define the output voltage from the internal voltage divider. The DAC voltage reference depends on the
DACREF value and the reference voltage selected in the VREF module, and is calculated as:
VDACREF = DACREF × VREF
256
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AC - Analog Comparator
28.5.4
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x06
0x00
-
6
5
4
3
Access
Reset
2
1
0
CMP
R/W
0
Bit 0 – CMP Analog Comparator Interrupt Enable
Writing this bit to '1' enables the Analog Comparator Interrupt.
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AC - Analog Comparator
28.5.5
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x07
0x00
-
6
Access
Reset
5
4
STATE
R
0
3
2
1
0
CMP
R/W
0
Bit 4 – STATE Analog Comparator State
This bit shows the current status of the OUT signal from the AC. It will have a synchronizer delay to get updated in
the I/O register (three cycles).
Bit 0 – CMP Analog Comparator Interrupt Flag
This is the interrupt flag for the AC. Writing a ‘1’ to this bit will clear the interrupt flag.
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ADC - Analog-to-Digital Converter
29.
ADC - Analog-to-Digital Converter
29.1
Features
•
•
•
•
•
•
•
•
•
•
•
29.2
10-Bit Resolution
0V to VDD Input Voltage Range
Multiple Internal ADC Reference Voltages
External Reference Input
Free-Running and Single Conversion Mode
Interrupt Available on Conversion Complete
Optional Interrupt on Conversion Results
Temperature Sensor Input Channel
Optional Event-Triggered Conversion
Window Comparator Function for Accurate Monitoring or Defined Thresholds
Accumulation up to 64 Samples per Conversion
Overview
The Analog-to-Digital Converter (ADC) peripheral produces 10-bit results. The ADC input can either be internal (e.g.,
a voltage reference) or external through the analog input pins. The ADC is connected to an analog multiplexer, which
allows the selection of multiple single-ended voltage inputs. The single-ended voltage inputs refer to 0V (GND).
The ADC supports sampling in bursts where a configurable number of conversion results are accumulated into a
single ADC result (Sample Accumulation). Further, a sample delay can be configured to tune the ADC sampling
frequency associated with a single burst. This is to tune the sampling frequency away from any harmonic noise
aliased with the ADC sampling frequency (within the burst) from the sampled signal. An automatic sampling delay
variation feature can be used to randomize this delay to slightly change the time between samples.
The ADC input signal is fed through a sample-and-hold circuit that ensures that the input voltage to the ADC is held
at a constant level during sampling.
The selectable voltage references from the internal Voltage Reference (VREF) peripheral, are VDD supply voltage, or
external VREF pin (VREFA).
A window compare feature is available for monitoring the input signal and can be configured to only trigger an
interrupt on user-defined thresholds for under, over, inside, or outside a window, with minimum software intervention
required.
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ADC - Analog-to-Digital Converter
29.2.1
Block Diagram
Figure 29-1. Block Diagram
AVDD
VREFA
Internal reference
.
.
.
ADC
AINn
MUXPOS
"convert"
Temp.Sense
"enable"
DACREF0
ACC
"accumulate"
AIN0
AIN1
VREF
Control logic
RES
>
<
WCMP
(Int. Req.)
WINLT
WINHT
RESRDY
(Int. Req.)
The analog input channel is selected by writing to the MUXPOS bits in the MUXPOS (ADCn.MUXPOS) register.
Any of the ADC input pins, GND, internal Voltage Reference (VREF), or temperature sensor, can be selected as
a single-ended input to the ADC. The ADC is enabled by writing a ‘1’ to the ADC ENABLE bit in the Control A
(ADCn.CTRLA) register. The voltage reference and input channel selections will not go into effect before the ADC is
enabled. The ADC does not consume power when the ENABLE bit in ADCn.CTRLA is ‘0’.
The ADC generates a 10-bit result that can be read from the Result (ADCn.RES) Register. The result is presented
right-adjusted.
29.2.2
Signal Description
Pin Name
Type
Description
AIN[n:0]
Analog input
Analog input pin
VREFA
Analog input
External voltage reference pin
29.3
Functional Description
29.3.1
Initialization
The following steps are recommended to initialize the ADC operation:
1. Configure the resolution by writing to the Resolution Selection (RESSEL) bit in the Control A (ADCn.CTRLA)
register.
2. Optional: Enable the Free-Running mode by writing a ‘1’ to the Free-Running (FREERUN) bit in
ADCn.CTRLA.
3. Optional: Configure the number of samples to be accumulated per conversion by writing the Sample
Accumulation Number Select (SAMPNUM) bits in the Control B (ADCn.CTRLB) register.
4. Configure a voltage reference by writing to the Reference Selection (REFSEL) bit in the Control C
(ADCn.CTRLC) register. The default is the internal voltage reference of the device (VREF, as configured there).
5. Configure the CLK_ADC by writing to the Prescaler (PRESC) bit field in the Control C (ADCn.CTRLC) register.
6. Configure an input by writing to the MUXPOS bit field in the MUXPOS (ADCn.MUXPOS) register.
7. Optional: Enable Start Event input by writing a ‘1’ to the Start Event Input (STARTEI) bit in the Event Control
(ADCn.EVCTRL) register. Configure the Event System accordingly.
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ADC - Analog-to-Digital Converter
8.
Enable the ADC by writing a ‘1’ to the ENABLE bit in ADCn.CTRLA.
Following these steps will initialize the ADC for basic measurements, which can be triggered by an event (if
configured) or by writing a ‘1’ to the Start Conversion (STCONV) bit in the Command (ADCn.COMMAND) register.
29.3.1.1 I/O Lines and Connections
The I/O pins AINx and VREF are configured by the port - I/O Pin Controller.
The digital input buffer should be disabled on the pin used as input for the ADC to disconnect the digital domain from
the analog domain to obtain the best possible ADC results. This is configured by the PORT peripheral.
29.3.2
Operation
29.3.2.1 Starting a Conversion
Once the input channel is selected by writing to the MUXPOS (ADCn.MUXPOS) register, a conversion is triggered
by writing a ‘1’ to the ADC Start Conversion (STCONV) bit in the Command (ADCn.COMMAND) register. This bit is
‘1’ as long as the conversion is in progress. In Single Conversion mode, STCONV is cleared by hardware when the
conversion is completed.
If a different input channel is selected while a conversion is in progress, the ADC will finish the current conversion
before changing the channel.
Depending on the accumulator setting, the conversion result is from a single sensing operation or a sequence of
accumulated samples. Once the triggered operation is finished, the Result Ready (RESRDY) flag in the Interrupt Flag
(ADCn.INTFLAG) register is set. The corresponding interrupt vector is executed if the Result Ready Interrupt Enable
(RESRDY) bit in the Interrupt Control (ADCn.INTCTRL) register is ‘1’ and the Global Interrupt Enable bit is ‘1’.
A single conversion can be started by writing a ‘1’ to the STCONV bit in ADCn.COMMAND. The STCONV bit can be
used to determine if a conversion is in progress. The STCONV bit will be set during a conversion and cleared once
the conversion is complete.
The RESRDY interrupt flag in ADCn.INTFLAG will be set even if the specific interrupt is disabled, allowing software
to check for finished conversion by polling the flag. A conversion can thus be triggered without causing an interrupt.
Alternatively, a conversion can be triggered by an event. This is enabled by writing a ‘1’ to the Start Event Input
(STARTEI) bit in the Event Control (ADCn.EVCTRL) register. Any incoming event routed to the ADC through the
Event System (EVSYS) will trigger an ADC conversion. This provides a method to start conversions at predictable
intervals or specific conditions.
The event trigger input is edge sensitive. When an event occurs, STCONV in ADCn.COMMAND is set. STCONV will
be cleared when the conversion is complete.
In Free-Running mode, the first conversion is started by writing the STCONV bit to ‘1’ in ADCn.COMMAND. A new
conversion cycle is started immediately after the previous conversion cycle has completed. A conversion complete
will set the RESRDY flag in ADCn.INTFLAGS.
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ADC - Analog-to-Digital Converter
29.3.2.2 Clock Generation
Figure 29-2. ADC Prescaler
ENABLE
"START"
Reset
8-bit PRESCALER
CTRLC
CLK_PER/256
CLK_PER/128
CLK_PER/64
CLK_PER/32
CLK_PER/16
CLK_PER/8
CLK_PER/4
CLK_PER/2
CLK_PER
PRESC
ADC clock source
(CLK_ADC)
The ADC requires an input clock frequency between 50 kHz and 1.5 MHz for maximum resolution. If a lower
resolution than ten bits is selected, the input clock frequency to the ADC can be higher than 1.5 MHz to get a higher
sample rate.
The ADC module contains a prescaler which generates the ADC clock (CLK_ADC) from any CPU clock (CLK_PER)
above 100 kHz. The prescaling is selected by writing to the Prescaler (PRESC) bits in the Control C (ADCn.CTRLC)
register. The prescaler starts counting from the moment the ADC is switched on by writing a ‘1’ to the ENABLE bit in
ADCn.CTRLA. The prescaler keeps running as long as the ENABLE bit is ‘1’. The prescaler counter is reset to zero
when the ENABLE bit is ‘0’.
When initiating a conversion by writing a ‘1’ to the Start Conversion (STCONV) bit in the Command
(ADCn.COMMAND) register or from an event, the conversion starts at the following rising edge of the CLK_ADC
clock cycle. The prescaler is kept reset as long as there is no ongoing conversion. This assures a fixed delay from
the trigger to the actual start of a conversion in CLK_PER cycles, as follows:
StartDelay =
PRESCfactor
+2
2
Figure 29-3. Start Conversion and Clock Generation
CLK_PER
STCONV
CLK_PER/2
CLK_PER/4
CLK_PER/8
29.3.2.3 Conversion Timing
A normal conversion takes 13 CLK_ADC cycles. The actual sample-and-hold takes place two CLK_ADC cycles
after the start of a conversion. The start of a conversion is initiated by writing a ‘1’ to the STCONV bit in
ADCn.COMMAND. When a conversion is complete, the result is available in the Result (ADCn.RES) register, and the
Result Ready interrupt flag is set (RESRDY in ADCn.INTFLAG). The interrupt flag will be cleared when the result is
read from the Result registers, or by writing a ‘1’ to the RESRDY bit in ADCn.INTFLAG.
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ADC - Analog-to-Digital Converter
Figure 29-4. ADC Timing Diagram - Single Conversion
Cycle Number
1
2
3
4
5
6
7
9
8
10
11
13
12
CLK_ADC
ENABLE
STCONV
RESRDY
RES
Result
conversion
complete
Both sampling time and sampling length can be adjusted using the Sample Delay bit field in the Control D
(ADCn.CTRLD) register and the Sample Length bit field in the Sample Control (ADCn.SAMPCTRL) register. Both
of these control the ADC sampling time in some CLK_ADC cycles. This allows sampling of high-impedance sources
without relaxing conversion speed. See the register description for further information. Total sampling time is given
by:
sample
SampleTime =
2 + SAMPDLY + SAMPLEN
fCLK_ADC
Figure 29-5. ADC Timing Diagram - Single Conversion With Delays
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK_ADC
ENABLE
STCONV
RES
Result
INITDLY
(0 – 256
CLK_ADC cycles)
SAMPDLY
(0 – 15
CLK_ADC cycles)
SAMPLEN
(0 – 31
CLK_ADC cycles)
In Free-Running mode, a new conversion will be started immediately after the conversion completes, while the
STCONV bit is ‘1’. The sampling rate RS in Free-Running mode is calculated by:
RS =
fCLK_ADC
13 + SAMPDLY + SAMPLEN
Figure 29-6. ADC Timing Diagram - Free-Running Conversion
2
3
4
6
5
7
1
Cycle Number
8
9
10
11
12
13
1
2
CLK_ADC
ENABLE
STCONV
RESRDY
RES
Result
sample
conversion
complete
29.3.2.4 Changing Channel or Reference Selection
The MUXPOS bits in the ADCn.MUXPOS register and the REFSEL bits in the ADCn.CTRLC register are buffered
through a temporary register to which the CPU has random access. This ensures that the channel and reference
selections only take place at a safe point during the conversion. The channel and reference selections are
continuously updated until a conversion is started.
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ADC - Analog-to-Digital Converter
Once the conversion starts, the channel and reference selections are locked to ensure sufficient sampling time for the
ADC. Continuous updating resumes in the last CLK_ADC clock cycle before the conversion completes (RESRDY in
ADCn.INTFLAGS is set). The conversion starts on the following rising CLK_ADC clock edge after the STCONV bit is
written to ‘1’.
29.3.2.4.1 ADC Input Channels
When changing channel selection, the user must observe the following guidelines to ensure that the correct channel
is selected:
In Single Conversion mode: The channel should be selected before starting the conversion. The channel selection
may be changed one ADC clock cycle after writing ‘1’ to the STCONV bit.
In Free-Running mode: The channel should be selected before starting the first conversion. The channel selection
may be changed one ADC clock cycle after writing ‘1’ to the STCONV bit. Since the next conversion has already
started automatically, the next result will reflect the previous channel selection. The subsequent conversions will
reflect the new channel selection.
The ADC requires a settling time after switching the input channel - refer to the Electrical Characteristics section for
details.
29.3.2.4.2 ADC Voltage Reference
The reference voltage for the ADC (VREF) controls the conversion range of the ADC. Input voltages that exceed the
selected VREF will be converted to the maximum result value of the ADC. For an ideal 10-bit ADC, this value is 0x3FF.
VREF can be selected by writing the Reference Selection (REFSEL) bits in the Control C (ADCn.CTRLC) register as
either VDD, external reference VREFA, or an internal reference from the VREF peripheral. VDD is connected to the ADC
through a passive switch.
When using the external reference voltage VREFA, configure ADCnREFSEL[0:2] in the corresponding VREF.CTRLn
register to the value that is closest, but above the applied reference voltage. For external references higher than 4.3V,
use ADCnREFSEL[0:2] = 0x3.
The internal reference is generated from an internal band gap reference through an internal amplifier, controlled by
the Voltage Reference (VREF) peripheral.
29.3.2.4.3 Analog Input Circuitry
The analog input circuitry is illustrated in Figure 29-7. An analog source applied to ADCn is subjected to the pin
capacitance and input leakage of that pin (represented by IH and IL), regardless of whether that channel is selected
as input for the ADC or not. When the channel is selected, the source must drive the S/H capacitor through the series
resistance (combined resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source
is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend
on how long the source needs to charge the S/H capacitor, which can vary substantially.
Figure 29-7. Analog Input Schematic
IIH
ADCn
Rin
Cin
IIL
VDD/2
29.3.2.5 ADC Conversion Result
After the conversion is complete (RESRDY is ‘1’), the conversion result RES is available in the ADC Result
(ADCn.RES) register. The result of a 10-bit conversion is given as follows:
RES =
1023 × VIN
VREF
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ADC - Analog-to-Digital Converter
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see description for
REFSEL in ADCn.CTRLC and ADCn.MUXPOS).
29.3.2.6 Temperature Measurement
The temperature measurement is based on an on-chip temperature sensor. For temperature measurement, follow
these steps:
1. Configure the internal voltage reference to 1.1V by configuring the VREF peripheral.
2. Select the internal voltage reference by writing the REFSEL bits in ADCn.CTRLC to 0x0.
3. Select the ADC temperature sensor channel by configuring the MUXPOS (ADCn.MUXPOS) register. This
enables the temperature sensor.
4. In ADCn.CTRLD select INITDLY ≥ 32 µs × fCLK_ADC.
5.
6.
7.
8.
In ADCn.SAMPCTRL select SAMPLEN ≥ 32 µs × fCLK_ADC.
In ADCn.CTRLC select SAMPCAP = 1.
Acquire the temperature sensor output voltage by starting a conversion.
Process the measurement result, as described below.
The measured voltage has a linear relationship to the temperature. Due to process variations, the temperature
sensor output voltage varies between individual devices at the same temperature. The individual compensation
factors are determined during the production test and saved in the Signature Row:
• SIGROW.TEMPSENSE0 is a gain/slope correction
• SIGROW.TEMPSENSE1 is an offset correction
To achieve accurate results, the result of the temperature sensor measurement must be processed in the application
software using factory calibration values. The temperature (in Kelvin) is calculated by this rule:
Temp = (((RESH > 8
RESH and RESL are the high and low bytes of the Result register (ADCn.RES), and TEMPSENSEn are the
respective values from the Signature row.
It is recommended to follow these steps in user code:
int8_t sigrow_offset = SIGROW.TEMPSENSE1; // Read signed value from signature row
uint8_t sigrow_gain = SIGROW.TEMPSENSE0;
// Read unsigned value from signature row
uint16_t adc_reading = 0;
// ADC conversion result with 1.1 V internal reference
uint32_t temp = adc_reading - sigrow_offset;
temp *= sigrow_gain; // Result might overflow 16 bit variable (10bit+8bit)
temp += 0x80;
// Add 1/2 to get correct rounding on division below
temp >>= 8;
// Divide result to get Kelvin
uint16_t temperature_in_K = temp;
29.3.2.7 Window Comparator Mode
The ADC can raise the WCMP flag in the Interrupt and Flag (ADCn.INTFLAG) register and request an interrupt
(WCMP) when the result of a conversion is above and/or below certain thresholds. The available modes are:
• The result is under a threshold
• The result is over a threshold
• The result is inside a window (above a lower threshold, but below the upper one)
• The result is outside a window (either under the lower or above the upper threshold)
The thresholds are defined by writing to the Window Comparator Threshold registers (ADCn.WINLT and
ADCn.WINHT). Writing to the Window Comparator mode (WINCM) bit field in the Control E (ADCn.CTRLE) register
selects the conditions when the flag is raised and/or the interrupt is requested.
Assuming the ADC is already configured to run, follow these steps to use the Window Comparator mode:
1. Choose which Window Comparator to use (see the WINCM description in ADCn.CTRLE), and set the required
threshold(s) by writing to ADCn.WINLT and/or ADCn.WINHT.
2. Optional: enable the interrupt request by writing a ‘1’ to the Window Comparator Interrupt Enable (WCMP) bit
in the Interrupt Control (ADCn.INTCTRL) register.
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3.
Enable the Window Comparator and select a mode by writing a non-zero value to the WINCM bit field in
ADCn.CTRLE.
When accumulating multiple samples, the comparison between the result and the threshold will happen after the last
sample was acquired. Consequently, the flag is raised only once, after taking the last sample of the accumulation.
29.3.3
Events
An ADC conversion can be triggered automatically by an event input if the Start Event Input (STARTEI) bit in the
Event Control (ADCn.EVCTRL) register is written to ‘1’.
When a new result can be read from the Result (ADCn.RES) register, the ADC will generate a result ready event.
The event is a pulse with a length of one clock period and handled by the Event System (EVSYS). The ADC result
ready event is always generated when the ADC is enabled.
See also the description of the Asynchronous User Channel n Input Selection in the Event System
(EVSYS.ASYNCUSERn).
29.3.4
Interrupts
Table 29-1. Available Interrupt Vectors and Sources
Name
Vector Description
Conditions
RESRDY Result Ready interrupt
The conversion result is available in the Result register (ADCn.RES)
WCMP
As defined by WINCM in ADCn.CTRLE
Window Comparator interrupt
When an interrupt condition occurs, the corresponding interrupt flag is set in the peripheral’s Interrupt Flags
(peripheral.INTFLAGS) register.
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral’s Interrupt
Control (peripheral.INTCTRL) register.
An interrupt request is generated when the corresponding interrupt source is enabled, and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral’s INTFLAGS register for
details on how to clear interrupt flags.
29.3.5
Sleep Mode Operation
The ADC is by default disabled in Standby sleep mode.
The ADC can stay fully operational in Standby sleep mode if the Run in Standby (RUNSTDBY) bit in the Control A
(ADCn.CTRLA) register is written to ‘1’.
When the device is entering Standby sleep mode when RUNSTDBY is ‘1’, the ADC will stay active, hence any
ongoing conversions will be completed, and interrupts will be executed as configured.
In Standby sleep mode, an ADC conversion must be triggered via the Event System (EVSYS), or the ADC must be
in Free-Running mode with the first conversion triggered by software before entering a sleep mode. The peripheral
clock is requested if needed and is turned off after the conversion is completed.
When an input event trigger occurs, the positive edge will be detected, the Start Conversion (STCONV) bit in the
Command (ADCn.COMMAND) register is set, and the conversion will start. When the conversion is completed,
the Result Ready (RESRDY) flag in the Interrupt Flags (ADCn.INTFLAGS) register is set, and the STCONV bit in
ADCn.COMMAND is cleared.
The reference source and supply infrastructure need time to stabilize when activated in Standby sleep mode.
Configure a delay for the start of the first conversion by writing a non-zero value to the Initial Delay (INITDLY) bits in
the Control D (ADCn.CTRLD) register.
In Power-Down sleep mode, no conversions are possible. Any ongoing conversions are halted and will be resumed
when going out of a sleep mode. At the end of conversion, the Result Ready (RESRDY) flag will be set, but the
content of the result (ADCn.RES) registers is invalid since the ADC was halted in the middle of a conversion.
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29.4
Register Summary - ADCn
Offset
Name
Bit Pos.
7
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
...
0x0F
CTRLA
CTRLB
CTRLC
CTRLD
CTRLE
SAMPCTRL
MUXPOS
Reserved
COMMAND
EVCTRL
INTCTRL
INTFLAGS
DBGCTRL
TEMP
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RUNSTBY
0x10
RES
0x12
WINLT
0x14
WINHT
0x16
CALIB
29.5
7:0
7:0
7:0
7:0
7:0
7:0
6
5
4
3
2
1
RESSEL
SAMPCAP
INITDLY[2:0]
REFSEL[1:0]
ASDV
FREERUN
SAMPNUM[2:0]
PRESC[2:0]
SAMPDLY[3:0]
WINCM[2:0]
SAMPLEN[4:0]
MUXPOS[4:0]
WCMP
WCMP
0
ENABLE
STCONV
STARTEI
RESRDY
RESRDY
DBGRUN
TEMP[7:0]
Reserved
7:0
15:8
7:0
15:8
7:0
15:8
7:0
RES[7:0]
RES[15:8]
WINLT[7:0]
WINLT[15:8]
WINHT[7:0]
WINHT[15:8]
DUTYCYC
Register Description
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29.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RUNSTBY
R/W
0
CTRLA
0x00
0x00
-
6
5
4
3
2
RESSEL
R/W
0
1
FREERUN
R/W
0
0
ENABLE
R/W
0
Bit 7 – RUNSTBY Run in Standby
This bit determines whether the ADC needs to run when the chip is in Standby sleep mode.
Bit 2 – RESSEL Resolution Selection
This bit selects the ADC resolution.
Value
Description
0
Full 10-bit resolution. The 10-bit ADC results are accumulated or stored in the ADC Result (ADC.RES)
register.
1
8-bit resolution. The conversion results are truncated to eight bits (MSbs) before they are accumulated
or stored in the ADC Result (ADC.RES) register. The two Least Significant bits (LSbs) are discarded.
Bit 1 – FREERUN Free-Running
Writing a ‘1’ to this bit will enable the Free-Running mode for the data acquisition. The first conversion is started
by writing the STCONV bit in ADC.COMMAND high. In the Free-Running mode, a new conversion cycle is started
immediately after or as soon as the previous conversion cycle has completed. This is signaled by the RESRDY flag in
ADCn.INTFLAGS.
Bit 0 – ENABLE ADC Enable
Value
Description
0
ADC is disabled
1
ADC is enabled
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29.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
-
6
5
4
3
Access
Reset
2
R/W
0
1
SAMPNUM[2:0]
R/W
0
0
R/W
0
Bits 2:0 – SAMPNUM[2:0] Sample Accumulation Number Select
These bits select how many consecutive ADC sampling results are accumulated automatically. When this bit is
written to a value greater than 0x0, the according number of consecutive ADC sampling results are accumulated into
the ADC Result (ADC.RES) register in one complete conversion.
Value
Name
Description
0x0
NONE
No accumulation
0x1
ACC2
2 results accumulated
0x2
ACC4
4 results accumulated
0x3
ACC8
8 results accumulated
0x4
ACC16
16 results accumulated
0x5
ACC32
32 results accumulated
0x6
ACC64
64 results accumulated
0x7
Reserved
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29.5.3
Control C
Name:
Offset:
Reset:
Property:
Bit
7
Access
Reset
R
0
CTRLC
0x02
0x00
-
6
SAMPCAP
R/W
0
5
4
REFSEL[1:0]
R/W
R/W
0
0
3
2
R
0
R/W
0
1
PRESC[2:0]
R/W
0
0
R/W
0
Bit 6 – SAMPCAP Sample Capacitance Selection
This bit selects the sample capacitance, and hence, the input impedance. The best value is dependent on the
reference voltage and the application's electrical properties.
Value
Description
0
Recommended for reference voltage values below 1V
1
Reduced size of sampling capacitance. Recommended for higher reference voltages.
Bits 5:4 – REFSEL[1:0] Reference Selection
These bits select the voltage reference for the ADC.
Value
Name
Description
0x0
INTERNAL
Internal reference
0x1
VDD
VDD
0x2
VREFA
External reference VREFA
Other
Reserved
Bits 2:0 – PRESC[2:0] Prescaler
These bits define the division factor from the peripheral clock (CLK_PER) to the ADC clock (CLK_ADC).
Value
Name
Description
0x0
DIV2
CLK_PER divided by 2
0x1
DIV4
CLK_PER divided by 4
0x2
DIV8
CLK_PER divided by 8
0x3
DIV16
CLK_PER divided by 16
0x4
DIV32
CLK_PER divided by 32
0x5
DIV64
CLK_PER divided by 64
0x6
DIV128
CLK_PER divided by 128
0x7
DIV256
CLK_PER divided by 256
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29.5.4
Control D
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
R/W
0
CTRLD
0x03
0x00
-
6
INITDLY[2:0]
R/W
0
5
R/W
0
4
ASDV
R/W
0
3
R/W
0
2
1
SAMPDLY[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 7:5 – INITDLY[2:0] Initialization Delay
These bits define the initialization/start-up delay before the first sample when enabling the ADC or changing to an
internal reference voltage. Setting this delay will ensure that the reference, MUXes, etc. are ready before starting the
first conversion. The initialization delay will also take place when waking up from deep sleep to do a measurement.
The delay is expressed as a number of CLK_ADC cycles.
Value
Name
Description
0x0
DLY0
Delay 0 CLK_ADC cycles
0x1
DLY16
Delay 16 CLK_ADC cycles
0x2
DLY32
Delay 32 CLK_ADC cycles
0x3
DLY64
Delay 64 CLK_ADC cycles
0x4
DLY128
Delay 128 CLK_ADC cycles
0x5
DLY256
Delay 256 CLK_ADC cycles
Other
Reserved
Bit 4 – ASDV Automatic Sampling Delay Variation
Writing this bit to ‘1’ enables automatic sampling delay variation between ADC conversions. The purpose of
varying sampling instant is to randomize the sampling instant and thus avoid standing frequency components in
the frequency spectrum. The value of the SAMPDLY bits is automatically incremented by one after each sample.
When the Automatic Sampling Delay Variation is enabled, and the SAMPDLY value reaches 0xF, it wraps around to
0x0.
Value
Name
Description
0
ASVOFF
The Automatic Sampling Delay Variation is disabled
1
ASVON
The Automatic Sampling Delay Variation is enabled
Bits 3:0 – SAMPDLY[3:0] Sampling Delay Selection
These bits define the delay between consecutive ADC samples. The programmable sampling delay allows modifying
the sampling frequency during hardware accumulation to suppress periodic noise sources that may otherwise disturb
the sampling. The SAMPDLY field can also be modified automatically from one sampling cycle to another, by setting
the ASDV bit. The delay is expressed as CLK_ADC cycles and is given directly by the bit field setting. The sampling
cap is kept open during the delay.
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29.5.5
Control E
Name:
Offset:
Reset:
Property:
Bit
7
CTRLE
0x4
0x00
-
6
5
4
3
Access
Reset
2
R/W
0
1
WINCM[2:0]
R/W
0
0
R/W
0
Bits 2:0 – WINCM[2:0] Window Comparator Mode
This bit field enables and defines when the interrupt flag is set in Window Comparator mode. RESULT is the
16-bit accumulator result. WINLT and WINHT are 16-bit lower threshold value and 16-bit higher threshold value,
respectively.
Value
Name
Description
0x0
NONE
No Window Comparison (default)
0x1
BELOW
RESULT < WINLT
0x2
ABOVE
RESULT > WINHT
0x3
INSIDE
WINLT < RESULT < WINHT
0x4
OUTSIDE
RESULT < WINLT or RESULT > WINHT
Other
Reserved
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29.5.6
Sample Control
Name:
Offset:
Reset:
Property:
Bit
7
SAMPCTRL
0x5
0x00
-
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
SAMPLEN[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – SAMPLEN[4:0] Sample Length
These bits extend the ADC sampling length in several CLK_ADC cycles. By default, the sampling time is two
CLK_ADC cycles. Increasing the sampling length allows sampling sources with higher impedance. The total
conversion time increases with the selected sampling length.
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29.5.7
MUXPOS
Name:
Offset:
Reset:
Property:
Bit
7
MUXPOS
0x06
0x00
-
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
MUXPOS[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – MUXPOS[4:0] MUXPOS
This bit field selects which single-ended analog input is connected to the ADC. If these bits are changed during a
conversion, the change will not take effect until this conversion is complete.
MUXPOS
Name
Input
0x00-0x0F
0x10-0x1B
0x1C
0x1D
0x1E
0x1F
Other
AIN0-AIN15
DACREF0
TEMPSENSE
GND
-
ADC input pin 0 - 15
Reserved
DAC reference in AC0
Reserved
Temperature sensor
GND
Reserved
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29.5.8
Command
Name:
Offset:
Reset:
Property:
Bit
7
COMMAND
0x08
0x00
-
6
5
4
3
Access
Reset
2
1
0
STCONV
R/W
0
Bit 0 – STCONV Start Conversion
Writing a ‘1’ to this bit will start a single measurement. If in Free-Running mode, this will start the first conversion.
STCONV will read as ‘1’ as long as a conversion is in progress. When the conversion is complete, this bit is
automatically cleared.
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29.5.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x09
0x00
-
6
5
4
3
Access
Reset
2
1
0
STARTEI
R/W
0
Bit 0 – STARTEI Start Event Input
This bit enables using the event input as a trigger for starting a conversion.
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29.5.10 Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x0A
0x00
-
6
5
4
3
Access
Reset
2
1
WCMP
R/W
0
0
RESRDY
R/W
0
Bit 1 – WCMP Window Comparator Interrupt Enable
Writing a ‘1’ to this bit enables the window comparator interrupt.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a ‘1’ to this bit enables the result ready interrupt.
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29.5.11 Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x0B
0x00
-
6
5
4
3
Access
Reset
2
1
WCMP
R/W
0
0
RESRDY
R/W
0
Bit 1 – WCMP Window Comparator Interrupt Flag
This window comparator interrupt flag is set when the measurement is complete and if the result matches the
selected Window Comparator mode defined by WINCM (ADCn.CTRLE). The comparison is done at the end of the
conversion. The flag is cleared by either writing a ‘1’ to the bit position or by reading the Result (ADCn.RES) register.
Writing a ‘0’ to this bit has no effect.
Bit 0 – RESRDY Result Ready Interrupt Flag
The Result Ready interrupt flag is set when a measurement is complete, and a new result is ready. The flag is
cleared by either writing a ‘1’ to the bit location or by reading the Result (ADCn.RES) register. Writing a ‘0’ to this bit
has no effect.
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29.5.12 Debug Run
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0C
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
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29.5.13 Temporary
Name:
Offset:
Reset:
Property:
TEMP
0x0D
0x00
-
The Temporary register is used by the CPU for 16-bit single-cycle access to the 16-bit registers of this peripheral. The
register is common for all the 16-bit registers of this peripheral and can be read and written by software. For more
details on reading and writing 16-bit registers, refer to Accessing 16-Bit Registers.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary
Temporary register for read/write operations in 16-bit registers.
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29.5.14 Result
Name:
Offset:
Reset:
Property:
RES
0x10
0x00
-
The ADCn.RESL and ADCn.RESH register pair represents the 16-bit value, ADCn.RES. The low byte [7:0] (suffix L)
is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
If the analog input is higher than the reference level of the ADC, the 10-bit ADC result will be equal the maximum
value of 0x3FF. Likewise, if the input is below 0V, the ADC result will be 0x000. As the ADC cannot produce a
result above 0x3FF values, the accumulated value will never exceed 0xFFC0 even after the maximum allowed 64
accumulations.
Bit
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RES[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RES[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:8 – RES[15:8] Result high byte
These bits constitute the MSB of the ADCn.RES register, where the MSb is RES[15]. The ADC itself has a 10-bit
output, ADC[9:0], where the MSb is ADC[9]. The data format in ADC and Digital Accumulation is 1’s complement,
where 0x0000 represents the zero, and 0xFFFF represents the largest number (full scale).
Bits 7:0 – RES[7:0] Result low byte
These bits constitute the LSB of ADC/Accumulator Result, (ADCn.RES) register. The data format in ADC and Digital
Accumulation is 1’s complement, where 0x0000 represents the zero, and 0xFFFF represents the largest number (full
scale).
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29.5.15 Window Comparator Low Threshold
Name:
Offset:
Reset:
Property:
WINLT
0x12
0x00
-
This register is the 16-bit low threshold for the digital comparator monitoring the ADCn.RES register. The ADC itself
has a 10-bit output, RES[9:0], where the MSb is RES[9]. The data format in ADC and Digital Accumulation is 1’s
complement, where 0x0000 represents the zero, and 0xFFFF represents the largest number (full scale).
The ADCn.WINLTH and ADCn.WINLTL register pair represents the 16-bit value, ADCn.WINLT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
When accumulating samples, the window comparator thresholds are applied to the accumulated value and not on
each sample.
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINLT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – WINLT[15:8] Window Comparator Low Threshold High Byte
These bits hold the MSB of the 16-bit register.
Bits 7:0 – WINLT[7:0] Window Comparator Low Threshold Low Byte
These bits hold the LSB of the 16-bit register.
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29.5.16 Window Comparator High Threshold
Name:
Offset:
Reset:
Property:
WINHT
0x14
0x00
-
This register is the 16-bit high threshold for the digital comparator monitoring the ADCn.RES register. The ADC itself
has a 10-bit output, RES[9:0], where the MSb is RES[9]. The data format in ADC and Digital Accumulation is 1’s
complement, where 0x0000 represents the zero, and 0xFFFF represents the largest number (full scale).
The ADCn.WINHTH and ADCn.WINHTL register pair represents the 16-bit value, ADCn.WINHT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINHT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINHT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – WINHT[15:8] Window Comparator High Threshold High Byte
These bits hold the MSB of the 16-bit register.
Bits 7:0 – WINHT[7:0] Window Comparator High Threshold Low Byte
These bits hold the LSB of the 16-bit register.
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29.5.17 Calibration
Name:
Offset:
Reset:
Property:
Bit
7
CALIB
0x16
0x01
-
6
5
4
3
Access
Reset
2
1
0
DUTYCYC
R/W
1
Bit 0 – DUTYCYC Duty Cycle
This bit determines the duty cycle of the ADC clock.
Value
Description
0
50% Duty Cycle
1
25% Duty Cycle
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UPDI - Unified Program and Debug Interface
30.
UPDI - Unified Program and Debug Interface
30.1
Features
•
•
•
30.2
Programming:
– External programming through UPDI one-wire (1W) interface
• Uses a dedicated pin of the device for programming
• No GPIO pins occupied during operation
• Asynchronous Half-Duplex UART protocol towards the programmer with the programming time up to
0.9 Mbps.
Debugging:
– Memory mapped access to device address space (NVM, RAM, I/O)
– No limitation on device clock frequency
– Unlimited number of user program breakpoints
– Two hardware breakpoints
– Run-time readout of CPU Program Counter (PC), Stack Pointer (SP), and Status register (SREG) for code
profiling
– Program flow control
• Go, Stop, Reset, Step Into
– Non-intrusive run-time chip monitoring without accessing system registers
• Monitor CRC status and sleep status
Unified Programming and Debug Interface (UPDI):
– Built-in error detection with error signature readout
– Frequency measurement of internal oscillators using the Event System
Overview
The Unified Program and Debug Interface (UPDI) is a proprietary interface for external programming and on-chip
debugging of a device.
The UPDI supports programming of nonvolatile memory (NVM) space; FLASH, EEPROM, fuses, lockbits, and the
user row. In addition, the UPDI can access the entire I/O and data space of the device. See the NVM controller
documentation for programming via the NVM controller and executing NVM controller commands.
Programming and debugging are done through the UPDI Physical interface (UPDI PHY), which is a one-wire UARTbased half duplex interface using a dedicated pin for data reception and transmission. Clocking of UPDI PHY is done
by the internal oscillator. The UPDI access layer grants access to the bus matrix, with memory mapped access to
system blocks such as memories, NVM, and peripherals.
The Asynchronous System Interface (ASI) provides direct interface access to On-Chip Debugging (OCD), NVM, and
System Management features. This gives the debugger direct access to system information, without requesting bus
access.
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UPDI - Unified Program and Debug Interface
30.2.1
Block Diagram
Figure 30-1. UPDI Block Diagram
ASI
Memories
UPDI Pin
(RX/TX Data)
UPDI
Physical
layer
UPDI
Access
layer
Bus Matrix
UPDI Controller
NVM
Peripherals
ASI Access
30.2.2
OCD
NVM
Controller
System
Management
ASI Internal Interfaces
Clocks
The PHY layer and the ACC layer can operate on different clock domains. The PHY layer clock is derived from the
dedicated internal oscillator, and the ACC layer clock is the same as the peripheral clock. There is a synchronization
boundary between the PHY and the ACC layer, which ensures correct operation between the clock domains. The
UPDI clock output frequency is selected through the ASI, and the default UPDI clock start-up frequency is 4 MHz
after enabling or resetting the UPDI. The UPDI clock frequency can be changed by writing to the UPDI Clock Divider
Select (UPDICLKSEL) bit field in the ASI Control A (UPDI.ASI_CTRLA) register.
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UPDI - Unified Program and Debug Interface
Figure 30-2. UPDI Clock Domains
ASI
SYNCH
UPDI Controller
UPDI
Physical
layer
Clock
Controller
30.3
30.3.1
Clock
Controller
CLK_UPDI
CLK_UPDI
source
~
UPDI
Access
layer
CLK_PER
CLK_PER
UPDICLKSEL
~
Functional Description
Principle of Operation
Communication through the UPDI is based on standard UART communication, using a fixed frame format, and
automatic baud rate detection for clock and data recovery. In addition to the data frame, there are several control
frames which are important to the communication. The supported frame formats are presented in Figure 30-3.
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Figure 30-3. Supported UPDI Frame Formats
DATA
St
0
1
2
3
4
5
6
7
P
S1 S2
P
S1 S2
P
S1 S2
IDLE
BREAK
SYNCH (0x55)
St
Synch Part
End_synch
ACK (0x40)
St
Data
Frame
IDLE
Frame
BREAK
SYNCH
ACK
Data frame consists of one Start bit (always low), eight data bits, one parity bit (even parity), and two
Stop bits (always high). If the Parity bit, or Stop bits have an incorrect value, an error will be detected and
signalized by the UPDI. The parity bit-check in the UPDI can be disabled by writing the Parity Disable
(PARD) bit in UPDI.CTRLA, in which case the parity generation from the debugger can be ignored.
Special frame that consists of 12 high bits. This is the same as keeping the transmission line in an Idle
state.
Special frame that consists of 12 low bits. The BREAK frame is used to reset the UPDI back to its default
state and is typically used for error recovery.
The SYNCH frame (0x55) is used by the Baud Rate Generator to set the baud rate for the coming
transmission. A SYNCH character is always expected by the UPDI in front of every new instruction, and
after a successful BREAK has been transmitted.
The Acknowledge (ACK) character is transmitted from the UPDI whenever an ST or STS instruction
has successfully crossed the synchronization boundary and have gained bus access. When an ACK is
received by the debugger, the next transmission can start.
30.3.1.1 UPDI UART
All transmission and reception of serial data on the UPDI is achieved using the UPDI frames presented in Figure
30-3. Communication is initiated from the debugger/programmer side, and every transmission must start with a
SYNCH character upon which the UPDI can recover the transmission baud rate, and store this setting for the coming
data. The baud rate set by the SYNCH character will be used for both reception and transmission for the instruction
byte received after the SYNCH. See 30.3.3 UPDI Instruction Set for details on when the next SYNCH character is
expected in the instruction stream.
There is no writable baud rate register in the UPDI, so the baud rate sampled from the SYNCH character is used for
data recovery by sampling the Start bit, and performing a majority vote on the middle samples.
The transmission baud rate of the PDI PHY is related to the selected UPDI clock, which can be adjusted by UPDI
Clock Select (UPDICLKSEL) bit in UPDI.ASI_CTRLA. See Table 30-1 for recommended maximum and minimum
baud rate settings. The receive and transmit baud rates are always the same within the accuracy of the auto-baud.
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UPDI - Unified Program and Debug Interface
Table 30-1. Recommended UART Baud Rate Based on UPDICLKSEL Setting
UPDICLKSEL[1:0]
Max. Recommended Baud Rate
Min. Recommended Baud Rate
0x1 (16 MHz)
0.9 Mbps
0.300 kbps
0x2 (8 MHz)
450 kbps
0.150 kbps
0x3 (4 MHz) - Default
225 kbps
0.075 kbps
The UPDI Baud Rate Generator utilizes fractional baud counting to minimize the transmission error. With the fixed
frame format used by the UPDI, the maximum and recommended receiver transmission error limits can be seen in
the following table:
Table 30-2. Receiver Baud Rate Error
Data + Parity Bits
Rslow
Rfast
Max. Total Error [%]
Recommended Max. RX Error [%]
9
96.39
104.76
+4.76/-3.61
+1.5/-1.5
30.3.1.2 BREAK Character
The BREAK character is used to reset the internal state of the UPDI to the default setting. This is useful if the UPDI
enters an error state due to a communication error, or when the synchronization between the debugger and the UPDI
is lost.
To ensure that a BREAK is successfully received by the UPDI in all cases, the debugger should send two
consecutive BREAK characters. If a single BREAK is sent while the UPDI is receiving or transmitting (possibly at
a very low baud rate), the UPDI will not detect it. However, this will cause a frame error (RX) or contention error (TX),
and abort the ongoing operation. Then, the UPDI will detect the next BREAK. The first BREAK will be detected if the
UPDI is idle.
No SYNCH character is required before the BREAK because the BREAK is used to reset the UPDI from any state.
This means that the UPDI will sample the BREAK with the last baud rate setting and be derived from the last valid
SYNCH character. If the communication error was caused by an incorrect sampling of the SYNCH character, the
device will not know the baud rate. To ensure that the BREAK will be detected in all cases, the recommended BREAK
duration should be 12-bit times the bit duration at the lowest possible baud rate (8192 times the CLK_PER) as shown
in Table 30-3).
Table 30-3. Recommended BREAK Character Duration
UPDICLKSEL[1:0]
Recommended BREAK Character Duration
0x1 (16 MHz)
6.15 ms
0x2 (8 MHz)
12.30 ms
0x3 (4 MHz) - Default
24.60 ms
30.3.1.3 SYNCH Character
The SYNCH character has eight bits and follows the regular UPDI frame format. It has a fixed value of 0x55. The
SYNCH character has two main purposes:
1. It acts as the enabling character for the UPDI after a disable.
2. It is used by the Baud Rate Generator to set the baud rate for the subsequent transmission. If an invalid
SYNCH character is sent, the next transmission will not be sampled correctly.
30.3.1.3.1 SYNCH in One-Wire Mode
The SYNCH character is used before each new instruction. When using the REPEAT instruction, the SYNCH
character is expected only before the first instruction after REPEAT.
The SYNCH is a known character which, through its property of toggling for each bit, allows the UPDI to measure
how many UPDI clock cycles are needed to sample the 8-bit SYNCH pattern. The information obtained through the
sampling is used to provide Asynchronous Clock Recovery and Asynchronous Data Recovery on reception, and to
keep the baud rate of the connected programmer when doing transmit operations.
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UPDI - Unified Program and Debug Interface
30.3.2
Operation
The UPDI must be enabled before the UART communication can start.
30.3.2.1 UPDI Enable
The dedicated UPDI pad is configured as an input with pull-up.When the pull-up is detected by a connected
debugger, the UPDI enable sequence, as depicted below, is started.
Figure 30-4. UPDI Enable Sequence
1
Drive low from debugger to request UPDI clock
2
UPDI clock ready; Communication channel ready.
1
UPDIPAD
St
D0
D1
D2
UPDI.txd
D4
D5
D6
D7
Sp
SYNC (0x55)
(Autobaud)
Handshake / BREAK
t RES
UPDI.rxd
D3
(Ignore)
2
Hi-Z
Hi-Z
UPDI.txd = 0
t UPDI
debugger.
UPDI.txd
Hi-Z
Hi-Z
Debugger.txd = 0
t Deb0
Debugger.txd = z.
t DebZ
Table 30-4. Timing in the Figure
Timing Label
Max.
Min.
tRES
200 µs
10 µs
tUPDI
200 µs
10 µs
tDeb0
1 µs
200 ns
tDebZ
14 ms
200 µs
When the pull-up is detected, the debugger initiates the enable sequence by driving the line low for a duration of
tDeb0.
The negative edge is detected by the UPDI, which starts the UPDI clock. The UPDI will continue to drive the line low
until the clock is stable and ready for the UPDI to use. The duration of tUPDI will vary, depending on the status of the
oscillator when the UPDI is enabled. After this duration, the data line will be released by the UPDI and pulled high.
When the debugger detects that the line is high, the initial SYNCH character (0x55) must be transmitted to
synchronize the UPDI communication data rate. If the Start bit of the SYNCH character is not sent within maximum
tDebZ, the UPDI will disable itself, and the UPDI enabling sequence must be re-initiated. The UPDI is disabled if the
timing is violated to avoid the UPDI being enabled unintentionally.
After successful SYNCH character transmission, the first instruction frame can be transmitted.
30.3.2.2 UPDI Disable
Any programming or debug session should be terminated by writing the UPDI Disable (UPDIDIS) bit in UPDI.CTRLB.
Writing this bit will reset the UPDI including any decoded KEYs (see 30.3.7 Enabling of Key Protected Interfaces)
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and disable the oscillator request for the module. If the disable operation is not performed, the UPDI and the
oscillators request will remain enabled. This causes power consumption increased for the application.
During the enable sequence the UPDI can disable itself in case of a faulty enable sequence. There are two cases
that will cause an automatic disable:
• A SYNCH character is not sent within 13.5 ms after the initial enable pulse described in 30.3.2.1 UPDI Enable.
• The first SYNCH character after an initiated enable is too short or too long to be detected as a valid SYNCH
character. See Table 30-1 for recommended baud rate operating ranges.
30.3.2.3 UPDI Communication Error Handling
The UPDI contains a comprehensive error detection system that provides information to the debugger when
recovering from an error scenario. The error detection consists of detecting physical transmission errors like parity
error, contention error, and frame error, to more high-level errors like access time-out error. See the UPDI Error
Signature (PESIG) bit field in the Status B (UPDI.STATUSB) register for an overview of the available error signatures.
Whenever the UPDI detects an error, it will immediately enter an internal Error state to avoid unwanted system
communication. In the Error state, the UPDI will ignore all incoming data requests, except when a BREAK character
is received. The following procedure must always be applied when recovering from an Error condition.
1. Send a BREAK character. See section BREAK Character for recommended BREAK character handling.
2. Send a SYNCH character at the desired baud rate for the next data transfer.
3. Execute a Load Control Status (LDCS) instruction to read the UPDI Error Signature (PESIG) bit field in the
Status B (UPDI.STATUSB) register and get the information about the occurred error.
4. The UPDI has now recovered from the Error state and is ready to receive the next SYNCH character and
instruction.
30.3.2.4 Direction Change
To ensure correct timing for a half-duplex UART operation, the UPDI has a built-in guard time mechanism to relax the
timing when changing direction from RX to TX mode. The guard time is represented by Idle bits inserted before the
next Start bit of the first response byte is transmitted. The number of Idle bits can be configured through the Guard
Time Value (GTVAL) bit field in the Control A (UPDI.CTRLA) register. The duration of each Idle bit is given by the
baud rate used by the current transmission.
Figure 30-5. UPDI Direction Change by Inserting Idle Bits
RX Data Frame
St
RX Data Frame
Dir Change
P
Data from
debugger to UPDI
S1
S2
IDLE bits
TX Data Frame
St
G uard Tim e #
IDLE bits inserted
TX Data Frame
P
S1
S2
Data from UPDI to
debugger
The UPDI guard time is the minimum Idle time that the connected debugger will experience when waiting for data
from the UPDI. The maximum Idle time is the same as time-out. The Idle time before a transmission will be more than
the expected guard time when the synchronization time plus the data bus accessing time is longer than the guard
time.
It is recommended to always use the insertion of minimum two Guard Time bits on the UPDI side, and one guard time
cycle insertion from the debugger side.
30.3.3
UPDI Instruction Set
The communication through the UPDI is based on a small instruction set. These instructions are part of the UPDI
Data Link (DL) layer. The instructions are used to access the UPDI registers, since they are mapped into an internal
memory space called “ASI Control and Status (CS) space”, as well as the memory-mapped system space. All
instructions are byte instructions and must be preceded by a SYNCH character to determine the baud rate for
the communication. See section UPDI UART for information about setting the baud rate for the transmission. The
following figure gives an overview of the UPDI instruction set.
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Figure 30-6. UPDI Instruction Set Overview
Opcode
LDS
STS
0
0
0
1
Size A
0
0
0
0
Opcode
LD
ST
0
0
0
1
Ptr
1
1
Size B
Size A/B
0
STCS
1
1
0
1
0
0
0
0
0
LDS
0
0
1
LD
0
1
0
STS
0
1
1
ST
1
0
0
LDCS (LDS Control/Status)
1
0
1
REPEAT
1
1
0
STCS (STS Control/Status)
1
1
1
KEY
Size A - Address Size
0
CS Address
LDCS
OPCODE
0
0
Byte - can address 0-255 B
0
1
Word (2 Bytes) - for memories up to 64 KB in size
1
0
3 Bytes - for memories above 64 KB in size
1
1
Reserved
Ptr - Pointer Access
0
0
0
0
* (ptr)
0
1
* (ptr++)
1
0
ptr
1
1
Reserved
Size B - Data Size
Size B
REPEAT
1
0
1
0
0
0
SIB
KEY
1
1
1
0
Size C
0
0
0
Byte
0
1
Word (2 Bytes)
1
0
Reserved
1
1
Reserved
CS Address (CS - Control/Status reg.)
Size C - Key Size
0
0
64 bits (8 Bytes)
0
1
128 bits (16 Bytes)
1
0
Reserved
1
1
Reserved
SIB - System Information Block Sel.
0
Receive KEY
1
Send SIB
30.3.3.1 LDS - Load Data from Data Space Using Direct Addressing
The LDS instruction is used to load data from the system bus into the PHY layer shift register for serial readout. The
LDS instruction is based on direct addressing, and the address must be given as an operand to the instruction for the
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data transfer to start. The maximum supported size for the address and data is 32 bits. The LDS instruction supports
repeated memory access when combined with the REPEAT instruction.
After issuing the LDS instruction, the number of desired address bytes, as indicated by the Size A field followed
by the output data size, which is selected by the Size B field, must be transmitted. The output data is issued after
the specified Guard Time (GT). When combined with the REPEAT instruction, the address must be sent in for each
iteration of the repeat, meaning after each time the output data sampling is done. There is no automatic address
increment when using REPEAT with LDS, as it uses a direct addressing protocol.
Figure 30-7. LDS Instruction Operation
OPCODE
Size A
Size B
Size A - Address Size
0
LDS
0
0
0
0
0
0
1
Word (2 Bytes) - for memories up to 64 KB in size
1
0
3 Bytes - for memories above 64 KB in size
1
1
Reserved
1 Byte - can address 0-255 B
Size B - Data Size
0
0
1 Byte
0
1
Word (2 Bytes)
1
0
Reserved
1
1
Reserved
ADDRESS_SIZE
Synch
(0x55)
LDS
Adr_0
RX
Adr_n
Data_0
Data_n
TX
ΔGT
When the instruction is decoded, and the address byte(s) are received as dictated by the decoded instruction, the DL
layer will synchronize all required information to the ACC layer, which will handle the bus request and synchronize
data buffered from the bus back again to the DL layer. This will create a synchronization delay that must be taken into
consideration upon receiving the data from the UPDI.
30.3.3.2 STS - Store Data to Data Space Using Direct Addressing
The STS instruction is used to store data that are shifted serially into the PHY layer shift register to the system bus
address space. The STS instruction is based on direct addressing, and the address must be given as an operand to
the instruction for the data transfer to start. The address is the first set of operands, and data are the second set. The
size of the address and data operands are given by the size fields presented in Figure 30-8. The maximum size for
both address and data is 32 bits.
The STS supports repeated memory access when combined with the REPEAT instruction.
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UPDI - Unified Program and Debug Interface
Figure 30-8. STS Instruction Operation
OPCODE
0
STS
1
Size A
0
Size B
Size A - Address Size
0
0
0
1 Byte - can address 0-255 B
0
1
Word (2 Bytes) - for memories up to 64 KB in size
1
0
3 Bytes - for memories above 64 KB in size
1
1
Reserved
Size B - Data Size
0
0
1 Byte
0
1
Word (2 Bytes)
1
0
Reserved
1
1
Reserved
ADDRESS_SIZE
Synch
(0x55)
STS
Adr_0
DATA_SIZE
Adr_n
Data_0
RX
Data_n
ACK
ΔGT
ACK
TX
ΔGT
The transfer protocol for an STS instruction is depicted in Figure 30-8, following this sequence:
1.
2.
3.
The address is sent.
An Acknowledge (ACK) is sent back from the UPDI if the transfer was successful.
The number of bytes, as specified in the STS instruction, is sent.
4.
A new ACK is received after the data have been successfully transferred.
30.3.3.3 LD - Load Data from Data Space Using Indirect Addressing
The LD instruction is used to load data from the data space and into the PHY layer shift register for serial readout.
The LD instruction is based on indirect addressing, which means that the Address Pointer in the UPDI needs to be
written before the data space read access. Automatic pointer post-increment operation is supported and is useful
when the LD instruction is utilized with the REPEAT instruction. It is also possible to do an LD from the UPDI Pointer
register. The maximum supported size for address and data load is 32 bits.
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Figure 30-9. LD Instruction Operation
OPCODE
LD
0
0
Ptr
1
Size A/B
Ptr - Pointer Access
0
Size A - Address Size
Synch
(0x55)
0
0
* ( ptr)
0
1
* (ptr++)
1
0
ptr
1
1
Reserved
Size B - Data Size
0
0
Byte - can address 0-255 B
0
0
Byte
0
1
Word (2 Bytes) - for memories up to 64 KB in size
0
1
Word (2 Bytes)
1
0
3 Bytes - for memories above 64 KB in size
1
0
Reserved
1
1
Reserved
1
1
Reserved
LD
DATA_SIZE
Data_0
RX
Data_n
TX
ΔGT
The figure above shows an example of a typical LD sequence, where the data are received after the Guard Time
(GT) period. Loading data from the UPDI Pointer register follows the same transmission protocol.
For the LD instruction from the data space, the pointer register must be set up by using an ST instruction to the
UPDI Pointer register. After the ACK has been received on a successful Pointer register write, the LD instruction must
be set up with the desired DATA SIZE operands. An LD to the UPDI Pointer register is done directly with the LD
instruction.
30.3.3.4 ST - Store Data from UPDI to Data Space Using Indirect Addressing
The ST instruction is used to store data from the UPDI PHY shift register to the data space. The ST instruction is
used to store data that are shifted serially into the PHY layer. The ST instruction is based on indirect addressing,
which means that the Address Pointer in the UPDI needs to be written before the data space. The automatic pointer
post-increment operation is supported and is useful when the ST instruction is utilized with the REPEAT instruction.
The ST instruction is also used to store the UPDI Address Pointer into the Pointer register. The maximum supported
size for storing address and data is 32 bits.
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Figure 30-10. ST Instruction Operation
OPCODE
ST
0
1
Ptr
1
Size A/B
Ptr - Pointer Access
0
0
0
* ( ptr)
0
1
* ( ptr++)
1
0
ptr
1
1
Reserved
Size A - Address Size
Size B - Data Size
0
0
Byte - can address 0-255 B
0
0
1 Byte
0
1
Word (2 Bytes) - for memories up to 64 KB in size
0
1
Word (2 Bytes)
1
0
3 Bytes - for memories above 64 KB in size
1
0
Reserved
1
1
Reserved
1
1
Reserved
ADDRESS_SIZE
Synch
(0x55)
ST
ADR_0
ADR_n
RX
ACK
TX
ΔGT
BLOCK_SIZE
Synch
(0x55)
ST
Data_0
RX
Data_n
ACK
TX
ΔGT
The figure above gives an example of an ST instruction to the UPDI Pointer register and the storage of regular data.
A SYNCH character is sent before each instruction. In both cases, an Acknowledge (ACK) is sent back by the UPDI if
the ST instruction was successful.
To write the UPDI Pointer register, the following procedure has to be followed:
1. Set the PTR field in the ST instruction to signature 0x2.
2.
3.
Set the address size (Size A) field to the desired address size.
After issuing the ST instruction, send Size A bytes of address data.
4.
Wait for the ACK character, which signifies a successful write to the Address register.
After the Address register is written, sending data is done in a similarly:
1. Set the PTR field in the ST instruction to signature 0x0 to write to the address specified by the UPDI Pointer
register. If the PTR field is set to 0x1, the UPDI pointer is automatically updated to the next address according
to the data size Size B field of the instruction after the write is executed.
2. Set the Size B field in the instruction to the desired data size.
3. After sending the ST instruction, send Size B bytes of data.
4.
Wait for the ACK character, which signifies a successful write to the bus matrix.
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When used with the REPEAT instruction, it is recommended to set up the Address register with the start address
for the block to be written and use the Pointer Post Increment register to automatically increase the address for
each repeat cycle. When using the REPEAT instruction, the data frame of Size B data bytes can be sent after each
received ACK.
30.3.3.5 LDCS - Load Data from Control and Status Register Space
The LDCS instruction is used to load serial readout data from the UPDI Control and the Status register space located
in the DL layer into the PHY layer shift register. The LDCS instruction is based on direct addressing, where the
address is part of the instruction operands. The LDCS instruction can access only the UPDI CS register space. This
instruction supports only byte access, and the data size is not configurable.
Figure 30-11. LDCS Instruction Operation
OPCODE
LDCS
1
0
CS Address
0
CS Address ( CS - Control/Status reg.)
0
Synch
(0x55)
LDCS
RX
Data
TX
Δgt
Figure 30-11 shows a typical example of LDCS data transmission. A data byte from the LDCS is transmitted from the
UPDI after the guard time is completed.
30.3.3.6 STCS - Store Data to Control and Status Register Space
The STCS instruction is used to store data to the UPDI Control and Status register space. Data are shifted in serially
into the PHY layer shift register and written as a whole byte to a selected CS register. The STCS instruction is based
on direct addressing, where the address is part of the instruction operand. The STCS instruction can access only the
internal UPDI register space. This instruction supports only byte access, and the data size is not configurable.
Figure 30-12. STCS Instruction Operation
OPCODE
STCS
1
1
CS Address
0
CS Address ( CS - Control/Status reg.)
0
Synch
(0x55)
STCS
Data
RX
TX
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Figure 30-12 shows the data frame transmitted after the SYNCH character and the instruction frames. The STCS
instruction byte can be immediately followed by the data byte. There is no response generated from the STCS
instruction, as is the case for the ST and STS instructions.
30.3.3.7 REPEAT - Set Instruction Repeat Counter
The REPEAT instruction is used to store the repeat count value into the UPDI Repeat Counter register on the DL
layer. When instructions are used with REPEAT, the protocol overhead for SYNCH and instruction frame can be
omitted on all instructions except the first instruction after the REPEAT is issued. REPEAT is most useful for memory
instructions (LD, ST, LDS, STS), but all instructions can be repeated, except for the REPEAT instruction itself.
The DATA_SIZE operand field refers to the size of the repeat value. Only up to 255 repeats are supported. The
instruction loaded directly after the REPEAT instruction will be issued for RPT_0 + 1 times. If the Repeat Counter
register is ‘0’, the instruction will run just once. An ongoing repeat can be aborted only by sending a BREAK
character.
Figure 30-13. REPEAT Instruction Operation used with ST Instruction
OPCODE
REPEAT
1
0
Size B
1
0
0
0
Size B - Data Size
0
0
1 Byte
0
1
Word (2 Bytes)
1
0
Reserved
1
1
Reserved
REPEAT_SIZE
Synch
(0x55)
REPEAT
RPT_0
Repeat Number of Blocks of DATA_SIZE
DATA_SIZE
Synch
(0x55)
ST
(ptr++)
Data_0
Data_n
DATA_SIZE
DATA_SIZE
DataB_1
DataB_n
RX
ACK
Δd
ACK
Δd
Δd
Δd
TX
Δd
Figure 30-13 gives an example of a repeat operation with an ST instruction using pointer post-increment operation.
After the REPEAT instruction is sent with RPT_0 = n, the first ST instruction is issued with SYNCH and instruction
frame, while the next n ST instructions are executed by only sending data bytes according to the ST operand
DATA_SIZE, and maintaining the Acknowledge (ACK) handshake protocol.
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Figure 30-14. REPEAT used with LD Instruction
REPEAT_SIZE
Synch
(0x55)
Synch
(0x55)
RPT_0
REPEAT
RPT_1
LD
(ptr++)
RX
Repeat Number of Blocks of DATA_SIZE
DATA_SIZE
DATA_SIZE
DataB_1
DataB_n
TX
ΔGT
For LD, data will come out continuously after the LD instruction. Note the guard time on the first data block.
If using indirect addressing instructions (LD/ST), it is recommended to always use the pointer post-increment option
when combined with REPEAT. The ST/LD instruction is necessary only before the first data block (number of data
bytes determined by DATA_SIZE). Otherwise, the same address will be accessed in all repeated access operations.
For direct addressing instructions (LDS/STS), the address must always be transmitted as specified in the instruction
protocol, before data can be received (LDS) or sent (STS).
30.3.3.8 KEY - Set Activation Key or Send System Information Block
The KEY instruction is used for communicating key bytes to the UPDI or for providing the programmer with a System
Information Block (SIB), opening up for executing protected features on the device. See Key Activation Overview for
an overview of functions that are activated by keys. For the KEY instruction, only a 64-bit key size is supported. The
maximum supported size for SIB is 128 bits.
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Figure 30-15. KEY Instruction Operation
SIB
KEY
1
1
1
0
Size C
0
Size C - Key Size
0
0
0
1 128 bits (16 Bytes) (SIB only)
64 bits (8 Bytes)
1
0
Reserved
1
1
Reserved
SIB - System Information Block Sel.
0
Send KEY
1
Receive SIB
KEY_SIZE
Synch
(0x55)
KEY
KEY_0
KEY_n
RX
TX
Synch
(0x55)
RX
KEY
SIB_0
Δgt
SIB_n
TX
SIB_SIZE
Figure 30-15 shows the transmission of a key and the reception of a SIB. In both cases, the Size C (SIZE_C) field
in the operand determines the number of frames being sent or received. There is no response after sending a KEY
to the UPDI. When requesting the SIB, data will be transmitted from the UPDI according to the current guard time
setting.
30.3.4
System Clock Measurement with UPDI
It is possible to use the UPDI to get an accurate measurement of the system clock frequency by utilizing the UPDI
event connected to TCB with Input Capture capabilities. A recommended setup flow for this feature is given by the
following steps:
• Set up TCBn.CTRLB with setting CNTMODE = 0x3, Input Capture Frequency Measurement mode
•
Write CAPTEI = 1 in TCBn.EVCTRL to enable Event Interrupt. Keep EDGE = 0 in TCBn.EVCTRL
•
•
Configure the Event System to route the UPDI SYNCH event (generator) to the TCB (user)
For the SYNCH character used to generate the UPDI events, it is recommended to use a slow baud rate in
the range of 10-50 kbps to get a more accurate measurement of the value captured by the timer between each
UPDI event. One particular thing is that if the capture is set up to trigger an interrupt, the first captured value
must be ignored. The second captured value based on the input event must be used for the measurement. See
Figure 30-16 for an example using 10 kbps UPDI SYNCH character pulses, giving a capture window of 200 µs
for the timer.
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•
It is possible to read out the captured value directly after the SYNCH character by reading the TCBn.CCMP
register, or the value can be written to memory by the CPU once the capture is done. For more details, refer to
the TCB - 16-bit Timer/Counter Type B section.
Figure 30-16. UPDI System Clock Measurement Events
Ignore the first
capture event
200 μs
UPDI_Input
TCB_CCMP
30.3.5
CAPT_1
CAPT_2
CAPT_3
Interbyte Delay
When loading data with the UPDI, or reading out the System Information Block, the output data will normally come
out with two IDLE bits between each transmitted byte for a multibyte transfer. Depending on the application on the
receiver side, data might be coming out too fast when there are no extra IDLE bits between each byte. By enabling
the IBDLY feature in UPDI.CTRLB, two extra Stop bits will be inserted between each byte to relax the sampling time
for the debugger. Interbyte delay works in the same way as a guard time, by inserting extra IDLE bits, but only a fixed
number of IDLE bits and only for multibyte transfers. The first transmitted byte after a direction change will be subject
to the regular Guard Time before it is transmitted, and the interbyte delay is not added to this time.
Figure 30-17. Interbyte Delay Example with LD and RPT
Too fast transm ission, no interbyte delay
RX
Debugger
Data
TX
RPT
CNT
LD*(ptr)
S
D0
GT
Debugger
Processing
B
D1
S
B
D1lots
D0
D2
S
B
D3
S
B
D4
D1lost
D2
S
B
D5
S
B
D4
Data sam pling ok with interbyte delay
RX
Debugger
Data
TX
RPT
CNT
Debugger
Processing
LD*(ptr)
GT
S IB
B
D0
D0
S IB
B
D1
D1
D2
D2
S IB
B
D3
S
B
D3
In Figure 30-17, GT denotes the Guard Time insertion, SB is for Stop Bit and IB is the inserted interbyte delay. The
rest of the frames are data and instructions.
30.3.6
System Information Block
The System Information Block (SIB) can be read out at any time by setting the SIB bit according to the KEY
instruction from 30.3.3.8 KEY - Set Activation Key or Send System Information Block. The SIB is always accessible
to the debugger, regardless of lock bit settings, and provides a compact form of supplying information about the
device and system parameters for the debugger. The information is vital in identifying and setting up the proper
communication channel with the device. The output of the SIB is interpreted as ASCII symbols. The key size field
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must be set to 16 bytes when reading out the complete SIB, and an 8-byte size can be used to read out only the
Family_ID. See Figure 30-18 for SIB format description and which data are available at different readout sizes.
Figure 30-18. System Information Block Format
16 8
30.3.7
[Byte][Bits]
[6:0] [55:0]
[7][7:0]
[10:8][23:0]
[13:11][23:0]
[14][7:0]
[15][7:0]
Field Name
Family_ID
Reserved
NVM_VERSION
OCD_VERSION
RESERVED
DBG_OSC_FREQ
Enabling of Key Protected Interfaces
The access to some internal interfaces and features is protected by the UPDI key mechanism. To activate a key, the
correct key data must be transmitted by using the KEY instruction, as described in 30.3.3.8 KEY - Set Activation Key
or Send System Information Block. Table 30-5 describes the available keys and the condition required when doing
the operation with the key active.
Table 30-5. Key Activation Overview
Key Name
Description
Requirements for Operation
Chip Erase
Start NVM chip erase.
Clear lock bits
NVMPROG
Activate NVM
Programming
Lock bits cleared.
ASI_SYS_STATUS.NVMPROG set
USERROW-Write
Program the user row
on the locked device
Lock bits set.
Write to key Status bit/
ASI_SYS_STATUS.UROWPROG set UPDI Reset
-
Conditions for Key
Invalidation
UPDI Disable/UPDI Reset
Programming done/UPDI
Reset
Table 30-6 gives an overview of the available key signatures that must be shifted in to activate the interfaces.
Table 30-6. Key Activation Signatures
Key Name
Key Signature (LSB Written First)
Size
Chip Erase
0x4E564D4572617365
64 bits
NVMPROG
0x4E564D50726F6720
64 bits
USERROW-Write
0x4E564D5573267465
64 bits
30.3.7.1 Chip Erase
The following steps should be followed to issue a chip erase:
1. Enter the Chip Erase key by using the KEY instruction. See Table 30-6 for the CHIPERASE signature.
2.
3.
4.
5.
6.
Optional: Read the Chip Erase (CHIPERASE) bit in the ASI Key Status (UPDI.ASI_KEY_STATUS) register to
see that the key is successfully activated.
Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
Read the NVM Lock Status (LOCKSTATUS) bit from the ASI System Status (UPDI.ASI_SYS_STATUS)
register.
The chip erase is done when LOCKSTATUS bit is ‘0’. If the LOCKSTATUS bit is ‘1’, return to step 5.
After a successful Chip Erase, the Lockbits will be cleared, and the UPDI will have full access to the system. Until
Lockbits are cleared, the UPDI cannot access the system bus, and only CS-space operations can be performed.
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CAUTION
During chip erase, the BOD is forced in ON state by writing to the Active (ACTIVE) bit field from the
Control A (BOD.CTRLA) register and uses the BOD Level (LVL) bit field from the BOD Configuration
(FUSE.BODCFG) fuse and the BOD Level (LVL) bit field from the Control B (BOD.CTRLB) register. If
the supply voltage VDD is below that threshold level, the device is unavailable until VDD is increased
adequately. See the BOD section for more details.
30.3.7.2 NVM Programming
If the device is unlocked, it is possible to write directly to the NVM Controller or to the Flash memory using the UPDI.
This will lead to unpredictable code execution if the CPU is active during the NVM programming. To avoid this, the
following NVM Programming sequence has to be executed.
1.
2.
3.
4.
5.
6.
7.
Follow the chip erase procedure, as described in Chip Erase. If the part is already unlocked, this point can be
skipped.
Enter the NVMPROG key by using the KEY instruction. See Table 30-6 for the NVMPROG signature.
Optional: Read the NVM Programming Key Status (NVMPROG) bit from the ASI Key Status
(UPDI.KEY_STATUS) register to see if the key has been activated.
Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
Read the NVM Programming Key Status (NVMPROG) bit from the ASI System Status
(UPDI.ASI_SYS_STATUS) register.
NVM Programming can start when the NVMPROG bit is ‘1’. If the NVMPROG bit is ‘0’, return to step 6.
8.
9.
Write data to NVM through the UPDI.
Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
10. Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
11. Programming is complete.
30.3.7.3 User Row Programming
The User Row Programming feature allows programming new values to the user row (USERROW) on a locked
device. To program with this functionality enabled, the following sequence must be followed:
1.
2.
3.
4.
5.
6.
Enter the USERROW-Write key located in Table 30-6 by using the KEY instruction. See Table 30-6 for the
USERROW-Write signature.
Optional: Read the User Row Write Key Status (UROWWRITE) bit from the ASI Key Status
(UPDI.ASI_KEY_STATUS) register to see if the key has been activated.
Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
Read the Start User Row Programming (UROWPROG) bit from the ASI System Status
(UPDI.ASI_SYS_STATUS) register.
User Row Programming can start when the UROWPROG bit is ‘1’. If UROWPROG is ‘0’, return to step 5.
7.
The data to be written to the User Row must first be written to a buffer in the RAM. The writable area in the
RAM has a size of 32 bytes, and it is only possible to write user row data to the first 32 byte addresses of the
RAM. Addressing outside this memory range will result in a nonexecuted write. The data will map 1:1 with the
user row space when the data is copied into the user row upon completion of the Programming sequence.
8. When all user row data has been written to the RAM, write the User Row Programming Done (UROWDONE)
bit in the ASI System Control A (UPDI.ASI_SYS_CTRLA) register.
9. Read the Start User Row Programming (UROWPROG) bit from the ASI System Status
(UPDI.ASI_SYS_STATUS) register.
10. The User Row Programming is completed when UROWPROG bit is ‘0’. If UROWPROG bit is ‘1’, return to step
9.
11. Write to the User Row Write Key Status (UROWWRITE) bit in the ASI Key Status (UPDI.ASI_KEY_STATUS)
register.
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12. Write the signature to the Reset Request (RSTREQ) bit in the ASI Reset Request (UPDI.ASI_RESET_REQ)
register. This will issue a System Reset.
13. Write 0x00 to the ASI Reset Request (UPDI.ASI_RESET_REQ) register to clear the System Reset.
14. The User Row Programming is complete.
It is not possible to read back data from the RAM in this mode. Only writes to the first 32 bytes of the RAM are
allowed.
30.3.8
Events
The UPDI can generate the following events:
Table 30-7. Event Generators in UPDI
Generator Name
Module
Event
UPDI
SYNCH
Description
SYNCH
character
Event Type
Level
Generating
Clock
Domain
CLK_UPDI
Length of Event
SYNCH char on UPDI pin
synchronized to CLK_UPDI
This event is set on the UPDI clock for each detected positive edge in the SYNCH character, and it is not possible to
disable this event from the UPDI.
The UPDI has no event users.
Refer to the Event System section for more details regarding event types and Event System configuration.
30.3.9
Sleep Mode Operation
The UPDI PHY layer runs independently of all sleep modes, and the UPDI is always accessible for a connected
debugger independent of the device’s sleep state. If the system enters a sleep mode that turns the system clock off,
the UPDI will not be able to access the system bus and read memories and peripherals. When enabled, the UPDI will
request the system clock so that the UPDI always has contact with the rest of the device. Thus, the UPDI PHY layer
clock is unaffected by the sleep mode’s settings. By reading the System Domain in Sleep (INSLEEP) bit in the ASI
System Status (UPDI.ASI_SYS_STATUS) register, it is possible to monitor if the system domain is in a sleep mode.
It is possible to prevent the system clock from stopping when going into a sleep mode, by writing to the Request
System Clock (CLKREQ) bit in the ASI System Control A (UPDI.ASI_SYS_CTRLA) register. If this bit is set, the
system sleep mode state is emulated, and the UPDI can access the system bus and read the peripheral registers
even in the deepest sleep modes.
The CLKREQ bit is by default ‘1’ when the UPDI is enabled, which means that the default operation is keeping the
system clock in ON state during the sleep modes.
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30.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
...
0x06
0x07
0x07
0x08
0x09
STATUSA
STATUSB
CTRLA
CTRLB
7:0
7:0
7:0
7:0
ASI_KEY_STATUS
ASI_KEY_STATUS
ASI_RESET_REQ
ASI_CTRLA
7:0
7:0
7:0
7:0
0x0A
ASI_SYS_CTRLA
7:0
0x0B
0x0C
ASI_SYS_STATUS
ASI_CRC_STATUS
7:0
7:0
30.5
7
6
5
4
3
DTD
NACKDIS
RSD
CCDETDIS
2
1
0
UPDIREV[3:0]
IBDLY
PARD
PESIG[2:0]
GTVAL[2:0]
UPDIDIS
Reserved
UROWWRITE NVMPROG CHIPERASE
UROWWRITE NVMPROG CHIPERASE
RSTREQ[7:0]
RSTSYS
INSLEEP
UPDICLKSEL[1:0]
UROWWRITE
CLKREQ
_FINAL
NVMPROG UROWPROG
LOCKSTATUS
CRC_STATUS[2:0]
Register Description
These registers are readable only through the UPDI with special instructions and are NOT readable through the CPU.
Registers at offset addresses 0x0-0x3 are the UPDI Physical configuration registers.
Registers at offset addresses 0x4-0xC are the ASI level registers.
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30.5.1
Status A
Name:
Offset:
Reset:
Property:
Bit
7
STATUSA
0x00
0x30
-
6
5
4
R
1
R
1
3
2
1
0
UPDIREV[3:0]
Access
Reset
R
0
R
0
Bits 7:4 – UPDIREV[3:0] UPDI Revision
This bit field contains the revision of the current UPDI implementation.
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30.5.2
Status B
Name:
Offset:
Reset:
Property:
Bit
7
STATUSB
0x01
0x00
-
6
5
4
3
Access
Reset
2
R
0
1
PESIG[2:0]
R
0
0
R
0
Bits 2:0 – PESIG[2:0] UPDI Error Signature
This bit field describes the UPDI error signature and is set when an internal UPDI Error condition occurs. The PESIG
bit field is cleared on a read from the debugger.
Table 30-8. Valid Error Signatures
PESIG[2:0]
Error Type
Error Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
No error
Parity error
Frame error
Access Layer Time-Out Error
Clock Recovery error
Bus error
Contention error
No error detected (Default)
Wrong sampling of the Parity bit
Wrong sampling of the Stop bits
UPDI can get no data or response from the Access layer
Wrong sampling of the Start bit
Reserved
Address error or access privilege error
Signalize Driving Contention on the UPDI pin
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30.5.3
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
IBDLY
R/W
0
CTRLA
0x02
0x00
-
6
5
PARD
R/W
0
4
DTD
R/W
0
3
RSD
R/W
0
2
R/W
0
1
GTVAL[2:0]
R/W
0
0
R/W
0
Bit 7 – IBDLY Inter-Byte Delay Enable
Writing a ‘1’ to this bit enables a fixed-length inter-byte delay between each data byte transmitted from the UPDI
when doing multibyte LD(S). The fixed length is two IDLE bits.
Bit 5 – PARD Parity Disable
Writing a ‘1’ to this bit will disable the parity detection in the UPDI by ignoring the Parity bit. This feature is
recommended to be used only during testing.
Bit 4 – DTD Disable Time-Out Detection
Writing a ‘1’ to this bit will disable the time-out detection on the PHY layer, which requests a response from the ACC
layer within a specified time (65536 UPDI clock cycles).
Bit 3 – RSD Response Signature Disable
Writing a ‘1’ to this bit will disable any response signatures generated by the UPDI. This reduces the protocol
overhead to a minimum when writing large blocks of data to the NVM space. When accessing the system bus, the
UPDI may experience delays. If the delay is predictable, the response signature may be disabled. Otherwise, a loss
of data may occur.
Bits 2:0 – GTVAL[2:0] Guard Time Value
This bit field selects the guard time value that will be used by the UPDI when the transmission direction switches from
RX to TX.
Value
Description
0x0
UPDI guard time: 128 cycles (default)
0x1
UPDI guard time: 64 cycles
0x2
UPDI guard time: 32 cycles
0x3
UPDI guard time: 16 cycles
0x4
UPDI guard time: 8 cycles
0x5
UPDI guard time: 4 cycles
0x6
UPDI guard time: 2 cycles
0x7
Reserved
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UPDI - Unified Program and Debug Interface
30.5.4
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x03
0x00
-
6
Access
Reset
5
4
NACKDIS
R/W
0
3
CCDETDIS
R/W
0
2
UPDIDIS
R/W
0
1
0
Bit 4 – NACKDIS Disable NACK Response
Writing a ‘1’ to this bit disables the NACK signature sent by the UPDI when a System Reset is issued during ongoing
LD(S) and ST(S) operations.
Bit 3 – CCDETDIS Collision and Contention Detection Disable
Writing a ‘1’ to this bit disables the contention detection. Writing a ‘0’ to this bit enables the contention detection.
Bit 2 – UPDIDIS UPDI Disable
Writing a ‘1’ to this bit disables the UPDI PHY interface. The clock request from the UPDI is lowered, and the UPDI is
reset. All the UPDI PHY configurations and keys will be reset when the UPDI is disabled.
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UPDI - Unified Program and Debug Interface
30.5.5
ASI Key Status
Name:
Offset:
Reset:
Property:
Bit
7
ASI_KEY_STATUS
0x07
0x00
-
6
Access
Reset
5
UROWWRITE
R/W
0
4
NVMPROG
R
0
3
CHIPERASE
R
0
2
1
0
Bit 5 – UROWWRITE User Row Write Key Status
This bit is set to ‘1’ if the UROWWRITE key is successfully decoded. This bit must be written as the final part of the
user row write procedure to correctly reset the programming session.
Bit 4 – NVMPROG NVM Programming Key Status
This bit is set to ‘1’ if the NVMPROG key is successfully decoded. The bit is cleared when the NVM Programming
sequence is initiated, and the NVMPROG bit in ASI_SYS_STATUS is set.
Bit 3 – CHIPERASE Chip Erase Key Status
This bit is set to ‘1’ if the Chip Erase key is successfully decoded. The bit is cleared by the Reset Request issued as
part of the Chip Erase sequence described in the Chip Erase section.
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UPDI - Unified Program and Debug Interface
30.5.6
ASI Key Status
Name:
Offset:
Reset:
Property:
Bit
7
ASI_KEY_STATUS
0x07
0x00
-
6
Access
Reset
5
UROWWRITE
R/W
0
4
NVMPROG
R
0
3
CHIPERASE
R
0
2
1
0
Bit 5 – UROWWRITE User Row Write Key Status
This bit is set to ‘1’ if the UROWWRITE KEY is active. Otherwise, this bit reads as ‘0’.
Bit 4 – NVMPROG NVM Programming
This bit is set to ‘1’ if the NVMPROG KEY is active. This bit is automatically reset after the programming sequence is
done. Otherwise, this bit reads as ‘0’.
Bit 3 – CHIPERASE Chip Erase
This bit is set to ‘1’ if the CHIPERASE KEY is active. This bit will automatically be reset when the Chip Erase
sequence is completed. Otherwise, this bit reads as ‘0’.
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UPDI - Unified Program and Debug Interface
30.5.7
ASI Reset Request
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
ASI_RESET_REQ
0x08
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
RSTREQ[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – RSTREQ[7:0] Reset Request
A Reset is signalized to the System when writing the Reset signature 0x59h to this address.
Writing any other signature to this register will clear the Reset.
When reading this register, reading bit RSTREQ[0] will tell if the UPDI is holding an active Reset on the system. If this
bit is ‘1’, the UPDI has an active Reset request to the system. All other bits will read as ‘0’.
The UPDI will not be reset when issuing a System Reset from this register.
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UPDI - Unified Program and Debug Interface
30.5.8
ASI Control A
Name:
Offset:
Reset:
Property:
Bit
7
ASI_CTRLA
0x09
0x03
-
6
5
4
3
Access
Reset
2
1
0
UPDICLKSEL[1:0]
R/W
R/W
1
1
Bits 1:0 – UPDICLKSEL[1:0] UPDI Clock Divider Select
Writing these bits selects the UPDI clock output frequency. The default setting after Reset and enable is 4 MHz. Any
other clock output selection is only recommended when the BOD is at the highest level. For all other BOD settings,
the default 4 MHz selection is recommended.
Value
Description
0x0
32 MHz UPDI clock
0x1
16 MHz UPDI clock
0x2
8 MHz UPDI clock
0x3
4 MHz UPDI clock (Default Setting)
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UPDI - Unified Program and Debug Interface
30.5.9
ASI System Control A
Name:
Offset:
Reset:
Property:
ASI_SYS_CTRLA
0x0A
0x00
-
Bit
7
6
5
4
3
2
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
1
UROWWRITE_
FINAL
R/W
0
0
CLKREQ
R/W
0
Bit 1 – UROWWRITE_FINAL User Row Programming Done
This bit must be written when the user row data have been written to the RAM. Writing a ‘1’ to this bit will start the
process of programming the user row data to the Flash.
If this bit is written before the user row data is written to the RAM by the UPDI, the CPU will proceed without the
written data.
This bit is writable only if the USERROW-Write key is successfully decoded.
Bit 0 – CLKREQ Request System Clock
If this bit is written to ‘1’, the ASI is requesting the system clock, independent of the system sleep modes. This makes
it possible for the UPDI to access the ACC layer, also if the system is in a sleep mode.
Writing a ‘0’ to this bit will lower the clock request.
This bit will be reset when the UPDI is disabled.
This bit is set by default when the UPDI is enabled.
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30.5.10 ASI System Status
Name:
Offset:
Reset:
Property:
Bit
7
ASI_SYS_STATUS
0x0B
0x01
-
6
Access
Reset
5
RSTSYS
R
0
4
INSLEEP
R
0
3
NVMPROG
R
0
2
UROWPROG
R
0
1
0
LOCKSTATUS
R
1
Bit 5 – RSTSYS System Reset Active
If this bit is set, there is an active Reset on the system domain. If this bit is cleared, the system is not in Reset.
This bit is cleared on read.
A Reset held from the ASI_RESET_REQ register will also affect this bit.
Bit 4 – INSLEEP System Domain in Sleep
If this bit is set, the system domain is in IDLE or deeper Sleep mode. If this bit is cleared, the system is not in Sleep.
Bit 3 – NVMPROG Start NVM Programming
If this bit is set, NVM Programming can start from the UPDI.
When the UPDI is done, it must reset the system through the UPDI Reset register.
Bit 2 – UROWPROG Start User Row Programming
If this bit is set, User Row Programming can start from the UPDI.
When the UPDI is done, it must write the UROWWRITE_FINAL bit in ASI_SYS_CTRLA.
Bit 0 – LOCKSTATUS NVM Lock Status
If this bit is set, the device is locked. If a Chip Erase is done, and the Lockbits are cleared, this bit will read as ‘0’.
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UPDI - Unified Program and Debug Interface
30.5.11 ASI CRC Status
Name:
Offset:
Reset:
Property:
Bit
7
ASI_CRC_STATUS
0x0C
0x00
-
6
5
4
3
Access
Reset
2
R
0
1
CRC_STATUS[2:0]
R
0
0
R
0
Bits 2:0 – CRC_STATUS[2:0] CRC Execution Status
This bit field signalizes the status of the CRC conversion. This bit field is one-hot encoded.
Value
Description
0x0
Not enabled
0x1
CRC enabled, busy
0x2
CRC enabled, done with OK signature
0x4
CRC enabled, done with FAILED signature
Other
Reserved
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Instruction Set Summary
31.
Instruction Set Summary
The instruction set summary is part of the AVR Instruction Set Manual, located at www.microchip.com/DS40002198.
Refer to the CPU version called AVRxt, for details regarding the devices documented in this data sheet.
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Electrical Characteristics
32.
Electrical Characteristics
32.1
Disclaimer
All typical values are measured at T = 25°C and VDD = 3V unless otherwise specified. All minimum and maximum
values are valid across operating temperature and voltage unless otherwise specified.
Typical values given should be considered for design guidance only, and actual part variation around these values is
expected.
32.2
Absolute Maximum Ratings
Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 32-1. Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage
IVDD
Current into a VDD pin
IGND
Conditions
Current out of a GND pin
Min.
Max.
Unit
-0.5
6
V
TA = [-40, 85]°C
-
200
mA
TA = [85, 125]°C
-
100
mA
TA = [-40, 85]°C
-
200
mA
TA = [85, 125]°C
-
100
mA
VPIN
Pin voltage with respect to GND
-0.5
VDD+0.5
V
IPIN
I/O pin sink/source current
-40
40
mA
Ic1(1)
I/O pin injection current except for the RESET pin
Vpin < GND-0.6V or
5.5V < Vpin ≤ 6.1V
4.9V < VDD ≤ 5.5V
-1
1
mA
Ic2(1)
I/O pin injection current except for the RESET pin
Vpin < GND-0.6V or
Vpin ≤ 5.5V
VDD ≤ 4.9V
-15
15
mA
Tstorage
Storage temperature
-65
150
°C
Note:
1.
– If VPIN is lower than GND-0.6V, then a current limiting resistor is required. The negative DC injection
current limiting resistor is calculated as R = (GND-0.6V – Vpin)/ICn.
– If VPIN is greater than VDD+0.6V, then a current limiting resistor is required. The positive DC injection
current limiting resistor is calculated as R = (Vpin-(VDD+0.6))/ICn.
32.3
General Operating Ratings
The device must operate within the ratings listed in this section for all other electrical characteristics and typical
characteristics of the device to be valid.
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Electrical Characteristics
Table 32-2. General Operating Conditions
Symbol Description
VDD
Condition
Operating Supply Voltage
VAO - Auto Grade and Extended Operating
temperature range
TA
Min.
Max. Unit
1.8(1,2)
5.5
V
2.7(2,3) 5.5
V
Operating temperature range Extended
-40
125
Industrial
-40
85
°C
Notes:
1. Operation is guaranteed down to 1.8V or BOD triggering level VBOD when BOD is active.
2. During Chip Erase, the BOD is forced ON. If the supply voltage VDD is below the configured VBOD, the erase
attempt will fail.
3. Operation is guaranteed down to 2.7V or BOD triggering level VBOD when BOD is active.
Table 32-3. Operating Voltage and Frequency
Symbol
Description
Condition
Min.
Max.
Unit
fCLK_CPU
Nominal operating system clock frequency
VDD = [1.8, 5.5]V
TA = [-40, 105]°C(1,4)
0
5
MHz
VDD = [2.7, 5.5]V
TA = [-40, 105]°C(2,4)
0
10
VDD = [4.5, 5.5]V
TA = [-40, 105]°C(3,4)
0
20
VDD = [2.7, 5.5]V
TA = [-40, 125]°C(2)
0
8
VDD = [4.5, 5.5]V
TA = [-40, 125]°C(3)
0
16
Notes:
1. Operation is guaranteed down to BOD triggering level, VBOD with BODLEVEL0.
2. Operation is guaranteed down to BOD triggering level, VBOD with BODLEVEL2.
3. Operation is guaranteed down to BOD triggering level, VBOD with BODLEVEL7.
4. These specifications do not apply to automotive range parts (-VAO).
The maximum CPU clock frequency depends on VDD. As shown in the figure below, the Maximum Frequency vs. VDD
is linear between 1.8V < VDD < 2.7V and 2.7V < VDD < 4.5V.
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Electrical Characteristics
Figure 32-1. Maximum Frequency vs. VDD for [-40, 105]°C
20 MHz
10 MHz
Safe Operating Area
5 MHz
1.8V
2.7V
4.5V
5.5V
Figure 32-2. Maximum Frequency vs. VDD for [105, 125]°C
16 MHz
8 MHz
Safe Operating Area
2.7V
4.5V
5.5V
Figure 32-3. Maximum Frequency vs. VDD for [-40, 125]°C, Automotive Range Parts (-VAO)
16 MHz
8 MHz
Safe Operating Area
2.7V
32.4
4.5V
5.5V
Power Considerations
The average chip-junction temperature, TJ, in °C, can be obtained from the following equations:
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Electrical Characteristics
•
•
Equation 1: TJ = TA + (PD x θJA)
Equation 2: TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide whether a cooling device is
necessary or not. If a cooling device has to be fitted on the chip, the second equation must be used to compute the
resulting average chip-junction temperature TJ in °C.
Power usage can be calculated by adding together system power consumption and I/O module power consumption.
The current drawn from pins with a capacitive load may be estimated (for one pin) as follows:
Icp ≈ VDD * Cload * fsw
Where Cload = pin load capacitance and fsw = average switching frequency of I/O pin.
Table 32-4. Thermal Resistance Data
32.5
Pin Count
Package
TA Range
θJA [°C/W]
θJC [°C/W]
32
VQFN
-40°C to 125°C
41
16
32
TQFP
-40°C to 125°C
69
20
48
VQFN
-40°C to 125°C
36
14.4
48
TQFP
-40°C to 125°C
68
17
Power Consumption
The values are measured power consumption under the following conditions, except where noted:
• VDD = 3V
• TA = 25°C
• OSC20M used as the system clock source, except where otherwise specified
• System power consumption measured with peripherals disabled and I/O ports driven low with inputs disabled
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Electrical Characteristics
Table 32-5. Power Consumption in Active and Idle Mode
Mode
Description
Active Active power
consumption
Clock Source
PDIV
Division
fCLK_CPU
OSC20M FREQSEL =
0x2
1
20 MHz
5V
10
-
mA
2
10 MHz
5V
5
-
mA
3V
3
-
mA
5V
2.5
5
mA
3V
1.5
-
mA
2V
1
-
mA
4
OSC20M FREQSEL =
0x1
OSCULP32K
Idle
Idle power consumption
5 MHz
1
16 MHz
5V
8
-
mA
2
8 MHz
5V
4
-
mA
3V
2.3
-
mA
32.768 kHz 5V
20
-
µA
3V
11
-
µA
2V
7
-
µA
1
OSC20M FREQSEL =
0x2
1
20 MHz
5V
2.8
-
mA
2
10 MHz
5V
1.4
-
mA
3V
1
-
mA
5V
0.7
3.5
mA
3V
0.5
-
mA
2V
0.4
-
mA
4
OSC20M FREQSEL =
0x1
OSCULP32K
VDD Typ. Max. Unit
5 MHz
1
16 MHz
5V
2.2
-
mA
2
8 MHz
5V
1.1
-
mA
3V
0.7
-
mA
32.768 kHz 5V
6
-
µA
3V
3
-
µA
2V
2
-
µA
1
Table 32-6. Power Consumption in Power-Down, Standby and Reset Mode
Mode
Standby
Description
Standby power
consumption
© 2021 Microchip Technology Inc.
Condition
Typ.
25°C
Max.
25°C
Max.
85°C(1)
Max.
125°C
Unit
RTC running at 1.024
kHz from external
XOSC32K (CL = 7.5
pF)
VDD = 3V
0.6
-
-
-
µA
RTC running at 1.024
kHz from internal
OSCULP32K
VDD = 3V
0.5
3
6
16
µA
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Electrical Characteristics
...........continued
Mode
Description
Condition
Typ.
25°C
PowerDown/
Standby
Power-down/
Standby power
consumption are
the same when
all peripherals
are stopped
All peripherals
stopped
VDD = 3V
0.1
Reset
Reset power
consumption
RESET line pulled low VDD = 3V
100
Max.
25°C
Max.
85°C(1)
Max.
125°C
Unit
2
5
15
µA
-
-
-
µA
Note:
1. These values are based on characterization and are not covered by production test limits.
32.6
Wake-Up Time
The following table shows wake-up time from various sleep modes with various system clock sources. It also shows
the start-up time from reset with no Unified Programming Interface (UPDI) connection active and with 0 ms start-up
time (SUT) setting.
Table 32-7. Start-Up and Wake-Up Time
Symbol
tstartup
Description
The start-up time from the release
of any Reset source. Execution
of first instruction. (Excluding
CRCSCAN)
twakeup(1) Wake-up from Idle
Clock
Source
Any
PDIV
Division
Any
VDD Min. Typ. Max. Unit
Any
Any
-
200
-
20 MHz
5V
-
1
-
10 MHz
3V
-
2
-
5 MHz
2V
-
4
-
OSC20M
1
FREQSEL =
2
0x1
16 MHz
5V
-
1.2
-
8 MHz
3V
-
2.4
-
OSCULP32K 1
32.768 kHz
OSC20M
1
FREQSEL =
2
0x2
20 MHz
5V
-
12
-
10 MHz
3V
-
13
-
5 MHz
2V
-
15
-
OSC20M
1
FREQSEL =
2
0x1
16 MHz
5V
-
16
-
8 MHz
3V
-
15
-
OSCULP32K 1
32.768 kHz
-
750
-
OSC20M
1
FREQSEL =
2
0x2
4
Wake-up time from Standby or
Power-down when clock source is
stopped
fCLK_CPU
4
µs
700
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on the
clock output (CLKOUT) pin. All peripherals and modules start execution from the first clock cycle, except the
CPU that is halted for four clock cycles before program execution starts.
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Electrical Characteristics
Figure 32-4. Wake-Up Time Definition
Wake-Up Time
Wake-Up Request
CLKOUT
32.7
Peripherals Power Consumption
Use the table below to calculate the additional current consumption for the different I/O peripherals in the various
operating modes.
Some peripherals will request the clock to be enabled when operating in STANDBY. See the peripheral chapter for
further information.
Operating conditions:
• VDD = 3V
• T = 25°C
• OSC20M at 1 MHz used as the system clock source, except where otherwise specified
• In Idle sleep mode, except where otherwise specified
Table 32-8. Peripherals Power Consumption
Typ.(1)
Unit
Continuous
19
µA
Sampling @ 1 kHz
1.2
TCA
16-bit count @ 1 MHz
13.0
µA
TCB
16-bit count @ 1 MHz
7.4
µA
RTC
16-bit count @ OSCULP32K
1.2
µA
WDT (including OSCULP32K)
0.7
µA
OSC20M
130
µA
Fast mode(2)
92
µA
Low-Power mode(2)
45
50 ksps
330
100 ksps
340
CL = 7.5 pF
0.5
µA
0.4
µA
Peripheral
BOD
AC
ADC(3)
XOSC32K
Conditions
OSCULP32K
µA
USART
Enable @ 9600 Baud
13.0
µA
SPI (Host)
Enable @ 100 kHz
2.1
µA
TWI (Host)
Enable @ 100 kHz
24.0
µA
TWI (Client)
Enable @ 100 kHz
17.0
µA
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Electrical Characteristics
...........continued
Typ.(1)
Unit
Erase Operation
1.5
mA
Write Operation
3.0
Peripheral
Conditions
Flash programming
Notes:
1. Current consumption of the module only. To calculate the total internal power consumption of the
microcontroller, add this value to the base power consumption given in the “Power Consumption” section
in electrical characteristics.
2. CPU in Standby mode.
3. Average power consumption with ADC active in Free-Running mode.
32.8
BOD and POR Characteristics
Table 32-9. Power Supply Characteristics
Symbol
SRON
Description
Condition
Min.
Power-on Slope
-
Typ.
Max.
Unit
-
100(1,2)
V/ms
Notes:
1. For design guidance only and not tested in production.
2. A slope faster than the maximum rating can trigger a Reset of the device if changing the voltage level after an
initial power-up.
Table 32-10. Power-on Reset (POR) Characteristics
Symbol
VPOR
Description
Condition
POR threshold voltage on VDD falling
VDD falls/rises at 0.5 V/ms or slower
POR threshold voltage on VDD rising
Min.
Typ. Max. Unit
0.8(1)
-
1.6(1)
1.4(1)
-
1.8
V
Note:
1. For design guidance only. Not tested in production.
Table 32-11. Brown-out Detector (BOD) Characteristics
Symbol
VBOD
VHYS
tBOD
tstartup
Description
BOD detection level (falling/rising)
Hysteresis
Detection time
Start-up time
© 2021 Microchip Technology Inc.
Condition
Min. Typ. Max. Unit
BODLEVEL0
1.7
1.8
2.0
BODLEVEL2
2.4
2.6
2.9
BODLEVEL7
3.9
4.3
4.5
BODLEVEL0
-
25
-
BODLEVEL2
-
40
-
BODLEVEL7
-
80
-
Continuous
-
7
-
µs
Sampled, 1 kHz
-
1
-
ms
Sampled, 125 Hz
-
8
-
Time from enable to ready
-
40
-
Complete Datasheet
V
mV
µs
DS40002172C-page 466
ATmega808/809/1608/1609
Electrical Characteristics
...........continued
Symbol
VINT
32.9
Description
Condition
Interrupt level 0
Min. Typ. Max. Unit
Percentage above the selected BOD level
-
4
-
Interrupt level 1
-
13
-
Interrupt level 2
-
25
-
%
External Reset Characteristics
Table 32-12. External Reset Characteristics
Mode
Description
Condition
VVIH_RST
Input Voltage for RESET
VVIL_RST
Input Low Voltage for RESET
tMIN_RST
Minimum pulse width on RESET pin
Rp_RST
RESET pull-up resistor
VReset = 0V
Min.
Typ.
Max.
Unit
0.7 × VDD
-
VDD + 0.2
V
-0.2
-
0.3 × VDD
-
-
0.5(1)
µs
20
35
50
kΩ
Note:
1. These parameters are for design guidance only and are not production tested.
32.10
Oscillators and Clocks
Operating conditions:
• VDD = 3V, unless otherwise specified
• Oscillator frequencies above speed specification must be divided so the CPU clock is always within
specification.
Table 32-13. 20 MHz Internal Oscillator (OSC20M) Characteristics
Symbol
fOSC20M
Description
Factory calibration frequency
Condition
FREQSEL = 0x01
Min. Typ. Max. Unit
TA = 25°C, 3.0V
16
FREQSEL = 0x02
fCAL
ETOTAL
EDRIFT
Frequency calibration range
Total error with 16 MHz and 20
MHz frequency selection
MHz
20
OSC20M FREQSEL
= 0x01
14.5
17.5 MHz
OSC20M FREQSEL
= 0x02
18.5
21.5 MHz
TA = 25°C, 3.0V
-1.5
1.5
%
TA = [0, 70]°C, VDD =
[1.8, 3.6]V
-2.0
2.0
%
Full operation range
-4.0
4.0
TA = [0, 70]°C, VDD =
[1.8, 5.5]V
-1.8
1.8
%
From target
frequency
Accuracy with 16 MHz and 20
Factory calibrated
MHz frequency selection relative VDD = 3V(1)
to the factory-stored frequency
value
ΔfOSC20M Calibration step size
-
0.75
-
%
DOSC20M Duty cycle
-
50
-
%
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 467
ATmega808/809/1608/1609
Electrical Characteristics
...........continued
Symbol
Description
tstartup
Start-up time
Condition
Min. Typ. Max. Unit
Within 2% accuracy
-
12
-
µs
Note:
1. See also the description of OSC20M on calibration.
Table 32-14. 32.768 kHz Internal Oscillator (OSCULP32K) Characteristics
Symbol
Description
fOSCULP32K
Condition
Min.
Factory calibration frequency
ETOTAL
Typ.
Max. Unit
32.768
kHz
Factory calibration accuracy
TA = 25°C, 3.0V
-3
3
%
Total error from target frequency
TA = [0, 70]°C, VDD = [1.8, 3.6]V
-10
+10
%
Full operation range
-20
+20
DOSCULP32K
Duty cycle
tstartup
Start-up time
50
-
%
250
-
µs
Table 32-15. 32.768 kHz External Crystal Oscillator (XOSC32K) Characteristics
Symbol
Description
fout
Frequency
tstartup
Start-up time
CL
Crystal load capacitance
ESR
Condition
Min.
Typ.
Max.
Unit
-
32.768
-
kHz
-
300
-
ms
7.5(1)
-
12.5(1)
pF
kΩ
CL = 7.5 pF
Equivalent Series Resistance - Safety Factor=3
CL = 7.5 pF
-
-
80(1)
CL = 12.5
pF
-
-
40(1)
Note:
1. This parameter is for design guidance only. Not production tested.
Figure 32-5. External Clock Waveform Characteristics
V IH1
V IL1
Table 32-16. External Clock Characteristics
Symbol
Description
Condition VDD=[1.8, 5.5]V VDD=[2.7, 5.5]V VDD=[4.5, 5.5]V Unit
Min.
Max.
Min.
Max.
Min.
Max.
0
5.0
0.0
10.0
0.0
20.0
MHz
fCLCL
Frequency
tCLCL
Clock Period
200
-
100
-
50
-
ns
tCHCX(1)
High Time
80
-
40
-
20
-
ns
tCLCX(1)
Low Time
80
-
40
-
20
-
ns
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 468
ATmega808/809/1608/1609
Electrical Characteristics
...........continued
Symbol
Description
Condition VDD=[1.8, 5.5]V VDD=[2.7, 5.5]V VDD=[4.5, 5.5]V Unit
Min.
Max.
Min.
Max.
Min.
Max.
Rise Time (for maximum
frequency)
-
40
-
20
-
10
ns
Fall Time (for maximum
frequency)
-
40
-
20
-
10
ns
ΔtCLCL(1) Change in period from one clock
cycle to the next
-
20
-
20
-
20
%
tCLCH
(1)
tCHCL(1)
Note:
1. This parameter is for design guidance only. Not production tested.
32.11
I/O Pin Characteristics
Table 32-17. I/O Pin Characteristics (TA=[-40, 85]°C, VDD=[1.8, 5.5]V unless otherwise noted)
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
-0.2
-
0.3×VDD
V
VIH
Input High Voltage
0.7×VDD
-
VDD+0.2V
V
IIH / IIL
I/O pin Input Leakage Current
VDD = 5.5V, pin high
-
< 0.05
-
µA
VDD = 5.5V, pin low
-
< 0.05
-
VDD = 1.8V, IOL = 1.5 mA
-
-
0.36
VDD = 3.0V, IOL = 7.5 mA
-
-
0.6
VDD = 5.0V, IOL = 15 mA
-
-
1
VDD = 1.8V, IOH = 1.5 mA
1.44
-
-
VDD = 3.0V, IOH = 7.5 mA
2.4
-
-
VDD = 5.0V, IOH = 15 mA
4
-
-
Maximum combined I/O sink/
source current per pin group
TA = 125°C
-
-
100(1,2)
Maximum combined I/O sink/
source current per pin group
TA = 25°C
-
-
200(1,2)
Rise time
VDD = 3.0V, load = 20 pF
-
2.5
-
VDD= 5.0 V, load = 20 pF
-
1.5
-
VDD = 3.0 V, load = 20 pF, slew rate
enabled
-
19
-
VDD= 5.0 V, load = 20 pF, slew rate
enabled
-
9
-
VOL
VOH
Itotal
tRISE
I/O pin drive strength
I/O pin drive strength
© 2021 Microchip Technology Inc.
Complete Datasheet
V
V
mA
ns
DS40002172C-page 469
ATmega808/809/1608/1609
Electrical Characteristics
...........continued
Symbol
tFALL
Description
Condition
Fall time
Min.
Typ.
Max.
Unit
VDD = 3.0 V, load = 20 pF
-
2.0
-
ns
VDD = 5.0 V, load = 20 pF
-
1.3
-
VDD = 3.0 V, load = 20 pF, slew rate
enabled
-
21
-
VDD = 5.0 V, load = 20 pF, slew rate
enabled
-
11
-
Cpin
I/O pin capacitance except for
TOSC, VREFA, and TWI pins
-
3.5
-
pF
Cpin
I/O pin capacitance on TOSC
pins
-
4
-
pF
Cpin
I/O pin capacitance on TWI pins
-
10
-
pF
Cpin
I/O pin capacitance on VREFA
pin
-
14
-
pF
Rp
Pull-up resistor
20
35
50
kΩ
Notes:
1. Pin group A (PA[7:0]), PF[6:2]), pin group B (PB[7:0], PC[7:0]), pin group C (PD:7:0, PE[3:0], PF[1:0]). For
28-pin and 32-pin devices, pin group A and B should be seen as a single group. The combined continuous
sink/source current for each group should not exceed the limits.
2. These parameters are for design guidance only and are not production tested.
32.12
USART
Figure 32-6. USART in SPI Mode - Timing Requirements in Host Mode
SS
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSb
LSb
tMOH
tMOH
MOSI
(Data Output)
MSb
LSb
Table 32-18. USART in SPI Host Mode - Timing Characteristics(1)
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
fSCK
SCK clock frequency
Host
-
-
10
MHz
tSCK
SCK period
Host
100
-
-
ns
tSCKW
SCK high/low width
Host
-
0.5 × tSCK
-
ns
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 470
ATmega808/809/1608/1609
Electrical Characteristics
...........continued
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
tSCKR
SCK rise time
Host
-
2.7
-
ns
tSCKF
SCK fall time
Host
-
2.7
-
ns
tMIS
MISO setup to SCK
Host
-
10
-
ns
tMIH
MISO hold after SCK
Host
-
10
-
ns
tMOS
MOSI setup to SCK
Host
-
0.5 × tSCK
-
ns
tMOH
MOSI hold after SCK
Host
-
1.0
-
ns
Note:
1. These parameters are for design guidance only and are not production tested.
32.13
SPI
Figure 32-7. SPI - Timing Requirements in Host Mode
SS
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSb
LSb
tMOH
tMOH
MOSI
(Data Output)
MSb
LSb
Figure 32-8. SPI - Timing Requirements in Client Mode
SS
tSSCKR
tSSS
tSSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data Input)
tSIH
MSb
tSOSS
MISO
(Data Output)
© 2021 Microchip Technology Inc.
tSSCK
LSb
tSOS
tSOSH
MSb
LSb
Complete Datasheet
DS40002172C-page 471
ATmega808/809/1608/1609
Electrical Characteristics
Table 32-19. SPI - Timing Characteristics(1)
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
fSCK
SCK clock frequency
Host
-
-
10
MHz
tSCK
SCK period
Host
100
-
-
ns
tSCKW
SCK high/low width
Host
-
0.5 × SCK
-
ns
tSCKR
SCK rise time
Host
-
2.7
-
ns
tSCKF
SCK fall time
Host
-
2.7
-
ns
tMIS
MISO setup to SCK
Host
-
10
-
ns
tMIH
MISO hold after SCK
Host
-
10
-
ns
tMOS
MOSI setup to SCK
Host
-
0.5 × SCK
-
ns
tMOH
MOSI hold after SCK
Host
-
1.0
-
ns
fSSCK
Client SCK clock frequency
Client
-
-
5
MHz
tSSCK
Client SCK period
Client
4 × t CLK_PER
-
-
ns
tSSCKW
SCK high/low width
Client
2 × t CLK_PER
-
-
ns
tSSCKR
SCK rise time
Client
-
-
1600
ns
tSSCKF
SCK fall time
Client
-
-
1600
ns
tSIS
MOSI setup to SCK
Client
3.0
-
-
ns
tSIH
MOSI hold after SCK
Client
t CLK_PER
-
-
ns
tSSS
SS setup to SCK
Client
21
-
-
ns
tSSH
SS hold after SCK
Client
20
-
-
ns
tSOS
MISO setup to SCK
Client
-
8.0
-
ns
tSOH
MISO hold after SCK
Client
-
13
-
ns
tSOSS
MISO setup after SS low
Client
-
11
-
ns
tSOSH
MISO hold after SS low
Client
-
8.0
-
ns
Note:
1. These parameters are for design guidance only and are not production tested.
32.14
TWI
Figure 32-9. TWI - Timing Requirements
tHIGH
tOF
SCL
tSU;STA
tHD ;STA
tSU ;DAT
tLOW
tSP
tHD ;DAT
tR
tSU ;STO
tBUF
SDA
S
© 2021 Microchip Technology Inc.
P
Complete Datasheet
S
DS40002172C-page 472
ATmega808/809/1608/1609
Electrical Characteristics
Table 32-20. TWI - Specifications(1)
Symbol
Description
Condition
Typ.
Max.
Unit
0
-
1000
kHz
fSCL
SCL clock frequency
VIH
Input high voltage
0.7×VDD
-
-
V
VIL
Input low voltage
-
-
0.3×VDD
V
VHYS
Hysteresis of Schmitt
Trigger inputs
0.4×VDD
V
VOL
Output low voltage
V
IOL
CB
tR
Low-level output
current
Capacitive load for
each bus line
Rise time for both
SDA and SCL
Max. frequency requires system
clock at 10 MHz, which, in turn,
requires VDD = [2.7, 5.5]V and T =
[-40, 105]°C
Min.
0.1×VDD
Iload = 20 mA, Fast mode+
-
-
0.2xVDD
Iload = 3 mA, Normal mode, VDD >
2V
-
-
0.4V
Iload = 3 mA, Normal mode, VDD ≤
2V
-
-
0.2×VDD
fSCL ≤ 400 kHz, VOL = 0.4V
3
-
-
fSCL ≤ 1 MHz, VOL = 0.4V
20
-
-
fSCL ≤ 100 kHz
-
-
400
fSCL ≤ 400 kHz
-
-
400
fSCL ≤ 1 MHz
-
-
550
fSCL ≤ 100 kHz
-
-
1000
fSCL ≤ 400 kHz
20
-
300
-
-
120
-
250
fSCL ≤ 1 MHz
tOF
Output fall time from
VIHmin to VILmax
tSP
Spikes suppressed by
the input filter
IL
Input current for each
I/O pin
CI
Capacitance for each
I/O pin
RP
Value of pull-up
resistor
10 pF < capacitance
of bus line < 400 pF
fSCL ≤ 100
kHz
pF
ns
ns
fSCL ≤ 400
kHz
20×(VDD/
5.5V)
-
250
fSCL ≤ 1 MHz
20×(VDD/
5.5V)
-
120
0
-
50
ns
-
-
1
µA
-
-
10
pF
(VDDVOL(max)) /IO
-
1000 ns/
(0.8473×CB)
Ω
0.1×VDD < VI < 0.9×VDD
fSCL ≤ 100 kHz
mA
L
© 2021 Microchip Technology Inc.
fSCL ≤ 400 kHz
-
-
300 ns/
(0.8473×CB)
fSCL ≤ 1 MHz
-
-
120 ns/
(0.8473×CB)
Complete Datasheet
DS40002172C-page 473
ATmega808/809/1608/1609
Electrical Characteristics
...........continued
Symbol
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Description
Hold time (repeated)
Start condition
Low period of SCL
Clock
High period of SCL
Clock
Setup time for
a repeated Start
condition
Data hold time
Data setup time
Setup time for Stop
condition
Bus free time
between a Stop and
Start condition
Condition
Min.
Typ.
Max.
Unit
fSCL ≤ 100 kHz
4.0
-
-
µs
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
Start
-
2.1
-
Repeated start
-
3.1
-
fSCL ≤ 100 kHz
4.7
-
-
fSCL ≤ 400 kHz
1.3
-
-
fSCL ≤ 1 MHz
0.5
-
-
fSCL ≤ 100 kHz
4.0
-
-
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
fSCL ≤ 100 kHz
4.7
-
-
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
-
3
-
TSCL
fSCL ≤ 100 kHz
0
-
3.45
µs
fSCL ≤ 400 kHz
0
-
0.9
fSCL ≤ 1 MHz
0
-
0.45
fSCL ≤ 100 kHz
250
-
-
fSCL ≤ 400 kHz
100
-
-
fSCL ≤ 1 MHz
50
-
-
fSCL ≤ 100 kHz
4
-
-
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
-
2
-
TSCL
fSCL ≤ 100 kHz
4.7
-
-
µs
fSCL ≤ 400 kHz
1.3
-
-
fSCL ≤ 1 MHz
0.5
-
-
-
2
-
TSCL
µs
µs
µs
ns
µs
TSCL
Note:
1. These parameters are for design guidance only and are not production tested.
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 474
ATmega808/809/1608/1609
Electrical Characteristics
Table 32-21. SDA Hold Time(1,2)
Symbol
tHD;DAT
Description
Condition
Data hold time
Host(3)
fCLK_PER = 5 MHz
fCLK_PER = 10 MHz
fCLK_PER = 20 MHz
tHD;DAT
Data hold time
Client(4)
All Frequencies
Min.
Typ.
Max.
Unit
SDAHOLD = 0x00
-
800
-
ns
SDAHOLD = 0x01
830
850
950
SDAHOLD = 0x02
830
850
950
SDAHOLD = 0x03
830
850
1270
SDAHOLD = 0x00
-
400
-
SDAHOLD = 0x01
430
450
550
SDAHOLD = 0x02
430
450
580
SDAHOLD = 0x03
430
550
1270
SDAHOLD = 0x00
-
200
220
SDAHOLD = 0x01
230
250
350
SDAHOLD = 0x02
260
450
580
SDAHOLD = 0x03
380
600
1270
SDAHOLD = 0x00
90
150
220
SDAHOLD = 0x01
130
200
350
SDAHOLD = 0x02
260
400
580
SDAHOLD = 0x03
390
550
1270
ns
Notes:
1. These parameters are for design guidance only and are not covered by production test limits.
2. SDAHOLD is the data hold time after the SCL signal is detected to be low. The actual hold time is, therefore,
higher than the configured hold time.
3. For Host mode, the data hold time is whatever is largest of the following:
– 4×tCLK_PER + 50 ns (typical)
– SDAHOLD configuration + SCL filter delay
4. For Client mode, the hold time is given by:
– SDAHOLD configuration + SCL filter delay
32.15
VREF
Table 32-22. Internal Voltage Reference Characteristics(1)
Symbol
Description
Min.
Typ.
Max.
Unit
-
25
-
µs
V
tstart
Start-up time
VDD
Power supply voltage range for 0V55
1.8
-
5.5
Power supply voltage range for 1V1
1.8
-
5.5
Power supply voltage range for 1V5
1.8
-
5.5
Power supply voltage range for 2V5
3.0
-
5.5
Power supply voltage range for 4V3
4.8
-
5.5
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 475
ATmega808/809/1608/1609
Electrical Characteristics
Note:
1. These parameters are for design guidance only and are not production tested.
Table 32-23. ADC Internal Voltage Reference Characteristics(1)
Symbol(2)
Description
Condition
Min.
Typ.
Max.
Unit
%
1V1
Internal reference voltage
VDD = [1.8V, 5.5V]
T = [0 - 105]°C
-2.0
2.0
0V55
1V5
2V5
4V3
Internal reference voltage
VDD = [1.8V, 5.5V]
T = [0 - 105]°C
-3.0
3.0
0V55
1V1
1V5
2V5
4V3
Internal reference voltage
VDD = [1.8V, 5.5V]
T = [-40 - 125]°C
-5.0
5.0
Notes:
1. These values are based on characterization and not covered by production test limits.
2. The symbols xVxx refer to the respective values of the ADC0REFSEL bit field in the VREF.CTRLA register.
Table 32-24. AC Internal Voltage Reference Characteristics(1)
Symbol(2)
Description
Condition
Min.
Typ.
Max.
Unit
%
0V55
1V1
1V5
2V5
Internal reference voltage
VDD = [1.8V, 5.5V]
T = [0 - 105]°C
-3.0
3.0
0V55
1V1
1V5
2V5
4V3
Internal reference voltage
VDD = [1.8V, 5.5V]
T = [-40 - 125]°C
-5.0
5.0
Notes:
1. These values are based on characterization and not covered by production test limits.
2. The symbols xVxx refer to the respective values of the AC0REFSEL bit field in the VREF.CTRLA register.
32.16
ADC
32.16.1 Internal Reference Characteristics
Operating conditions:
• VDD = 1.8 to 5.5V
• Temperature = -40°C to 125°C
• DUTYCYC = 25%
• CLKADC = 13 * fADC
• SAMPCAP is 10 pF for 0.55V reference, while it is set to 5 pF for VREF ≥ 1.1V
• Applies for all allowed combinations of VREF selections and Sample Rates unless otherwise noted
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 476
ATmega808/809/1608/1609
Electrical Characteristics
Table 32-25. Power Supply, Reference, and Input Range
Symbol
VDD
VREF
CIN
Description
Supply voltage
Reference voltage
Input capacitance
Conditions
Min.
Typ.
Max.
Unit
CLKADC ≤ 1.5 MHz
1.8
-
5.5
V
CLKADC > 1.5 MHz
2.7
-
5.5
REFSEL = Internal reference
0.55
-
VDD-0.5
REFSEL = External reference
1.1
REFSEL = VDD
1.8
-
5.5
SAMPCAP = 5 pF
-
5
-
SAMPCAP = 10 pF
-
10
-
V
VDD
pF
RIN
Input resistance
-
14
-
kΩ
VIN
Input voltage range
0
-
VREF
V
IBAND
Input bandwidth
-
-
57.5
kHz
Min.
Typ.
Max.
Unit
1.1V ≤ VREF
15
-
115
ksps
1.1V ≤ VREF (8-bit resolution)
15
-
150
VREF = 0.55V (10 bits)
7.5
-
20
VREF = 0.55V (10 bits)
100
-
260
1.1V ≤ VREF (10 bits)
200
-
1500
1.1V ≤ VREF (8-bit resolution)
200
-
2000
2
2
33
CLKADC cycles
8.7
-
50
µs
-
22
-
µs
1.1V ≤ VREF
Table 32-26. Clock and Timing Characteristics(1)
Symbol
fADC
CLKADC
Description
Sample rate
Clock frequency
Conditions
Ts
Sampling time
TCONV
Conversion time (latency)
Sampling time = 2 CLKADC
TSTART
Start-up time
Internal VREF
kHz
Note:
1. These parameters are for design guidance only and are not production tested.
Table 32-27. Accuracy Characteristics Internal Reference(2)
Symbol
Description
Res
Resolution
INL
Integral Nonlinearity
Conditions
Min.
Typ.
Max.
Unit
-
10
-
bit
fADC = 7.7 ksps
-
1.0
3.0
LSB
REFSEL =
INTERNAL or VDD
fADC = 15 ksps
-
1.0
3.0
REFSEL =
INTERNAL or VDD
fADC = 77 ksps
-
1.0
3.0
fADC = 115 ksps
-
1.2
3.0
REFSEL =
INTERNAL
VREF = 0.55V
1.1V ≤ VREF
© 2021 Microchip Technology Inc.
Complete Datasheet
DS40002172C-page 477
ATmega808/809/1608/1609
Electrical Characteristics
...........continued
Symbol
DNL(1)
Description
Differential Nonlinearity
Conditions
Min.
Typ.
Max.
Unit
fADC = 7.7 ksps
-
0.6
1.3
LSB
fADC = 15 ksps
-
0.4
1.2
fADC = 15 ksps
-
0.4
1.0
fADC = 77 ksps
-
0.4
1.0
fADC = 115 ksps
-
0.5
1.6
fADC = 115 ksps
-
0.9
2.0
T = [0-105]°C
-
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