ATmega48PA/88PA/168PA
AVR® Microcontroller with picoPower® Technology
Introduction
®
The picoPower ATmega48PA/88PA/168PA is a low-power CMOS 8-bit microcontroller based on the
®
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
®
ATmega48PA/88PA/168PA achieves throughputs close to 1 MIPS per MHz. This empowers system
designers to optimize the device for power consumption versus processing speed.
Feature
®
High Performance, Low-Power AVR 8-Bit Microcontroller Family
Advanced RISC Architecture
•
– 131 Powerful instructions
– Most single clock cycle execution
– 32 x 8 General purpose working registers
– Fully static operation
– Up to 20 MIPS throughput at 20 MHz
– On-chip 2-cycle multiplier
•
High Endurance Nonvolatile Memory Segments
– 4K/8K/16K Bytes of in-system self-programmable Flash program memory
– 256/512/512 Bytes EEPROM
– 512/1K/1K Bytes internal SRAM
– Write/erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional boot code section with independent lock bits
• In-system programming by on-chip boot program
• True read-while-write operation
– Programming lock for software security
•
QTouch Library Support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
•
Peripheral Features
– Two 8-bit Timer/counters with separate prescaler and Compare mode
– One 16-bit Timer/counter with separate prescaler, Compare mode, and Capture mode
– Real time counter with separate oscillator
– Six PWM channels
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 1
ATmega48PA/88PA/168PA
–
–
–
–
–
–
•
•
•
•
•
•
8-channel 10-bit ADC in TQFP and QFN/MLF package
• Temperature measurement
6-channel 10-bit ADC in PDIP package
• Temperature measurement
Two master/slave SPI serial interface
One programmable serial USART
One byte-oriented 2-wire serial interface (Philips I2C compatible)
Programmable watchdog timer with separate on-chip oscillator
– One on-chip analog comparator
– Interrupt and wake-up on pin change
Special Microcontroller Features
– Power-on Reset and programmable Brown-out Detection
– Internal calibrated oscillator
– External and internal interrupt sources
– Six sleep modes: idle, ADC noise reduction, power-save, power-down, standby, and extended
standby
I/O and Packages
– 23 Programmable I/O lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V
Temperature Range:
– -40°C to 105°C
Speed Grade:
– ATmega48PA/88PA/168PA: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C
– Active mode: 0.2 mA
– Power-Down mode: 0.1 μA
– Power-Save mode: 0.75 μA (Including 32 kHz RTC)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 2
Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description...............................................................................................................10
2. Configuration Summary........................................................................................... 11
3. Ordering Information ...............................................................................................12
3.1.
3.2.
3.3.
ATmega48PA..............................................................................................................................12
ATmega88PA .............................................................................................................................13
ATmega168PA............................................................................................................................14
4. Block Diagram......................................................................................................... 15
5. Pin Configurations................................................................................................... 16
5.1.
5.2.
Pin-out........................................................................................................................................ 16
Pin Descriptions......................................................................................................................... 20
6. I/O Multiplexing........................................................................................................22
7. Resources............................................................................................................... 24
8. Data Retention.........................................................................................................25
9. About Code Examples.............................................................................................26
10. Capacitive Touch Sensing....................................................................................... 27
10.1. QTouch Library........................................................................................................................... 27
11. AVR CPU Core........................................................................................................ 28
11.1.
11.2.
11.3.
11.4.
11.5.
Overview.................................................................................................................................... 28
Arithmetic Logic Unit (ALU)........................................................................................................ 29
Status Register...........................................................................................................................29
General Purpose Register File................................................................................................... 32
Stack Pointer.............................................................................................................................. 33
11.6. Instruction Execution Timing...................................................................................................... 35
11.7. Reset and Interrupt Handling..................................................................................................... 36
12. AVR Memories.........................................................................................................39
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
Overview.................................................................................................................................... 39
In-System Reprogrammable Flash Program Memory................................................................39
SRAM Data Memory.................................................................................................................. 40
EEPROM Data Memory............................................................................................................. 42
I/O Memory.................................................................................................................................43
Register Description................................................................................................................... 44
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DS40002011A-page 3
ATmega48PA/88PA/168PA
13. System Clock and Clock Options............................................................................ 53
13.1. Clock Systems and Their Distribution........................................................................................ 53
13.2. Clock Sources............................................................................................................................ 54
13.3. Low-Power Crystal Oscillator..................................................................................................... 56
13.4. Full Swing Crystal Oscillator.......................................................................................................58
13.5. Low-Frequency Crystal Oscillator.............................................................................................. 59
13.6. Calibrated Internal RC Oscillator................................................................................................60
13.7. 128 kHz Internal Oscillator......................................................................................................... 61
13.8. External Clock............................................................................................................................ 62
13.9. Timer/Counter Oscillator.............................................................................................................63
13.10. Clock Output Buffer....................................................................................................................63
13.11. System Clock Prescaler............................................................................................................. 63
13.12. Register Description...................................................................................................................64
14. Power Management and Sleep Modes................................................................... 68
14.1. Overview.................................................................................................................................... 68
14.2. Sleep Modes.............................................................................................................................. 68
14.3. BOD Disable...............................................................................................................................69
14.4. Idle Mode....................................................................................................................................69
14.5. ADC Noise Reduction Mode...................................................................................................... 69
14.6. Power-Down Mode.....................................................................................................................70
14.7. Power-Save Mode......................................................................................................................70
14.8. Standby Mode............................................................................................................................ 71
14.9. Extended Standby Mode............................................................................................................ 71
14.10. Power Reduction Register......................................................................................................... 71
14.11. Minimizing Power Consumption................................................................................................. 71
14.12. Register Description...................................................................................................................73
15. System Control and Reset.......................................................................................78
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.
15.7.
15.8.
15.9.
Resetting the AVR...................................................................................................................... 78
Reset Sources............................................................................................................................78
Power-on Reset..........................................................................................................................79
External Reset............................................................................................................................80
Brown-out Detection...................................................................................................................80
Watchdog System Reset............................................................................................................ 81
Internal Voltage Reference.........................................................................................................81
Watchdog Timer......................................................................................................................... 82
Register Description................................................................................................................... 84
16. Interrupts................................................................................................................. 88
16.1.
16.2.
16.3.
16.4.
Interrupt Vectors in ATmega48PA.............................................................................................. 88
Interrupt Vectors in ATmega88PA.............................................................................................. 89
Interrupt Vectors in ATmega168PA............................................................................................ 92
Register Description................................................................................................................... 95
17. EXTINT - External Interrupts................................................................................... 98
17.1. Pin Change Interrupt Timing.......................................................................................................98
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ATmega48PA/88PA/168PA
17.2. Register Description................................................................................................................... 99
18. I/O-Ports................................................................................................................ 108
18.1.
18.2.
18.3.
18.4.
Overview.................................................................................................................................. 108
Ports as General Digital I/O......................................................................................................109
Alternate Port Functions........................................................................................................... 112
Register Description................................................................................................................. 124
19. 8-bit Timer/Counter0 (TC0) with PWM.................................................................. 136
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
19.9.
Features................................................................................................................................... 136
Overview.................................................................................................................................. 136
Timer/Counter Clock Sources.................................................................................................. 138
Counter Unit............................................................................................................................. 138
Output Compare Unit............................................................................................................... 139
Compare Match Output Unit.....................................................................................................141
Modes of Operation..................................................................................................................143
Timer/Counter Timing Diagrams.............................................................................................. 147
Register Description................................................................................................................. 149
20. 16-bit Timer/Counter1 (TC1) with PWM................................................................ 161
20.1. Overview.................................................................................................................................. 161
20.2. Features................................................................................................................................... 161
20.3. Block Diagram.......................................................................................................................... 161
20.4. Definitions.................................................................................................................................162
20.5. Registers.................................................................................................................................. 163
20.6. Accessing 16-bit Timer/Counter Registers............................................................................... 163
20.7. Timer/Counter Clock Sources.................................................................................................. 166
20.8. Counter Unit............................................................................................................................. 166
20.9. Input Capture Unit.................................................................................................................... 167
20.10. Output Compare Units............................................................................................................. 169
20.11. Compare Match Output Unit.....................................................................................................171
20.12. Modes of Operation..................................................................................................................172
20.13. Timer/Counter 0, 1 Prescalers................................................................................................. 180
20.14. Timer/Counter Timing Diagrams.............................................................................................. 180
20.15. Register Description.................................................................................................................182
21. Timer/Counter 0, 1 Prescalers...............................................................................195
21.1.
21.2.
21.3.
21.4.
Internal Clock Source............................................................................................................... 195
Prescaler Reset........................................................................................................................195
External Clock Source..............................................................................................................195
Register Description................................................................................................................. 197
22. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous Operation...................199
22.1.
22.2.
22.3.
22.4.
22.5.
Features................................................................................................................................... 199
Overview.................................................................................................................................. 199
Timer/Counter Clock Sources.................................................................................................. 201
Counter Unit............................................................................................................................. 201
Output Compare Unit............................................................................................................... 202
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ATmega48PA/88PA/168PA
22.6. Compare Match Output Unit.....................................................................................................204
22.7. Modes of Operation..................................................................................................................205
22.8. Timer/Counter Timing Diagrams.............................................................................................. 209
22.9. Asynchronous Operation of Timer/Counter2............................................................................ 210
22.10. Timer/Counter Prescaler.......................................................................................................... 212
22.11. Register Description................................................................................................................. 212
23. Serial Peripheral Interface (SPI)............................................................................227
23.1.
23.2.
23.3.
23.4.
23.5.
Features................................................................................................................................... 227
Overview.................................................................................................................................. 227
SS Pin Functionality................................................................................................................. 231
Data Modes.............................................................................................................................. 231
Register Description................................................................................................................. 232
24. Universal Synchronous Asynchronous Receiver Transceiver (USART)............... 237
24.1. Features................................................................................................................................... 237
24.2. Overview.................................................................................................................................. 237
24.3. Block Diagram.......................................................................................................................... 237
24.4. Clock Generation......................................................................................................................238
24.5. Frame Formats.........................................................................................................................241
24.6. USART Initialization................................................................................................................. 242
24.7. Data Transmission – The USART Transmitter......................................................................... 243
24.8. Data Reception – The USART Receiver.................................................................................. 245
24.9. Asynchronous Data Reception.................................................................................................249
24.10. Multi-Processor Communication Mode.................................................................................... 252
24.11. Examples of Baud Rate Setting............................................................................................... 252
24.12. Register Description.................................................................................................................255
25. USART in SPI (USARTSPI) Mode.........................................................................265
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
25.7.
25.8.
Features................................................................................................................................... 265
Overview.................................................................................................................................. 265
Clock Generation......................................................................................................................265
SPI Data Modes and Timing.....................................................................................................266
Frame Formats.........................................................................................................................266
Data Transfer............................................................................................................................268
AVR USART MSPIM vs. AVR SPI............................................................................................269
Register Description................................................................................................................. 270
26. Two-Wire Serial Interface (TWI)............................................................................ 271
26.1.
26.2.
26.3.
26.4.
26.5.
26.6.
26.7.
26.8.
26.9.
Features................................................................................................................................... 271
Two-Wire Serial Interface Bus Definition..................................................................................271
Data Transfer and Frame Format.............................................................................................272
Multi-Master Bus Systems, Arbitration, and Synchronization...................................................275
Overview of the TWI Module.................................................................................................... 277
Using the TWI...........................................................................................................................279
Transmission Modes................................................................................................................ 282
Multi-Master Systems and Arbitration...................................................................................... 300
Register Description................................................................................................................. 301
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ATmega48PA/88PA/168PA
27. Analog Comparator (AC)....................................................................................... 309
27.1. Overview.................................................................................................................................. 309
27.2. Analog Comparator Multiplexed Input...................................................................................... 309
27.3. Register Description................................................................................................................. 310
28. Analog-to-Digital Converter (ADC)........................................................................ 314
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
28.9.
Features................................................................................................................................... 314
Overview.................................................................................................................................. 314
Starting a Conversion...............................................................................................................316
Prescaling and Conversion Timing...........................................................................................317
Changing Channel or Reference Selection.............................................................................. 319
ADC Noise Canceler................................................................................................................ 321
ADC Conversion Result........................................................................................................... 324
Temperature Measurement...................................................................................................... 325
Register Description................................................................................................................. 325
29. debugWIRE On-chip Debug System..................................................................... 334
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
Features................................................................................................................................... 334
Overview.................................................................................................................................. 334
Physical Interface..................................................................................................................... 334
Software Breakpoints............................................................................................................... 335
Limitations of debugWIRE........................................................................................................335
Register Description................................................................................................................. 335
30. Self-Programming the Flash..................................................................................337
30.1. Overview.................................................................................................................................. 337
30.2. Addressing the Flash During Self-Programming...................................................................... 338
30.3. Register Description................................................................................................................. 343
31. Boot Loader Support – Read-While-Write Self-programming (BTLDR)................ 346
31.1.
31.2.
31.3.
31.4.
31.5.
31.6.
31.7.
31.8.
31.9.
Features................................................................................................................................... 346
Overview.................................................................................................................................. 346
Application and Boot Loader Flash Sections............................................................................346
Read-While-Write and No Read-While-Write Flash Sections...................................................347
Boot Loader Lock Bits.............................................................................................................. 349
Entering the Boot Loader Program...........................................................................................351
Addressing the Flash During Self-Programming...................................................................... 351
Self-Programming the Flash.....................................................................................................352
Register Description................................................................................................................. 361
32. Memory Programming (MEMPROG).....................................................................364
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
Program And Data Memory Lock Bits...................................................................................... 364
Fuse Bits.................................................................................................................................. 365
Signature Bytes........................................................................................................................ 368
Calibration Byte........................................................................................................................ 368
Serial Number.......................................................................................................................... 368
Page Size................................................................................................................................. 369
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ATmega48PA/88PA/168PA
32.7. Parallel Programming Parameters, Pin Mapping, and Commands..........................................369
32.8. Parallel Programming...............................................................................................................371
32.9. Serial Downloading.................................................................................................................. 378
33. Electrical Characteristics....................................................................................... 384
33.1.
33.2.
33.3.
33.4.
33.5.
33.6.
33.7.
33.8.
33.9.
Absolute Maximum Ratings......................................................................................................384
Common DC Characteristics....................................................................................................384
Speed Grades.......................................................................................................................... 388
Clock Characteristics................................................................................................................389
System and Reset Characteristics........................................................................................... 390
SPI Timing Characteristics....................................................................................................... 391
Two-Wire Serial Interface Characteristics................................................................................ 392
ADC Characteristics................................................................................................................. 394
Parallel Programming Characteristics...................................................................................... 395
34. Typical Characteristics (TA = -40°C to 105°C).......................................................398
34.1. ATmega48PA Typical Characteristics.......................................................................................398
34.2. ATmega88PA: Typical Characteristics......................................................................................423
34.3. ATmega168PA Typical Characteristics.....................................................................................448
35. Register Summary.................................................................................................472
35.1. Note..........................................................................................................................................474
36. Instruction Set Summary....................................................................................... 476
37. Packaging Information...........................................................................................481
37.1.
37.2.
37.3.
37.4.
37.5.
32-pin 32A................................................................................................................................ 481
32-pin 32M1-A..........................................................................................................................482
32-pin 32CC1........................................................................................................................... 483
28-pin 28M1............................................................................................................................. 483
28-pin 28P3.............................................................................................................................. 484
38. Errata.....................................................................................................................486
38.1. Errata ATmega48PA.................................................................................................................486
38.2. Errata ATmega88PA.................................................................................................................487
38.3. Errata ATmega168PA...............................................................................................................488
39. Datasheet Revision History................................................................................... 490
39.1. Revision A – 4/2018................................................................................................................. 490
39.2. Pre Microchip Revisions...........................................................................................................490
The Microchip Web Site.............................................................................................. 491
Customer Change Notification Service........................................................................491
Customer Support....................................................................................................... 491
Product Identification System...................................................................................... 492
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Datasheet Complete
DS40002011A-page 8
ATmega48PA/88PA/168PA
Microchip Devices Code Protection Feature............................................................... 492
Legal Notice.................................................................................................................493
Trademarks................................................................................................................. 493
Quality Management System Certified by DNV...........................................................494
Worldwide Sales and Service......................................................................................495
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 9
ATmega48PA/88PA/168PA
Description
1.
Description
®
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega48PA/88PA/168PA provides the following features: 4K/8K/16Kbytes of in-system
programmable Flash with read-while-write capabilities, 256/512/512bytes EEPROM, 512/1K/1Kbytes
SRAM, 23 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC),
three flexible timer/counters with Compare modes and PWM, 1 serial programmable USARTs , 1 byteoriented 2-wire Serial Interface (I2C), a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF
packages), a programmable watchdog timer with internal oscillator, an SPI serial port, and six software
selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters,
SPI port, and interrupt system to continue functioning. The Power-Down mode saves the register
contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware
Reset. In Power-Save mode, the asynchronous timer continues to run, allowing the user to maintain a
timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and
all I/O modules except asynchronous timer and ADC to minimize switching noise during ADC
conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is
sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby
mode, both the main oscillator and the asynchronous timer continue to run.
®
Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust
sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression™
(AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain
allows you to explore, develop and debug your own touch applications.
The device is manufactured using Microchip’s high density nonvolatile memory technology. The on-chip
ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by
a conventional nonvolatile memory programmer, or by an on-chip boot program running on the AVR core.
The boot program can use any interface to download the application program in the application Flash
memory. Software in the boot Flash section will continue to run while the application Flash section is
updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-system selfprogrammable Flash on a monolithic chip, the ATmega48PA/88PA/168PA is a powerful microcontroller
that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega48PA/88PA/168PA is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and
evaluation kits.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 10
ATmega48PA/88PA/168PA
Configuration Summary
2.
Configuration Summary
Features
ATmega48PA/88PA/168PA
Pin Count
28/32
Flash (Bytes)
4K/8K/16K
SRAM (Bytes)
512/1K/1K
EEPROM (Bytes)
256/512/512
Interrupt Vector Size (instruction word/vector)
1/1/2
General Purpose I/O Lines
23
SPI
2
TWI (I2C)
1
USART
1
ADC
10-bit 15 kSPS
ADC Channels
8
8-bit Timer/Counters
2
16-bit Timer/Counters
1
ATmega88PA and ATmega168PA support a real read-while-write self-programming mechanism. There is
a separate boot loader section, and the SPM instruction can only execute from there. In ATmega48PA,
there is no read-while-write support and no separate boot loader section. The SPM instruction can
execute from the entire Flash.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 11
ATmega48PA/88PA/168PA
Ordering Information
3.
Ordering Information
3.1
ATmega48PA
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
20
1.8 - 5.5
ATmega48PA-AU
ATmega48PA-AUR(4)
ATmega48PA-CCU
ATmega48PA-CCUR(4)
ATmega48PA-MMH(5)
ATmega48PA-MMHR(4)(5)
ATmega48PA-MU
ATmega48PA-MUR(4)
ATmega48PA-PU
32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 85°C)
ATmega48PA-AN
ATmega48PA-ANR(4)
ATmega48PA-MMN
ATmega48PA-MMNR(4)
ATmega48PA-MN
ATmega48PA-MNR(4)
ATmega48PA-PN
32A
32A
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 105°C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32CC1
32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 12
ATmega48PA/88PA/168PA
Ordering Information
3.2
ATmega88PA
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
20
1.8 - 5.5
ATmega88PA-AU
ATmega88PA-AUR(4)
ATmega88PA-CCU
ATmega88PA-CCUR(4)
ATmega88PA-MMH(5)
ATmega88PA-MMHR(4)(5)
ATmega88PA-MU
ATmega88PA-MUR(4)
ATmega88PA-PU
32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 85°C)
ATmega88PA-AN
ATmega88PA-ANR(4)
ATmega88PA-MMN
ATmega88PA-MMNR(4)
ATmega88PA-MN
ATmega88PA-MNR(4)
ATmega88PA-PN
32A
32A
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 105°C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32CC1
32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 13
ATmega48PA/88PA/168PA
Ordering Information
3.3
ATmega168PA
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
20
1.8 - 5.5
ATmega168PA-AU
ATmega168PA-AUR(4)
ATmega168PA-CCU
ATmega168PA-CCUR(4)
ATmega168PA-MMH(5)
ATmega168PA-MMHR(4)(5)
ATmega168PA-MU
ATmega168PA-MUR(4)
ATmega168PA-PU
32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 85°C)
ATmega168PA-AN
ATmega168PA-ANR(4)
ATmega168PA-MN
ATmega168PA-MNR(4)
ATmega168PA-PN
32A
32A
32M1-A
32M1-A
28P3
Industrial
(-40°C to 105°C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32CC1
32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 14
ATmega48PA/88PA/168PA
Block Diagram
4.
Block Diagram
Figure 4-1. Block Diagram
SRAM
debugWire
CPU
OCD
Clock generation
XTAL1 /
TOSC1
XTAL2 /
TOSC2
32.768kHz
XOSC
8MHz
Calib RC
External
clock
16MHz LP
XOSC
VCC
128kHz int
osc
Power
Supervision
POR/BOD &
RESET
RESET
GND
ADC6,ADC7,PC[5:0]
AREF
ADC[7:0]
AREF
PD[7:0], PC[6:0], PB[7:0]
PD3, PD2
PCINT[23:0]
INT[1:0]
PB1, PB2
PD5
PB0
OC1A/B
T1
ICP1
PB3
PD3
OC2A
OC2B
© 2018 Microchip Technology Inc.
NVM
programming
Power
management
and clock
control
Watchdog
Timer
ADC
EXTINT
FLASH
D
A
T
A
B
U
S
EEPROM
EEPROMIF
I/O
PORTS
I
N
/
O
U
T
PB[7:0]
PC[6:0]
PD[7:0]
GPIOR[2:0]
TC 0
D
A
T
A
B
U
S
(8-bit)
SPI 0
AC
Internal
Reference
USART 0
RxD0
TxD0
XCK0
PD0
PD1
PD4
TWI 0
SDA0
SCL0
PC4
PC5
T0
OC0A
OC0B
PD4
PD6
PD5
MISO0
MOSI0
SCK0
SS0
PB4
PB3
PB5
PB2
AIN0
AIN1
PD6
PD7
ADCMUX
ADC6, ADC7
PC[5:0]
TC 1
(16-bit)
TC 2
(8-bit async)
Datasheet Complete
DS40002011A-page 15
ATmega48PA/88PA/168PA
Pin Configurations
5.
5.1
Pin Configurations
Pin-out
Figure 5-1. 28-pin PDIP
(PCINT14/RESET) PC6
1
28
PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0
2
27
PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1
3
26
PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2
4
25
PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3
5
24
PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4
6
23
PC0 (ADC0/PCINT8)
VCC
7
22
GND
GND
8
21
AREF
(PCINT6/XTAL1/TOSC1) PB6
9
20
AVCC
(PCINT7/XTAL2/TOSC2) PB7
10
19
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
11
18
PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6
12
17
PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7
13
16
PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0
14
15
PB1 (OC1A/PCINT1)
© 2018 Microchip Technology Inc.
Datasheet Complete
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
DS40002011A-page 16
ATmega48PA/88PA/168PA
Pin Configurations
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
28
27
26
25
24
23
22
Figure 5-2. 28-pin MLF Top View
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
18
GND
(PCINT6/XTAL1/TOSC1) PB6
5
17
AREF
(PCINT7/XTAL2/TOSC2) PB7
6
16
AVCC
(PCINT21/OC0B/T1) PD5
7
15
PB5 (SCK/PCINT5)
Bottom pad should be
soldered to ground
© 2018 Microchip Technology Inc.
14
4
(PCINT4/MISO) PB4
GND
13
PC0 (ADC0/PCINT8)
(PCINT3/OC2A/MOSI) PB3
19
12
3
(PCINT2/SS/OC1B) PB2
VCC
11
PC1 (ADC1/PCINT9)
(PCINT1/OC1A) PB1
20
10
2
(PCINT0/CLKO/ICP1) PB0
(PCINT20/XCK/T0) PD4
(PCINT23/AIN1) PD7
PC2 (ADC2/PCINT10)
9
21
8
1
(PCINT22/OC0A/AIN0) PD6
(PCINT19/OC2B/INT1) PD3
Datasheet Complete
DS40002011A-page 17
ATmega48PA/88PA/168PA
Pin Configurations
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
29
28
27
Digital
Analog
Crystal/CLK
PC2 (ADC2/PCINT10)
PD0 (RXD/PCINT16)
30
Programming/debug
25
PD1 (TXD/PCINT17)
31
Ground
26
PD2 (INT0/PCINT18)
32
Power
PC3 (ADC3/PCINT11)
Figure 5-3. 32-pin TQFP Top View
GND
GND
5
20
AREF
VCC
6
19
ADC6
(PCINT6/XTAL1/TOSC1) PB6
7
18
AVCC
(PCINT7/XTAL2/TOSC2) PB7
8
17
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
© 2018 Microchip Technology Inc.
16
21
(PCINT4/MISO) PB4
4
15
VCC
(PCINT3/OC2A/MOSI) PB3
ADC7
14
22
(PCINT2/SS/OC1B) PB2
3
13
GND
(PCINT1/OC1A) PB1
PC0 (ADC0/PCINT8)
12
23
(PCINT0/CLKO/ICP1) PB0
2
11
(PCINT20/XCK/T0) PD4
(PCINT23/AIN1) PD7
PC1 (ADC1/PCINT9)
10
24
(PCINT22/OC0A/AIN0) PD6
1
9
(PCINT19/OC2B/INT1) PD3
Datasheet Complete
DS40002011A-page 18
ATmega48PA/88PA/168PA
Pin Configurations
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
32
31
30
29
28
27
26
25
Figure 5-4. 32-pin MLF Top View
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
GND
5
20
AREF
VCC
6
19
ADC6
(PCINT6/XTAL1/TOSC1) PB6
7
18
AVCC
(PCINT7/XTAL2/TOSC2) PB7
8
17
PB5 (SCK/PCINT5)
16
GND
(PCINT4/MISO) PB4
21
15
4
(PCINT3/OC2A/MOSI) PB3
VCC
14
ADC7
(PCINT2/SS/OC1B) PB2
22
13
3
(PCINT1/OC1A) PB1
GND
12
PC0 (ADC0/PCINT8)
(PCINT0/CLKO/ICP1) PB0
23
11
2
(PCINT23/AIN1) PD7
(PCINT20/XCK/T0) PD4
10
PC1 (ADC1/PCINT9)
(PCINT22/OC0A/AIN0) PD6
24
9
1
(PCINT21/OC0B/T1) PD5
(PCINT19/OC2B/INT1) PD3
Bottom pad should be
soldered to ground
Table 5-1. 32UFBGA
1
2
3
4
5
6
A
PD2
PD1
PC6
PC4
PC2
PC1
B
PD3
PD4
PD0
PC5
PC3
PC0
C
GND
GND
-
-
ADC7
GND
D
VCC
VCC
-
-
AREF
ADC6
E
PB6
PD6
PB0
PB2
AVCC
PB5
F
PB7
PD5
PD7
PB1
PB3
PB4
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 19
ATmega48PA/88PA/168PA
Pin Configurations
5.2
Pin Descriptions
5.2.1
VCC
Digital supply voltage pin.
5.2.2
GND
Ground.
5.2.3
Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated during a Reset condition even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting oscillator
amplifier.
If the internal calibrated RC oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] input for
the asynchronous timer/counter2 if the AS2 bit in ASSR is set.
5.2.4
Port C (PC[5:0])
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The PC[5:0]
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated during a Reset condition even if the clock is not running.
5.2.5
PC6/RESET
If the RSTDISBL fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of
PC6 differ from those of the other pins of Port C.
If the RSTDISBL fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are
not guaranteed to generate a Reset.
The various special features of Port C are elaborated in the Alternate Functions of Port C section.
5.2.6
Port D (PD[7:0])
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each pin). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated during a Reset condition even if the clock is not running.
5.2.7
AVCC
AVCC is the supply voltage pin for the A/D Converter (ADC), PC[3:0], and PE[3:2]. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that PC[6:4] use digital supply voltage, VCC.
5.2.8
AREF
AREF is the analog reference pin for the A/D Converter.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 20
ATmega48PA/88PA/168PA
Pin Configurations
5.2.9
ADC[7:6]
In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are
powered by the analog supply and serve as 10-bit ADC channels.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 21
ATmega48PA/88PA/168PA
I/O Multiplexing
6.
I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
I2C 0
(32-pin
32UFBGA)
Pin#
(32-pin
MLF/
TQFP)
Pin#
(28-pin
MLF)
Pin#
(28-pin
PIPD)
Pin#
PAD
EXTINT PCINT
B1
1
1
5
PD3
INT1
B2
2
2
6
PD4
D1
4
3
7
VCC
C1
3
4
8
GND
D2
6
-
-
VCC
C2
5
-
-
GND
E1
7
5
9
PB6
PCINT6
XTAL1/
TOSC1
F1
8
6
10
PB7
PCINT7
XTAL2/
TOSC2
F2
9
7
11
PD5
PCINT21
OC0B
E2
10
8
12
PD6
PCINT22 AIN0
OC0A
F3
11
9
13
PD7
PCINT23 AIN1
E3
12
10
14
PB0
PCINT0
F4
13
11
15
PB1
PCINT1
OC1A
E4
14
12
16
PB2
PCINT2
OC1B
SS0
F5
15
13
17
PB3
PCINT3
OC2A
MOSI0
F6
16
14
18
PB4
PCINT4
MISO0
E6
17
15
19
PB5
PCINT5
SCK0
E5
18
16
20
AVCC
D6
19
-
-
ADC6
D5
20
17
21
AREF
C6
21
18
22
GND
C5
22
-
-
ADC7
B6
23
19
13
PC0
PCINT8
ADC0
A6
24
20
24
PC1
PCINT9
ADC1
A2
25
21
25
PC2
PCINT10 ADC2
B5
26
22
26
PC3
PCINT11 ADC3
A4
27
23
27
PC4
PCINT12 ADC4
SDA0
B4
28
24
28
PC5
PCINT13 ADC5
SCL0
© 2018 Microchip Technology Inc.
ADC/A
C
OSC
T/C #0 T/C USART
#1 0
PCINT19
OC2B
PCINT20
T0
CLKO
SPI 0
XCK0
T1
ICP1
ADC6
ADC7
Datasheet Complete
DS40002011A-page 22
ATmega48PA/88PA/168PA
I/O Multiplexing
(32-pin
32UFBGA)
Pin#
(32-pin
MLF/
TQFP)
Pin#
(28-pin
MLF)
Pin#
(28-pin
PIPD)
Pin#
PAD
A3
29
25
1
PC6/
RESET
PCINT14
B3
30
26
2
PD0
PCINT16
RXD0
A2
31
27
3
PD1
PCINT17
TXD0
A1
32
28
4
PD2
© 2018 Microchip Technology Inc.
EXTINT PCINT
INT0
ADC/A
C
OSC
T/C #0 T/C USART
#1 0
I2C 0
SPI 0
PCINT18
Datasheet Complete
DS40002011A-page 23
ATmega48PA/88PA/168PA
Resources
7.
Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 24
ATmega48PA/88PA/168PA
Data Retention
8.
Data Retention
Reliability qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 25
ATmega48PA/88PA/168PA
About Code Examples
9.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O registers located in extended I/O map, IN, OUT, SBIS, SBIC, CBI, and SBI instructions must be
replaced with instructions that allow access to extended I/O. Typically LDS and STS combined with SBRS,
SBRC, SBR, and CBR.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 26
ATmega48PA/88PA/168PA
Capacitive Touch Sensing
10.
10.1
Capacitive Touch Sensing
QTouch Library
®
®
The QTouch library provides a simple to use solution to realize touch sensitive interfaces on most AVR
™
microcontrollers. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and
then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor
states.
The QTouch library is FREE and downloadable from QTouch Library . For implementation details and
other information, refer to the QTouch Library User Guide, also available for download from the Microchip
website.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 27
ATmega48PA/88PA/168PA
AVR CPU Core
11.
AVR CPU Core
11.1
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must, therefore, be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 11-1. Block Diagram of the AVR Architecture
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R18
R16
R14
R12
R10
R8
R6
R4
R2
R0
Program
counter
Flash program
memory
Instruction
register
Instruction
decode
Data memory
Stack
pointer
Status
register
ALU
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the register file, the operation is executed, and the result is
stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space
addressing – enabling efficient address calculations. One of these address pointers can be used as an
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 28
ATmega48PA/88PA/168PA
AVR CPU Core
address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit
X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided into two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the Stack
Pointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table.
The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, SPI, and
other I/O functions. The I/O memory can be accessed directly, or as the data space locations following
those of the register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
11.2
Arithmetic Logic Unit (ALU)
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories: arithmetic, logical, and bit-functions. Some implementations of the architecture provide a
powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction
Set Summary section for a detailed description.
Related Links
36. Instruction Set Summary
11.3
Status Register
The Status register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status register is updated after all ALU operations, as specified in the instruction set
reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 29
ATmega48PA/88PA/168PA
AVR CPU Core
The Status register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 30
ATmega48PA/88PA/168PA
AVR CPU Core
11.3.1
Status Register
Name:
Offset:
Reset:
Property:
SREG
0x5F
0x00
When addressing as I/O Register: address offset is 0x3F
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit
Access
Reset
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – I Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable register is cleared,
none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a
bit in T can be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry flag is useful in BCD
arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag
V. See the Instruction Set Description for detailed information.
Bit 3 – V Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
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Bit 0 – C Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
11.4
General Purpose Register File
The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the register file:
•
•
•
•
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 11-2. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them
are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user data space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
11.4.1
The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
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Figure 11-3. The X-, Y-, and Z-registers
15
X-register
0
7
R26
YH
YL
0
7
R28
ZH
ZL
0
7
R31
0
0
R29
7
0
0
R27
7
15
Z-register
XL
7
15
Y-register
XH
0
0
R30
In the different addressing modes, these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
36. Instruction Set Summary
11.5
Stack Pointer
The stack is mainly used for storing temporary data, local variables, and return addresses after interrupts
and subroutine calls. The stack is implemented as growing from higher to lower memory locations. The
Stack Pointer register always points to the top of the stack.
The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are
located. A stack PUSH command will decrease the stack pointer. The stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial stack
pointer value equals the last address of the internal SRAM and the stack pointer must be set to point
above start of the SRAM. See the table for stack pointer details.
Table 11-1. Stack Pointer Instructions
Instruction Stack Pointer
Description
PUSH
Decremented by 1 Data is pushed onto the stack
CALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
ICALL
RCALL
POP
Incremented by 1
Data is popped from the stack
RET
Incremented by 2
Return address is popped from the stack with return from subroutine or
return from interrupt
RETI
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The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH register will not be present.
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11.5.1
Stack Pointer Register Low and High byte
Name:
Offset:
Reset:
Property:
SPL and SPH
0x5D
0x4FF
When addressing I/O registers as data space the offset address is 0x3D
The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Bit
15
14
13
12
11
10
9
8
SP10
SP9
SP8
Access
R
R
R
R
R
RW
RW
RW
Reset
0
0
0
0
0
1
0
0
Bit
Access
Reset
7
6
5
4
3
2
1
0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 – SP Stack Pointer Register
SPL and SPH are combined into SP.
Related Links
20.6 Accessing 16-bit Timer/Counter Registers
11.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal
clock division is used. The figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power unit.
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Figure 11-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU
operation using two register operands is executed and the result is stored back to the destination register.
Figure 11-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
11.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset vector
each have a separate program vector in the program memory space. All interrupts are assigned
individual enable bits, which must be written logic one together with the global interrupt enable bit in the
Status register in order to enable the interrupt. Depending on the program counter value, interrupts may
be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and interrupt
vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vectors
can be moved to the start of the boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset vector can be moved to the start of the boot Flash section by programming the
BOOTRST Fuse.
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction
– RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program
counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and
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hardware clears the corresponding interrupt flag. Interrupt flags can be cleared by writing a logic one to
the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt
enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI
instruction. The following example shows how this can be used to avoid interrupts during the timed
EEPROM write sequence.
Assembly Code Example(1)
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example(1)
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
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