ATmega324P/V
AVR® Microcontroller with Core Independent Peripherals
and picoPower® Technology
Introduction
®
®
The picoPower ATmega324P/V is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
®
ATmega324P/V achieves throughputs close to 1 MIPS per MHz. This empowers system designers to
optimize the device for power consumption versus processing speed.
Feature
High Performance, Low-Power AVR 8-Bit Microcontroller Family
•
•
Advanced RISC Architecture:
– 131 Powerful instructions
– Most single clock cycle execution
– 32 x 8 General purpose working registers
– Fully static operation
– Up to 20 MIPS throughput at 20 MHz
– On-chip 2-cycle multiplier
High Endurance Nonvolatile Memory Segments:
– 32K Bytes of in-system self-programmable Flash program memory
– 1K Bytes EEPROM
– 2K Bytes internal SRAM
– Write/erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional boot code section with independent lock bits
• In-system programming by on-chip boot program
• True read-while-write operation
– Programming lock for software security
®
•
QTouch Library Support:
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix™ acquisition
– Up to 64 sense channels
•
JTAG (IEEE std. 1149.1 compliant) Interface:
– Boundary-scan capabilities according to the JTAG standard
– Extensive on-chip debug support
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 1
ATmega324P/V
•
•
•
•
•
•
1.
– Programming of Flash, EEPROM, fuses, and lock bits through the JTAG interface
Peripheral Features:
– Two 8-bit timer/counters with separate Prescaler and Compare mode
– One 16-bit timer/counter with separate prescaler, Compare mode, and Capture mode
– Real time counter with separate oscillator
– Six PWM channels
– 8-channel 10-bit ADC
• Differential mode with selectable gain at 1x, 10x or 200x
– One byte-oriented 2-wire serial interface (Philips I2C compatible)
– Two programmable serial USART
– One master/slave SPI serial interface
– Programmable watchdog timer with separate on-chip oscillator
– On-chip analog comparator
– Interrupt and wake-up on pin change
Special Microcontroller Features:
– Power-on Reset and programmable Brown-out Detection
– Internal calibrated RC oscillator
– External and internal interrupt sources
– Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby, and extended
standby
I/O and Packages:
– 32 Programmable I/O lines
– 40-pin PDIP
– 44-lead TQFP
– 44-pad VQFN/QFN
Operating Voltage:
– 1.8 - 5.5V for ATmega324P/VV
– 2.7 - 5.5V for ATmega324P/V
Speed Grades:
– ATmega324P/VV:
• 0 - 4 MHz @ 1.8V - 5.5V
• 0 - 10 MHz @ 2.7V - 5.5V
– ATmega324P/V:
• 0 - 10 MHz @ 2.7V - 5.5V
• 0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C:
– Active mode: 0.4 mA
– Power-Down mode: 0.1 μA
– Power-Save mode: 0.6 μA (Including 32 kHz RTC)
Refer to Data Retention.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 2
Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description...............................................................................................................10
2. Configuration Summary........................................................................................... 11
3. Ordering Information ...............................................................................................12
4. Block Diagram......................................................................................................... 14
5. Pin Configurations................................................................................................... 15
5.1.
5.2.
Pinout......................................................................................................................................... 15
Pin Descriptions......................................................................................................................... 16
6. I/O Multiplexing........................................................................................................18
7. General Information.................................................................................................20
7.1.
7.2.
7.3.
Resources.................................................................................................................................. 20
About Code Examples................................................................................................................20
Capacitive Touch Sensing.......................................................................................................... 20
8. AVR CPU Core........................................................................................................ 21
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
Overview.................................................................................................................................... 21
Arithmetic Logic Unit (ALU)........................................................................................................ 22
Status Register...........................................................................................................................22
General Purpose Register File................................................................................................... 25
Stack Pointer.............................................................................................................................. 26
Instruction Execution Timing...................................................................................................... 28
Reset and Interrupt Handling..................................................................................................... 29
9. AVR Memories.........................................................................................................32
9.1.
9.2.
9.3.
Overview.................................................................................................................................... 32
In-System Reprogrammable Flash Program Memory................................................................32
SRAM Data Memory.................................................................................................................. 33
9.4.
9.5.
9.6.
EEPROM Data Memory............................................................................................................. 34
I/O Memory.................................................................................................................................35
Register Description................................................................................................................... 36
10. System Clock and Clock Options............................................................................ 45
10.1.
10.2.
10.3.
10.4.
Clock Systems and Their Distribution........................................................................................ 45
Clock Sources............................................................................................................................ 46
Low-Power Crystal Oscillator..................................................................................................... 48
Full Swing Crystal Oscillator.......................................................................................................49
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Datasheet Complete
DS40002012A-page 3
ATmega324P/V
10.5. Low Frequency Crystal Oscillator...............................................................................................51
10.6. Calibrated Internal RC Oscillator................................................................................................52
10.7. 128 kHz Internal Oscillator......................................................................................................... 53
10.8. External Clock............................................................................................................................ 53
10.9. Timer/Counter Oscillator.............................................................................................................54
10.10. Clock Output Buffer....................................................................................................................55
10.11. System Clock Prescaler............................................................................................................. 55
10.12. Register Description...................................................................................................................55
11. Power Management and Sleep Modes................................................................... 59
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
11.8.
11.9.
11.10.
11.11.
11.12.
Overview.................................................................................................................................... 59
Sleep Modes.............................................................................................................................. 59
BOD Disable...............................................................................................................................60
Idle Mode....................................................................................................................................60
ADC Noise Reduction Mode...................................................................................................... 60
Power-Down Mode.....................................................................................................................61
Power-Save Mode......................................................................................................................62
Standby Mode............................................................................................................................ 62
Extended Standby Mode............................................................................................................ 62
Power Reduction Register..........................................................................................................62
Minimizing Power Consumption................................................................................................. 62
Register Description................................................................................................................... 64
12. System Control and Reset.......................................................................................69
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
12.7.
12.8.
12.9.
Resetting the AVR...................................................................................................................... 69
Reset Sources............................................................................................................................69
Power-on Reset..........................................................................................................................70
External Reset............................................................................................................................71
Brown-out Detection...................................................................................................................71
Watchdog System Reset............................................................................................................ 72
Internal Voltage Reference.........................................................................................................72
Watchdog Timer......................................................................................................................... 73
Register Description................................................................................................................... 75
13. Interrupts................................................................................................................. 79
13.1. Overview.................................................................................................................................... 79
13.2. Interrupt Vectors in ATmega324P/V........................................................................................... 79
13.3. Register Description................................................................................................................... 82
14. External Interrupts (EXINT)..................................................................................... 85
14.1. Overview.................................................................................................................................... 85
15. I/O-Ports.................................................................................................................. 97
15.1.
15.2.
15.3.
15.4.
Overview.................................................................................................................................... 97
Ports as General Digital I/O........................................................................................................98
Alternate Port Functions...........................................................................................................101
Register Description................................................................................................................. 114
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 4
ATmega324P/V
16. 8-bit Timer/Counter0 (TC0) with PWM.................................................................. 129
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
16.8.
16.9.
Features................................................................................................................................... 129
Overview.................................................................................................................................. 129
Timer/Counter Clock Sources.................................................................................................. 131
Counter Unit............................................................................................................................. 131
Output Compare Unit............................................................................................................... 132
Compare Match Output Unit.....................................................................................................134
Modes of Operation..................................................................................................................136
Timer/Counter Timing Diagrams.............................................................................................. 140
Register Description................................................................................................................. 142
17. 16-bit Timer/Counter1 (TC1) with PWM................................................................ 154
17.1. Overview.................................................................................................................................. 154
17.2. Features................................................................................................................................... 154
17.3. Block Diagram.......................................................................................................................... 154
17.4. Definitions.................................................................................................................................155
17.5. Registers.................................................................................................................................. 156
17.6. Accessing 16-bit Timer/Counter Registers............................................................................... 156
17.7. Timer/Counter Clock Sources.................................................................................................. 159
17.8. Counter Unit............................................................................................................................. 159
17.9. Input Capture Unit.................................................................................................................... 160
17.10. Output Compare Units............................................................................................................. 162
17.11. Compare Match Output Unit.....................................................................................................164
17.12. Modes of Operation..................................................................................................................165
17.13. Timer/Counter 0, 1 Prescalers................................................................................................. 173
17.14. Timer/Counter Timing Diagrams.............................................................................................. 173
17.15. Register Description.................................................................................................................175
18. Timer/Counter 0, 1 Prescalers...............................................................................188
18.1.
18.2.
18.3.
18.4.
Internal Clock Source............................................................................................................... 188
Prescaler Reset........................................................................................................................188
External Clock Source..............................................................................................................188
Register Description................................................................................................................. 190
19. 8-bit Timer/Counter2 (TC2) with PWM and Asynchronous Operation...................192
19.1. Features................................................................................................................................... 192
19.2. Overview.................................................................................................................................. 192
19.3. Timer/Counter Clock Sources.................................................................................................. 194
19.4. Counter Unit............................................................................................................................. 194
19.5. Output Compare Unit............................................................................................................... 195
19.6. Compare Match Output Unit.....................................................................................................197
19.7. Modes of Operation..................................................................................................................198
19.8. Timer/Counter Timing Diagrams.............................................................................................. 202
19.9. Asynchronous Operation of Timer/Counter2............................................................................ 203
19.10. Timer/Counter Prescaler.......................................................................................................... 205
19.11. Register Description................................................................................................................. 205
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 5
ATmega324P/V
20. Serial Peripheral Interface (SPI)............................................................................220
20.1.
20.2.
20.3.
20.4.
20.5.
Features................................................................................................................................... 220
Overview.................................................................................................................................. 220
SS Pin Functionality................................................................................................................. 224
Data Modes.............................................................................................................................. 224
Register Description................................................................................................................. 225
21. Universal Synchronous Asynchronous Receiver Transceiver (USART)............... 230
21.1. Features................................................................................................................................... 230
21.2. Overview.................................................................................................................................. 230
21.3. Block Diagram.......................................................................................................................... 230
21.4. Clock Generation......................................................................................................................231
21.5. Frame Formats.........................................................................................................................234
21.6. USART Initialization................................................................................................................. 235
21.7. Data Transmission – The USART Transmitter......................................................................... 236
21.8. Data Reception – The USART Receiver.................................................................................. 238
21.9. Asynchronous Data Reception.................................................................................................242
21.10. Multi-Processor Communication Mode.................................................................................... 245
21.11. Examples of Baud Rate Setting............................................................................................... 245
21.12. Register Description.................................................................................................................248
22. USART in SPI (USARTSPI) Mode.........................................................................258
22.1.
22.2.
22.3.
22.4.
22.5.
22.6.
22.7.
22.8.
Features................................................................................................................................... 258
Overview.................................................................................................................................. 258
Clock Generation......................................................................................................................258
SPI Data Modes and Timing.....................................................................................................259
Frame Formats.........................................................................................................................259
Data Transfer............................................................................................................................261
AVR USART MSPIM vs. AVR SPI............................................................................................262
Register Description................................................................................................................. 263
23. Two-Wire Serial Interface (TWI)............................................................................ 264
23.1.
23.2.
23.3.
23.4.
23.5.
23.6.
23.7.
23.8.
23.9.
Features................................................................................................................................... 264
Two-Wire Serial Interface Bus Definition..................................................................................264
Data Transfer and Frame Format.............................................................................................265
Multi-Master Bus Systems, Arbitration, and Synchronization...................................................268
Overview of the TWI Module.................................................................................................... 270
Using the TWI...........................................................................................................................272
Transmission Modes................................................................................................................ 275
Multi-Master Systems and Arbitration...................................................................................... 293
Register Description................................................................................................................. 294
24. Analog Comparator (AC)....................................................................................... 302
24.1. Overview.................................................................................................................................. 302
24.2. Analog Comparator Multiplexed Input...................................................................................... 302
24.3. Register Description................................................................................................................. 303
25. Analog-to-Digital Converter (ADC)........................................................................ 307
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Datasheet Complete
DS40002012A-page 6
ATmega324P/V
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
25.7.
25.8.
Features................................................................................................................................... 307
Overview.................................................................................................................................. 307
Starting a Conversion...............................................................................................................309
Prescaling and Conversion Timing...........................................................................................310
Changing Channel or Reference Selection.............................................................................. 314
ADC Noise Canceler................................................................................................................ 315
ADC Conversion Result........................................................................................................... 319
Register Description................................................................................................................. 321
26. JTAG Interface and On-chip Debug System......................................................... 330
26.1. Features................................................................................................................................... 330
26.2. Overview.................................................................................................................................. 330
26.3. Test Access Port (TAP)............................................................................................................ 331
26.4. TAP Controller.......................................................................................................................... 333
26.5. Using the Boundary-scan Chain...............................................................................................334
26.6. Using the On-Chip Debug System........................................................................................... 334
26.7. On-Chip Debug Specific JTAG Instructions............................................................................. 335
26.8. Using the JTAG Programming Capabilities.............................................................................. 336
26.9. Bibliography..............................................................................................................................336
26.10. IEEE 1149.1 (JTAG) Boundary-Scan....................................................................................... 336
26.11. Data Registers..........................................................................................................................337
26.12. Boundry-Scan Specific JTAG Instructions............................................................................... 339
26.13. Boundary-Scan Chain.............................................................................................................. 340
26.14. ATmega324P/V Boundary-scan Order.....................................................................................343
26.15. Boundary-scan Description Language Files............................................................................ 345
26.16. Register Description.................................................................................................................345
27. Boot Loader Support – Read-While-Write Self-programming (BTLDR)................ 350
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
27.7.
27.8.
27.9.
Features................................................................................................................................... 350
Overview.................................................................................................................................. 350
Application and Boot Loader Flash Sections............................................................................350
Read-While-Write and No Read-While-Write Flash Sections...................................................351
Entering the Boot Loader Program...........................................................................................353
Boot Loader Lock Bits.............................................................................................................. 354
Addressing the Flash During Self-Programming...................................................................... 355
Self-Programming the Flash.....................................................................................................356
Register Description................................................................................................................. 364
28. Memory Programming (MEMPROG).....................................................................367
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
28.9.
Program And Data Memory Lock Bits...................................................................................... 367
Fuse Bits.................................................................................................................................. 368
Signature Bytes........................................................................................................................ 370
Calibration Byte........................................................................................................................ 371
Serial Number.......................................................................................................................... 371
Page Size................................................................................................................................. 371
Parallel Programming Parameters, Pin Mapping, and Commands..........................................371
Parallel Programming...............................................................................................................374
Serial Downloading.................................................................................................................. 381
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 7
ATmega324P/V
28.10. Programming Via the JTAG Interface...................................................................................... 385
29. Electrical Characteristics....................................................................................... 400
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
29.7.
29.8.
29.9.
Absolute Maximum Ratings......................................................................................................400
DC Characteristics................................................................................................................... 400
Speed Grades.......................................................................................................................... 403
Clock Characteristics................................................................................................................403
System and Reset Characteristics........................................................................................... 404
External interrupts characteristics............................................................................................ 405
SPI Timing Characteristics....................................................................................................... 405
Two-wire Serial Interface Characteristics................................................................................. 407
ADC characteristics..................................................................................................................409
30. Typical Characteristics...........................................................................................414
30.1. Active Supply Current...............................................................................................................414
30.2. Idle Supply Current...................................................................................................................417
30.3. Supply Current of I/O Modules................................................................................................. 419
30.4. Power-down Supply Current.................................................................................................... 420
30.5. Power-save Supply Current..................................................................................................... 421
30.6. Standby Supply Current........................................................................................................... 422
30.7. Pin Pull-Up............................................................................................................................... 422
30.8. Pin Driver Strength................................................................................................................... 425
30.9. Pin Threshold and Hysteresis.................................................................................................. 427
30.10. BOD Threshold........................................................................................................................ 430
30.11. Internal Oscillator Speed.......................................................................................................... 432
30.12. Current Consumption of Peripheral Units................................................................................ 434
30.13. Current Consumption in Reset and Reset Pulse Width........................................................... 437
31. Register Summary.................................................................................................439
32. Instruction Set Summary....................................................................................... 443
33. Packaging Information...........................................................................................448
33.1. 40-pin PDIP.............................................................................................................................. 448
33.2. 44-pin TQFP.............................................................................................................................449
33.3. 44-pin VQFN............................................................................................................................ 449
34. Errata.....................................................................................................................451
34.1. Rev. A.......................................................................................................................................451
35. Datasheet Revision History................................................................................... 452
35.1. Rev. A – 3/2018........................................................................................................................452
35.2. Pre Microchip Revisions...........................................................................................................452
The Microchip Web Site.............................................................................................. 453
Customer Change Notification Service........................................................................453
Customer Support....................................................................................................... 453
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Datasheet Complete
DS40002012A-page 8
ATmega324P/V
Microchip Devices Code Protection Feature............................................................... 453
Legal Notice.................................................................................................................454
Trademarks................................................................................................................. 454
Quality Management System Certified by DNV...........................................................455
Worldwide Sales and Service......................................................................................456
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 9
ATmega324P/V
Description
1.
Description
The ATmega324P/V is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega324P/V achieves
throughputs close to 1 MIPS per MHz. This empowers the system designer to optimize the device for
power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega324P/V provides the following features: 32Kbytes of in-system programmable Flash with
read-while-write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 32 general purpose I/O lines, 32
general purpose working registers, real time counter (RTC), three flexible timer/counters with compare
modes and PWM, two serial programmable USARTs , one byte-oriented 2-wire serial interface (I2C), a 8channel 10-bit ADC with optional differential input stage with programmable gain, a programmable
watchdog timer with internal oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface,
also used for accessing the on-chip debug system and programming and six software selectable PowerSaving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port, and
interrupt system to continue functioning. The Power-Down mode saves the register contents but freezes
the oscillator, disabling all other chip functions until the next interrupt or hardware Reset. In Power-Save
mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest
of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except the
asynchronous timer and ADC to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low power consumption. In Extended Standby mode, both the main oscillator and the
asynchronous timer continue to run.
®
Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust
sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression™
(AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain
allows you to explore, develop and debug your own touch applications.
The device is manufactured using Microchip’s high density nonvolatile memory technology. The on-chip
ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by
a conventional nonvolatile memory programmer, or by an on-chip boot program running on the AVR core.
The boot program can use any interface to download the application program in the application Flash
memory. Software in the boot Flash section will continue to run while the application Flash section is
updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-system self
programmable Flash on a monolithic chip, the ATmega324P/V is a powerful microcontroller that provides
a highly flexible and cost effective solution to many embedded control applications.
The ATmega324P/V is supported with a full suite of program and system development tools including: C
Compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 10
ATmega324P/V
Configuration Summary
2.
Configuration Summary
The table below compares the device series of feature and pin compatible devices, providing a seamless
migration path.
Table 2-1. Configuration Summary and Device Comparison
Features
ATmega164P/V
ATmega324P/V
ATmega644P/V
Pin Count
40/44
40/44
40/44
Flash (Bytes)
16K
32K
64K
SRAM (Bytes)
1K
2K
4K
EEPROM (Bytes)
512
1K
2K
General Purpose I/O
Lines
32
32
32
SPI
1
1
1
TWI (I2C)
1
1
1
USART
2
2
2
10-bit 15ksps
10-bit 15ksps
10-bit 15ksps
ADC Channels
8
8
8
Analog Comparator
1
1
1
8-bit Timer/Counters
2
2
2
16-bit Timer/Counters
1
1
1
PWM channels
6
6
6
PDIP
PDIP
PDIP
TQFP
TQFP
TQFP
VQFN/QFN
VQFN/QFN
VQFN/QFN
ADC
Packages
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 11
ATmega324P/V
Ordering Information
3.
Ordering Information
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
10
1.8 - 5.5
ATmega324PV-10AU
TQFP (44A)
Industrial
(-40°C to 85°C)
ATmega324PV-10AUR(4)
TQFP (44A)
ATmega324PV-10PU
PDIP (40P6)
ATmega324PV-10MU
VQFN (44M1)
ATmega324PV-10MUR(4)
VQFN (44M1)
ATmega324P-20AU
TQFP (44A)
ATmega324P-20AUR(4)
TQFP (44A)
ATmega324P-20PU
PDIP (40P6)
ATmega324P-20MU
VQFN (44M1)
ATmega324P-20MUR(4)
VQFN (44M1)
ATmega324PV-10AN
TQFP (44A)
ATmega324PV-10ANR(4)
TQFP (44A)
ATmega324PV-10PN
PDIP (40P6)
ATmega324PV-10MN
VQFN (44M1)
ATmega324PV-10MNR(4)
VQFN (44M1)
ATmega324P-20AN
TQFP (44A)
ATmega324P-20ANR(4)
TQFP (44A)
ATmega324P-20PN
PDIP (40P6)
ATmega324P-20MN
VQFN (44M1)
ATmega324P-20MNR(4)
VQFN (44M1)
20
10
20
2.7 - 5.5
1.8 - 5.5
2.7 - 5.5
Industrial
(-40°C to 85°C)
Industrial
(-40°C to 105°C)
Industrial
(-40°C to 105°C)
Note:
1. This device can also be supplied in wafer form. Please contact your local sales office for detailed
ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 12
ATmega324P/V
Ordering Information
Package Type
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44A
44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
44M1 44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat NoLead (VQFN)
Related Links
29.3 Speed Grades
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 13
ATmega324P/V
Block Diagram
4.
Block Diagram
Figure 4-1. Block Diagram
SRAM
TCK
TMS
TDI
TDO
JTAG
CPU
OCD
Clock generation
TOSC1
32.768kHz
XOSC
TOSC2
XTAL1
16MHz LP
XOSC
XTAL2
VCC
RESET
GND
8MHz
Calib RC
128kHz int
osc
External
clock
Power
Supervision
POR/BOD &
RESET
ADC[7:0]
AREF
PCINT[31:0]
INT[2:0]
OC1A/B
T1
ICP1
OC2A
OC2B
© 2018 Microchip Technology Inc.
NVM
programming
Power
management
and clock
control
Watchdog
Timer
ADC
EXTINT
TC 1
(16-bit)
TC 2
(8-bit async)
FLASH
D
A
T
A
B
U
S
EEPROM
EEPROMIF
I/O
PORTS
I
N
/
O
U
T
GPIOR[2:0]
D
A
T
A
B
U
S
TC 0
(8-bit)
SPI
AC
Internal
Reference
USART 0
RxD0
TxD0
XCK0
USART 1
RxD1
TxD1
XCK1
TWI
Datasheet Complete
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
T0
OC0A
OC0B
MISO
MOSI
SCK
SS
AIN0
AIN1
ACO
ADCMUX
SDA
SCL
DS40002012A-page 14
ATmega324P/V
Pin Configurations
5.
Pin Configurations
5.1
Pinout
5.1.1
PDIP
(PCINT8/XCK0/T0)
(ADC0/PCINT0)
(PCINT9/CLKO/T1)
(ADC1/PCINT1)
(PCINT10/INT2/AIN0)
(ADC2/PCINT2)
(PCINT11/OC0A/AIN1)
(ADC3/PCINT3)
(PCINT12/OC0B/
(ADC4/PCINT4)
(PCINT13/MOSI)
(ADC5/PCINT5)
(PCINT14/MISO)
(ADC6/PCINT6)
(PCINT15//SCK)
(ADC7/PCINT7)
XTAL2
(TOSC2/PCINT23)
XTAL1
(TOSC1/PCINT22)
(PCINT24/RXD0)
(TDI/PCINT21)
(PCINT25/TXD0)
(TDO/PCINT20)
(PCINT26/RXD1/INT0)
(TMS/PCINT19)
(PCINT27/TXD1/INT1)
(TCK/PCINT18)
(PCINT28/XCK1/OC1B)
(SDA/PCINT17)
(PCINT29/OC1A)
(SCL/PCINT16)
(PCINT30/OC2B/ICP1)
© 2018 Microchip Technology Inc.
(OC2A/PCINT31)
Datasheet Complete
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
DS40002012A-page 15
ATmega324P/V
Pin Configurations
PB1 (T1/CLKO/PCINT9)
PB0 (XCK0/T0/PCINT8)
GND
VCC
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
41
40
39
38
37
36
35
34
Crystal/Osc
PB2 (AIN0/INT2/PCINT10)
Analog
42
Digital
PB3 (AIN1/OC0A/PCINT11)
Programming/debug
43
Ground
PB4 (SS/OC0B/PCINT12)
Power
44
TQFN and QFN
6
28
GND
XTAL2
7
27
AVCC
XTAL1
8
26
PC7 (TOSC2/PCINT23)
(PCINT24/RXD0) PD0
9
25
PC6 (TOSC1/PCINT22)
(PCINT25/TXD0) PD1
10
24
PC5 (TDI/PCINT21)
(PCINT26/RXD1/INT0) PD2
11
23
PC4 (TDO/PCINT20)
5.2
Pin Descriptions
5.2.1
VCC
Digital supply voltage pin.
5.2.2
GND
Ground.
© 2018 Microchip Technology Inc.
22
GND
(PCINT19/TMS) PC3
AREF
21
29
(PCINT18/TCK) PC2
5
20
VCC
(PCINT17/SDA) PC1
PA7 (ADC7/PCINT7)
19
30
(PCINT16/SCL) PC0
4
18
RESET
GND
PA6 (ADC6/PCINT6)
17
31
VCC
3
16
(PCINT15/SCK) PB7
(PCINT31/OC2A) PD7
PA5 (ADC5/PCINT5)
15
32
(PCINT30/OC2B/ICP1) PD6
2
14
(PCINT14/MISO) PB6
(PCINT29/OC1A) PD5
PA4 (ADC4/PCINT4)
13
33
(PCINT28/XCK1/OC1B) PD4
1
12
(PCINT13/MOSI) PB5
(PCINT27/TXD1/INT1) PD3
5.1.2
Datasheet Complete
DS40002012A-page 16
ATmega324P/V
Pin Configurations
5.2.3
Port A (PA[7:0])
This port serves as analog inputs to the analog-to-digital converter.
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a Reset condition, even if the clock is not running.
5.2.4
Port B (PB[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated during a Reset condition, even if the clock is not running.
This port also serves the functions of various special features.
5.2.5
Port C (PC[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if the pull-up resistors are activated.
Port pins are tri-stated during a Reset condition, even if the clock is not running.
This port also serves the functions of the JTAG interface, along with special features.
5.2.6
Port D (PD[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each pin.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if the pull-up resistors are activated.
Port pins are tri-stated during a Reset condition, even if the clock is not running.
This port also serves the functions of various special features.
5.2.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even
if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
5.2.8
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
5.2.9
XTAL2
Output from the inverting oscillator amplifier.
5.2.10
AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-Digital Converter (ADC). It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to
VCC through a low-pass filter.
5.2.11
AREF
This is the analog reference pin for the analog-to-digital converter.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 17
ATmega324P/V
I/O Multiplexing
6.
I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
40-pin PDIP Pin #
PAD
1
6
PB[5]
PCINT13
MOSI
2
7
PB[6]
PCINT14
MISO
3
8
PB[7]
PCINT15
SCK
4
9
RESET
5
10
VCC
6
11
GND
7
12
XTAL2
8
13
XTAL1
9
14
PD[0]
PCINT24
RxD0
10
15
PD[1]
PCINT25
TxD0
11
16
PD[2]
INT0
PCINT26
RxD1
12
17
PD[3]
INT1
PCINT27
13
18
PD[4]
PCINT28
OC1B
14
19
PD[5]
PCINT29
OC1A
15
20
PD[6]
PCINT30
OC2B
16
21
PD[7]
PCINT31
OC2A
17
-
VCC
18
-
GND
19
22
PC[0]
PCINT16
SCL
20
23
PC[1]
PCINT17
SDA
21
24
PC[2]
PCINT18
TCK
22
25
PC[3]
PCINT19
TMS
23
26
PC[4]
PCINT20
TDO
24
27
PC[5]
PCINT21
TDI
25
28
PC[6]
PCINT22
TOSC1
26
29
PC[7]
PCINT23
TOSC2
27
30
AVCC
28
31
GND
29
32
AREF
30
33
PA[7]
PCINT7
ADC7
31
34
PA[6]
PCINT6
ADC6
32
35
PA[5]
PCINT5
ADC5
33
36
PA[4]
PCINT4
ADC4
34
37
PA[3]
PCINT3
ADC3
© 2018 Microchip Technology Inc.
EXTINT
PCINT
ADC/AC
OSC
T/C # 0
T/C # 1
USART
I2C
32-pin TQFP/QFN Pin #
SPI
JTAG
TXD1
XCK1
ICP1
AREF
Datasheet Complete
DS40002012A-page 18
ATmega324P/V
I/O Multiplexing
32-pin TQFP/QFN Pin #
40-pin PDIP Pin #
PAD
35
38
36
PCINT
ADC/AC
PA[2]
PCINT2
ADC2
39
PA[1]
PCINT1
ADC1
37
40
PA[0]
PCINT0
ADC0
38
-
VCC
39
-
GND
40
1
PB[0]
PCINT8
41
2
PB[1]
PCINT9
42
3
PB[2]
43
4
44
5
© 2018 Microchip Technology Inc.
EXTINT
INT2
OSC
T/C # 0
T/C # 1
T0
CLKO
PCINT10
AIN0
PB[3]
PCINT11
AIN1
PB[4]
PCINT12
USART
I2C
SPI
JTAG
XCK0
T1
OC0A
OC0B
Datasheet Complete
SS
DS40002012A-page 19
ATmega324P/V
General Information
7.
General Information
7.1
Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.microchip.com/design-centers/8-bit/microchip-avr-mcus.
7.2
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Refer to the C compiler documentation for more details.
For I/O Registers located in extended I/O map, IN, OUT, SBIS, SBIC, CBI, and SBI instructions must be
replaced with instructions that allow access to extended I/O. Typically LDS and STS combined with SBRS,
SBRC, SBR, and CBR.
7.3
Capacitive Touch Sensing
7.3.1
QTouch Library
®
®
The QTouch library provides a simple to use solution to realize touch sensitive interfaces on most AVR
™
microcontrollers. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and
then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor
states.
The QTouch library is FREE and downloadable from QTouch Library . For implementation details and
other information, refer to the QTouch Library User Guide, also available for download from the Microchip
website.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 20
ATmega324P/V
AVR CPU Core
8.
AVR CPU Core
8.1
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must, therefore, be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 8-1. Block Diagram of the AVR Architecture
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R18
R16
R14
R12
R10
R8
R6
R4
R2
R0
Program
counter
Flash program
memory
Instruction
register
Instruction
decode
Data memory
Stack
pointer
Status
register
ALU
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the register file, the operation is executed, and the result is
stored back in the register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space
addressing – enabling efficient address calculations. One of these address pointers can be used as an
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 21
ATmega324P/V
AVR CPU Core
address pointer for lookup tables in Flash program memory. These added function registers are the 16-bit
X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided into two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently, the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the Stack
Pointer (SP) in the Reset routine (before subroutines or interrupts are executed). The SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status register. All interrupts have a separate interrupt vector in the interrupt vector table.
The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt
vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control registers, SPI, and
other I/O functions. The I/O memory can be accessed directly, or as the data space locations following
those of the register file, 0x20 - 0x5F. In addition, this device has extended I/O space from 0x60 - 0xFF in
SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.2
Arithmetic Logic Unit (ALU)
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories: arithmetic, logical, and bit-functions. Some implementations of the architecture provide a
powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction
Set Summary section for a detailed description.
Related Links
32. Instruction Set Summary
8.3
Status Register
The Status register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status register is updated after all ALU operations, as specified in the instruction set
reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 22
ATmega324P/V
AVR CPU Core
The Status register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 23
ATmega324P/V
AVR CPU Core
8.3.1
Status Register
Name:
Offset:
Reset:
Property:
SREG
0x5F
0x00
When addressing as I/O register: address offset is 0x3F
When addressing I/O registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Bit
Access
Reset
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – I Global Interrupt Enable
The Global Interrupt Enable bit must be set for interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared,
none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a
bit in T can be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry flag is useful in BCD
arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag
V. See the Instruction Set Description for detailed information.
Bit 3 – V Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 24
ATmega324P/V
AVR CPU Core
Bit 0 – C Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
8.4
General Purpose Register File
The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the register file:
•
•
•
•
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 8-2. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them
are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user data space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
8.4.1
The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 25
ATmega324P/V
AVR CPU Core
Figure 8-3. The X-, Y-, and Z-registers
15
X-register
0
7
R26
YH
YL
0
7
R28
ZH
ZL
0
7
R31
0
0
R29
7
0
0
R27
7
15
Z-register
XL
7
15
Y-register
XH
0
0
R30
In the different addressing modes, these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
32. Instruction Set Summary
8.5
Stack Pointer
The stack is mainly used for storing temporary data, local variables, and return addresses after interrupts
and subroutine calls. The stack is implemented as growing from higher to lower memory locations. The
Stack Pointer register always points to the top of the stack.
The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are
located. A stack PUSH command will decrease the stack pointer. The stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial stack
pointer value equals the last address of the internal SRAM and the stack pointer must be set to point
above start of the SRAM. See the table for stack pointer details.
Table 8-1. Stack Pointer Instructions
Instruction Stack Pointer
Description
PUSH
Decremented by 1 Data is pushed onto the stack
CALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
ICALL
RCALL
POP
Incremented by 1
Data is popped from the stack
RET
Incremented by 2
Return address is popped from the stack with return from subroutine or
return from interrupt
RETI
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 26
ATmega324P/V
AVR CPU Core
The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH register will not be present.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 27
ATmega324P/V
AVR CPU Core
8.5.1
Stack Pointer Register Low and High byte
Name:
Offset:
Reset:
Property:
SPL and SPH
0x5D
0x8FF
When addressing I/O Registers as data space the offset address is 0x3D
The SPL and SPH register pair represents the 16-bit value, SP. The low byte [7:0] (suffix L) is accessible
at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on
reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in Opcode for the IN and OUT instructions. For the extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
RW
RW
Reset
0
0
0
0
RW
RW
1
0
0
0
Bit
7
6
5
4
3
2
1
0
SP[11:8]
SP[7:0]
Access
Reset
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
Bits 11:0 – SP[11:0] Stack Pointer Register
SPL and SPH are combined into SP.
Related Links
17.6 Accessing 16-bit Timer/Counter Registers
8.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal
clock division is used. The figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power unit.
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002012A-page 28
ATmega324P/V
AVR CPU Core
Figure 8-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU
operation using two register operands is executed and the result is stored back to the destination register.
Figure 8-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
8.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset vector
each have a separate program vector in the program memory space. All interrupts are assigned
individual enable bits, which must be written logic one together with the global interrupt enable bit in the
Status register in order to enable the interrupt. Depending on the program counter value, interrupts may
be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and interrupt
vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vectors
can be moved to the start of the boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset vector can be moved to the start of the boot Flash section by programming the
BOOTRST Fuse.
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction
– RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the interrupt flag. For these interrupts, the program
counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and
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Datasheet Complete
DS40002012A-page 29
ATmega324P/V
AVR CPU Core
hardware clears the corresponding interrupt flag. Interrupt flags can be cleared by writing a logic one to
the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt
enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI
instruction. The following example shows how this can be used to avoid interrupts during the timed
EEPROM write sequence.
Assembly Code Example(1)
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example(1)
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1