ATMEGA325V-8AI

Features • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – In-System Self-programmable Flash Program Memory • 32KBytes (ATmega325/ATmega3250) • 64KBytes (ATmega645/ATmega6450) – EEPROM • 1Kbytes (ATmega325/ATmega3250) • 2Kbytes (ATmega645/ATmega6450) – Internal SRAM • 2Kbytes (ATmega325/ATmega3250) • 4Kbytes (ATmega645/ATmega6450) – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security Atmel® QTouch® library support – Capacitive touch buttons, sliders and wheels – QTouch and QMatrix® acquisition – Up to 64 sense channels JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP Speed Grade: – ATmega325V/ATmega3250V/ATmega645V/ATmega6450V: • 0 - 4MHz @ 1.8 - 5.5V; 0 - 8MHz @ 2.7 - 5.5V – Atmel ATmega325/3250/645/6450: • 0 - 8MHz @ 2.7 - 5.5V; 0 - 16MHz @ 4.5 - 5.5V Temperature range: – -40°C to 85°C IndustrSial Ultra-Low Power Consumption – Active Mode: 1MHz, 1.8V: 350µA 32kHz, 1.8V: 20µA (including Oscillator) – Power-down Mode: 100 nA at 1.8V 8-bit Atmel Microcontroller with In-System Programmable Flash ATmega325/V ATmega3250/V ATmega645/V ATmega6450/V Summary 2570NS–AVR–05/11 ATmega325/3250/645/6450 1. Pin Configurations DNC GND VCC DNC PA0 PA1 PA2 81 80 79 78 77 76 DNC 82 DNC PH4 (PCINT20) PF7 (ADC7/TDI) 89 83 PF6 (ADC6/TDO) 90 84 PF5 (ADC5/TMS) 91 PH6 (PCINT22) PF4 (ADC4/TCK) 92 PH5 (PCINT21) PF3 (ADC3) 93 85 PF2 (ADC2) 94 86 PF1(ADC1) 95 DNC PF0 (ADC0) 96 PH7 (PCINT23) AREF 97 87 AGND 98 88 AVCC 99 Pinout ATmega3250/6450 100 Figure 1-1. DNC 1 75 PA3 (RXD/PCINT0) PE0 2 74 PA4 INDEX CORNER (TXD/PCINT1) PE1 3 73 PA5 (XCK/AIN0/PCINT2) PE2 4 72 PA6 (AIN1/PCINT3) PE3 5 71 PA7 (USCK/SCL/PCINT4) PE4 6 70 PG2 (DI/SDA/PCINT5) PE5 7 69 PC7 (DO/PCINT6) PE6 8 68 PC6 (CLKO/PCINT7) PE7 9 67 DNC VCC 10 66 PH3 (PCINT19) GND 11 65 PH2 (PCINT18) DNC 12 64 PH1 (PCINT17) (PCINT24) PJ0 13 63 PH0 (PCINT16) (PCINT25) PJ1 14 62 DNC DNC 15 61 DNC DNC 16 60 DNC DNC 17 59 DNC DNC 18 58 PC5 ATmega3250/6450 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DNC (PCINT26) PJ2 (PCINT27) PJ3 (PCINT28) PJ4 (PCINT29) PJ5 (PCINT30) PJ6 DNC (ICP1) PD0 (INT0) PD1 PD2 PD3 PD4 PD5 PD6 PD7 35 DNC PG0 XTAL1 (TOSC1) 51 34 25 33 (OC1B/PCINT14) PB6 GND PG1 XTAL2 (TOSC2) PC0 52 32 53 24 31 23 (OC1A/PCINT13) PB5 VCC (OC0A/PCINT12) PB4 RESET/PG5 PC1 30 PC2 54 29 55 22 (T0) PG4 21 (MISO/PCINT11) PB3 (T1) PG3 (MOSI/PCINT10) PB2 28 PC3 27 PC4 56 DNC 57 20 26 19 (OC2A/PCINT15) PB7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 2 2570NS–AVR–05/11 ATmega325/3250/645/6450 DNC 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 PA1 PA2 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ATmega325/645 64 Figure 1-2. 48 PA3 47 PA4 INDEX CORNER (TXD/PCINT1) PE1 3 46 PA5 (XCK/AIN0/PCINT2) PE2 4 45 PA6 (AIN1/PCINT3) PE3 5 44 PA7 (USCK/SCL/PCINT4) PE4 6 43 PG2 (DI/SDA/PCINT5) PE5 7 42 PC7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 40 PC5 (SS/PCINT8) PB0 10 39 PC4 (SCK/PCINT9) PB1 11 38 PC3 (MOSI/PCINT10) PB2 12 37 PC2 (MISO/PCINT11) PB3 13 36 PC1 (OC0A/PCINT12) PB4 14 35 PC0 (OC1A/PCINT13) PB5 15 34 PG1 (OC1B/PCINT14) PB6 16 33 PG0 PD7 32 PD6 31 PD5 30 PD4 29 PD3 28 PD2 27 PD1 (INT0) 26 (ICP1) PD0 25 XTAL1 (TOSC1) 24 XTAL2 (TOSC2) 23 GND 22 VCC 21 RESET/PG5 20 (T0) PG4 19 (T1) PG3 18 (OC2A/PCINT15) PB7 17 Note: 41 PC6 ATmega325/645 The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 3 2570NS–AVR–05/11 ATmega325/3250/645/6450 2. Overview The Atmel ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Block Diagram GND PF0 - PF7 VCC PORTA DRIVERS PORTF DRIVERS DATA DIR. REG. PORTF DATA REGISTER PORTF PC0 - PC7 PA0 - PA7 PORTC DRIVERS DATA DIR. REG. PORTA DATA REGISTER PORTA XTAL2 Figure 2-1. XTAL1 2.1 DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND CALIB. OSC ADC INTERNAL OSCILLATOR AREF STACK POINTER WATCHDOG TIMER ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER BOUNDARYSCAN INSTRUCTION REGISTER TIMING AND CONTROL TIMER/ COUNTERS GENERAL PURPOSE REGISTERS X PROGRAMMING LOGIC INSTRUCTION DECODER CONTROL LINES + - INTERRUPT UNIT ALU EEPROM STATUS REGISTER AVR CPU ANALOG COMPARATOR Z Y RESET DATA DIR. REG. PORTH DATA REGISTER PORTH PROGRAM COUNTER DATA DIR. REG. PORTJ DATA REGISTER PORTJ PORTH DRIVERS PORTJ DRIVERS PJ0 - PJ6 PH0 - PH7 OSCILLATOR JTAG TAP USART UNIVERSAL SERIAL INTERFACE DATA REGISTER PORTE DATA DIR. REG. PORTE PORTE DRIVERS PE0 - PE7 SPI DATA REGISTER PORTB DATA DIR. REG. PORTB PORTB DRIVERS PB0 - PB7 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD0 - PD7 DATA REG. PORTG DATA DIR. REG. PORTG PORTG DRIVERS PG0 - PG4 The Atmel®AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The 4 2570NS–AVR–05/11 ATmega325/3250/645/6450 resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer will continue to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheelsfunctionality into AVR microcontrollers. The patented charge-transfer signal acquisition offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent KeySuppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATmega325/3250/645/6450 is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 5 2570NS–AVR–05/11 ATmega325/3250/645/6450 2.2 Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450 The ATmega325, ATmega3250, ATmega645, and ATmega6450 differ only in memory sizes, pin count and pinout. Table 2-1 on page 6 summarizes the different configurations for the four devices. Table 2-1. 2.3 Configuration Summary General Purpose I/O Pins Device Flash EEPROM RAM ATmega325 32Kbytes 1Kbytes 2Kbytes 54 ATmega3250 32Kbytes 1Kbytes 2Kbytes 69 ATmega645 64Kbytes 2Kbytes 4Kbytes 54 ATmega6450 64Kbytes 2Kbytes 4Kbytes 69 Pin Descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2.3.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the Atmel ATmega325/3250/645/6450 as listed on page 68. 2.3.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 6 2570NS–AVR–05/11 ATmega325/3250/645/6450 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the Atmel ATmega325/3250/645/6450 as listed on page 71. 2.3.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the Atmel ATmega325/3250/645/6450 as listed on page 72. 2.3.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.3.9 Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the Atmel ATmega325/3250/645/6450 as listed on page 72. 2.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3250/6450 as listed on page 72. 7 2570NS–AVR–05/11 ATmega325/3250/645/6450 2.3.11 Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3250/6450 as listed on page 72. 2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page 301. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. 8 2570NS–AVR–05/11 ATmega325/3250/645/6450 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 6. Capacitive touch sensing The Atmel®QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR ® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. 9 2570NS–AVR–05/11 ATmega325/3250/645/6450 7. Register Summary Note: Registers with bold type only available in ATmega3250/6450. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved - - - - - - - - Page (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - - (0xFA) Reserved - - - - - - - - (0xF9) Reserved - - - - - - - - (0xF8) Reserved - - - - - - - - (0xF7) Reserved - - - - - - - - (0xF6) Reserved - - - - - - - - (0xF5) Reserved - - - - - - - - (0xF4) Reserved - - - - - - - - (0xF3) Reserved - - - - - - - - (0xF2) Reserved - - - - - - - - (0xF1) Reserved - - - - - - - - (0xF0) Reserved - - - - - - - - (0xEF) Reserved - - - - - - - - (0xEE) Reserved - - - - - - - - (0xED) Reserved - - - - - - - - (0xEC) Reserved - - - - - - - - (0xEB) Reserved - - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) Reserved - - - - - - - - (0xE6) Reserved - - - - - - - - (0xE5) Reserved - - - - - - - - (0xE4) Reserved - - - - - - - - (0xE3) Reserved - - - - - - - - (0xE2) Reserved - - - - - - - - (0xE1) Reserved - - - - - - - - (0xE0) Reserved - - - - - - - - (0xDF) Reserved - - - - - - - - (0xDE) Reserved - - - - - - - - (0xDD) PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 84 (0xDC) DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 84 (0xDB) PINJ - PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 84 (0xDA) PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 84 (0xD9) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 84 (0xD8) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 84 (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) Reserved - - - - - - - - (0xCD) Reserved - - - - - - - - (0xCC) Reserved - - - - - - - - (0xCB) Reserved - - - - - - - - (0xCA) Reserved - - - - - - - - (0xC9) Reserved - - - - - - - - (0xC8) Reserved - - - - - - - - (0xC7) Reserved - - - - - - - - (0xC6) UDR0 (0xC5) UBRR0H (0xC4) UBRR0L USART0 Data Register 179 USART0 Baud Rate Register High USART0 Baud Rate Register Low 184 184 10 2570NS–AVR–05/11 ATmega325/3250/645/6450 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xC3) Reserved - - - - - - - - Page (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 181 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 180 182 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserved - - - - - - - - (0xBB) Reserved - - - - - - - - (0xBA) USIDR (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 193 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 194 USI Data Register 192 (0xB7) Reserved - - - - - - - - (0xB6) ASSR - - - EXCLK AS2 TCN2UB OCR2UB TCR2UB (0xB5) Reserved - - - - - - - - (0xB4) Reserved - - - - - - - - (0xB3) OCR2A Timer/Counter 2 Output Compare Register A 145 (0xB2) TCNT2 Timer/Counter2 145 (0xB1) Reserved - - - - - - - - (0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 (0xAF) Reserved - - - - - - - - 145 143 (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Timer/Counter1 Output Compare Register B High (0x8A) OCR1BL Timer/Counter1 Output Compare Register B Low 127 (0x89) OCR1AH Timer/Counter1 Output Compare Register A High 127 (0x88) OCR1AL Timer/Counter1 Output Compare Register A Low 127 (0x87) ICR1H Timer/Counter1 Input Capture Register High 127 (0x86) ICR1L Timer/Counter1 Input Capture Register Low 127 (0x85) TCNT1H Timer/Counter1 High 127 127 11 2570NS–AVR–05/11 ATmega325/3250/645/6450 Address Name (0x84) TCNT1L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x83) Reserved - - - - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 126 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 125 123 Timer/Counter1 Low - - Page 127 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 200 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 217 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 213 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 198/217 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High 215 216 (0x78) ADCL (0x77) Reserved - - - ADC Data Register Low - - - - - 216 (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) PCMSK3 - PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 (0x72) Reserved - - - - - - - - (0x71) Reserved - - - - - - - - (0x70) TIMSK2 - - - - - - OCIE2A TOIE2 146 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 128 (0x6E) TIMSK0 - - - - - - OCIE0A TOIE0 99 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 58 (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 59 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 59 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - - - - - ISC01 ISC00 (0x68) Reserved - - - - - - - - (0x67) Reserved - - - - - - - - (0x66) OSCCAL (0x65) Reserved - - - - - - - - Oscillator Calibration Register [CAL7..0] 58 56 32 (0x64) PRR - - - - PRTIM1 PRSPI PSUSART0 PRADC (0x63) Reserved - - - - - - - - 40 (0x62) Reserved - - - - - - - - (0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 32 (0x60) WDTCR - - - WDCE WDE WDP2 WDP1 WDP0 47 I T H S V N Z C 12 0x3F (0x5F) SREG 0x3E (0x5E) SPH Stack Pointer High 0x3D (0x5D) SPL Stack Pointer Low 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) Reserved - - - - - - - - 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - 0x37 (0x57) SPMCSR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 263 0x36 (0x56) Reserved 0x35 (0x55) MCUCR JTD - - PUD - - IVSEL IVCE 53/81/227 0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF 47 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 35 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 223 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 198 0x2F (0x4F) Reserved - - - - - - - - 0x2E (0x4E) SPDR 0x2D (0x4D) SPSR SPIF WCOL - - - - - SPI2X 156 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 154 0x2B (0x4B) GPIOR2 General Purpose I/O Register 0x2A (0x4A) GPIOR1 General Purpose I/O Register 0x29 (0x49) Reserved - - - 0x28 (0x48) Reserved - - - 0x27 (0x47) OCR0A Timer/Counter0 Output Compare A 98 0x26 (0x46) TCNT0 Timer/Counter0 98 14 14 SPI Data Register 156 25 25 - - - - - - - - - - 12 2570NS–AVR–05/11 ATmega325/3250/645/6450 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x25 (0x45) Reserved - - - - - - - - 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 96 0x23 (0x43) GTCCR TSM - - - - - PSR2 PSR10 101/147 0x22 (0x42) EEARH - - - - - 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR - - - - EERIE EEPROM Address Register High Page 22 22 22 EEMWE EEWE EERE General Purpose I/O Register 22 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK PCIE3 PCIE2 PCIE1 PCIE0 - - - INT0 25 57 0x1C (0x3C) EIFR PCIF3 PCIF2 PCIF1 PCIF0 - - - INTF0 57 0x1B (0x3B) Reserved - - - - - - - - 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - - OCF2A TOV2 147 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 128 0x15 (0x35) TIFR0 - - - - - - OCF0A TOV0 99 0x14 (0x34) PORTG - - - PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 83 0x13 (0x33) DDRG - - - DDG4 DDG3 DDG2 DDG1 DDG0 84 0x12 (0x32) PING - - PING5 PING4 PING3 PING2 PING1 PING0 84 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 83 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 83 0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 83 0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 83 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 83 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 83 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 82 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 82 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 83 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 82 82 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 82 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 82 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 82 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 82 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 81 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 81 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 81 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 13 2570NS–AVR–05/11 ATmega325/3250/645/6450 8. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr)