ATmega32A
megaAVR® Data Sheet
Introduction
The ATmega32A is a low power, CMOS 8-bit microcontrollers based on the AVR® enhanced RISC architecture. The ATmega32A is a 40/44-pins device with 32 KB Flash, 2 KB SRAM and 1 KB EEPROM. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million
instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 32Kbytes of In-System Self-programmable Flash program memory
– 1024Bytes EEPROM
– 2Kbytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• QTouch® Library Support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix™ acquisition
– Up to 64 sense channels
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ATmega32A
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels in TQFP Package Only
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
• Operating Voltages
– 2.7V - 5.5V
• Speed Grades
– 0 - 16MHz
• Power Consumption at 1MHz, 3V, 25°C
– Active: 0.6mA
– Idle Mode: 0.2mA
– Power-down Mode: < 1µA
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ATmega32A
Table of Contents
1
Pin Configurations ................................................................................. 10
2
Overview ................................................................................................. 11
2.1
Block Diagram ................................................................................................. 11
2.2
Pin Descriptions............................................................................................... 12
3
Resources ............................................................................................... 13
4
Data Retention ........................................................................................ 13
5
About Code Examples ........................................................................... 14
6
Capacitive touch sensing ...................................................................... 14
7
AVR CPU Core ........................................................................................ 15
8
9
7.1
Overview.......................................................................................................... 15
7.2
ALU – Arithmetic Logic Unit............................................................................. 16
7.3
Status Register ................................................................................................ 16
7.4
General Purpose Register File ........................................................................ 17
7.5
Stack Pointer ................................................................................................... 19
7.6
Instruction Execution Timing ........................................................................... 20
7.7
Reset and Interrupt Handling........................................................................... 21
AVR Memories ........................................................................................ 23
8.1
Overview.......................................................................................................... 23
8.2
In-System Reprogrammable Flash Program Memory ..................................... 23
8.3
SRAM Data Memory........................................................................................ 24
8.4
EEPROM Data Memory .................................................................................. 25
8.5
I/O Memory...................................................................................................... 26
8.6
Register Description ........................................................................................ 27
System Clock and Clock Options ......................................................... 31
9.1
Clock Systems and their Distribution ............................................................... 31
9.2
Clock Sources ................................................................................................. 32
9.3
Default Clock Source....................................................................................... 32
9.4
Crystal Oscillator ............................................................................................. 32
9.5
Low-frequency Crystal Oscillator ..................................................................... 34
9.6
External RC Oscillator ..................................................................................... 34
9.7
Calibrated Internal RC Oscillator ..................................................................... 35
9.8
External Clock ................................................................................................. 36
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ATmega32A
9.9
Timer/Counter Oscillator.................................................................................. 37
9.10
Register Description ........................................................................................ 38
10 Power Management and Sleep Modes ................................................. 39
10.1
Sleep Modes.................................................................................................... 39
10.2
Idle Mode......................................................................................................... 39
10.3
ADC Noise Reduction Mode............................................................................ 40
10.4
Power-down Mode........................................................................................... 40
10.5
Power-save Mode............................................................................................ 40
10.6
Standby Mode ................................................................................................. 40
10.7
Extended Standby Mode ................................................................................. 41
10.8
Minimizing Power Consumption ...................................................................... 41
10.9
Register Description ........................................................................................ 43
11 System Control and Reset .................................................................... 44
11.1
Resetting the AVR ........................................................................................... 44
11.2
Reset Sources ................................................................................................. 44
11.3
Internal Voltage Reference.............................................................................. 47
11.4
Watchdog Timer .............................................................................................. 48
11.5
Register Description ........................................................................................ 49
12 Interrupts ................................................................................................ 51
12.1
Interrupt Vectors in ATmega32A ..................................................................... 51
12.2
Register Description ........................................................................................ 54
13 I/O Ports .................................................................................................. 56
13.1
Overview.......................................................................................................... 56
13.2
Ports as General Digital I/O ............................................................................. 57
13.3
Alternate Port Functions .................................................................................. 61
13.4
Register Description ........................................................................................ 70
14 External Interrupts ................................................................................. 73
14.1
Register Description ........................................................................................ 73
15 8-bit Timer/Counter0 with PWM ............................................................ 76
15.1
Features .......................................................................................................... 76
15.2
Overview.......................................................................................................... 76
15.3
Timer/Counter Clock Sources ......................................................................... 77
15.4
Counter Unit .................................................................................................... 77
15.5
Output Compare Unit....................................................................................... 78
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ATmega32A
15.6
Compare Match Output Unit ............................................................................ 79
15.7
Modes of Operation ......................................................................................... 80
15.8
Timer/Counter Timing Diagrams ..................................................................... 84
15.9
Register Description ........................................................................................ 86
16 Timer/Counter0 and Timer/Counter1 Prescalers ................................ 90
16.1
Overview.......................................................................................................... 90
16.2
Internal Clock Source ...................................................................................... 90
16.3
Prescaler Reset ............................................................................................... 90
16.4
External Clock Source ..................................................................................... 90
16.5
Register Description ........................................................................................ 92
17 16-bit Timer/Counter1 ............................................................................ 93
17.1
Features .......................................................................................................... 93
17.2
Overview.......................................................................................................... 93
17.3
Accessing 16-bit Registers .............................................................................. 95
17.4
Timer/Counter Clock Sources ......................................................................... 98
17.5
Counter Unit .................................................................................................... 98
17.6
Input Capture Unit ........................................................................................... 99
17.7
Compare Match Output Unit .......................................................................... 103
17.8
Modes of Operation ....................................................................................... 104
17.9
Timer/Counter Timing Diagrams ................................................................... 111
17.10
Register Description ...................................................................................... 112
18 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 119
18.1
Features ........................................................................................................ 119
18.2
Overview........................................................................................................ 119
18.3
Timer/Counter Clock Sources ....................................................................... 120
18.4
Counter Unit .................................................................................................. 120
18.5
Output Compare Unit..................................................................................... 121
18.6
Compare Match Output Unit .......................................................................... 123
18.7
Modes of Operation ....................................................................................... 123
18.8
Timer/Counter Timing Diagrams ................................................................... 127
18.9
Asynchronous Operation of the Timer/Counter ............................................. 129
18.10
Timer/Counter Prescaler ............................................................................... 131
18.11
Register Description ...................................................................................... 131
19 SPI – Serial Peripheral Interface ......................................................... 136
19.1
Features ........................................................................................................ 136
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ATmega32A
19.2
Overview........................................................................................................ 136
19.3
SS Pin Functionality ...................................................................................... 140
19.4
Data Modes ................................................................................................... 142
20 USART ................................................................................................... 144
20.1
Features ........................................................................................................ 144
20.2
Overview........................................................................................................ 144
20.3
Clock Generation ........................................................................................... 146
20.4
Frame Formats .............................................................................................. 148
20.5
USART Initialization....................................................................................... 149
20.6
Data Transmission – The USART Transmitter .............................................. 150
20.7
Data Reception – The USART Receiver ....................................................... 153
20.8
Asynchronous Data Reception ...................................................................... 157
20.9
Multi-processor Communication Mode .......................................................... 160
20.10
Accessing UBRRH/UCSRC Registers ......................................................... 161
20.11
Register Description ...................................................................................... 163
20.12
Examples of Baud Rate Setting..................................................................... 167
21 Two-wire Serial Interface ..................................................................... 172
21.1
Features ........................................................................................................ 172
21.2
Two-wire Serial Interface Bus Definition........................................................ 172
21.3
Data Transfer and Frame Format .................................................................. 173
21.4
Multi-master Bus Systems, Arbitration and Synchronization ......................... 175
21.5
Overview of the TWI Module ......................................................................... 177
21.6
Using the TWI................................................................................................ 179
21.7
Transmission Modes ..................................................................................... 181
21.8
Multi-master Systems and Arbitration............................................................ 192
21.9
Register Description ...................................................................................... 195
22 Analog Comparator .............................................................................. 198
22.1
Overview........................................................................................................ 198
22.2
Analog Comparator Multiplexed Input ........................................................... 198
22.3
Register Description ...................................................................................... 199
23 Analog to Digital Converter ................................................................. 201
23.1
Features ........................................................................................................ 201
23.2
Overview........................................................................................................ 201
23.3
Operation....................................................................................................... 202
23.4
Starting a Conversion .................................................................................... 203
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23.5
Prescaling and Conversion Timing ................................................................ 204
23.6
Changing Channel or Reference Selection ................................................... 207
23.7
ADC Noise Canceler ..................................................................................... 208
23.8
ADC Conversion Result................................................................................. 212
23.9
Register Description ...................................................................................... 214
24 JTAG Interface and On-chip Debug System ...................................... 218
24.1
Features ........................................................................................................ 218
24.2
Overview........................................................................................................ 218
24.3
TAP – Test Access Port ................................................................................ 218
24.4
TAP Controller ............................................................................................... 220
24.5
Using the Boundary-scan Chain .................................................................... 221
24.6
Using the On-chip Debug System ................................................................. 221
24.7
On-chip Debug Specific JTAG Instructions ................................................... 222
24.8
Using the JTAG Programming Capabilities ................................................... 222
24.9
Register Description ...................................................................................... 223
24.10
Bibliography................................................................................................... 223
25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 224
25.1
Features ........................................................................................................ 224
25.2
Overview........................................................................................................ 224
25.3
Data Registers............................................................................................... 224
25.4
Boundary-scan Specific JTAG Instructions ................................................... 226
25.5
Boundary-scan Chain .................................................................................... 227
25.6
ATmega32A Boundary-scan Order ............................................................... 237
25.7
Boundary-scan Description Language Files .................................................. 242
25.8
Register Description ...................................................................................... 242
26 Boot Loader Support – Read-While-Write Self-Programming ......... 243
26.1
Features ........................................................................................................ 243
26.2
Overview........................................................................................................ 243
26.3
Application and Boot Loader Flash Sections ................................................. 243
26.4
Read-While-Write and no Read-While-Write Flash Sections ........................ 243
26.5
Boot Loader Lock Bits ................................................................................... 246
26.6
Entering the Boot Loader Program ................................................................ 247
26.7
Addressing the Flash during Self-Programming ............................................ 248
26.8
Self-Programming the Flash .......................................................................... 249
26.9
Register Description ...................................................................................... 254
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27 Memory Programming ......................................................................... 256
27.1
Program And Data Memory Lock Bits ........................................................... 256
27.2
Fuse Bits........................................................................................................ 257
27.3
Signature Bytes ............................................................................................. 258
27.4
Calibration Byte ............................................................................................. 258
27.5
Page Size ...................................................................................................... 259
27.6
Parallel Programming Parameters, Pin Mapping, and Commands ............... 259
27.7
Parallel Programming .................................................................................... 261
27.8
SPI Serial Downloading ................................................................................. 269
27.9
SPI Serial Programming Pin Mapping ........................................................... 269
27.10
Programming via the JTAG Interface ............................................................ 274
28 Electrical Characteristics .................................................................... 286
28.1
Absolute Maximum Ratings* ......................................................................... 286
28.2
DC Characteristics ........................................................................................ 286
28.3
Speed Grades ............................................................................................... 288
28.4
Clock Characteristics..................................................................................... 288
28.5
System and Reset Characteristics ................................................................ 289
28.6
Two-wire Serial Interface Characteristics ...................................................... 289
28.7
SPI Timing Characteristics ............................................................................ 291
28.8
ADC Characteristics ...................................................................................... 293
29 Typical Characteristics ........................................................................ 296
29.1
Active Supply Current .................................................................................... 296
29.2
Idle Supply Current........................................................................................ 299
29.3
Power-down Supply Current.......................................................................... 302
29.4
Power-save Supply Current........................................................................... 303
29.5
Standby Supply Current ................................................................................ 304
29.6
Pin Pull-up ..................................................................................................... 304
29.7
Pin Driver Strength ........................................................................................ 306
29.8
Pin Thresholds and Hysteresis ...................................................................... 308
29.9
BOD Thresholds and Analog Comparator Offset .......................................... 311
29.10
Internal Oscillator Speed ............................................................................... 313
29.11
Current Consumption of Peripheral Units ...................................................... 319
29.12
Current Consumption in Reset and Reset Pulsewidth .................................. 322
30 Register Summary ............................................................................... 324
31 Instruction Set Summary ..................................................................... 326
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ATmega32A
32 Ordering Information ........................................................................... 329
33 Packaging Information ........................................................................ 330
33.1
44A ................................................................................................................ 330
33.2
40P6 .............................................................................................................. 331
33.3
44M1.............................................................................................................. 332
34 Errata ..................................................................................................... 333
34.1
ATmega32A, rev. J to rev. K ......................................................................... 333
34.2
ATmega32A, rev. G to rev. I .......................................................................... 334
35 Datasheet Revision History ................................................................. 335
35.1
Rev. A – 11/2018 ........................................................................................... 335
35.2
Rev. 8155E – 02/2014................................................................................... 335
35.3
Rev. 8155D – 10/2013................................................................................... 335
35.4
Rev. 8155C – 02/2011................................................................................... 335
35.5
Rev. 8155B – 07/2009................................................................................... 335
35.6
Rev. 8155A – 06/2008................................................................................... 336
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DS40002072A-page 9
ATmega32A
1. Pin Configurations
Figure 1-1.
Pinout ATmega32A
PDIP
(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
PB4 (SS)
PB3 (AIN1/OC0)
PB2 (AIN0/INT2)
PB1 (T1)
PB0 (XCK/T0)
GND
VCC
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
TQFP/MLF
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(RXD) PD0
(TXD) PD1
(INT0) PD2
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PD3
PD4
PD5
PD6
PD7
VCC
GND
(SCL) PC0
(SDA) PC1
(TCK) PC2
(TMS) PC3
(INT1)
(OC1B)
(OC1A)
(ICP1)
(OC2)
Note:
Bottom pad should
be soldered to ground.
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
GND
AVCC
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
Data Sheet Complete
DS40002072A-page 10
ATmega32A
2. Overview
The AVR® ATmega32A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32A achieves throughputs approaching
1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
PA0 - PA7
PC0 - PC7
PORTA DRIVERS/BUFFERS
PORTC DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
PORTC DIGITAL INTERFACE
VCC
GND
AVCC
MUX &
ADC
ADC
INTERFACE
TWI
AREF
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
TIMERS/
COUNTERS
OSCILLATOR
INTERNAL
OSCILLATOR
XTAL1
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
WATCHDOG
TIMER
OSCILLATOR
XTAL2
X
INSTRUCTION
DECODER
Y
MCU CTRL.
& TIMING
RESET
Z
CONTROL
LINES
ALU
AVR CPU
STATUS
REGISTER
EEPROM
PROGRAMMING
LOGIC
SPI
USART
+
-
INTERNAL
CALIBRATED
OSCILLATOR
INTERRUPT
UNIT
COMP.
INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
PB0 - PB7
PD0 - PD7
The AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
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DS40002072A-page 11
ATmega32A
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega32A provides the following features: 32Kbytes of In-System Programmable Flash Program memory
with Read-While-Write capabilities, 1024bytes EEPROM, 2Kbyte SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming,
three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable
USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage
with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI
serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the
USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching
noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby
mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Microchip’s high density nonvolatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use
any interface to download the application program in the Application Flash memory. Software in the Boot Flash
section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the
ATmega32A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.
The AVR ATmega32A is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2.2
Pin Descriptions
2.2.1
VCC
Digital supply voltage.
2.2.2
GND
Ground.
2.2.3
Port A (PA7:PA0)
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal
pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both
high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will
source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
2.2.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
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DS40002072A-page 12
ATmega32A
Port B also serves the functions of various special features of the ATmega32A as listed on page 64.
2.2.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a
reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.
The TD0 pin is tri-stated unless TAP states that shift out data are entered.
Port C also serves the functions of the JTAG interface and other special features of the ATmega32A as listed on
page 66.
2.2.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega32A as listed on page 68.
2.2.7
RESET
Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in Table 28-3 on page 289. Shorter pulses are not ensured to
generate a reset.
2.2.8
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.9
XTAL2
Output from the inverting Oscillator amplifier.
2.2.10
AVCC
AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if
the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.2.11
AREF
AREF is the analog reference pin for the A/D Converter.
3. Resources
A comprehensive set of development tools, application notes and data sheets are available for download on
http://www.microchip.com.
Note:
1.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
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Data Sheet Complete
DS40002072A-page 13
ATmega32A
5. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C Compiler documentation for more details.
6. Capacitive touch sensing
The QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix™ acquisition methods.
Touch sensing can be added to any application by linking the appropriate QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Microchip website at the following location
http://www.microchip.com. For implementation details and other information, refer to the QTouch Library User
Guide - also available for download from the Microchip website.
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Data Sheet Complete
DS40002072A-page 14
ATmega32A
7. AVR CPU Core
Overview
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
Figure 7-1.
Block Diagram of the AVR MCU Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Instruction
Decoder
Control Lines
Indirect Addressing
Instruction
Register
Direct Addressing
7.1
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
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Data Sheet Complete
DS40002072A-page 15
ATmega32A
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in
the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have
priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.
7.2
7.3
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the AVR Instruction Set Manual on www.microchip.com
for a detailed description.
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the AVR Instruction Set Manual. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
7.3.1
SREG – AVR Status Register(1)
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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SREG
DS40002072A-page 16
ATmega32A
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Manual on
www.microchip.com.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a half carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation.
Note:
7.4
1. Refer to the AVR Instruction Set Manual on www.microchip.com for more details.
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.
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Data Sheet Complete
DS40002072A-page 17
ATmega32A
Figure 7-2.
AVR CPU General Purpose Working Registers
7
0
Addr.
R0
$00
R1
$01
R2
$02
…
R13
$0D
General
R14
$0E
Purpose
R15
$0F
Working
R16
$10
Registers
R17
$11
…
R26
$1A
X-register Low Byte
R27
$1B
X-register High Byte
R28
$1C
Y-register Low Byte
R29
$1D
Y-register High Byte
R30
$1E
Z-register Low Byte
R31
$1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.
As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to
index any register in the file.
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Data Sheet Complete
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ATmega32A
7.4.1
The X-register, Y-register and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are
defined as described in Figure 7-3.
Figure 7-3.
The X-, Y-, and Z-registers
15
X - register
XH
7
XL
0
R27 ($1B)
15
Y - register
0
R26 ($1A)
YH
7
YL
0
R29 ($1D)
Z - register
0
7
0
7
0
R28 ($1C)
15
ZH
7
0
R31 ($1F)
ZL
7
0
0
R30 ($1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the AVR Instruction Set Manual on www.microchip.com for details).
7.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory
locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data
SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease
the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts
are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be
set to point above start of the SRAM, see Figure 8-2 on page 24.
See Table 7-1 on page 19 for Stack Pointer details.
Table 7-1.
Stack Pointer instructions
Instruction
Stack pointer
Description
PUSH
Decremented by 1
Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2
Return address is pushed onto the stack with a subroutine call or
interrupt
POP
Incremented by 1
Data is popped from the stack
RET
RETI
Incremented by 2
Return address is popped from the stack with return from
subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
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Data Sheet Complete
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ATmega32A
7.5.1
SPH and SPL – Stack Pointer High and Low Register
Bit
Read/Write
Initial Value
7.6
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 7-4.
The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 7-5.
Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
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Data Sheet Complete
DS40002072A-page 20
ATmega32A
7.7
Reset and Interrupt Handling
The AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits
BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 256 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in “Interrupts” on page 51. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 51 for
more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the
BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 243.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is
set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR® exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002072A-page 21
ATmega32A
Assembly Code Example
in r16, SREG
cli
; store SREG value
; disable interrupts during timed sequence
sbi EECR, EEMWE
; start EEPROM write
sbi EECR, EEWE
out SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
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