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ATMEGA644PA-MUR

ATMEGA644PA-MUR

  • 厂商:

    ACTEL(微芯科技)

  • 封装:

    VFQFN44

  • 描述:

    IC MCU 8BIT 64KB FLASH 44VQFN

  • 数据手册
  • 价格&库存
ATMEGA644PA-MUR 数据手册
ATmega164A/PA/324A/PA/644A/PA/1284/P megaAVR® Data Sheet Introduction The ATmega164A/PA/324A/PA/644A/PA/1284/P is a low power, CMOS 8-bit microcontrollers based on the AVR® enhanced RISC architecture. The ATmega164A/PA/324A/PA/644A/PA/1284/P is a 40/49-pins device ranging from 16 KB to 128 KB Flash, with 1 KB to 16 KB SRAM, 512 Bytes to 4 KB EEPROM. By executing instructions in a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. Features  High-performance, low-power 8-bit AVR® Microcontroller  Advanced RISC architecture  131 powerful Instructions – most single-clock cycle execution  32 × 8 general purpose working registers  Fully static operation  Up to 20MIPS throughput at 20MHz  On-chip 2-cycle multiplier  High endurance non-volatile memory segments  16/32/64/128KBytes of In-System Self-programmable Flash program memory  512/1K/2K/4KBytes EEPROM  1/2/4/16KBytes Internal SRAM  Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM  Data retention: 20 years at 85°C/ 100 years at 25°C(1)  Optional Boot Code Section with Independent Lock Bits   In-System Programming by On-chip Boot Program  True Read-While-Write Operation Programming Lock for Software Security  QTouch® Library Support  Capacitive touch buttons, sliders and wheels  QTouch and QMatrix™ acquisition  Up to 64 sense channels  JTAG (IEEE std. 1149.1 Compliant) Interface  Boundary-scan Capabilities According to the JTAG Standard  Extensive On-chip Debug Support  Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 1 ATmega164A/PA/324A/PA/644A/PA/1284/P  Peripheral Features  Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes  One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode  Real Time Counter with Separate Oscillator  Six PWM Channels  8-channel, 10-bit ADC  Differential mode with selectable gain at 1×, 10× or 200×  Byte-oriented Two-wire Serial Interface  Two Programmable Serial USART  Master/Slave SPI Serial Interface  Programmable Watchdog Timer with Separate On-chip Oscillator  On-chip Analog Comparator  Interrupt and Wake-up on Pin Change  Special Microcontroller Features  Power-on Reset and Programmable Brown-out Detection  Internal Calibrated RC Oscillator  External and Internal Interrupt Sources  Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby  I/O and Packages  32 Programmable I/O Lines  40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF  44-pad DRQFN  49-ball VFBGA  Operating Voltages  1.8 - 5.5V  Speed Grades  0 - 4MHz @ 1.8 - 5.5V  0 - 10MHz @ 2.7 - 5.5V  0 - 20MHz @ 4.5 - 5.5V  Power Consumption at 1MHz, 1.8V, 25C Note:  Active: 0.4mA  Power-down Mode: 0.1µA  Power-save Mode: 0.6µA (Including 32kHz RTC) 1. See “Data retention” on page 17 for details.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 2 ATmega164A/PA/324A/PA/644A/PA/1284/P Table of Contents 1 2 Pin configurations ............................................................................................................... 11 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 11 1.2 Pinout - DRQFN for ATmega164A/164PA/324A/324PA ................................. 12 1.3 Pinout - VFBGA for ATmega164A/164PA/324A/324PA .................................. 13 Overview .................................................................................................................................... 13 2.1 Block diagram .................................................................................................. 14 2.2 Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P ...................................................................................................................................... 15 2.3 Pin Descriptions............................................................................................... 15 3 Resources 4 About code examples 5 Data retention ......................................................................................................................... 17 6 Capacitive touch sensing 7 AVR CPU Core 8 9 ................................................................................................................................ 17 ....................................................................................................... 17 ............................................................................................... 17 ....................................................................................................................... 18 7.1 Overview.......................................................................................................... 18 7.2 ALU – Arithmetic Logic Unit............................................................................. 19 7.3 Status Register ................................................................................................ 19 7.4 General Purpose Register File ........................................................................ 21 7.5 Stack Pointer ................................................................................................... 22 7.6 Instruction Execution Timing ........................................................................... 23 7.7 Reset and interrupt handling ........................................................................... 24 AVR memories ....................................................................................................................... 27 8.1 Overview.......................................................................................................... 27 8.2 In-System Reprogrammable Flash Program Memory ..................................... 27 8.3 SRAM data memory ........................................................................................ 28 8.4 EEPROM data memory ................................................................................... 30 8.5 I/O memory...................................................................................................... 31 8.6 Register Description ........................................................................................ 32 System clock and clock options ................................................................................ 38 9.1 Clock systems and their distribution ................................................................ 38 9.2 Clock Sources ................................................................................................. 39  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 3 ATmega164A/PA/324A/PA/644A/PA/1284/P 9.3 Low Power Crystal Oscillator........................................................................... 41 9.4 Full swing Crystal Oscillator ............................................................................ 42 9.5 Low Frequency Crystal Oscillator .................................................................... 43 9.6 Calibrated Internal RC Oscillator ..................................................................... 44 9.7 128kHz internal oscillator ................................................................................ 45 9.8 External clock .................................................................................................. 46 9.9 Timer/Counter Oscillator.................................................................................. 46 9.10 Clock Output Buffer ......................................................................................... 47 9.11 System Clock Prescaler .................................................................................. 47 9.12 Register description ......................................................................................... 48 10 Power management and sleep modes ................................................................... 50 10.1 Overview.......................................................................................................... 50 10.2 Sleep Modes.................................................................................................... 50 10.3 BOD disable(1) ................................................................................................. 51 10.4 Idle mode......................................................................................................... 51 10.5 ADC Noise Reduction mode............................................................................ 51 10.6 Power-down mode........................................................................................... 52 10.7 Power-save mode............................................................................................ 52 10.8 Standby mode ................................................................................................. 52 10.9 Extended Standby mode ................................................................................. 52 10.10 Power Reduction Register ............................................................................... 53 10.11 Minimizing Power Consumption ...................................................................... 53 10.12 Register description ......................................................................................... 55 11 System Control and Reset ............................................................................................. 58 11.1 Resetting the AVR ........................................................................................... 58 11.2 Internal Voltage Reference.............................................................................. 62 11.3 Watchdog Timer .............................................................................................. 63 11.4 Register description ......................................................................................... 66 12 Interrupts ................................................................................................................................... 69 12.1 Overview.......................................................................................................... 69 12.2 Interrupt Vectors in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 69 12.3 Register description ......................................................................................... 73 13 External Interrupts .............................................................................................................. 75 13.1 Overview.......................................................................................................... 75 13.2 Register description ......................................................................................... 75  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 4 ATmega164A/PA/324A/PA/644A/PA/1284/P 14 I/O-Ports ..................................................................................................................................... 80 14.1 Overview.......................................................................................................... 80 14.2 Ports as General Digital I/O ............................................................................. 81 14.3 Alternate Port Functions .................................................................................. 85 14.4 Register description ......................................................................................... 97 15 8-bit Timer/Counter0 with PWM .................................................................................. 99 15.1 Features .......................................................................................................... 99 15.2 Overview.......................................................................................................... 99 15.3 Timer/Counter Clock Sources ....................................................................... 100 15.4 Counter Unit .................................................................................................. 100 15.5 Output Compare unit ..................................................................................... 101 15.6 Compare Match Output unit .......................................................................... 102 15.7 Modes of operation........................................................................................ 103 15.8 Timer/Counter Timing diagrams .................................................................... 107 15.9 Register description ....................................................................................... 109 16 16-bit Timer/Counter1 and Timer/Counter3(1) with PWM .......................... 115 16.1 Features ........................................................................................................ 115 16.2 Overview........................................................................................................ 115 16.3 Accessing 16-bit Registers ............................................................................ 117 16.4 Timer/Counter Clock Sources ....................................................................... 120 16.5 Prescaler Reset ............................................................................................. 120 16.6 Counter Unit .................................................................................................. 121 16.7 Input Capture Unit ......................................................................................... 122 16.8 Output Compare units ................................................................................... 123 16.9 Compare Match Output unit .......................................................................... 126 16.10 Modes of Operation ....................................................................................... 127 16.11 Timer/Counter Timing diagrams .................................................................... 134 16.12 Register description ....................................................................................... 136 17 8-bit Timer/Counter2 with PWM and asynchronous operation ............. 146 17.1 Features ........................................................................................................ 146 17.2 Overview........................................................................................................ 146 17.3 Timer/Counter clock sources ......................................................................... 147 17.4 Counter unit ................................................................................................... 148 17.5 Output Compare unit ..................................................................................... 148 17.6 Compare Match Output unit .......................................................................... 150  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 5 ATmega164A/PA/324A/PA/644A/PA/1284/P 17.7 Modes of operation........................................................................................ 151 17.8 Timer/Counter Timing diagrams .................................................................... 155 17.9 Asynchronous Operation of Timer/Counter2 ................................................. 156 17.10 Timer/Counter Prescaler ............................................................................... 158 17.11 Register description ....................................................................................... 159 18 SPI – Serial Peripheral Interface ............................................................................... 166 18.1 Features ........................................................................................................ 166 18.2 Overview........................................................................................................ 166 18.3 SS pin functionality ........................................................................................ 170 18.4 Data modes ................................................................................................... 170 18.5 Register description ....................................................................................... 172 19 USART ...................................................................................................................................... 175 19.1 Features ........................................................................................................ 175 19.2 USART1 and USART0 .................................................................................. 175 19.3 Overview........................................................................................................ 175 19.4 Clock Generation ........................................................................................... 176 19.5 Frame formats ............................................................................................... 179 19.6 USART Initialization....................................................................................... 180 19.7 Data Transmission – The USART Transmitter .............................................. 181 19.8 Data Reception – The USART Receiver ....................................................... 184 19.9 Asynchronous Data Reception ...................................................................... 188 19.10 Multi-processor Communication mode .......................................................... 191 19.11 Register description ....................................................................................... 193 19.12 Examples of Baud Rate Setting..................................................................... 198 20 USART in SPI mode .......................................................................................................... 202 20.1 Features ........................................................................................................ 202 20.2 Overview........................................................................................................ 202 20.3 Clock Generation ........................................................................................... 202 20.4 SPI Data Modes and Timing.......................................................................... 203 20.5 Frame Formats .............................................................................................. 203 20.6 Data Transfer................................................................................................. 205 20.7 AVR USART MSPIM vs. AVR SPI ................................................................ 207 20.8 Register description ....................................................................................... 208 21 Two-wire Serial Interface 21.1 .............................................................................................. 211 Features ........................................................................................................ 211  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 6 ATmega164A/PA/324A/PA/644A/PA/1284/P 21.2 Two-wire Serial Interface bus definition......................................................... 211 21.3 Data Transfer and Frame Format .................................................................. 212 21.4 Multi-master Bus Systems, Arbitration and Synchronization ......................... 214 21.5 Overview of the TWI Module ......................................................................... 217 21.6 Using the TWI................................................................................................ 219 21.7 Transmission modes ..................................................................................... 222 21.8 Multi-master Systems and Arbitration............................................................ 234 21.9 Register description ....................................................................................... 236 22 AC - Analog Comparator ............................................................................................... 240 22.1 Overview........................................................................................................ 240 22.2 Analog Comparator Multiplexed Input ........................................................... 240 22.3 Register description ....................................................................................... 241 23 ADC - Analog-to-digital converter ........................................................................... 243 23.1 Features ........................................................................................................ 243 23.2 Overview........................................................................................................ 243 23.3 Operation....................................................................................................... 244 23.4 Starting a conversion..................................................................................... 245 23.5 Prescaling and Conversion Timing ................................................................ 246 23.6 Changing Channel or Reference Selection ................................................... 249 23.7 ADC Noise Canceler ..................................................................................... 250 23.8 ADC Conversion Result................................................................................. 255 23.9 Register description ....................................................................................... 257 24 JTAG interface and on-chip debug system ....................................................... 262 24.1 Features ........................................................................................................ 262 24.2 Overview........................................................................................................ 262 24.3 TAP – Test Access Port ................................................................................ 262 24.4 TAP controller................................................................................................ 264 24.5 Using the Boundary-scan Chain .................................................................... 265 24.6 Using the On-chip Debug System ................................................................. 265 24.7 On-chip Debug Specific JTAG Instructions ................................................... 266 24.8 Using the JTAG Programming Capabilities ................................................... 266 24.9 Bibliography................................................................................................... 267 24.10 Register description ....................................................................................... 267 25 IEEE 1149.1 (JTAG) Boundary-scan 25.1 ...................................................................... 268 Features ........................................................................................................ 268  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 7 ATmega164A/PA/324A/PA/644A/PA/1284/P 25.2 Overview........................................................................................................ 268 25.3 Data Registers............................................................................................... 269 25.4 Boundary-scan Specific JTAG Instructions ................................................... 270 25.5 Boundary-scan Chain .................................................................................... 271 25.6 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order 274 25.7 Boundary-scan Description Language Files .................................................. 275 25.8 Register description ....................................................................................... 276 26 Boot loader support – read-while-write self-programming ..................... 277 26.1 Features ........................................................................................................ 277 26.2 Overview........................................................................................................ 277 26.3 Application and Boot Loader Flash Sections ................................................. 277 26.4 Read-While-Write and No Read-While-Write Flash Sections........................ 278 26.5 Boot Loader Lock Bits ................................................................................... 280 26.6 Entering the Boot Loader Program ................................................................ 281 26.7 Addressing the Flash During Self-Programming ........................................... 282 26.8 Self-Programming the Flash .......................................................................... 283 26.9 Register description ....................................................................................... 293 27 Memory programming .................................................................................................... 295 27.1 Program And Data Memory Lock Bits ........................................................... 295 27.2 Fuse bits ........................................................................................................ 296 27.3 Signature Bytes ............................................................................................. 298 27.4 Calibration byte.............................................................................................. 298 27.5 Page Size ...................................................................................................... 298 27.6 Parallel Programming Parameters, Pin Mapping, and Commands ............... 299 27.7 Parallel programming .................................................................................... 301 27.8 Serial downloading ........................................................................................ 309 27.9 Serial Programming Instruction set ............................................................... 312 27.10 Programming via the JTAG Interface ............................................................ 314 28 Electrical characteristics (TA = -40°C to 85°C) ................................................ 326 28.1 DC Characteristics......................................................................................... 326 28.2 Speed grades ................................................................................................ 332 28.3 Clock characteristics...................................................................................... 333 28.4 System and reset characteristics................................................................... 334 28.5 External interrupts characteristics ................................................................. 334 28.6 SPI timing characteristics .............................................................................. 335  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 8 ATmega164A/PA/324A/PA/644A/PA/1284/P 28.7 Two-wire Serial Interface Characteristics ...................................................... 336 28.8 ADC characteristics ....................................................................................... 338 29 Electrical Characteristics - TA = -40°C to 105°C ............................................. 341 29.1 DC Characteristics......................................................................................... 341 30 Typical characteristics -TA = -40°C to 85°C ...................................................... 345 30.1 ATmega164A typical characteristics - TA = -40°C to 85°C ........................... 345 30.2 ATmega164PA typical characteristics - TA = -40°C to 85°C ......................... 372 30.3 ATmega324A typical characteristics - TA = -40°C to 85°C ........................... 398 30.4 ATmega324PA typical characteristics - TA = -40°C to 85°C ......................... 424 30.5 ATmega644A typical characteristics - TA = -40°C to 85°C ........................... 450 30.6 ATmega644PA typical characteristics - TA = -40°C to 85°C ......................... 476 30.7 ATmega1284 typical characteristics - TA = -40°C to 85°C............................ 502 30.8 ATmega1284P typical characteristics - TA = -40°C to 85°C ......................... 528 31 Typical Characteristics - TA = -40°C to 105°C ................................................. 554 31.1 ATmega164PA Typical Characteristics - TA = -40°C to 105°C ..................... 555 31.2 ATmega324PA Typical Characteristics - TA = -40°C to 105°C ..................... 575 31.3 ATmega644PA Typical Characteristics - TA = -40°C to 105°C ..................... 595 31.4 ATmega1284P typical characteristics - TA = -40°C to 105°C ....................... 614 32 Register summary ............................................................................................................. 637 33 Instruction set summary 34 Ordering information ............................................................................................... 641 ....................................................................................................... 644 34.1 ATmega164A................................................................................................. 644 34.2 ATmega164PA .............................................................................................. 645 34.3 ATmega324A................................................................................................. 646 34.4 ATmega324PA .............................................................................................. 647 34.5 ATmega644A................................................................................................. 648 34.6 ATmega644PA .............................................................................................. 649 34.7 ATmega1284 ................................................................................................. 650 34.8 ATmega1284P............................................................................................... 651 35 Packaging information ................................................................................................... 652 35.1 44A ................................................................................................................ 652 35.2 40P6 .............................................................................................................. 654 35.3 44M1.............................................................................................................. 655 35.4 44MC ............................................................................................................. 658  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 9 ATmega164A/PA/324A/PA/644A/PA/1284/P 35.5 36 Errata 49C2 .............................................................................................................. 661 ......................................................................................................................................... 664 37 Data sheet revision history .......................................................................................... 665 37.1 Rev. B - 01/2020............................................................................................ 665 37.2 Rev. A - 10/2018............................................................................................ 665 37.3 Rev. 8272G - 01/2015 ................................................................................... 665 37.4 Rev. 8272F - 08/2014 .................................................................................... 665 37.5 Rev. 8272E - 04/2013.................................................................................... 666 37.6 Rev. 8272D - 05/12 ....................................................................................... 666 37.7 Rev. 8272C - 06/11 ....................................................................................... 666 37.8 Rev. 8272B - 05/11........................................................................................ 666 37.9 Rev. 8272A - 01/10........................................................................................ 667  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 10 ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Pin configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 1-1. Pinout (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3*) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 (PCINT28/XCK1/OC1B) PD4 (PCINT29/OC1A) PD5 (PCINT30/OC2B/ICP) PD6 PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31) PB4 (SS/OC0B/PCINT12) PB3 (AIN1/OC0A/PCINT11) PB2 (AIN0/INT2/PCINT10) PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) TQFP/QFN/MLF (PCINT13/ICP3/MOSI) PB5 (PCINT14/OC3A/MISO) PB6 (PCINT15/OC3B/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0/T3*) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 PD3 PD4 PD5 PD6 PD7 VCC GND (PCINT16/SCL) PC0 (PCINT17/SDA) PC1 (PCINT18/TCK) PC2 (PCINT19/TMS) PC3 (PCINT27/TXD1/INT1) (PCINT28/XCK1/OC1B) (PCINT29/OC1A) (PCINT30/OC2B/ICP) (PCINT31/OC2A) *T3 is only available for ATmega1284/1284P PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 11 ATmega164A/PA/324A/PA/644A/PA/1284/P Pinout - DRQFN for ATmega164A/164PA/324A/324PA Figure 1-2. DRQFN - pinout Top view Bottom view A18 B1 B15 A17 B2 B14 B3 A2 A3 A4 B14 B2 A16 B13 A16 B13 B3 A15 A15 B12 B4 B5 B11 A13 A2 A3 A4 A14 A5 B11 A13 B5 A6 A12 B10 A11 B9 A10 B8 A9 B7 A8 B6 A7 B8 A10 B9 A11 B10 A12 B7 A9 B6 A8 A1 B1 B12 A14 A6 A18 B15 A17 B4 A5 Table 1-1. A24 B20 A23 B19 A22 B18 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 A1 A7 1.2 DRQFN - pinout. A1 PB5 A7 PD3 A13 PC4 A19 PA3 B1 PB6 B6 PD4 B11 PC5 B16 PA2 A2 PB7 A8 PD5 A14 PC6 A20 PA1 B2 RESET B7 PD6 B12 PC7 B17 PA0 A3 VCC A9 PD7 A15 AVCC A21 VCC B3 GND B8 VCC B13 GND B18 GND A4 XTAL2 A10 GND A16 AREF A22 PB0 B4 XTAL1 B9 PC0 B14 PA7 B19 PB1 A5 PD0 A11 PC1 A17 PA6 A23 PB2 B5 PD1 B10 PC2 B15 PA5 B20 PB3 A6 PD2 A12 PC3 A18 PA4 A24 PB4  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 12 ATmega164A/PA/324A/PA/644A/PA/1284/P 1.3 Pinout - VFBGA for ATmega164A/164PA/324A/324PA Figure 1-3. VFBGA - pinout Top view 1 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G Table 1-2. 2. 2 Bottom view BGA - pinout 1 2 3 4 5 6 7 A GND PB4 PB2 GND VCC PA2 GND B PB6 PB5 PB3 PB0 PA0 PA3 PA5 C VCC RESET PB7 PB1 PA1 PA6 AREF D GND XTAL2 PD0 GND PA4 PA7 GND E XTAL1 PD1 PD5 PD7 PC5 PC7 AVCC F PD2 PD3 PD6 PC0 PC2 PC4 PC6 G GND PD4 VCC GND PC1 PC3 GND Overview The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 13 ATmega164A/PA/324A/PA/644A/PA/1284/P 2.1 Block diagram Figure 2-1. Block diagram PA7..0 PB7..0 VCC RESET GND Power Supervision POR / BOD & RESET PORT A (8) PORT B (8) Watchdog Timer Analog Comparator A/D Converter Watchdog Oscillator USART 0 XTAL1 Oscillator Circuits / Clock Generation EEPROM Internal Bandgap reference XTAL2 SPI 8bit T/C 0 CPU 16bit T/C 1 16bit T/C 1 JTAG/OCD 8bit T/C 2 TWI FLASH SRAM PORT C (8) TOSC2/PC7 TOSC1/PC6 USART 1 16bit T/C 3* PORT D (8) PD7..0 PC5..0 * Only available in ATmega1284/1284P The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features: 16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three (four for ATmega1284/1284P) flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented two-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 14 ATmega164A/PA/324A/PA/644A/PA/1284/P timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression™ (AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using the high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Table 2-1. Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Device Flash EEPROM RAM ATmega164A 16K 512 1K ATmega164PA 16K 512 1K ATmega324A 32K 1K 2K ATmega324PA 32K 1K 2K ATmega644A 64K 2K 4K ATmega644PA 64K 2K 4K ATmega1284 128K 4K 16K ATmega1284P 128K 4K 16K 2.3 Pin Descriptions 2.3.1 VC Units bytes Digital supply voltage. 2.3.2 GND Ground.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 15 ATmega164A/PA/324A/PA/644A/PA/1284/P 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 87. 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 88. 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of the JTAG interface, along with special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 91. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 94. 2.3.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and reset characteristics” on page 334. Shorter pulses are not guaranteed to generate a reset. 2.3.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.9 XTAL2 Output from the inverting Oscillator amplifier. 2.3.10 AVCC AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.11 AREF This is the analog reference pin for the Analog-to-digital Converter.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 16 ATmega164A/PA/324A/PA/644A/PA/1284/P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on www.microchip.com 4. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details. The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". Note: 5. 1. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 6. Capacitive touch sensing The QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from www.microchip.com. For implementation details and other information, refer to the “QTouch Library User Guide” - also available for download from the microchip website.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 17 ATmega164A/PA/324A/PA/644A/PA/1284/P 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1. Block diagram of the AVR architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Control Lines Direct Addressing Instruction Decoder Indirect Addressing Instruction Register Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 18 ATmega164A/PA/324A/PA/644A/PA/1284/P operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 7.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the AVR Instruction Set Manual. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 19 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.3.1 SREG – Status Register(1) The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the AVR Instruction Set Manual on www.microchip.com. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetic. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. Note: 1. Refer to the Instruction Set Manual on www.microchip.com for more details  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 20 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:  One 8-bit output operand and one 8-bit result input  Two 8-bit output operands and one 8-bit result input  Two 8-bit output operands and one 16-bit result input  One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 21 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH 7 YL 0 R29 (0x1D) Z-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the AVR Instruction Set Manual for details). 7.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure 8-2 on page 29. See Table 7-1 for Stack Pointer details. Table 7-1. Stack Pointer instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL ICALL RCALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt POP Incremented by 1 Data is popped from the stack RET RETI Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent, see Table 7-2 on page 23. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 22 ATmega164A/PA/324A/PA/644A/PA/1284/P 7.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value Note: 1. R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0/0(1) 0/1(1) 1/0(1) 0 0 1 1 1 1 1 1 1 1 Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. Table 7-2. 7.5.2 R R/W Stack Pointer size Device Stack Pointer size ATmega164A/ATmega164PA SP[10:0] ATmega324A/ATmega324PA SP[11:0] ATmega644A/ATmega644PA SP[12:0] ATmega1284/ATmega1284P SP[13:0] RAMPZ – Extended Z-pointer Register for ELPM/SPM(1) Bit 7 6 5 4 3 2 1 0 0x3B (0x5B) RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4 on page 23. Note that LPM is not affected by the RAMPZ setting. Figure 7-4. The Z-pointer used by ELPM and SPM. Bit (Individually) 7 0 7 0 RAMPZ Bit (Z-pointer) 23 7 ZH 16 15 0 ZL 8 7 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. Note: 7.6 1. RAMPZ is only valid for ATmega1284/ATmega1284P. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-5 on page 24 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 23 ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 7-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-6. Single Cycle ALU operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 7.7 Reset and interrupt handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section ”Memory programming” on page 295 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 69. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 69 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see ”Memory programming” on page 295. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 24 ATmega164A/PA/324A/PA/644A/PA/1284/P writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1
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