ATMEGA644PV-20AU

8-bit AVR Microcontrollers ATmega644P/V DATASHEET COMPLETE Introduction ® ® The Atmel picoPower ATmega644P is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega644P achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. Feature ® ® High Performance, Low Power Atmel AVR 8-Bit Microcontroller Family • • • Advanced RISC Architecture – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – 64KBytes of In-System Self-Programmable Flash Program Memory – 2KBytes EEPROM – 4KBytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data Retention: 20 Years at 85°C/100 Years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security Atmel QTouch® Library Support – Capacitive Touch Buttons, Sliders and Wheels – QTouch and QMatrix acquisition Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 – • • Up to 64 Sense Channels JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – – – • • • • • Real Time Counter with Separate Oscillator Six PWM Channels 8-channel 10-bit ADC • Differential Mode with Selectable Gain at 1×, 10× or 200× – One Byte-oriented 2-wire Serial Interface (Philips I2C compatible) – Two Programmable Serial USART – One Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP – 44-lead TQFP – 44-pad VQFN/QFN Operating Voltage: – 1.8 - 5.5V for ATmega644PV – 2.7 - 5.5V for ATmega644P Speed Grades – ATmega644PV: • 0 - 4MHz @ 1.8V - 5.5V • 0 - 10MHz @ 2.7V - 5.5V – ATmega644P: • 0 - 10MHz @ 2.7V - 5.5V • 0 - 20MHz @ 4.5 - 5.5V Power Consumption at 1MHz, 1.8V, 25°C – Active Mode: 0.4mA – Power-down Mode: 0.1μA – Power-save Mode: 0.6μA (Including 32kHz RTC) Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 2 1. Refer to Data Retention. Related Links Data Retention on page 20 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 3 Table of Contents Introduction......................................................................................................................1 Feature............................................................................................................................ 1 1. Description...............................................................................................................10 2. Configuration Summary........................................................................................... 11 3. Ordering Information ...............................................................................................12 4. Block Diagram......................................................................................................... 14 5. Pin Configurations................................................................................................... 15 5.1. 5.2. Pinout......................................................................................................................................... 15 Pin Descriptions..........................................................................................................................16 6. I/O Multiplexing........................................................................................................ 18 7. General Information................................................................................................. 20 7.1. 7.2. 7.3. 7.4. Resources.................................................................................................................................. 20 Data Retention............................................................................................................................20 About Code Examples................................................................................................................20 Capacitive Touch Sensing.......................................................................................................... 20 8. AVR CPU Core........................................................................................................ 21 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. Overview.....................................................................................................................................21 ALU – Arithmetic Logic Unit........................................................................................................22 Status Register...........................................................................................................................22 General Purpose Register File................................................................................................... 24 Stack Pointer.............................................................................................................................. 25 Accessing 16-bit Registers.........................................................................................................27 8.7. 8.8. Instruction Execution Timing...................................................................................................... 28 Reset and Interrupt Handling..................................................................................................... 28 9. AVR Memories.........................................................................................................31 9.1. Overview.....................................................................................................................................31 9.2. 9.3. 9.4. 9.5. 9.6. In-System Reprogrammable Flash Program Memory................................................................ 31 SRAM Data Memory...................................................................................................................32 EEPROM Data Memory............................................................................................................. 33 I/O Memory.................................................................................................................................34 Register Description................................................................................................................... 34 10. System Clock and Clock Options............................................................................ 43 10.1. Clock Systems and Their Distribution.........................................................................................43 10.2. Clock Sources............................................................................................................................ 44 10.3. Low Power Crystal Oscillator......................................................................................................46 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 4 10.4. Full Swing Crystal Oscillator.......................................................................................................47 10.5. Low Frequency Crystal Oscillator...............................................................................................48 10.6. Calibrated Internal RC Oscillator................................................................................................49 10.7. 128kHz Internal Oscillator.......................................................................................................... 50 10.8. External Clock............................................................................................................................ 51 10.9. Timer/Counter Oscillator.............................................................................................................52 10.10. Clock Output Buffer....................................................................................................................52 10.11. System Clock Prescaler............................................................................................................. 52 10.12. Register Description...................................................................................................................53 11. PM - Power Management and Sleep Modes........................................................... 57 11.1. 11.2. 11.3. 11.4. 11.5. 11.6. 11.7. 11.8. 11.9. 11.10. 11.11. 11.12. Overview.....................................................................................................................................57 Sleep Modes...............................................................................................................................57 BOD Disable...............................................................................................................................58 Idle Mode....................................................................................................................................58 ADC Noise Reduction Mode.......................................................................................................58 Power-Down Mode.....................................................................................................................59 Power-save Mode.......................................................................................................................59 Standby Mode............................................................................................................................ 60 Extended Standby Mode............................................................................................................ 60 Power Reduction Register..........................................................................................................60 Minimizing Power Consumption................................................................................................. 60 Register Description................................................................................................................... 62 12. SCRST - System Control and Reset....................................................................... 68 12.1. 12.2. 12.3. 12.4. 12.5. 12.6. 12.7. 12.8. 12.9. Resetting the AVR...................................................................................................................... 68 Reset Sources............................................................................................................................68 Power-on Reset..........................................................................................................................69 External Reset............................................................................................................................70 Brown-out Detection...................................................................................................................70 Watchdog System Reset............................................................................................................ 71 Internal Voltage Reference.........................................................................................................71 Watchdog Timer......................................................................................................................... 72 Register Description................................................................................................................... 74 13. Interrupts................................................................................................................. 78 13.1. Overview.....................................................................................................................................78 13.2. Interrupt Vectors in ATmega644P...............................................................................................78 13.3. Register Description................................................................................................................... 81 14. External Interrupts................................................................................................... 84 14.1. EXINT - External Interrupts........................................................................................................ 84 15. I/O-Ports.................................................................................................................. 96 15.1. 15.2. 15.3. 15.4. Overview.....................................................................................................................................96 Ports as General Digital I/O........................................................................................................97 Alternate Port Functions...........................................................................................................100 Register Description................................................................................................................. 113 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 5 16. TC0 - 8-bit Timer/Counter0 with PWM...................................................................128 16.1. 16.2. 16.3. 16.4. 16.5. 16.6. 16.7. 16.8. 16.9. Features................................................................................................................................... 128 Overview...................................................................................................................................128 Timer/Counter Clock Sources.................................................................................................. 130 Counter Unit............................................................................................................................. 130 Output Compare Unit................................................................................................................131 Compare Match Output Unit.....................................................................................................133 Modes of Operation..................................................................................................................134 Timer/Counter Timing Diagrams...............................................................................................138 Register Description................................................................................................................. 140 17. TC1 - 16-bit Timer/Counter1 with PWM.................................................................153 17.1. Overview...................................................................................................................................153 17.2. Features................................................................................................................................... 153 17.3. Block Diagram.......................................................................................................................... 153 17.4. Definitions.................................................................................................................................154 17.5. Registers.................................................................................................................................. 155 17.6. Accessing 16-bit Registers.......................................................................................................155 17.7. Timer/Counter Clock Sources.................................................................................................. 158 17.8. Counter Unit............................................................................................................................. 158 17.9. Input Capture Unit.................................................................................................................... 159 17.10. Output Compare Units............................................................................................................. 161 17.11. Compare Match Output Unit.....................................................................................................163 17.12. Modes of Operation..................................................................................................................164 17.13. Timer/Counter Timing Diagrams.............................................................................................. 172 17.14. Register Description.................................................................................................................173 18. Timer/Counter 0, 1 Prescalers...............................................................................186 18.1. 18.2. 18.3. 18.4. Internal Clock Source............................................................................................................... 186 Prescaler Reset........................................................................................................................186 External Clock Source..............................................................................................................186 Register Description................................................................................................................. 187 19. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation................... 189 19.1. Features................................................................................................................................... 189 19.2. Overview...................................................................................................................................189 19.3. Timer/Counter Clock Sources.................................................................................................. 191 19.4. Counter Unit............................................................................................................................. 191 19.5. Output Compare Unit................................................................................................................192 19.6. Compare Match Output Unit.....................................................................................................194 19.7. Modes of Operation..................................................................................................................195 19.8. Timer/Counter Timing Diagrams...............................................................................................199 19.9. Asynchronous Operation of Timer/Counter2............................................................................ 200 19.10. Timer/Counter Prescaler.......................................................................................................... 202 19.11. Register Description................................................................................................................. 202 20. SPI – Serial Peripheral Interface........................................................................... 215 20.1. Features................................................................................................................................... 215 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 6 20.2. Overview...................................................................................................................................215 20.3. SS Pin Functionality................................................................................................................. 219 20.4. Data Modes.............................................................................................................................. 219 20.5. Register Description................................................................................................................. 220 21. USART - Universal Synchronous Asynchronous Receiver Transceiver................225 21.1. Features................................................................................................................................... 225 21.2. Overview...................................................................................................................................225 21.3. Block Diagram.......................................................................................................................... 225 21.4. Clock Generation......................................................................................................................226 21.5. Frame Formats.........................................................................................................................229 21.6. USART Initialization..................................................................................................................230 21.7. Data Transmission – The USART Transmitter......................................................................... 231 21.8. Data Reception – The USART Receiver.................................................................................. 233 21.9. Asynchronous Data Reception.................................................................................................237 21.10. Multi-Processor Communication Mode.................................................................................... 239 21.11. Examples of Baud Rate Setting............................................................................................... 240 21.12. Register Description.................................................................................................................243 22. USARTSPI - USART in SPI Mode.........................................................................253 22.1. 22.2. 22.3. 22.4. 22.5. 22.6. 22.7. 22.8. Features................................................................................................................................... 253 Overview...................................................................................................................................253 Clock Generation......................................................................................................................253 SPI Data Modes and Timing.....................................................................................................254 Frame Formats.........................................................................................................................254 Data Transfer............................................................................................................................256 AVR USART MSPIM vs. AVR SPI............................................................................................257 Register Description................................................................................................................. 258 23. TWI - 2-wire Serial Interface..................................................................................259 23.1. 23.2. 23.3. 23.4. 23.5. 23.6. 23.7. 23.8. 23.9. Features................................................................................................................................... 259 Two-Wire Serial Interface Bus Definition..................................................................................259 Data Transfer and Frame Format.............................................................................................260 Multi-master Bus Systems, Arbitration, and Synchronization...................................................263 Overview of the TWI Module.................................................................................................... 265 Using the TWI...........................................................................................................................267 Transmission Modes................................................................................................................ 270 Multi-master Systems and Arbitration.......................................................................................288 Register Description................................................................................................................. 290 24. AC - Analog Comparator....................................................................................... 298 24.1. Overview...................................................................................................................................298 24.2. Analog Comparator Multiplexed Input...................................................................................... 298 24.3. Register Description................................................................................................................. 299 25. ADC - Analog to Digital Converter.........................................................................304 25.1. Features................................................................................................................................... 304 25.2. Overview...................................................................................................................................304 25.3. Starting a Conversion...............................................................................................................306 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 7 25.4. Prescaling and Conversion Timing...........................................................................................307 25.5. 25.6. 25.7. 25.8. Changing Channel or Reference Selection.............................................................................. 310 ADC Noise Canceler................................................................................................................ 312 ADC Conversion Result............................................................................................................316 Register Description................................................................................................................. 318 26. JTAG Interface and On-chip Debug System..........................................................328 26.1. Features................................................................................................................................... 328 26.2. Overview...................................................................................................................................328 26.3. TAP – Test Access Port............................................................................................................ 329 26.4. TAP Controller.......................................................................................................................... 330 26.5. Using the Boundary-scan Chain...............................................................................................331 26.6. Using the On-chip Debug System............................................................................................ 331 26.7. On-chip Debug Specific JTAG Instructions.............................................................................. 332 26.8. Using the JTAG Programming Capabilities.............................................................................. 332 26.9. Bibliography..............................................................................................................................333 26.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................333 26.11. Data Registers..........................................................................................................................334 26.12. Boundry-scan Specific JTAG Instructions................................................................................ 335 26.13. Boundary-scan Chain...............................................................................................................337 26.14. ATmega644P Boundary-scan Order........................................................................................ 340 26.15. Boundary-scan Description Language Files............................................................................ 342 26.16. Register Description.................................................................................................................342 27. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 347 27.1. 27.2. 27.3. 27.4. 27.5. 27.6. 27.7. 27.8. 27.9. Features................................................................................................................................... 347 Overview...................................................................................................................................347 Application and Boot Loader Flash Sections............................................................................347 Read-While-Write and No Read-While-Write Flash Sections...................................................348 Entering the Boot Loader Program...........................................................................................350 Boot Loader Lock Bits.............................................................................................................. 351 Addressing the Flash During Self-Programming...................................................................... 352 Self-Programming the Flash.....................................................................................................353 Register Description................................................................................................................. 361 28. MEMPROG- Memory Programming......................................................................364 28.1. Program And Data Memory Lock Bits...................................................................................... 364 28.2. Fuse Bits...................................................................................................................................365 28.3. Signature Bytes........................................................................................................................ 368 28.4. Calibration Byte........................................................................................................................ 368 28.5. Serial Number...........................................................................................................................368 28.6. Page Size................................................................................................................................. 368 28.7. Parallel Programming Parameters, Pin Mapping, and Commands.......................................... 369 28.8. Parallel Programming...............................................................................................................371 28.9. Serial Downloading...................................................................................................................378 28.10. Programming Via the JTAG Interface.......................................................................................383 29. Electrical Characteristics....................................................................................... 397 29.1. Absolute Maximum Ratings......................................................................................................397 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 8 29.2. DC Characteristics....................................................................................................................397 29.3. 29.4. 29.5. 29.6. 29.7. 29.8. 29.9. Speed Grades.......................................................................................................................... 400 Clock Characteristics................................................................................................................400 System and Reset Characteristics........................................................................................... 401 External interrupts characteristics............................................................................................ 402 SPI Timing Characteristics....................................................................................................... 403 Two-wire Serial Interface Characteristics................................................................................. 404 ADC characteristics..................................................................................................................406 30. Typical Characteristics........................................................................................... 411 30.1. Active Supply Current............................................................................................................... 411 30.2. Idle Supply Current...................................................................................................................413 30.3. Supply Current of I/O Modules................................................................................................. 415 30.4. Power-down Supply Current.....................................................................................................416 30.5. Power-save Supply Current......................................................................................................417 30.6. Standby Supply Current........................................................................................................... 418 30.7. Pin Pull-Up................................................................................................................................418 30.8. Pin Driver Strength................................................................................................................... 421 30.9. Pin Threshold and Hysteresis...................................................................................................423 30.10. BOD Threshold........................................................................................................................ 425 30.11. Internal Oscillator Speed.......................................................................................................... 427 30.12. Current Consumption of Peripheral Units................................................................................ 429 30.13. Current Consumption in Reset and Reset Pulse Width........................................................... 431 31. Register Summary.................................................................................................433 32. Instruction Set Summary....................................................................................... 437 33. Packaging Information...........................................................................................441 33.1. 40-pin PDIP.............................................................................................................................. 441 33.2. 44-pin TQFP.............................................................................................................................442 33.3. 44-pin VQFN.............................................................................................................................443 34. Errata.....................................................................................................................444 34.1. 34.2. 34.3. 34.4. 34.5. 34.6. 34.7. 34.8. Rev. A....................................................................................................................................... 444 Rev. B....................................................................................................................................... 444 Rev. C.......................................................................................................................................444 Rev. D.......................................................................................................................................444 Rev. E....................................................................................................................................... 444 Rev. F....................................................................................................................................... 444 Rev. G.......................................................................................................................................444 Rev. H.......................................................................................................................................444 35. Datasheet Revision History................................................................................... 445 35.1. Rev. B – 08/2016...................................................................................................................... 445 35.2. Rev. A – 07/2016...................................................................................................................... 445 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 9 1. Description The Atmel® ATmega644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega644P achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega644P provides the following features: 64Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 2Kbytes EEPROM, 4Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, two serial programmable USARTs , one byte-oriented 2-wire Serial Interface (I2C), a 8channel 10-bit ADC with optional differential input stage with programmable gain, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main oscillator and the asynchronous timer continue to run. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega644P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega644P is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 10 2. Configuration Summary The table below compares the device series of feature and pin compatible devices, providing a seamless migration path. Table 2-1. Configuration Summary and Device Comparison Features ATmega164/V ATmega324/V ATmega644/V Pin Count 40/44 40/44 40/44 Flash (Bytes) 16K 32K 64K SRAM (Bytes) 1K 2K 4K EEPROM (Bytes) 512 1K 2K General Purpose I/O Lines 32 32 32 SPI 1 1 1 TWI (I2C) 1 1 1 USART 2 2 2 10-bit 15ksps 10-bit 15ksps 10-bit 15ksps ADC Channels 8 8 8 Analog Comparator 1 1 1 8-bit Timer/Counters 2 2 2 16-bit Timer/Counters 1 1 1 PWM channels 6 6 6 PDIP PDIP PDIP TQFP TQFP TQFP VQFN/QFN VQFN/QFN VQFN/QFN ADC Packages Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 11 3. Ordering Information Speed [MHz](3) Power Supply [V] 10 1.8 - 5.5 20 10 20 2.7 - 5.5 1.8 - 5.5 2.7 - 5.5 Ordering Code(2) Package(1) Operational Range ATmega644PV-10AU 44A Industrial (-40°C to 85°C) ATmega644PV-10AUR(4) 44A ATmega644PV-10PU 40P6 ATmega644PV-10MU 44M1 ATmega644PV-10MUR(4) 44M1 ATmega644P-20AU 44A ATmega644P-20AUR(4) 44A ATmega644P-20PU 40P6 ATmega644P-20MU 44M1 ATmega644P-20MUR(4) 44M1 ATmega644PV-10AN 44A ATmega644PV-10ANR(4) 44A ATmega644PV-10PN 40P6 ATmega644PV-10MN 44M1 ATmega644PV-10MNR(4) 44M1 ATmega644P-20AN 44A ATmega644P-20ANR(4) 44A ATmega644P-20PN 40P6 ATmega644P-20MN 44M1 ATmega644P-20MNR(4) 44M1 Industrial (-40°C to 85°C) Industrial (-40°C to 105°C) Industrial (-40°C to 105°C) Note:  1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Refer to Speed Grades for Speed vs. VCC 4. Tape & Reel. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 12 Package Type 40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP) 44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP) 44M1 44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat NoLead (VQFN) Related Links Speed Grades on page 400 Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 13 4. Block Diagram Figure 4-1. Block Diagram SRAM TCK TMS TDI TDO JTAG CPU OCD Clock generation TOSC1 32.768kHz XOSC TOSC2 XTAL1 16MHz LP XOSC XTAL2 VCC RESET GND 8MHz Calib RC 128kHz int osc External clock Power Supervision POR/BOD & RESET ADC[7:0] AREF PCINT[31:0] INT[2:0] OC1A/B T1 ICP1 OC2A OC2B NVM programming Power management and clock control Watchdog Timer ADC EXTINT TC 1 (16-bit) TC 2 (8-bit async) FLASH D A T A B U S EEPROM EEPROMIF I/O PORTS I N / O U T GPIOR[2:0] D A T A B U S TC 0 (8-bit) SPI AC Internal Reference USART 0 RxD0 TxD0 XCK0 USART 1 RxD1 TxD1 XCK1 TWI PA[7:0] PB[7:0] PC[7:0] PD[7:0] T0 OC0A OC0B MISO MOSI SCK SS AIN0 AIN1 ACO ADCMUX SDA SCL Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 14 5. Pin Configurations 5.1. Pinout 5.1.1. PDIP (PCINT8/XCK0/T0) (ADC0/PCINT0) (PCINT9/CLKO/T1) (ADC1/PCINT1) (PCINT10/INT2/AIN0) (ADC2/PCINT2) (PCINT11/OC0A/AIN1) (ADC3/PCINT3) (PCINT12/OC0B/ (ADC4/PCINT4) (PCINT13/MOSI) (ADC5/PCINT5) (PCINT14/MISO) (ADC6/PCINT6) (PCINT15//SCK) (ADC7/PCINT7) XTAL2 (TOSC2/PCINT23) XTAL1 (TOSC1/PCINT22) (PCINT24/RXD0) (TDI/PCINT21) (PCINT25/TXD0) (TDO/PCINT20) (PCINT26/RXD1/INT0) (TMS/PCINT19) (PCINT27/TXD1/INT1) (TCK/PCINT18) (PCINT28/XCK1/OC1B) (SDA/PCINT17) (PCINT29/OC1A) (SCL/PCINT16) (PCINT30/OC2B/ICP1) (OC2A/PCINT31) Power Ground Programming/debug Digital Analog Crystal/Osc Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 15 PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) 41 40 39 38 37 36 35 34 Crystal/Osc PB2 (AIN0/INT2/PCINT10) Analog 42 Digital PB3 (AIN1/OC0A/PCINT11) Programming/debug 43 Ground PB4 (SS/OC0B/PCINT12) Power 44 TQFN and QFN 28 GND XTAL2 7 27 AVCC XTAL1 8 26 PC7 (TOSC2/PCINT23) (PCINT24/RXD0) PD0 9 25 PC6 (TOSC1/PCINT22) (PCINT25/TXD0) PD1 10 24 PC5 (TDI/PCINT21) (PCINT26/RXD1/INT0) PD2 11 23 PC4 (TDO/PCINT20) (PCINT16/SCL) PC0 22 6 (PCINT19/TMS) PC3 GND 21 AREF (PCINT18/TCK) PC2 29 20 5 (PCINT17/SDA) PC1 VCC 19 PA7 (ADC7/PCINT7) 18 30 GND 4 17 RESET VCC PA6 (ADC6/PCINT6) 16 31 (PCINT31/OC2A) PD7 3 15 (PCINT15/SCK) PB7 (PCINT30/OC2B/ICP1) PD6 PA5 (ADC5/PCINT5) 14 (PCINT14/MISO) PB6 32 (PCINT29/OC1A) PD5 PA4 (ADC4/PCINT4) 2 13 33 (PCINT28/XCK1/OC1B) PD4 1 12 (PCINT13/MOSI) PB5 (PCINT27/TXD1/INT1) PD3 5.1.2. 5.2. Pin Descriptions 5.2.1. VCC Digital supply voltage. 5.2.2. GND Ground. 5.2.3. Port A (PA[7:0]) This port serves as analog inputs to the Analog-to-digital Converter. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 16 This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. 5.2.4. Port B (PB[7:0]) This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port also serves the functions of various special features. 5.2.5. Port C (PC[7:0]) This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port also serves the functions of the JTAG interface, along with special features. 5.2.6. Port D (PD[7:0]) This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port also serves the functions of various special features. 5.2.7. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. 5.2.8. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 5.2.9. XTAL2 Output from the inverting Oscillator amplifier. 5.2.10. AVCC AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 5.2.11. AREF This is the analog reference pin for the Analog-to-digital Converter. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 17 6. I/O Multiplexing Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1. PORT Function Multiplexing 32-pin TQFP/ QFN/ MLF Pin # 40-pin PDIP Pin # PAD 1 6 PB[5] EXTINT PCINT PCINT13 ADC/AC OSC T/C # 0 T/C # 1 USART MOSI 2 7 PB[6] PCINT14 MISO 3 8 PB[7] PCINT15 SCK 4 9 RESET 5 10 VCC 6 11 GND 7 12 XTAL2 8 13 XTAL1 9 14 PD[0] 10 15 PD[1] 11 16 PD[2] INT0 12 17 PD[3] INT1 13 18 PD[4] PCINT28 OC1B 14 19 PD[5] PCINT29 OC1A 15 20 PD[6] PCINT30 OC2B 16 21 PD[7] PCINT31 OC2A 17 - VCC RxD2 MISO1 18 - GND TxD2 MOSI1 19 22 PC[0] PCINT16 SCL 20 23 PC[1] PCINT17 SDA 21 24 PC[2] PCINT18 TCK 22 25 PC[3] PCINT19 TMS 23 26 PC[4] PCINT20 TDO 24 27 PC[5] PCINT21 TDI 25 28 PC[6] PCINT22 TOSC1 26 29 PC[7] PCINT23 TOSC2 27 30 AVCC 28 31 GND 29 32 AREF 30 33 PA[7] PCINT7 ADC7 31 34 PA[6] PCINT6 ADC6 32 35 PA[5] PCINT5 ADC5 33 36 PA[4] PCINT4 ADC4 34 37 PA[3] PCINT3 ADC3 PCINT24 RxD0 PCINT25 TxD0 PCINT26 RxD1 PCINT27 TXD1 I2C SPI JTAG XCK1 ICP1 AREF Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 18 32-pin TQFP/ QFN/ MLF Pin # 40-pin PDIP Pin # PAD 35 38 36 EXTINT PCINT ADC/AC PA[2] PCINT2 ADC2 39 PA[1] PCINT1 ADC1 37 40 PA[0] PCINT0 ADC0 38 - VCC SDA1 39 - GND SCL1 40 1 PB[0] PCINT8 41 2 PB[1] PCINT9 42 3 PB[2] 43 4 44 INT2 OSC T/C # 0 T/C # 1 T0 CLKO PCINT10 AIN0 PB[3] PCINT11 AIN1 5 PB[4] PCINT12 - - GND - - GND - - GND - - GND - - GND USART I2C SPI JTAG XCK0 T1 OC0A OC0B SS Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 19 7. General Information 7.1. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. 7.2. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 7.3. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 7.4. Capacitive Touch Sensing 7.4.1. QTouch Library ® ® The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on ® most Atmel AVR microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel ® QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: http:// www.atmel.com/technologies/touch/. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 20 8. AVR CPU Core 8.1. Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 8-1. Block Diagram of the AVR Architecture Register file R31 (ZH) R29 (YH) R27 (XH) R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1 R30 (ZL) R28 (YL) R26 (XL) R24 R22 R20 R18 R16 R14 R12 R10 R8 R6 R4 R2 R0 Program counter Flash program memory Instruction register Instruction decode Data memory Stack pointer Status register ALU In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 21 The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 8.2. ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction Set Summary section for a detailed description. Related Links Instruction Set Summary on page 437 8.3. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 22 8.3.1. Status Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. Name:  SREG Offset:  0x5F Reset:  0x00 Property: When addressing as I/O Register: address offset is 0x3F   Bit Access Reset 7 6 5 4 3 2 1 0 I T H S V N Z C R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. Bit 6 – T: Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in BCD arithmetic. See the Instruction Set Description for detailed information. Bit 4 – S: Sign Flag, S = N ㊉ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the Instruction Set Description for detailed information. Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction Set Description for detailed information. Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 23 Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 8.4. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • • • • One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Figure 8-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D Ge ne ra l R14 0x0E P urpos e R15 0x0F Working R16 0x10 Re gis te rs R17 0x11 … R26 0x1A X-re gis te r Low Byte R27 0x1B X-re gis te r High Byte R28 0x1C Y-re gis te r Low Byte R29 0x1D Y-re gis te r High Byte R30 0x1E Z-re gis te r Low Byte R31 0x1F Z-re gis te r High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in the figure, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. 8.4.1. The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in the figure. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 24 Figure 8-3. The X-, Y-, and Z-registers 15 X-register XH 7 0 15 Y-register 7 R26 YH YL 0 7 R28 ZH ZL 0 0 0 R29 7 0 0 R27 7 15 Z-register XL 7 0 0 R31 R30 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). Related Links Instruction Set Summary on page 437 8.5. Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM. See the table for Stack Pointer details. Table 8-1. Stack Pointer Instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt ICALL RCALL POP Incremented by 1 Data is popped from the stack RET Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt RETI The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 25 8.5.1. Stack Pointer Register Low and High byte The SPL and SPH register pair represents the 16-bit value, SP.The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. Name:  SPL and SPH Offset:  0x5D Reset:  0x10FF Property: When addressing I/O Registers as data space the offset address is 0x3D   Bit 15 14 13 Access R R R Reset 0 0 0 Bit Access Reset 12 11 10 9 8 SP12 SP11 SP10 SP9 SP8 RW RW RW RW RW 1 0 0 0 0 7 6 5 4 3 2 1 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 RW RW RW RW RW RW RW RW 1 1 1 1 1 1 1 1 Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 – SPn: Stack Pointer Register SPL and SPH are combined into SP. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 26 8.5.2. Extended Z-pointer Register for ELPM/SPM When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. Name:  RAMPZ Offset:  0x5B Reset:  0x0 Property: When addressing I/O Registers as data space the offset address is 0x3B   Bit Access Reset 7 6 5 4 3 2 1 0 RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5, 6, 7 – RAMPZn: Extended Z-pointer Register for ELPM/SPM For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in the below figure. Note that LPM is not affected by the RAMPZ setting. Figure 8-4. The Z-pointer used by ELPM and SPM Bit (Individually) 7 0 7 RAMPZ Bit (Z-pointer) 23 0 7 ZH 16 15 0 ZL 8 7 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 8.6. Accessing 16-bit Registers The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register using a 16-bit bus. For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the low byte of the 16-bit register in the same clock cycle. For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the temporary register. This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing the register. Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers. The temporary registers can also be read and written directly from user software. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 27 8.7. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. The Figure below shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 8-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch The following Figure shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 8-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 8.8. Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. They have determined priority levels: The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse. Atmel ATmega644P/V [DATASHEET] Atmel-42744B-ATmega644P/V_Datasheet_Complete-08/2016 28 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts: The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. The Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example(1) in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example(1) char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1