ATmega64A
ATmega64A
DATASHEET COMPLETE
Introduction
®
The Atmel ATmega64A is a low-power CMOS 8-bit microcontroller based
®
on the AVR enhanced RISC architecture. By executing powerful instructions
in a single clock cycle, the ATmega64A achieves throughputs close to
1MIPS per MHz. This empowers system designer to optimize the device for
power consumption versus processing speed.
Features
•
•
•
•
High-performance, Low-power Atmel AVR 8-bit Microcontroller
Advanced RISC Architecture
– 130 Powerful Instructions - Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers + Peripheral Control
Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 64Kbytes of In-System Self-programmable Flash program
memory
– 2Kbytes EEPROM
– 4Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Up to 64 Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
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•
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture
Mode
–
–
–
–
–
•
•
•
•
Real Time Counter with Separate Oscillator
Two 8-bit PWM Channels
6 PWM Channels with Programmable Resolution from 1 to 16 Bits
Output Compare Modulator
8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V
Speed Grades
– 0 - 16MHz
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Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description.................................................................................................................9
2. Configuration Summary........................................................................................... 10
3. Ordering Information................................................................................................ 11
4. Block Diagram......................................................................................................... 12
5. ATmega103 and ATmega64A Compatibility............................................................ 13
5.1.
ATmega103 Compatibility Mode.................................................................................................13
6. Pin Configurations................................................................................................... 14
6.1.
Pin Descriptions..........................................................................................................................14
7. Resources................................................................................................................18
8. Data Retention.........................................................................................................19
9. About Code Examples............................................................................................. 20
10. Capacitive Touch Sensing....................................................................................... 21
11. AVR CPU Core........................................................................................................ 22
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
Overview.....................................................................................................................................22
ALU – Arithmetic Logic Unit........................................................................................................23
Status Register...........................................................................................................................23
General Purpose Register File................................................................................................... 25
Stack Pointer.............................................................................................................................. 26
Instruction Execution Timing...................................................................................................... 26
Reset and Interrupt Handling..................................................................................................... 27
12. AVR Memories.........................................................................................................30
12.1. Overview.....................................................................................................................................30
12.2.
12.3.
12.4.
12.5.
12.6.
12.7.
In-System Reprogrammable Flash Program Memory................................................................ 30
SRAM Data Memory...................................................................................................................31
EEPROM Data Memory............................................................................................................. 33
I/O Memory.................................................................................................................................34
External Memory Interface......................................................................................................... 34
Register Description................................................................................................................... 41
13. System Clock and Clock Options............................................................................ 52
13.1. Clock Systems and their Distribution..........................................................................................52
13.2. Clock Sources............................................................................................................................ 53
13.3. Default Clock Source..................................................................................................................54
13.4. Crystal Oscillator........................................................................................................................ 54
13.5. Low-frequency Crystal Oscillator................................................................................................55
13.6. External RC Oscillator................................................................................................................ 56
13.7. Calibrated Internal RC Oscillator................................................................................................56
13.8. External Clock............................................................................................................................ 57
13.9. Timer/Counter Oscillator.............................................................................................................58
13.10. Register Description...................................................................................................................58
14. Power Management and Sleep Modes................................................................... 61
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
14.7.
14.8.
14.9.
Sleep Modes...............................................................................................................................61
Idle Mode....................................................................................................................................62
ADC Noise Reduction Mode.......................................................................................................62
Power-down Mode......................................................................................................................62
Power-save Mode.......................................................................................................................62
Standby Mode............................................................................................................................ 63
Extended Standby Mode............................................................................................................ 63
Minimizing Power Consumption................................................................................................. 63
Register Description................................................................................................................... 65
15. System Control and Reset.......................................................................................67
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.
Resetting the AVR...................................................................................................................... 67
Reset Sources............................................................................................................................67
Internal Voltage Reference.........................................................................................................71
Watchdog Timer......................................................................................................................... 71
Timed Sequences for Changing the Configuration of the Watchdog Timer............................... 72
Register Description................................................................................................................... 73
16. Interrupts................................................................................................................. 77
16.1. Interrupt Vectors in ATmega64A.................................................................................................77
16.2. Register Description................................................................................................................... 82
17. External Interrupts................................................................................................... 85
17.1. Register Description................................................................................................................... 85
18. I/O Ports.................................................................................................................. 92
18.1.
18.2.
18.3.
18.4.
Overview.....................................................................................................................................92
Ports as General Digital I/O........................................................................................................93
Alternate Port Functions.............................................................................................................96
Register Description..................................................................................................................111
19. Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers....................... 134
19.1.
19.2.
19.3.
19.4.
19.5.
Overview...................................................................................................................................134
Internal Clock Source............................................................................................................... 134
Prescaler Reset........................................................................................................................134
External Clock Source..............................................................................................................134
Register Description................................................................................................................. 135
20. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3).................................137
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20.1. Features................................................................................................................................... 137
20.2. Overview...................................................................................................................................137
20.3. Accessing 16-bit Registers.......................................................................................................140
20.4. Timer/Counter Clock Sources.................................................................................................. 142
20.5. Counter Unit............................................................................................................................. 142
20.6. Input Capture Unit.................................................................................................................... 143
20.7. Output Compare Units..............................................................................................................146
20.8. Compare Match Output Unit.....................................................................................................147
20.9. Modes of Operation..................................................................................................................148
20.10. Timer/Counter Timing Diagrams.............................................................................................. 156
20.11. Register Description................................................................................................................. 157
21. 8-bit Timer/Counter0 with PWM and Asynchronous Operation............................. 192
21.1. Features................................................................................................................................... 192
21.2. Overview...................................................................................................................................192
21.3. Timer/Counter Clock Sources.................................................................................................. 193
21.4. Counter Unit............................................................................................................................. 193
21.5. Output Compare Unit................................................................................................................194
21.6. Compare Match Output Unit.....................................................................................................196
21.7. Modes of Operation..................................................................................................................197
21.8. Timer/Counter Timing Diagrams...............................................................................................201
21.9. Asynchronous Operation of the Timer/Counter........................................................................ 203
21.10. Timer/Counter Prescaler.......................................................................................................... 204
21.11. Register Description................................................................................................................. 205
22. 8-bit Timer/Counter2 with PWM.............................................................................215
22.1.
22.2.
22.3.
22.4.
22.5.
22.6.
22.7.
22.8.
22.9.
Features................................................................................................................................... 215
Overview...................................................................................................................................215
Timer/Counter Clock Sources.................................................................................................. 216
Counter Unit............................................................................................................................. 216
Output Compare Unit................................................................................................................217
Compare Match Output Unit.....................................................................................................219
Modes of Operation..................................................................................................................220
Timer/Counter Timing Diagrams...............................................................................................224
Register Description................................................................................................................. 225
23. Output Compare Modulator (OCM1C2).................................................................233
23.1. Overview...................................................................................................................................233
23.2. Description................................................................................................................................233
24. SPI – Serial Peripheral Interface........................................................................... 235
24.1.
24.2.
24.3.
24.4.
24.5.
Features................................................................................................................................... 235
Overview...................................................................................................................................235
SS Pin Functionality................................................................................................................. 238
Data Modes.............................................................................................................................. 239
Register Description................................................................................................................. 240
25. USART...................................................................................................................245
25.1. Features................................................................................................................................... 245
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25.2. Overview...................................................................................................................................245
25.3. Clock Generation......................................................................................................................247
25.4. Frame Formats.........................................................................................................................250
25.5. USART Initialization..................................................................................................................251
25.6. Data Transmission – The USART Transmitter......................................................................... 252
25.7. Data Reception – The USART Receiver.................................................................................. 255
25.8. Asynchronous Data Reception.................................................................................................258
25.9. Multi-Processor Communication Mode.....................................................................................261
25.10. Examples of Baud Rate Setting............................................................................................... 262
25.11. Register Description................................................................................................................. 265
26. TWI - Two-wire Serial Interface............................................................................. 274
26.1.
26.2.
26.3.
26.4.
26.5.
26.6.
26.7.
26.8.
Features................................................................................................................................... 274
Overview...................................................................................................................................274
Two-Wire Serial Interface Bus Definition..................................................................................276
Data Transfer and Frame Format.............................................................................................277
Multi-master Bus Systems, Arbitration and Synchronization....................................................280
Using the TWI...........................................................................................................................281
Multi-master Systems and Arbitration.......................................................................................298
Register Description................................................................................................................. 299
27. Analog Comparator............................................................................................... 306
27.1. Overview...................................................................................................................................306
27.2. Analog Comparator Multiplexed Input...................................................................................... 306
27.3. Register Description................................................................................................................. 307
28. ADC - Analog to Digital Converter......................................................................... 311
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
Features....................................................................................................................................311
Overview...................................................................................................................................311
Starting a Conversion...............................................................................................................313
Prescaling and Conversion Timing...........................................................................................314
Changing Channel or Reference Selection.............................................................................. 317
ADC Noise Canceler................................................................................................................ 318
ADC Conversion Result............................................................................................................322
Register Description................................................................................................................. 324
29. JTAG Interface and On-chip Debug System..........................................................335
29.1. Features................................................................................................................................... 335
29.2. Overview...................................................................................................................................335
29.3. TAP – Test Access Port............................................................................................................ 336
29.4. TAP Controller.......................................................................................................................... 337
29.5. Using the Boundary-scan Chain...............................................................................................338
29.6. Using the On-chip Debug System............................................................................................ 338
29.7. On-chip Debug Specific JTAG Instructions.............................................................................. 339
29.8. Using the JTAG Programming Capabilities.............................................................................. 340
29.9. Bibliography..............................................................................................................................340
29.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................340
29.11. Data Registers..........................................................................................................................341
29.12. Boundry-scan Specific JTAG Instructions................................................................................ 343
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29.13. Boundary-scan Chain...............................................................................................................344
29.14. ATmega64A Boundary-scan Order.......................................................................................... 354
29.15. Boundary-scan Description Language Files............................................................................ 363
29.16. Register Description.................................................................................................................363
30. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 366
30.1.
30.2.
30.3.
30.4.
30.5.
30.6.
30.7.
30.8.
30.9.
Features................................................................................................................................... 366
Overview...................................................................................................................................366
Application and Boot Loader Flash Sections............................................................................366
Read-While-Write and No Read-While-Write Flash Sections...................................................367
Boot Loader Lock Bits.............................................................................................................. 369
Entering the Boot Loader Program...........................................................................................370
Addressing the Flash During Self-Programming...................................................................... 371
Self-Programming the Flash.....................................................................................................372
Register Description................................................................................................................. 380
31. Memory Programming........................................................................................... 383
31.1. Program and Data Memory Lock Bits.......................................................................................383
31.2. Fuse Bits...................................................................................................................................384
31.3. Signature Bytes........................................................................................................................ 386
31.4. Calibration Byte........................................................................................................................ 386
31.5. Page Size................................................................................................................................. 387
31.6. Parallel Programming...............................................................................................................387
31.7. Parallel Programming Parameters, Pin Mapping, and Commands.......................................... 394
31.8. Serial Downloading...................................................................................................................396
31.9. Serial Programming Pin Mapping.............................................................................................396
31.10. Programming Via the JTAG Interface.......................................................................................400
32. Electrical Characteristics – TA = -40°C to 85°C.....................................................415
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
32.7.
32.8.
32.9.
DC Characteristics....................................................................................................................415
Speed Grades.......................................................................................................................... 417
Clock Characteristics................................................................................................................417
System and Reset Characteristics........................................................................................... 418
Two-wire Serial Interface Characteristics................................................................................. 419
Parallel Programming Characteristics...................................................................................... 421
SPI Timing Characteristics....................................................................................................... 422
ADC Characteristics................................................................................................................. 424
External Data Memory Timing.................................................................................................. 427
33. Electrical Characteristics – TA = -40°C to 105°C...................................................433
33.1. DC Characteristics....................................................................................................................433
34. Typical Characteristics – TA = -40°C to 85°C........................................................ 436
34.1.
34.2.
34.3.
34.4.
34.5.
34.6.
Active Supply Current...............................................................................................................436
Idle Supply Current...................................................................................................................440
Power-Down Supply Current....................................................................................................443
Power-Save Supply Current.....................................................................................................444
Standby Supply Current........................................................................................................... 445
Pin Pull-up................................................................................................................................ 446
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34.7. Pin Driver Strength................................................................................................................... 449
34.8. Pin Thresholds and Hysteresis.................................................................................................451
34.9. BOD Thresholds and Analog Comparator Offset..................................................................... 454
34.10. Internal Oscillator Speed..........................................................................................................455
34.11. Current Consumption of Peripheral Units.................................................................................462
34.12. Current Consumption in Reset and Reset Pulse width............................................................ 464
35. Typical Characteristics – TA = -40°C to 105°C...................................................... 466
35.1. Active Supply Current...............................................................................................................466
35.2. Idle Supply Current...................................................................................................................469
35.3. Power-down Supply Current.....................................................................................................472
35.4. Pin Pull-up................................................................................................................................ 473
35.5. Pin Driver Strength................................................................................................................... 475
35.6. Pin Thresholds and Hysteresis.................................................................................................477
35.7. BOD Thresholds and Analog Comparator Offset..................................................................... 480
35.8. Internal Oscillator Speed.......................................................................................................... 482
35.9. Current Consumption of Peripheral Units.................................................................................487
35.10. Current Consumption in Reset and Reset Pulsewidth............................................................. 490
36. Register Summary.................................................................................................492
37. Instruction Set Summary....................................................................................... 495
38. Packaging Information...........................................................................................500
38.1. 64A........................................................................................................................................... 500
38.2. 64M1.........................................................................................................................................501
39. Errata.....................................................................................................................502
39.1. ATmega64A Rev. D.................................................................................................................. 502
40. Datasheet Revision History................................................................................... 504
40.1. 8160E - 07/2015.......................................................................................................................504
40.2. 8160D - 02/2013.......................................................................................................................504
40.3. 8160C - 07/2009.......................................................................................................................504
40.4. 8160B - 03/2009.......................................................................................................................504
40.5. 8160A - 08/2008.......................................................................................................................504
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1.
Description
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with ReadWhile- Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general
purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes
and PWM, two USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional
differential input stage with programmable gain, programmable Watchdog Timer with internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip
Debug system and programming, and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with
low power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer
continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot Program can use any interface to download the Application Program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega64A is a powerful microcontroller that
provides a highly-flexible and cost-effective solution to many embedded control applications.
The ATmega64A AVR is supported with a full suite of program and system development tools including: C
compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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2.
Configuration Summary
Features
ATmega64A
Pin count
64
Flash (KB)
64
SRAM (KB)
4
EEPROM (KB)
2
General Purpose I/O pins
53
SPI
1
TWI (I2C)
1
USART
2
ADC
10-bit, up to 76.9ksps (15ksps at max resolution)
ADC channels
6 (8 in TQFP and QFN/MLF packages)
AC propagation delay
Typ 400ns
8-bit Timer/Counters
2
16-bit Timer/Counters
1
PWM channels
8
RC Oscillator
+/-3%
VREF Bandgap
Operating voltage
2.7 - 5.5V
Max operating frequency
16MHz
Temperature range
-55°C to +125°C
JTAG
Yes
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3.
Ordering Information
Speed (MHz)
16
Power Supply
2.7 - 5.5V
Ordering Code(2)
Package(1)
ATmega64A-AU
ATmega64A-AUR(3)
64A
64A
ATmega64A-MU
64M1
ATmega64A-MUR(3)
64M1
ATmega64A-AN
ATmega64A-ANR(3)
64A
64A
ATmega64A-MN
64M1
ATmega64A-MNR(3)
64M1
Operational Range
Industrial (-40oC to 85oC)
Extended (-40oC to 105oC)(4)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape and Reel
4. See characterization specifications at 105°C
Package Type
64A
64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package
(QFN/MLF)
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4.
Block Diagram
Figure 4-1 Block Diagram
SRAM
TCK
TMS
TDI
TDO
JTAG
OCD
PARPROG
PEN
PDI
PDO
SCK
CPU
FLASH
NVM
programming
EEPROMIF
SERPROG
ExtMem
AD[7:0]
A[15:8]
RD/WR/ALE
I/O
PORTS
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[7:0]
PF[7:0]
PG[4:0]
ExtInt
INT[7:0]
Clock generation
XTAL1
XTAL2
TOSC1
8MHz
Crystal Osc
8MHz
Calib RC
12MHz
External
RC Osc
External
clock
32.768kHz
XOSC
1MHz int
osc
Power
management
and clock
control
D
A
T
A
B
U
S
EEPROM
TOSC2
VCC
RESET
GND
Power
Supervision
POR/BOD &
RESET
Watchdog
Timer
Internal
Reference
MISO
MOSI
SCK
SS
SPI
SDA
SCL
TWI
RxD0
TxD0
XCK0
USART 0
RxD1
TxD1
XCK1
USART 1
ADC
AC
TC 0
(8-bit async)
ADC[7:0]
AREF
AIN0
AIN1
ACO
ADCMUX
OC0
TC 1
OC1A/B/C
T1
ICP1
TC 2
T2
OC2
TC 3
OC3A/B
T3
ICP3
(16-bit)
(8-bit)
(16-bit)
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5.
ATmega103 and ATmega64A Compatibility
The ATmega64A is a highly complex microcontroller where the number of I/O locations supersedes the
64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the
ATmega103, all I/O locations present in ATmega103 have the same location in ATmega64A. Most
additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (that is, in the
ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and
ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM
space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might
be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility
mode can be selected by programming the fuse M103C. In this mode, none of the functions in the
Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended
Interrupt vectors are removed.
The Atmel AVR ATmega64A is 100% pin compatible with ATmega103, and can replace the ATmega103
on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega64A” describes
what the user should be aware of replacing the ATmega103 by an ATmega64A.
5.1.
ATmega103 Compatibility Mode
By programming the M103C fuse, the ATmega64A will be compatible with the ATmega103 regards to
RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega64A are
not available in this compatibility mode, these features are listed below:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the
Baud Rate Register is available.
One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters with
three compare registers.
Two-wire serial interface is not supported.
Port C is output only.
Port G serves alternate functions only (not a general I/O port).
Port F serves as digital input only in addition to analog input to the ADC.
Boot Loader capabilities is not supported.
It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
The External Memory Interface can not release any Address pins for general I/O, neither configure
different wait-states to different External Memory Address sections.
In addition, there are some other minor differences to make it more compatible to ATmega103:
Only EXTRF and PORF exists in MCUCSR.
Timed sequence not required for Watchdog Time-out change.
External Interrupt pins 3 - 0 serve as level interrupt only.
USART has no FIFO buffer, so data overrun comes earlier.
Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega64A.
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6.
Pin Configurations
Figure 6-1 Pinout ATmega64A
Power
Ground
Programming/debug
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Digital
Analog
Crystal/Osc
External Memory
PEN
1
48
PA3 (AD3)
38
PC3 (A11)
(MOSI) PB2
12
37
PC2 (A10)
(MISO) PB3
13
36
PC1 (A9)
(OC0) PB4
14
35
PC0 (A8)
(OC1A) PB5
15
34
PG1 (RD)
(OC1B) PB6
16
33
PG0 (WR)
32
11
31
(SCK) PB1
(T2) PD7
PC4 (A12)
(T1) PD6
39
30
10
(XCK1) PD5
(SS) PB0
29
PC5 (A13)
(ICP1) PD4
40
28
9
(TXD1/INT3) PD3
(ICP3/INT7) PE7
27
PC6 (A14)
26
PC7 (A15)
41
(SDA/INT1) PD1
42
8
(RXD1/INT2) PD2
7
(T3/INT6) PE6
25
(OC3C/INT5) PE5
(SCL/INT0) PD0
PG2 (ALE)
24
43
XTAL1
6
23
(OC3B/INT4) PE4
XTAL2
PA7 (AD7)
22
44
21
5
VCC
(OC3A/AIN1) PE3
GND
PA6 (AD6)
20
45
RESET
4
19
(XCK0/AIN0) PE2
(TOSC1) PG4
PA5 (AD5)
18
PA4 (AD4)
46
(TOSC2) PG3
47
3
17
2
(OC2/OC1C) PB7
(RXD0/PDI) PE0
(TXD0/PDO) PE1
Note: The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF
package should be soldered to ground.
6.1.
Pin Descriptions
6.1.1.
VCC
Digital supply voltage.
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6.1.2.
GND
Ground.
6.1.3.
Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
A pins are tristated when a reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port A.
Related Links
Alternate Functions of Port A on page 98
6.1.4.
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port B.
Related Links
Alternate Functions of Port B on page 100
6.1.5.
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tristated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of special features of the ATmega64A as listed in Alternate Functions of
Port C. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated
when a reset condition becomes active.
Note: The Atmel AVR ATmega64A is by default shipped in ATmega103 compatibility mode. Thus, if the
parts are not programmed before they are put on the PCB, PORTC will be output during first power up,
and until the ATmega103 compatibility mode is disabled.
Related Links
Alternate Functions of Port C on page 102
6.1.6.
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tristated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port D.
Related Links
Alternate Functions of Port D on page 103
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6.1.7.
Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
E pins are tristated when a reset condition becomes active, even if the clock is not running.
Port E also serves the functions of various special features of the ATmega64A as listed in Alternate
Functions of Port E.
Related Links
Alternate Functions of Port E on page 105
6.1.8.
Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can
provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset
condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up
resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input Port only.
Related Links
Alternate Functions of Port F on page 108
6.1.9.
Port G (PG4:PG0)
Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
G pins are tristated when a reset condition becomes active, even if the clock is not running.
Port G also serves the functions of various special features.
The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.
In Atmel AVR ATmega103 compatibility mode, these pins only serves as strobes signals to the external
memory as well as input to the 32kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and
PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3
and PG4 are oscillator pins.
Related Links
Alternate Functions of Port G on page 110
6.1.10.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. The minimum pulse length is given in System and Reset Characteristics. Shorter
pulses are not guaranteed to generate a reset.
Related Links
System and Reset Characteristics on page 418
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6.1.11.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
6.1.12.
XTAL2
Output from the inverting Oscillator amplifier.
6.1.13.
AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC,
even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
6.1.14.
AREF
AREF is the analog reference pin for the A/D Converter.
6.1.15.
PEN
PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high. By
holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode.
PEN has no function during normal operation.
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7.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download
on http://www.atmel.com/avr.
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8.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
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9.
About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware
that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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10.
Capacitive Touch Sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most
®
Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix
acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.
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11.
AVR CPU Core
11.1.
Overview
This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is
to ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 11-1 Block Diagram of the AVR MCU Architecture
Da ta Bus 8-bit
Fla s h
P rogra m
Me mory
P rogra m
Counte r
S ta tus
a nd Control
32 x 8
Ge ne ra l
P urpos e
Re gis tre rs
Control Line s
Dire ct Addre s s ing
Ins truction
De code r
Indire ct Addre s s ing
Ins truction
Re gis te r
Inte rrupt
Unit
SPI
Unit
Wa tchdog
Time r
ALU
Ana log
Compa ra tor
i/O Module 1
Da ta
S RAM
i/O Module 2
i/O Module n
EEP ROM
I/O Line s
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the Program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
Program memory. This concept enables instructions to be executed in every clock cycle. The Program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash Program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
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The Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
Program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the Application
program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the Register File, 0x20 - 0x5F. In addition, the ATmega64A has Extended I/O space
from $60 in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
11.2.
ALU – Arithmetic Logic Unit
The high-performance Atmel AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide
a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the
“Instruction Set” section for a detailed description.
11.3.
Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. Note that the Status Register is updated after all ALU operations, as specified in the
Instruction Set Reference. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
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11.3.1.
SREG – The AVR Status Register
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses. The device is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space
from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Name: SREG
Offset: 0x3F
Reset: 0x00
Property: When addressing I/O Registers as data space the offset address is 0x5F
Bit
Access
Reset
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable Register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the Instruction Set Reference.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD
arithmetic. See the “Instruction Set Description” for detailed information.
Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the “Instruction Set Description” for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set
Description” for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
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Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
11.4.
General Purpose Register File
The Register File is optimized for the Atmel AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
•
•
•
•
One 8-bit output operand and one 8-bit result input.
Two 8-bit output operands and one 8-bit result input.
Two 8-bit output operands and one 16-bit result input.
One 16-bit output operand and one 16-bit result input.
The following figure shows the structure of the 32 general purpose working registers in the CPU.
Figure 11-2 AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
Ge ne ra l
R14
0x0E
P urpos e
R15
0x0F
Working
R16
0x10
Re gis te rs
R17
0x11
…
R26
0x1A
X-re gis te r Low Byte
R27
0x1B
X-re gis te r High Byte
R28
0x1C
Y-re gis te r Low Byte
R29
0x1D
Y-re gis te r High Byte
R30
0x1E
Z-re gis te r Low Byte
R31
0x1F
Z-re gis te r High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions.
As shown in the figure above, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as
SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-,
Y-, and Z-pointer Registers can be set to index any register in the file.
11.4.1.
The X-register, Y-register and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X,
Y and Z are defined as described in the following figure.
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Figure 11-3 The X-, Y- and Z-Registers
15
X-re gis te r
XH
XL
7
0
7
0
R27 (0x1B)
15
Y-re gis te r
R26 (0x1A)
YH
YL
7
0
Z-re gis te r
ZH
7
0
0
7
0
R29 (0x1D)
15
0
R28 (0x1C)
ZL
7
0
0
R31 (0x1F)
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).
11.5.
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the
Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory
locations. This implies that a Stack PUSH command decreases the Stack Pointer. If software reads the
Program Counter from the Stack after a call or an interrupt, unused bits (bit 15) should be masked out.
The Stack Pointer points to the data SRAM Stack area where the subroutine and interrupt Stacks are
located. This Stack space in the data SRAM must be defined by the program before any subroutine calls
are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack
Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is
decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction,
and it is incremented by two when data is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
Bit
15
14
13
12
11
10
9
8
0x3E
S P15
S P14
S P13
S P12
S P11
S P10
S P9
S P8
S PH
0x3D
S P7
S P6
S P5
S P4
S P3
S P2
S P1
S P0
S PL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Re a d/Write
Initia l Va lue
0
0
11.6.
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The Atmel AVR CPU
is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No
internal clock division is used.
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The following figure shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to
obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per
clocks, and functions per power-unit.
Figure 11-4 The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCP U
1s t Ins truction Fe tch
1s t Ins truction Exe cute
2nd Ins truction Fe tch
2nd Ins truction Exe cute
3rd Ins truction Fe tch
3rd Ins truction Exe cute
4th Ins truction Fe tch
The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 11-5 Single Cycle ALU Operation
T1
T2
T3
T4
clkCP U
Tota l Exe cution Time
Re gis te r Ope ra nds Fe tch
ALU Ope ra tion Exe cute
Re s ult Write Ba ck
11.7.
Reset and Interrupt Handling
The Atmel AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned
individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the
Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may
be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section Memory Programming for details.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt
Vectors. The complete list of Vectors is shown in Interrupts . The list also determines the priority levels of
the different interrupts. The lower the address the higher is the priority level. RESET has the highest
priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the
start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the MCU Control
Register (MCUCR). Refer to Interrupts for more information. The Reset Vector can also be moved to the
start of the boot Flash section by programming the BOOTRST Fuse, see Boot Loader Support – ReadWhile-Write Self-Programming.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
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interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt
Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to
execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt
Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt
condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt
Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by
order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored
when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
The following example shows how this can be used to avoid interrupts during the timed EEPROM write
sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1