ATmega16M1/ATmega32M1/ATmega64M1/
ATmega32C1/ATmega64C1 Automotive
8-bit AVR Microcontroller with 16K/32K/64Kbytes
In-system
DATASHEET
Features
● High performance, low power AVR® 8-bit microcontroller
● Advanced RISC architecture
●
●
●
●
●
131 powerful instructions - most single clock cycle execution
32 x 8 general purpose working registers
Fully static operation
Up to 1MIPS throughput per MHz
On-chip 2-cycle multiplier
● Data and non-volatile program memory
● 16K/32K/64Kbytes flash of in-system programmable program memory
● Endurance: 10,000 write/erase cycles
● Optional boot code section with independent lock bits
● In-system programming by on-chip boot program
● True read-while-write operation
● 512/1024/2048 Bytes of in-system programmable EEPROM
● Endurance: 100,000 write/erase cycles
● Programming lock for flash program and EEPROM data security
● 1024/2048/4096 bytes internal SRAM
● On chip debug interface (debugWIRE)
● CAN 2.0A/B with 6 message objects - ISO 16845 certified(1)
● LIN 2.1 and 1.3 controller or 8-Bit UART
● One 12-bit high-speed PSC (power stage controller) (only Atmel®
ATmega16/32/64M1)
●
●
●
●
Non overlapping inverted PWM output pins with flexible dead-time
Variable PWM duty cycle and frequency
Synchronous update of all PWM registers
Auto stop function for emergency event
● Peripheral features
● One 8-bit general purpose Timer/Counter with separate prescaler, compare mode
and capture mode
● One 16-bit general purpose Timer/Counter with separate prescaler, compare
mode and capture mode
● One master/slave SPI serial interface
7647O-AVR-01/15
● 10-bit ADC
● Up to 11 single ended channels and 3 fully differential ADC channel pairs
● Programmable gain (5x, 10x, 20x, 40x) on differential channels
● Internal reference voltage
● Direct power supply voltage measurement
● 10-bit DAC for variable voltage reference (comparators, ADC)
● Four analog comparators with variable threshold detection
● 100µA ±6% current source (LIN node identification)
● Interrupt and wake-up on pin change
● Programmable watchdog timer with separate on-chip oscillator
● On-chip temperature sensor
● Special microcontroller features
●
●
●
●
Low power idle, noise reduction, and power down modes
Power on reset and programmable brown out detection
In-system programmable via SPI port
High precision crystal oscillator for CAN operations (16MHz)
● Internal calibrated RC oscillator (8MHz)
● On-chip PLL for fast PWM (32MHz, 64MHz) and CPU (16MHz) (only Atmel® ATmega16/32/64M1)
● Operating voltage:
● 2.7V - 5.5V
● Extended operating temperature:
● –40°C to +125°C
● Core speed grade:
● 0 - 8MHz at 2.7 - 4.5V
● 0 - 16MHz at 4.5 - 5.5V
Note:
Table 1.
1.
See certification on Atmel web site and note on Section 16.4.3 “Baud Rate” on page 148.
ATmega32/64/M1/C1 Product Line-up
Part Number
ATmega32C1
ATmega64C1
ATmega16M1
ATmega32M1
ATmega64M1
Flash size
32Kbyte
64Kbyte
16Kbyte
32Kbyte
64Kbyte
RAM size
2048 bytes
4096 bytes
1024 bytes
2048 bytes
4096 bytes
EEPROM size
1024 bytes
2048 bytes
512 bytes
1024 bytes
2048 bytes
8-bit timer
Yes
16-bit timer
Yes
PSC
No
Yes
PWM outputs
4
4
10
10
10
Fault inputs (PSC)
0
0
3
3
3
PLL
No
Yes
10-bit ADC channels
11 single
3 differential
10-bit DAC
Yes
analog comparators
4
Current source
Yes
CAN
Yes
LIN/UART
Yes
On-chip temp.
sensor
Yes
SPI interface
Yes
2
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
Pin Configurations
PC7 (D2A/AMP2+/PCINT15)
PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5)
PB6 (ADC7/PSCOUT1B/PCINT6)
PB7 (ADC4/PSCOUT0B/SCK/PCINT7)
PC0 (PCINT8/INT3/PSCOUT1A)
PD0 (PCINT16/PSCOUT0A)
PE0 (PCINT24/RESET/OCD)
PD1 (PCINT17/PSCIN0/CLKO)
Figure 1-1. ATmega16/32/64M1 TQFP32/QFN32 (7*7mm) Package
32 31 30 29 28 27 26 25
Note:
(PCINT18/PSCIN2/OC1A/MISO_A) PD2
1
24
PB4 (AMP0+/PCINT4)
(PCINT19/TXD/TXLIN/OC0A/MOSI_A) PD3
2
23
PB3 (AMP0-/PCINT3)
(PCINT9/PSCIN1/OC1B/SS_A) PC1
3
22
PC6 (ADC10-/ACMP1/PCINT14)
4
21
AREF(ISRC)
5
20
AGND
(PCINT10/T0/TXCAN) PC2
6
19
AVCC
(PCINT11/T1/RXCAN/ICP1B) PC3
7
18
PC5 (ADC9/ACMP3/AMP1+/PCINT13)
(PCINT0/MISO/PSCOUT2A) PB0
8
17
PC4 (ADC8/ACMPN3/AMP1-/PCINT12)
(ADC5/INT1/ACMPN0/PCINT2) PB2
(ACMP0/PCINT23) PD7
(ADC3/ACMPN2/INT0/PCINT22) PD6
(ADC2/ACMP2/PCINT21) PD5
(PCINT26/ADC0/XTAL2) PE2
10 11 12 13 14 15 16
(PCINT20/ADC1/RXD/RXLIN/ICP1A/SCK_A) PD4
9
(PCINT25/OC0B/XTAL1) PE1
VCC
GND
(PCINT1/MOSI/PSCOUT2B) PB1
1.
On the engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on
PC4. It is located on PE2.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
3
PC7 (D2A/AMP2+/PCINT15)
PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5)
PB6 (ADC7/PCINT6)
PB7 (ADC4/SCK/PCINT7)
PC0 (PCINT8/INT3)
PD0 (PCINT16)
PE0 (PCINT24/RESET/OCD)
PD1 (PCINT17/CLKO)
Figure 1-2. ATmega32/64C1 TQFP32/QFN32 (7*7 mm) Package
32 31 30 29 28 27 26 25
Note:
4
(PCINT18/OC1A/MISO_A) PD2
1
24
PB4 (AMP0+/PCINT4)
(PCINT19/TXD/TXLIN/OC0A/MOSI_A) PD3
2
23
PB3 (AMP0-/PCINT3)
(PCINT9/OC1B/SS_A) PC1
3
22
PC6 (ADC10-/ACMP1/PCINT14)
VCC
4
21
AREF(ISRC)
GND
5
20
AGND
19
AVCC
7
18
PC5 (ADC9/ACMP3/AMP1+/PCINT13)
(PCINT0/MISO) PB0
8
17
PC4 (ADC8/ACMPN3/AMP1-/PCINT12)
(ADC5/INT1/ACMPN0/PCINT2) PB2
(ACMP0/PCINT23) PD7
(ADC3/ACMPN2/INT0/PCINT22) PD6
(ADC2/ACMP2/PCINT21) PD5
(PCINT26/ADC0/XTAL2) PE2
10 11 12 13 14 15 16
(PCINT20/ADC1/RXD/RXLIN/ICP1A/SCK_A) PD4
9
(PCINT1/MOSI) PB1
6
(PCINT25/OC0B/XTAL1) PE1
(PCINT10/T0/TXCAN) PC2
(PCINT11/T1/RXCAN/ICP1B) PC3
On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located
on PC4. It is located on PE2.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
1.1
Pin Descriptions
Table 1-1.
Pin Out Description
QFN32 Pin
Number
Mnemonic
Type
Name, Function and Alternate Function
5
GND
Power
Ground: 0V reference
20
AGND
Power
Analog Ground: 0V reference for analog part
4
VCC
Power
Power Supply
Power
Analog Power Supply: This is the power supply voltage for analog
part
19
AVCC
For a normal use this pin must be connected.
21
AREF
Power
Analog Reference: reference for analog converter. This is the
reference voltage of the A/D converter. As output, can be used by
external analog
ISRC (Current Source Output)
MISO (SPI Master In Slave Out)
8
PB0
I/O
PSCOUT2A (PSC Module 2 Output A)
PCINT0 (Pin Change Interrupt 0)
MOSI (SPI Master Out Slave In)
9
PB1
I/O
PSCOUT2B (PSC Module 2 Output B)
PCINT1 (Pin Change Interrupt 1)
ADC5 (Analog Input Channel 5 )
16
PB2
I/O
INT1 (External Interrupt 1 Input)
ACMPN0 (analog comparator 0 Negative Input)
PCINT2 (Pin Change Interrupt 2)
23
PB3
I/O
24
PB4
I/O
AMP0- (Analog Differential Amplifier 0 Negative Input)
PCINT3 (Pin Change Interrupt 3)
AMP0+ (Analog Differential Amplifier 0 Positive Input)
PCINT4 (Pin Change Interrupt 4)
ADC6 (Analog Input Channel 6)
INT2 (External Interrupt 2 Input)
26
PB5
I/O
ACMPN1 (analog comparator 1 Negative Input)
AMP2- (Analog Differential Amplifier 2 Negative Input)
PCINT5 (Pin Change Interrupt 5)
ADC7 (Analog Input Channel 7)
27
PB6
I/O
PSCOUT1B (PSC Module 1 Output A)
PCINT6 (Pin Change Interrupt 6)
ADC4 (Analog Input Channel 4)
28
PB7
I/O
PSCOUT0B (PSC Module 0 Output B)
SCK (SPI Clock)
PCINT7 (Pin Change Interrupt 7)
PSCOUT1A (PSC Module 1 Output A)
30
Note:
1.
PC0
I/O
INT3 (External Interrupt 3 Input)
PCINT8 (Pin Change Interrupt 8)
On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located
on PC4. It is located on PE2.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
5
Table 1-1.
Pin Out Description (Continued)
QFN32 Pin
Number
Mnemonic
Type
Name, Function and Alternate Function
PSCIN1 (PSC Digital Input 1)
3
PC1
I/O
OC1B (Timer 1 Output Compare B)
SS_A (Alternate SPI Slave Select)
PCINT9 (Pin Change Interrupt 9)
T0 (Timer 0 clock input)
6
PC2
I/O
TXCAN (CAN Transmit Output)
PCINT10 (Pin Change Interrupt 10)
T1 (Timer 1 clock input)
7
PC3
I/O
RXCAN (CAN Receive Input)
ICP1B (Timer 1 input capture alternate B input)
PCINT11 (Pin Change Interrupt 11)
ADC8 (Analog Input Channel 8)
17
PC4
I/O
AMP1- (Analog Differential Amplifier 1 Negative Input)
ACMPN3 (analog comparator 3 Negative Input)
PCINT12 (Pin Change Interrupt 12)
ADC9 (Analog Input Channel 9)
18
PC5
I/O
AMP1+ (Analog Differential Amplifier 1 Positive Input)
ACMP3 (analog comparator 3 Positive Input)
PCINT13 (Pin Change Interrupt 13)
ADC10 (Analog Input Channel 10)
22
PC6
I/O
ACMP1 (analog comparator 1 Positive Input)
PCINT14 (Pin Change Interrupt 14)
D2A (DAC output)
25
PC7
I/O
AMP2+ (Analog Differential Amplifier 2 Positive Input)
PCINT15 (Pin Change Interrupt 15)
29
PD0
I/O
32
PD1
I/O
PSCOUT0A (PSC Module 0 Output A)
PCINT16 (Pin Change Interrupt 16)
PSCIN0 (PSC Digital Input 0)
CLKO (System Clock Output)
PCINT17 (Pin Change Interrupt 17)
OC1A (Timer 1 Output Compare A)
1
PD2
I/O
PSCIN2 (PSC Digital Input 2)
MISO_A (Programming and alternate SPI Master In Slave Out)
PCINT18 (Pin Change Interrupt 18)
TXD (UART Tx data)
TXLIN (LIN Transmit Output)
2
PD3
I/O
OC0A (Timer 0 Output Compare A)
SS (SPI Slave Select)
MOSI_A (Programming and alternate Master Out SPI Slave In)
Note:
6
1.
PCINT19 (Pin Change Interrupt 19)
On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located
on PC4. It is located on PE2.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
Table 1-1.
Pin Out Description (Continued)
QFN32 Pin
Number
Mnemonic
Type
Name, Function and Alternate Function
ADC1 (Analog Input Channel 1)
RXD (UART Rx data)
12
PD4
I/O
RXLIN (LIN Receive Input)
ICP1A (Timer 1 input capture alternate A input)
SCK_A (Programming and alternate SPI Clock)
PCINT20 (Pin Change Interrupt 20)
ADC2 (Analog Input Channel 2)
13
PD5
I/O
ACMP2 (analog comparator 2 Positive Input)
PCINT21 (Pin Change Interrupt 21)
ADC3 (Analog Input Channel 3)
14
PD6
I/O
ACMPN2 (analog comparator 2 Negative Input)
INT0 (External Interrupt 0 Input)
PCINT22 (Pin Change Interrupt 22)
15
PD7
I/O
31
PE0
I/O or I
ACMP0 (analog comparator 0 Positive Input)
PCINT23 (Pin Change Interrupt 23)
RESET (Reset Input)
OCD (On Chip Debug I/O)
PCINT24 (Pin Change Interrupt 24)
XTAL1 (XTAL Input)
10
PE1
I/O
OC0B (Timer 0 Output Compare B)
PCINT25 (Pin Change Interrupt 25)
XTAL2 (XTAL Output)
11
Note:
1.
PE2
I/O
ADC0 (Analog Input Channel 0)
PCINT26 (Pin Change Interrupt 26)
On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located
on PC4. It is located on PE2.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
7
2.
Overview
The Atmel® ATmega16/32/64/M1/C1 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega16/32/64/M1/C1 achieves
throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status and
Control
32 x 8
General
Purpose
Registers
Control Lines
Indirect Addressing
Instruction
Decoder
Direct Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Watchdog
Timer
4 Analog
Comparators
ALU
HW LIN/UART
Timer 0
Data
SRAM
Timer 1
ADC
EEPROM
DAC
I/O Lines
MPSC
Current Source
CAN
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The Atmel ATmega16/32/64/M1/C1 provides the following features: 16K/32K/64K bytes of In-System Programmable Flash
with Read-while-write capabilities, 512/1024/2048 bytes EEPROM, 1024/2048/4096 bytes SRAM, 27 general purpose I/O
lines, 32 general purpose working registers, one Motor Power Stage Controller, two flexible Timer/Counters with compare
modes and PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with programmable
gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual Oscillator, an SPI serial port, an On-chip Debug
system and four software selectable power saving modes.
8
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to
continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or Hardware Reset. The ADC noise reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is
running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the
program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory
programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download
the application program in the application Flash memory. Software in the boot flash section will continue to run while the
application flash section is updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with insystem self-programmable flash on a monolithic chip, the Atmel ATmega16/32/64/M1/C1 is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega16/32/64/M1/C1 AVR is supported with a full suite of program and system development tools including: C
compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2.2
Automotive Quality Grade
The Atmel® ATmega16/32/64/M1/C1 have been developed and manufactured according to the most stringent requirements
of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive
characterization (Temperature and Voltage). The quality and reliability of the ATmega16/32/64/M1/C1 have been verified
during regular product qualification as per AEC-Q100 grade 1.
As indicated in the ordering information paragraph, the products are available in only one temperature grade.
Table 2-1.
Temperature Grade Identification for Automotive Products
Temperature
Temperature Identifier
Comments
–40, +125
Z
Full automotive temperature range
2.3
Pin Descriptions
2.3.1
VCC
Digital supply voltage.
2.3.2
GND
Ground.
2.3.3
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port B also serves the functions of various special features of the Atmel ATmega16/32/64/M1/C1 as listed in Section 9.3.2
“Alternate Functions of Port B” on page 58.
2.3.4
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port C also serves the functions of special features of the ATmega16/32/64/M1/C1 as listed in Section 9.3.3 “Alternate
Functions of Port C” on page 61.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
9
2.3.5
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port D output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, port D pins that are externally pulled
low will source current if the pull-up resistors are activated. The port D pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port D also serves the functions of various special features of the Atmel® ATmega16/32/64/M1/C1 as listed on 64.
2.3.6
Port E (PE2..0) RESET/ XTAL1/ XTAL2
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port E output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, port E pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
If the RSTDISBL fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from
those of the other pins of Port E.
If the RSTDISBL fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum
pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 7-1 on page
39. Shorter pulses are not guaranteed to generate a reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting oscillator amplifier.
The various special features of Port E are elaborated in Section 9.3.5 “Alternate Functions of Port E” on page 67 and Section
5.1 “Clock Systems and their Distribution” on page 25.
2.3.7
AVCC
AVCC is the supply voltage pin for the A/D converter, D/A converter, current source. It should be externally connected to
VCC, even if the ADC, DAC are not used. If the ADC is used, it should be connected to VCC through a low-pass filter (see
Section 18.6.2 “Analog Noise Canceling Techniques” on page 204).
2.3.8
AREF
This is the analog reference pin for the A/D converter.
2.4
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors
include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C
compiler documentation for more details.
10
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
3.
AVR CPU Core
3.1
Introduction
This section discusses the AVR® core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and
handle interrupts.
Architectural Overview
Figure 3-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status and
Control
32 x 8
General
Purpose
Registers
Instruction
Decoder
Control Lines
Indirect Addressing
Instruction
Register
Direct Addressing
3.2
ALU
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and
buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions
to be executed in every clock cycle. The program memory is in-system reprogrammable Flash memory.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This
allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the
register file, the operation is executed, and the result is stored back in the register file – in one clock cycle.
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
11
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling
efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in
Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect
information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole
address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or
32-bit instruction.
Program flash memory space is divided in two sections, the boot program section and the application program section. Both
sections have dedicated Lock bits for write and read/write protection. The SPM (store program memory) instruction that
writes into the application flash memory section must reside in the boot program section.
during interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through
the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR® architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance
with their interrupt vector position. The lower the interrupt vector address, the higher is the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions.
The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F. In
addition, the Atmel ATmega16/32/64/M1/C1 has extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
3.3
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some
implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. See the “Instruction Set” section for a detailed description.
3.4
Status Register
The status register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the status register is
updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for
using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored when returning from an
interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set to enabled the interrupts. The individual interrupt enable control is then performed
in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled independent
of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the
RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and
CLI instructions, as described in the instruction set reference.
12
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit
from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry Is useful in BCD arithmetic. See the
“Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the
“Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the “Instruction Set Description” for
detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed
information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed
information.
3.5
General Purpose Register File
The register file is optimized for the AVR enhanced RISC instruction set. In order to achieve the required performance and
flexibility, the following input/output schemes are supported by the register file:
● One 8-bit output operand and one 8-bit result input
●
●
●
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
13
Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3-2. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle
instructions.
As shown in Figure 3-2, each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the
file.
3.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described
in
Figure 3-3.
Figure 3-3. The X-, Y-, and Z-registers
X-register
15
XH
XL
7
0
7
R27 (0x1B)
Y-register
0
R26 (0x1A)
15
YH
YL
0
7
0
7
0
R29 (0x1D)
Z-register
0
R28 (0x1C)
15
ZH
ZL
0
7
0
7
0
R31 (0x1F)
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and
automatic decrement (see the instruction set reference for details).
14
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
3.6
Stack Pointer
The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after
interrupts and subroutine calls. The stack pointer register always points to the top of the stack. Note that the stack is
implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH
command decreases the stack pointer.
The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located. This stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The stack pointer must be set to point above 0x100. The stack pointer is decremented by one when data is pushed onto the
stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the stack with
subroutine call or interrupt. The stack pointer is incremented by one when data is popped from the stack with the POP
instruction, and it is incremented by two when data is popped from the stack with return from subroutine RET or return from
interrupt RETI.
The AVR® stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only
SPL is needed. In this case, the SPH Register will not be present.
Bit
Read/Write
Initial Value
3.7
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Top address of the SRAM (0x04FF/0x08FF/0x10FF)
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fastaccess Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 3-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
15
Figure 3-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 3-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
3.8
Reset and Interrupt Handling
The AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a separate
program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic
one together with the global interrupt enable bit in the status register in order to enable the interrupt. Depending on the
program counter value, interrupts may be automatically disabled when boot lock bits BLB02 or BLB12 are programmed. This
feature improves software security. See Section 25. “Memory Programming” on page 255 for details.
The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete
list of vectors is shown in Section 8. “Interrupts” on page 47. The list also determines the priority levels of the different
interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is ANACOMP0 –
the analog comparator 0 interrupt. The interrupt vectors can be moved to the start of the boot flash section by setting the
IVSEL bit in the MCU control register (MCUCR). Refer to Section 8. “Interrupts” on page 47 for more information. The reset
vector can also be moved to the start of the boot flash section by programming the BOOTRST fuse, see Section 24. “Boot
Loader Support – Read-while-write Self-Programming ATmega16/32/64/M1/C1” on page 241.
3.8.1
Interrupt Behavior
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can
write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
The I-bit is automatically set when a return from interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these
interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,
and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt
flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and
remembered until the global interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any
pending interrupt is served.
Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from
an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed
after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can
be used to avoid interrupts during the timed EEPROM write sequence.
16
ATmega16/32/64/M1/C1 [DATASHEET]
7647O–AVR–01/15
Assembly Code Example
in
cli
sbi
sbi
out
r16, SREG
EECR, EEMWE
EECR, EEWE
SREG, r16
; store SREG value
; disable interrupts during timed sequence
; start EEPROM write
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;
/* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1