8-bit AVR Microcontrollers
ATmega48A/88A/168A
DATASHEET COMPLETE
Introduction
®
The Atmel ATmega48A/88A/168A is a low-power CMOS 8-bit
microcontroller based on the AVR® enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega48A/88A/
168A achieves throughputs close to 1MIPS per MHz. This empowers system
designer to optimize the device for power consumption versus processing
speed.
Feature
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
•
Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-chip 2-cycle Multiplier
•
High Endurance Non-volatile Memory Segments
– 4K/8K/16KBytes of In-System Self-Programmable Flash program
Memory
– 256/512/512Bytes EEPROM
– 512/1K/1KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
•
Atmel® QTouch® Library Support
– Capacitive Touch Buttons, Sliders and Wheels
– QTouch and QMatrix® Acquisition
– Up to 64 sense channels
Atmel-42733B-ATmega48A/88A/168A_Datasheet_Complete-11/2016
•
•
•
•
•
•
•
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
• Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
• Temperature Measurement
– Two Master/Slave SPI Serial Interface
– One Programmable Serial USART
– One Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– One On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 - 5.5V
Temperature Range:
– -40°C to 85°C
Speed Grade:
– 0 - 4MHz @ 1.8 - 5.5V
– 0 - 10MHz @ 2.7 - 5.5V
– 0 - 20MHz @ 4.5 - 5.5V
Power Consumption at 1MHz, 1.8V, 25°C
– Active Mode: 0.2mA
– Power-down Mode: 0.1μA
– Power-save Mode: 0.75μA (Including 32kHz RTC)
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Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description.................................................................................................................9
2. Configuration Summary........................................................................................... 10
3. Ordering Information ............................................................................................... 11
3.1.
3.2.
3.3.
ATmega48A................................................................................................................................ 11
ATmega88A ...............................................................................................................................12
ATmega168A .............................................................................................................................13
4. Block Diagram......................................................................................................... 14
5. Pin Configurations................................................................................................... 15
5.1.
5.2.
Pin-out........................................................................................................................................ 15
Pin Descriptions..........................................................................................................................19
6. I/O Multiplexing........................................................................................................ 21
7. Resources................................................................................................................23
8. Data Retention.........................................................................................................24
9. About Code Examples............................................................................................. 25
10. Capacitive Touch Sensing....................................................................................... 26
10.1. QTouch Library........................................................................................................................... 26
11. AVR CPU Core........................................................................................................ 27
11.1.
11.2.
11.3.
11.4.
11.5.
Overview.....................................................................................................................................27
ALU – Arithmetic Logic Unit........................................................................................................28
Status Register...........................................................................................................................28
General Purpose Register File................................................................................................... 30
Stack Pointer.............................................................................................................................. 31
11.6. Instruction Execution Timing...................................................................................................... 33
11.7. Reset and Interrupt Handling..................................................................................................... 34
12. AVR Memories.........................................................................................................36
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
Overview.....................................................................................................................................36
In-System Reprogrammable Flash Program Memory................................................................ 36
SRAM Data Memory...................................................................................................................37
EEPROM Data Memory............................................................................................................. 39
I/O Memory.................................................................................................................................40
Register Description................................................................................................................... 41
13. System Clock and Clock Options............................................................................ 51
13.1. Clock Systems and Their Distribution.........................................................................................51
13.2. Clock Sources............................................................................................................................ 52
13.3. Low Power Crystal Oscillator......................................................................................................54
13.4. Full Swing Crystal Oscillator.......................................................................................................55
13.5. Low Frequency Crystal Oscillator...............................................................................................56
13.6. Calibrated Internal RC Oscillator................................................................................................57
13.7. 128kHz Internal Oscillator.......................................................................................................... 58
13.8. External Clock............................................................................................................................ 59
13.9. Timer/Counter Oscillator.............................................................................................................60
13.10. Clock Output Buffer....................................................................................................................60
13.11. System Clock Prescaler............................................................................................................. 60
13.12. Register Description...................................................................................................................61
14. PM - Power Management and Sleep Modes...........................................................65
14.1. Overview.....................................................................................................................................65
14.2. Sleep Modes...............................................................................................................................65
14.3. Idle Mode....................................................................................................................................65
14.4. ADC Noise Reduction Mode.......................................................................................................66
14.5. Power-Down Mode.....................................................................................................................66
14.6. Power-save Mode.......................................................................................................................67
14.7. Standby Mode............................................................................................................................ 67
14.8. Extended Standby Mode............................................................................................................ 67
14.9. Power Reduction Register..........................................................................................................67
14.10. Minimizing Power Consumption.................................................................................................68
14.11. Register Description................................................................................................................... 69
15. SCRST - System Control and Reset....................................................................... 74
15.1.
15.2.
15.3.
15.4.
15.5.
Resetting the AVR...................................................................................................................... 74
Reset Sources............................................................................................................................74
Power-on Reset..........................................................................................................................75
External Reset............................................................................................................................76
Brown-out Detection...................................................................................................................76
15.6.
15.7.
15.8.
15.9.
Watchdog System Reset............................................................................................................ 77
Internal Voltage Reference.........................................................................................................77
Watchdog Timer......................................................................................................................... 78
Register Description................................................................................................................... 80
16. Interrupts................................................................................................................. 84
16.1.
16.2.
16.3.
16.4.
Interrupt Vectors in ATmega48A.................................................................................................84
Interrupt Vectors in ATmega88A.................................................................................................85
Interrupt Vectors in ATmega168A...............................................................................................88
Register Description................................................................................................................... 91
17. EXINT - External Interrupts..................................................................................... 94
17.1. Pin Change Interrupt Timing.......................................................................................................94
17.2. Register Description................................................................................................................... 95
18. I/O-Ports................................................................................................................ 104
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18.1. Overview...................................................................................................................................104
18.2. Ports as General Digital I/O......................................................................................................105
18.3. Alternate Port Functions...........................................................................................................108
18.4. Register Description................................................................................................................. 120
19. TC0 - 8-bit Timer/Counter0 with PWM...................................................................132
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
19.9.
Features................................................................................................................................... 132
Overview...................................................................................................................................132
Timer/Counter Clock Sources.................................................................................................. 134
Counter Unit............................................................................................................................. 134
Output Compare Unit................................................................................................................135
Compare Match Output Unit.....................................................................................................137
Modes of Operation..................................................................................................................138
Timer/Counter Timing Diagrams...............................................................................................142
Register Description................................................................................................................. 144
20. TC1 - 16-bit Timer/Counter1 with PWM.................................................................156
20.1. Overview...................................................................................................................................156
20.2. Features................................................................................................................................... 156
20.3. Block Diagram.......................................................................................................................... 156
20.4. Definitions.................................................................................................................................157
20.5. Registers.................................................................................................................................. 158
20.6. Accessing 16-bit Registers.......................................................................................................158
20.7. Timer/Counter Clock Sources.................................................................................................. 161
20.8. Counter Unit............................................................................................................................. 161
20.9. Input Capture Unit.................................................................................................................... 162
20.10. Output Compare Units............................................................................................................. 164
20.11. Compare Match Output Unit.....................................................................................................166
20.12. Modes of Operation..................................................................................................................167
20.13. Timer/Counter Timing Diagrams.............................................................................................. 175
20.14. Register Description.................................................................................................................176
21. Timer/Counter 0, 1 Prescalers...............................................................................193
21.1.
21.2.
21.3.
21.4.
Internal Clock Source............................................................................................................... 193
Prescaler Reset........................................................................................................................193
External Clock Source..............................................................................................................193
Register Description................................................................................................................. 194
22. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation................... 196
22.1. Features................................................................................................................................... 196
22.2. Overview...................................................................................................................................196
22.3. Timer/Counter Clock Sources.................................................................................................. 198
22.4. Counter Unit............................................................................................................................. 198
22.5. Output Compare Unit................................................................................................................199
22.6. Compare Match Output Unit.....................................................................................................201
22.7. Modes of Operation..................................................................................................................202
22.8. Timer/Counter Timing Diagrams...............................................................................................206
22.9. Asynchronous Operation of Timer/Counter2............................................................................ 207
22.10. Timer/Counter Prescaler.......................................................................................................... 209
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22.11. Register Description................................................................................................................. 209
23. SPI – Serial Peripheral Interface........................................................................... 222
23.1.
23.2.
23.3.
23.4.
23.5.
Features................................................................................................................................... 222
Overview...................................................................................................................................222
SS Pin Functionality................................................................................................................. 226
Data Modes.............................................................................................................................. 226
Register Description................................................................................................................. 227
24. USART - Universal Synchronous Asynchronous Receiver Transceiver................232
24.1. Features................................................................................................................................... 232
24.2. Overview...................................................................................................................................232
24.3. Block Diagram.......................................................................................................................... 232
24.4. Clock Generation......................................................................................................................233
24.5. Frame Formats.........................................................................................................................236
24.6. USART Initialization..................................................................................................................237
24.7. Data Transmission – The USART Transmitter......................................................................... 238
24.8. Data Reception – The USART Receiver.................................................................................. 240
24.9. Asynchronous Data Reception.................................................................................................244
24.10. Multi-Processor Communication Mode.................................................................................... 246
24.11. Examples of Baud Rate Setting............................................................................................... 247
24.12. Register Description.................................................................................................................250
25. USARTSPI - USART in SPI Mode.........................................................................261
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
25.7.
25.8.
Features................................................................................................................................... 261
Overview...................................................................................................................................261
Clock Generation......................................................................................................................261
SPI Data Modes and Timing.....................................................................................................262
Frame Formats.........................................................................................................................262
Data Transfer............................................................................................................................264
AVR USART MSPIM vs. AVR SPI............................................................................................265
Register Description................................................................................................................. 266
26. TWI - 2-wire Serial Interface..................................................................................267
26.1.
26.2.
26.3.
26.4.
26.5.
26.6.
26.7.
26.8.
26.9.
Features................................................................................................................................... 267
Two-Wire Serial Interface Bus Definition..................................................................................267
Data Transfer and Frame Format.............................................................................................268
Multi-master Bus Systems, Arbitration and Synchronization....................................................271
Overview of the TWI Module.................................................................................................... 273
Using the TWI...........................................................................................................................275
Transmission Modes................................................................................................................ 278
Multi-master Systems and Arbitration.......................................................................................296
Register Description................................................................................................................. 298
27. AC - Analog Comparator....................................................................................... 306
27.1. Overview...................................................................................................................................306
27.2. Analog Comparator Multiplexed Input...................................................................................... 306
27.3. Register Description................................................................................................................. 307
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28. ADC - Analog to Digital Converter.........................................................................312
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
28.9.
Features................................................................................................................................... 312
Overview...................................................................................................................................312
Starting a Conversion...............................................................................................................314
Prescaling and Conversion Timing...........................................................................................315
Changing Channel or Reference Selection.............................................................................. 317
ADC Noise Canceler................................................................................................................ 319
ADC Conversion Result............................................................................................................322
Temperature Measurement...................................................................................................... 323
Register Description................................................................................................................. 323
29. DBG - debugWIRE On-chip Debug System.......................................................... 334
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
Features................................................................................................................................... 334
Overview...................................................................................................................................334
Physical Interface..................................................................................................................... 334
Software Break Points..............................................................................................................335
Limitations of debugWIRE........................................................................................................335
Register Description................................................................................................................. 335
30. Self-Programming the Flash..................................................................................337
30.1. Overview...................................................................................................................................337
30.2. Addressing the Flash During Self-Programming...................................................................... 338
30.3. Register Description................................................................................................................. 343
31. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 346
31.1.
31.2.
31.3.
31.4.
31.5.
31.6.
31.7.
31.8.
Features................................................................................................................................... 346
Overview...................................................................................................................................346
Application and Boot Loader Flash Sections............................................................................346
Read-While-Write and No Read-While-Write Flash Sections...................................................347
Boot Loader Lock Bits.............................................................................................................. 349
Entering the Boot Loader Program...........................................................................................350
Addressing the Flash During Self-Programming...................................................................... 351
Self-Programming the Flash.....................................................................................................352
31.9. Register Description................................................................................................................. 361
32. MEMPROG- Memory Programming......................................................................364
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
32.7.
32.8.
Program And Data Memory Lock Bits...................................................................................... 364
Fuse Bits...................................................................................................................................365
Signature Bytes........................................................................................................................ 368
Calibration Byte........................................................................................................................ 368
Page Size................................................................................................................................. 368
Parallel Programming Parameters, Pin Mapping, and Commands.......................................... 368
Parallel Programming...............................................................................................................370
Serial Downloading...................................................................................................................377
33. Electrical Characteristics....................................................................................... 383
33.1. Absolute Maximum Ratings......................................................................................................383
33.2. Common DC Characteristics....................................................................................................383
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33.3. Speed Grades.......................................................................................................................... 387
33.4.
33.5.
33.6.
33.7.
33.8.
33.9.
Clock Characteristics................................................................................................................387
System and Reset Characteristics........................................................................................... 388
SPI Timing Characteristics....................................................................................................... 390
Two-wire Serial Interface Characteristics................................................................................. 391
ADC Characteristics................................................................................................................. 393
Parallel Programming Characteristics...................................................................................... 394
34. Typical Characteristics (TA = -40°C to 85°C)......................................................... 397
34.1. ATmega48A Typical Characteristics.........................................................................................397
34.2. ATmega88A: Typical Characteristics........................................................................................418
34.3. ATmega168A Typical Characteristics.......................................................................................442
35. Register Summary.................................................................................................465
35.1. Note..........................................................................................................................................467
36. Instruction Set Summary....................................................................................... 469
37. Packaging Information...........................................................................................473
37.1.
37.2.
37.3.
37.4.
37.5.
32-pin 32A................................................................................................................................ 473
32-pin 32M1-A..........................................................................................................................474
32-pin 32CC1........................................................................................................................... 475
28-pin 28M1..............................................................................................................................476
28-pin 28P3.............................................................................................................................. 477
38. Errata.....................................................................................................................478
38.1. Errata ATmega48A................................................................................................................... 478
38.2. Errata ATmega88A................................................................................................................... 478
38.3. Errata ATmega168A................................................................................................................. 479
39. Datasheet Revision History................................................................................... 480
39.1. Rev. B – 11/2016...................................................................................................................... 480
39.2. Rev. A – 06/2016...................................................................................................................... 480
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1.
Description
The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega48A/88A/168A provides the following features: 4K/8K/16Kbytes of In-System Programmable
Flash with Read-While-Write capabilities, 256/512/512bytes EEPROM, 512/1K/1Kbytes SRAM, 23
general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible
Timer/Counters with compare modes and PWM, 1 serial programmable USARTs , 1 byte-oriented 2-wire
Serial Interface (I2C), a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages) , a
programmable Watchdog Timer with internal Oscillator, an SPI serial port, and six software selectable
power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O
modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In
Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby mode, both the
main oscillator and the asynchronous timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality
into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and
includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™)
technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you
to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega48A/88A/168A is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded control
applications.
The ATmega48A/88A/168A is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and
Evaluation kits.
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2.
Configuration Summary
Features
ATmega48A/88A/168A
Pin Count
28/32
Flash (Bytes)
4K/8K/16K
SRAM (Bytes)
512/1K/1K
EEPROM (Bytes)
256/512/512
Interrupt Vector Size (instruction word/vector)
1/1/2
General Purpose I/O Lines
23
SPI
2
TWI (I2C)
1
USART
1
ADC
10-bit 15kSPS
ADC Channels
8
8-bit Timer/Counters
2
16-bit Timer/Counters
1
ATmega88A and ATmega168A support a real Read-While-Write Self-Programming mechanism. There is
a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48A,
there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can
execute from the entire Flash.
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3.
Ordering Information
3.1.
ATmega48A
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
20
1.8 - 5.5
ATmega48A-AU
ATmega48A-AUR(4)
ATmega48A-CCU
ATmega48A-CCUR(4)
ATmega48A-MMH(5)
ATmega48A-MMHR(4)(5)
ATmega48A-MU
ATmega48A-MUR(4)
ATmega48A-PU
32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 85°C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32CC1
32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)
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3.2.
ATmega88A
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
20
1.8 - 5.5
ATmega88A-AU
ATmega88A-AUR(4)
ATmega88A-CCU
ATmega88A-CCUR(4)
ATmega88A-MMH(5)
ATmega88A-MMHR(4)(5)
ATmega88A-MU
ATmega88A-MUR(4)
ATmega88A-PU
32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 85°C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32CC1
32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)
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3.3.
ATmega168A
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
20
1.8 - 5.5
ATmega168A-AU
ATmega168A-AUR(5)
ATmega168A-CCU
ATmega168A-CCUR(5)
ATmega168A-MMH(4)
ATmega168A-MMHR(4)(5)
ATmega168A-MU
ATmega168A-MUR(5)
ATmega168A-PU
32A
32A
32CC1
32CC1
28M1
28M1
32M1-A
32M1-A
28P3
Industrial
(-40°C to 85°C)
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Please refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
5. NiPdAu Lead Finish.
Package Type
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/
MLF)
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
32CC1
32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)
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4.
Block Diagram
Figure 4-1. Block Diagram
SRAM
debugWire
CPU
OCD
Clock generation
XTAL1 /
TOSC1
XTAL2 /
TOSC2
32.768kHz
XOSC
8MHz
Calib RC
External
clock
16MHz LP
XOSC
VCC
128kHz int
osc
Power
Supervision
POR/BOD &
RESET
RESET
GND
ADC6,ADC7,PC[5:0]
AREF
ADC[7:0]
AREF
PD[7:0], PC[6:0], PB[7:0]
PD3, PD2
PCINT[23:0]
INT[1:0]
PB1, PB2
PD5
PB0
OC1A/B
T1
ICP1
PB3
PD3
OC2A
OC2B
NVM
programming
Power
management
and clock
control
Watchdog
Timer
ADC
EXTINT
FLASH
D
A
T
A
B
U
S
I/O
PORTS
I
N
/
O
U
T
EEPROM
EEPROMIF
PB[7:0]
PC[6:0]
PD[7:0]
GPIOR[2:0]
TC 0
D
A
T
A
B
U
S
(8-bit)
SPI 0
AC
Internal
Reference
USART 0
RxD0
TxD0
XCK0
PD0
PD1
PD4
TWI 0
SDA0
SCL0
PC4
PC5
T0
OC0A
OC0B
PD4
PD6
PD5
MISO0
MOSI0
SCK0
SS0
PB4
PB3
PB5
PB2
AIN0
AIN1
PD6
PD7
ADCMUX
ADC6, ADC7
PC[5:0]
TC 1
(16-bit)
TC 2
(8-bit async)
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5.
Pin Configurations
5.1.
Pin-out
Figure 5-1. 28-pin PDIP
(PCINT14/RESET) PC6
1
28
PC5 (ADC5/SCL/PCINT13)
(PCINT16/RXD) PD0
2
27
PC4 (ADC4/SDA/PCINT12)
(PCINT17/TXD) PD1
3
26
PC3 (ADC3/PCINT11)
(PCINT18/INT0) PD2
4
25
PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3
5
24
PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4
6
23
PC0 (ADC0/PCINT8)
VCC
7
22
GND
GND
8
21
AREF
(PCINT6/XTAL1/TOSC1) PB6
9
20
AVCC
(PCINT7/XTAL2/TOSC2) PB7
10
19
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
11
18
PB4 (MISO/PCINT4)
(PCINT22/OC0A/AIN0) PD6
12
17
PB3 (MOSI/OC2A/PCINT3)
(PCINT23/AIN1) PD7
13
16
PB2 (SS/OC1B/PCINT2)
(PCINT0/CLKO/ICP1) PB0
14
15
PB1 (OC1A/PCINT1)
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
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PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
28
27
26
25
24
23
22
Figure 5-2. 28-pin MLF Top View
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
GND
4
18
GND
(PCINT6/XTAL1/TOSC1) PB6
5
17
AREF
(PCINT7/XTAL2/TOSC2) PB7
6
16
AVCC
(PCINT21/OC0B/T1) PD5
7
15
PB5 (SCK/PCINT5)
(PCINT4/MISO) PB4
(PCINT3/OC2A/MOSI) PB3
Bottom pad should be
soldered to ground
14
PC0 (ADC0/PCINT8)
13
19
(PCINT2/SS/OC1B) PB2
3
12
VCC
(PCINT1/OC1A) PB1
PC1 (ADC1/PCINT9)
11
20
10
2
(PCINT0/CLKO/ICP1) PB0
(PCINT20/XCK/T0) PD4
9
PC2 (ADC2/PCINT10)
(PCINT23/AIN1) PD7
21
8
1
(PCINT22/OC0A/AIN0) PD6
(PCINT19/OC2B/INT1) PD3
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PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
29
28
27
Digital
Analog
Crystal/CLK
PC2 (ADC2/PCINT10)
PD0 (RXD/PCINT16)
30
Programming/debug
25
PD1 (TXD/PCINT17)
31
Ground
26
PD2 (INT0/PCINT18)
32
Power
PC3 (ADC3/PCINT11)
Figure 5-3. 32-pin TQFP Top View
GND
5
20
AREF
VCC
6
19
ADC6
(PCINT6/XTAL1/TOSC1) PB6
7
18
AVCC
(PCINT7/XTAL2/TOSC2) PB7
8
17
PB5 (SCK/PCINT5)
16
GND
(PCINT4/MISO) PB4
21
15
4
(PCINT3/OC2A/MOSI) PB3
VCC
14
ADC7
(PCINT2/SS/OC1B) PB2
22
13
3
(PCINT1/OC1A) PB1
GND
12
PC0 (ADC0/PCINT8)
(PCINT0/CLKO/ICP1) PB0
23
11
2
(PCINT23/AIN1) PD7
(PCINT20/XCK/T0) PD4
10
PC1 (ADC1/PCINT9)
(PCINT22/OC0A/AIN0) PD6
24
9
1
(PCINT21/OC0B/T1) PD5
(PCINT19/OC2B/INT1) PD3
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PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
32
31
30
29
28
27
26
25
Figure 5-4. 32-pin MLF Top View
Power
Ground
Programming/debug
Digital
Analog
Crystal/CLK
GND
5
20
AREF
VCC
6
19
ADC6
(PCINT6/XTAL1/TOSC1) PB6
7
18
AVCC
(PCINT7/XTAL2/TOSC2) PB7
8
17
PB5 (SCK/PCINT5)
16
GND
(PCINT4/MISO) PB4
21
15
4
(PCINT3/OC2A/MOSI) PB3
VCC
14
ADC7
(PCINT2/SS/OC1B) PB2
22
13
3
(PCINT1/OC1A) PB1
GND
12
PC0 (ADC0/PCINT8)
(PCINT0/CLKO/ICP1) PB0
23
11
2
(PCINT23/AIN1) PD7
(PCINT20/XCK/T0) PD4
10
PC1 (ADC1/PCINT9)
(PCINT22/OC0A/AIN0) PD6
24
9
1
(PCINT21/OC0B/T1) PD5
(PCINT19/OC2B/INT1) PD3
Bottom pad should be
soldered to ground
Table 5-1. 32UFBGA
1
2
3
4
5
6
A
PD2
PD1
PC6
PC4
PC2
PC1
B
PD3
PD4
PD0
PC5
PC3
PC0
C
GND
GND
-
-
ADC7
GND
D
VCC
VCC
-
-
AREF
ADC6
E
PB6
PD6
PB0
PB2
AVCC
PB5
F
PB7
PD5
PD7
PB1
PB3
PB4
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5.2.
Pin Descriptions
5.2.1.
VCC
Digital supply voltage.
5.2.2.
GND
Ground.
5.2.3.
Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] input
for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
5.2.4.
Port C (PC[5:0])
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC[5:0]
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
5.2.5.
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics
of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are
not guaranteed to generate a Reset.
The various special features of Port C are elaborated in the Alternate Functions of Port C section.
5.2.6.
Port D (PD[7:0])
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
5.2.7.
AVCC
AVCC is the supply voltage pin for the A/D Converter, PC[3:0], and PE[3:2]. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that PC[6:4] use digital supply voltage, VCC.
5.2.8.
AREF
AREF is the analog reference pin for the A/D Converter.
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5.2.9.
ADC[7:6] (TQFP and VFQFN Package Only)
In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are
powered from the analog supply and serve as 10-bit ADC channels.
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6.
I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
(32-pin
32UFBGA)
Pin#
(32-pin
MLF/
TQFP)
Pin#
(28-pin
MLF)
Pin#
(28-pin
PIPD)
Pin#
PAD
EXTINT PCINT
B1
1
1
5
PD[3]
INT1
B2
2
2
6
PD[4]
D1
4
3
7
VCC
C1
3
4
8
GND
D2
6
-
-
VCC
C2
5
-
-
GND
E1
7
5
9
PB[6]
PCINT6
XTAL1/
TOSC1
F1
8
6
10
PB[7]
PCINT7
XTAL2/
TOSC2
F2
9
7
11
PD[5]
PCINT21
OC0B
E2
10
8
12
PD[6]
PCINT22 AIN0
OC0A
F3
11
9
13
PD[7]
PCINT23 AIN1
E3
12
10
14
PB[0]
PCINT0
F4
13
11
15
PB[1]
PCINT1
OC1A
E4
14
12
16
PB[2]
PCINT2
OC1B
SS0
F5
15
13
17
PB[3]
PCINT3
OC2A
MOSI0
F6
16
14
18
PB[4]
PCINT4
MISO0
E6
17
15
19
PB[5]
PCINT5
SCK0
E5
18
16
20
AVCC
D6
19
-
-
ADC6
D5
20
17
21
AREF
C6
21
18
22
GND
C5
22
-
-
ADC7
B6
23
19
13
PC[0]
PCINT8
ADC0
A6
24
20
24
PC[1]
PCINT9
ADC1
A2
25
21
25
PC[2]
PCINT10 ADC2
B5
26
22
26
PC[3]
PCINT11 ADC3
A4
27
23
27
PC[4]
PCINT12 ADC4
SDA0
B4
28
24
28
PC[5]
PCINT13 ADC5
SCL0
ADC/A
C
OSC
T/C #0 T/C USART
#1 0
PCINT19
OC2B
PCINT20
T0
CLKO
I2C 0
SPI 0
XCK0
T1
ICP1
ADC6
ADC7
Atmel ATmega48A/88A/168A [DATASHEET]
Atmel-42733B-ATmega48A/88A/168A_Datasheet_Complete-11/2016
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(32-pin
32UFBGA)
Pin#
(32-pin
MLF/
TQFP)
Pin#
(28-pin
MLF)
Pin#
(28-pin
PIPD)
Pin#
PAD
EXTINT PCINT
A3
29
25
1
PC[6]/
RESET
PCINT14
B3
30
26
2
PD[0]
PCINT16
RXD0
A2
31
27
3
PD[1]
PCINT17
TXD0
A1
32
28
4
PD[2]
INT0
ADC/A
C
OSC
T/C #0 T/C USART
#1 0
I2C 0
SPI 0
PCINT18
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7.
Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.atmel.com/avr.
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8.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
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9.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
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10.
10.1.
Capacitive Touch Sensing
QTouch Library
®
®
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on
®
most Atmel AVR microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel
®
QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location: http://
www.atmel.com/technologies/touch/. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.
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11.
AVR CPU Core
11.1.
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 11-1. Block Diagram of the AVR Architecture
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R18
R16
R14
R12
R10
R8
R6
R4
R2
R0
Program
counter
Flash program
memory
Instruction
register
Instruction
decode
Data memory
Stack
pointer
Status
register
ALU
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
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The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application
Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt
Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from
0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
11.2.
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or between
a register and an immediate are executed. The ALU operations are divided into three main categories –
arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful
multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction Set
Summary section for a detailed description.
Related Links
Instruction Set Summary on page 469
11.3.
Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set
Reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
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11.3.1.
Status Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: SREG
Offset: 0x5F
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x3F
Bit
Access
Reset
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable Register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T: Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in
BCD arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S: Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the Instruction Set Description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
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Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
11.4.
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
•
•
•
•
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 11-2. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
Ge ne ra l
R14
0x0E
P urpos e
R15
0x0F
Working
R16
0x10
Re gis te rs
R17
0x11
…
R26
0x1A
X-re gis te r Low Byte
R27
0x1B
X-re gis te r High Byte
R28
0x1C
Y-re gis te r Low Byte
R29
0x1D
Y-re gis te r High Byte
R30
0x1E
Z-re gis te r Low Byte
R31
0x1F
Z-re gis te r High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions. As shown in the figure, each register is also assigned a data memory
address, mapping them directly into the first 32 locations of the user Data Space. Although not being
physically implemented as SRAM locations, this memory organization provides great flexibility in access
of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
11.4.1.
The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
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Figure 11-3. The X-, Y-, and Z-registers
15
X-register
XH
7
0
15
Y-register
7
R26
YH
YL
0
7
R28
ZH
ZL
0
7
R31
0
0
R29
7
0
0
R27
7
15
Z-register
XL
0
0
R30
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary on page 469
11.5.
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to
lower memory locations. The Stack Pointer Register always points to the top of the Stack.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack
Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point
above start of the SRAM. See the table for Stack Pointer details.
Table 11-1. Stack Pointer Instructions
Instruction Stack pointer
Description
PUSH
Decremented by 1 Data is pushed onto the stack
CALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
ICALL
RCALL
POP
Incremented by 1
Data is popped from the stack
RET
Incremented by 2
Return address is popped from the stack with return from subroutine or
return from interrupt
RETI
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
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11.5.1.
Stack Pointer Register High byte
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Name: SPH
Offset: 0x5E
Reset: RAMEND
Property: When addressing I/O Registers as data space the offset address is 0x3E
Bit
7
6
5
4
3
2
1
0
(SP[10:8]) SPH
Access
Reset
RW
RW
RW
0
0
0
Bits 2:0 – (SP[10:8]) SPH: Stack Pointer Register
SPH and SPL are combined into SP. It means SPH[2:0] is SP[10:8].
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11.5.2.
Stack Pointer Register Low byte
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Name: SPL
Offset: 0x5D
Reset: 0x11111111
Property: When addressing I/O Registers as data space the offset address is 0x3D
Bit
7
6
5
4
3
2
1
0
(SP[7:0]) SPL
Access
Reset
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
1
Bits 7:0 – (SP[7:0]) SPL: Stack Pointer Register
SPH and SPL are combined into SP. It means SPL[7:0] is SP[7:0].
11.6.
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal
clock division is used. The Figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 11-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following Figure shows the internal timing concept for the Register File. In a single clock cycle an
ALU operation using two register operands is executed, and the result is stored back to the destination
register.
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Figure 11-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
11.7.
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector
each have a separate program vector in the program memory space. All interrupts are assigned individual
enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status
Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be
automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves
software security.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt
Vectors. They have determined priority levels: The lower the address the higher is the priority level.
RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors
can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register
(MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programming
the BOOTRST Fuse.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts:
The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program
Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and
hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic
one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled,
or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main
program and execute one more instruction before any pending interrupt is served.
The Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
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The following example shows how this can be used to avoid interrupts during the timed EEPROM write
sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
