ATmega48P/V/88P/V/168P/V
megaAVR® Data Sheet
Introduction
The ATmega48P/V/88P/V/168P/V is a low power, CMOS 8-bit microcontrollers based on the AVR®
enhanced RISC architecture. By executing instructions in a single clock cycle, the devices achieve CPU
throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
– 4/8/16KBytes of In-System Self-Programmable Flash program memory
– 256/512/512Bytes EEPROM
– 512/1K/1KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
• QTouch® Library Support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix™ acquisition
– Up to 64 sense channels
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
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ATmega48P/V/88P/V/168P/V
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
• Operating Voltage:
– 1.8 - 5.5V for ATmega48PV/88PV/168PV
– 2.7 - 5.5V for ATmega48P/88P/168P
• Temperature Range:
– -40°C to 85°C
• Speed Grade:
– ATmega48PV/88PV/168PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V
– ATmega48P/88P/168P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V
• Low Power Consumption at 1MHz, 1.8V, 25°C:
– Active Mode: 0.3mA
– Power-down Mode: 0.1µA
– Power-save Mode: 0.8µA (Including 32kHz RTC)
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DS40002065A-page 2
ATmega48P/V/88P/V/168P/V
Table of Contents
1
Pin Configurations ................................................................................. 10
1.1
2
Pin Descriptions............................................................................................... 11
Overview ................................................................................................. 12
2.1
Block Diagram ................................................................................................. 13
2.2
Comparison Between ATmega48P, ATmega88P and ATmega168P ............. 15
3
Resources ............................................................................................... 16
4
Data Retention ........................................................................................ 16
5
About Code Examples ........................................................................... 16
6
Capacitive touch sensing ...................................................................... 16
7
AVR CPU Core ........................................................................................ 17
8
9
7.1
Overview.......................................................................................................... 17
7.2
ALU – Arithmetic Logic Unit............................................................................. 18
7.3
Status Register ................................................................................................ 18
7.4
General Purpose Register File ........................................................................ 20
7.5
Stack Pointer ................................................................................................... 21
7.6
Instruction Execution Timing ........................................................................... 22
7.7
Reset and Interrupt Handling........................................................................... 23
AVR Memories ........................................................................................ 25
8.1
Overview.......................................................................................................... 25
8.2
In-System Reprogrammable Flash Program Memory ..................................... 25
8.3
SRAM Data Memory........................................................................................ 27
8.4
EEPROM Data Memory .................................................................................. 28
8.5
I/O Memory...................................................................................................... 29
8.6
Register Description ........................................................................................ 30
System Clock and Clock Options ......................................................... 35
9.1
Clock Systems and their Distribution ............................................................... 35
9.2
Clock Sources ................................................................................................. 36
9.3
Low Power Crystal Oscillator........................................................................... 37
9.4
Full Swing Crystal Oscillator ............................................................................ 39
9.5
Low Frequency Crystal Oscillator .................................................................... 41
9.6
Calibrated Internal RC Oscillator ..................................................................... 42
9.7
128 kHz Internal Oscillator .............................................................................. 43
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ATmega48P/V/88P/V/168P/V
9.8
External Clock ................................................................................................. 43
9.9
Clock Output Buffer ......................................................................................... 44
9.10
Timer/Counter Oscillator.................................................................................. 44
9.11
System Clock Prescaler .................................................................................. 44
9.12
Register Description ........................................................................................ 46
10 Power Management and Sleep Modes ................................................. 48
10.1
Sleep Modes.................................................................................................... 48
10.2
BOD Disable.................................................................................................... 49
10.3
Idle Mode......................................................................................................... 49
10.4
ADC Noise Reduction Mode............................................................................ 49
10.5
Power-down Mode........................................................................................... 50
10.6
Power-save Mode............................................................................................ 50
10.7
Standby Mode ................................................................................................. 50
10.8
Extended Standby Mode ................................................................................. 50
10.9
Power Reduction Register ............................................................................... 51
10.10
Minimizing Power Consumption ...................................................................... 51
10.11
Register Description ........................................................................................ 53
11 System Control and Reset .................................................................... 55
11.1
Resetting the AVR ........................................................................................... 55
11.2
Reset Sources ................................................................................................. 55
11.3
Power-on Reset............................................................................................... 56
11.4
External Reset ................................................................................................. 57
11.5
Brown-out Detection ........................................................................................ 57
11.6
Watchdog System Reset ................................................................................. 58
11.7
Internal Voltage Reference.............................................................................. 58
11.8
Watchdog Timer .............................................................................................. 59
11.9
Register Description ........................................................................................ 63
12 Interrupts ................................................................................................ 66
12.1
Interrupt Vectors in ATmega48P ..................................................................... 66
12.2
Interrupt Vectors in ATmega88P ..................................................................... 68
12.3
Interrupt Vectors in ATmega168P ................................................................... 72
12.4
Register Description ........................................................................................ 77
13 External Interrupts ................................................................................. 79
13.1
Pin Change Interrupt Timing............................................................................ 79
13.2
Register Description ........................................................................................ 80
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ATmega48P/V/88P/V/168P/V
14 I/O-Ports .................................................................................................. 85
14.1
Overview.......................................................................................................... 85
14.2
Ports as General Digital I/O ............................................................................. 86
14.3
Alternate Port Functions .................................................................................. 90
14.4
Register Description ...................................................................................... 102
15 8-bit Timer/Counter0 with PWM .......................................................... 104
15.1
Features ........................................................................................................ 104
15.2
Overview........................................................................................................ 104
15.3
Timer/Counter Clock Sources ....................................................................... 106
15.4
Counter Unit .................................................................................................. 106
15.5
Output Compare Unit..................................................................................... 107
15.6
Compare Match Output Unit .......................................................................... 108
15.7
Modes of Operation ....................................................................................... 109
15.8
Timer/Counter Timing Diagrams ................................................................... 114
15.9
Register Description ...................................................................................... 116
16 16-bit Timer/Counter1 with PWM ........................................................ 123
16.1
Features ........................................................................................................ 123
16.2
Overview........................................................................................................ 123
16.3
Accessing 16-bit Registers ............................................................................ 125
16.4
Timer/Counter Clock Sources ....................................................................... 128
16.5
Counter Unit .................................................................................................. 129
16.6
Input Capture Unit ......................................................................................... 130
16.7
Output Compare Units................................................................................... 132
16.8
Compare Match Output Unit .......................................................................... 133
16.9
Modes of Operation ....................................................................................... 135
16.10
Timer/Counter Timing Diagrams ................................................................... 142
16.11
Register Description ...................................................................................... 144
17 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 152
17.1
Internal Clock Source .................................................................................... 152
17.2
Prescaler Reset ............................................................................................. 152
17.3
External Clock Source ................................................................................... 152
17.4
Register Description ...................................................................................... 154
18 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 155
18.1
Features ........................................................................................................ 155
18.2
Overview........................................................................................................ 155
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ATmega48P/V/88P/V/168P/V
18.3
Timer/Counter Clock Sources ....................................................................... 156
18.4
Counter Unit .................................................................................................. 156
18.5
Output Compare Unit..................................................................................... 157
18.6
Compare Match Output Unit .......................................................................... 159
18.7
Modes of Operation ....................................................................................... 160
18.8
Timer/Counter Timing Diagrams ................................................................... 164
18.9
Asynchronous Operation of Timer/Counter2 ................................................. 166
18.10
Timer/Counter Prescaler ............................................................................... 167
18.11
Register Description ...................................................................................... 169
19 SPI – Serial Peripheral Interface ......................................................... 177
19.1
Features ........................................................................................................ 177
19.2
Overview........................................................................................................ 177
19.3
SS Pin Functionality ...................................................................................... 182
19.4
Data Modes ................................................................................................... 182
19.5
Register Description ...................................................................................... 184
20 USART0 ................................................................................................. 187
20.1
Features ........................................................................................................ 187
20.2
Overview........................................................................................................ 187
20.3
Clock Generation ........................................................................................... 188
20.4
Frame Formats .............................................................................................. 191
20.5
USART Initialization....................................................................................... 192
20.6
Data Transmission – The USART Transmitter .............................................. 194
20.7
Data Reception – The USART Receiver ....................................................... 196
20.8
Asynchronous Data Reception ...................................................................... 200
20.9
Multi-processor Communication Mode .......................................................... 203
20.10
Register Description ...................................................................................... 205
20.11
Examples of Baud Rate Setting..................................................................... 209
21 USART in SPI Mode ............................................................................. 214
21.1
Features ........................................................................................................ 214
21.2
Overview........................................................................................................ 214
21.3
Clock Generation ........................................................................................... 214
21.4
SPI Data Modes and Timing.......................................................................... 215
21.5
Frame Formats .............................................................................................. 216
21.6
Data Transfer................................................................................................. 218
21.7
AVR USART MSPIM vs. AVR SPI ................................................................ 220
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ATmega48P/V/88P/V/168P/V
21.8
Register Description ...................................................................................... 221
22 2-wire Serial Interface .......................................................................... 224
22.1
Features ........................................................................................................ 224
22.2
2-wire Serial Interface Bus Definition ............................................................ 224
22.3
Data Transfer and Frame Format .................................................................. 226
22.4
Multi-master Bus Systems, Arbitration and Synchronization ......................... 228
22.5
Overview of the TWI Module ......................................................................... 231
22.6
Using the TWI................................................................................................ 233
22.7
Transmission Modes ..................................................................................... 237
22.8
Multi-master Systems and Arbitration............................................................ 251
22.9
Register Description ...................................................................................... 252
23 Analog Comparator .............................................................................. 258
23.1
Overview........................................................................................................ 258
23.2
Analog Comparator Multiplexed Input ........................................................... 258
23.3
Register Description ...................................................................................... 259
24 Analog-to-Digital Converter ................................................................ 262
24.1
Features ........................................................................................................ 262
24.2
Overview........................................................................................................ 262
24.3
Starting a Conversion .................................................................................... 264
24.4
Prescaling and Conversion Timing ................................................................ 265
24.5
Changing Channel or Reference Selection ................................................... 267
24.6
ADC Noise Canceler ..................................................................................... 268
24.7
ADC Conversion Result................................................................................. 273
24.8
Temperature Measurement ........................................................................... 273
24.9
Register Description ...................................................................................... 274
25 debugWIRE On-chip Debug System .................................................. 279
25.1
Features ........................................................................................................ 279
25.2
Overview........................................................................................................ 279
25.3
Physical Interface .......................................................................................... 279
25.4
Software Break Points ................................................................................... 280
25.5
Limitations of debugWIRE ............................................................................. 280
25.6
Register Description ...................................................................................... 280
26 Self-Programming the Flash, ATmega48P ......................................... 281
26.1
Overview........................................................................................................ 281
26.2
Addressing the Flash During Self-Programming ........................................... 282
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26.3
Register Description ...................................................................................... 288
27 Boot Loader Support – Read-While-Write Self-Programming, ATmega88P and ATmega168P
290
27.1
Features ........................................................................................................ 290
27.2
Overview........................................................................................................ 290
27.3
Application and Boot Loader Flash Sections ................................................. 290
27.4
Read-While-Write and No Read-While-Write Flash Sections........................ 291
27.5
Boot Loader Lock Bits ................................................................................... 293
27.6
Entering the Boot Loader Program ................................................................ 294
27.7
Addressing the Flash During Self-Programming ........................................... 295
27.8
Self-Programming the Flash .......................................................................... 295
27.9
Register Description ...................................................................................... 304
28 Memory Programming ......................................................................... 306
28.1
Program And Data Memory Lock Bits ........................................................... 306
28.2
Fuse Bits........................................................................................................ 307
28.3
Signature Bytes ............................................................................................. 309
28.4
Calibration Byte ............................................................................................. 309
28.5
Page Size ...................................................................................................... 310
28.6
Parallel Programming Parameters, Pin Mapping, and Commands ............... 310
28.7
Parallel Programming .................................................................................... 312
28.8
Serial Downloading........................................................................................ 319
29 Electrical Characteristics .................................................................... 324
29.1
Absolute Maximum Ratings* ......................................................................... 324
29.2
DC Characteristics......................................................................................... 324
29.3
Speed Grades ............................................................................................... 327
29.4
Clock Characteristics..................................................................................... 329
29.5
System and Reset Characteristics ................................................................ 330
29.6
SPI Timing Characteristics ............................................................................ 331
29.7
2-wire Serial Interface Characteristics ........................................................... 333
29.8
ADC Characteristics – Preliminary Data........................................................ 335
29.9
Parallel Programming Characteristics ........................................................... 336
30 Typical Characteristics ........................................................................ 338
30.1
ATmega48P Typical Characteristics ............................................................. 338
30.2
ATmega88P Typical Characteristics ............................................................. 362
30.3
ATmega168P Typical Characteristics ........................................................... 386
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ATmega48P/V/88P/V/168P/V
31 Register Summary ............................................................................... 411
32 Instruction Set Summary ..................................................................... 415
33 Ordering Information ........................................................................... 418
33.1
ATmega48P................................................................................................... 418
33.2
ATmega88P................................................................................................... 419
33.3
ATmega168P................................................................................................. 420
34 Packaging Information ........................................................................ 421
34.1
32A ................................................................................................................ 421
34.2
28M1.............................................................................................................. 422
34.3
32M1-A .......................................................................................................... 423
34.4
28P3 .............................................................................................................. 424
35 Errata ..................................................................................................... 425
35.1
Errata ATmega48P........................................................................................ 425
35.2
Errata ATmega88P........................................................................................ 426
35.3
Errata ATmega168P...................................................................................... 428
36 Datasheet Revision History ................................................................. 430
36.1
Rev. A-11/2018.............................................................................................. 430
36.2
Rev. 8025M-06/11 ......................................................................................... 430
36.3
Rev. 8025L-07/10 .......................................................................................... 430
36.4
Rev. 8025K-10/09.......................................................................................... 430
36.5
Rev. 8025J-05/09 .......................................................................................... 430
36.6
Rev. 8025I-02/09 ........................................................................................... 430
36.7
Rev. 8025H-02/09 ......................................................................................... 431
36.8
Rev. 8025G-01/09 ......................................................................................... 431
36.9
Rev. 8025F-08/08.......................................................................................... 431
36.10
Rev. 8025E-08/08.......................................................................................... 431
36.11
Rev. 8025D-03/08 ......................................................................................... 432
36.12
Rev. 8025C-01/08 ......................................................................................... 432
36.13
Rev. 8025B-01/08.......................................................................................... 432
36.14
Rev. 8025A-07/07.......................................................................................... 433
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DS40002065A-page 9
ATmega48P/V/88P/V/168P/V
Pin Configurations
Figure 1-1.
Pinout ATmega48P/88P/168P
PDIP
32
31
30
29
28
27
26
25
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
TQFP Top View
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
9
10
11
12
13
14
15
16
(PCINT14/RESET) PC6
(PCINT16/RXD) PD0
(PCINT17/TXD) PD1
(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
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PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK/PCINT5)
9
10
11
12
13
14
15
16
8
9
10
11
12
13
14
NOTE: Bottom pad should be soldered to ground.
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
AREF
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/OC2A/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
32
31
30
29
28
27
26
25
PD2 (INT0/PCINT18)
PD1 (TXD/PCINT17)
PD0 (RXD/PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
32 MLF Top View
28 MLF Top View
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
VCC
GND
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NOTE: Bottom pad should be soldered to ground.
Data Sheet Complete
(PCINT21/OC0B/T1) PD5
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
(PCINT19/OC2B/INT1) PD3
(PCINT20/XCK/T0) PD4
GND
VCC
GND
VCC
(PCINT6/XTAL1/TOSC1) PB6
(PCINT7/XTAL2/TOSC2) PB7
(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/OC2A/MOSI) PB3
(PCINT4/MISO) PB4
1.
DS40002065A-page 10
ATmega48P/V/88P/V/168P/V
1.1
Pin Descriptions
1.1.1
VCC
Digital supply voltage.
1.1.2
GND
Ground.
1.1.3
Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting
Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
92 and “System Clock and Clock Options” on page 35.
1.1.4
Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC5:0 output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
1.1.5
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical
characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 29-3 on page 330. Shorter pulses are not ensured to
generate a Reset.
The various special features of Port C are elaborated in “Alternate Functions of Port C” on page
95.
1.1.6
Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
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DS40002065A-page 11
ATmega48P/V/88P/V/168P/V
The various special features of Port D are elaborated in “Alternate Functions of Port D” on page
98.
1.1.7
AVCC
AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter. Note that PC6:4 use digital supply voltage, VCC.
1.1.8
AREF
AREF is the analog reference pin for the A/D Converter.
1.1.9
ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.
2.
Overview
The ATmega48P/88P/168P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48P/88P/168P achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
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Block Diagram
Block Diagram
GND
Figure 2-1.
VCC
2.1
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
debugWIRE
Flash
SRAM
PROGRAM
LOGIC
CPU
EEPROM
AVCC
AREF
DATABUS
GND
8bit T/C 0
16bit T/C 1
A/D Conv.
8bit T/C 2
Analog
Comp.
Internal
Bandgap
USART 0
SPI
TWI
PORT D (8)
PORT B (8)
PORT C (7)
2
6
RESET
XTAL[1..2]
PD[0..7]
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PC[0..6]
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
The ATmega48P/88P/168P provides the following features: 4K/8K/16Kbytes of In-System
Programmable Flash with Read-While-Write capabilities, 256/512/512bytes EEPROM,
512/1K/1Kbytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers,
three flexible Timer/Counters with compare modes, internal and external interrupts, a serial
programmable USART, a byte-oriented, 2-wire Serial Interface, an SPI serial port, a 6-channel
10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer
with internal Oscillator, and five software selectable power saving modes. The Idle mode stops
the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port,
and interrupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware
reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to
maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode
stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching
noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression™ (AKS™) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Microchip’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot
program running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the ATmega48P/88P/168P is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega48P/88P/168P AVR is supported with a full suite of program and system
development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,
In-Circuit Emulators, and Evaluation kits.
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DS40002065A-page 14
ATmega48P/V/88P/V/168P/V
2.2
Comparison Between ATmega48P, ATmega88P and ATmega168P
The ATmega48P, ATmega88P and ATmega168P differ only in memory sizes, boot loader
support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt
vector sizes for the three devices.
Table 2-1.
Memory Size Summary
Device
Flash
EEPROM
RAM
Interrupt Vector Size
ATmega48P
4KBytes
256Bytes
512Bytes
1 instruction word/vector
ATmega88P
8KBytes
512Bytes
1KBytes
1 instruction word/vector
ATmega168P
16KBytes
512Bytes
1KBytes
2 instruction words/vector
ATmega88P and ATmega168P support a real Read-While-Write Self-Programming mechanism.
There is a separate Boot Loader Section, and the SPM instruction can only execute from there.
In ATmega48P, there is no Read-While-Write support and no separate Boot Loader Section.
The SPM instruction can execute from the entire Flash.
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DS40002065A-page 15
ATmega48P/V/88P/V/168P/V
3.
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.microchip.com
Note:
4.
1.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
5.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation
for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
6.
Capacitive touch sensing
The QTouch Library provides a simple to use solution to realize touch sensitive interfaces on
most AVR® microcontrollers. The QTouch Library includes support for the QTouch and
QMatrix™ acquisition methods.
Touch sensing can be added to any application by linking the appropriate QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and
sensors, and then calling the touch sensing API’s to retrieve the channel information and
determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Microchip website at the following
location http://www.microchip.com. For implementation details and other information, refer to the
QTouch Library User Guide - also available for download from the Microchip website.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002065A-page 16
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7.
AVR CPU Core
7.1
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 7-1.
Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is In-System Reprogrammable Flash
memory.
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a
typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic
operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word
format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the
Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega48P/88P/168P has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
7.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
7.3
Status Register
The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to perform
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conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
7.3.1
SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
0x3F (0x5F)
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers. If the Global Interrupt
Enable Register is cleared, none of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is
set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared
by the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or
destination for the operated bit. A bit from a register in the Register File can be copied into T by
the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
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• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
7.4
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
•
One 8-bit output operand and one 8-bit result input
•
Two 8-bit output operands and one 8-bit result input
•
Two 8-bit output operands and one 16-bit result input
•
One 16-bit output operand and one 16-bit result input
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7-2.
AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 7-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically
implemented as SRAM locations, this memory organization provides great flexibility in access of
the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
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7.4.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These
registers are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 7-3.
Figure 7-3.
The X-, Y-, and Z-registers
15
X-register
XH
7
XL
0
R27 (0x1B)
15
Y-register
0
R26 (0x1A)
YH
7
YL
0
R29 (0x1D)
Z-register
0
7
0
7
0
R28 (0x1C)
15
ZH
7
0
R31 (0x1F)
ZL
7
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
7.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. Note that the Stack is implemented as
growing from higher to lower memory locations. The Stack Pointer Register always points to the
top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine
and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are
executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the
internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure
8-3 on page 27.
See Table 7-1 for Stack Pointer details.
Table 7-1.
Stack Pointer instructions
Instruction
Stack pointer
Description
PUSH
Decremented by 1
Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2
Return address is pushed onto the stack with a subroutine call or
interrupt
POP
Incremented by 1
Data is popped from the stack
RET
RETI
Incremented by 2
Return address is popped from the stack with return from
subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this case, the
SPH Register will not be present.
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7.5.1
SPH and SPL – Stack Pointer High and Stack Pointer Low Register
Bit
15
14
13
12
11
10
9
8
0x3E (0x5E)
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
0x3D (0x5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
Read/Write
Initial Value
7.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
Figure 7-4.
The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the
destination register.
Figure 7-5.
Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
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7.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory
Programming” on page 306 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 66. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 66 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming,
ATmega88P and ATmega168P” on page 290.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are
disabled. The user software can write logic one to the I-bit to enable nested interrupts. All
enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set
when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt
Vector in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
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Assembly Code Example
in
r16, SREG
; store SREG
value
cli
; disable interrupts during timed
sequence
sbi
EECR, EEMPE
; start
EEPROM write
sbi
EECR, EEPE
out
SREG, r16
; restore
SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;
SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
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