AVR 8-Bit Microcontroller
ATmega8A Data Sheet
Introduction
®
The ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega8A achieves
throughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
Features
•
•
•
•
•
High-performance, Low-power AVR 8-bit Microcontroller
Advanced RISC Architecture
– 130 powerful instructions - most single-clock cycle execution
– 32 x 8 general purpose working registers
– Fully static operation
– Up to 16 MIPS throughput at 16 MHz
– On-chip 2-cycle multiplier
High Endurance Nonvolatile Memory segments
– 8 KB of In-System Self-programmable Flash program memory
– 512B EEPROM
– 1 KB internal SRAM
– Write/erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional boot code section with independent lock bits
• In-system programming by on-chip boot program
• True read-while-write operation
– Programming lock for software security
®
Microchip QTouch library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
Peripheral Features
– Two 8-bit timer/counters with separate prescaler, one compare mode
– One 16-bit timer/counter with separate prescaler, compare mode, and capture mode
– Real-time counter with separate oscillator
– Three PWM channels
– 8-channel ADC in TQFP and QFN/MLF package
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 1
AVR 8-Bit Microcontroller
–
–
–
–
–
–
•
•
•
•
•
• Eight channels 10-bit accuracy
6-channel ADC in PDIP package
• Six channels 10-bit accuracy
Byte-oriented two-wire serial interface
Programmable serial USART
Master/slave SPI serial interface
Programmable watchdog timer with separate on-chip oscillator
On-chip analog comparator
Special Microcontroller Features
– Power-on Reset and programmable Brown-out Detection
– Internal calibrated RC oscillator
– External and internal interrupt sources
– Five sleep modes: Idle, ADC noise reduction, power-save, power-down, and standby
I/O and Packages
– 23 programmable I/O lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V
Speed Grades
– 0 - 16 MHz
Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.6 mA
– Idle mode: 1.0 mA
– Power-down mode: 0.5 μA
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 2
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description.................................................................................................................9
2. Configuration Summary...........................................................................................10
3. Ordering Information................................................................................................ 11
4. Block Diagram......................................................................................................... 12
5. Pin Configurations................................................................................................... 13
5.1.
5.2.
Pin Descriptions......................................................................................................................... 15
Accessing 16-bit Registers.........................................................................................................17
6. I/O Multiplexing........................................................................................................20
7. Resources............................................................................................................... 22
8. Data Retention.........................................................................................................23
9. About Code Examples.............................................................................................24
10. Capacitive Touch Sensing....................................................................................... 25
10.1. QTouch Library........................................................................................................................... 25
11. AVR CPU Core........................................................................................................ 26
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
11.7.
Overview.................................................................................................................................... 26
ALU – Arithmetic Logic Unit....................................................................................................... 27
Status Register...........................................................................................................................27
General Purpose Register File................................................................................................... 30
Stack Pointer.............................................................................................................................. 31
Instruction Execution Timing...................................................................................................... 32
Reset and Interrupt Handling..................................................................................................... 33
12. AVR Memories.........................................................................................................35
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
Overview.................................................................................................................................... 35
In-System Reprogrammable Flash Program Memory................................................................35
SRAM Data Memory.................................................................................................................. 36
EEPROM Data Memory............................................................................................................. 38
I/O Memory.................................................................................................................................39
Register Description................................................................................................................... 39
13. System Clock and Clock Options............................................................................ 46
13.1. Clock Systems and their Distribution..........................................................................................46
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 3
AVR 8-Bit Microcontroller
13.2.
13.3.
13.4.
13.5.
13.6.
13.7.
13.8.
13.9.
Clock Sources............................................................................................................................ 47
Crystal Oscillator........................................................................................................................ 48
Low-frequency Crystal Oscillator................................................................................................49
External RC Oscillator................................................................................................................ 50
Calibrated Internal RC Oscillator................................................................................................51
External Clock............................................................................................................................ 51
Timer/Counter Oscillator.............................................................................................................52
Register Description................................................................................................................... 52
14. Power Management and Sleep Modes................................................................... 54
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
14.7.
14.8.
Sleep Modes.............................................................................................................................. 54
Idle Mode....................................................................................................................................55
ADC Noise Reduction Mode...................................................................................................... 55
Power-down Mode..................................................................................................................... 55
Power-save Mode...................................................................................................................... 55
Standby Mode............................................................................................................................ 56
Minimizing Power Consumption................................................................................................. 56
Register Description................................................................................................................... 57
15. System Control and Reset.......................................................................................59
15.1.
15.2.
15.3.
15.4.
15.5.
15.6.
Resetting the AVR...................................................................................................................... 59
Reset Sources............................................................................................................................59
Internal Voltage Reference.........................................................................................................62
Watchdog Timer......................................................................................................................... 63
Timed Sequences for Changing the Configuration of the Watchdog Timer............................... 63
Register Description................................................................................................................... 64
16. Interrupts................................................................................................................. 68
16.1. Interrupt Vectors in ATmega8A.................................................................................................. 68
16.2. Register Description................................................................................................................... 73
17. External Interrupts................................................................................................... 76
17.1. Register Description................................................................................................................... 76
18. I/O Ports.................................................................................................................. 80
18.1.
18.2.
18.3.
18.4.
Overview.................................................................................................................................... 80
Ports as General Digital I/O........................................................................................................81
Alternate Port Functions.............................................................................................................84
Register Description................................................................................................................... 93
19. 8-bit Timer/Counter0..............................................................................................104
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
Features................................................................................................................................... 104
Overview.................................................................................................................................. 104
Timer/Counter Clock Sources.................................................................................................. 105
Counter Unit............................................................................................................................. 105
Operation..................................................................................................................................106
Timer/Counter Timing Diagrams.............................................................................................. 106
Register Description................................................................................................................. 106
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 4
AVR 8-Bit Microcontroller
20. Timer/Counter0 and Timer/Counter1 Prescalers................................................... 111
20.1.
20.2.
20.3.
20.4.
20.5.
Overview...................................................................................................................................111
Internal Clock Source................................................................................................................111
Prescaler Reset........................................................................................................................ 111
External Clock Source.............................................................................................................. 111
Register Description................................................................................................................. 112
21. 16-bit Timer/Counter1............................................................................................ 114
21.1. Features................................................................................................................................... 114
21.2. Overview...................................................................................................................................114
21.3. Accessing 16-bit Registers....................................................................................................... 117
21.4. Timer/Counter Clock Sources...................................................................................................119
21.5. Counter Unit............................................................................................................................. 119
21.6. Input Capture Unit.................................................................................................................... 120
21.7. Output Compare Units..............................................................................................................122
21.8. Compare Match Output Unit.....................................................................................................124
21.9. Modes of Operation..................................................................................................................125
21.10. Timer/Counter Timing Diagrams.............................................................................................. 133
21.11. Register Description................................................................................................................. 134
22. 8-bit Timer/Counter2 with PWM and Asynchronous Operation............................. 150
22.1. Features................................................................................................................................... 150
22.2. Overview.................................................................................................................................. 150
22.3. Timer/Counter Clock Sources.................................................................................................. 151
22.4. Counter Unit............................................................................................................................. 151
22.5. Output Compare Unit............................................................................................................... 152
22.6. Compare Match Output Unit.....................................................................................................154
22.7. Modes of Operation..................................................................................................................155
22.8. Timer/Counter Timing Diagrams.............................................................................................. 159
22.9. Asynchronous Operation of the Timer/Counter........................................................................ 161
22.10. Timer/Counter Prescaler.......................................................................................................... 163
22.11. Register Description................................................................................................................. 163
23. SPI – Serial Peripheral Interface........................................................................... 173
23.1.
23.2.
23.3.
23.4.
23.5.
Features................................................................................................................................... 173
Overview.................................................................................................................................. 173
SS Pin Functionality................................................................................................................. 176
Data Modes.............................................................................................................................. 177
Register Description................................................................................................................. 178
24. USART - Universal Synchronous and Asynchronous serial Receiver and
Transmitter.............................................................................................................183
24.1.
24.2.
24.3.
24.4.
24.5.
Features................................................................................................................................... 183
Overview.................................................................................................................................. 183
Clock Generation......................................................................................................................185
Frame Formats.........................................................................................................................188
USART Initialization................................................................................................................. 189
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 5
AVR 8-Bit Microcontroller
24.6. Data Transmission – The USART Transmitter......................................................................... 190
24.7. Data Reception – The USART Receiver.................................................................................. 192
24.8. Asynchronous Data Reception.................................................................................................196
24.9. Multi-Processor Communication Mode.................................................................................... 199
24.10. Accessing UBRRH/UCSRC Registers..................................................................................... 200
24.11. Register Description................................................................................................................. 201
24.12. Examples of Baud Rate Setting............................................................................................... 210
25. TWI - Two-wire Serial Interface............................................................................. 214
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
25.7.
25.8.
Features................................................................................................................................... 214
Overview.................................................................................................................................. 214
Two-Wire Serial Interface Bus Definition..................................................................................216
Data Transfer and Frame Format.............................................................................................217
Multi-master Bus Systems, Arbitration and Synchronization....................................................220
Using the TWI...........................................................................................................................222
Multi-master Systems and Arbitration...................................................................................... 239
Register Description................................................................................................................. 241
26. AC - Analog Comparator....................................................................................... 248
26.1. Overview.................................................................................................................................. 248
26.2. Analog Comparator Multiplexed Input...................................................................................... 248
26.3. Register Description................................................................................................................. 249
27. ADC - Analog to Digital Converter.........................................................................253
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
27.7.
27.8.
Features................................................................................................................................... 253
Overview.................................................................................................................................. 253
Starting a Conversion...............................................................................................................255
Prescaling and Conversion Timing...........................................................................................255
Changing Channel or Reference Selection.............................................................................. 257
ADC Noise Canceler................................................................................................................ 258
ADC Conversion Result........................................................................................................... 262
Register Description................................................................................................................. 263
28. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 272
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
28.9.
Features................................................................................................................................... 272
Overview.................................................................................................................................. 272
Application and Boot Loader Flash Sections............................................................................272
Read-While-Write and No Read-While-Write Flash Sections...................................................273
Boot Loader Lock Bits.............................................................................................................. 275
Entering the Boot Loader Program...........................................................................................276
Addressing the Flash During Self-Programming...................................................................... 277
Self-Programming the Flash.....................................................................................................278
Register Description................................................................................................................. 285
29. MEMPROG- Memory Programming......................................................................288
29.1. Program and Data Memory Lock Bits...................................................................................... 288
29.2. Fuse Bits.................................................................................................................................. 289
29.3. Signature Bytes........................................................................................................................ 291
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 6
AVR 8-Bit Microcontroller
29.4.
29.5.
29.6.
29.7.
29.8.
29.9.
Calibration Byte........................................................................................................................ 291
Page Size................................................................................................................................. 291
Parallel Programming Parameters, Pin Mapping, and Commands..........................................292
Parallel Programming...............................................................................................................294
Serial Downloading.................................................................................................................. 302
Serial Programming Pin Mapping.............................................................................................302
30. Electrical Characteristics – TA = -40°C to 85°C.................................................... 307
30.1.
30.2.
30.3.
30.4.
30.5.
30.6.
30.7.
DC Characteristics................................................................................................................... 307
Speed Grades.......................................................................................................................... 309
Clock Characteristics................................................................................................................309
System and Reset Characteristics........................................................................................... 310
Two-wire Serial Interface Characteristics................................................................................. 311
SPI Timing Characteristics....................................................................................................... 313
ADC Characteristics................................................................................................................. 314
31. Electrical Characteristics – TA = -40°C to 105°C.................................................. 316
31.1. DC Characteristics................................................................................................................... 316
32. Typical Characteristics – TA = -40°C to 85°C........................................................319
32.1. Active Supply Current...............................................................................................................319
32.2. Idle Supply Current...................................................................................................................323
32.3. Power-down Supply Current.................................................................................................... 326
32.4. Power-save Supply Current..................................................................................................... 327
32.5. Standby Supply Current........................................................................................................... 328
32.6. Pin Pull-up................................................................................................................................ 331
32.7. Pin Driver Strength................................................................................................................... 333
32.8. Pin Thresholds and Hysteresis.................................................................................................337
32.9. Bod Thresholds and Analog Comparator Offset...................................................................... 342
32.10. Internal Oscillator Speed..........................................................................................................344
32.11. Current Consumption of Peripheral Units.................................................................................351
32.12. Current Consumption in Reset and Reset Pulsewidth............................................................. 354
33. Typical Characteristics – TA = -40°C to 105°C......................................................356
33.1. ATmega8A Typical Characteristics...........................................................................................356
34. Register Summary.................................................................................................385
35. Instruction Set Summary....................................................................................... 387
36. Packaging Information...........................................................................................391
36.1. 32-pin 32A................................................................................................................................ 391
36.2. 28-pin 28P3.............................................................................................................................. 392
36.3. 32-pin 32M1-A..........................................................................................................................393
37. Errata.....................................................................................................................394
37.1. ATmega8A, rev. L.....................................................................................................................394
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 7
AVR 8-Bit Microcontroller
38. Appendix A: Revision History................................................................................ 396
The Microchip Web Site.............................................................................................. 398
Customer Change Notification Service........................................................................398
Customer Support....................................................................................................... 398
Microchip Devices Code Protection Feature............................................................... 398
Legal Notice.................................................................................................................399
Trademarks................................................................................................................. 399
Quality Management System Certified by DNV...........................................................400
Worldwide Sales and Service......................................................................................401
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 8
AVR 8-Bit Microcontroller
Description
1.
Description
®
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to
be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega8A provides the following features: 8 KB of In-System Programmable Flash with ReadWhile-Write capabilities, 512 B of EEPROM, 1 KB of SRAM, 23 general purpose I/O lines, 32 general
purpose working registers, three flexible timer/counters with compare modes, internal and external
interrupts, a serial programmable USART, one byte oriented two-wire serial interface, a 6-channel ADC
(eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog timer
with internal oscillator, an SPI serial port, and five software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, timer/counters, one SPI port, and interrupt system to
continue functioning. The Power-down mode saves the register contents but freezes the oscillator,
disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the
asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode,
the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low-power consumption.
Microchip offers the QTouch library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust
sensing and includes fully debounced reporting of touch keys and includes Adjacent Key SuppressionTM
(AKSTM) technology for unambiguous detection of key events. The easy-to-use QTouch Composer allows
you to explore, develop and debug your own touch applications.
The device is manufactured using Microchip’s high density nonvolatile memory technology. The on-chip
ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by
a conventional nonvolatile memory programmer, or by an on-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the ATmega8A is a powerful microcontroller that provides
a highly flexible and cost effective solution to many embedded control applications.
The device is supported with a full suite of program and system development tools including: C
Compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kit.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 9
AVR 8-Bit Microcontroller
Configuration Summary
2.
Configuration Summary
Features
ATmega8A
Pin count
32
Flash (KB)
8
SRAM (KB)
1
EEPROM (Bytes)
512
General Purpose I/O pins
23
SPI
1
TWI (I2C)
1
USART
1
ADC
10-bit 15 ksps
ADC channels
6 (8 in TQFP and QFN/MLF packages)
AC propagation delay
Typ 400 ns
8-bit Timer/Counters
2
16-bit Timer/Counters
1
PWM channels
3
RC Oscillator
+/-3%
Operating voltage
2.7 - 5.5V
Max operating frequency
16 MHz
Temperature range
-40°C to +105°C
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 10
AVR 8-Bit Microcontroller
Ordering Information
3.
Ordering Information
Speed (MHz)
16
Power Supply
2.7 - 5.5V
Ordering Code(2)
Package(1)
ATmega8A-AU
ATmega8A-AUR(3)
32A
32A
ATmega8A-PU
28P3
ATmega8A-MU
32M1-A
ATmega8A-MUR(3)
32M1-A
ATmega8A-AN
ATmega8A-ANR(3)
32A
32A
ATmega8A-MN
32M1-A
ATmega8A-MNR(3)
32M1-A
ATmega8A-PN
28P3
Operational Range
Industrial (-40oC to 85oC)
Extended (-40oC to 105oC)
Note:
1. This device can also be supplied in wafer form. Please contact your local Microchip sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Tape and Reel
Package Type
32A
32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A 32-pad, 5 x 5 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame
Package (QFN/MLF)
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 11
AVR 8-Bit Microcontroller
Block Diagram
4.
Block Diagram
Figure 4-1. Block Diagram
SRAM
CPU
FLASH
XTAL1/
TOSC1
XTAL2/
TOSC2
VCC
RESET
GND
Clock generation
8 MHz
Crystal Osc
1/2/4/8MHz
Calib RC
12MHz
External
RC Osc
32.768kHz
XOSC
External
clock
1MHz int
osc
Power
Supervision
POR/BOD &
RESET
ADC[7:0]
AREF
AIN0
AIN1
ADCMUX
Power
management
and clock
control
EEPROMIF
NVM
programming
Watchdog
Timer
Internal
Reference
D
A
T
A
B
U
S
ADC
SPI
PB[7:0]
PC[6:0]
PD[7:0]
EXTINT
INT[1:0]
AC
USART
TC 1
(16-bit)
TWI
TC 2
(8-bit async)
© 2017 Microchip Technology Inc.
MISO
MOSI
SCK
SS
I/O
PORTS
(8-bit)
SDA
SCL
PARPROG
Serial
Programming
TC 0
RxD
TxD
XCK
EEPROM
Datasheet Complete
T0
OC1A/B
T1
ICP1
OC2
40001974A-page 12
AVR 8-Bit Microcontroller
Pin Configurations
5.
Pin Configurations
Figure 5-1. PDIP
(RESET) PC6
1
28
PC5 (ADC5/SCL)
(RXD) PD0
2
27
PC4 (ADC4/SDA)
(TXD) PD1
3
26
PC3 (ADC3)
(INT0) PD2
4
25
PC2 (ADC2)
(INT1) PD3
5
24
PC1 (ADC1)
(XCK/T0) PD4
6
23
PC0 (ADC0)
VCC
7
22
GND
GND
8
21
AREF
(XTAL1/TOSC1) PB6
9
20
AVCC
(XTAL2/TOSC2) PB7
10
19
PB5 (SCK)
(T1) PD5
11
18
PB4 (MISO)
(AIN0) PD6
12
17
PB3 (MOSI/OC2)
(AIN1) PD7
13
16
PB2 (SS/OC1B)
(ICP1) PB0
14
15
PB1 (OC1A)
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 13
AVR 8-Bit Microcontroller
Pin Configurations
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
32
31
30
29
28
27
26
25
Figure 5-2. TQFP Top View
GND
5
20
AREF
VCC
6
19
ADC6
(XTAL1/TOSC1) PB6
7
18
AVCC
(XTAL2/TOSC2) PB7
8
17
PB5 (SCK)
© 2017 Microchip Technology Inc.
16
GND
(MISO) PB4
21
15
4
(MOSI/OC2) PB3
VCC
14
ADC7
(SS/OC1B) PB2
22
13
3
(OC1A) PB1
GND
12
PC0 (ADC0)
(ICP1) PB0
23
11
2
(AIN1) PD7
(XCK/T0) PD4
10
PC1 (ADC1)
(AIN0) PD6
24
9
1
(T1) PD5
(INT1) PD3
Datasheet Complete
40001974A-page 14
AVR 8-Bit Microcontroller
Pin Configurations
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
32
31
30
29
28
27
26
25
Figure 5-3. MLF Top View
GND
3
22
ADC7
VCC
4
21
GND
GND
5
20
AREF
VCC
6
19
ADC6
(XTAL1/TOSC1) PB6
7
18
AVCC
(XTAL2/TOSC2) PB7
8
17
PB5 (SCK)
(MISO) PB4
(MOSI/OC2) PB3
(SS/OC1B) PB2
(OC1A) PB1
(ICP1) PB0
(AIN1) PD7
(AIN0) PD6
(T1) PD5
16
PC0 (ADC0)
15
23
14
2
13
(XCK/T0) PD4
12
PC1 (ADC1)
11
24
10
1
9
(INT1) PD3
NOTE:
The large center pad underneath
the MLF packages is made of
metal and internally connected to
GND. It should be soldered or
glued to the PCB to ensure good
mechanical stability. If the center
pad is left unconneted, the
package might loosen from the
PCB.
5.1
Pin Descriptions
5.1.1
VCC
Digital supply voltage.
5.1.2
GND
Ground.
5.1.3
Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 15
AVR 8-Bit Microcontroller
Pin Configurations
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator
amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator
amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for
the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in Alternate Functions of Port B and System Clock
and Clock Options.
5.1.4
Port C (PC5:PC0)
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
5.1.5
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics
of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer
than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse
length is given in Table 30-5. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated in Alternate Functions of Port C.
5.1.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D
output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port
D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8A as listed in Alternate
Functions of Port D.
5.1.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. The minimum pulse length is given in Table 30-5. Shorter pulses are not
guaranteed to generate a reset.
5.1.8
AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter. Note that Port C (5:4) use digital supply voltage, VCC.
5.1.9
AREF
AREF is the analog reference pin for the A/D Converter.
5.1.10
ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins
are powered from the analog supply and serve as 10-bit ADC channels.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 16
AVR 8-Bit Microcontroller
Pin Configurations
5.2
Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit
data bus. A 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has
a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary
register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the
16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte
stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the
same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit
register is copied into the temporary register in the same clock cycle as the Low byte is read.
Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16-bit
registers does not involve using the temporary register.
To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte
must be read before the High byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts
updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and
ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.
Assembly Code Example(1)
:.
; Set TCNT1 to 0x01FF
ldi
r17,0x01
ldi
r16,0xFF
out
TCNT1H,r17
out
TCNT1L,r16
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
:.
C Code Example(1)
unsigned int i;
:.
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
:.
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs
between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary
register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access
outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update
the temporary register, the main code must disable the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 17
AVR 8-Bit Microcontroller
Pin Configurations
Asesmbly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in
r16,TCNT1L
in
r17,TCNT1H
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note: 1. See About Code Examples.
The assembly code example returns the TCNT1 value in the r17:r16 Register pair.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing
any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out
TCNT1H,r17
out
TCNT1L,r16
; Restore global interrupt flag
out
SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 18
AVR 8-Bit Microcontroller
Pin Configurations
Note: 1. See About Code Examples.
The assembly code example requires that the r17:r16 Register pair contains the value to be written to
TCNT1.
Related Links
About Code Examples
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 19
AVR 8-Bit Microcontroller
I/O Multiplexing
6.
I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. 32-Pin TQFP and MLF: PORT Function Multiplexing
No
PAD32
EXTINT
1
PD[3]
INT1
2
PD[4]
3
GND
4
VCC
5
GND
6
VCC
7
PB[6]
XTAL1/TOSC1
8
PB[7]
XTAL2/TOSC2
9
PD[5]
10
PD[6]
AIN0
11
PD[7]
AIN1
12
PB[0]
ICP1
13
PB[1]
OC1A
14
PB[2]
OC1B
SS0
15
PB[3]
OC2
MOSI0
16
PB[4]
MISO0
17
PB[5]
SCK0
18
AVCC
19
ADC6
20
AREF
21
GND
22
ADC7
ADC7
23
PC[0]
ADC0
24
PC[1]
ADC1
25
PC[2]
ADC2
26
PC[3]
ADC3
27
PC[4]
ADC4
SDA0
28
PC[5]
ADC5
SCL0
29
PC[6]/RESET
30
PD[0]
ADC/AC
OSC
T/C # 0
T/C # 1
T0
USART
I2C
SPI
XCK0
T1
ADC6
© 2017 Microchip Technology Inc.
RXD0
Datasheet Complete
40001974A-page 20
AVR 8-Bit Microcontroller
I/O Multiplexing
No
PAD32
31
PD[1]
32
PD[2]
EXTINT
ADC/AC
OSC
T/C # 0
T/C # 1
USART
I2C
SPI
I2C
SPI
TXD0
INT0
Table 6-2. 28-Pin PDIP: PORT Function Multiplexing
No
PAD28
EXTINT
ADC/AC
OSC
T/C # 0
T/C # 1
1
PC[6]/RESET
2
PD[0]
RXD0
3
PD[1]
TXD0
4
PD[2]
INT0
5
PD[3]
INT1
6
PD[4]
7
VCC
8
GND
9
PB[6]
XTAL1/TOSC1
10
PB[7]
XTAL2/TOSC2
11
PD[5]
12
PD[6]
AIN0
13
PD[7]
AIN1
14
PB[0]
ICP1
15
PB[1]
OC1A
16
PB[2]
OC1B
SS0
17
PB[3]
OC2
MOSI0
18
PB[4]
MISO0
19
PB[5]
SCK0
20
AVCC
21
AREF
22
GND
23
PC[0]
ADC0
24
PC[1]
ADC1
25
PC[2]
ADC2
26
PC[3]
ADC3
27
PC[4]
ADC4
SDA0
28
PC[5]
ADC5
SCL0
T0
USART
XCK0
T1
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 21
AVR 8-Bit Microcontroller
Resources
7.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download
on http://www.atmel.com/avr.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 22
AVR 8-Bit Microcontroller
Data Retention
8.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 23
AVR 8-Bit Microcontroller
About Code Examples
9.
About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device.
These code examples assume that the part specific header file is included before compilation. Be aware
that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Please confirm with the C compiler documentation for more details.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 24
AVR 8-Bit Microcontroller
Capacitive Touch Sensing
10.
10.1
Capacitive Touch Sensing
QTouch Library
®
®
The QTouch library provides a simple to use solution to realize touch sensitive interfaces on most AVR
™
microcontrollers. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and
then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor
states.
The QTouch library is FREE and downloadable from QTouch Library . For implementation details and
other information, refer to the QTouch Library User Guide - also available for download from the
Microchip website.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 25
AVR 8-Bit Microcontroller
AVR CPU Core
11.
AVR CPU Core
11.1
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 11-1. Block Diagram of the AVR MCU Architecture
Program
counter
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R18
R16
R14
R12
R10
R8
R6
R4
R2
R0
Flash program
memory
Instruction
register
Instruction
decode
Data memory
Stack
pointer
Status
register
ALU
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the Program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
Program memory. This concept enables instructions to be executed in every clock cycle. The Program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 26
AVR 8-Bit Microcontroller
AVR CPU Core
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash Program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
The Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format. Every
Program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the Application
program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM
instruction that writes into the Application Flash memory section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt
enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations
following those of the Register File, 0x20 - 0x5F.
11.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or
between a register and an immediate are executed. The ALU operations are divided into three main
categories: arithmetic, logical, and bit functions. Some implementations of the architecture provide a
powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the
Instruction Set section for a detailed description.
11.3
Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. Note that the Status Register is updated after all ALU operations, as specified in the
Instruction Set Reference. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 27
AVR 8-Bit Microcontroller
AVR CPU Core
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 28
AVR 8-Bit Microcontroller
AVR CPU Core
11.3.1
SREG – The AVR Status Register
Name:
Offset:
Reset:
Property:
SREG
0x3F [ID-0000035c]
0x00
When addressing I/O Registers as data space the offset address is 0x5F
When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset
addresses.
Bit
Access
Reset
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – I Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable Register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the Instruction Set Reference.
Bit 6 – T Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD
arithmetic. See the “Instruction Set Description” for detailed information.
Bit 4 – S Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the “Instruction Set Description” for detailed information.
Bit 3 – V Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set
Description” for detailed information.
Bit 2 – N Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 1 – Z Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 29
AVR 8-Bit Microcontroller
AVR CPU Core
Bit 0 – C Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
11.4
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
•
•
•
•
One 8-bit output operand and one 8-bit result input.
Two 8-bit output operands and one 8-bit result input.
Two 8-bit output operands and one 16-bit result input.
One 16-bit output operand and one 16-bit result input.
The following figure shows the structure of the 32 general purpose working registers in the CPU.
Figure 11-2. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions.
As shown in the figure above, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as
SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-,
Y-, and Z-pointer Registers can be set to index any register in the file.
11.4.1
The X-register, Y-register and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X,
Y and Z are defined as described in the following figure.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 30
AVR 8-Bit Microcontroller
AVR CPU Core
Figure 11-3. The X-, Y- and Z-Registers
15
X-register
XH
XL
7
0
7
0
R27 (0x1B)
15
Y-register
R26 (0x1A)
YH
YL
7
0
Z-register
ZH
7
0
0
7
0
R29 (0x1D)
15
0
R28 (0x1C)
ZL
7
0
0
R31 (0x1F)
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).
11.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from
higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The
Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located.
A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or
interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the
Stack Pointer must be set to point above start of the SRAM, see Figure Data Memory Map in SRAM Data
Memory.
See table below for Stack Pointer details.
Table 11-1. Stack Pointer instructions
Instruction Stack pointer
Description
PUSH
Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
POP
Incremented by 1
Data is popped from the stack
RET
RETI
Incremented by 2
Return address is popped from the stack with return from subroutine or
return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
Related Links
SRAM Data Memory
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 31
AVR 8-Bit Microcontroller
AVR CPU Core
11.5.1
SPH and SPL - Stack Pointer High and Stack Pointer Low Register
Bit
15
14
13
12
11
10
9
8
0x3E
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
0x3D
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
Initial Value
0
0
11.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal
clock division is used.
The following figure shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to
obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per
clocks, and functions per power-unit.
Figure 11-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The next figure shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 11-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 32
AVR 8-Bit Microcontroller
AVR CPU Core
11.7
Reset and Interrupt Handling
The Atmel AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned
individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the
Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may
be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves
software security. See the section Memory Programming for details.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt
Vectors. The complete list of Vectors is shown in Interrupts . The list also determines the priority levels of
the different interrupts. The lower the address the higher is the priority level. RESET has the highest
priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the
start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt
Control Register (GICR). Refer to Interrupts for more information. The Reset Vector can also be moved to
the start of the boot Flash section by programming the BOOTRST Fuse, see Boot Loader Support –
Read-While-Write Self-Programming.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt
Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to
execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt
Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt
condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt
Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed
by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do
not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,
the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored
when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI
instruction. The following example shows how this can be used to avoid interrupts during the timed
EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
© 2017 Microchip Technology Inc.
Datasheet Complete
40001974A-page 33
AVR 8-Bit Microcontroller
AVR CPU Core
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
