ATPL230A-AKU-R

ATPL230A ATPL Series Power Line Communications Device DATASHEET Description ATPL230A is a power line communications base band modem, compliant with the PHY layer of PRIME (Power Line Intelligent Metering Evolution) specification. PRIME is an open standard technology used for Smart Grid applications like Smart Metering, Industrial Lighting and Automation, Home Automation, Street Lighting, Solar Energy and PHEV Charging Stations. ATPL230A PRIME device includes enhanced features such as additional robust modes and frequency band extension. ATPL230A is able to operate in independently selectable transmission bands up to 472 kHz, achieving baud rates ranging from 5.4 kbps up to 128.6 kbps. ATPL230A has been conceived to be bundled with an external Atmel ® MCU or MPU. Atmel provides a PRIME PHY layer library which is used by the external MCU/MPU to take control of ATPL230A PHY layer device. Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 1. Features  Modem  Power Line Carrier Modem for 50 Hz and 60 Hz mains  97-carriers OFDM PRIME compliant  DBPSK, DQPSK, D8PSK modulation schemes available  Additional enhanced modes available: DBPSK Robust and DQPSK Robust  Eight selectable channels between 42kHz and 472kHz available. Only one channel can be active at a time FCC ARIB CENELEC A - BCD 2  Baud rate Selectable: 5.4 to 128.6 kbps  Four dedicated buffers for transmission/reception  Up to 124.6 dBμVrms injected signal against PRIME load  Up to 79.6 dB of dynamic range in PRIME networks  Automatic Gain Control and continuous amplitude tracking in signal reception  Class D switching power amplifier control  Integrated 1.2V LDO regulator to supply analog functions  Medium Access Control co-processor features  Viterbi soft decoding and PRIME CRC calculation  128-bit AES encryption  Channel sensing and collision pre-detection ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 471,680 CHANNEL 8 416,992 424,805 CHANNEL 7 362,305 370,117 CHANNEL 6 307,617 315,430 CHANNEL 5 252,930 260,742 CHANNEL 4 198,242 206,055 CHANNEL 3 143.555 151.367 CHANNEL 2 88,867 96,680 41,992 CHANNEL 1 f (kHz) Block Diagram Figure 2-1. ATPL230A Functional Block Diagram VIMA VIPA VRP VRM VRC EMIT(6:11) TXRX1 VZ CROSS ADC TXDRV0 EMIT(0:5) TXRX0 PHY_CORE AGC_CTRL Recepon Chain EMITER_CTRL AGC(0:5) TXDRV1 2. Transmission Chain ZERO CROSS DETECTOR BUF_RX0 BUF_RX2 BUF_RX1 BUF_RX3 BUF_TX0 BUF_TX2 BUF_TX1 BUF_TX3 BER CINR EVM CD RSSI CRC AES CS SCK MOSI MISO EINT ARST SRST PLL INIT CLKEA CLKEB CLKOUT PHY CONTROL SPI BRIDGE CLOCK & RESET INTERFACE ATPL230A POWER MANAGEMENT VDDIO VDDOUT VDDPLL VDDIN VDDIN AN VDDOUT AN GND AGND ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 3 3. Signal Description Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO 3.3V digital supply. Digital power supply must be decoupled by external capacitors Power 3.0V to 3.6V VDDIN 3.3V Digital LDO input supply Power 3.0V to 3.6V VDDIN AN 3.3V Analog LDO input supply Power 3.0V to 3.6V VDDOUT AN 1.2V Analog LDO output. A capacitor in the range 0.1μF - 10μF must be connected to each pin Power 1.2V VDDOUT 1.2V Digital LDO output. A capacitor in the range 0.1μF - 10μF must be connected to each pin Power 1.2V VDDPLL 1.2V PLL supply. It must be decoupled by a 100nF external capacitor, and connected to VDDOUT through a filter (Cut off frequency: 25kHz) Power 1.2V GND(1) Digital Ground Power Analog Ground Power AGND (1) Clocks, Oscillators and PLLs (2) CLKEA External Clock Oscillator • CLKEA must be connected to one terminal of a crystal (when a crystal is being used) or used as input for external clock signal Input VDDIO CLKEB(2) External Clock Oscillator • CLKEB must be connected to one terminal of a crystal (when a crystal is being used) or must be floating when an external clock signal is connected through CLKEA I/O VDDIO CLKOUT 10MHz External Clock Output Output VDDIO Reset/Test ARST Asynchronous Reset Input Low VDDIO Internal pull up(3) SRST Synchronous Reset Input Low VDDIO Internal pull up(3) PLL INIT PLL Initialization Signal Input Low VDDIO Internal pull up(3) PPLC (PRIME Power Line Communications) Transceiver 4 EMIT [0:11](4) PLC Tri-state Transmission ports Output VDDIO AGC [0:5] Automatic Gain Control: • These digital tri-state outputs are managed by AGC hardware logic to drive external circuitry when input signal attenuation is needed Output VDDIO ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 Table 3-1. Signal Description List Type Active Level Voltage reference Signal Name Function TXRX0 Analog Front-End Transmission/Reception for TXDRV0 • This digital output is used to modify external coupling behavior in Transmission/Reception. The suitable value depends on the external circuitry configuration. The polarity of this pin can be inverted by software. Output VDDIO TXRX1 Analog Front-End Transmission/Reception for TXDRV1 • This digital output is used to modify external coupling behavior in Transmission/Reception. The suitable value depends on the external circuitry configuration. The polarity of this pin can be inverted by software. Output VDDIO VZ CROSS(5) Mains Zero-Cross Detection Signal: • This input detects the zero-crossing of the mains voltage Input VDDIO VIMA Negative Differential Voltage Input Input VDDOUT AN VIPA Positive Differential Voltage Input Input VDDOUT AN VRP Internal Reference “Plus” Voltage. Connect an external decoupling capacitor between VRP and VRM (1nF - 100nF) Output VDDOUT AN VRM Internal Reference “Minus” Voltage. Connect an external decoupling capacitor between VRP and VRM (1nF - 100nF) Output VDDOUT AN VRC Common-mode Voltage. Bypass to analog ground with an external decoupling capacitor (100pF - 1nF) Output VDDOUT AN Comments Internal pull down(3) Serial Peripheral Interface - SPI CS SPI CS • SPI bridge Slave Select Input SCK SPI SCK • SPI bridge Clock signal MOSI VDDIO Internal pull up(3) Input VDDIO Internal pull up(3) SPI MOSI • SPI bridge Master Out Slave In Input VDDIO Internal pull up(3) MISO SPI MISO • SPI bridge Master In Slave Out Output VDDIO EINT PHY Layer External Interrupt Output Low Low VDDIO Notes: 1. Separate pins are provided for GND and AGND grounds. Layout considerations should be taken into account to reduce interference. Ground pins should be connected as shortly as possible to the system ground plane. For more details about EMC Considerations, please refer to AVR040 application note. 2. The crystal should be located as close as possible to CLKEA and CLKEB pins. See Table 10-7 on page 112. 3. See Table 10-5 on page 109. 4. Different configurations allowed depending on external topology and net behavior. 5. Depending on whether an isolated or a non-isolated power supply is being used, isolation of this pin should be taken into account in the circuitry design. Please refer to the Reference Design for further information. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 5 4. Package and Pinout 4.1 80-Lead LQFP Package Outline Figure 4-1. Orientation of the 80-Lead LQFP Package 41 60 61 40 80 21 1 4.2 80-Lead LQFP Pinout Table 4-1. 6 20 80 - Lead LQFP Pinout 1 NC 21 VDDIO 41 GND 61 GND 2 NC 22 NC 42 EMIT8 62 AGND 3 NC 23 CLKOUT 43 EMIT9 63 VDDOUT AN 4 ARST 24 CS 44 EMIT10 64 VIMA 5 PLL INIT 25 SCK 45 EMIT11 65 VIPA 6 GND 26 MOSI 46 VDDIO 66 VDDOUT AN 7 CLKEA 27 MISO 47 GND 67 AGND 8 GND 28 VDDIO 48 VDDOUT 68 VRP 9 CLKEB 29 GND 49 TXRX0 69 VRM 10 VDDIO 30 EMIT0 50 TXRX1 70 VRC 11 GND 31 EMIT1 51 GND 71 VDDIN AN 12 VDDPLL 32 EMIT2 52 AGC2 72 AGND 13 GND 33 EMIT3 53 AGC5 73 AGND 14 VDDIN 34 VDDIO 54 AGC1 74 VDDIN AN 15 VDDIN 35 GND 55 AGC4 75 GND 16 GND 36 EMIT4 56 AGC0 76 VDDIO 17 VDDOUT 37 EMIT5 57 AGC3 77 VZ CROSS 18 GND 38 EMIT6 58 VDDIO 78 NC 19 NC 39 EMIT7 59 GND 79 NC 20 SRST 40 VDDIO 60 EINT 80 NC ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 5. Analog Front-End 5.1 PLC coupling circuitry description Atmel PLC coupling reference designs have been designed to achieve high performance, low cost and simplicity. With these values on mind, Atmel has developed a set of PLC couplings covering frequencies up to 472 kHz compliant with different applicable regulations. Atmel PLC technology is purely digital and does not require external DAC/ADC, thus simplifying the external required circuitry. Generally Atmel PLC coupling reference designs make use of few passive components plus a Class D amplification stage for transmission. All PLC coupling reference designs are generally composed by the same sub-circuits:  Transmission Stage  Reception Stage  Filtering Stage  Coupling Stage Figure 5-1. PLC coupling block diagram RECEPTION STAGE AGC0 AGC1 AGC2 AGC3 AGC4 AGC5 VIPA VRC VIMA VDD TO MAINS COUPLING STAGE FILTERING STAGE TRANSMISSION STAGE EMIT0 EMIT1 EMIT2 EMIT3 EMIT4 EMIT5 TXRX0 ATPL230A A particular reference design can contain more than one sub-circuit of the same kind (i.e.: two transmission stages). 5.1.1 Transmission Stage The transmission stage adapts the EMIT signals and amplifies them if required. It can be composed by:  Driver: A group of resistors which adapt the EMIT signals to either control the Class-D amplifier or to be filtered by the next stage.  Amplifier: If required, a Class-D amplifier which generates a square waveform from 0 to VDD is included.  Bias and protection: A couple of resistors and a couple of Schottky barrier diodes provide a DC component and provide protection from received disturbances. Transmission stage shall be always followed by a filtering stage. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 7 5.1.2 Filtering Stage The filtering stage is composed by band-pass filters which have been designed to achieve high performance in field deployments complying at the same time with the proper normative and standards. The in-band flat response filtering stage does not distort the injected signal, reduces spurious emission to the limits set by the corresponding regulation and blocks potential interferences from other transmission channels. The filtering stage has three aims:  Band-pass filtering of high frequency components of the square waveform generated by the transmission stage  Adapt Input/Output impedances for optimal reception/transmission. This is controlled by TXRX signals  In some cases, Band-pass filtering for received signals When the system is intended to be connected to a physical channel with high voltage or which is not electrically referenced to the same point then the filtering stage must be always followed by a coupling stage. 5.1.3 Coupling Stage The coupling stage blocks the DC component of the line to/from which the signal is injected/received (i.e.: 50/60 Hz of the mains). This is carried out by a high voltage capacitor. Coupling stage could also electrically isolate the coupling circuitry from the external world by means of a 1:1 transformer. 5.1.4 Reception Stage The reception stage adapts the received analog signal to be properly captured by the ATPL230A internal reception chain. Reception circuit is independent of the PLC channel which is being used. It basically consists of:  Anti aliasing filter (RC Filter)  Automatic Gain Control (AGC) circuit  Driver of the internal ADC The AGC circuit avoids distortion on the received signal that may arise when the input signal is high enough to polarize the protective diodes in direct region. The driver to the internal ADC comprises a couple of resistors and a couple of capacitors. This driver provides a DC component and adapts the received signal to be properly converted by the internal reception chain. 8 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 5.1.5 Generic PLC Coupling Please consider that this is a generic PLC Coupling design for a particular application please refer to Atmel doc43052 “PLC Coupling Reference Designs”. Figure 5-2. PLC Coupling block diagram detailed RECEPTION STAGE VIPA AGC5 AGC2 AGC4 AGC1 AGC3 AGC0 VRC VIMA 3V3 TRANSMISSION STAGE VDD 3V3 VDD EMIT0 EMIT1 FILTERING STAGE COUPLING STAGE EMIT2 L 3V3 EMIT3 N EMIT4 EMIT5 3V3 VDD 3V3 TXRX + 5.2 ATPLCOUP reference designs Atmel provides PLC coupling reference designs for different applications and frequency bands up to 500 kHz. Please refer to Atmel doc43052 “PLC Coupling Reference Designs” for a detailed description. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9 5.3 Zero-crossing detection 5.3.1 Overview Zero Crossing Detector block works predicting future zero crossings of the Mains signal in function of its past zero crossings. To achieve this, the system embeds a configurable Input Signal Management (ISM) block and a PLL, both of which manage Zero Crossing Detector Input Signal to calculate Zero Crossing Output Flag. The zero-cross detection of waves of 50 Hz and 60 Hz with ±10% of error is supported. The PLL block interprets its input signal such a way that it indicates a zero cross in the middle of a positive pulse. It is important to note that depending on the external circuit implementing the Zero Crossing Detector Input Signal this interpretation is not always correct. Thus, for some cases it is required to transform the Input Signal in a signal where the middle of a positive pulse corresponds to a truly zero cross. This transformation is implemented through the Input Signal Management (ISM) block, configured by MODE_INV and MODE_REP fields in ZC_CONFIG register. Zero Crossing Detector Input Signal (VZ CROSS) must fulfil some requirements. The first requirement is that VZ CROSS signal must be a pulse train with a duty cycle being >60% or 7 16 8.3.1.7 CRC PRIMEPLUS Polynomial Register Name: PRIMEPLUS_CRC_POLY Address: 0xFEF5 (MSB) – 0xFEF6 (LSB) Access: Read/Write Reset: 0x080F 15 14 13 7 6 5 12 11 PRIMEPLUS_CRC_POLY (15:8) 4 3 PRIMEPLUS_CRC_POLY (7:0) 10 9 8 2 1 0 This register allows the PRIME v1.4 mode physical CRC polynomial configuration. Each bit of the register represents a grade coefficient selected by its position into the register. For example the reset value 0x080F corresponds to the polynomial X^12 + X^11 + X^3 + X^2 + X + 1. In this polynomial the active coefficients are 12, 11, 3, 2, 1, 0. The most significant coefficient (12) represents the polynomial grade and is implemented by the algorithm feedback so it is not included in the register. With the other coefficients we calculate the register value needed as follows: 2^11 + 2^3 + 2^2 + 2^1 + 2^0 = 2063 = 0x080F. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 33 8.3.1.8 CRC PRIMEPLUS Reset Value Register Name: PRIMEPLUS_CRC_RST Address: 0xFEF7 (MSB) – 0xFEF8 (LSB) Access: Read/Write Reset: 0x0000 15 14 13 7 6 5 12 11 PRIMEPLUS_CRC_RST (15:8) 4 3 PRIMEPLUS_CRC_RST (7:0) 10 9 8 2 1 0 This register stores the initial value of the PRIME v1.4 mode physical CRC computation algorithm. 34 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 8.3.1.9 Peripheral CRC Polynomial Register Name: VCRC_POLY Address: 0xFF0E (MSB) – 0xFF11 (LSB) Access: Read/Write Reset: 0x04C11DB7 31 30 .. .. .. VCRC_POLY (31:0) .. 1 0 This is a 32 bits register used to store the CRC polynomial mathematical expression. Each register bit location represents an exponential degree of the polynomial. Meaning that, for a register value of 0x04C11DB7; the corresponding polynomial expression is x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1. Note that, the first exponential degree (x^32) is taken by the feedback of the circuit itself. To configure the system in CRC mode, the bit VCRC_POLY(0) must be set to ‘1’. Otherwise, if VCRC_POLY(0) is set to ‘0’ the system works in LFSR (Linear Feedback Shift Register) mode. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 35 8.3.1.10 Peripheral CRC Reset Value Register Name: VCRC_RST Address: 0xFF12 (MSB) – 0xFF15 (LSB) Access: Read/Write Reset: 0x00000000 31 30 .. .. .. VCRC_RST (31:0) .. 1 0 This is a 32 bits register used to store the initial value to start calculating the CRC. This value is fixed by either the CRC used or by the protocol implemented. 36 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 8.3.1.11 Peripheral CRC Configuration Register Name: VCRC_CONF Address: 0xFF16 Access: Read/Write Reset: 0xC3 7 FB_TYPE 6 MSBF 5 MIRRORED32 4 MIRRORED8 3 CIN 2 COUT 1 WIDTH1 0 WIDTH0 This is an 8 bits register used to configure different CRC´s and LFSR´s. This register contains the following control bits: • FB_TYPE: Configures desired circuit feedback type ‘0’: Select circuit feedback type as below. + 4 3 < X^5 X^4 2 < + 1 < X^3 X^2 0 < Input + < X^1 X^0 ‘1’: Select circuit feedback type as below. 4 Input + < 3 < 2 + < 1 0 < < + X^5 X^4 X^3 X^2 X^1 X^0 • MSBF: Allows to choose byte calculation mode ‘0’: Select the least significant bit (LSB) first to start calculations. ‘1’: Select the most significant bit (MSB) first to start calculations. • MIRRORED8: Allows to flip (turn over) the desired CRC size (bytes) in the 32-bit VCRC_CRC register configured by WIDTH1 and WIDTH0 bits. ‘0’: No flipping is performed and the 32-bit VCRC_CRC register will remain unalterable as below. ‘1’: Flip the desired CRC size (bytes) in the 32-bit VCRC_CRC register configured by the control bits WIDTH1 and WIDTH0. For example, if control bits WIDTH1 and WIDTH0 are both set to ‘1’ (CRC size = 4, see link table), it will flip the four blocks of bytes in the register. In another case when CRC size = 3 (WIDTH1=’1’ and WIDTH0=’0’), it will flip the first three blocks of bytes (beginning from less significant byte) in the register ignoring the last byte. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 37 • MIRRORED32: Allows byte shifting in the 32-bit VCRC_CRC register. ‘0’: No byte shifting is performed and the entire 32-bit VCRC_CRC register will remain unalterable as below. ‘1’: The 32-bit VCRC_CRC register is reorganized by shifting the four blocks of bytes. Meaning that, in a byte the MSB will become the LSB. After this command, the VCRC_CRC register will look as below. Both control bits MIRRORED32 AND MIRRORED8 can be set to ‘1’ to obtain the two results simultaneously. • CIN: Complement (opposite) the INPUT byte of the VCRC_INPUT register ‘0’: Disable complement. ‘1’: Enable complement. • COUT: Complement (opposite) the OUTPUT byte of the VCRC_INPUT register ‘0’: Disable complement. ‘1’: Enable complement. • WIDTH(1:0): Select CRC size in bytes: 38 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 WIDTH(1:0) CRC size [Bytes] “00” 1 “01” 2 “10” 3 “11” 4 8.3.1.12 Peripheral CRC Input Register Name: VCRC_INPUT Address: 0xFF17 Access: Read/Write Reset: 0x00 7 6 5 4 3 VCRC_INPUT (7:0) 2 1 0 This is an 8 bits register used to write the input bytes for CRC calculations. Each time a byte has been written in this register, the VCRC block detects the byte automatically and initiates the operation adding this new byte to previous calculations. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 39 8.3.1.13 Peripheral CRC Control Register Name: VCRC_CTL Address: 0xFF18 Access: Read/Write Reset: 0x00 7 0 6 0 5 0 4 BUSY 3 0 2 0 1 0 0 RESTART The VCRC_CTL register contains the following control bits: • BUSY:  ‘0’: VCRC block is ready to receive a new data byte.  ‘1’: VCRC block is busy performing calculations. Unable to write in VCRC_INPUT register. • RESTART: Configures desired circuit feedback type: 40  ‘0’: Reset disable. After a reset, RESTART bit is set to ‘0’ automatically after a period of time.  ‘1’: Reset enable. Delete the actual VCRC_CRC register value and does not affect configuration registers. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 8.3.1.14 Peripheral CRC Value Register Name: VCRC_CRC Address: 0xFF19 (MSB) – 0xFF1C (LSB) Access: Read-only Reset: 0x00000000 31 30 .. .. .. VCRC_CRC (31:0) .. 1 0 This is a 32 bits register containing the final computed CRC value. The value in this register depends on the CRC size (bytes) selected in the control bits WIDTH1 and WIDTH0. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 41 8.3.2 AES Registers 8.3.2.1 Peripheral AES Key Register Name: AES_KEY Address: 0xFFA0 (MSB) – 0xFFAF (LSB) Access: Read/Write Reset: 0x00..00 127 126 .. .. .. AES_KEY (127:0) .. The register AES_KEY is used to store the 128 bits “KEY” of the encryption algorithm. 42 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 1 0 8.3.2.2 Peripheral AES Data Field Register Name: AES_DATA Address: 0xFFB0 (MSB) – 0xFFBF (LSB) Access: Read/Write Reset: 0x00..00 127 126 .. .. .. AES_DATA (127:0) .. 1 0 AES_DATA register is used to store the encrypted/decrypted data. The size of the data packet for an encryption/decryption operation is always 128 bits. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 43 8.3.2.3 Peripheral AES Control Register Name: AES_CTL Address: 0xFFC0 Access: Read/Write Reset: 0x04 7 - 6 - 5 - 4 RESET 3 - 2 READY The register AES_CTL contains some bits for control operation purposes. • RESET: Initializes the AES block: ‘0’: Reset disabled. ‘1’: Reset enabled. • READY: Indicates the encryption/decryption ongoing operation: ‘0’: Indicates encryption/decryption ongoing operation. ‘1’: Indicates encryption/decryption operation is done. • START: Initialize encrypt/decrypt process: ‘1’: Start selected functional mode. Automatically set to ‘0’ after process begins. • CIPHER: Configures functional mode: ‘0’: AES block is in decrypt (decode) mode. ‘1’: AES block is in encrypt (code) mode. 44 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 1 START 0 CIPHER 8.3.3 MAC Info Registers 8.3.3.1 BER SOFT Average Error Registers Name: Address: Access: Reset: 7 TXRXBUF_BERSOFT_AVG_RX0 0xFD57 Read-only 0x00 6 5 4 3 TXRXBUF_BERSOFT_AVG_RX0 2 1 0 After a message is received in BUF_RX0, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi soft* decision. In PRIME v1.4 mode, it is calculated from the arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX0. Name: Address: Access: Reset: 7 TXRXBUF_BERSOFT_AVG_RX1 0xFD58 Read-only 0x00 6 5 4 3 TXRXBUF_BERSOFT_AVG_RX1 2 1 0 After a message is received in BUF_RX1, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi soft* decision. In PRIME v1.4 mode, it is calculated from the arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX1. Name: Address: Access: Reset: 7 TXRXBUF_BERSOFT_AVG_RX2 0xFD59 Read-only 0x00 6 5 4 3 TXRXBUF_BERSOFT_AVG_RX2 2 1 0 After a message is received in BUF_RX2, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi soft* decision. In PRIME v1.4 mode, it is calculated from the arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX2. Name: TXRXBUF_BERSOFT_AVG_RX3 Address: Access: Reset: 0xFD5A Read-only 0x00 7 6 5 4 3 TXRXBUF_BERSOFT_AVG_RX3 2 1 0 After a message is received in BUF_RX3, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi soft* decision. In PRIME v1.4 mode, it is calculated from the ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 45 arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX3. * Viterbi Soft Decision: in “soft” decision there are sixteen decision levels. Once decodified, a strong ‘0’ is represented by a value of “0”, while a strong ‘1’ is represented by a value of “15”. The rest of values are intermediate, so “7” is used to represent a weak ‘0’ and “8” represents a weak ‘1’. Soft decision calculates the error in one bit received as the distance in decision levels between the value received (a value in the range 0 to 15) and the corrected one (0 or 15). Figure 8-2. Example of Viterbi Soft detection decision levels in a BPSK constellation Symbol Threshold Weak `1´ Weak `0´ Str on ge St 9 8 7 0´ r` ´ r `1 ge n ro 6 10 5 11 4 12 Decision Thresholds 3 Φ1 14 15 `1´ 46 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 Example: 2 13 Φ0 Received value = 0 Decodified value = Φex Error accumulated = +3 1 Φex 0 `0´ 8.3.3.2 BER SOFT Maximum Error Registers Name: Address: Access: Reset: 7 TXRXBUF_BERSOFT_MAX_RX0 0xFD5B Read-only 0x00 6 5 4 3 TXRXBUF_BERSOFT_MAX_RX0 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX0, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi soft* decision. The value is cleared by hardware each time a new message is received in BUF_RX0. Name: Address: Access: Reset: 7 TXRXBUF_BERSOFT_MAX_RX1 0xFD5C Read-only 0x00 6 5 4 3 TXRXBUF_BERSOFT_MAX_RX1 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX1, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi soft* decision. The value is cleared by hardware each time a new message is received in BUF_RX1. Name: TXRXBUF_BERSOFT_MAX_RX2 Address: Access: Reset: 0xFD5D Read-only 0x00 7 6 5 4 3 TXRXBUF_BERSOFT_MAX_RX2 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX2, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi soft* decision. The value is cleared by hardware each time a new message is received in BUF_RX2. Name: Address: Access: Reset: 7 TXRXBUF_BERSOFT_MAX_RX3 0xFD5E Read-only 0x00 6 5 4 3 TXRXBUF_BERSOFT_MAX_RX3 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX3, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi soft* decision. The value is cleared by hardware each time a new message is received in BUF_RX3. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 47 8.3.3.3 BER HARD Average Error Registers Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_AVG_RX0 0xFD63 Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_AVG_RX0 2 1 0 After a message is received in BUF_RX0, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi hard* decision. In PRIME v1.4 mode, it is calculated from the arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX0. Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_AVG_RX1 0xFD64 Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_AVG_RX1 2 1 0 After a message is received in BUF_RX1, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi hard* decision. In PRIME v1.4 mode, it is calculated from the arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX1. Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_AVG_RX2 0xFD65 Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_AVG_RX2 2 1 0 After a message is received in BUF_RX2, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi hard* decision. In PRIME v1.4 mode, it is calculated from the arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX2. Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_AVG_RX3 0xFD66 Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_AVG_RX3 2 1 0 After a message is received in BUF_RX3, this register stores the logarithm of the number of accumulated errors regarding the number of received bits, using Viterbi hard* decision. In PRIME v1.4 mode, it is calculated from the 48 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 arithmetic average of the accumulated errors in each one of the four replicated symbols. The value is cleared by hardware each time a new message is received in BUF_RX3. * Viterbi Hard Decision: in “hard” detection there are only two decision levels. If the received value is different than the corrected one, the error value taken is “1”. Otherwise, the error value taken is “0”. Figure 8-3. Example of Viterbi Hard detection decision levels in a BPSK constellation Symbol Threshold = Decision Thresholds Weak `0´ Weak `1´ Str on ge r St ´ `0 `1´ er ng ro 0 1 Example: Received value = 0 Decodified value = Φex Error accumulated = +0 Φ1 Φ0 `1´ Φex `0´ ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 49 8.3.3.4 BER HARD Maximum Error Registers Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_MAX_RX0 0xFD67 Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_MAX_RX0 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX0, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi hard* decision. The value is cleared by hardware each time a new message is received in BUF_RX0. Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_MAX_RX1 0xFD68 Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_MAX_RX1 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX1, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi hard* decision. The value is cleared by hardware each time a new message is received in BUF_RX1. Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_MAX_RX2 0xFD69 Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_MAX_RX2 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX2, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi hard* decision. The value is cleared by hardware each time a new message is received in BUF_RX2. Name: Address: Access: Reset: 7 TXRXBUF_BERHARD_MAX_RX3 0xFD6A Read-only 0x00 6 5 4 3 TXRXBUF_BERHARD_MAX_RX3 2 1 0 Used only in PRIME v1.4 mode. After a message is received in BUF_RX3, this register stores the logarithm of the maximum error of the four replicated symbols, regarding the number of received bits, using Viterbi hard* decision. The value is cleared by hardware each time a new message is received in BUF_RX3. 50 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 8.3.3.5 False Positive Configuration Register Name: FALSE_POSITIVE_CONFIG Address: 0xFEC4 Access: Read/Write Reset: 0x10 7 6 - - 5 ERR_CRC8 _MAC_HD 4 ERR_PROT OCOL 3 ERR_LEN 2 ERR_PAD_ LEN 1 0 ERR_PDU ERR_SP Through FALSE_POSITIVE_CONFIG register the user is able to configure FALSE_POSITIVE register behavior. When a flag of this register is set to ‘1’, the correspondent field of the packet is included in the false positive computation algorithm. False positive algorithm is only enabled in PRIME v1.3 mode. See “False Positive Counter Register” • ERR_CRC8_MAC_HD: Bad CRC8 MAC value (The one located at the header part of the packet). • ERR_PROTOCOL: Unsupported protocol field. • ERR_LEN: Invalid LEN field value. LEN field is located in the PRIME PPDU header and it defines the length of the payload (after coding) in OFDM symbols. See PRIME specification for further details about PPDU structure. • ERR_PAD_LEN: Invalid PAD_LEN value. PAD_LEN field is located in the PRIME PPDU header and it defines the length of the PAD field (after coding) in bytes. See PRIME specification for further details about PPDU structure. • ERR_PDU: Unsupported Header Type. • ERR_SP: Unsupported Security Protocol. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 51 8.3.3.6 False Positive Counter Register Name: FALSE_POSITIVE Address: 0xFEC5 (MSB) – 0xFEC6 (LSB) Access: Read-only Reset: 0x0000 15 14 13 7 6 5 12 11 FALSE_POSITIVE (15:8) 4 3 FALSE_POSITIVE (7:0) 10 9 8 2 1 0 This register holds the number of received PRIME v1.3 packets with a good CRC8_PHY value but with an unsupported value in any of the fields indicated by FALSE_POSITIVE_CONFIG register. Only a physical layer reset initializes the register. Note: 52 Once the register has reached its maximum value, a new error causes the register to roll over. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9. PRIME PHY Layer 9.1 Overview The physical layer consists of a hardware implementation of the enhanced PRIME Physical Layer Entity, which is an Orthogonal Frequency Division Multiplexing (OFDM) system in the 42 kHz to 472 kHz frequency band. This PHY layer transmits and receives MPDUs (MAC Protocol Data Unit) between neighbor nodes. From the transmission point of view, the PHY layer receives its inputs from the MAC (Medium Access Control) layer. At the end of transmission branch, data is output to the physical channel. On the reception side, the PHY layer receives its inputs from the physical channel, and at the end of reception branch, the data flows to the MAC layer. A PHY layer block diagram is shown below: Figure 9-1. PHY Layer Block Diagram Convolutional Encoder from MAC layer Scrambler CRC Interleaver Cyclic Prefix BUF_TXi Sub-carrier Modulator IFFT PRIME PHY Layer to MAC layer BUF_RXi Sub-carrier Demodulator FFT CRC Interleaver Pre - FFT Syncro Convolutional Decoder Scrambler Converter / PAD Tx Gain Control AGC(5:0) TxRx Control TXRX0 Analog Front - End Control Converter TXRX1 Rx Carrier Detection The diagram can be divided in five sub-blocks: TxRx buffers, Transmission branch, Reception branch, Analog Front End control and Carrier Detection. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 53 9.1.1 TxRx Buffers There are 4 dedicated buffers for transmission (BUF_TX0, BUF_TX1, BUF_TX2 and BUF_TX3) and 4 dedicated buffers for reception (BUF_RX0, BUF_RX1, BUF_RX2, BUF_RX3). The main features are shown below: Table 9-1. TxRx Buffers features BUF_TXi Size configurable  Number of buffers enabled configurable  Start time forced or programmed  Transmission can be forced regardless of the carrier detection and frames reception  Transmission parameters configurable  Error detector  9.1.2 BUF_RXi Size configurable  Number of buffers enabled configurable  Enable/Disable interrupts  Parameters saved (BER, RSSI, CINR…)  Transmission Branch PHY layer takes data to be sent from BUF_TXi. The Cyclic Redundancy Check (CRC) fields are hardware-generated in real time, and properly appended to the transmission data. The rest of the chain is hardware-wired, and performs automatically all the tasks needed to send data according to PRIME specifications. In the following figure, the block diagram of the transmission branch is shown. Figure 9-2. Transmission Branch Convolutional From BUF_TXi Encoder Scrambler CRC Interleaver Cyclic Prefix Sub - carrier Modulator IFFT Converter / PAD Tx The output is differential modulated using a DBPSK/DQPSK/D8PSK scheme. After modulation, IFFT (Inverse Fourier Transform) block and cyclic prefix block allow to implement an OFDM scheme. A Converter and a Power Amplifier Driver is the last block in the transmission branch. This block is responsible for adjusting the signal to reach the best transmission efficiency, thus reducing consumption and power dissipation. 9.1.3 Reception Branch The reception branch performs automatically all the tasks needed to process received data. PHY layer delivers data to MAC layer through the BUF_RXi. Figure 9-3. Reception Branch to BUF_RXi 54 Sub - carrier Demodulator FFT CRC Interleaver Pre - FFT Syncro Convolutional Decoder Scrambler ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 Converter Rx 9.1.4 Analog Front End control 9.1.4.1 Gain control This block implements an Automatic Gain Control (AGC) which attenuates the PLC input signal via activating some outputs of the ATPL230A, so there is no saturation and therefore no distortion in the OFDM signal. There are 6 outputs of the ATPL230A controlled by this peripheral. AGC0, AGC1, AGC2, AGC3, AGC4 and AGC5. Please see reference design for further information and recommended external circuitry values. 9.1.4.2 TxRx control This block modifies the configuration of the external Analog Front End by means of TXRX outputs. There are two TXRX outputs, one for each TXDRV. These digital outputs are used to modify external filter conditions between transmission and reception. To allow different external circuitry topologies, the polarity of both signals can be inverted by hardware (see “TXRX Polarity Selector Register” ). Figure 9-4. TxRx control block diagram Gain Control TxRx Control TXDRV0 Emiter Control TXDRV1 Analog Front - End Control AGC [0:5] EMIT [0:5] TXRX0 External Analog Front - End EMIT [6:11] TXRX1 ATPL230A See reference design for further information about TxRx control. 9.1.5 Carrier Detection Looking for an easy detection of incoming messages, the PRIME specification defines a carrier detection algorithm that shall be based on preamble detection and header recognition. ATPL230A implements by hardware a set of detection techniques to control access to medium, thus improving frame synchronization in reception and decreasing collision ratio in transmission. 9.2 PHY parameters A complete description of the PRIME PHY Layer can be found in PRIME specification. Please refer to the PRIME specification provided by the PRIME Alliance in www.prime-alliance.org PRIME specifies a complete set of primitives to manage the PHY Layer, and the PHY-SAP (PHY Service Access Point) from MAC layer. Doc43048 “Atmel PRIME Implementation” integrates all these functions, making them transparent to the final user and simplifying the management. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 55 9.3 PHY Layer Registers 9.3.1 PHY Configuration Registers 9.3.1.1 PHY Layer Special Function Register Name: PHY_SFR Address: 0xFE2A Access: Read/Write Reset: 0x87 7 BCH_ERR 6 CD 5 UMD 4 - 3 - 2 - 1 - 0 INT_PHY • BCH_ERR: Busy Channel Error Flag This bit is cleared to ‘0’ by hardware to indicate the presence of an OFDM signal at the transmission instant. Otherwise, this field value is ‘1’. This bit is used for returning a result of “Busy Channel” in the PHY_DATA confirm primitive (see PRIME specification). • CD: Carrier Detect bit This bit is set to ‘1’ by hardware when an OFDM signal is detected, and it is active during the whole reception. This bit is used in channel access (CSMA-CA algorithm) for performing channel-sensing. • UMD: Unsupported Modulation Scheme flag This flag is set to ‘1’ by hardware every time a header with correct CRC is received, but the PROTOCOL field in this header indicates a modulation scheme not supported by the system. • INT_PHY: Physical Layer interruption This bit is internally connected to the EINT pin. It is Low level active and it is set to '0' by the PHY layer to trigger an interrupt in the external host. In reception, every time a PLC message is received, the PHY layer generates two interrupts. One of them when the physical header is correctly received (two first symbols), and the other one when the message is completely received. In transmission, an interrupt will be generated every time a complete message has been sent. The signal is cleared by writing '1' in the bit PHY_SFR(0). 56 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.1.2 Channel selector Register Name: CTPS Address: 0xFEFA (MSB) – 0xFEFD (LSB) Access: Read/Write Reset: 0x000150C7 31 23 30 22 29 21 15 14 13 7 6 5 28 27 20 19 CTPS(23:16) 12 11 CTPS(15:8) 4 3 CTPS(7:0) 26 18 25 17 24 CTPS (24) 16 10 9 8 2 1 0 Configures the channel: Value Name Description 0x000150C7 CHANNEL1 42 - 89 kHz 0x00026A44 CHANNEL2 97 - 144 kHz 0x000383C1 CHANNEL3 151 - 198 kHz 0x00049D3D CHANNEL4 206 - 253 kHz 0x0005B6BA CHANNEL5 261 - 308 kHz 0x0006D036 CHANNEL6 315 - 362 kHz 0x0007E9B3 CHANNEL7 370 - 417 kHz 0x00090330 CHANNEL8 425 - 472 kHz ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 57 9.3.2 RX Buffers Registers 9.3.2.1 RX Time Registers Name: TXRXBUF_RECTIME_RX0 Address: 0xFD83 – 0xFD86 Access: Read-only Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_RECTIME_RX0 (31:24) 20 19 TXRXBUF_RECTIME_RX0 (23:16) 12 11 TXRXBUF_RECTIME_RX0 (15:8) 4 3 TXRXBUF_RECTIME_RX0 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 26 25 24 18 17 16 10 9 8 2 1 0 26 25 24 18 17 16 10 9 8 2 1 0 Reception Time in Buffer 0. Name: TXRXBUF_RECTIME_RX1 Address: 0xFD87 – 0xFD8A Access: Read-only Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_RECTIME_RX1 (31:24) 20 19 TXRXBUF_RECTIME_RX1 (23:16) 12 11 TXRXBUF_RECTIME_RX1 (15:8) 4 3 TXRXBUF_RECTIME_RX1 (7:0) Reception Time in Buffer 1. Name: TXRXBUF_RECTIME_RX2 Address: 0xFD8B – 0xFD8E Access: Read-only Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 Reception Time in Buffer 2. 58 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 28 27 TXRXBUF_RECTIME_RX2 (31:24) 20 19 TXRXBUF_RECTIME_RX2 (23:16) 12 11 TXRXBUF_RECTIME_RX2 (15:8) 4 3 TXRXBUF_RECTIME_RX2 (7:0) Name: TXRXBUF_RECTIME_RX3 Address: 0xFD8F – 0xFD92 Access: Read-only Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_RECTIME_RX3 (31:24) 20 19 TXRXBUF_RECTIME_RX3 (23:16) 12 11 TXRXBUF_RECTIME_RX3 (15:8) 4 3 TXRXBUF_RECTIME_RX3 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 Reception Time in Buffer 3. When there has been a reception, these registers show when it happened. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 59 9.3.2.2 Buffer Selection Register Name: TXRXBUF_SELECT_BUFF_RX Address: 0xFDD3 Access: Read/Write Reset: 0x00 7 - 6 - 5 - 4 - 3 SB3 2 SB2 Select Reception Buffer: It is used to establish what reception buffers are active. • SB0: Select Buffer 0 0: Disable Buffer 1: Enable Buffer • SB1: Select Buffer 1 0: Disable Buffer 1: Enable Buffer • SB2: Select Buffer 2 0: Disable Buffer 1: Enable Buffer • SB3: Select Buffer 3 0: Disable Buffer 1: Enable Buffer 60 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 1 SB1 0 SB0 9.3.2.3 RX Interrupts Register Name: TXRXBUF_RX_INT Address: 0xFDD4 Access: Read/Write Reset: 0x00 7 PI_RX3 6 PI_RX2 5 PI_RX1 4 PI_RX0 3 HI_RX3 2 HI_RX2 1 HI_RX1 0 HI_RX0 Interrupt Reception Register: When there is some issue with the reception, the micro is warned and then micro tests what buffer is affected through this register. • PI_RX3: Notice Payload Interrupt Reception Buffer 3 • PI_RX2: Notice Payload Interrupt Reception Buffer 2 • PI_RX1: Notice Payload Interrupt Reception Buffer 1 • PI_RX0: Notice Payload Interrupt Reception Buffer 0 • HI_RX3: Notice Header Interrupt Reception Buffer 3 • HI_RX2: Notice Header Interrupt Reception Buffer 2 • HI_RX1: Notice Header Interrupt Reception Buffer 1 • HI_RX0: Notice Header Interrupt Reception Buffer 0 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 61 9.3.2.4 RX Configuration Register Name: TXRXBUF_RXCONF Address: 0xFDD5 Access: Read/Write Reset: 0x02 7 DIS_RX3 6 DIS_RX2 5 DIS_RX1 4 DIS_RX0 3 2 NEXT_BUF 1 EH This register permits us configure/know several features in reception:  Disable an active reception interrupt.  Knowing what buffer will be the next to be written.  Enable/disable header interruptions.  Activate/deactivate the overwrite mode in buffer reception when a reception is received. • DIS_RX3: Disable Interrupt Buffer 3 0: Enabled 1: Disabled • DIS_RX2: Disable Interrupt Buffer 2 0: Enabled 1: Disabled • DIS_RX1: Disable Interrupt Buffer 1 0: Enabled 1: Disabled • DIS_RX0: Disable Interrupt Buffer 0 0: Enabled 1: Disabled • NEXT_BUF: It shows the next buffer which will be written 0: Buffer 0 1: Buffer 1 2: Buffer 2 3: Buffer 3 • EH: Disable header interruptions 0: Disabled 1: Enabled • MS: Enable overwrite mode 0: Disabled 1: Enabled 62 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 0 MS 9.3.2.5 RX Initial Address Registers Name: Address: Access: Reset: TXRXBUF_INITAD_RX0 0xFDD6 - 0xFDD7 Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_INITAD_RX0 (15:8) 4 3 TXRXBUF_INITAD_RX0 (7:0) 10 9 8 2 1 0 12 11 TXRXBUF_INITAD_RX1 (15:8) 4 3 TXRXBUF_INITAD_RX1 (7:0) 10 9 8 2 1 0 12 11 TXRXBUF_INITAD_RX2 (15:8) 4 3 TXRXBUF_INITAD_RX2 (7:0) 10 9 8 2 1 0 12 11 TXRXBUF_INITAD_RX3 (15:8) 4 3 TXRXBUF_INITAD_RX3 (7:0) 10 9 8 2 1 0 Initial Address of Reception Buffer 0. Name: Address: Access: Reset: TXRXBUF_INITAD_RX1 0xFDD8 - 0xFDD9 Read/Write 0x0000 15 14 13 7 6 5 Initial Address of Reception Buffer 1. Name: Address: Access: Reset: TXRXBUF_INITAD_RX2 0xFDDA - 0xFDDB Read/Write 0x0000 15 14 13 7 6 5 Initial Address of Reception Buffer 2. Name: Address: Access: Reset: TXRXBUF_INITAD_RX3 0xFDDC - 0xFDDD Read/Write 0x0000 15 14 13 7 6 5 Initial Address of Reception Buffer 3. These four registers contain four pointers to the beginning of the respective Rx buffer in peripheral memory (buffer 0 to 3). This way, buffers are configurable in both size and position. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 63 9.3.2.6 Robust RX Mode Register Name: TXRXBUF_RXCONF_ROBO_MODE Address: 0xFDF3 Access: Read-only Reset: 0x00 7 6 5 RC_RX3 4 3 RC_RX2 2 RC_RX1 This register shows the reception mode of each RX buffer: • RC_RX0: Buffer 0 reception mode. • RC_RX1: Buffer 1 reception mode. • RC_RX2: Buffer 2 reception mode. • RC_RX3: Buffer 3 reception mode. Value 64 Name Description 0 PRIME 1.3 Mode PRIME v1.3 1 Reserved Reserved 2 PRIME 1.4 PRIME v1.4 reception mode 3 PRIME 1.4 c PRIME v1.4 reception backwards compatible mode ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 1 0 RC_RX0 9.3.3 RX Info Registers 9.3.3.1 Minimum RSSI Registers Name: TXRXBUF_RSSIMIN_RX0 Address: 0xFD6B Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMIN_RX0 2 1 0 This register stores the minimum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX0. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIMIN_RX1 Address: 0xFD6C Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMIN_RX1 2 1 0 This register stores the minimum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX1. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIMIN_RX2 Address: 0xFD6D Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMIN_RX2 2 1 0 This register stores the minimum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX2. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIMIN_RX3 Address: 0xFD6E Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMIN_RX3 2 1 0 This register stores the minimum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX3. The measurement is done at symbol level. The value is stored in dB. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 65 9.3.3.2 Average RSSI Registers Name: TXRXBUF_RSSIAVG_RX0 Address: 0xFD6F Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIAVG_RX0 2 1 0 This register stores the average RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX0. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIAVG_RX1 Address: 0xFD70 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIAVG_RX1 2 1 0 This register stores the average RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX1. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIAVG_RX2 Address: 0xFD71 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIAVG_RX2 2 1 0 This register stores the average RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX2. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIAVG_RX3 Address: 0xFD72 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIAVG_RX3 2 1 0 This register stores the average RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX3. The measurement is done at symbol level. The value is stored in dB. 66 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.3.3 Maximum RSSI Registers Name: TXRXBUF_RSSIMAX_RX0 Address: 0xFD73 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMAX_RX0 2 1 0 This register stores the maximum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX0. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIMAX_RX1 Address: 0xFD74 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMAX_RX1 2 1 0 This register stores the maximum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX1. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIMAX_RX2 Address: 0xFD75 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMAX_RX2 2 1 0 This register stores the maximum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX2. The measurement is done at symbol level. The value is stored in dB. Name: TXRXBUF_RSSIMAX_RX3 Address: 0xFD76 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_RSSIMAX_RX3 2 1 0 This register stores the maximum RSSI (Received Signal Strength Indication) value measured in the last message received in BUF_RX3. The measurement is done at symbol level. The value is stored in dB. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 67 9.3.3.4 Minimum CINR Registers Name: TXRXBUF_CINRMIN_RX0 Address: 0xFD77 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMIN_RX0 2 1 0 This register stores the minimum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX0. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRMIN_RX1 Address: 0xFD78 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMIN_RX1 2 1 0 This register stores the minimum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX1. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRMIN_RX2 Address: 0xFD79 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMIN_RX2 2 1 0 This register stores the minimum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX2. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRMIN_RX3 Address: 0xFD7A Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMIN_RX3 2 1 0 This register stores the minimum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX3. The measurement is done at symbol level. The value is stored in ¼ dB steps. 68 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.3.5 Average CINR Registers Name: TXRXBUF_CINRAVG_RX0 Address: 0xFD7B Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRAVG_RX0 2 1 0 This register stores the average CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX0. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRAVG_RX1 Address: 0xFD7C Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRAVG_RX1 2 1 0 This register stores the average CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX1. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRAVG_RX2 Address: 0xFD7D Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRAVG_RX2 2 1 0 This register stores the average CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX2. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRAVG_RX3 Address: 0xFD7E Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRAVG_RX3 2 1 0 This register stores the average CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX3. The measurement is done at symbol level. The value is stored in ¼ dB steps. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 69 9.3.3.6 Maximum CINR Registers Name: TXRXBUF_CINRMAX_RX0 Address: 0xFD7F Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMAX_RX0 2 1 0 This register stores the maximum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX0. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRMAX_RX1 Address: 0xFD80 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMAX_RX1 2 1 0 This register stores the maximum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX1. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRMAX_RX2 Address: 0xFD81 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMAX_RX2 2 1 0 This register stores the maximum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX2. The measurement is done at symbol level. The value is stored in ¼ dB steps. Name: TXRXBUF_CINRMAX_RX3 Address: 0xFD82 Access: Read-only Reset: 0x00 7 6 5 4 3 TXRXBUF_CINRMAX_RX3 2 1 0 This register stores the maximum CINR (Carrier to Interference + Noise ratio) value measured in the last message received in BUF_RX3. The measurement is done at symbol level. The value is stored in ¼ dB steps. 70 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.3.7 Header EVM Registers Name: TXRXBUF_EVM_HD_RX0 Address: 0xFDA3 - 0xFDA4 Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_HD_RX0 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_HD_RX0 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message header in BUF_RX0. The 7 msb, TXRXBUF_EVM_HD_RX0 (15:9), represent the integer part in %, being the TXRXBUF_EVM_HD_RX0 (8:0) bits the fractional part if more precision were required. This register is used by the physical layer for being in accordance with PRIME specification. Name: TXRXBUF_EVM_HD_RX1 Address: 0xFDA5 - 0xFDA6 Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_HD_RX1 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_HD_RX1 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message header in BUF_RX1. The 7 msb, TXRXBUF_EVM_HD_RX1 (15:9), represent the integer part in %, being the TXRXBUF_EVM_HD_RX1 (8:0) bits the fractional part if more precision were required. This register is used by the physical layer for being in accordance with PRIME specification. Name: TXRXBUF_EVM_HD_RX2 Address: 0xFDA7 - 0xFDA8 Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_HD_RX2 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_HD_RX2 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message header in BUF_RX2. The 7 msb, TXRXBUF_EVM_HD_RX2 (15:9), represent the integer part in %, being the TXRXBUF_EVM_HD_RX2 (8:0) bits the fractional part if more precision were required. This register is used by the physical layer for being in accordance with PRIME specification. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 71 Name: TXRXBUF_EVM_HD_RX3 Address: 0xFDA9 - 0xFDAA Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_HD_RX3 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_HD_RX3 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message header in BUF_RX3. The 7 msb, TXRXBUF_EVM_HD_RX3 (15:9), represent the integer part in %, being the TXRXBUF_EVM_HD_RX3 (8:0) bits the fractional part if more precision were required. This register is used by the physical layer for being in accordance with PRIME specification. 72 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.3.8 Payload EVM Registers Name: TXRXBUF_EVM_PYLD_RX0 Address: 0xFDAB - 0xFDAC Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_PYLD_RX0 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_PYLD_RX0 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message payload in BUF_RX0. The 7 msb, TXRXBUF_EVM_PYLD_RX0 (15:9), represent the integer part in %, being the TXRXBUF_EVM_PYLD_RX0 (8:0) bits the fractional part if more precision were required. Name: TXRXBUF_EVM_PYLD_RX1 Address: 0xFDAD - 0xFDAE Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_PYLD_RX1 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_PYLD_RX1 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message payload in BUF_RX1. The 7 msb, TXRXBUF_EVM_PYLD_RX1 (15:9), represent the integer part in %, being the TXRXBUF_EVM_PYLD_RX1 (8:0) bits the fractional part if more precision were required. Name: TXRXBUF_EVM_PYLD_RX2 Address: 0xFDAF - 0xFDB0 Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_PYLD_RX2 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_PYLD_RX2 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message payload in BUF_RX2. The 7 msb, TXRXBUF_EVM_PYLD_RX2 (15:9), represent the integer part in %, being the TXRXBUF_EVM_PYLD_RX2 (8:0) bits the fractional part if more precision were required. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 73 Name: TXRXBUF_EVM_PYLD_RX3 Address: 0xFDB1 - 0xFDB2 Access: Read-only Reset: 0x0000 15 14 13 12 11 TXRXBUF_EVM_PYLD_RX3 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_EVM_PYLD_RX3 (7:0) 2 1 0 This register stores the maximum EVM (Error Vector Magnitude) measured in the reception of the last message payload in BUF_RX3. The 7 msb, TXRXBUF_EVM_PYLD_RX3 (15:9), represent the integer part in %, being the TXRXBUF_EVM_PYLD_RX3 (8:0) bits the fractional part if more precision were required. 74 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.3.9 Accumulated Header EVM Registers Name: TXRXBUF_EVM_HDACUM_RX0 Address: 0xFDB3 - 0xFDB6 Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_HDACUM_RX0 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_HDACUM_RX0 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_HDACUM_RX0 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message header in BUF_RX0. Name: TXRXBUF_EVM_HDACUM_RX1 Address: 0xFDB7 - 0xFDBA Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_HDACUM_RX1 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_HDACUM_RX1 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_HDACUM_RX1 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message header in BUF_RX1. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 75 Name: TXRXBUF_EVM_HDACUM_RX2 Address: 0xFDBB - 0xFDBE Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_HDACUM_RX2 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_HDACUM_RX2 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_HDACUM_RX2 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message header in BUF_RX2. Name: TXRXBUF_EVM_HDACUM_RX3 Address: 0xFDBF - 0xFDC2 Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_HDACUM_RX3 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_HDACUM_RX3 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_HDACUM_RX3 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message header in BUF_RX3. 76 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.3.10 Accumulated Payload EVM Registers Name: TXRXBUF_EVM_PYLACUM_RX0 Address: 0xFDC3 - 0xFDC6 Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_PYLACUM_RX0 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_PYLACUM_RX0 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_PYLACUM_RX0 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message payload in BUF_RX0. Name: TXRXBUF_EVM_PYLACUM_RX1 Address: 0xFDC7 - 0xFDCA Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_PYLACUM_RX1 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_PYLACUM_RX1 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_PYLACUM_RX1 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message payload in BUF_RX1. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 77 Name: TXRXBUF_EVM_PYLACUM_RX2 Address: 0xFDCB - 0xFDCE Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_PYLACUM_RX2 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_PYLACUM_RX2 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_PYLACUM_RX2 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message payload in BUF_RX2. Name: TXRXBUF_EVM_PYLACUM_RX3 Address: 0xFDCF - 0xFDD2 Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 TXRXBUF_EVM_PYLACUM_RX3 (20:13) 25 24 23 22 21 20 19 18 TXRXBUF_EVM_PYLACUM_RX3 (12:5) 17 16 15 7 0 14 13 12 TXRXBUF_EVM_PYLACUM_RX3 (4:0) 6 0 5 0 4 0 11 10 0 9 0 8 0 3 0 2 0 1 0 0 0 When receiving an OFDM symbol, the total sum of all its individual carriers EVMs (Error Vector Magnitude) is calculated in order to further calculate the average EVM value. This register stores the maximum total sum between the two OFDM symbols received in the last message payload in BUF_RX3. 78 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.4 TX Config Registers 9.3.4.1 Global Amplitude Registers Name: TXRXBUF_GLBL_AMP_TX0 Address: 0xFD20 Access: Read/Write Reset: 0xFF 7 6 5 4 3 TXRXBUF_GLBL_AMP_TX0 2 1 0 Being “Amax” the maximum voltage reachable in the external driver MOS couple, this register sets the global amplitude for the transmitted frame (chirp+header+payload), when BUF_TX0 is used, following this formula: Name: TXRXBUF_GLBL_AMP_TX1 Address: 0xFD21 Access: Read/Write Reset: 0xFF 7 6 5 4 3 TXRXBUF_GLBL_AMP_TX1 2 1 0 Being “Amax” the maximum voltage reachable in the external driver MOS couple, this register sets the global amplitude for the transmitted frame (chirp+header+payload), when BUF_TX1 is used, following this formula: Name: TXRXBUF_GLBL_AMP_TX2 Address: 0xFD22 Access: Read/Write Reset: 0xFF 7 6 5 4 3 TXRXBUF_GLBL_AMP_TX2 2 1 0 Being “Amax” the maximum voltage reachable in the external driver MOS couple, this register sets the global amplitude for the transmitted frame (chirp+header+payload), when BUF_TX2 is used, following this formula: ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 79 Name: TXRXBUF_GLBL_AMP_TX3 Address: 0xFD23 Access: Read/Write Reset: 0xFF 7 6 5 4 3 TXRXBUF_GLBL_AMP_TX3 2 1 0 Being “Amax” the maximum voltage reachable in the external driver MOS couple, this register sets the global amplitude for the transmitted frame (chirp+header+payload), when BUF_TX3 is used, following this formula: 80 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.4.2 Signal Amplitude Registers Name: TXRXBUF_SGNL_AMP_TX0 Address: 0xFD24 Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_SGNL_AMP_TX0 2 1 0 This register stores the amplitude value for the transmitted frame (only header+payload; chirp not affected), when BUF_TX0 is used. If this value is equal to 0xFF, the header+payload transmitted are not attenuated. If this register is equal to 0x00, the header+payload are nullified. Name: TXRXBUF_SGNL_AMP_TX1 Address: 0xFD25 Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_SGNL_AMP_TX1 2 1 0 This register stores the amplitude value for the transmitted frame (only header+payload; chirp not affected), when BUF_TX1 is used. If this value is equal to 0xFF, the header+payload transmitted are not attenuated. If this register is equal to 0x00, the header+payload are nullified. Name: TXRXBUF_SGNL_AMP_TX2 Address: 0xFD26 Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_SGNL_AMP_TX2 2 1 0 This register stores the amplitude value for the transmitted frame (only header+payload; chirp not affected), when BUF_TX2 is used. If this value is equal to 0xFF, the header+payload transmitted are not attenuated. If this register is equal to 0x00, the header+payload are nullified. Name: TXRXBUF_SGNL_AMP_TX3 Address: 0xFD27 Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_SGNL_AMP_TX3 2 1 0 This register stores the amplitude value for the transmitted frame (only header+payload; chirp not affected), when BUF_TX3 is used. If this value is equal to 0xFF, the header+payload transmitted are not attenuated. If this register is equal to 0x00, the header+payload are nullified. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 81 9.3.4.3 Chirp Amplitude Registers Name: TXRXBUF_CHIRP_AMP_TX0 Address: 0xFD28 Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_CHIRP_AMP_TX0 2 1 0 This register stores the amplitude value for the transmitted chirp (header and payload not affected), when BUF_TX0 is used. If this value is equal to 0xFF, the chirp transmitted is not attenuated. If this register is equal to 0x00, the chirp is nullified. Name: TXRXBUF_CHIRP_AMP_TX1 Address: 0xFD29 Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_CHIRP_AMP_TX1 2 1 0 This register stores the amplitude value for the transmitted chirp (header and payload not affected), when BUF_TX1 is used. If this value is equal to 0xFF, the chirp transmitted is not attenuated. If this register is equal to 0x00, the chirp is nullified. Name: TXRXBUF_CHIRP_AMP_TX2 Address: 0xFD2A Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_CHIRP_AMP_TX2 2 1 0 This register stores the amplitude value for the transmitted chirp (header and payload not affected), when BUF_TX2 is used. If this value is equal to 0xFF, the chirp transmitted is not attenuated. If this register is equal to 0x00, the chirp is nullified. Name: TXRXBUF_CHIRP_AMP_TX3 Address: 0xFD2B Access: Read/Write Reset: 0x60 7 6 5 4 3 TXRXBUF_CHIRP_AMP_TX3 2 1 0 This register stores the amplitude value for the transmitted chirp (header and payload not affected), when BUF_TX3 is used. If this value is equal to 0xFF, the chirp transmitted is not attenuated. If this register is equal to 0x00, the chirp is nullified. 82 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.5 TX Buffers Registers 9.3.5.1 TX Time Registers Name: TXRXBUF_EMITIME_TX0 Address: 0xFD00 - 0xFD03 Access: Read/Write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_EMITIME_TX0 (31:24) 20 19 TXRXBUF_EMITIME_TX0 (23:16) 12 11 TXRXBUF_EMITIME_TX0 (15:8) 4 3 TXRXBUF_EMITIME_TX0 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 28 27 TXRXBUF_EMITIME_TX1 (31:24) 20 19 TXRXBUF_EMITIME_TX1 (23:16) 12 11 TXRXBUF_EMITIME_TX1 (15:8) 4 3 TXRXBUF_EMITIME_TX1 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 28 27 TXRXBUF_EMITIME_TX2 (31:24) 20 19 TXRXBUF_EMITIME_TX2 (23:16) 12 11 TXRXBUF_EMITIME_TX2 (15:8) 4 3 TXRXBUF_EMITIME_TX2 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 Transmission time of Buffer 0. Name: TXRXBUF_EMITIME_TX1 Address: 0xFD04 - 0xFD07 Access: Read/Write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 Transmission time of Buffer 1. Name: TXRXBUF_EMITIME_TX2 Address: 0xFD08 - 0xFD0B Access: Read/Write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 Transmission time of Buffer 2. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 83 Name: TXRXBUF_EMITIME_TX3 Address: 0xFD0C - 0xFD0F Access: Read/Write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_EMITIME_TX3 (31:24) 20 19 TXRXBUF_EMITIME_TX3 (23:16) 12 11 TXRXBUF_EMITIME_TX3 (15:8) 4 3 TXRXBUF_EMITIME_TX3 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 Transmission time of Buffer 3. These registers contain the time value (referenced to the 20-bit PHY layer global timer) when a programmed transmission in the corresponding buffer shall begin. 84 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.5.2 TX Post-activation Time TxRx Registers Name: Address: Access: Reset: TXRXBUF_TXRX_TA_TX0 0xFD10 - 0xFD11 Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TA_TX0 (15:8) 4 3 TXRXBUF_TXRX_TA_TX0 (7:0) 10 9 8 2 1 0 10 9 8 2 1 0 10 9 8 2 1 0 10 9 8 2 1 0 Post-activation time TxRx of Buffer 0. Name: Address: Access: Reset: TXRXBUF_TXRX_TA_TX1 0xFD12 - 0xFD13 Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TA_TX1 (15:8) 4 3 TXRXBUF_TXRX_TA_TX1 (7:0) Post-activation time TxRx of Buffer 1. Name: Address: Access: Reset: TXRXBUF_TXRX_TA_TX2 0xFD14 - 0xFD15 Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TA_TX2 (15:8) 4 3 TXRXBUF_TXRX_TA_TX2 (7:0) Post-activation time TxRx of Buffer 2. Name: Address: Access: Reset: TXRXBUF_TXRX_TA_TX3 0xFD16 - 0xFD17 Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TA_TX3 (15:8) 4 3 TXRXBUF_TXRX_TA_TX3 (7:0) Post-activation time TxRx of Buffer 3. The user can modify these registers to set the period of time to maintain active (according to polarity) TXRX output signals once a transmission has finished. This parameter is useful to improve the external coupling transient response. When automatic TxRx has been selected, in these registers must be set this time for the suitable buffer. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 85 9.3.5.3 TX Pre-activation Time TxRx Registers Name: Address: Access: Reset: TXRXBUF_TXRX_TB_TX0 0xFD18 - 0xFD19 Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TB_TX0 (15:8) 4 3 TXRXBUF_TXRX_TB_TX0 (7:0) 10 9 8 2 1 0 10 9 8 2 1 0 10 9 8 2 1 0 10 9 8 2 1 0 Pre-activation time TxRx of Buffer 0. Name: Address: Access: Reset: TXRXBUF_TXRX_TB_TX1 0xFD1A - 0xFD1B Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TB_TX1 (15:8) 4 3 TXRXBUF_TXRX_TB_TX1 (7:0) Pre-activation time TxRx of Buffer 1. Name: Address: Access: Reset: TXRXBUF_TXRX_TB_TX2 0xFD1C - 0xFD1D Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TB_TX2 (15:8) 4 3 TXRXBUF_TXRX_TB_TX2 (7:0) Pre-activation time TxRx of Buffer 2. Name: Address: Access: Reset: TXRXBUF_TXRX_TB_TX3 0xFD1E - 0xFD1F Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_TXRX_TB_TX3 (15:8) 4 3 TXRXBUF_TXRX_TB_TX3 (7:0) Pre-activation time TxRx of Buffer 3. The user can modify these registers to specify the period of time to set active (according to polarity) TXRX output signals before a transmission starts. This parameter is useful to improve the external coupling transient response. When automatic TxRx has been selected, in these registers must be set this time for the suitable buffer. 86 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.5.4 TX Timeout Registers Name: Address: Access: Reset: TXRXBUF_TIMEOUT_TX0 0xFD2C - 0xFD2F Read/Write 0x000124F8 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_TIMEOUT_TX0 (31:24) 20 19 TXRXBUF_TIMEOUT_TX0 (23:16) 12 11 TXRXBUF_TIMEOUT_TX0 (15:8) 4 3 TXRXBUF_TIMEOUT_TX0 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 26 25 24 18 17 16 10 9 8 2 1 0 26 25 24 18 17 16 10 9 8 2 1 0 Timeout Buffer 0. Name: Address: Access: Reset: TXRXBUF_TIMEOUT_TX1 0xFD30 - 0xFD33 Read/Write 0x000124F8 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_TIMEOUT_TX1 (31:24) 20 19 TXRXBUF_TIMEOUT_TX1 (23:16) 12 11 TXRXBUF_TIMEOUT_TX1 (15:8) 4 3 TXRXBUF_TIMEOUT_TX1 (7:0) Timeout Buffer 1. Name: Address: Access: Reset: TXRXBUF_TIMEOUT_TX2 0xFD34 - 0xFD37 Read/Write 0x000124F8 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_TIMEOUT_TX2 (31:24) 20 19 TXRXBUF_TIMEOUT_TX2 (23:16) 12 11 TXRXBUF_TIMEOUT_TX2 (15:8) 4 3 TXRXBUF_TIMEOUT_TX2 (7:0) Timeout Buffer 2. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 87 Name: Address: Access: Reset: TXRXBUF_TIMEOUT_TX3 0xFD38 - 0xFD3B Read/Write 0x000124F8 31 30 29 23 22 21 15 14 13 7 6 5 28 27 TXRXBUF_TIMEOUT_TX3 (31:24) 20 19 TXRXBUF_TIMEOUT_TX3 (23:16) 12 11 TXRXBUF_TIMEOUT_TX3 (15:8) 4 3 TXRXBUF_TIMEOUT_TX3 (7:0) 26 25 24 18 17 16 10 9 8 2 1 0 Timeout Buffer 3. Transmission timeout. Maximum period of time that the PHY layer shall wait before discarding a frame that is waiting to be transmitted. 88 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.5.5 TX Configuration Registers Name: TXRXBUF_TXCONF_TX0 Address: 0xFD3C Access: Read/Write Reset: 0xA0 7 - 6 5 4 3 2 1 0 TRS0 ATR0 - FE0 EB0 DC0 DR0 • TRS0: TxRx established by software in buffer 0. TxRx established by software for activated/deactivated TXRX signal before/after each transmission to work properly transistors when this feature has been selected. 0: Disabled 1: Enabled • ATR0: TxRx control mode in buffer 0. Establishing software/hardware control of TXRX signal for transmitting. 1: by hardware 0: by software • FE0: Transmission forced/unforced in buffer 0. When force transmission is required, if it is possible (Carrier Detection or Reception are in course and not disable) and suitable buffer is enabled, a transmission is immediately started. 0: Transmission unforced 1: Transmission forced • EB0: Buffer 0 enabled/disabled in buffer 0. Enable buffer that it has been required. 0: Disabled 1: Enabled • DC0: Carrier Detect enabled/disabled for transmission in buffer 0. Starting transmission though carrier detection is in course. 0: Enabled 1: Disabled • DR0: Reception enabled/disabled for transmission in buffer 0. Starting transmission though reception is in course. 0: Enabled 1: Disabled ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 89 Name: TXRXBUF_TXCONF_TX1 Address: 0xFD3D Access: Read/Write Reset: 0xA0 7 - 6 5 4 3 2 1 0 TRS1 ATR1 - FE1 EB1 DC1 DR1 • TRS1: TxRx established by software in buffer 1. TxRx established by software for activated/deactivated TXRX signal before/after each transmission to work properly transistors when this feature has been selected. 0: Disabled 1: Enabled • ATR1: TxRx control mode in buffer 1. Establishing software/hardware control of TXRX signal for transmitting. 1: by hardware 0: by software • FE1: Transmission forced/unforced in buffer 1. When force transmission is required, if it is possible (Carrier Detection or Reception are in course and not disable) and suitable buffer is enabled, a transmission is immediately started. 0: Transmission unforced 1: Transmission forced • EB1: Buffer 0 enabled/disabled in buffer 1. Enable buffer that it has been required. 0: Disabled 1: Enabled • DC1: Carrier Detect enabled/disabled for transmission in buffer 1. Starting transmission though carrier detection is in course. 0: Enabled 1: Disabled • DR1: Reception enabled/disabled for transmission in buffer 1. Starting transmission though reception is in course. 0: Enabled 1: Disabled 90 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 Name: TXRXBUF_TXCONF_TX2 Address: 0xFD3E Access: Read/Write Reset: 0xA0 7 - 6 5 4 3 2 1 0 TRS2 ATR2 - FE2 EB2 DC2 DR2 • TRS2: TxRx established by software in buffer 2. TxRx established by software for activated/deactivated TXRX signal before/after each transmission to work properly transistors when this feature has been selected. 0: Disabled 1: Enabled • ATR2: TxRx control mode in buffer 2. Establishing software/hardware control of TXRX signal for transmitting. 1: by hardware 0: by software • FE2: Transmission forced/unforced in buffer 2. When force transmission is required, if it is possible (Carrier Detection or Reception are in course and not disable) and suitable buffer is enabled, a transmission is immediately started. 0: Transmission unforced 1: Transmission forced • EB2: Buffer 0 enabled/disabled in buffer 2. Enable buffer that it has been required. 0: Disabled 1: Enabled • DC2: Carrier Detect enabled/disabled for transmission in buffer 2. Starting transmission though carrier detection is in course. 0: Enabled 1: Disabled • DR2: Reception enabled/disabled for transmission in buffer 2. Starting transmission though reception is in course. 0: Enabled 1: Disabled ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 91 Name: TXRXBUF_TXCONF_TX3 Address: 0xFD3F Access: Read/Write Reset: 0xA0 7 - 6 5 4 3 2 1 0 TRS3 ATR3 - FE3 EB3 DC3 DR3 • TRS3: TxRx established by software in buffer 3. TxRx established by software for activated/deactivated TXRX signal before/after each transmission to work properly transistors when this feature has been selected. 0: Disabled 1: Enabled • ATR3: TxRx control mode in buffer 3. Establishing software/hardware control of TXRX signal for transmitting. 1: by hardware 0: by software • FE3: Transmission forced/unforced in buffer 3. When force transmission is required, if it is possible (Carrier Detection or Reception are in course and not disable) and suitable buffer is enabled, a transmission is immediately started. 0: Transmission unforced 1: Transmission forced • EB3: Buffer 0 enabled/disabled in buffer 3. Enable buffer that it has been required. 0: Disabled 1: Enabled • DC3: Carrier Detect enabled/disabled for transmission in buffer 3. Starting transmission though carrier detection is in course. 0: Enabled 1: Disabled • DR3: Reception enabled/disabled for transmission in buffer 3. Starting transmission though reception is in course. 0: Enabled 1: Disabled 92 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.5.6 TX Initial Address Registers Name: Address: Access: Reset: TXRXBUF_INITAD_TX0 0xFD40 - 0xFD41 Read/Write 0x0000 15 14 13 7 6 5 12 11 TXRXBUF_INITAD_TX0 (15:8) 4 3 TXRXBUF_INITAD_TX0 (7:0) 10 9 8 2 1 0 12 11 TXRXBUF_INITAD_TX1 (15:8) 4 3 TXRXBUF_INITAD_TX1 (7:0) 10 9 8 2 1 0 12 11 TXRXBUF_INITAD_TX2 (15:8) 4 3 TXRXBUF_INITAD_TX2 (7:0) 10 9 8 2 1 0 12 11 TXRXBUF_INITAD_TX3 (15:8) 4 3 TXRXBUF_INITAD_TX3 (7:0) 10 9 8 2 1 0 Initial Address of Transmission Buffer 0. Name: Address: Access: Reset: TXRXBUF_INITAD_TX1 0xFD42 - 0xFD43 Read/Write 0x0000 15 14 13 7 6 5 Initial Address of Transmission Buffer 1. Name: Address: Access: Reset: TXRXBUF_INITAD_TX2 0xFD44 - 0xFD45 Read/Write 0x0000 15 14 13 7 6 5 Initial Address of Transmission Buffer 2. Name: Address: Access: Reset: TXRXBUF_INITAD_TX3 0xFD46 - 0xFD47 Read/Write 0x0000 15 14 13 7 6 5 Initial Address of Transmission Buffer 3. These four registers contain four pointers to the beginning of the respective Tx buffer in peripheral memory (buffer 0 to 3). This way, buffers are configurable in both size and position. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 93 9.3.5.7 TX Result Register Name: TXRXBUF_RESULT_TX Address: 0xFD50 - 0xFD51 Access: Read-only Reset: 0x1111 15 7 - 14 6 13 ET_TX1 5 ET_TX3 12 4 11 3 - 10 2 This register stores the transmission status of each buffer. Value 94 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 Name Description 0 ET0_TX Transmission in process 1 ET1_TX Successful transmission 2 ET2_TX Wrong Length 3 ET3_TX Busy Channel 4 ET4_TX Previous transmission in process 5 ET5_TX Reception transmission in process 6 ET6_TX Invalid Scheme 7 ET7_TX Timeout 9 ET_TX0 1 ET_TX2 8 0 9.3.5.8 TX Interrupts Register Name: TXRXBUF_TX_INT Address: 0xFD52 Access: Read-only Reset: 0x00 7 - 6 5 4 3 - - HI_N HI_TX3 2 HI_TX2 1 HI_TX1 0 HI_TX0 Interrupt register of Transmission and Noise buffers: • HI_N: Notice Interrupt Noise Buffer • HI_TX3: Notice Interrupt Transmission Buffer 3 • HI_TX2: Notice Interrupt Transmission Buffer 2 • HI_TX1: Notice Interrupt Transmission Buffer 1 • HI_TX0: Notice Interrupt Transmission Buffer 0 When there is some issue with the transmission or noise reception, the micro is warned and then micro tests what buffer is affected through this register. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 95 9.3.5.9 Robust TX Control Register Name: TXRXBUF_TXCONF_ROBO_CTL Address: 0xFDF2 Access: Read/Write Reset: 0x00 7 6 5 RC3 4 RC2 3 2 RC1 This register sets the transmission mode of each TX buffer • RC0: Buffer 0 transmission mode • RC1: Buffer 1 transmission mode • RC2: Buffer 2 transmission mode • RC3: Buffer 3 transmission mode Value 96 Name Description 0 PRIME 1.3 Mode PRIME v1.3 1 Reserved Reserved 2 PRIME 1.4 PRIME v1.4 transmission mode 3 PRIME 1.4 c PRIME v1.4 transmission backwards compatible mode ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 1 0 RC0 9.3.6 AFE Configuration Registers 9.3.6.1 Branch Selection Register Name: TXRXBUF_TXCONF_SELBRANCH Address: 0xFDFB Access: Read/Write Reset: 0x00 7 BR2_TX3 6 BR1_TX3 5 BR2_TX2 4 BR1_TX2 3 BR2_TX1 2 BR1_TX1 1 BR2_TX0 0 BR1_TX0 • BR1_TX0: Enable/Disable EMIT(0:5) output pins, when BUF_TX0 is used 1: Enabled 0: Disabled • BR2_TX0: Enable/Disable EMIT(6:11) output pins, when BUF_TX0 is used 1: Enabled 0: Disabled • BR1_TX1: Enable/Disable EMIT(0:5) output pins, when BUF_TX1 is used 1: Enabled 0: Disabled • BR2_TX1: Enable/Disable EMIT(6:11) output pins, when BUF_TX1 is used 1: Enabled 0: Disabled • BR1_TX2: Enable/Disable EMIT(0:5) output pins, when BUF_TX2 is used 1: Enabled 0: Disabled • BR2_TX2: Enable/Disable EMIT(6:11) output pins, when BUF_TX2 is used 1: Enabled 0: Disabled • BR1_TX3: Enable/Disable EMIT(0:5) output pins, when BUF_TX3 is used 1: Enabled 0: Disabled • BR2_TX3: Enable/Disable EMIT(6:11) output pins, when BUF_TX3 is used 1: Enabled 0: Disabled ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 97 9.3.6.2 TXRX Polarity Selector Register Name: AFE_CTL Address: 0xFE90 Access: Read/Write Reset: 0x00 7 - 6 - 5 - 4 - 3 - • TXRX1_POL: TXRX1 pin polarity control 0: TXRX1 pin output = ‘0’ in transmission and ‘1’ in reception. 1: TXRX1 pin output = ‘1’ in transmission and ‘0’ in reception. • TXRX0_POL: TXRX0 pin polarity control 0: TXRX0 pin output = ‘0’ in transmission and ‘1’ in reception. 1: TXRX0 pin output = ‘1’ in transmission and ‘0’ in reception. 98 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 2 - 1 0 TXRX1_POL TXRX0_POL 9.3.7 Zero-crossing Registers 9.3.7.1 Zero-Cross Time Registers Name: TXRXBUF_ZCT_RX0 Address: 0xFD93 - 0xFD96 Access: Read-only Reset: 0x00000000 31 30 29 28 27 TXRXBUF_ZCT_RX0 (31:24) 26 25 24 23 22 21 20 19 TXRXBUF_ZCT_RX0 (23:16) 18 17 16 15 14 13 12 11 TXRXBUF_ZCT_RX0 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_ZCT_RX0 (7:0) 2 1 0 Instant in time at which the last zero-cross event took place, at the end of the last message received in BUF_RX0. It is expressed in 10 μs steps. It is set by hardware and is a read-only register. This register is used by the physical layer for being in accordance with PRIME specification. Name: TXRXBUF_ZCT_RX1 Address: 0xFD97 - 0xFD9A Access: Read-only Reset: 0x00000000 31 30 29 28 27 TXRXBUF_ZCT_RX1 (31:24) 26 25 24 23 22 21 20 19 TXRXBUF_ZCT_RX1 (23:16) 18 17 16 15 14 13 12 11 TXRXBUF_ZCT_RX1 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_ZCT_RX1 (7:0) 2 1 0 Instant in time at which the last zero-cross event took place, at the end of the last message received in BUF_RX1. It is expressed in 10 μs steps. It is set by hardware and is a read-only register. This register is used by the physical layer for being in accordance with PRIME specification. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 99 Name: TXRXBUF_ZCT_RX2 Address: 0xFD9B - 0xFD9E Access: Read-only Reset: 0x00000000 31 30 29 28 27 TXRXBUF_ZCT_RX2 (31:24) 26 25 24 23 22 21 20 19 TXRXBUF_ZCT_RX2 (23:16) 18 17 16 15 14 13 12 11 TXRXBUF_ZCT_RX2 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_ZCT_RX2 (7:0) 2 1 0 Instant in time at which the last zero-cross event took place, at the end of the last message received in BUF_RX2. It is expressed in 10 μs steps. It is set by hardware and is a read-only register. This register is used by the physical layer for being in accordance with PRIME specification. Name: TXRXBUF_ZCT_RX3 Address: 0xFD9F - 0xFDA2 Access: Read-only Reset: 0x00000000 31 30 29 28 27 TXRXBUF_ZCT_RX3 (31:24) 26 25 24 23 22 21 20 19 TXRXBUF_ZCT_RX3 (23:16) 18 17 16 15 14 13 12 11 TXRXBUF_ZCT_RX3 (15:8) 10 9 8 7 6 5 4 3 TXRXBUF_ZCT_RX3 (7:0) 2 1 0 Instant in time at which the last zero-cross event took place, at the end of the last message received in BUF_RX3. It is expressed in 10 μs steps. It is set by hardware and is a read-only register. This register is used by the physical layer for being in accordance with PRIME specification. 100 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.7.2 Zero Crossing Configuration Register Name: ZC_CONFIG Address: 0xFF1E Access: Read/Write Reset: 0x00 7 - 6 - 5 - 4 - 3 2 1 0 MODE_REP MODE_INV MODE_ASC MODE_MUX • MODE_REP: Repetition Mode ‘0’: No effect. ‘1’: Zero Crossing Detector Input Signal period is down by half. • MODE_INV: Inversion Mode ‘0’: No effect. ‘1’: Zero Crossing Detector Input Signal is inverted. • MODE_ASC: Ascent-Descent Mode ‘0’: If MODE_MUX is 1, Ascent Zero Crossing. ‘1’: If MODE_MUX is 1, Descent Zero Crossing. • MODE_MUX: Zero Crossing Mode ‘0’: Selection of both ascent and descent zero-crossing. ‘1’: Selection of ascent or descent zero-crossing. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 101 9.3.7.3 Zero Crossing Filter Register Name: ZC_FILTER Address: 0xFF23 Access: Read/Write Reset: 0xB2 7 ZC_FILTER_BP 6 5 4 3 ZC_FILTER_NUM [6:0] 2 1 0 • ZC_FILTER_BP: Zero Crossing Input Signal Filter Enable ‘0’: Filter enabled. ‘1’: Filter not enabled. • ZC_FILTER_NUM [6:0]: Zero Crossing Input Signal Filter Parameter Time (counted in number of clock cycles) that the Zero Crossing Input Signal (1-bit) must be constant to set that value as the input signal for Zero Crossing Detection. Used to refuse fast transitions in Zero Crossing Input Signal. 102 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.8 Other Registers 9.3.8.1 System Configuration Register Name: SYS_CONFIG Address: 0xFE2C Access: Read/Write Reset: 0x04 7 - 6 - 5 - 4 - 3 2 1 0 CONV_PD - - PHY_RST • CONV_PD: Converter Power Down Microcontroller can activate internal converter power down mode by setting this bit. When internal converter is in power down mode, the system is unable to receive. This bit is high-level active. • PHY_RST: Physical Layer Reset This bit resets the Physical layer. To perform a Physical layer reset cycle, microcontroller must set this bit to ‘1’ and then must clear it to ‘0’. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 103 9.3.8.2 PHY Layer Timer Register Name: TIMER_BEACON_REF Address: 0xFE47 - 0xFE4A Access: Read-only Reset: 0x00000000 31 30 29 28 27 TIMER_BEACON_REF (31:24) 26 25 24 23 22 21 20 19 TIMER_BEACON_REF (23:16) 18 17 16 15 14 13 12 11 TIMER_BEACON_REF (15:8) 10 9 8 7 6 5 4 3 TIMER_BEACON_REF (7:0) 2 1 0 Timer for the physical layer, which consists of a free-running clock measured in 10 μs steps. It indefinitely increases a unit each 10 microseconds, overflowing back to 0. It is set by hardware and is a read-only register. This register is used by the physical layer for being in accordance with PRIME specification. 104 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.8.3 PHY Layer Error Counter Register Name: PHY_ERRORS Address: 0xFE94 Access: Read/Write Reset: 0x00 7 - 6 - 5 - 4 3 2 PHY_ERRORS 1 0 The system stores in these bits the number of times that a Physical layer error has occurred. This counter can be cleared to zero. The value stored in this register is cleared every time the register is read. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 105 10. Electrical characteristics 10.1 Absolute Maximum Ratings Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions given in the Recommended Operating Conditions section. Exposure to the Absolute Maximum Conditions for extended periods may affect device reliability. Table 10-1. Absolute Maximum Ratings Parameter Symbol Rating Supply Voltage VDDIO -0.5 to 4.0 Input Voltage VI -0.5 to VDDIO +0.5 (≤ 4.0V) Output Voltage VO -0.5 to VDDIO +0.5 ( 4us > 612us PLL INIT > 1.65us* ARST > 410us > 1.65us* > 0.9us SRST FULL OPERATION SYSTEM (*) 1.65us = 33*tclk 114 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 11. Mechanical Characteristics 11.1 LQFP80 Mechanical Characteristics Figure 11-1. 80 LQFP package dimensions Table 11-1. LQFP Package Reference JEDEC Drawing Reference Table 11-2. MS-026 LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 115 12. Recommended mounting conditions 12.1 Conditions of Standard Reflow Table 12-1. Conditions of Standard Reflow Items Method Times Floor Life Floor Life Condition Contents IR (Infrared Reflow) / Convection 2 Please use within 2 years after Before unpacking production From unpacking to second reflow Within 8 days Baking with 125ºC +/- 3ºC for 24hrs +2hrs/-0hrs is required. Then please In case over period of floor life use within 8 days (please remember baking is up to 2 times). Between 5ºC and 30ºC and also below 70% RH required. (It is preferred lower humidity in the required temp. range). Figure 12-1. LQFP80 package soldering profile Note: H rank: 260ºC Max a: Average ramp-up rate: 1ºC/s to 4ºC/s b: Preheat & Soak: 170ºC to 190ºC, 60s to 180s c: Average ramp-up rate: 1ºC/s to 4ºC/s d: Peak temperature: 260ºC Max, up to 255ºC within 10s d’: Liquidous temperature: Up to 230ºC within 40s or Up to 225ºC within 60s or Up to 220ºC within 80s e: Cooling: 116 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 Natural cooling or forced cooling 12.2 Manual Soldering Table 12-2. Manual Soldering Items Contents Before unpacking Please use production From unpacking to Manual Soldering Within 2 years after production (No control required for moisture adsorption because it is partial heating) Floor life Floor life condition Solder Condition within 2 years after Between 5°C and 30°C and also below 70% RH required. (It is preferred lower humidity in the required temp. range). Temperature of soldering iron: Max 400°C, Time: Within 5 seconds/pin *Be careful for touching package body with iron ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 117 13. Ordering Information Table 13-1. Ordering Information Atmel Ordering Code ATPL230A-AKU-Y ATPL230A-AKU-R Package 80 LQFP 80 LQFP AT Atmel Designator AT = Atmel Product Family PL = Power Line Communications Device Designator Device Revision Package Type Pb-Free Pb-Free PL 230 A - A K U - X Temperature Range Industrial (-40ºC to 85ºC) Industrial (-40ºC to 85ºC) xx Customer marking xx = “ ” Shipping Carrier Option Y = Tray R = Tape and Reel Package Device Grade or Wafer/Die Thickness U = Lead free (Pb-free) Industrial temperature range (-40ºC to +85ºC) Package Option AK = 80 LQFP 118 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 14. Revision History In the table that follows, the most recent version of the document appears first. Doc Rev. Comments 43053 J Change Request Ref. Analog Front-End Figure 5-3 and Figure 5-5: updated. Analog Front-End Section 5.3 ”Zero-crossing detection”: updated. Peripheral Registers I Added the following registers: “Zero Crossing Configuration” and “Zero Crossing Filter” PRIME PHY Layer Added Section 9.3.7.2 ”Zero Crossing Configuration Register” and Section 9.3.7.3 ”Zero Crossing Filter Register”. H G Analog Front-End Section 5.2 ”ATPLCOUP reference designs” modified. Format changes according to new templates. Chapters order redefined. Deleted Section “Power Considerations”: the information of this section is in Section 3. ”Signal Description”. Modified Section 5. ”Analog Front-End” (was “PLC coupling circuitry description”). Changed “PRIME + Robust” by “PRIME v1.4”. F Electrical Characteristics Section 10.6 ”Oscillator” updated: modified Figure 10-5, added equation and information after the figure. Table 10-7 updated: added the values of CXTAL and CPARA20M . Modified the notes below the table. Ordering Information Table 13-1: added new Atmel Ordering Code “ATPL230A-AKU-R”. MAC Coprocessor E Removed the following registers: “0xFD53, 0xFD54, 0xFD55, 0xFD56, 0xFD5F, 0xFD60, 0xFD61 and 0xFD62”. Updated Section 8.3.3.3 ”BER HARD Average Error Registers”. Mechanical Characteristics Table 11-1,Table 11-2 added. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 119 Doc Rev. Comments 43053 Minor changes. Signal Description CLKOUT: “20 MHz CLK Output” changed to “10 MHz External Clock Output”. SPI Controller Chapter added. MAC Coprocessor D “Address: 0xFE62 - 0xFE67” changed to “Address: 0xFEBA (MSB) - 0xFEBB (LSB)” in Section 8.3.1.2 ”CRC32 Errors Counter Register”. PRIME PHY Layer “Reset: 0x000000” changed to “Reset: 0x00000000” in Section 9.3.3.9 ”Accumulated Header EVM Registers”. “Reset: 0x000000” changed to “Reset: 0x00000000” in Section 9.3.3.10 ”Accumulated Payload EVM Registers”. “Reset: 0x00000000” changed to “Reset: 0x000124F8” in Section 9.3.5.4 ”TX Timeout Registers”. “Reset: 0x0000” changed to “Reset: 0x1111” in Section 9.3.5.7 ”TX Result Register”. C 120 “GND” changed to “AGND” in the following pins: 62, 67, 72 and 73. Changed the description of “VDDIN AN” in Section 3. ”Signal Description”. B Update Package. A First Issue. ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 Change Request Ref. Table of Contents Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 4.2 80-Lead LQFP Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 80-Lead LQFP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5. Analog Front-End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 5.2 5.3 PLC coupling circuitry description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ATPLCOUP reference designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zero-crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. SPI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 6.2 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8. MAC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 8.2 8.3 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Advanced Encryption Standard (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MAC Coprocessor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9. PRIME PHY Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 9.2 9.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 PHY parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PHY Layer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.1 10.2 10.3 10.4 10.5 10.6 10.7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power On Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 107 108 109 112 112 114 11. Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.1 LQFP80 Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 12. Recommended mounting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.1 Conditions of Standard Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12.2 Manual Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 14. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 121 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2016 Atmel Corporation. / Rev.: Atmel-43053J-ATPL230A-Datasheet_22-Sep-16. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. 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Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.