ATR0601-PFQW86

Features • • • • • • • • Very Low Power Design (40 mW) Single IF Architecture Excellent Noise Performance 1.5-bit ADC On Chip Small QFN Package (4 mm × 4 mm, 24 pins) Highly integrated, Few External Components Advanced BiCMOS Technology (UHF6s) RoHS Compliant GPS Front-end IC 1. Description The ATR0601 is a single IF GPS front-end IC, designed to meet the requirements of mobile and automotive applications. Excellent RF performance combined with low noise figure enables high quality GPS solutions and it's very low power consumption fits perfectly to portable devices. Featuring a balanced XTO and a fully integrated balanced frequency synthesizer, only few external components are required. ATR0601 The ATR0601 offers a complete autonomous mode, utilizing the on chip AGC in closed loop operation, to set the gain of the IF VGA. Alternatively, in combination with the Antaris™4 baseband processor family, the optimum gain of the IF VGA can be computed and set by software, using the digital SDI interface. PUXTO PURF EGC AGCO NBPI BPI NBP BP VDIG VCC Block Diagram VCC Figure 1-1. SDI PMSS Logic ≥1 A D RF NRF A D VCO PLL SL SH SC XTO NXTO XTO X MO TEST GND NX 4866G–GPS–11/06 2. Pin Configuration Pinning QFN24 SC SH SL SDI EGC VCC Figure 2-1. 24 23 22 21 20 19 VDIG AGCO NXTO NX X XTO 1 2 3 4 5 6 Paddle GND 18 17 16 15 14 13 PURF PUXTO NBPI BPI NBP BP VCC MO TEST NRF RF NC 7 8 9 10 11 12 Table 2-1. Pin Symbol Type(1) Paddle GND S Common ground Digital supply Function 1 VDIG S 2 AGCO A_I/O 3 NXTO A_I XTO interface (optional: TCXO input) 4 NX A_O XTO interface 5 X A_O XTO interface 6 XTO A_I XTO interface (optional: TCXO input) 7 VCC S 8 MO A_O Testbuffer output (fIF) 9 TEST A_I Enable testbuffer 10 NRF A_I RF input complementary 11 RF A_I RF input 12 NC – 13 BP A_O IF-Filter interface (mixer output, open collector) 14 NBP A_O IF-Filter interface (mixer output complementary, open collector) 15 BPI A_I IF-Filter interface (IF-input) 16 NBPI A_I IF-Filter interface (IF-input complementary) 17 PUXTO D_I Power-up XTO 18 PURF D_I Power-up RF 19 VCC S Analog supply 20 EGC D_I Enable external gain control (high = external; low = internal) 21 SDI D_I Input for external gain control signal (Σ∆ modulation) AGC: gain control voltage output/corner frequency determination Analog supply Not connected 22 SL D_O Data output: “low” 23 SH D_O Data output: “high” 24 SC D_O Sample clock Note: 2 Pin Description 1. Type: A_I Analog input, A_O Analog output, D_I Digital input, D_O Digital output, S Supply ATR0601 4866G–GPS–11/06 ATR0601 3. Functional Description 3.1 General Description The ATR0601 GPS receiver IC has been especially designed for GPS applications in both mobile phone and automotive applications. From this system point of view, it incorporates highest isolation between GPS and cellular bands, as well as very low power consumption. The L1 input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a centre frequency of: fRF = 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a chip rate of 1.023 Mbps. As the input signal power at the antenna is approximately –140 dBm, the desired signal is below the thermal noise floor. 3.2 PMSS Logic The Power Management, Startup and Shutdown Logic ensures reliable operation within the recommended operating and timing conditions. The external power control signals PUrf and PUxto are passed thru Schmitt-trigger inputs, digital and analog supply voltages are analyzed by monitoring circuits. 3.3 XTO The XTO is designed for minimum phase noise and frequency perturbations. The balanced topology gives maximum isolation from external and ground coupled noise. The built-in jump start circuitry ensures reliable start-up behaviour of any specified crystal. For use with an external TCXO, the XTO circuitry can be used as a single-ended or balanced input buffer. The recommended reference frequency is: fXTO = 23.104 MHz. 3.4 VCO/PLL The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no external components are required. The VCO combines very good phase noise behaviour and excellent spurious suppression. The relation between the reference frequency (fXTO) and the VCO centre frequency (fVCO) is given by: fVCO = fXTO × 64 = 23.104 MHz × 64 = 1478.656 MHz. 3.5 RF-Mixer/Image-filter Combined with the antenna an external LNA provides a first band-pass filtering of the signal. For the LNA, Atmel’s ATR0610 is recommended, due to it’s low Noise Figure, high linearity an low power consumption. The output of the LNA drives an SAW filter, which provides image rejection for the mixer and the required isolation of all GSM bands. The output of the SAW filter is fed into a highly linear mixer with high conversion gain and excellent noise performance. The IF frequency (fIF) is given by: fIF = fRF – fVCO = 1575.42 MHz – 1478.656 MHz = 96.764 MHz. 3.6 IF-filter The mixer directly drives an external LC band-pass filter via open collector outputs. In order to provide highest selectivity and conversion gain, it is recommended to design the external filter, according to the application proposal, as a 2-pole filter with a quality factor Q > 25. 3 4866G–GPS–11/06 3.7 VGA/AGC The output of the IF-Filter drives an on-chip Variable Gain Amplifier (VGA) which is combined with additional low-pass filtering. The on-chip Automatic Gain Control (AGC) stage sets the gain of the VGA in order to optimally charge the input of the following analog-to-digital converter. The AGC control loop can be selected for on-chip closed loop operation or for external gain control mode. For external gain control mode, the loop needs to be closed by the baseband IC ATR0621. 3.8 A/D Converter The analog-to-digital converter stage has a total resolution of 1.5 bit. It comprises balanced comparators and a sub sampling unit, clocked by the reference frequency (fXTO). The frequency spectrum of the digital output signal (fOUT), present at the data outputs SL and SH, is then given by: fOUT = ⏐ fIF – fXTO × n⏐ . The selected sub sampling factor (n = 4) leads to the designated digital output signal, with a centre frequency given by: fOUT = fIF – fXTO × 4 = 96.764 MHz – 23.104 MHz – 4 = 4.348 MHz. 3.9 Clock and Data Driver CMOS output drivers are providing 1.5 bit data (SH, SL) and the system clock (SC). The rail-to-rail output signal level is determined by the digital supply voltage (VDIG). 4 ATR0601 4866G–GPS–11/06 ATR0601 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Analog supply voltage VCC –0.3 to +3.7 V Digital supply voltage VDIG –0.3 to +3.7 V Vin –0.3 to +3.7 V Input voltage Operating temperature Top –40 to +85 °C Storage temperature Tstg –55 to +125 °C Symbol Value Unit Rth 125 K/W 5. Thermal Resistance Parameters Junction ambient 6. Operating Range Parameters Symbol Value Unit Analog supply voltage VCC 2.70 to 3.30 V Digital supply voltage VDIG 1.65 to 2.00 V V∆ ≥ 0.80 V Temp –40 to +85 °C Input frequency fRF 1575.42 MHz Reference frequency fXTO 23.104 MHz Supply voltage difference (V∆ = VCC – VDIG) Temperature range 7. ESD Characteristics Parameters Symbol Norm Value Unit ESD level HBM (Human Body Model) VHBM ANSI/ESD STM.5.1-2001 2500 V ESD level MM (Machine Machine Model) VMM EIA/JESD22 A115 A 250 V ESD level CDM (Charged Device Model) VCDM ESD STM.5.3.1-1999 1250 V 8. Electrical Characteristics No. 1 1.1 Parameters Test Conditions Pin Symbol VPUxto = VPUrf = VPU,on 7, 19 IS VPUxto = VPUrf = VPU,on 1 7, 19 Min. Typ. Max. Unit Type* 14.2 mA A IDIG 700 µA A IS_XTO 2.9 mA A Common Analog supply current(1) (1),(2) 1.2 Digital supply current 1.3 Analog supply current in XTO mode(1) VPUxto = VPU,on, VPUrf = VPU,off *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Conditions: VCC = 2.7V; VDIG = 1.65V; Temperature = 27°C 2. Capacitive load (CL = 3.3 pF) at pins 22, 23, 24 3. Capacitive load (CL = 3.3 pF) at pin 24 5 4866G–GPS–11/06 8. Electrical Characteristics (Continued) No. Parameters Test Conditions 1.4 Digital supply current in XTO mode(1),(3) VPUxto = VPU,on, VPUrf = VPU,off 1.5 Supply current in power down mode(1) VPUxto = VPUrf = VPU,off 1.6 Maximum total gain VAGCO = 2.2V 1.7 2 Pin Symbol 1 IDIG_XTO 1, 7, 19 IPD Min. Max. 500 2 Gmax_tot Noise figure (SSB) Typ. 90 6.8 NFtot Unit Type* µA A µA A dB B dB C Mixer 2.1 Output frequency fXTO = 23.104 MHz 13, 14 fIF 96.764 MHz A 2.2 Input impedance (balanced) fRF = 1575.42 MHz 10, 11 Z11 10-j80 Ω C 2.3 Conversion Gain Recommended IF-filter 8 GMIX 20 dB B 2.4 Noise figure (SSB) 8 NFMIX 5.8 dB C 3 VGA/AGC 3.1 Minimum gain VAGCO = 1.0V GVGA,min 0 dB B 3.2 Maximum gain VAGCO = 2.2V GVGA,max 70 dB B 3.3 Control-voltage sensitivity VAGCO = 2.2V NVGA,min 6.6 dB/V D VAGCO = 1.0V NVGA,max 150 dB/V D 3.4 AGC cut-off frequency Cext = open 2 f3dB_AGC 250 kHz D 3.5 AGC cut-off frequency Cext = 100 pF 2 f3dB_AGC 33 kHz D 3.6 Gain-control output voltage 2 VAGCO V B 4 0.9 2.3 Reference Oscillator 4.1 XTO phase noise at 100 Hz With specified crystal 24 Pn100 –80 dBc/Hz C 4.2 XTO phase noise at 1 kHz With specified crystal 24 Pn1k –100 dBc/Hz C 5 Clock and Data Driver 5.1 Clock driver frequency fXTO = 23.104 MHz 24 fCLK 23.104 MHz A 5.2 Clock output level Cload,max = 10 pF 24 VCLK,high 0.9 × VDIG V B 5.3 Clock output level Cload.max = 10 pF 24 VCLK,low 0.1 × VDIG V B 5.4 Data output level Cload,max = 10 pF 22, 23 VData,high 0.9 × VDIG V B 5.5 Data output level Cload,max = 10 pF 22, 23 VData,low 0.1 × VDIG V B V A V A 6 PMSS 6.1 Voltage level power-on 17, 18 VPU,on 6.2 Voltage level power-off 17, 18 VPU,off 1.3 0.5 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Conditions: VCC = 2.7V; VDIG = 1.65V; Temperature = 27°C 2. Capacitive load (CL = 3.3 pF) at pins 22, 23, 24 3. Capacitive load (CL = 3.3 pF) at pin 24 6 ATR0601 4866G–GPS–11/06 ATR0601 9. Timing Figure 9-1. Recommended Power-up/down Sequence VCC VDIG PUxto PUrf tmin = 0s Figure 9-2. tmin = 0s tmin = 0s tmin = 5ms tmin = 0s tmin=0s tmin = 0s Recommended Sleep-mode Sequence VCC VDIG PUxto PUrf tmin = 0s Figure 9-3. tmin = 4 µs tmin = 0s Recommended XTO Start-up/Shut-down Sequence VCC VDIG PUxto tmin = 1 ms Figure 9-4. tmin = 4 µs Sample Clock Start-up Delay VCC VDIG PUxto SC tmax = 500 µs T = 1/23.104 MHz 7 4866G–GPS–11/06 Figure 9-5. Synchronous Shut-down Behavior of SC with Respect to PUxto VCC VDIG PUxto SC T = 1/23.104 MHz tmin = 0s tmax = 25ns Figure 9-6. tmax = 0s Data Outputs SL and SH are Valid with Rising Edge of Sample Clock SC SL SH SC T = 1/23.104 MHz 8 ATR0601 4866G–GPS–11/06 ATR0601 10. Application Circuit 68 VDIG PU RF EGC 20 100pF AGCO 2 NBPI 16 5pF BPI 15 BP 13 VDIG 1 VCC 19 VCC 7 VCC PU RF PU XTO NBP 14 5pF 100nF 220nH 100nF 220nH 220nH 100nF 4.7nF 220nH VCC VCC VCC Figure 10-1. Application Example Using a GPS Crystal with ESRtyp = 12Ω (Please see Table 10-1 on page 11) SDI 21 17 PUxto 18 PUrf PMSS Logic ≥1 10nF 1.3pF 47pF 4.7nH SL 22 A 11 RF D Data out "low" 5.6nH 1.5pF ATR0610 SAW B4060 1.3pF LNA section (opt.) SH 23 A 10 NRF D VCO PLL 6 XTO SC 24 Data out "high" Sample clock 3 NXTO 4 NX 47pF Reference frequency: Application #1 Note: 12 NC X1 XTO 5 X 8 MO 82pF 9 TEST 27 GND 47pF Please consider the recommended IF-filter layout, shown in Figure 10-5 on page 11. Figure 10-2. Application Example Using a GPS Crystal with ESRtyp ≈ 12Ω (Please see Table 10-2 on page 12) 6 XTO 3 NXTO 47pF 5 R1 X 82pF 4 NX X1 47pF Reference frequency: Application #2 Note: The external series resistor R1 has to be selected depending on the typical value of the crystal ESR. Please refer to Application Note “ATR0601: Crystal and TXCO selection”. 9 4866G–GPS–11/06 Figure 10-3. Equivalent Application Examples Using a GPS TCXO (Please see Table 10-3 on page 12) 22 pF 6 XTO 12 pF 3 TCXO NXTO 4.7 pF 5 X Do not 4 connect NX Reference frequency: Application #4a 6 12 pF XTO 22 pF 3 TCXO NXTO 4.7 pF 5 X Do not 4 connect NX Reference frequency: Application #4b Figure 10-4. Application Example Using an External Reference and Balanced Inputs (Please see Table 10-4 on page 12) 1:1 6 XTO Vin 3 NXTO 5 Do not connect X 4 NX Reference frequency: Application #5 10 ATR0601 4866G–GPS–11/06 ATR0601 Figure 10-5. Recommended IF-filter: Layout versus Schematic 13 14 15 16 Lc NBP BPI NBPI Cb BP Ca 13 14 15 16 Ld B Le Cb Ca Lc Ld Le Lf Lf A 4.7nF 68 VCC Note: Mutual inductance between the four inductors Lc - Lf plays an important role in the IF-filter characteristics. In any design, the layout arrangement shown in Figure 10-5 on page 11 should be resembled as close as possible. Measures: A = 2.8 mm; B = 1.4 mm; Lc - Lf: Wirewound SMD inductors, 0603 size. (Please see Table 11-1). Table 10-1. Specification of GPS Crystals Appropriate for the Application Example Shown in Figure 10-1 on page 9 Parameter Comment Min. Typ. Max. Units Frequency Characteristics Fundamental Frequency Nominal frequency referenced to 25°C Calibration tolerance Frequency at 23°C ±2°C Frequency deviation Over operating temperature range Temperature range Operating temperature range 23.104 MHz 7.0 ±ppm 15.0 ±ppm –40.0 +85.0 °C 18.5 19.5 pF 23 Ω Electrical Load capacitance (CL) Equivalent Series Resistance (ESR) Fundamental Specification 7 12 11 4866G–GPS–11/06 Table 10-2. Specification of GPS Crystals Appropriate for the Application Example Shown in Figure 10-2 on page 9 Parameter Comment Min. Typ. Max. Units 40 Ω Equivalent Series Resistance (ESR) Fundamental Note: Specification 7 All other parameters as specified in Table 10-1. Table 10-3. Specification of GPS TCXOs Appropriate for the Application Example Shown in Figure 10-3 on page 10 (For Baseband with SuperSense™ Software) Parameter Comment Min. Typ. Max. Units Frequency Characteristics Nominal Frequency Nominal frequency referenced to 25°C 23.104 MHz Over operating temperature range 0.5 ±ppm Frequency deviation Including calibration, temperature, soldering and ageing effects 8 ±ppm Temperature range Operating temperature range –40.0 +85.0 °C 1.5 V Electrical Output waveform DC coupled clipped sinewave Output voltage (peak-to-peak) Operating range 0.8 Output load capacitance Tolerable load capacitance 10 Table 10-4. pF Specification of an External Reference Signal for the Application Example Shown in Figure 10-4 on page 10 Parameter Comment Min. Typ. Max. Units Signal Characteristics Nominal Frequency 12 23.104 Waveform Sinewave or clipped sinewave Amplitude Voltage peak-to-peak 0.6 0.9 MHz 1.2 V ATR0601 4866G–GPS–11/06 ATR0601 11. Demonstration Board Figure 11-1. Schematic of Demonstration Board R8 VCC C23 L3 L5 L4 C22 C21 13 14 BP 15 2 NBPI 1 C3 C10 16 BPI NBP J3 P1 L6 8 2 MO AGCO VDD1.8 20 EGC 21 C7 J2 NIN 1 2 3 NOUT R1 9 TEST 23 11 RF 1 P2 IN OUT 2 C15 10 5 XTO NXTO 6 3 C5 VDD1.8 1 2 3 C1 19 7 1 2 J4 NX 4 NC 12 PURF PUXTO 18 17 C6 J1 X1 C4 VCC J6 24 R7 FB1 VCC 1 2 SC X VCC J5 22 SL NRF FI1 1 2 SH L2 6 P4 SDI C17 5 1 2 3 VDD1.8 1 2 3 J8 1 2 3 J9 VDIG 1 FB2 C2 C19 C9 C8 13 4866G–GPS–11/06 Figure 11-2. Illustration of Demonstration Board Table 11-1. Qty Value Device Parts Tolerance Manufacturer ® Mfr. Order Code 90120-0762 4 JP2E J3, J4, J5, J6 Molex 5 JP3E J1, J2, J7, J8, J9 Molex 90120-0763 Vishay® CRCW0402000Z Vishay CRCW040268RJ 1 0 RESISTOR-0402 R1 1 68Ω RESISTOR-0402 R8 5% 1 2n2 CAPACITOR-0402 C3 5% Vishay VJ0402Y222JXJA 2 1p3 CAPACITOR-0402 C15, C17 0.1 pF Taiyo Yuden® EVK105CH1R3BW 1 5n6 2% Multilayer 2 5p0 ±0p1 2 10µ 1 4.7n 1 ® INDUCTOR-0402 L2 2% Würth Elektronik CAPACITOR-0402 C21, C22 ±0p1 Yageo America 0402CG509C9B200 ELKO-B C1, C2 20% Vishay 293D106X0016B2 CAPACITOR-0402 C23 5% Vishay VJ0402Y472JXJA 27 RESISTOR-0402 R7 5% Vishay CRCW040227RJ 2 47p CAPACITOR-0402 C5, C6 5% Vishay VJ0402A470JXXA. 1 82p CAPACITOR-0402 C4 Vishay VJ0402A820JXXA 4 100n CAPACITOR-0402 C7, C8, C9, C19 5% Vishay VJ0402V104JXJ 1 100p CAPACITOR-0402 C10 5% Vishay VJ0402A101JXXA. Johnson Components™ 142-0711-841 3 4 14 BOM of Demonstration Board 142-0711-841 COAX-SMA 220n 2% INDUCTOR_WIREWOUND-0603 P1, P2, P4 L3, L4, L5, L6 2% 744784056G Würth Elektronik 744761222G 2 74279266 FERRITE_BEAD-0603 FB1, FB2 Würth Elektronik 74279266 1 ATR0601-1 ATR0601-1 IC1 Atmel® 1 B4060 1 RSX-5 23.104 MHz ® FILTER-BALANCED FI1 Epcos XTAL-4PIN-6035 X1 Rakon ATR0601 B4060 XZC736 IEC19RSX-5 23.104 MHz ATR0601 4866G–GPS–11/06 ATR0601 12. Recommended Footprint Figure 12-1. Recommended Footprint (QFN24 - 4 mm × 4 mm) 15 4866G–GPS–11/06 13. Ordering Information Extended Type Number Package Remarks QFN24, 4 × 4 ATR0601-PFQW Taped and reeled, Pb-free, RoHS compliant 14. Package Information Package: QFN 24 - 4 x 4 Exposed pad 2.6 x 2.6 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances±0.05 4 0.9±0.1 +0 2.6 0.05-0.05 24 19 1 24 1 0.4 18 13 6 6 0.25 12 technical drawings according to DIN specifications 7 0.5 nom. 0.2 2.5 Drawing-No.: 6.543-5101.02-4 Issue: 2; 29.11.05 Moisture sensitivity level (MSL) = 2 16 ATR0601 4866G–GPS–11/06 ATR0601 15. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4866G-GPS-11/06 • Figure 10-1 “Application Example Using a GPS Crystal with ESRtyp = 12Ω” on page 9 changed” 4866F-GPS-06/06 • Figure 10-3 “Equivalent Application Examples Using a GPS TCXO” on page 10 changed • Table 10-3 “Specification of GPS TCXOs Appropriate for the Application Example” on page 12 changed • Table 10-4 “Specification of an External Reference Signal for the Application Example” on page 12 changed. 17 4866G–GPS–11/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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