Features
• Core
•
•
•
•
•
•
•
– ARM® Cortex®-M3 revision 2.0 running at up to 48 MHz
– Thumb®-2 instruction
– 24-bit SysTick Counter
– Nested Vector Interrupt Controller
Pin-to-pin compatible with SAM7S legacy products (48- and 64-pin versions) and
SAM3S (48-, 64- and 100-pin versions)
Memories
– From 16 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,
single plane
– From 4 to 24 Kbytes embedded SRAM
– 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines
System
– Embedded voltage regulator for single supply operation
– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe
operation
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure
Detection and optional low power 32.768 kHz for RTC or device clock
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default
frequency for device startup. In-application trimming access for frequency
adjustment
– Slow Clock Internal RC oscillator as permanent low-power mode device clock
– One PLL up to 130 MHz for device clock
– Up to 10 peripheral DMA (PDC) channels
Low Power Modes
– Sleep and Backup modes, down to 3 µA in Backup mode
– Ultra low power RTC
Peripherals
– Up to 2 USARTs with RS-485 and SPI mode support. One USART (USART0) has
ISO7816, IrDA® and PDC support in addition
– Two 2-wire UARTs
– 2 Two Wire Interface (I2C compatible), 1 SPI
– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and
PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for
Stepper Motor
– 4-channel 16-bit PWM
– 32-bit Real-time Timer and RTC with calendar and alarm features
– Up to 16 channels, 384 KSPS 10-bit ADC
– One 500 KSPS 10-bit DAC
I/O
– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Three 32-bit Parallel Input/Output Controllers
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm
– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm
– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm
AT91SAM
ARM-based
Flash MCU
SAM3N Series
Summary
11011BS–ATARM–22-Feb-12
1. SAM3N Description
Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz
and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set
includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose
16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC.
The SAM3N series is ready for capacitive touch thanks to the QTouch library, offering an easy
way to implement buttons, wheels and sliders.
The SAM3N device is an entry-level general purpose microcontroller. That makes the SAM3N
the ideal starting point to move from 8- /16-bit to 32-bit microcontrollers.
It operates from 1.62V to 3.6V and is available in 48-pin, 64-pin and 100-pin QFP, 48-pin and
64-pin QFN, and 100-pin BGA packages.
The SAM3N series is the ideal migration path from the SAM3S for applications that require a
reduced BOM cost. The SAM3N series is pin-to-pin compatible with the SAM3S series. Its
aggressive price point and high level of integration pushes its scope of use far into cost-sensitive, high-volume applications.
2
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
1.1
Configuration Summary
The SAM3N4/2/1/0/00 differ in memory size, package and features list. Table 1-1 summarizes
the configurations of the 9 devices.
Table 1-1.
Configuration Summary
Device
SAM3N4A
SAM3N4B
SAM3N4C
SAM3N2A
SAM3N2B
SAM3N2C
SAM3N1A
SAM3N1B
SAM3N1C
SAM3N0A
SAM3N0B
SAM3N0C
SAM3N00A
SAM3N00B
Flash
256 Kbytes
256 Kbytes
256 Kbytes
128 Kbytes
128 Kbytes
128 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
SRAM
Package
Number
of PIOs
ADC
Timer
24 Kbytes
LQFP48
QFN48
34
8 channels
6(1)
24 Kbytes
LQFP64
QFN64
47
10 channels
6(2)
24 Kbytes
LQFP100
BGA100
79
16 channels
6
16 Kbytes
LQFP48
QFN48
34
8 channels
6(1)
16 Kbytes
LQFP64
QFN64
47
10 channels
6((2)
16 Kbytes
LQFP100
BGA100
79
16 channels
6
8 Kbytes
LQFP48
QFN48
34
8 channels
6(1)
8 Kbytes
LQFP64
QFN64
47
10 channels
6(2)
8 Kbytes
LQFP100
BGA100
79
16 channels
6
8 Kbytes
LQFP48
QFN48
34
8 channels
6(1)
8 Kbytes
LQFP64
QFN64
47
10 channels
6(2)
8 Kbytes
LQFP100
BGA100
79
16 channels
6
4 KBytes
LQFP48
QFN48
34
8 channels
6(1)
4 KBytes
LQFP64
QFN64
47
10 channels
6(2)
PDC
Channels
USART
DAC
8
1
_
10
2
1
10
2
1
8
1
_
10
2
1
10
2
1
8
1
_
10
2
1
10
2
1
8
1
_
10
2
1
10
2
1
8
1
_
10
2
1
Notes:
1. Only two TC channels are accessible through the PIO.
2. Only three TC channels are accessible through the PIO.
3
11011BS–ATARM–22-Feb-12
2. SAM3N Block Diagram
Figure 2-1.
SAM3N 100-pin version Block Diagram
TST
PCK0-PCK2
XIN
XOUT
System Controller
PMC
JTAG & Serial Wire
OSC
3-20 MHz
In-Circuit Emulator
WDT
RC OSC
12/8/4 MHz
XIN32
XOUT32
ERASE
Voltage
Regulator
SM
FLASH
OSC 32k
I/D
RC 32k
24-bit
SysTick Counter N
V
Cortex-M3 Processor
I
Fmax 48 MHz
C
SUPC
PLL
SRAM
256 KBytes
128 KBytes
64 KBytes
24 KBytes
16 KBytes
8 KBytes
ROM
16 KBytes
S
3- layer AHB Bus Matrix Fmax 48 MHz
RTT
RTC
POR
VDDIO
NRST
RSTC
PIOA
Peripheral
Bridge
PIOB
PIOC
VDDCORE
URXD0
UTXD0
UART0
URXD1
UTXD1
UART1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
Timer Counter A
TC[0..2]
PDC
TIOA[0:2]
TIOB[0:2]
USART0
PDC
TCLK[0:2]
Timer Counter B
TCLK[3:5]
TC[3..5]
TIOA[3:5]
TIOB[3:5]
USART1
PDC
ADTRG
AD[0..15]
SPI
PWM
PWM[0:3]
10-bit ADC
PDC
ADVREF
DAC0
PDC
TWI0
TWI1
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
TWCK1
TWD1
10-bit DAC
DATRG
PDC
4
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Figure 2-2.
SAM3N 64-pin version Block Diagram
TST
PCK0-PCK2
System Controller
Voltage
Regulator
PMC
JTAG & Serial Wire
XIN
XOUT
OSC
3-20 MHz
In-Circuit Emulator
WDT
RC OSC
12/8/4 MHz
ERASE
I/D
RC 32k
FLASH
OSC 32k
24-bit
SysTick Counter N
V
Cortex-M3 Processor
I
Fmax 48 MHz
C
SM
SUPC
XIN32
XOUT32
PLL
SRAM
256 KBytes
128 KBytes
64 KBytes
24 KBytes
16 KBytes
8 KBytes
ROM
16 KBytes
S
3-layer
Matrix
48 Fmax
MHz 48 MHz
3- AHB
layerBus
AHB
Matrix
BusFmax
RTT
RTC
POR
VDDIO
NRST
RSTC
PIOA
Peripheral
Bridge
PIOB
VDDCORE
URXD0
UTXD0
UART0
URXD1
UTXD1
UART1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
Timer Counter A
TC[0..2]
PDC
PDC
Timer Counter B
USART0
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
TC[3..5]
USART1
ADTRG
AD[0..9]
SPI
PWM
PWM[0:3]
10-bit ADC
PDC
ADVREF
DAC0
PDC
PDC
TWI0
TWI1
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
TWCK1
TWD1
10-bit DAC
DATRG
PDC
5
11011BS–ATARM–22-Feb-12
Figure 2-3.
SAM3N 48-pin version Block Diagramz
TST
PCK0-PCK2
XIN
XOUT
System Controller
PMC
JTAG & Serial Wire
OSC
3-20 MHz
In-Circuit Emulator
WDT
RC OSC
12/8/4 MHz
XIN32
XOUT32
ERASE
SUPC
OSC 32k
24-bit
SysTick Counter N
V
Cortex-M3 Processor
I
Fmax 48 MHz
C
SM
I/D
RC 32k
Voltage
Regulator
FLASH
256 KBytes
128 KBytes
64 KBytes
32 KBytes
16 KBytes
SRAM
24 KBytes
16 KBytes
8 KBytes
4 KBytes
ROM
16 KBytes
S
3-layer
Matrix
48Fmax
MHz 48 MHz
3- AHB
layerBus
AHB
BusFmax
Matrix
PLL
RTT
RTC
POR
VDDIO
NRST
RSTC
PIOA
Peripheral
Bridge
PIOB
VDDCORE
URXD0
UTXD0
UART0
URXD1
UTXD1
UART1
Timer Counter A
TC[0..1]
PDC
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
TCLK[0..1]
TIOA[0..1]
TIOB[0..1]
Timer Counter B
TC[3..5]
PDC
PDC
ADTRG
AD[0..7]
SPI
PWM
PWM[0:3]
10-bit ADC
ADVREF
PDC
PDC
TWI0
TWI1
6
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
TWCK1
TWD1
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1.
Signal Description List
Signal Name
Function
Active
Level
Type
Voltage
Reference
Comments
Power Supplies
VDDIO
Peripherals I/O Lines Power Supply
1.8V Output
Power
1.65 V to 1.95V
1.65V to 1.95V
Connected externally
to VDDOUT
VDDOUT
Voltage Regulator Output
Oscillator and PLL Power Supply
VDDCORE
Power the core, the embedded memories
and the peripherals
GND
Ground
1.62V to 3.6V
Power
Power
Voltage Regulator, ADC and DAC Power
Supply
VDDPLL
VDDIN
Power
Power
Ground
1.8V to 3.6V(3)
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
XOUT
Main Oscillator Output
XIN32
XOUT32
PCK0 - PCK2
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Input
Output
Input
Output
Programmable Clock Output
Reset State:
- PIO Input
- Internal Pull-up
disabled
- Schmitt Trigger
enabled(1)
VDDIO
Reset State:
- PIO Input
- Internal Pull-up
enabled
- Schmitt Trigger
enabled(1)
Output
ICE and JTAG
TCK/SWCLK
Test Clock/Serial Wire Clock
Input
TDI
Test Data In
Input
TDO/TRACESWO
Test Data Out/Trace Asynchronous Data
Out
TMS/SWDIO
Test Mode Select /Serial Wire
Input/Output
JTAGSEL
JTAG Selection
Output
Input / I/O
Input
High
VDDIO
Reset State:
- SWJ-DP Mode
- Internal pull-up
disabled
- Schmitt Trigger
enabled(1)
Permanent Internal
pull-down
7
11011BS–ATARM–22-Feb-12
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Active
Level
Type
Voltage
Reference
Comments
Flash Memory
ERASE
Flash and NVM Configuration Bits Erase
Command
Input
Reset State:
- Erase Input
- Internal pull-down
enabled
- Schmitt Trigger
enabled(1)
High
VDDIO
Reset/Test
NRST
TST
Microcontroller Reset
I/O
Test Mode Select
Input
Low
VDDIO
Permanent Internal
pull-up
VDDIO
Permanent Internal
pull-down
Universal Asynchronous Receiver Transceiver - UARTx
URXDx
UART Receive Data
Input
UTXDx
UART Transmit Data
Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31
PB0 - PB14
PC0 - PC31
Parallel IO Controller A
I/O
Parallel IO Controller B
I/O
Parallel IO Controller C
Reset State:
- PIO or System
IOs(2)
- Internal pull-up
enabled
- Schmitt Trigger
enabled(1)
VDDIO
I/O
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
Output
CTSx
USARTx Clear To Send
Input
Input
Timer/Counter - TC
TCLKx
TC Channel x External Clock Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PWMx
8
PWM Waveform Output for channel x
Output
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Active
Level
Type
Voltage
Reference
Comments
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
I/O
MOSI
Master Out Slave In
I/O
SPCK
SPI Serial Clock
I/O
SPI Peripheral Chip Select 0
I/O
Low
Output
Low
SPI_NPCS0
SPI_NPCS1 SPI_NPCS3
SPI Peripheral Chip Select
Two-Wire Interface- TWIx
TWDx
TWIx Two-wire Serial Data
I/O
TWCKx
TWIx Two-wire Serial Clock
I/O
Analog
Analog
ADVREF
ADC and DAC Reference
10-bit Analog-to-Digital Converter - ADC
AD0 - AD15
Analog Inputs
ADTRG
ADC Trigger
Analog
Input
VDDIO
Digital-to-Analog Converter Controller- DACC
DAC0
DACC channel analog output
DATRG
DACC Trigger
Analog
Input
VDDIO
Fast Flash Programming Interface
PGMEN0-PGMEN2
Programming Enabling
Input
PGMM0-PGMM3
Programming Mode
Input
PGMD0-PGMD15
Programming Data
I/O
PGMRDY
Programming Ready
Output
High
PGMNVALID
Data Direction
Output
Low
PGMNOE
Programming Read
Input
Low
PGMCK
Programming Clock
Input
PGMNCMD
Programming Command
Input
VDDIO
Low
Notes:
1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System IOs.
3. See Section 5.3 “Typical Powering Schematics” for restriction on voltage range of Analog Cells.
9
11011BS–ATARM–22-Feb-12
4. Package and Pinout
SAM3N4/2/1/0/00 series is pin-to-pin compatible with SAM3S products. Furthermore
SAM3N4/2/1/0/00 devices have new functionalities referenced in italic inTable 4-1, Table 4-3
and Table 4-4.
4.1
SAM3N4/2/1/0/00C Package and Pinout
4.1.1
100-lead LQFP Package Outline
Figure 4-1.
Orientation of the 100-lead LQFP Package
75
51
76
50
100
26
1
25
4.1.2
100-ball TFBGA Package Outline
The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its
dimensions are 9 x 9 x 1.1 mm.
Figure 4-2.
Orientation of the 100-ball TFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K
BALL A1
1
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
4.1.3
100-Lead LQFP Pinout
Table 4-1.
100-lead LQFP SAM3N4/2/1/0/00C Pinout
1
ADVREF
26
GND
51
TDI/PB4
76
TDO/TRACESWO/PB5
2
GND
27
VDDIO
52
PA6/PGMNOE
77
JTAGSEL
3
PB0/AD4
28
PA16/PGMD4
53
PA5/PGMRDY
78
PC18
4
PC29/AD13
29
PC7
54
PC28
79
TMS/SWDIO/PB6
5
PB1/AD5
30
PA15/PGMD3
55
PA4/PGMNCMD
80
PC19
6
PC30/AD14
31
PA14/PGMD2
56
VDDCORE
81
PA31
7
PB2/AD6
32
PC6
57
PA27
82
PC20
8
PC31/AD15
33
PA13/PGMD1
58
PC8
83
TCK/SWCLK/PB7
9
PB3/AD7
34
PA24
59
PA28
84
PC21
10
VDDIN
35
PC5
60
NRST
85
VDDCORE
11
VDDOUT
36
VDDCORE
61
TST
86
PC22
12
PA17/PGMD5/AD0
37
PC4
62
PC9
87
ERASE/PB12
13
PC26
38
PA25
63
PA29
88
PB10
14
PA18/PGMD6/AD1
39
PA26
64
PA30
89
PB11
15
PA21/AD8
40
PC3
65
PC10
90
PC23
16
VDDCORE
41
PA12/PGMD0
66
PA3
91
VDDIO
17
PC27
42
PA11/PGMM3
67
PA2/PGMEN2
92
PC24
18
PA19/PGMD7/AD2
43
PC2
68
PC11
93
PB13/DAC0
19
PC15/AD11
44
PA10/PGMM2
69
VDDIO
94
PC25
20
PA22/AD9
45
GND
70
GND
95
GND
21
PC13/AD10
46
PA9/PGMM1
71
PC14
96
PB8/XOUT
47
PC1
72
PA1/PGMEN1
22
23
24
25
PA23
PC12/AD12
PA20/AD3
PC0
48
PA8/XOUT32/
PGMM0
73
PC16
49
PA7/XIN32/
PGMNVALID
74
PA0/PGMEN0
50
VDDIO
75
PC17
97
98
99
100
PB9/PGMCK/XIN
VDDIO
PB14
VDDPLL
11
11011BS–ATARM–22-Feb-12
4.1.4
100-ball TFBGA Pinout
Table 4-2.
100-ball TFBGA SAM3N4/2/1/0/00C Pinout
A1
PB1
C6
PB7
F1
PA18
H6
PC4
A2
PC29
C7
PC16
F2
PC26
H7
PA11
A3
VDDIO
C8
PA1
F3
VDDOUT
H8
PC1
A4
PB9
C9
PC17
F4
GND
H9
PA6
A5
PB8
C10
PA0
F5
VDDIO
H10
PB4
A6
PB13
D1
PB3
F6
PA27
J1
PC15
A7
PB11
D2
PB0
F7
PC8
J2
PC0
A8
PB10
D3
PC24
F8
PA28
J3
PA16
A9
PB6
D4
PC22
F9
TST
J4
PC6
A10
JTAGSEL
D5
GND
F10
PC9
J5
PA24
B1
PC30
D6
GND
G1
PA21
J6
PA25
B2
ADVREF
D7
VDDCORE
G2
PC27
J7
PA10
B3
GNDANA
D8
PA2
G3
PA15
J8
GND
B4
PB14
D9
PC11
G4
VDDCORE
J9
VDDCORE
B5
PC21
D10
PC14
G5
VDDCORE
J10
VDDIO
B6
PC20
E1
PA17
G6
PA26
K1
PA22
B7
PA31
E2
PC31
G7
PA12
K2
PC13
B8
PC19
E3
VDDIN
G8
PC28
K3
PC12
B9
PC18
E4
GND
G9
PA4
K4
PA20
B10
PB5
E5
GND
G10
PA5
K5
PC5
C1
PB2
E6
NRST
H1
PA19
K6
PC3
C2
VDDPLL
E7
PA29
H2
PA23
K7
PC2
C3
PC25
E8
PA30
H3
PC7
K8
PA9
C4
PC23
E9
PC10
H4
PA14
K9
PA8
C5
PB12
E10
PA3
H5
PA13
K10
PA7
1
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
4.2
SAM3N4/2/1/0/00B Package and Pinout
Figure 4-3.
Orientation of the 64-pad QFN Package
64
49
1
48
16
33
17
TOP VIEW
32
Figure 4-4.
Orientation of the 64-lead LQFP Package
48
33
49
32
64
17
1
16
13
11011BS–ATARM–22-Feb-12
4.2.1
64-Lead LQFP and QFN Pinout
64-pin version SAM3N devices are pin-to-pin compatible with SAM3S products. Furthermore,
SAM3N products have new functionalities shown in italic in Table 4-3.
Table 4-3.
64-pin SAM3N4/2/1/0/00B Pinout
1
ADVREF
17
GND
33
TDI/PB4
49
TDO/TRACESWO/PB5
2
GND
18
VDDIO
34
PA6/PGMNOE
50
JTAGSEL
3
PB0/AD4
19
PA16/PGMD4
35
PA5/PGMRDY
51
TMS/SWDIO/PB6
4
PB1AD5
20
PA15/PGMD3
36
PA4/PGMNCMD
52
PA31
5
PB2/AD6
21
PA14/PGMD2
37
PA27/PGMD15
53
TCK/SWCLK/PB7
6
PB3/AD7
22
PA13/PGMD1
38
PA28
54
VDDCORE
7
VDDIN
23
PA24/PGMD12
39
NRST
55
ERASE/PB12
8
VDDOUT
24
VDDCORE
40
TST
56
PB10
9
PA17/PGMD5/AD0
25
PA25/PGMD13
41
PA29
57
PB11
10
PA18/PGMD6/AD1
26
PA26/PGMD14
42
PA30
58
VDDIO
11
PA21/PGMD9/AD8
27
PA12/PGMD0
43
PA3
59
PB13/DAC0
12
VDDCORE
28
PA11/PGMM3
44
PA2/PGMEN2
60
GND
13
PA19/PGMD7/AD2
29
PA10/PGMM2
45
VDDIO
61
XOUT/PB8
30
PA9/PGMM1
46
GND
14
15
16
Note:
1
PA22/PGMD10/AD9
PA23/PGMD11
PA20/PGMD8/AD3
31
PA8/XOUT32/PGMM
0
47
PA1/PGMEN1
32
PA7/XIN32/XOUT32/
PGMNVALID
48
PA0/PGMEN0
62
63
64
XIN/PGMCK/PB9
PB14
VDDPLL
The bottom pad of the QFN package must be connected to ground.
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
4.3
SAM3N4/2/1/0/00A Package and Pinout
Figure 4-5.
Orientation of the 48-pad QFN Package
48
37
1
36
12
25
13
TOP VIEW
24
Figure 4-6.
Orientation of the 48-lead LQFP Package
36
25
37
24
48
13
1
12
15
11011BS–ATARM–22-Feb-12
4.3.1
48-Lead LQFP and QFN Pinout
Table 4-4.
48-pin SAM3N4/2/1/0/00A Pinout
1
1
13
VDDIO
25
TDI/PB4
37
TDO/TRACESWO/
PB5
GND
14
PA16/PGMD4
26
PA6/PGMNOE
38
JTAGSEL
3
PB0/AD4
15
PA15/PGMD3
27
PA5/PGMRDY
39
TMS/SWDIO/PB6
4
PB1/AD5
16
PA14/PGMD2
28
PA4/PGMNCMD
40
TCK/SWCLK/PB7
5
PB2/AD6
17
PA13/PGMD1
29
NRST
41
VDDCORE
6
PB3/AD7
18
VDDCORE
30
TST
42
ERASE/PB12
7
VDDIN
19
PA12/PGMD0
31
PA3
43
PB10
8
VDDOUT
20
PA11/PGMM3
32
PA2/PGMEN2
44
PB11
9
PA17/PGMD5/AD0
21
PA10/PGMM2
33
VDDIO
45
XOUT/PB8
22
PA9/PGMM1
34
GND
11
12
Note:
2
10
ADVREF
PA18/PGMD6/AD1
PA19/PGMD7/AD2
PA20/AD3
23
PA8/XOUT32/PG
MM0
35
PA1/PGMEN1
24
PA7/XIN32/PGMN
VALID
36
PA0/PGMEN0
46
47
48
XIN/P/PB9/GMCK
VDDIO
VDDPLL
The bottom pad of the QFN package must be connected to ground.
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
5. Power Considerations
5.1
Power Supplies
The SAM3N product has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals. Voltage ranges from 1.62V and 1.95V.
• VDDIO pins: Power the Peripherals I/O lines, Backup part, 32 kHz crystal oscillator and
oscillator pads. Voltage ranges from 1.62V and 3.6V
• VDDIN pin: Voltage Regulator, ADC and DAC Power Supply. Voltage ranges from 1.8V to
3.6V for the Voltage Regulator
• VDDPLL pin: Powers the PLL, the Fast RC and the 3 to 20 MHz oscillators. Voltage ranges
from 1.62V and 1.95V.
5.2
Voltage Regulator
The SAM3N embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is intended to supply the internal core of SAM3N. It features two different
operating modes:
• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws
60 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current
depending on the required load current. In Wait Mode quiescent current is only 7 µA.
• In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT)
is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach
Normal mode is less than100 µs.
For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regulator section in the Electrical Characteristics section of the datasheet.
5.3
Typical Powering Schematics
The SAM3N supports a 1.62V-3.6V single supply mode. The internal regulator input connected
to the source and its output feeds VDDCORE. Figure 5-1 shows the power schematics.
As VDDIN powers the voltage regulator and the ADC/DAC, when the user does not want to use
the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is different from Backup mode).
17
11011BS–ATARM–22-Feb-12
Figure 5-1.
Single Supply
VDDIO
Main Supply
(1.8V-3.6V)
VDDOUT
I/Os.
ADC, DAC
VDDIN
Voltage
Regulator
VDDCORE
VDDPLL
Figure 5-2.
Core Externally Supplied
Main Supply
(1.62V-3.6V)
Can be the
same supply
ADC, DAC Supply
(3V-3.6V)
VDDIO
VDDOUT
VDDCORE Supply
(1.62V-1.95V)
I/Os.
ADC, DAC
VDDIN
VDDCORE
Voltage
Regulator
VDDPLL
Note:
Restrictions
With Main Supply < 3V, ADC and DAC are not usable.
With Main Supply >= 3V, all peripherals are usable.
Figure 5-3 below provides an example of the powering scheme when using a backup battery.
Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch
off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after
backup reset). External wake-up of the system can be from a push button or any signal. See
Section 5.6 “Wake-up Sources” for further details.TFBGA
1
SAM3N Summary
11011BS–ATARM–22-Feb-12
SAM3N Summary
Figure 5-3.
Core Externally Supplied (backup battery)
ADC, DAC Supply
(3V-3.6V)
Backup
Battery
VDDIO
+
-
I/Os.
ADC, DAC
VDDIN
Main Supply
IN
OUT
3.3V
LDO
VDDOUT
VDDCORE
Voltage
Regulator
ON/OFF
VDDPLL
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
5.4
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLL. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
5.5
Low Power Modes
The various low-power modes of the SAM3N are described below:
5.5.1
Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system
that is performing periodic wakeups to carry out tasks but not requiring fast startup time
(
CO. 20 R>
C
7. 50
64
a. so
L
Option A
9. 00 BSC
Pin 1#
Triangle
SAM3N Summary--------------1101185-ATARM-22-Feb-12
SAM3N Summary
14. Ordering Information
Table 14-1.
Ordering Code
ATSAM3N4CA-AU
ATSAM3N4CA-CU
ATSAM3N4BA-AU
ATSAM3N4BA-MU
ATSAM3N4AA-AU
ATSAM3N4AA-MU
ATSAM3N2CA-AU
ATSAM3N2CA-CU
ATSAM3N2BA-AU
ATSAM3N2BA-MU
ATSAM3N2AA-AU
ATSAM3N2AA-MU
ATSAM3N1CA-AU
ATSAM3N1CB-AU
ATSAM3N1CA-CU
ATSAM3N1CB-CU
ATSAM3N1BA-AU
ATSAM3N1BB-AU
ATSAM3N1BA-MU
ATSAM3N1BB-MU
MRL
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
B
A
B
A
B
Flash
(Kbytes)
Package
Package Type
Temperature
Operating Range
256
LQFP100
Green
Industrial
-40°C to 85°C
256
TFBGA100
Green
Industrial
-40°C to 85°C
256
LQFP64
Green
Industrial
-40°C to 85°C
256
QFN64
Green
Industrial
-40°C to 85°C
256
LQFP48
Green
Industrial
-40°C to 85°C
256
QFN48
Green
Industrial
-40°C to 85°C
128
LQFP100
Green
Industrial
-40°C to 85°C
128
TFBGA100
Green
Industrial
-40°C to 85°C
128
LQFP64
Green
Industrial
-40°C to 85°C
128
QFN64
Green
Industrial
-40°C to 85°C
128
LQFP48
Green
Industrial
-40°C to 85°C
128
QFN48
Green
Industrial
-40°C to 85°C
64
LQFP100
Green
Industrial
-40°C to 85°C
64
LQFP100
Green
Industrial
-40°C to 85°C
64
TFBGA100
Green
Industrial
-40°C to 85°C
64
TFBGA100
Green
Industrial
-40°C to 85°C
64
LQFP64
Green
Industrial
-40°C to 85°C
64
LQFP64
Green
Industrial
-40°C to 85°C
64
QFN 64
Green
Industrial
-40°C to 85°C
64
QFN 64
Green
Industrial
-40°C to 85°C
57
11011BS–ATARM–22-Feb-12
Table 14-1.
Ordering Code
ATSAM3N1AA-AU
ATSAM3N1AB-AU
ATSAM3N1AA-MU
ATSAM3N1AB-MU
ATSAM3N0CA-AU
ATSAM3N0CA-CU
ATSAM3N0BA-AU
ATSAM3N0BA-MU
ATSAM3N0AA-AU
ATSAM3N0AA-MU
ATSAM3N00BA-AU
ATSAM3N00BA-MU
ATSAM3N00AA-AU
ATSAM3N00AA-MU
MRL
A
B
A
B
A
A
A
A
A
A
A
A
A
A
Flash
(Kbytes)
Package
Package Type
Temperature
Operating Range
64
LQFP48
Green
Industrial
-40°C to 85°C
64
LQFP48
Green
Industrial
-40°C to 85°C
64
QFN48
Green
Industrial
-40°C to 85°C
64
QFN48
Green
Industrial
-40°C to 85°C
32
LQFP100
Green
Industrial
-40°C to 85°C
32
TFBGA100
Green
Industrial
-40°C to 85°C
32
LQFP64
Green
Industrial
-40°C to 85°C
32
QFN64
Green
Industrial
-40°C to 85°C
32
LQFP48
Green
Industrial
-40°C to 85°C
32
QFN48
Green
Industrial
-40°C to 85°C
16
LQFP64
Green
Industrial
-40°C to 85°C
16
QFN64
Green
Industrial
-40°C to 85°C
16
LQFP48
Green
Industrial
-40°C to 85°C
16
QFN48
Green
Industrial
-40°C to 85°C
11011BS–ATARM–22-Feb-12
SAM3N Summary
58
SAM3N Summary
59
11011BS–ATARM–22-Feb-12
Revision History
Doc. Rev.
11011BS
Change
Request Ref.
Comments
Overview:
All mentions of 100-ball LFBGA changed into 100-ball TFBGA
Section 8. “Product Mapping”, Heading was ‘Memories’. Changed to ‘Product Mapping’
Section 4.1.4 “100-ball TFBGA Pinout”, whole pinout table updated
Updated package dimensions in ‘Features’
8044
7685
7201
7965
Doc. Rev
Comments
11011AS
First issue
Change
Request Ref.
11011BS–ATARM–22-Feb-12
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