ATSAM3S2BA-MUR

SAM3S Atmel | SMART ARM-based Flash MCU DATASHEET Description The Atmel ® | SMART SAM3S series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM ® Cortex ® -M3 processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48 Kbytes of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Controller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM timer, two 3-channel general-purpose 16-bit timers an RTC, an ADC, a 12-bit DAC and an analog comparator. The SAM3S device is a medium range general purpose microcontroller with the best ratio in terms of reduced power consumption, processing power and peripheral set. This enables the SAM3S to sustain a wide range of applications including consumer, industrial control, and PC peripherals. It operates from 1.62V to 3.6V and is available in 48-, 64- and 100-pin QFP, 48and 64-pin QFN, and 100-pin TFBGA packages. The SAM3S series is the ideal migration path from the SAM7S series for applications that require more performance.The SAM3S series is pin-to-pin compatible with the SAM3N, SAM4S series (64- and 100-pin versions) and SAM7S series (64-pin versions). Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Features  Core ̶ ARM® Cortex®-M3 revision 2.0 running at up to 64 MHz ̶ Memory Protection Unit (MPU) ̶ Thumb®-2 instruction set  Pin-to-pin compatible with AT91SAM7S series (48- and 64-pin versions)  Memories  ̶ From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane ̶ From 16 to 48 Kbytes embedded SRAM ̶ 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines ̶ 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support ̶ Memory Protection Unit (MPU) System Embedded voltage regulator for single supply operation ̶ Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation ̶ ̶ ̶ Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power 32.768 kHz for RTC or device clock High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment ̶   2 Slow Clock Internal RC oscillator as permanent low-power mode device clock ̶ Two PLLs up to 130 MHz for device clock and for USB ̶ Temperature Sensor ̶ Up to 22 peripheral DMA (PDC) channels Low Power Modes ̶ Sleep and Backup modes, down to 1.8 µA in Backup mode ̶ Ultra low power RTC Peripherals ̶ USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip Transceiver ̶ Up to 2 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode ̶ Two 2-wire UARTs ̶ Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller (I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC) ̶ Up to two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor ̶ 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control ̶ 32-bit Real-time Timer and RTC with calendar and alarm features ̶ Up to 15-channel, 1Msps ADC with differential input mode and programmable gain stage ̶ One 2-channel 12-bit 1Msps DAC ̶ One Analog Comparator with flexible input selection, Selectable input hysteresis ̶ 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) ̶ Write Protected Registers SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15  I/O ̶ ̶ Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination  Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel Capture Mode Packages ̶ ̶ 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm ̶ 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 3 1. Configuration Summary The SAM3S microcontrollers differ in memory size, package and features list. Table 1-1 below summarizes the configurations of the device family Table 1-1. Device Configuration Summary Flash SRAM Timer Counter Channels GPIOs UART/ USARTs ADC 12-bit DAC Output External Bus Interface HSMCI Package 1 port 4 bits LQFP100 TFBGA100 SAM3S4C 256 Kbytes single plane 48 Kbytes 6 79 2/2(1) 15 ch. 2 8-bit data, 4 chip selects, 24-bit address SAM3S4B 256 Kbytes single plane 48 Kbytes 6(2) 47 2/2(1) 10 ch. 2 - 1 port 4 bits LQFP64 QFN 64 SAM3S4A 256 Kbytes single plane 48 Kbytes 6(2) 34 2/1 8 ch. - - - LQFP48 QFN 48 SAM3S2C 128 Kbytes single plane 32 Kbytes 6 79 2/2(1) 15 ch. 2 8-bit data, 4 chip selects, 24-bit address 1 port 4 bits LQFP100 TFBGA100 SAM3S2B 128 Kbytes single plane 32 Kbytes 6(2) 47 2/2(1) 10 ch. 2 - 1 port 4 bits LQFP64 QFN 64 SAM3S2A 128 Kbytes single plane 32 Kbytes 6(2) 34 2/1 8 ch. - - - LQFP48 QFN 48 SAM3S1C 64 Kbytes single plane 16 Kbytes 6 79 2/2(1) 15 ch. 2 8-bit data, 4 chip selects, 24-bit address 1 port 4 bits LQFP100 TFBGA100 SAM3S1B 64 Kbytes single plane 16 Kbytes 6(2) 47 2/2(1) 10 ch. 2 - 1 port 4 bits LQFP64 QFN 64 SAM3S1A 64 Kbytes single plane 16 Kbytes 6(2) 34 2/1 8 ch. - - - LQFP48 QFN 48 Notes: 4 1. Full Modem support on USART1. 2. Three TC channels are reserved for internal use. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Block Diagram TST UT O IN VD D System Controller VD D SE L SAM3S 100-pin Version Block Diagram TD TDI TMO TC S/S K/ W SW DI CL O K Figure 2-1. JTA G Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M Flash Unique Identifier In-Circuit Emulator XIN XOUT 3-20 MHz Osc. WKUPx SUPC 24-Bit N Cortex-M3 Processor SysTick Counter V Fmax 64 MHz I C MPU XIN32 XOUT32 OSC 32k ERASE RC 32k I/D FLASH 256 KBytes 128 KBytes 64 KBytes SRAM 48 KBytes 32 KBytes 16 KBytes ROM 16 KBytes S 4-layer AHB Bus Matrix Fmax 64 MHz 8 GPBREG VDDIO RTT VDDCORE RTC POR VDDPLL RSTC WDT Peripheral Bridge SM 2668 USB 2.0 Bytes Full FIFO Speed PIOA / PIOB / PIOC TWCK0 TWD0 TWCK1 TWD1 URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 RI1 DCD1 TWI0 PDC TWI1 PDC UART0 PDC UART1 PDC PDC USART1 PDC TIOA[0:2] TIOB[0:2] TC[0..2] TCLK[3:5] Timer Counter 1 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TF TK TD RD RK RF PDC SPI PDC TC[3..5] SSC PWMH[0:3] PWML[0:3] PWMFI0 ADTRG AD[0..14] ADVREF DAC0 DAC1 DATRG D[7:0] A[0:23] A21/NANDALE A22/NANDCLE NCS0 NCS1 NCS2 NCS3 NRD NWE NANDOE NANDWE NWAIT PIODC[7:0] PIODCEN1 PIODCEN2 PIODCCLK PIO Timer Counter 0 TIOB[3:5] NAND Flash Logic Static Memory Controller TCLK[0:2] TIOA[3:5] External Bus Interface PDC USART0 DDP DDM PIO NRST Transceiver 2. PWM PDC PDC Temp. Sensor ADC PDC DAC PDC MCCK MCCDA MCDA[0..3] High Speed MCI Analog Comparator ADC DAC Temp Sensor ADVREF CRC Unit SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 5 System Controller O UT VD D IN VD D TD TST JT AG SE L SAM3S 64-pin Version Block Diagram I TD O TM S/ TC SW K/ DIO SW CL K Figure 2-2. Voltage Regulator PCK0-PCK2 PLLA PMC PLLB JTAG & Serial Wire RC 12/8/4 M Flash Unique Identifier In-Circuit Emulator XIN XOUT 3-20 MHz Osc. WKUPx SUPC 24-Bit N Cortex-M3 Processor SysTick Counter V Fmax 64 MHz I C MPU XIN32 XOUT32 OSC 32K I/D FLASH 256 KBytes 128 KBytes 64 KBytes SRAM 48 KBytes 32 KBytes 16 KBytes ROM 16 KBytes S RC 32k 4-layer AHB Bus Matrix Fmax 64 MHz 8 GPBREG VDDIO RTT VDDCORE RTC VDDPLL POR Peripheral Bridge RSTC NRST WDT 2668 USB 2.0 Bytes Full FIFO Speed Transceiver ERASE DDP DDM SM PIOA / PIOB TWCK0 TWD0 TWI0 PDC TWCK1 TWD1 TWI1 PDC URXD0 UTXD0 UART0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 UART1 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 RI1 DCD1 TCLK[0:2] TIOA[0:2] TIOB[0:2] PDC PIODC[7:0] PIODCEN1 PIODCEN2 PIODCCLK PIO PDC PDC SPI NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK SSC TF TK TD RD RK RF PDC USART0 PDC PDC USART1 PDC Timer Counter 0 TC[0..2] PDC Timer Counter 1 TC[3..5] PWMH[0:3] PWML[0:3] PWMFI0 ADTRG AD[0..9] 6 MCCDA MCDA[0..3] PWM PDC Temp. Sensor ADC ADVREF DAC0 DAC1 DATRG MCCK High Speed MCI PDC Analog Comparator CRC Unit DAC PDC SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 ADC DAC Temp Sensor ADVREF O UT IN System Controller VD D VD D TD TST JT AG SE L SAM3S 48-pin Version Block Diagram I TD O TM S/ TC SW K/ DIO SW CL K Figure 2-3. Voltage Regulator PCK0-PCK2 PLLA PLLB PMC JTAG & Serial Wire RC 12/8/4 M XIN XOUT In-Circuit Emulator 3-20 MHz Osc. WKUPx Flash Unique Identifier Cortex-M3 Processor Fmax 64 MHz 24-Bit SysTick Counter SUPC MPU XIN32 OSC32K XOUT32 I/D N V I C FLASH 256 KBytes 128 KBytes 64 KBytes SRAM 48 KBytes 32 KBytes 16 KBytes ROM 16 KBytes S RC 32k ERASE 4-layer AHB Bus Matrix Fmax 64 MHz 8 GPBREG RTT VDDIO VDDCORE POR VDDPLL Peripheral Bridge RSTC WDT 2668 USB 2.0 Bytes Full FIFO Speed Transceiver RTC DDP DDM SM PIOA / PIOB TWCK0 TWD0 TWI0 PDC TWCK1 TWD1 TWI1 PDC URXD0 UTXD0 UART0 URXD1 UTXD1 UART1 RXD0 TXD0 SCK0 SPI NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK SSC TF TK TD RD RK RF PDC PDC PDC PDC USART0 RTS0 CTS0 PDC Timer Counter 0 TCLK[0:2] TIOA[0:2] TC[0..2] TIOB[0:2] Timer Counter 1 Analog Comparator TC[3..5] ADC Temp Sensor ADVREF PWMH[0:3] PWML[0:3] PWMFI0 PWM PDC CRC Unit ADTRG Temp. Sensor AD[0..7] ADVREF ADC PDC SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 7 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power 1.8V to 3.6V(4) VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.62 V to 1.95V VDDCORE Power the core, the embedded memories and the peripherals Power GND Ground Ground 1.62V to 1.95V Supply Controller - SUPC Reset State: WKUPx Wake Up input pins Input VDDIO - PIO Input - Internal Pull-up disabled - Schmitt Trigger enabled(1) Clocks, Oscillators and PLLs XIN Main Oscillator Input Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output Reset State: Output - PIO Input - Internal Pull-up disabled Input Output VDDIO - Schmitt Trigger enabled(1) Reset State: PCK0 - PCK2 Programmable Clock Output - PIO Input Output - Internal Pull-up enabled - Schmitt Trigger enabled(1) Serial Wire/JTAG Debug Port - SWJ-DP TCK/SWCLK Test Clock/Serial Wire Clock Input TDI Test Data In Input TDO/TRACESWO Test Data Out / Trace Asynchronous Data Out Output TMS/SWDIO Test Mode Select /Serial Wire Input/Output Input / I/O JTAGSEL JTAG Selection Input Reset State: - SWJ-DP Mode VDDIO - Internal pull-up disabled(5) - Schmitt Trigger enabled(1) Permanent Internal pull-down High Flash Memory Reset State: ERASE Flash and NVM Configuration Bits Erase Command Input High VDDIO - Erase Input - Internal pull-down enabled - Schmitt Trigger enabled(1) 8 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage reference Comments Reset/Test NRST Synchronous Microcontroller Reset TST Test Select I/O Low Permanent Internal VDDIO pull-up Permanent Internal Input pull-down Universal Asynchronous Receiver Transmitter - UARTx URXDx UART Receive Data Input UTXDx UART Transmit Data Output PIO Controller - PIOA - PIOB - PIOC PA0 - PA31 Parallel IO Controller A I/O PB0 - PB14 Parallel IO Controller B I/O PC0 - PC31 Parallel IO Controller C I/O Reset State: VDDIO - PIO or System IOs(2) - Internal pull-up enabled - Schmitt Trigger enabled(1) PIO Controller - Parallel Capture Mode (PIOA Only) PIODC0-PIODC7 Parallel Capture Mode Data Input PIODCCLK Parallel Capture Mode Clock Input PIODCEN1-2 Parallel Capture Mode Enable Input VDDIO External Bus Interface D0 - D7 Data Bus I/O A0 - A23 Address Bus NWAIT External Wait Signal Output Input Low Static Memory Controller - SMC NCS0 - NCS3 Chip Select Lines Output Low NRD Read Signal Output Low NWE Write Enable Output Low NAND Flash Logic NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low High Speed Multimedia Card Interface - HSMCI MCCK Multimedia Card Clock I/O MCCDA Multimedia Card Slot A Command I/O MCDA0 - MCDA3 Multimedia Card Slot A Data I/O Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock I/O TXDx USARTx Transmit Data I/O RXDx USARTx Receive Data Input RTSx USARTx Request To Send CTSx USARTx Clear To Send Output Input SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 9 Table 3-1. Signal Description List (Continued) Signal Name Function Type DTR1 USART1 Data Terminal Ready DSR1 USART1 Data Set Ready Input DCD1 USART1 Data Carrier Detect Input RI1 USART1 Ring Indicator Input Active Level Voltage reference Comments I/O Synchronous Serial Controller - SSC TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock I/O RK SSC Receive Clock I/O TF SSC Transmit Frame Sync I/O RF SSC Receive Frame Sync I/O Timer/Counter - TC TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I/O Line A I/O TIOBx TC Channel x I/O Line B I/O Pulse Width Modulation Controller- PWMC PWMHx PWM Waveform Output High for channel x PWMLx PWM Waveform Output Low for channel x PWMFI0 PWM Fault Input Output only output in complementary mode when dead time insertion is enabled Output Input Serial Peripheral Interface - SPI MISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial Clock I/O SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPI_NPCS1 SPI_NPCS3 SPI Peripheral Chip Select Output Low Two-Wire Interface- TWI TWDx TWIx Two-wire Serial Data I/O TWCKx TWIx Two-wire Serial Clock I/O Analog ADC, DAC and Analog Comparator Reference ADVREF Analog Analog-to-Digital Converter - ADC AD0 - AD14 Analog Inputs Analog, Digital ADTRG ADC Trigger Input 10 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 VDDIO Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Voltage reference Comments 12-bit Digital-to-Analog Converter - DAC DAC0 - DAC1 Analog output DACTRG DAC Trigger Analog, Digital Input VDDIO SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage reference Comments Fast Flash Programming Interface - FFPI PGMEN0-PGMEN2 Programming Enabling Input VDDIO PGMM0-PGMM3 Programming Mode Input PGMD0-PGMD15 Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low PGMCK Programming Clock Input PGMNCMD Programming Command Input VDDIO Low USB Full Speed Device DDM USB Full Speed Data - DDP Notes: 12 USB Full Speed Data + 1. 2. 3. 4. 5. Reset State: Analog, Digital VDDIO - USB Mode - Internal Pull-down(3) Schmitt Triggers can be disabled through PIO registers. Some PIO lines are shared with System IOs. Refer to the “USB” sub section in the product “Electrical Characteristics” Section for Pull-down value in USB Mode. See Section 5.4 “Typical Powering Schematics” for restriction on voltage range of Analog Cells. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding to this PIO line must be enabled to avoid current consumption due to floating input. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 4. Package and Pinout 4.1 SAM3S4/S2/S1C Package and Pinout Figure 4-2 shows the orientation of the 100-ball TFBGA Package 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball TFBGA Package Outline The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm. Figure 4-2. Orientation of the 100-BALL TFBGA Package TOP VIEW 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K BALL A1 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 13 4.1.3 100-Lead LQFP Pinout Table 4-1. 100-lead LQFP SAM3S4/S2/S1C Pinout 1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/PB 5 2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL 3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18 4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6 5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19 6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31 7 PB2/AD6 32 PC6 57 PA27/PGMD15 82 PC20 8 PC31 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7 9 PB3/AD7 34 PA24/PGMD12 59 PA28 84 PC21 10 VDDIN 35 PC5 60 NRST 85 VDDCORE 11 VDDOUT 36 VDDCORE 61 TST 86 PC22 12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12 13 PC26 38 PA25/PGMD13 63 PA29 88 DDM/PB10 14 PA18/PGMD6/AD1 39 PA26/PGMD14 64 PA30 89 DDP/PB11 15 PA21/PGMD9/AD8 40 PC3 65 PC10 90 PC23 16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO 17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24 18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0 19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25 20 PA22/PGMD10/AD9 45 GND 70 GND 95 GND 21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT 22 PA23/PGMD11 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN 23 PC12/AD12 48 PA8/XOUT32/ PGMM0 73 PC16 98 VDDIO 24 PA20/PGMD8/AD3 49 74 PA0/PGMEN0 99 PB14/DAC1 25 PC0 50 75 PC17 100 VDDPLL 14 PA7/XIN32/ PGMNVALID VDDIO SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 4.1.4 100-ball TFBGA Pinout Table 4-2. 100-ball TFBGA SAM3S4/S2/S1C Pinout A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1 PA18/PGMD6/AD1 H6 PC4 A2 PC29 C7 PC16 F2 PC26 H7 PA11/PGMM3 A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1 A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4 A6 PB13/DAC0 D1 PB3/AD7 F6 PA27/PGMD15 J1 PC15/AD11 A7 DDP/PB11 D2 PB0/AD4 F7 PC8 J2 PC0 A8 DDM/PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4 A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6 A10 JTAGSEL D5 GND F10 PC9 J5 PA24/PGMD12 B1 PC30/AD14 D6 GND G1 PA21/PGMD9/AD8 J6 PA25/PGMD13 B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10/PGMM2 B3 GNDANA D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND B4 PB14/DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO B6 PC20 E1 PA17/PGMD5/AD0 G6 PA26/PGMD14 K1 PA22/PGMD10/AD9 B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10 B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12 B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/PGMD8/AD3 B10 TDO/TRACESWO/ PB5 E5 GND G10 PA5/PGMRDY K5 PC5 C1 PB2/AD6 E6 NRST H1 PA19/PGMD7/AD2 K6 PC3 C2 VDDPLL E7 PA29/AD13 H2 PA23/PGMD11 K7 PC2 C3 PC25 E8 PA30 H3 PC7 K8 PA9/PGMM1 C4 PC23 E9 PC10 H4 PA14/PGMD2 K9 PA8/XOUT32/PGMM0 C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10 PA7/XIN32/ PGMNVALID SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15 4.2 SAM3S4/S2/S1B Package and Pinout Figure 4-3. Orientation of the 64-pad QFN Package 64 49 1 48 16 33 32 17 Figure 4-4. TOP VIEW Orientation of the 64-lead LQFP Package 48 49 32 64 17 1 16 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 33 16 4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. Table 4-3. 64-pin SAM3S4/2/1B Pinout 1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5 2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL 3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6 4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31 5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7 6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE 7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12 8 VDDOUT 24 VDDCORE 40 TST 56 DDM/PB10 9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 DDP/PB11 10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO 11 PA21/PGMD9/AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0 12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND 13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8 14 PA22/PGMD10/AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9 15 PA23/PGMD11 31 PA8/XOUT32/PGMM0 47 PA1/PGMEN1 63 PB14/DAC1 PA0/PGMEN0 64 VDDPLL 16 PA20/PGMD8/AD3 32 PA7/XIN32/PGMNVALID 48 Note: The bottom pad of the QFN package must be connected to ground. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 17 4.3 SAM3S4/2/1A Package and Pinout Figure 4-5. Orientation of the 48-pad QFN Package 48 37 1 36 12 25 13 24 TOP VIEW Figure 4-6. Orientation of the 48-lead LQFP Package 36 37 24 48 13 1 18 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 25 12 4.3.1 48-Lead LQFP and QFN Pinout Table 4-4. 48-pin SAM3S4/2/1A Pinout 1 ADVREF 13 VDDIO 25 TDI/PB4 37 TDO/TRACESWO/ PB5 2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL 3 PB0/AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS/SWDIO/PB6 4 PB1/AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK/SWCLK/PB7 5 PB2/AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE 6 PB3/AD7 18 VDDCORE 30 TST 42 ERASE/PB12 7 VDDIN 19 PA12/PGMD0 31 PA3 43 DDM/PB10 8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 DDP/PB11 9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT/PB8 10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/PB9/PGMCK 11 PA19/PGMD7/AD2 23 PA8/XOUT32/ PGMM0 35 PA1/PGMEN1 47 VDDIO 12 PA20/AD3 24 36 PA0/PGMEN0 48 VDDPLL PA7/XIN32/ PGMNVALID Note: The bottom pad of the QFN package must be connected to ground. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 19 5. Power Considerations 5.1 Power Supplies The SAM3S product has several types of power supply pins:  VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.62V to 1.95V.  VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers); USB transceiver; Backup part, 32 kHz crystal oscillator and oscillator pads; ranges from 1.62V to 3.6V.  VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply; Voltage ranges from 1.8V to 3.6V  VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator; voltage ranges from 1.62V to 1.95V. 5.2 Power-up Considerations 5.2.1 VDDIO Versus VDDCORE VDDIO must always be higher than or equal to VDDCORE. VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached the following thresholds:  the minimum VT+ of the core power supply brownout detector (1.36 V)  the minimum value of tRST (100 µs) If VDDCORE rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 5 V/ms. If VDDCORE is powered by the internal regulator, all power-up considerations are met. Figure 5-1. VDDCORE and VDDIO Constraints at Startup Supply (V) VDDIO VDDIO(min) VDDCORE VDDCORE(min) VT+ tRST Core supply POR output SLCK 20 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Time (t) 5.2.2 VDDIO Versus VDDIN At power-up, VDDIO needs to reach 0.6 V before VDDIN reaches 1.0 V. VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5 V). 5.3 Voltage Regulator The SAM3S embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of SAM3S. It features two different operating modes:  In Normal mode, the voltage regulator consumes less than 700 µA static current and draws 80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode quiescent current is only 7 µA.  In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT) is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach Normal mode is inferior to 100 µs. For adequate input and output power supply decoupling/bypassing, refer to the “Voltage Regulator” section in the “Electrical Characteristics” section of the datasheet. 5.4 Typical Powering Schematics The SAM3S supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-2 shows the power schematics. As VDDIN powers the voltage regulator, the ADC/DAC and the analog comparator, when the user does not want to use the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is different from Backup mode). Figure 5-2. Single Supply VDDIO Main Supply (1.8V-3.6V) USB Transceivers. ADC, DAC Analog Comp. VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Note: For USB, VDDIO needs to be greater than 3.0V. For ADC, VDDIN needs to be greater than 2.0V. For DAC, VDDIN needs to be greater than 2.4V. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 21 Figure 5-3. Core Externally Supplied. VDDIO Main Supply (1.62V-3.6V) USB Transceivers. Can be the same supply ADC, DAC Analog Comp. VDDIN ADC, DAC, Analog Comparator Supply (1.8V-3.6V) VDDOUT Voltage Regulator VDDCORE VDDCORE Supply (1.62V-1.95V) VDDPLL Note: For USB, VDDIO needs to be greater than 3.0V For ADC, VDDIN needs to be greater than 2.0V. For DAC, VDDIN needs to be greater than 2.4V. Figure 5-4 below provides an example of the powering scheme when using a backup battery. Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from a push button or any signal. See Section 5.7 “Wake-up Sources” for further details. Figure 5-4. Backup Battery VDDIO Backup Battery USB Transceivers. + ADC, DAC Analog Comp. VDDIN Main Supply IN VDDOUT OUT Voltage Regulator 3.3V LDO VDDCORE ON/OFF VDDPLL PIOx (Output) WKUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. Note: 22 For ADC, VDDIN needs to be greater than 2.0V. For DAC, VDDIN needs to be greater than 2.4V. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 5.5 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.6 Low Power Modes The various low power modes of the SAM3S are described below: 5.6.1 Backup Mode The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time ( 0, ensure that none of the WKUPx pins that are enabled for a wake-up (exit from Backup mode) hold an active polarity. This is checked by reading the pin status in the PIO Controller. If WKUPENx = 1 and the pin WKUPx holds an active polarity, the system must not be instructed to enter Backup mode. 5.8 Fast Startup The SAM3S allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-6, is fully asynchronous and provides a fast start-up signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 4 MHz Fast RC oscillator, switches the master clock on this 4MHz clock and reenables the processor clock. 26 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Figure 5-6. Fast Start-Up Sources USBEN usb_wakeup RTCEN rtc_alarm RTTEN rtt_alarm FSTT0 WKUP0 Falling/Rising Edge Detector fast_restart FSTT1 WKUP1 Falling/Rising Edge Detector FSTT15 WKUP15 Falling/Rising Edge Detector SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 27 6. Input/Output Lines The SAM3S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up or pulldown, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to the product “PIO Controller” section. The input/output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM3S embeds high speed pads able to handle up to 32 MHz for HSMCI (MCK/2), 45 MHz for SPI clock lines and 35 MHz on other lines. See AC Characteristics Section in the Electrical Characteristics Section of the datasheet for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os. Each I/O line also embeds an ODT (On-Die Termination), see Figure 6-1. It consists of an internal series resistor termination scheme for impedance matching between the driver output (SAM3S) and the PCB trace impedance preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. In conclusion ODT helps diminish signal integrity issues. Figure 6-1. On-Die Termination Z0 ~ Zout + Rodt ODT 36 Ohms Typ. Rodt Receiver SAM3 Driver with Zout ~ 10 Ohms 6.2 PCB Trace Z0 ~ 50 Ohms System I/O Lines System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few. Described below are the SAM3S system I/O lines shared with PIO lines: These pins are software configurable as general purpose I/O or system pins. At startup the default function of these pins is always used. 28 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Table 6-1. System I/O Configuration Pin List SYSTEM_IO bit number Default function after reset Other function 12 ERASE PB12 Low Level at startup(1) 10 DDM PB10 - 11 DDP PB11 - 7 TCK/SWCLK PB7 - 6 TMS/SWDIO PB6 - 5 TDO/TRACESWO PB5 - 4 TDI PB4 - - PA7 XIN32 - - PA8 XOUT32 - - PB9 XIN - Constraints for normal start Configuration In Matrix User Interface Registers (Refer to the SystemIO Configuration Register in the “Bus Matrix” section of the datasheet.) See footnote (2) below See footnote (3) below PB8 XOUT 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PB12 into PIO mode, 2. In the product Datasheet Refer to: “Slow Clock Generator” of the “Supply Controller” section. 3. In the product Datasheet Refer to: “3 to 20 MHZ Crystal Oscillator” information in the ”PMC” section. - Notes: 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on page 8. At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer to the “Debug and Test” Section of the product datasheet. SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the “Debug and Test” Section. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 29 6.3 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet. 6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input. 6.5 ERASE Pin The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations. This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100 ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation. The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing. Please refer to Section 10.3 “Peripheral Signal Multiplexing on I/O Lines” on page 37. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash. 30 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 7. Product Mapping Figure 7-1. SAM3S Product Mapping 0x00000000 Code 0x00000000 Address memory space Peripherals 0x40000000 HSMCI Boot Memory Code 0x00400000 Internal Flash 18 0x40004000 SSC 0x20000000 22 0x40008000 0x00800000 SRAM Internal ROM 1 MByte bit band region 0x00C00000 Reserved 0x1FFFFFFF SPI 0x22000000 21 0x4000C000 Reserved 0x23FFFFFF Undefined 0x40010000 TC0 0x24000000 0x40000000 32 MBytes bit band alias 23 TC0 24 TC0 External RAM 0x60000000 0x61000000 TC2 25 0x40014000 TC1 SMC Chip Select 0 TC1 +0x80 Peripherals 0x60000000 TC0 +0x40 External SRAM TC3 26 +0x40 SMC Chip Select 1 0x62000000 TC1 0xA0000000 TC1 0x63000000 0x64000000 SMC Chip Select 3 TC5 28 0x40018000 0xE0000000 TWI0 System Reserved 0x9FFFFFFF 27 +0x80 Reserved SMC Chip Select 2 TC4 19 0x4001C000 0xFFFFFFFF TWI1 20 0x40020000 0x400E0000 System Controller PWM USART1 0x400E0400 Reserved 5 0x400E0600 0x40030000 UART0 Reserved 8 0x400E0740 15 0x4002C000 PMC ID 14 0x40028000 MATRIX block peripheral USART0 10 0x400E0200 offset 31 0x40024000 SMC 1 MByte bit band regiion 0x40034000 CHIPID UDP 0x400E0800 UART1 ADC 9 0x400E0A00 29 0x4003C000 EFC DACC 6 0x400E0C00 33 0x40038000 30 0x40040000 Reserved ACC 0x400E0E00 CRCCU 11 0x400E1000 Reserved 12 0x400E0000 PIOC System Controller 13 0x400E1400 0x400E2600 RSTC Reserved 1 +0x10 35 0x40048000 PIOB 0x400E1200 34 0x40044000 PIOA 0x40100000 SUPC Reserved +0x30 0x40200000 RTT 3 +0x50 0x40400000 32 MBytes bit band alias WDT Reserved 4 +0x60 0x60000000 RTC 2 +0x90 GPBR 0x400E1600 Reserved 0x4007FFFF SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 31 8. Memories 8.1 Embedded Memories 8.1.1 Internal SRAM The ATSAM3S4 product (256-Kbyte internal Flash version) embeds a total of 48 Kbytes high-speed SRAM. The ATSAM3S2 product (128-Kbyte internal Flash version) embeds a total of 32 Kbytes high-speed SRAM. The ATSAM3S1 product (64-Kbyte internal Flash version) embeds a total of 16 Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region. The bit band alias region is mapped from 0x2200 0000 to 0x23FF FFFF. 8.1.2 Internal ROM The SAM3S product embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA), In Application Programming routines (IAP) and Fast Flash Programming Interface (FFPI). At any time, the ROM is mapped at address 0x0080 0000. 8.1.3 Embedded Flash 8.1.3.1 Flash Overview The Flash of the ATSAM3S4 (256-Kbytes internal Flash version) is organized in one bank of 1024 pages (Single plane) of 256 bytes. The Flash of the ATSAM3S2 (128-Kbytes internal Flash version) is organized in one bank of 512 pages (Single plane) of 256 bytes. The Flash of the ATSAM3S1 (64-Kbytes internal Flash version) is organized in one bank of 256 pages (Single plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. 8.1.3.2 Flash Power Supply The Flash is supplied by VDDCORE. 8.1.3.3 Enhanced Embedded Flash Controller The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance. The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 8.1.3.4 Flash Speed The user needs to set the number of wait states depending on the frequency used. For more details, refer to the “AC Characteristics” sub section in the product “Electrical Characteristics” Section. 32 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 8.1.3.5 Lock Regions Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 8-1. Number of Lock Bits Product Number of Lock Bits Lock Region Size ATSAM3S4 16 16 kbytes (64 pages) ATSAM3S2 8 16 kbytes (64 pages) ATSAM3S1 4 16 kbytes (64 pages) If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.1.3.6 Security Bit Feature The SAM3S features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application. 8.1.3.7 Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 8.1.3.8 Unique Identifier Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the unique identifier. 8.1.3.9 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST is tied high and PA0 and PA1 are tied low. 8.1.3.10 SAM-BA® Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART and USB. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 33 The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). 8.1.3.11 GPNVM Bits The SAM3S features two GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Table 8-2. General Purpose Non-volatile Memory Bits GPNVMBit[#] 8.1.4 Function 0 Security bit 1 Boot mode selection Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via GPNVM. A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface. Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default. 8.2 External Memories The SAM3S features an External Bus Interface to provide the interface to a wide range of external memories and to any parallel peripheral. 34 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 9. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc... See the system controller block diagram in Figure 17-1 on page 262 9.1 System Controller and Peripherals Mapping Please refer to Section 7-1 “SAM3S Product Mapping” on page 31. All the peripherals are in the bit band region and are mapped in the bit band alias region. 9.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S embeds three features to monitor, warn and/or reset the chip: • Power-on-Reset on VDDIO • Brownout Detector on VDDCORE • Supply Monitor on VDDIO 9.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to the “Electrical Characteristics” section of the datasheet. 9.2.2 Brownout Detector on VDDCORE The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to the “Supply Controller” and Electrical Characteristics sections of the datasheet. 9.2.3 Supply Monitor on VDDIO The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information, refer to the “SUPC” and “Electrical Characteristics” sections of the datasheet. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 35 10. Peripherals 10.1 Peripheral Identifiers Table 10-1 defines the Peripheral Identifiers of the SAM3S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. Peripheral Identifiers PMC Clock Control Instance ID Instance Name NVIC Interrupt 0 SUPC X Supply Controller 1 RSTC X Reset Controller 2 RTC X Real Time Clock 3 RTT X Real Time Timer 4 WDT X Watchdog Timer 5 PMC X Power Management Controller 6 EEFC X Enhanced Embedded Flash Controller 36 Instance Description 7 - - 8 UART0 X X Reserved UART 0 9 UART1 X X UART 1 10 SMC X X SMC 11 PIOA X X Parallel I/O Controller A 12 PIOB X X Parallel I/O Controller B 13 PIOC X X Parallel I/O Controller C 14 USART0 X X USART 0 15 USART1 X X USART 1 16 - - - Reserved 17 - - - Reserved 18 HSMCI X X High Speed Multimedia Card Interface 19 TWI0 X X Two Wire Interface 0 20 TWI1 X X Two Wire Interface 1 21 SPI X X Serial Peripheral Interface 22 SSC X X Synchronous Serial Controller 23 TC0 X X Timer/Counter Channel 0 24 TC1 X X Timer/Counter Channel 1 25 TC2 X X Timer/Counter Channel 2 26 TC3 X X Timer/Counter Channel 3 27 TC4 X X Timer/Counter Channel 4 28 TC5 X X Timer/Counter Channel 5 29 ADC X X Analog-to-Digital Converter 30 DACC X X Digital-to-Analog Converter 31 PWM X X Pulse Width Modulation 32 CRCCU X X CRC Calculation Unit 33 ACC X X Analog Comparator 34 UDP X X USB Device Port SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 10.2 APB/AHB bridge The SAM3S product embeds one peripheral bridge: The peripherals of the bridge are clocked by MCK. 10.3 Peripheral Signal Multiplexing on I/O Lines The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB) or 3 PIO controllers on the 100-pin version, (PIOA, PIOB, PIOC), that multiplex the I/O lines of the peripheral set. The SAM3S 64-pin and 100-pin PIO Controllers control up to 32 lines. (See, Table 10-2.) Each line can be assigned to one of three peripheral functions: A, B or C. The multiplexing tables in the following pages define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO Controllers. Note that some peripheral functions which are output only, might be duplicated within the tables. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37 10.3.1 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments PA0 PWMH0 TIOA0 A17 WKUP0 High drive PA1 PWMH1 TIOB0 A18 WKUP1 High drive PA2 PWMH2 SCK0 DATRG WKUP2 High drive PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 WKUP3 PA5 RXD0 NPCS3 WKUP4 PA6 TXD0 PCK0 PA7 RTS0 PWMH3 PA8 CTS0 ADTRG PA9 URXD0 NPCS1 PA10 UTXD0 NPCS2 PA11 NPCS0 PWMH0 PA12 MISO PWMH1 PA13 MOSI PWMH2 PA14 SPCK PWMH3 PA15 TF TIOA1 PWML3 PA16 TK TIOB1 PWML2 WKUP15/PIODCEN2 PA17 TD PCK1 PWMH3 AD0 PA18 RD PCK2 A14 AD1 PA19 RK PWML0 A15 AD2/WKUP9 PA20 RF PWML1 A16 AD3/WKUP10 PA21 RXD1 PCK1 PA22 TXD1 NPCS3 PA23 SCK1 PA24 High drive XIN32 WKUP5 PWMFI0 XOUT32 WKUP6 WKUP7 WKUP8 WKUP14/PIODCEN1 AD8 64/100-pin versions NCS2 AD9 64/100-pin versions PWMH0 A19 PIODCCLK 64/100-pin versions RTS1 PWMH1 A20 PIODC0 64/100-pin versions PA25 CTS1 PWMH2 A23 PIODC1 64/100-pin versions PA26 DCD1 TIOA2 MCDA2 PIODC2 64/100-pin versions PA27 DTR1 TIOB2 MCDA3 PIODC3 64/100-pin versions PA28 DSR1 TCLK1 MCCDA PIODC4 64/100-pin versions PA29 RI1 TCLK2 MCCK PIODC5 64/100-pin versions PA30 PWML2 NPCS2 MCDA0 WKUP11/PIODC6 64/100-pin versions PA31 NPCS1 PCK2 MCDA1 PIODC7 64/100-pin versions 38 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 10.3.2 PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B Peripheral C Extra Function PB0 PWMH0 AD4 PB1 PWMH1 AD5 PB2 URXD1 NPCS2 AD6/ WKUP12 PB3 UTXD1 PCK2 AD7 PB4 TWD1 PWMH2 PB5 TWCK1 PWML0 System Function Comments TDI WKUP13 TDO/TRACESWO PB6 TMS/SWDIO PB7 TCK/SWCLK PB8 XOUT PB9 XIN PB10 DDM PB11 DDP PB12 PWML1 ERASE PB13 PWML2 PCK0 DAC0 64/100-pin versions PB14 NPCS1 PWMH3 DAC1 64/100-pin versions SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 39 10.3.3 PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A Peripheral B PC0 D0 PWML0 100-pin version PC1 D1 PWML1 100-pin version PC2 D2 PWML2 100-pin version PC3 D3 PWML3 100-pin version PC4 D4 NPCS1 100-pin version PC5 D5 100-pin version PC6 D6 100-pin version PC7 D7 100-pin version PC8 NWE 100-pin version PC9 NANDOE 100-pin version PC10 NANDWE 100-pin version PC11 NRD 100-pin version PC12 NCS3 PC13 NWAIT PC14 NCS0 PC15 NCS1 PC16 A21/NANDALE 100-pin version PC17 A22/NANDCLE 100-pin version PC18 A0 PWMH0 100-pin version PC19 A1 PWMH1 100-pin version PC20 A2 PWMH2 100-pin version PC21 A3 PWMH3 100-pin version PC22 A4 PWML3 100-pin version PC23 A5 TIOA3 100-pin version PC24 A6 TIOB3 100-pin version PC25 A7 TCLK3 100-pin version PC26 A8 TIOA4 100-pin version PC27 A9 TIOB4 100-pin version PC28 A10 TCLK4 100-pin version PC29 A11 TIOA5 AD13 100-pin version PC30 A12 TIOB5 AD14 100-pin version PC31 A13 TCLK5 40 PWML0 Peripheral C Extra Function System Function Comments AD12 100-pin version AD10 100-pin version 100-pin version PWML1 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 AD11 100-pin version 100-pin version 11. ARM Cortex® M3 Processor 11.1 About this section This section provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software and hardware engineers, including those who have no experience of ARM products. Note: The information in this section is reproduced from source material provided to Atmel by ARM Ltd. in terms of Atmel’s license for the ARM Cortex™-M3 processor core. This information is copyright ARM Ltd., 2008 - 2009. 11.2 About the Cortex-M3 processor and core peripherals  The Cortex-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:  outstanding processing performance combined with fast interrupt handling  enhanced system debug with extensive breakpoint and trace capabilities  efficient processor core, system and memories  ultra-low power consumption with integrated sleep modes  platform security, with integrated memory protection unit (MPU). Figure 11-1. Typical Cortex-M3 implementation Cortex-M3 Processor NVIC Debug Access Port Processor Core Serial Wire Viewer Memory Protection Unit Flash Patch Data Watchpoints Bus Matrix Code Interface SRAM and Peripheral Interface The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 41 capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to deliver industryleading interrupt performance. The NVIC provides up to 16 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend loadmultiple and store-multiple operations. Interrupt handlers do not require any assembler stubs, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down. 11.2.1 System level interface The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine grain memory control, enabling applications to implement security privilege levels, separating code, data and stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications. 11.2.2 Integrated configurable debug The Cortex-M3 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. 11.2.3 Cortex-M3 processor features and benefits summary  tight integration of system peripherals reduces area and development costs  Thumb instruction set combines high code density with 32-bit performance  code-patch ability for ROM system updates  power control optimization of system components  integrated sleep modes for low power consumption  fast code execution permits slower processor clock or increases sleep mode time  hardware division and fast multiplier  deterministic, high-performance interrupt handling for time-critical applications • memory protection unit (MPU) for safety-critical applications  extensive debug and trace capabilities: ̶ 42 Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and tracing. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.2.4 Cortex-M3 core peripherals These are: 11.2.4.1 Nested Vectored Interrupt Controller The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. 11.2.4.2 System control block The System control block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 11.2.4.3 System timer The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter. 11.2.4.4 Memory protection unit The Memory protection unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions, and an optional predefined background region. 11.3 Programmers model This section describes the Cortex-M3 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 11.3.1 Processor mode and privilege levels for software execution The processor modes are: 11.3.1.1 Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. 11.3.1.2 Handler mode Used to handle exceptions. The processor returns to Thread mode when it has finished exception processing. The privilege levels for software execution are: 11.3.1.3 Unprivileged The software:  has limited access to the MSR and MRS instructions, and cannot use the CPS instruction  cannot access the system timer, NVIC, or system control block  might have restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level. 11.3.1.4 Privileged The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level. In Thread mode, the CONTROL register controls whether software execution is privileged or unprivileged, see “CONTROL register” on page 52. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 43 11.3.2 Stacks The processor uses a full descending stack. This means the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see “Stack Pointer” on page 45. In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see “CONTROL register” on page 52. In Handler mode, the processor always uses the main stack. The options for processor operations are: Table 11-1. Summary of processor mode, execution privilege level, and stack use options Processor mode Used to execute Privilege level for software execution Stack used Thread Applications Privileged or unprivileged (1) Main stack or process stack(1) Handler Exception handlers Always privileged Main stack 1. See “CONTROL register” on page 52. 11.3.3 Core registers The processor core registers are:         +,./0121        .45,  ,5  .62,      '.,589,: .6.2 !"# $"% &"# (741,6.5 '"(! )*&) 44 )*&)  SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 14./ Table 11-2. Core register set summary Type Required privilege Name (1) (2) Reset value Description R0-R12 RW Either Unknown “General-purpose registers” on page 45 MSP RW Privileged See description “Stack Pointer” on page 45 PSP RW Either Unknown “Stack Pointer” on page 45 LR RW Either 0xFFFFFFFF “Link Register” on page 45 PC RW Either See description “Program Counter” on page 45 PSR RW Privileged 0x01000000 “Program Status Register” on page 46 ASPR RW Either 0x00000000 “Application Program Status Register” on page 47 IPSR RO Privileged 0x00000000 “Interrupt Program Status Register” on page 48 EPSR RO Privileged 0x01000000 “Execution Program Status Register” on page 48 PRIMASK RW Privileged 0x00000000 “Priority Mask Register” on page 49 FAULTMASK RW Privileged 0x00000000 “Fault Mask Register” on page 50 BASEPRI RW Privileged 0x00000000 “Base Priority Mask Register” on page 51 CONTROL RW Privileged 0x00000000 “CONTROL register” on page 52 1. 2. 11.3.3.1 Describes access type during program execution in thread mode and Handler mode. Debug access can differ. An entry of Either means privileged and unprivileged software can access the register. General-purpose registers R0-R12 are 32-bit general-purpose registers for data operations. 11.3.3.2 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to use:  0 = Main Stack Pointer (MSP). This is the reset value.  1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. 11.3.3.3 Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF. 11.3.3.4 Program Counter The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is always 0 because instruction fetches must be halfword aligned. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 45 11.3.3.5 Program Status Register The Program Status Register (PSR) combines:  Application Program Status Register (APSR)  Interrupt Program Status Register (IPSR)  Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments are: • APSR: 31 30 29 28 27 N Z C V Q 23 22 21 20 26 25 24 Reserved 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved • IPSR: 31 30 29 28 Reserved 23 22 21 20 Reserved 15 14 13 12 7 6 5 8 ISR_NUMBER Reserved 4 3 2 27 26 1 0 25 24 ISR_NUMBER • EPSR: 31 30 29 28 Reserved 23 22 ICI/IT 21 20 T 19 18 17 11 10 9 16 Reserved 15 14 13 12 ICI/IT 7 6 5 4 3 Reserved 46 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 8 Reserved 2 1 0 The PSR bit assignments are: 31 30 29 28 27 N Z C V Q 23 22 21 20 26 25 24 ICI/IT T 19 18 17 16 11 10 9 8 Reserved ISR_NUMBER 1 0 Reserved 15 14 13 12 ICI/IT 7 6 5 4 3 2 ISR_NUMBER Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:  read all of the registers using PSR with the MRS instruction  write to the APSR using APSR with the MSR instruction. The PSR combinations and attributes are: Table 11-3. PSR register combinations Register Type PSR RW (1), IEPSR RO IAPSR (2) APSR, EPSR, and IPSR EPSR and IPSR (1) APSR and IPSR (2) APSR and EPSR RW EAPSR 1. 2. Combination RW The processor ignores writes to the IPSR bits. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits. See the instruction descriptions “MRS” on page 138 and “MSR” on page 139 for more information about how to access the program status registers. 11.3.3.6 Application Program Status Register The APSR contains the current state of the condition flags from previous instruction executions. See the register summary in Table 11-2 on page 45 for its attributes. The bit assignments are: • N Negative or less than flag: 0 = operation result was positive, zero, greater than, or equal 1 = operation result was negative or less than. • Z Zero flag: 0 = operation result was not zero 1 = operation result was zero. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 47 • C Carry or borrow flag: 0 = add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1 = add operation resulted in a carry bit or subtract operation did not result in a borrow bit. • V Overflow flag: 0 = operation did not result in an overflow 1 = operation resulted in an overflow. • Q Sticky saturation flag: 0 = indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1 = indicates when an SSAT or USAT instruction results in saturation. This bit is cleared to zero by software using an MRS instruction. 11.3.3.7 Interrupt Program Status Register The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 11-2 on page 45 for its attributes. The bit assignments are: • ISR_NUMBER This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault 4 = Memory management fault 5 = Bus fault 6 = Usage fault 7-10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 50 = IRQ34 see “Exception types” on page 62 for more information. 11.3.3.8 Execution Program Status Register The EPSR contains the Thumb state bit, and the execution state bits for either the: 48  If-Then (IT) instruction  Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 See the register summary in Table 11-2 on page 45 for the EPSR attributes. The bit assignments are: • ICI Interruptible-continuable instruction bits, see “Interruptible-continuable instructions” on page 49. • IT Indicates the execution state bits of the IT instruction, see “IT” on page 128. • T Always set to 1. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are ignored. Fault handlers can examine EPSR value in the stacked PSR to indicate the operation that is at fault. See “Exception entry and return” on page 66 11.3.3.9 Interruptible-continuable instructions When an interrupt occurs during the execution of an LDM or STM instruction, the processor:  stops the load multiple or store multiple instruction operation temporarily  stores the next register operand in the multiple operation to EPSR bits[15:12]. After servicing the interrupt, the processor:  returns to the register pointed to by bits[15:12]  resumes execution of the multiple load or store instruction. When the EPSR holds ICI execution state, bits[26:25,11:10] are zero. 11.3.3.10 If-Then block The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” on page 128 for more information. 11.3.3.11 Exception mask registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS” on page 138, “MSR” on page 139, and “CPS” on page 134 for more information. 11.3.3.12 Priority Mask Register The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary in Table 11-2 on page 45 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved 0 PRIMASK SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 49 • PRIMASK 0 = no effect 1 = prevents the activation of all exceptions with configurable priority. 11.3.3.13 Fault Mask Register The FAULTMASK register prevents activation of all exceptions. See the register summary in Table 11-2 on page 45 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved • FAULTMASK 0 = no effect 1 = prevents the activation of all exceptions. The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler. 50 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 0 FAULTMASK 11.3.3.14 Base Priority Mask Register The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 11-2 on page 45 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 BASEPRI • BASEPRI Priority mask bits: 0x0000 = no effect Nonzero = defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI. This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” on page 153 for more information. Remember that higher priority field values correspond to lower exception priorities. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 51 11.3.3.15 CONTROL register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 11-2 on page 45 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Active Stack Pointer Thread Mode Privilege Level Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved • Active stack pointer Defines the current stack: 0 = MSP is the current stack pointer 1 = PSP is the current stack pointer. In Handler mode this bit reads as zero and ignores writes. • Thread mode privilege level Defines the Thread mode privilege level: 0 = privileged 1 = unprivileged. Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register. In an OS environment, ARM recommends that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack. By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see “MSR” on page 139. When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See “ISB” on page 137 52 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.3.4 Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See “Exception entry” on page 67 and “Exception return” on page 67 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller” on page 146 for more information. 11.3.5 Data types The processor:  supports the following data types: ̶ 32-bit words ̶ 16-bit halfwords ̶ 8-bit bytes  supports 64-bit data transfer instructions.  manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus (PPB) accesses are always little-endian. See “Memory regions, types and attributes” on page 54 for more information.  11.3.6 The Cortex Microcontroller Software Interface Standard For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:    a common way to: ̶ access peripheral registers ̶ define exception vectors the names of: ̶ the registers of the core peripherals ̶ the core exception vectors a device-independent interface for RTOS kernels, including a debug channel. The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3 processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack and a Flash file system. CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIScompliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. This document uses the register short names defined by the CMSIS. In a few cases these differ from the architectural short names that might be used in other documents. The following sections give more information about the CMSIS:  “Power management programming hints” on page 71  “Intrinsic functions” on page 75  “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 146  “NVIC programming hints” on page 158. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 53 11.4 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The memory map is: [)))))))) 9HQGRUVSHFLILF PHPRU\ 0% [( [())))) 3ULYDWHSHULSKHUDO 0% EXV [( ['))))))) ([WHUQDOGHYLFH *% [$ [))))))) ([WHUQDO5$0 [)))))) *% 0% %LWEDQGDOLDV [ [))))))) [ [))))) 0% %LWEDQGUHJLRQ [ 3HULSKHUDO *% [ [))))))) [)))))) 0% %LWEDQGDOLDV 65$0 *% [ [))))))) [ [))))) 0% %LWEDQGUHJLRQ [ &RGH *% [ The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see “Bit-banding” on page 58. The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see “About the Cortex-M3 peripherals” on page 145. This memory mapping is generic to ARM Cortex-M3 products. To get the specific memory mapping of this product, refer to the Memories section of the datasheet. 11.4.1 Memory regions, types and attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: 54 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.4.1.1 Normal The processor can re-order transactions for efficiency, or perform speculative reads. 11.4.1.2 Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. 11.4.1.3 Strongly-ordered The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. The additional memory attributes include. 11.4.1.4 Shareable For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, software must ensure data coherency between the bus masters. 11.4.1.5 Execute Never (XN) Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an XN region causes a memory management fault exception. 11.4.2 Memory system ordering of memory accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see “Software ordering of memory accesses” on page 57. However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses caused by two instructions is: 1RUPDO DFFHVV 1RQVKDUHDEOH 6KDUHDEOH 6WURQJO\ RUGHUHG DFFHVV 1RUPDODFFHVV     'HYLFHDFFHVVQRQVKDUHDEOH     'HYLFHDFFHVVVKDUHDEOH     6WURQJO\RUGHUHGDFFHVV     $ $ 'HYLFHDFFHVV Where: - Means that the memory system does not guarantee the ordering of the accesses. < Means that accesses are observed in program order, that is, A1 is always observed before A2. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 55 11.4.3 Behavior of memory accesses The behavior of accesses to each region in the memory map is: Table 11-4. Memory access behavior Address range Memory region Memory type XN Description 0x000000000x1FFFFFFF Code Normal (1) - Executable region for program code. You can also put data here. Executable region for data. You can also put code here. 0x200000000x3FFFFFFF SRAM Normal 0x400000000x5FFFFFFF Peripheral Device (1) XN This region includes bit band and bit band alias areas, see Table 11-6 on page 58. 0x600000000x9FFFFFFF External RAM Normal (1) - Executable region for data. 0xA00000000xDFFFFFFF External device Device (1) XN External Device memory 0xE00000000xE00FFFFF Private Peripheral Bus Stronglyordered (1) XN This region includes the NVIC, System timer, and system control block. 0xE01000000xFFFFFFFF Reserved Device (1) XN Reserved 1. (1) - This region includes bit band and bit band alias areas, see Table 11-6 on page 58. See “Memory regions, types and attributes” on page 54 for more information. The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory protection unit” on page 192. 11.4.3.1 Additional memory access constraints for shared memory When a system includes shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 11-5 shows: Table 11-5. Memory region share ability policies Address range Memory region Memory type Shareability 0x000000000x1FFFFFFF Code Normal (1) - 0x200000000x3FFFFFFF SRAM Normal (1) - 0x400000000x5FFFFFFF Peripheral (2) Device (1) - 0x600000000x7FFFFFFF WBWA (2) External RAM 0x800000000x9FFFFFFF 56 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Normal (1) WT (2) Table 11-5. Memory region share ability policies (Continued) Address range Memory region 0xA00000000xBFFFFFFF Memory type Shareability Shareable (1) External device Device (1) 0xC00000000xDFFFFFFF Nonshareable (1) 0xE00000000xE00FFFFF Private Peripheral Bus Stronglyordered(1) Shareable (1) - 0xE01000000xFFFFFFFF Vendor-specific device(2) Device (1) - - 1. 2. See “Memory regions, types and attributes” on page 54 for more information. The Peripheral and Vendor-specific device regions have no additional access constraints. 11.4.4 Software ordering of memory accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because:  the processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence.  the processor has multiple bus interfaces  memory or devices in the memory map have different wait states  some memory accesses are buffered or speculative. “Memory system ordering of memory accesses” on page 55 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions: 11.4.4.1 DMB The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See “DMB” on page 135. 11.4.4.2 DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB” on page 136. 11.4.4.3 ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See “ISB” on page 137. Use memory barrier instructions in, for example:  MPU programming: ̶ Use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. ̶ Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 57  Vector table. If the program changes an entry in the vector table, and then enables the corresponding exception, use a DMB instruction between the operations. This ensures that if the exception is taken immediately after being enabled the processor uses the new exception vector.  Self-modifying code. If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. This ensures subsequent instruction execution uses the updated program.  Memory map switching. If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. This ensures subsequent instruction execution uses the updated memory map.  Dynamic exception priority change. When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. This ensures the change takes effect on completion of the DSB instruction.  Using a semaphore in multi-master system. If the system contains more than one bus master, for example, if another processor is present in the system, each processor must use a DMB instruction after any semaphore instructions, to ensure other bus masters see the memory transactions in the order in which they were executed. Memory accesses to Strongly-ordered memory, such as the system control block, do not require the use of DMB instructions. 11.4.5 Bit-banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1MB of the SRAM and peripheral memory regions. The memory map has two 32MB alias regions that map to two 1MB bit-band regions:  accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown in Table 11-6  accesses to the 32MB peripheral alias region map to the 1MB peripheral bit-band region, as shown in Table 11-7. Table 11-6. SRAM memory bit-banding regions Address range Memory region 0x20000000- SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. SRAM bit-band alias Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. 0x200FFFFF 0x220000000x23FFFFFF Table 11-7. Instruction and data accesses Peripheral memory bit-banding regions Address range Memory region 0x40000000- Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. Peripheral bit-band region Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. 0x400FFFFF 0x420000000x43FFFFFF Instruction and data accesses A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bitband region. The following formula shows how the alias region maps onto the bit-band region: 58 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where:  Bit_word_offset is the position of the target bit in the bit-band memory region.  Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.  Bit_band_base is the starting address of the alias region.  Byte_offset is the number of the byte in the bit-band region that contains the targeted bit.  Bit_number is the bit position, 0-7, of the targeted bit. Figure 11-2 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bitband region:  The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0 = 0x22000000 + (0xFFFFF*32) + (0*4).  The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4).  The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0 *4).  The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C = 0x22000000+ (0*32) + (7*4). Figure 11-2. Bit-band mapping 0%DOLDVUHJLRQ [)))))& [))))) [))))) [))))) [))))(& [))))( [))))( [))))( [& [ [ [ [& [ [ [ 0%65$0ELWEDQGUHJLRQ           [)))))       [         [))))(         [         [))))'         [         [))))&         [ 11.4.5.1 Directly accessing an alias region Writing to a word in the alias region updates a single bit in the bit-band region. Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bitband region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit. Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. Reading a word in the alias region:  0x00000000 indicates that the targeted bit in the bit-band region is set to zero SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 59  0x00000001 indicates that the targeted bit in the bit-band region is set to 1 11.4.5.2 Directly accessing a bit-band region “Behavior of memory accesses” on page 56 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 11.4.6 Memory endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. or “Little-endian format” describes how words of data are stored in memory. 11.4.6.1 Little-endian format In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and the most significant byte at the highest-numbered byte. For example: 0HPRU\  5HJLVWHU   $GGUHVV$ % $ % $ % $ % OVE\WH   %   %   %  % PVE\WH 11.4.7 Synchronization primitives The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism. A pair of synchronization primitives comprises: 11.4.7.1 A Load-Exclusive instruction Used to read the value of a memory location, requesting exclusive access to that location. 11.4.7.2 A Store-Exclusive instruction Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is: 0: it indicates that the thread or process gained exclusive access to the memory, and the write succeeds, 1: it indicates that the thread or process did not gain exclusive access to the memory, and no write is performed, The pairs of Load-Exclusive and Store-Exclusive instructions are:  the word instructions LDREX and STREX  the halfword instructions LDREXH and STREXH  the byte instructions LDREXB and STREXB. Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 60  Use a Load-Exclusive instruction to read the value of the location.  Update the value, as required.  Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and tests the returned status bit. If this bit is: SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 0: The read-modify-write completed successfully, 1: No write was performed. This indicates that the value returned the first step might be out of date. The software must retry the read-modify-write sequence, Software can use the synchronization primitives to implement a semaphores as follows:  Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.  If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address.  If the returned status bit from the second step indicates that the Store-Exclusive succeeded then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed the first step. The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has executed a LoadExclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory locations addressed by exclusive accesses by each processor. The processor removes its exclusive access tag if:  It executes a CLREX instruction  It executes a Store-Exclusive instruction, regardless of whether the write succeeds.  An exception occurs. This means the processor can resolve semaphore conflicts between different threads. In a multiprocessor implementation:  executing a CLREX instruction removes only the local exclusive access tag for the processor  executing a Store-Exclusive instruction, or an exception. removes the local exclusive access tags, and all global exclusive access tags for the processor. For more information about the synchronization primitive instructions, see “LDREX and STREX” on page 97 and “CLREX” on page 99. 11.4.8 Programming hints for the synchronization primitives ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide intrinsic functions for generation of these instructions: Table 11-8. C compiler intrinsic functions for exclusive access instructions Instruction Intrinsic function LDREX, LDREXH, or LDREXB unsigned int __ldrex(volatile void *ptr) STREX, STREXH, or STREXB int __strex(unsigned int val, volatile void *ptr) CLREX void __clrex(void) The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic function. For example, the following C code generates the require LDREXB operation: __ldrex((volatile char *) 0xFF); 11.5 Exception model This section describes the exception model. 11.5.1 Exception states Each exception is in one of the following states: SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 61 11.5.1.1 Inactive The exception is not active and not pending. 11.5.1.2 Pending The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. 11.5.1.3 Active An exception that is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case both exceptions are in the active state. 11.5.1.4 Active and pending The exception is being serviced by the processor and there is a pending exception from the same source. 11.5.2 Exception types The exception types are: 11.5.2.1 Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. 11.5.2.2 Non Maskable Interrupt (NMI) A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be:   Masked or prevented from activation by any other exception. Preempted by any exception other than Reset. 11.5.2.3 Hard fault A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. 11.5.2.4 Memory management fault A memory management fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. 11.5.2.5 Bus fault A bus fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. 11.5.2.6 Usage fault A usage fault is an exception that occurs because of a fault related to instruction execution. This includes:  62 an undefined instruction SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15  an illegal unaligned access  invalid state on instruction execution  an error on exception return. The following can cause a usage fault when the core is configured to report them:  an unaligned address on word and halfword memory access  division by zero. 11.5.2.7 SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. 11.5.2.8 PendSV PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. 11.5.2.9 SysTick A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick. 11.5.2.10 Interrupt (IRQ) A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 11-9. Properties of the different exception types Exception number (1) IRQ number (1) Exception type Priority Vector address or offset (2) Activation 1 - Reset -3, the highest 0x00000004 Asynchronous 2 -14 NMI -2 0x00000008 Asynchronous 3 -13 Hard fault -1 0x0000000C - 4 -12 Memory management fault Configurable (3) 0x00000010 Synchronous 5 -11 Bus fault Configurable (3) 0x00000014 Synchronous when precise, asynchronous when imprecise 6 -10 Usage fault Configurable (3) 0x00000018 Synchronous 7-10 - - - Reserved - 0x0000002C Synchronous 11 -5 SVCall Configurable 12-13 - - - 14 -2 PendSV (3) Reserved - Configurable (3) 0x00000038 Asynchronous (3) 0x0000003C Asynchronous 0x00000040 and above (6) Asynchronous 15 -1 SysTick Configurable 16 and above 0 and above (4) Interrupt (IRQ) Configurable (5) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 63 1. 2. 3. 4. 5. 6. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register” on page 48. See “Vector table” on page 65 for more information. See “System Handler Priority Registers” on page 172. See the “Peripheral Identifiers” section of the datasheet. See “Interrupt Priority Registers” on page 153. Increasing in steps of 4. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 11-9 on page 63 shows as having configurable priority, see:  “System Handler Control and State Register” on page 175  “Interrupt Clear-enable Registers” on page 149. For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault handling” on page 68. 11.5.3 Exception handlers The processor handles exceptions using: 11.5.3.1 Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ34 are the exceptions handled by ISRs. 11.5.3.2 Fault handlers Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers. 11.5.3.3 System handlers NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 11.5.4 Vector table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 11-3 on page 65 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. 64 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Figure 11-3. Vector table Exception number IRQ number 45 29 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Vector Offset IRQ29 0x00B4 . . . 0x004C . . . IRQ2 0x0048 IRQ1 0x0044 IRQ0 0x0040 0x003C 0x0038 12 Systick PendSV Reserved Reserved for Debug 11 -5 10 SVCall 0x002C 9 Reserved 8 7 6 -10 5 -11 4 -12 3 -13 2 -14 1 0x0018 0x0014 0x0010 0x000C 0x0008 0x0004 0x0000 Usage fault Bus fault Memory management fault Hard fault Reserved Reset Initial SP value On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, see “Vector Table Offset Register” on page 166. 11.5.5 Exception priorities As Table 11-9 on page 63 shows, all exceptions have an associated priority, with:  a lower priority value indicating a higher priority  configurable priorities for all exceptions except Reset, Hard fault. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities see  “System Handler Priority Registers” on page 172  “Interrupt Priority Registers” on page 153. Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 65 When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 11.5.6 Interrupt priority grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields:  an upper field that defines the group priority  a lower field that defines a subpriority within the group. Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler, If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see “Application Interrupt and Reset Control Register” on page 167. 11.5.7 Exception entry and return Descriptions of exception handling use the following terms: 11.5.7.1 Preemption When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt priority grouping” on page 66 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception entry” on page 67 more information. 11.5.7.2 Return This occurs when the exception handler is completed, and:  there is no pending exception with sufficient priority to be serviced  the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception return” on page 67 for more information. 11.5.7.3 Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. 11.5.7.4 Late-arriving This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 66 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.5.7.5 Exception entry Exception entry occurs when there is a pending exception with sufficient priority and either:  the processor is in Thread mode  the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers, see “Exception mask registers” on page 49. An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred as stacking and the structure of eight data words is referred as stack frame. The stack frame contains the following information:  R0-R3, R12  Return address  PSR  LR. Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of the Configuration Control Register (CCR) is set to 1, stack align adjustment is performed during stacking. The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack frame and what operation mode the was processor was in before the entry occurred. If no higher priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case. 11.5.7.6 Exception return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:  a POP instruction that includes the PC  a BX instruction with any register.  an LDR or LDM instruction with the PC as the destination. EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 11-10 shows the EXC_RETURN[3:0] values with a description of the exception return behavior. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 67 The processor sets EXC_RETURN bits[31:4] to 0xFFFFFFF. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the exception return sequence. Table 11-10. Exception return behavior EXC_RETURN[3:0] Description bXXX0 Reserved. Return to Handler mode. b0001 Exception return gets state from MSP. Execution uses MSP after return. b0011 Reserved. b01X1 Reserved. Return to Thread mode. b1001 Exception return gets state from MSP. Execution uses MSP after return. Return to Thread mode. b1101 Exception return gets state from PSP. Execution uses PSP after return. b1X11 11.6 Reserved. Fault handling Faults are a subset of the exceptions, see “Exception model” on page 61. The following generate a fault: ̶ a bus error on: ̶ an instruction fetch or vector table load ̶ a data access  an internally-detected error such as an undefined instruction or an attempt to change state with a BX instruction  attempting to execute an instruction from a memory region marked as Non-Executable (XN).  an MPU fault because of a privilege violation or an attempt to access an unmanaged region. 11.6.1 Fault types Table 11-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. See “Configurable Fault Status Register” on page 177 for more information about the fault status registers. Table 11-11. Faults Fault Handler Bus error on a vector read Bit name Fault status register VECTTBL “Hard Fault Status Register” on page 183 Hard fault Fault escalated to a hard fault FORCED MPU mismatch: - on instruction access on data access during exception stacking during exception unstacking 68 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Memory managem ent fault IACCVIOL (1) DACCVIOL MSTKERR MUNSKERR “Memory Management Fault Address Register” on page 184 Table 11-11. Faults (Continued) Fault Handler Bus error: Bit name Fault status register - - during exception stacking STKERR during exception unstacking UNSTKERR during instruction prefetch Bus fault “Bus Fault Status Register” on page 179 IBUSERR Precise data bus error PRECISERR Imprecise data bus error IMPRECISER R Attempt to access a coprocessor NOCP Undefined instruction UNDEFINSTR Attempt to enter an invalid instruction set state (2) Usage fault INVSTATE Invalid EXC_RETURN value INVPC Illegal unaligned load or store UNALIGNED Divide By 0 DIVBYZERO 1. 2. “Usage Fault Status Register” on page 181 Occurs on an access to an XN region even if the MPU is disabled. Attempting to use an instruction set other than the Thumb instruction set. 11.6.2 Fault escalation and hard faults All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers” on page 172. Software can disable execution of the handlers for these faults, see “System Handler Control and State Register” on page 175. Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler. as described in “Exception model” on page 61. In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:  A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level.  A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler for the new fault cannot preempt the currently executing fault handler.  An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception.  A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 69 11.6.3 Fault status registers and fault address registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 11-12. Table 11-12. Fault status and fault address registers Handler Status register name Address register name Hard fault HFSR - Memory management fault MMFSR MMFAR Bus fault BFSR BFAR Usage fault UFSR - Register description “Hard Fault Status Register” on page 183 “Memory Management Fault Status Register” on page 178 “Memory Management Fault Address Register” on page 184 “Bus Fault Status Register” on page 179 “Bus Fault Address Register” on page 185 “Usage Fault Status Register” on page 181 11.6.4 Lockup The processor enters a lockup state if a hard fault occurs when executing the hard fault handlers. When the processor is in lockup state it does not execute any instructions. The processor remains in lockup state until:  11.7 it is reset Power management The Cortex-M3 processor sleep modes reduce power consumption:  Backup Mode  Wait Mode  Sleep Mode The SLEEPDEEP bit of the SCR selects which sleep mode is used, see “System Control Register” on page 169. For more information about the behavior of the sleep modes see “Low Power Modes” in the PMC section of the datasheet. This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 11.7.1 Entering sleep mode This section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 11.7.1.1 Wait for interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI instruction it stops executing instructions and enters sleep mode. See “WFI” on page 144 for more information. 70 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.7.1.2 Wait for event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event register. When the processor executes a WFE instruction, it checks this register:  if the register is 0 the processor stops executing instructions and enters sleep mode  if the register is 1 the processor clears the register to 0 and continues executing instructions without entering sleep mode. See “WFE” on page 143 for more information. 11.7.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the execution of an exception handler it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the processor to run when an exception occurs. 11.7.2 Wakeup from sleep mode The conditions for the processor to wakeup depend on the mechanism that cause it to enter sleep mode. 11.7.2.1 Wakeup from WFI or sleep-on-exit Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULTMASK see “Exception mask registers” on page 49. 11.7.2.2 Wakeup from WFE The processor wakes up if:  it detects an exception with sufficient priority to cause exception entry In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about the SCR see “System Control Register” on page 169. 11.7.3 Power management programming hints ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following intrinsic functions for these instructions: void __WFE(void) // Wait for Event void __WFE(void) // Wait for Interrupt SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 71 11.8 Instruction set summary The processor implements a version of the Thumb instruction set. Table 11-13 lists the supported instructions. In Table 11-13:  angle brackets, , enclose alternative forms of the operand  braces, {}, enclose optional operands  the Operands column is not exhaustive  Op2 is a flexible second operand that can be either a register or a constant  most instructions can use an optional condition code suffix. For more information on the instructions and operands, see the instruction descriptions. Table 11-13. 72 Cortex-M3 instructions Mnemonic Operands Brief description Flags Page ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V page 101 ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V page 101 ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V page 101 ADR Rd, label Load PC-relative address - page 85 AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C page 104 ASR, ASRS Rd, Rm, Arithmetic Shift Right N,Z,C page 105 B label Branch - page 125 BFC Rd, #lsb, #width Bit Field Clear - page 121 BFI Rd, Rn, #lsb, #width Bit Field Insert - page 121 BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C page 104 BKPT #imm Breakpoint - page 133 BL label Branch with Link - page 125 BLX Rm Branch indirect with Link - page 125 BX Rm Branch indirect - page 125 CBNZ Rn, label Compare and Branch if Non Zero - page 127 CBZ Rn, label Compare and Branch if Zero - page 127 CLREX - Clear Exclusive - page 99 CLZ Rd, Rm Count leading zeros - page 107 CMN, CMNS Rn, Op2 Compare Negative N,Z,C,V page 108 CMP, CMPS Rn, Op2 Compare N,Z,C,V page 108 CPSID iflags Change Processor State, Disable Interrupts - page 134 CPSIE iflags Change Processor State, Enable Interrupts - page 134 DMB - Data Memory Barrier - page 135 DSB - Data Synchronization Barrier - page 136 EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C page 104 ISB - Instruction Synchronization Barrier - page 137 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Table 11-13. Cortex-M3 instructions (Continued) Mnemonic Operands Brief description Flags Page IT - If-Then condition block - page 128 LDM Rn{!}, reglist Load Multiple registers, increment after - page 94 LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before - page 94 LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after - page 94 LDR Rt, [Rn, #offset] Load Register with word - page 89 LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte - page 89 LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes - page 89 LDREX Rt, [Rn, #offset] Load Register Exclusive - page 89 LDREXB Rt, [Rn] Load Register Exclusive with byte - page 89 LDREXH Rt, [Rn] Load Register Exclusive with halfword - page 89 LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword - page 89 LDRSB, LDRSBT Rt, [Rn, #offset] Load Register with signed byte - page 89 LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword - page 89 LDRT Rt, [Rn, #offset] Load Register with word - page 89 LSL, LSLS Rd, Rm, Logical Shift Left N,Z,C page 105 LSR, LSRS Rd, Rm, Logical Shift Right N,Z,C page 105 MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result - page 115 MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result - page 115 MOV, MOVS Rd, Op2 Move N,Z,C page 109 MOVT Rd, #imm16 Move Top - page 111 MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C page 109 MRS Rd, spec_reg Move from special register to general register - page 138 MSR spec_reg, Rm Move from general register to special register N,Z,C,V page 139 MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z page 115 MVN, MVNS Rd, Op2 Move NOT N,Z,C page 109 NOP - No Operation - page 140 ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C page 104 ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C page 104 POP reglist Pop registers from stack - page 96 PUSH reglist Push registers onto stack - page 96 RBIT Rd, Rn Reverse Bits - page 112 REV Rd, Rn Reverse byte order in a word - page 112 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 73 Table 11-13. 74 Cortex-M3 instructions (Continued) Mnemonic Operands Brief description Flags Page REV16 Rd, Rn Reverse byte order in each halfword - page 112 REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend - page 112 ROR, RORS Rd, Rm, Rotate Right N,Z,C page 105 RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C page 105 RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V page 101 SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V page 101 SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract - page 122 SDIV {Rd,} Rn, Rm Signed Divide - page 117 SEV - Send Event - page 141 SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result - page 116 SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result - page 116 SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q page 118 STM Rn{!}, reglist Store Multiple registers, increment after - page 94 STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before - page 94 STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after - page 94 STR Rt, [Rn, #offset] Store Register word - page 89 STRB, STRBT Rt, [Rn, #offset] Store Register byte - page 89 STRD Rt, Rt2, [Rn, #offset] Store Register two words - page 89 STREX Rd, Rt, [Rn, #offset] Store Register Exclusive - page 97 STREXB Rd, Rt, [Rn] Store Register Exclusive byte - page 97 STREXH Rd, Rt, [Rn] Store Register Exclusive halfword - page 97 STRH, STRHT Rt, [Rn, #offset] Store Register halfword - page 89 STRT Rt, [Rn, #offset] Store Register word - page 89 SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V page 101 SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V page 101 SVC #imm Supervisor Call - page 142 SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - page 123 SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - page 123 TBB [Rn, Rm] Table Branch Byte - page 130 TBH [Rn, Rm, LSL #1] Table Branch Halfword - page 130 TEQ Rn, Op2 Test Equivalence N,Z,C page 113 TST Rn, Op2 Test N,Z,C page 113 UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract - page 122 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Table 11-13. 11.9 Cortex-M3 instructions (Continued) Mnemonic Operands Brief description Flags Page UDIV {Rd,} Rn, Rm Unsigned Divide - page 117 UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate (32 x 32 + 64), 64-bit result - page 116 UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 x 32), 64-bit result - page 116 USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q page 118 UXTB {Rd,} Rm {,ROR #n} Zero extend a byte - page 123 UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword - page 123 WFE - Wait For Event - page 143 WFI - Wait For Interrupt - page 144 Intrinsic functions ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, you might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ANSI cannot directly access: Table 11-14. CMSIS intrinsic functions to generate some Cortex-M3 instructions Instruction CMSIS intrinsic function CPSIE I void __enable_irq(void) CPSID I void __disable_irq(void) CPSIE F void __enable_fault_irq(void) CPSID F void __disable_fault_irq(void) ISB void __ISB(void) DSB void __DSB(void) DMB void __DMB(void) REV uint32_t __REV(uint32_t int value) REV16 uint32_t __REV16(uint32_t int value) REVSH uint32_t __REVSH(uint32_t int value) RBIT uint32_t __RBIT(uint32_t int value) SEV void __SEV(void) WFE void __WFE(void) WFI void __WFI(void) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 75 The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 11-15. CMSIS intrinsic functions to access the special registers Special register Access CMSIS function Read uint32_t __get_PRIMASK (void) Write void __set_PRIMASK (uint32_t value) Read uint32_t __get_FAULTMASK (void) Write void __set_FAULTMASK (uint32_t value) Read uint32_t __get_BASEPRI (void) Write void __set_BASEPRI (uint32_t value) Read uint32_t __get_CONTROL (void) Write void __set_CONTROL (uint32_t value) Read uint32_t __get_MSP (void) Write void __set_MSP (uint32_t TopOfMainStack) Read uint32_t __get_PSP (void) Write void __set_PSP (uint32_t TopOfProcStack) PRIMASK FAULTMASK BASEPRI CONTROL MSP PSP 11.10 About the instruction descriptions The following sections give more information about using the instructions:  “Operands” on page 76  “Restrictions when using PC or SP” on page 76  “Flexible second operand” on page 77  “Shift Operations” on page 78  “Address alignment” on page 80  “PC-relative expressions” on page 80  “Conditional execution” on page 80  “Instruction width selection” on page 82. 11.10.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible in that they can either be a register or a constant. See “Flexible second operand” . 11.10.2 Restrictions when using PC or SP Many instructions have restrictions on whether you can use the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register. See instruction descriptions for more information. Bit[0] of any address you write to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M3 processor only supports Thumb instructions. 76 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.10.3 Flexible second operand Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction. Operand2 can be a:  “Constant”  “Register with optional shift” on page 77 11.10.3.1 Constant You specify an Operand2 constant in the form: #constant where constant can be:  any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word  any constant of the form 0x00XY00XY  any constant of the form 0xXY00XY00  any constant of the form 0xXYXYXYXY. In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions. When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant. 11.10.3.2 Instruction substitution Your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2. 11.10.3.3 Register with optional shift You specify an Operand2 register in the form: Rm {, shift} where: Rm is the register holding the data for the second operand. shift is an optional shift to be applied to Rm. It can be one of: ASR #n arithmetic shift right n bits, 1 ≤ n ≤ 32. LSL #n logical shift left n bits, 1 ≤ n ≤ 31. LSR #n logical shift right n bits, 1 ≤ n ≤ 32. ROR #n rotate right n bits, 1 ≤ n ≤ 31. RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If you omit the shift, or specify LSL #0, the instruction uses the value in Rm. If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 77 carry flag when used with certain instructions. For information on the shift operations and how they affect the carry flag, see “Shift Operations” 11.10.4 Shift Operations Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed:  directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register  during the calculation of Operand2 by the instructions that specify the second operand as a register with shift, see “Flexible second operand” on page 77. The result is used by the instruction. The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or “Flexible second operand” on page 77. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length. 11.10.4.1 ASR Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result. See Figure 11-4 on page 78. You can use the ASR #n operation to divide the value in the register Rm by 2n, with the result being rounded towards negative-infinity. When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.  If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.  If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm. Figure 11-4. ASR #3 &DUU\ )ODJ         11.10.4.2 LSR Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the righthand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 11-5. You can use the LSR #n operation to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer. When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm. 78  If n is 32 or more, then all the bits in the result are cleared to 0.  If n is 33 or more and the carry flag is updated, it is updated to 0. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Figure 11-5. LSR #3   &DUU\ )ODJ          11.10.4.3 LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0. See Figure 11-6 on page 79. You can use he LSL #n operation to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning. When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.  If n is 32 or more, then all the bits in the result are cleared to 0.  If n is 33 or more and the carry flag is updated, it is updated to 0. Figure 11-6. LSL #3           &DUU\ )ODJ  11.10.4.4 ROR Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result. And it moves the right-hand n bits of the register into the left-hand n bits of the result. See Figure 11-7. When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm.  If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.  ROR with shift length, n, more than 32 is the same as ROR with shift length n-32. Figure 11-7. ROR #3 &DUU\ )ODJ         SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 79 11.10.4.5 RRX Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result. See Figure 11-8 on page 80. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm. Figure 11-8. RRX &DUU\ )ODJ       11.10.5 Address alignment An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. The Cortex-M3 processor supports unaligned access only for the following instructions:  LDR, LDRT  LDRH, LDRHT  LDRSH, LDRSHT  STR, STRT  STRH, STRHT All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address aligned. For more information about usage faults see “Fault handling” on page 68. Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see “Configuration and Control Register” on page 170. 11.10.6 PC-relative expressions A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error.  For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.  For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.  Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number]. 11.10.7 Conditional execution Most data processing instructions can optionally update the condition flags in the Application Program Status Register (APSR) according to the result of the operation, see “Application Program Status Register” on page 47. 80 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect. You can execute an instruction conditionally, based on the condition flags set in another instruction, either:  immediately after the instruction that updated the flags  after any number of intervening instructions that have not updated the flags. Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 11-16 on page 82 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction:  does not execute  does not write any value to its destination register  does not affect any of the flags  does not generate any exception. Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” on page 128 for more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might automatically insert an IT instruction if you have conditional instructions outside the IT block. Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result. This section describes:  “The condition flags”  “Condition code suffixes” . 11.10.7.1 The condition flags The APSR contains the following condition flags: N Set to 1 when the result of the operation was negative, cleared to 0 otherwise. Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise. C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise. V Set to 1 when the operation caused overflow, cleared to 0 otherwise. For more information about the APSR see “Program Status Register” on page 46. A carry occurs:  if the result of an addition is greater than or equal to 232  if the result of a subtraction is positive or zero  as the result of an inline barrel shifter operation in a move or logical instruction. Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than –231. Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more information. 11.10.7.2 Condition code suffixes The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. Table 11-16 shows the condition codes to use. You can use conditional execution with the IT instruction to reduce the number of branch instructions in code. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 81 Table 11-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 11-16. Condition code suffixes Suffix Flags Meaning EQ Z=1 Equal NE Z=0 Not equal CS or HS C=1 Higher or same, unsigned ≥ CC or LO C=0 Lower, unsigned < MI N=1 Negative PL N=0 Positive or zero VS V=1 Overflow VC V=0 No overflow HI C = 1 and Z = 0 Higher, unsigned > LS C = 0 or Z = 1 Lower or same, unsigned ≤ GE N=V Greater than or equal, signed ≥ LT N != V Less than, signed < GT Z = 0 and N = V Greater than, signed > LE Z = 1 and N != V Less than or equal, signed ≤ AL Can have any value Always. This is the default when no suffix is specified. 11.10.7.3 Absolute value The example below shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1). MOVS IT RSBMI R0, R1 MI R0, R1, #0 ; R0 = R1, setting flags ; IT instruction for the negative condition ; If negative, R0 = -R1 11.10.7.4 Compare and update value The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3. CMP ITT CMPGT MOVGT R0, R1 GT R2, R3 R4, R5 ; ; ; ; Compare R0 and R1, setting flags IT instruction for the two GT conditions If 'greater than', compare R2 and R3, setting flags If still 'greater than', do R4 = R5 11.10.8 Instruction width selection There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, you can force a specific instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding. If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error. In some cases it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding. 82 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.10.8.1 Instruction width selection To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The example below shows instructions with the instruction width suffix. BCS.W label ; creates a 32-bit instruction even for a short branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 83 11.11 Memory access instructions Table 11-17 shows the memory access instructions: Table 11-17. 84 Memory access instructions Mnemonic Brief description See ADR Load PC-relative address “ADR” on page 85 CLREX Clear Exclusive “CLREX” on page 99 LDM{mode} Load Multiple registers “LDM and STM” on page 94 LDR{type} Load Register using immediate offset “LDR and STR, immediate offset” on page 86 LDR{type} Load Register using register offset “LDR and STR, register offset” on page 89 LDR{type}T Load Register with unprivileged access “LDR and STR, unprivileged” on page 91 LDR Load Register using PC-relative address “LDR, PC-relative” on page 92 LDREX{type} Load Register Exclusive “LDREX and STREX” on page 97 POP Pop registers from stack “PUSH and POP” on page 96 PUSH Push registers onto stack “PUSH and POP” on page 96 STM{mode} Store Multiple registers “LDM and STM” on page 94 STR{type} Store Register using immediate offset “LDR and STR, immediate offset” on page 86 STR{type} Store Register using register offset “LDR and STR, register offset” on page 89 STR{type}T Store Register with unprivileged access “LDR and STR, unprivileged” on page 91 STREX{type} Store Register Exclusive “LDREX and STREX” on page 97 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.11.1 ADR Load PC-relative address. 11.11.1.1 Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. label is a PC-relative expression. See “PC-relative expressions” on page 80. 11.11.1.2 Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative. If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that bit[0] of the address you generate is set to1 for correct execution. Values of label must be within the range of −4095 to +4095 from the address in the PC. You might have to use the .W suffix to get the maximum offset range or to generate addresses that are not wordaligned. See “Instruction width selection” on page 82. 11.11.1.3 Restrictions Rd must not be SP and must not be PC. 11.11.1.4 Condition flags This instruction does not change the flags. 11.11.1.5 Examples ADR R1, TextMessage ; Write address value of a location labelled as ; TextMessage to R1 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 85 11.11.2 LDR and STR, immediate offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. 11.11.2.1 Syntax op{type}{cond} Rt, op{type}{cond} Rt, op{type}{cond} Rt, opD{cond} Rt, Rt2, opD{cond} Rt, Rt2, opD{cond} Rt, Rt2, [Rn {, #offset}] [Rn, #offset]! [Rn], #offset [Rn {, #offset}] [Rn, #offset]! [Rn], #offset ; ; ; ; ; ; immediate offset pre-indexed post-indexed immediate offset, two words pre-indexed, two words post-indexed, two words where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional execution” on page 80. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn. If offset is omitted, the address is the contents of Rn. Rt2 is the additional register to load or store for two-word operations. 11.11.2.2 Operation LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes: 11.11.2.3 Offset addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is: [Rn, #offset] 11.11.2.4 Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! 11.11.2.5 Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: 86 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 [Rn], #offset The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 80. Table 11-18 shows the ranges of offset for immediate, pre-indexed and post-indexed forms. Table 11-18. Offset ranges Instruction type Immediate offset Pre-indexed Post-indexed Word, halfword, signed halfword, byte, or signed byte −255 to 4095 −255 to 255 −255 to 255 Two words multiple of 4 in the range −1020 to 1020 multiple of 4 in the range −1020 to 1020 multiple of 4 in the range −1020 to 1020 11.11.2.6 Restrictions For load instructions:  Rt can be SP or PC for word loads only  Rt must be different from Rt2 for two-word loads  Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. When Rt is PC in a word load instruction:  bit[0] of the loaded value must be 1 for correct execution  a branch occurs to the address created by changing bit[0] of the loaded value to 0  if the instruction is conditional, it must be the last instruction in the IT block. For store instructions:  Rt can be SP for word stores only  Rt must not be PC  Rn must not be PC  Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. 11.11.2.7 Condition flags These instructions do not change the flags. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 87 11.11.2.8 Examples 88 LDR LDRNE R8, [R10] R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 ; ; ; ; ; ; ; ; ; ; ; ; ; ; SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095. Store R3 as halfword data into address in R4, then increment R4 by 4 Load R8 from a word 32 bytes above the address in R3, and load R9 from a word 36 bytes above the address in R3 Store R0 to address in R8, and store R1 to a word 4 bytes above the address in R8, and then decrement R8 by 16. 11.11.3 LDR and STR, register offset Load and Store with register offset. 11.11.3.1 Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional execution” on page 80. Rt is the register to load or store. Rn is the register on which the memory address is based. Rm is a register containing a value to be used as the offset. LSL #n is an optional shift, with n in the range 0 to 3. 11.11.3.2 Operation LDR instructions load a register with a value from memory. STR instructions store a register value into memory. The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 80. 11.11.3.3 Restrictions In these instructions:  Rn must not be PC  Rm must not be SP and must not be PC  Rt can be SP only for word loads and word stores  Rt can be PC only for word loads. When Rt is PC in a word load instruction:  bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address  if the instruction is conditional, it must be the last instruction in the IT block. 11.11.3.4 Condition flags These instructions do not change the flags. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 89 11.11.3.5 Examples STR LDRSB STR 90 R0, [R5, R1] ; ; R0, [R5, R1, LSL #1] ; ; ; R0, [R1, R2, LSL #2] ; ; Store value of R0 into an address equal to sum of R5 and R1 Read byte value from an address equal to sum of R5 and two times R1, sign extended it to a word value and put it in R0 Stores R0 to an address equal to sum of R1 and four times R2 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.11.4 LDR and STR, unprivileged Load and Store with unprivileged access. 11.11.4.1 Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional execution” on page 80. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn. 11.11.4.2 Operation These load and store instructions perform the same function as the memory access instructions with immediate offset, see “LDR and STR, immediate offset” on page 86. The difference is that these instructions have only unprivileged access even when used in privileged software. When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset. 11.11.4.3 Restrictions In these instructions:  Rn must not be PC  Rt must not be SP and must not be PC. 11.11.4.4 Condition flags These instructions do not change the flags. 11.11.4.5 Examples STRBTEQ R4, [R7] LDRHT R2, [R2, #8] ; ; ; ; Conditionally store least significant byte in R4 to an address in R7, with unprivileged access Load halfword value from an address equal to sum of R2 and 8 into R2, with unprivileged access SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 91 11.11.5 LDR, PC-relative Load register from memory. 11.11.5.1 Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional execution” on page 80. Rt is the register to load or store. Rt2 is the second register to load or store. label is a PC-relative expression. See “PC-relative expressions” on page 80. 11.11.5.2 Operation LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address alignment” on page 80. label must be within a limited range of the current instruction. Table 11-19 shows the possible offsets between label and the PC. Table 11-19. Offset ranges Instruction type Offset range Word, halfword, signed halfword, byte, signed byte −4095 to 4095 Two words −1020 to 1020 You might have to use the .W suffix to get the maximum offset range. See “Instruction width selection” on page 82. 11.11.5.3 Restrictions In these instructions:  Rt can be SP or PC only for word loads  Rt2 must not be SP and must not be PC  Rt must be different from Rt2. When Rt is PC in a word load instruction: 92  bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address  if the instruction is conditional, it must be the last instruction in the IT block. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.11.5.4 Condition flags These instructions do not change the flags. 11.11.5.5 Examples LDR R0, LookUpTable LDRSB R7, localdata ; ; ; ; ; Load R0 with a word of data from an address labelled as LookUpTable Load a byte value from an address labelled as localdata, sign extend it to a word value, and put it in R7 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 93 11.11.6 LDM and STM Load and Store Multiple registers. 11.11.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM Load Multiple registers. STM Store Multiple registers. addr_mode is any one of the following: IA Increment address After each access. This is the default. DB Decrement address Before each access. cond is an optional condition code, see “Conditional execution” on page 80. Rn is the register on which the memory addresses are based. ! is an optional writeback suffix. If ! is present the final address, that is loaded from or stored to, is written back into Rn. reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range, see “Examples” on page 95. LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending stacks. LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks. STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending stacks. STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks 11.11.6.2 Operation LDM instructions load the registers in reglist with word values from memory addresses based on Rn. STM instructions store the word values in the registers in reglist to memory addresses based on Rn. For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” on page 96 for details. 11.11.6.3 Restrictions In these instructions:  94 Rn must not be PC SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15  reglist must not contain SP  in any STM instruction, reglist must not contain PC  in any LDM instruction, reglist must not contain PC if it contains LR  reglist must not contain Rn if you specify the writeback suffix. When PC is in reglist in an LDM instruction:  bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address  if the instruction is conditional, it must be the last instruction in the IT block. 11.11.6.4 Condition flags These instructions do not change the flags. 11.11.6.5 Examples LDM STMDB R8,{R0,R2,R9} ; LDMIA is a synonym for LDM R1!,{R3-R6,R11,R12} 11.11.6.6 Incorrect examples STM LDM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable R2, {} ; There must be at least one register in the list SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 95 11.11.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. 11.11.7.1 Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional execution” on page 80. reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range. PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred mnemonics in these cases. 11.11.7.2 Operation PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. See “LDM and STM” on page 94 for more information. 11.11.7.3 Restrictions In these instructions:  reglist must not contain SP  for the PUSH instruction, reglist must not contain PC  for the POP instruction, reglist must not contain PC if it contains LR. When PC is in reglist in a POP instruction:  bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address  if the instruction is conditional, it must be the last instruction in the IT block. 11.11.7.4 Condition flags These instructions do not change the flags. 11.11.7.5 Examples PUSH PUSH POP 96 {R0,R4-R7} {R2,LR} {R0,R10,PC} SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.11.8 LDREX and STREX Load and Store Register Exclusive. 11.11.8.1 Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the value in Rn. 11.11.8.2 Operation LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address. STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address. The address used in any Store-Exclusive instruction must be the same as the address in the most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see “Synchronization primitives” on page 60 If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is guaranteed that no other process in the system has accessed the memory location between the Load-exclusive and Store-Exclusive instructions. For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and StoreExclusive instruction to a minimum. The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding Load-Exclusive instruction is unpredictable. 11.11.8.3 Restrictions In these instructions:  do not use PC  do not use SP for Rd and Rt  for STREX, Rd must be different from both Rt and Rn  the value of offset must be a multiple of four in the range 0-1020. 11.11.8.4 Condition flags These instructions do not change the flags. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 97 11.11.8.5 Examples MOV R1, #0x1 ; Initialize the ‘lock taken’ value LDREX CMP ITT STREXEQ CMPEQ BNE .... R0, R0, EQ R0, R0, try ; ; ; ; ; ; ; try 98 [LockAddr] #0 R1, [LockAddr] #0 Load the lock value Is the lock free? IT instruction for STREXEQ and CMPEQ Try and claim the lock Did this succeed? No – try again Yes – we have the lock SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.11.9 CLREX Clear Exclusive. 11.11.9.1 Syntax CLREX{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.11.9.2 Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation. See “Synchronization primitives” on page 60 for more information. 11.11.9.3 Condition flags These instructions do not change the flags. 11.11.9.4 Examples CLREX SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 99 11.12 General data processing instructions Table 11-20 shows the data processing instructions: Table 11-20. 100 Data processing instructions Mnemonic Brief description See ADC Add with Carry “ADD, ADC, SUB, SBC, and RSB” on page 101 ADD Add “ADD, ADC, SUB, SBC, and RSB” on page 101 ADDW Add “ADD, ADC, SUB, SBC, and RSB” on page 101 AND Logical AND “AND, ORR, EOR, BIC, and ORN” on page 104 ASR Arithmetic Shift Right “ASR, LSL, LSR, ROR, and RRX” on page 105 BIC Bit Clear “AND, ORR, EOR, BIC, and ORN” on page 104 CLZ Count leading zeros “CLZ” on page 107 CMN Compare Negative “CMP and CMN” on page 108 CMP Compare “CMP and CMN” on page 108 EOR Exclusive OR “AND, ORR, EOR, BIC, and ORN” on page 104 LSL Logical Shift Left “ASR, LSL, LSR, ROR, and RRX” on page 105 LSR Logical Shift Right “ASR, LSL, LSR, ROR, and RRX” on page 105 MOV Move “MOV and MVN” on page 109 MOVT Move Top “MOVT” on page 111 MOVW Move 16-bit constant “MOV and MVN” on page 109 MVN Move NOT “MOV and MVN” on page 109 ORN Logical OR NOT “AND, ORR, EOR, BIC, and ORN” on page 104 ORR Logical OR “AND, ORR, EOR, BIC, and ORN” on page 104 RBIT Reverse Bits “REV, REV16, REVSH, and RBIT” on page 112 REV Reverse byte order in a word “REV, REV16, REVSH, and RBIT” on page 112 REV16 Reverse byte order in each halfword “REV, REV16, REVSH, and RBIT” on page 112 REVSH Reverse byte order in bottom halfword and sign extend “REV, REV16, REVSH, and RBIT” on page 112 ROR Rotate Right “ASR, LSL, LSR, ROR, and RRX” on page 105 RRX Rotate Right with Extend “ASR, LSL, LSR, ROR, and RRX” on page 105 RSB Reverse Subtract “ADD, ADC, SUB, SBC, and RSB” on page 101 SBC Subtract with Carry “ADD, ADC, SUB, SBC, and RSB” on page 101 SUB Subtract “ADD, ADC, SUB, SBC, and RSB” on page 101 SUBW Subtract “ADD, ADC, SUB, SBC, and RSB” on page 101 TEQ Test Equivalence “TST and TEQ” on page 113 TST Test “TST and TEQ” on page 113 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.12.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 11.12.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. A Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 80. cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 77 for details of the options. imm12 is any value in the range 0-4095. 11.12.1.2 Operation The ADD instruction adds the value of Operand2 or imm12 to the value in Rn. The ADC instruction adds the values in Rn and Operand2, together with the carry flag. The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn. The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one. The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2. Use ADC and SBC to synthesize multiword arithmetic, see “Multiword arithmetic examples” on page 103. See also “ADR” on page 85. ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses the imm12 operand. 11.12.1.3 Restrictions In these instructions:  Operand2 must not be SP and must not be PC  Rd can be SP only in ADD and SUB, and only with the additional restrictions: ̶ Rn must also be SP ̶ any shift in Operand2 must be limited to a maximum of 3 bits using LSL  Rn can be SP only in ADD and SUB  Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where: SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 101 ̶ you must not specify the S suffix ̶ Rm must not be PC and must not be SP ̶  if the instruction is conditional, it must be the last instruction in the IT block with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: ̶ you must not specify the S suffix ̶ the second operand must be a constant in the range 0 to 4095. ̶ ̶ When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to b00 before performing the calculation, making the base address for the calculation word-aligned. ̶ If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. ARM recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because your assembler automatically calculates the correct constant for the ADR instruction. When Rd is PC in the ADD{cond} PC, PC, Rm instruction:  bit[0] of the value written to the PC is ignored  a branch occurs to the address created by forcing bit[0] of that value to 0. 11.12.1.4 Condition flags If S is specified, these instructions update the N, Z, C and V flags according to the result. 11.12.1.5 Examples ADD SUBS RSB ADCHI 102 R2, R1, R3 R8, R6, #240 R4, R4, #1280 R11, R0, R3 ; ; ; ; Sets the flags on the result Subtracts contents of R4 from 1280 Only executed if C flag set and Z flag clear SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.12.1.6 Multiword arithmetic examples 11.12.1.7 64-bit addition The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5. ADDS ADC R4, R0, R2 R5, R1, R3 ; add the least significant words ; add the most significant words with carry 11.12.1.8 96-bit subtraction Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2. SUBS SBCS SBC R6, R6, R9 R9, R2, R1 R2, R8, R11 ; subtract the least significant words ; subtract the middle words with carry ; subtract the most significant words with carry SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 103 11.12.2 AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. 11.12.2.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND logical AND. ORR logical OR, or bit set. EOR logical Exclusive OR. BIC logical AND NOT, or bit clear. ORN logical OR NOT. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 80. cond is an optional condition code, see See “Conditional execution” on page 80.. Rd is the destination register. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 77 for details of the options. 11.12.2.2 Operation The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2. The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. 11.12.2.3 Restrictions Do not use SP and do not use PC. 11.12.2.4 Condition flags If S is specified, these instructions: 104  update the N and Z flags according to the result  can update the C flag during the calculation of Operand2, see “Flexible second operand” on page 77  do not affect the V flag. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.12.2.5 Examples AND ORREQ ANDS EORS BIC ORN ORNS R9, R2, R9, R7, R0, R7, R7, R2, #0xFF00 R0, R5 R8, #0x19 R11, #0x18181818 R1, #0xab R11, R14, ROR #4 R11, R14, ASR #32 11.12.3 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 11.12.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 80. Rd is the destination register. Rm is the register holding the value to be shifted. Rs is the register holding the shift length to apply to the value in Rm. Only the least significant byte is used and can be in the range 0 to 255. n is the shift length. The range of shift length depends on the instruction: ASR shift length from 1 to 32 LSL shift length from 0 to 31 LSR shift length from 1 to 32 ROR shift length from 1 to 31. MOV{S}{cond} Rd, Rm is the preferred syntax for LSL{S}{cond} Rd, Rm, #0. 11.12.3.2 Operation ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by constant n or register Rs. RRX moves the bits in register Rm to the right by 1. In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on what result is generated by the different instructions, see “Shift Operations” on page 78. 11.12.3.3 Restrictions Do not use SP and do not use PC. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 105 11.12.3.4 Condition flags If S is specified:  these instructions update the N and Z flags according to the result  the C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” on page 78. 11.12.3.5 Examples ASR LSLS LSR ROR RRX 106 R7, R1, R4, R4, R4, R8, R2, R5, R5, R5 #9 #3 #6 R6 ; ; ; ; ; Arithmetic shift right by 9 bits Logical shift left by 3 bits with flag update Logical shift right by 6 bits Rotate right by the value in the bottom byte of R6 Rotate right with extend SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.12.4 CLZ Count Leading Zeros. 11.12.4.1 Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. Rm is the operand register. 11.12.4.2 Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set in the source register, and zero if bit[31] is set. 11.12.4.3 Restrictions Do not use SP and do not use PC. 11.12.4.4 Condition flags This instruction does not change the flags. 11.12.4.5 Examples CLZ CLZNE R4,R9 R2,R3 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 107 11.12.5 CMP and CMN Compare and Compare Negative. 11.12.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional execution” on page 80. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 77 for details of the options. 11.12.5.2 Operation These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not write the result to a register. The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS instruction, except that the result is discarded. The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction, except that the result is discarded. 11.12.5.3 Restrictions In these instructions:  do not use PC  Operand2 must not be SP. 11.12.5.4 Condition flags These instructions update the N, Z, C and V flags according to the result. 11.12.5.5 Examples CMP CMN CMPGT 108 R2, R9 R0, #6400 SP, R7, LSL #2 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.12.6 MOV and MVN Move and Move NOT. 11.12.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 80. cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. Operand2 is a flexible second operand. See “Flexible second operand” on page 77 for details of the options. imm16 is any value in the range 0-65535. 11.12.6.2 Operation The MOV instruction copies the value of Operand2 into Rd. When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the corresponding shift instruction:  ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n  LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0  LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n  ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n  RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX. Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:  MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs  MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs  MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs  MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs See “ASR, LSL, LSR, ROR, and RRX” on page 105. The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd. The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 operand. 11.12.6.3 Restrictions You can use SP and PC only in the MOV instruction, with the following restrictions:  the second operand must be a register without shift  you must not specify the S suffix. When Rd is PC in a MOV instruction:  bit[0] of the value written to the PC is ignored  a branch occurs to the address created by forcing bit[0] of that value to 0. Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM instruction set. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 109 11.12.6.4 Condition flags If S is specified, these instructions:  update the N and Z flags according to the result  can update the C flag during the calculation of Operand2, see “Flexible second operand” on page 77  do not affect the V flag. 11.12.6.5 Example MOVS MOV MOVS MOV MOV MVNS 110 R11, #0x000B R1, #0xFA05 R10, R12 R3, #23 R8, SP R2, #0xF ; ; ; ; ; ; ; Write value of 0x000B to R11, flags get updated Write value of 0xFA05 to R1, flags are not updated Write value in R12 to R10, flags get updated Write value of 23 to R3 Write value of stack pointer to R8 Write value of 0xFFFFFFF0 (bitwise inverse of 0xF) to the R2 and update flags SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.12.7 MOVT Move Top. 11.12.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. imm16 is a 16-bit immediate constant. 11.12.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT instruction pair enables you to generate any 32-bit constant. 11.12.7.3 Restrictions Rd must not be SP and must not be PC. 11.12.7.4 Condition flags This instruction does not change the flags. 11.12.7.5 Examples MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword ; and APSR are unchanged SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 111 11.12.8 REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 11.12.8.1 Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. Rn is the register holding the operand. 11.12.8.2 Operation Use these instructions to change endianness of data: REV converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian data. REV16 converts 16-bit big-endian data into little-endian data or 16-bit little-endian data into big-endian data. REVSH converts either: 16-bit signed big-endian data into 32-bit signed little-endian data 16-bit signed little-endian data into 32-bit signed big-endian data. 11.12.8.3 Restrictions Do not use SP and do not use PC. 11.12.8.4 Condition flags These instructions do not change the flags. 11.12.8.5 Examples REV REV16 REVSH REVHS RBIT 112 R3, R0, R0, R3, R7, R7 R0 R5 R7 R8 ; ; ; ; ; Reverse Reverse Reverse Reverse Reverse byte order of value in R7 and write it to R3 byte order of each 16-bit halfword in R0 Signed Halfword with Higher or Same condition bit order of value in R8 and write the result to R7 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.12.9 TST and TEQ Test bits and Test Equivalence. 11.12.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional execution” on page 80. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible second operand” on page 77 for details of the options. 11.12.9.2 Operation These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register. The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as the ANDS instruction, except that it discards the result. To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0. The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. This is the same as the EORS instruction, except that it discards the result. Use the TEQ instruction to test if two values are equal without affecting the V or C flags. TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands. 11.12.9.3 Restrictions Do not use SP and do not use PC. 11.12.9.4 Condition flags These instructions:  update the N and Z flags according to the result  can update the C flag during the calculation of Operand2, see “Flexible second operand” on page 77  do not affect the V flag. 11.12.9.5 Examples TST R0, #0x3F8 TEQEQ R10, R9 ; ; ; ; Perform bitwise AND of R0 value to 0x3F8, APSR is updated but result is discarded Conditionally test if value in R10 is equal to value in R9, APSR is updated but result is discarded SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 113 11.13 Multiply and divide instructions Table 11-21 shows the multiply and divide instructions: Table 11-21. 114 Multiply and divide instructions Mnemonic Brief description See MLA Multiply with Accumulate, 32-bit result “MUL, MLA, and MLS” on page 115 MLS Multiply and Subtract, 32-bit result “MUL, MLA, and MLS” on page 115 MUL Multiply, 32-bit result “MUL, MLA, and MLS” on page 115 SDIV Signed Divide “SDIV and UDIV” on page 117 SMLAL Signed Multiply with Accumulate (32x32+64), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 116 SMULL Signed Multiply (32x32), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 116 UDIV Unsigned Divide “SDIV and UDIV” on page 117 UMLAL Unsigned Multiply with Accumulate (32x32+64), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 116 UMULL Unsigned Multiply (32x32), 64-bit result “UMULL, UMLAL, SMULL, and SMLAL” on page 116 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.13.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. 11.13.1.1 Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional execution” on page 80. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional execution” on page 80. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be added or subtracted from. 11.13.1.2 Operation The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd. The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32 bits of the result in Rd. The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and places the least significant 32 bits of the result in Rd. The results of these instructions do not depend on whether the operands are signed or unsigned. 11.13.1.3 Restrictions In these instructions, do not use SP and do not use PC. If you use the S suffix with the MUL instruction:  Rd, Rn, and Rm must all be in the range R0 to R7  Rd must be the same as Rm  you must not use the cond suffix. 11.13.1.4 Condition flags If S is specified, the MUL instruction:  updates the N and Z flags according to the result  does not affect the C and V flags. 11.13.1.5 Examples MUL MLA MULS MULLT MLS R10, R2, R5 R10, R2, R1, R5 R0, R2, R2 R2, R3, R2 R4, R5, R6, R7 ; ; ; ; ; Multiply, R10 Multiply with Multiply with Conditionally Multiply with = R2 x R5 accumulate, R10 = flag update, R0 = multiply, R2 = R3 subtract, R4 = R7 (R2 x R1) + R5 R2 x R2 x R2 - (R5 x R6) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 115 11.13.2 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. 11.13.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional execution” on page 80. RdHi, RdLo are the destination registers. For UMLAL and SMLAL they also hold the accumulating value. Rn, Rm are registers holding the operands. 11.13.2.2 Operation The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. 11.13.2.3 Restrictions In these instructions:  do not use SP and do not use PC  RdHi and RdLo must be different registers. 11.13.2.4 Condition flags These instructions do not affect the condition code flags. 11.13.2.5 Examples UMULL SMLAL 116 R0, R4, R5, R6 R4, R5, R3, R8 ; Unsigned (R4,R0) = R5 x R6 ; Signed (R5,R4) = (R5,R4) + R3 x R8 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.13.3 SDIV and UDIV Signed Divide and Unsigned Divide. 11.13.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. 11.13.3.2 Operation SDIV performs a signed integer division of the value in Rn by the value in Rm. UDIV performs an unsigned integer division of the value in Rn by the value in Rm. For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero. 11.13.3.3 Restrictions Do not use SP and do not use PC. 11.13.3.4 Condition flags These instructions do not change the flags. 11.13.3.5 Examples SDIV UDIV R0, R2, R4 R8, R8, R1 ; Signed divide, R0 = R2/R4 ; Unsigned divide, R8 = R8/R1 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 117 11.14 Saturating instructions This section describes the saturating instructions, SSAT and USAT. 11.14.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 11.14.1.1 Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 to 32 for SSAT n ranges from 0 to 31 for USAT. Rm is the register containing the value to saturate. shift #s is an optional shift applied to Rm before saturating. It must be one of the following: ASR #s where s is in the range 1 to 31 LSL #s where s is in the range 0 to 31. 11.14.1.2 Operation These instructions saturate to a signed or unsigned n-bit value. The SSAT instruction applies the specified shift, then saturates to the signed range −2n–1 ≤ x ≤ 2n–1−1. The USAT instruction applies the specified shift, then saturates to the unsigned range 0 ≤ x ≤ 2n−1. For signed n-bit saturation using SSAT, this means that:  if the value to be saturated is less than −2n−1, the result returned is −2n-1  if the value to be saturated is greater than 2n−1−1, the result returned is 2n-1−1  otherwise, the result returned is the same as the value to be saturated. For unsigned n-bit saturation using USAT, this means that:  if the value to be saturated is less than 0, the result returned is 0  if the value to be saturated is greater than 2n−1, the result returned is 2n−1  otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, you must use the MSR instruction, see “MSR” on page 139. To read the state of the Q flag, use the MRS instruction, see “MRS” on page 138. 11.14.1.3 Restrictions Do not use SP and do not use PC. 118 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.14.1.4 Condition flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. 11.14.1.5 Examples SSAT R7, #16, R7, LSL #4 USATNE R0, #7, R5 ; ; ; ; ; Logical shift left value in R7 by 4, then saturate it as a signed 16-bit value and write it back to R7 Conditionally saturate value in R5 as an unsigned 7 bit value and write it to R0 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 119 11.15 Bitfield instructions Table 11-22 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 11-22. 120 Packing and unpacking instructions Mnemonic Brief description See BFC Bit Field Clear “BFC and BFI” on page 121 BFI Bit Field Insert “BFC and BFI” on page 121 SBFX Signed Bit Field Extract “SBFX and UBFX” on page 122 SXTB Sign extend a byte “SXT and UXT” on page 123 SXTH Sign extend a halfword “SXT and UXT” on page 123 UBFX Unsigned Bit Field Extract “SBFX and UBFX” on page 122 UXTB Zero extend a byte “SXT and UXT” on page 123 UXTH Zero extend a halfword “SXT and UXT” on page 123 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.15.1 BFC and BFI Bit Field Clear and Bit Field Insert. 11.15.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32−lsb. 11.15.1.2 Operation BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are unchanged. BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged. 11.15.1.3 Restrictions Do not use SP and do not use PC. 11.15.1.4 Condition flags These instructions do not affect the flags. 11.15.1.5 Examples BFC BFI R4, #8, #12 R9, R2, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0 ; Replace bit 8 to bit 19 (12 bits) of R9 with ; bit 0 to bit 11 from R2 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 121 11.15.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 11.15.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32−lsb. 11.15.2.2 Operation SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register. UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination register. 11.15.2.3 Restrictions Do not use SP and do not use PC. 11.15.2.4 Condition flags These instructions do not affect the flags. 11.15.2.5 Examples SBFX UBFX 122 R0, R1, #20, #4 ; ; R8, R11, #9, #10 ; ; Extract bit 20 to bit 23 (4 bits) from R1 and sign extend to 32 bits and then write the result to R0. Extract bit 9 to bit 18 (10 bits) from R11 and zero extend to 32 bits and then write the result to R8 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.15.3 SXT and UXT Sign extend and Zero extend. 11.15.3.1 Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits. ROR #24 Value from Rm is rotated right 24 bits. If ROR #n is omitted, no rotation is performed. 11.15.3.2 Operation These instructions do the following:  Rotate the value from Rm right by 0, 8, 16 or 24 bits.  Extract bits from the resulting value: SXTB extracts bits[7:0] and sign extends to 32 bits. UXTB extracts bits[7:0] and zero extends to 32 bits. SXTH extracts bits[15:0] and sign extends to 32 bits. UXTH extracts bits[15:0] and zero extends to 32 bits. 11.15.3.3 Restrictions Do not use SP and do not use PC. 11.15.3.4 Condition flags These instructions do not affect the flags. 11.15.3.5 Examples SXTH R4, R6, ROR #16 UXTB R3, R10 ; ; ; ; ; Rotate R6 right by 16 bits, then obtain the lower halfword of the result and then sign extend to 32 bits and write the result to R4. Extract lowest byte of the value in R10 and zero extend it, and write the result to R3 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 123 11.16 Branch and control instructions Table 11-23 shows the branch and control instructions: Table 11-23. 124 Branch and control instructions Mnemonic Brief description See B Branch “B, BL, BX, and BLX” on page 125 BL Branch with Link “B, BL, BX, and BLX” on page 125 BLX Branch indirect with Link “B, BL, BX, and BLX” on page 125 BX Branch indirect “B, BL, BX, and BLX” on page 125 CBNZ Compare and Branch if Non Zero “CBZ and CBNZ” on page 127 CBZ Compare and Branch if Non Zero “CBZ and CBNZ” on page 127 IT If-Then “IT” on page 128 TBB Table Branch Byte “TBB and TBH” on page 130 TBH Table Branch Halfword “TBB and TBH” on page 130 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.16.1 B, BL, BX, and BLX Branch instructions. 11.16.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional execution” on page 80. label is a PC-relative expression. See “PC-relative expressions” on page 80. Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must be 1, but the address to branch to is created by changing bit[0] to 0. 11.16.1.2 Operation All these instructions cause a branch to label, or to the address indicated in Rm. In addition:  The BL and BLX instructions write the address of the next instruction to LR (the link register, R14).  The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0. Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT” on page 128. Table 11-24 shows the ranges for the various branch instructions. Table 11-24. Branch ranges Instruction Branch range B label −16 MB to +16 MB Bcond label (outside IT block) −1 MB to +1 MB Bcond label (inside IT block) −16 MB to +16 MB BL{cond} label −16 MB to +16 MB BX{cond} Rm Any value in register BLX{cond} Rm Any value in register You might have to use the .W suffix to get the maximum branch range. See “Instruction width selection” on page 82. 11.16.1.3 Restrictions The restrictions are:  do not use PC in the BLX instruction  for BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 125  when any of these instructions is inside an IT block, it must be the last instruction of the IT block. Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch range when it is inside an IT block. 11.16.1.4 Condition flags These instructions do not change the flags. 11.16.1.5 Examples 126 B BLE B.W BEQ BEQ.W BL loopA ng target target target funC BX BXNE BLX LR R0 R0 ; ; ; ; ; ; ; ; ; ; ; Branch to loopA Conditionally branch to label ng Branch to target within 16MB range Conditionally branch to target Conditionally branch to target within 1MB Branch with link (Call) to function funC, return address stored in LR Return from function call Conditionally branch to address stored in R0 Branch with link and exchange (Call) to a address stored in R0 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.16.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 11.16.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. 11.16.2.2 Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions. CBZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BEQ label CBNZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BNE label 11.16.2.3 Restrictions The restrictions are:  Rn must be in the range of R0 to R7  the branch destination must be within 4 to 130 bytes after the instruction  these instructions must not be used inside an IT block. 11.16.2.4 Condition flags These instructions do not change the flags. 11.16.2.5 Examples CBZ CBNZ R5, target ; Forward branch if R5 is zero R0, target ; Forward branch if R0 is not zero SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 127 11.16.3 IT If-Then condition instruction. 11.16.3.1 Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then. Applies the condition cond to the instruction. E Else. Applies the inverse condition of cond to the instruction. It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E. 11.16.3.2 Operation The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT block. The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their syntax. Your assembler might be able to generate the required IT instructions for conditional instructions automatically, so that you do not need to write them yourself. See your assembler documentation for details. A BKPT instruction in an IT block is always executed, even if its condition fails. Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked PSR. Instructions designed for use for exception returns can be used as normal to return from the exception, and execution of the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to branch to an instruction in an IT block. 11.16.3.3 Restrictions The following instructions are not permitted in an IT block:  IT  CBZ and CBNZ  CPSID and CPSIE. Other restrictions when using an IT block are:  128 a branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: ̶ ADD PC, PC, Rm ̶ MOV PC, Rm ̶ B, BL, BX, BLX ̶ any LDM, LDR, or POP instruction that writes to the PC SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 ̶ TBB and TBH  do not branch to any instruction inside an IT block, except when returning from an exception handler  all conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one  each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block. Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them. 11.16.3.4 Condition flags This instruction does not change the flags. 11.16.3.5 Example ITTE ANDNE ADDSNE MOVEQ NE R0, R0, R1 R2, R2, #1 R2, R3 ; ; ; ; Next 3 instructions are conditional ANDNE does not update condition flags ADDSNE updates condition flags Conditional move CMP R0, #9 ITE ADDGT ADDLE GT R1, R0, #55 R1, R0, #48 ; ; ; ; ; Convert R0 hex value (0 to 15) into ASCII ('0'-'9', 'A'-'F') Next 2 instructions are conditional Convert 0xA -> 'A' Convert 0x0 -> '0' IT GT ; IT block with only one conditional instruction ADDGT R1, R1, #1 ; Increment R1 conditionally ITTEE MOVEQ ADDEQ ANDNE BNE.W EQ R0, R1 R2, R2, #10 R3, R3, #1 dloop ; ; ; ; ; ; IT ADD NE R0, R0, R1 ; Next instruction is conditional ; Syntax error: no condition code used in IT block Next 4 instructions are conditional Conditional move Conditional add Conditional AND Branch instruction can only be used in the last instruction of an IT block SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 129 11.16.4 TBB and TBH Table Branch Byte and Table Branch Halfword. 11.16.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. Rm is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table. 11.16.4.2 Operation These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the address of the byte immediately after the TBB or TBH instruction. 11.16.4.3 Restrictions The restrictions are:  Rn must not be SP  Rm must not be SP and must not be PC  when any of these instructions is used inside an IT block, it must be the last instruction of the IT block. 11.16.4.4 Condition flags These instructions do not change the flags. 130 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.16.4.5 Examples ADR.W R0, BranchTable_Byte TBB [R0, R1] ; R1 is the index, R0 is the base address of the ; branch table Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 ; Case1 offset calculation DCB ((Case2-Case1)/2) ; Case2 offset calculation DCB ((Case3-Case1)/2) ; Case3 offset calculation TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 131 11.17 Miscellaneous instructions Table 11-25 shows the remaining Cortex-M3 instructions: Table 11-25. 132 Miscellaneous instructions Mnemonic Brief description See BKPT Breakpoint “BKPT” on page 133 CPSID Change Processor State, Disable Interrupts “CPS” on page 134 CPSIE Change Processor State, Enable Interrupts “CPS” on page 134 DMB Data Memory Barrier “DMB” on page 135 DSB Data Synchronization Barrier “DSB” on page 136 ISB Instruction Synchronization Barrier “ISB” on page 137 MRS Move from special register to register “MRS” on page 138 MSR Move from register to special register “MSR” on page 139 NOP No Operation “NOP” on page 140 SEV Send Event “SEV” on page 141 SVC Supervisor Call “SVC” on page 142 WFE Wait For Event “WFE” on page 143 WFI Wait For Interrupt “WFI” on page 144 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.17.1 BKPT Breakpoint. 11.17.1.1 Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 11.17.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition specified by the IT instruction. 11.17.1.3 Condition flags This instruction does not change the flags. 11.17.1.4 Examples BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can ; extract the immediate value by locating it using the PC) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 133 11.17.2 CPS Change Processor State. 11.17.2.1 Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register. iflags is a sequence of one or more flags: i Set or clear PRIMASK. f Set or clear FAULTMASK. 11.17.2.2 Operation CPS changes the PRIMASK and FAULTMASK special register values. See “Exception mask registers” on page 49 for more information about these registers. 11.17.2.3 Restrictions The restrictions are:  use CPS only from privileged software, it has no effect if used in unprivileged software  CPS cannot be conditional and so must not be used inside an IT block. 11.17.2.4 Condition flags This instruction does not change the condition flags. 11.17.2.5 Examples CPSID CPSID CPSIE CPSIE 134 i f i f ; ; ; ; Disable interrupts and configurable fault handlers (set PRIMASK) Disable interrupts and all fault handlers (set FAULTMASK) Enable interrupts and configurable fault handlers (clear PRIMASK) Enable interrupts and fault handlers (clear FAULTMASK) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.17.3 DMB Data Memory Barrier. 11.17.3.1 Syntax DMB{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.17.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory. 11.17.3.3 Condition flags This instruction does not change the flags. 11.17.3.4 Examples DMB ; Data Memory Barrier SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 135 11.17.4 DSB Data Synchronization Barrier. 11.17.4.1 Syntax DSB{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.17.4.2 Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. 11.17.4.3 Condition flags This instruction does not change the flags. 11.17.4.4 Examples DSB ; Data Synchronisation Barrier 136 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.17.5 ISB Instruction Synchronization Barrier. 11.17.5.1 Syntax ISB{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.17.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ISB instruction has been completed. 11.17.5.3 Condition flags This instruction does not change the flags. 11.17.5.4 Examples ISB ; Instruction Synchronisation Barrier SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 137 11.17.6 MRS Move the contents of a special register to a general-purpose register. 11.17.6.1 Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional execution” on page 80. Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 11.17.6.2 Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag. In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence. BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction. See “MSR” on page 139. 11.17.6.3 Restrictions Rd must not be SP and must not be PC. 11.17.6.4 Condition flags This instruction does not change the flags. 11.17.6.5 Examples MRS 138 R0, PRIMASK ; Read PRIMASK value and write it to R0 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.17.7 MSR Move the contents of a general-purpose register into the specified special register. 11.17.7.1 Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see “Conditional execution” on page 80. Rn is the source register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 11.17.7.2 Operation The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR, see “Application Program Status Register” on page 47. Privileged software can access all special registers. In unprivileged software writes to unallocated or execution state bits in the PSR are ignored. When you write to BASEPRI_MAX, the instruction writes to BASEPRI only if either:  Rn is non-zero and the current BASEPRI value is 0  Rn is non-zero and less than the current BASEPRI value. See “MRS” on page 138. 11.17.7.3 Restrictions Rn must not be SP and must not be PC. 11.17.7.4 Condition flags This instruction updates the flags explicitly based on the value in Rn. 11.17.7.5 Examples MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 139 11.17.8 NOP No Operation. 11.17.8.1 Syntax NOP{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.17.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. 11.17.8.3 Condition flags This instruction does not change the flags. 11.17.8.4 Examples NOP 140 ; No operation SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.17.9 SEV Send Event. 11.17.9.1 Syntax SEV{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.17.9.2 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see “Power management” on page 70. 11.17.9.3 Condition flags This instruction does not change the flags. 11.17.9.4 Examples SEV ; Send Event SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 141 11.17.10SVC Supervisor Call. 11.17.10.1 Syntax SVC{cond} #imm where: cond is an optional condition code, see “Conditional execution” on page 80. imm is an expression evaluating to an integer in the range 0-255 (8-bit value). 11.17.10.2 Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested. 11.17.10.3 Condition flags This instruction does not change the flags. 11.17.10.4 Examples SVC 142 0x32 ; Supervisor Call (SVC handler can extract the immediate value ; by locating it via the stacked PC) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.17.11WFE Wait For Event. 11.17.11.1 Syntax WFE{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.17.11.2 Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs:  an exception, unless masked by the exception mask registers or the current priority level  an exception enters the Pending state, if SEVONPEND in the System Control Register is set  a Debug Entry request, if Debug is enabled  an event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction. If the event register is 1, WFE clears it to 0 and returns immediately. For more information see “Power management” on page 70. 11.17.11.3 Condition flags This instruction does not change the flags. 11.17.11.4 Examples WFE ; Wait for event SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 143 11.17.12WFI Wait for Interrupt. 11.17.12.1 Syntax WFI{cond} where: cond is an optional condition code, see “Conditional execution” on page 80. 11.17.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs:  an exception  a Debug Entry request, regardless of whether Debug is enabled. 11.17.12.3 Condition flags This instruction does not change the flags. 11.17.12.4 Examples WFI ; Wait for interrupt 144 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.18 About the Cortex-M3 peripherals The address map of the Private peripheral bus (PPB) is: Table 11-26. Core peripheral register regions Address Core peripheral Description 0xE000E008-0xE000E00F System control block Table 11-30 on page 158 0xE000E010-0xE000E01F System timer Table 11-33 on page 187 0xE000E100-0xE000E4EF Nested Vectored Interrupt Controller Table 11-27 on page 146 0xE000ED00-0xE000ED3F System control block Table 11-30 on page 158 0xE000ED90-0xE000EDB8 Memory protection unit Table 11-35 on page 193 0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller Table 11-27 on page 146 In register descriptions:   the register type is described as follows: RW Read and write. RO Read-only. WO Write-only. the required privilege gives the privilege level required to access the register, as follows: Privileged Only privileged software can access the register. Unprivileged Both unprivileged and privileged software can access the register. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 145 11.19 Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports:  1 to 35 interrupts.  A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.  Level detection of interrupt signals.  Dynamic reprioritization of interrupts.  Grouping of priority values into group priority and subpriority fields.  Interrupt tail-chaining. The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC registers is: Table 11-27. NVIC register summary Address Name Type Required privilege Reset value Description 0xE000E1000xE000E104 ISER0- RW Privileged 0x00000000 “Interrupt Set-enable Registers” on page 148 0xE000E1800xE000E184 ICER0ICER1 RW Privileged 0x00000000 “Interrupt Clear-enable Registers” on page 149 0xE000E2000xE000E204 ISPR0- RW Privileged 0x00000000 “Interrupt Set-pending Registers” on page 150 0xE000E2800xE000E284 ICPR0ICPR1 RW Privileged 0x00000000 “Interrupt Clear-pending Registers” on page 151 0xE000E3000xE000E304 IABR0IABR1 RO Privileged 0x00000000 “Interrupt Active Bit Registers” on page 152 0xE000E400- IPR0- 0xE000E41C IPR8 RW Privileged 0x00000000 “Interrupt Priority Registers” on page 153 0xE000EF00 STIR 0x00000000 “Software Trigger Interrupt Register” on page 156 1. ISER1 ISPR1 WO Configurable (1) See the register description for more information. 11.19.1 The CMSIS mapping of the Cortex-M3 NVIC registers To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:  the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit integers, so that: ̶ ̶ ̶ 146 the array ISER[0] to ISER[1] corresponds to the registers ISER0-ISER1 the array ICER[0] to ICER[1] corresponds to the registers ICER0-ICER1 the array ISPR[0] to ISPR[1] corresponds to the registers ISPR0-ISPR1 ̶ the array ICPR[0] to ICPR[1] corresponds to the registers ICPR0-ICPR1 ̶ the array IABR[0] to IABR[1] corresponds to the registers IABR0-IABR1 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15  the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[34] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds the interrupt priority for interrupt n. The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For more information see the description of the NVIC_SetPriority function in “NVIC programming hints” on page 158. Table 11-28 shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt. Table 11-28. Mapping of interrupts to the interrupt variables CMSIS array elements (1) Interrupts Set-enable Clear-enable Set-pending Clear-pending Active Bit 0-34 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0] 35-63 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1] 1. Each array element corresponds to a single NVIC register, for example the element ICER[0] corresponds to the ICER0 register. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 147 11.19.2 Interrupt Set-enable Registers The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See:  the register summary in Table 11-27 on page 146 for the register attributes  Table 11-28 on page 147 for which interrupts are controlled by each register. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETENA bits 23 22 21 20 SETENA bits 15 14 13 12 SETENA bits 7 6 5 4 SETENA bits • SETENA Interrupt set-enable bits. Write: 0 = no effect 1 = enable interrupt. Read: 0 = interrupt disabled 1 = interrupt enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. 148 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.19.3 Interrupt Clear-enable Registers The ICER0-ICER1 register disables interrupts, and shows which interrupts are enabled. See:  the register summary in Table 11-27 on page 146 for the register attributes  Table 11-28 on page 147 for which interrupts are controlled by each register The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA • CLRENA Interrupt clear-enable bits. Write: 0 = no effect 1 = disable interrupt. Read: 0 = interrupt disabled 1 = interrupt enabled. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 149 11.19.4 Interrupt Set-pending Registers The ISPR0-ISPR1 register forces interrupts into the pending state, and shows which interrupts are pending. See:  the register summary in Table 11-27 on page 146 for the register attributes  Table 11-28 on page 147 for which interrupts are controlled by each register. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETPEND 23 22 21 20 SETPEND 15 14 13 12 SETPEND 7 6 5 4 SETPEND • SETPEND Interrupt set-pending bits. Write: 0 = no effect. 1 = changes interrupt state to pending. Read: 0 = interrupt is not pending. 1 = interrupt is pending. Writing 1 to the ISPR bit corresponding to: • an interrupt that is pending has no effect • a disabled interrupt sets the state of that interrupt to pending 150 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.19.5 Interrupt Clear-pending Registers The ICPR0-ICPR1 register removes the pending state from interrupts, and show which interrupts are pending. See:  the register summary in Table 11-27 on page 146 for the register attributes  Table 11-28 on page 147 for which interrupts are controlled by each register. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRPEND 23 22 21 20 CLRPEND 15 14 13 12 CLRPEND 7 6 5 4 CLRPEND • CLRPEND Interrupt clear-pending bits. Write: 0 = no effect. 1 = removes pending state an interrupt. Read: 0 = interrupt is not pending. 1 = interrupt is pending. Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 151 11.19.6 Interrupt Active Bit Registers The IABR0-IABR1 register indicates which interrupts are active. See:  the register summary in Table 11-27 on page 146 for the register attributes  Table 11-28 on page 147 for which interrupts are controlled by each register. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACTIVE 23 22 21 20 ACTIVE 15 14 13 12 ACTIVE 7 6 5 4 ACTIVE • ACTIVE Interrupt active flags: 0 = interrupt not active 1 = interrupt active. A bit reads as one if the status of the corresponding interrupt is active or active and pending. 152 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.19.7 Interrupt Priority Registers The IPR0-IPR8 registers provide a 4-bit priority field for each interrupt (See the “Peripheral Identifiers” section of the datasheet for more details). These registers are byte-accessible. See the register summary in Table 11-27 on page 146 for their attributes. Each register holds four priority fields, that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[34], as shown: 11.19.7.1 IPRm 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IP[4m+3] 23 22 21 20 IP[4m+2] 15 14 13 12 IP[4m+1] 7 6 5 4 IP[4m] 11.19.7.2 IPR4 31 30 29 28 IP[19] 23 22 21 20 IP[18] 15 14 13 12 Reserved 7 6 5 4 Reserved 11.19.7.3 IPR3 31 30 29 28 IP[15] 23 22 21 20 IP[14] 15 14 13 12 IP[13] 7 6 5 4 IP[12] SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 153 11.19.7.4 IPR2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IP[11] 23 22 21 20 IP[10] 15 14 13 12 IP[9] 7 6 5 4 IP[8] 11.19.7.5 IPR1 31 30 29 28 Reserved 23 22 21 20 IP[6] 15 14 13 12 IP[5] 7 6 5 4 IP[4] 11.19.7.6 IPR0 31 30 29 28 IP[3] 23 22 21 20 IP[2] 15 14 13 12 IP[1] 7 6 5 4 IP[0] • Priority, byte offset 3 • Priority, byte offset 2 • Priority, byte offset 1 • Priority, byte offset 0 Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes. See “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 146 for more information about the IP[0] to IP[34] interrupt priority array, that provides the software view of the interrupt priorities. Find the IPR number and byte offset for interrupt N as follows: • the corresponding IPR number, M, is given by M = N DIV 4 154 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 • the byte offset of the required Priority field in this register is N MOD 4, where: – byte offset 0 refers to register bits[7:0] – byte offset 1 refers to register bits[15:8] – byte offset 2 refers to register bits[23:16] – byte offset 3 refers to register bits[31:24]. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 155 11.19.8 Software Trigger Interrupt Register Write to the STIR to generate a Software Generated Interrupt (SGI). See the register summary in Table 11-27 on page 146 for the STIR attributes. When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see “System Control Register” on page 169. Only privileged software can enable unprivileged access to the STIR. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 8 INTID 4 3 2 1 INTID • INTID Interrupt ID of the required SGI, in the range 0-239. For example, a value of b000000011 specifies interrupt IRQ3. 156 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 0 11.19.9 Level-sensitive interrupts The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the processor enters the ISR, it automatically removes the pending state from the interrupt, see “Hardware and software control of interrupts” . For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 11.19.9.1 Hardware and software control of interrupts The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:  the NVIC detects that the interrupt signal is HIGH and the interrupt is not active  the NVIC detects a rising edge on the interrupt signal  software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending Registers” on page 150, or to the STIR to make an SGI pending, see “Software Trigger Interrupt Register” on page 156. A pending interrupt remains pending until one of the following: The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then: ̶ ̶  For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. Software writes to the corresponding interrupt clear-pending register bit. For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 157 11.19.10NVIC design hints and tips Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter pending state even it is disabled. Before programming VTOR to relocate the vector table, ensure the vector table entries of the new vector table are setup for fault handlers and all enabled exception like interrupts. For more information see “Vector Table Offset Register” on page 166. 11.19.10.1 NVIC programming hints Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 11-29. CMSIS functions for NVIC control CMSIS interrupt control function Description void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping void NVIC_EnableIRQ(IRQn_t IRQn) Enable IRQn void NVIC_DisableIRQ(IRQn_t IRQn) Disable IRQn uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn) Return true if IRQn is pending void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status uint32_t NVIC_GetActive (IRQn_t IRQn) Return the IRQ number of the active interrupt void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn void NVIC_SystemReset (void) Reset the system For more information about these functions see the CMSIS documentation. 11.20 System control block The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 11-30. Summary of the system control block registers Address Name Type Required privilege Reset value Description 0xE000E008 ACTLR RW Privileged 0x00000000 “Auxiliary Control Register” on page 161 0xE000ED00 CPUID RO Privileged 0x412FC230 “CPUID Base Register” on page 162 0xE000ED04 ICSR RW (1) Privileged 0x00000000 “Interrupt Control and State Register” on page 163 0xE000ED08 VTOR RW Privileged 0x00000000 “Vector Table Offset Register” on page 166 158 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Table 11-30. Summary of the system control block registers (Continued) Address Name Type Required privilege Reset value 0xE000ED0C AIRCR RW (1) Privileged 0xFA050000 “Application Interrupt and Reset Control Register” on page 167 0xE000ED10 SCR RW Privileged 0x00000000 “System Control Register” on page 169 0xE000ED14 CCR RW Privileged 0x00000200 “Configuration and Control Register” on page 170 0xE000ED18 SHPR1 RW Privileged 0x00000000 “System Handler Priority Register 1” on page 173 0xE000ED1C SHPR2 RW Privileged 0x00000000 “System Handler Priority Register 2” on page 174 0xE000ED20 SHPR3 RW Privileged 0x00000000 “System Handler Priority Register 3” on page 174 0xE000ED24 SHCRS RW Privileged 0x00000000 “System Handler Control and State Register” on page 175 0xE000ED28 CFSR RW Privileged 0x00000000 “Configurable Fault Status Register” on page 177 0xE000ED28 MMSR(2) RW Privileged 0x00 “Memory Management Fault Address Register” on page 184 0xE000ED29 BFSR (2) RW Privileged 0x00 “Bus Fault Status Register” on page 179 0xE000ED2A UFSR (2) RW Privileged 0x0000 “Usage Fault Status Register” on page 181 0xE000ED2C HFSR RW Privileged 0x00000000 “Hard Fault Status Register” on page 183 0xE000ED34 MMAR RW Privileged Unknown “Memory Management Fault Address Register” on page 184 0xE000ED38 BFAR RW Privileged Unknown “Bus Fault Address Register” on page 185 Notes: Description 1. See the register description for more information. 2. A subregister of the CFSR. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 159 11.20.1 The CMSIS mapping of the Cortex-M3 SCB registers To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the CMSIS, the byte array SHP[0] to SHP[12] corresponds to the registers SHPR1-SHPR3. 160 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.2 Auxiliary Control Register The ACTLR provides disable bits for the following processor functions:  IT folding  write buffer use for accesses to the default memory map  interruption of multi-cycle instructions. See the register summary in Table 11-30 on page 158 for the ACTLR attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 DISFOLD 1 DISDEFWBUF 0 DISMCYCINT Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 Reserved 4 • DISFOLD When set to 1, disables IT folding. see “About IT folding” on page 161 for more information. • DISDEFWBUF When set to 1, disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus faults but decreases performance because any store to memory must complete before the processor can execute the next instruction. This bit only affects write buffers implemented in the Cortex-M3 processor. • DISMCYCINT When set to 1, disables interruption of load multiple and store multiple instructions. This increases the interrupt latency of the processor because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. 11.20.2.1 About IT folding In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable IT folding. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 161 11.20.3 CPUID Base Register The CPUID register contains the processor part number, version, and implementation information. See the register summary in Table 11-30 on page 158 for its attributes. The bit assignments are: 31 30 29 28 27 26 19 18 25 24 17 16 9 8 1 0 Implementer 23 22 21 20 Variant 15 14 Constant 13 12 11 10 3 2 PartNo 7 6 5 4 PartNo • Implementer Implementer code: 0x41 = ARM • Variant Variant number, the r value in the rnpn product revision identifier: 0x2 = r2p0 • Constant Reads as 0xF • PartNo Part number of the processor: 0xC23 = Cortex-M3 • Revision Revision number, the p value in the rnpn product revision identifier: 0x0 = r2p0 162 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Revision 11.20.4 Interrupt Control and State Register The ICSR:  provides: ̶  set-pending and clear-pending bits for the PendSV and SysTick exceptions indicates: ̶ the exception number of the exception being processed ̶ whether there are preempted active exceptions ̶ the exception number of the highest priority pending exception ̶ whether any interrupts are pending. See the register summary in Table 11-30 on page 158, and the Type descriptions in Table 11-33 on page 187, for the ICSR attributes. The bit assignments are: 31 30 Reserved 29 Reserved 23 22 Reserved for Debug ISRPENDING 15 14 28 27 26 25 24 PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR Reserved 20 19 18 17 16 21 VECTPENDING 13 12 11 VECTPENDING 7 6 5 10 RETTOBASE 4 3 9 Reserved 2 8 VECTACTIVE 1 0 VECTACTIVE • PENDSVSET RW PendSV set-pending bit. Write: 0 = no effect 1 = changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending. • PENDSVCLR WO PendSV clear-pending bit. Write: 0 = no effect 1 = removes the pending state from the PendSV exception. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 163 • PENDSTSET RW SysTick exception set-pending bit. Write: 0 = no effect 1 = changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending 1 = SysTick exception is pending. • PENDSTCLR WO SysTick exception clear-pending bit. Write: 0 = no effect 1 = removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown. • Reserved for Debug use RO This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug. • ISRPENDING RO Interrupt pending flag, excluding Faults: 0 = interrupt not pending 1 = interrupt pending. • VECTPENDING RO Indicates the exception number of the highest priority pending enabled exception: 0 = no pending exceptions Nonzero = the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. • RETTOBASE RO Indicates whether there are preempted active exceptions: 0 = there are preempted active exceptions to execute 1 = there are no active exceptions, or the currently-executing exception is the only active exception. 164 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 • VECTACTIVE RO Contains the active exception number: 0 = Thread mode Nonzero = The exception number (1) of the currently active exception. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, ClearPending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” on page 48. When you write to the ICSR, the effect is Unpredictable if you: • write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit • write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit. Note: 1. This is the same value as IPSR bits [8:0] see “Interrupt Program Status Register” on page 48. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 165 11.20.5 Vector Table Offset Register The VTOR indicates the offset of the vector table base address from memory address 0x00000000. See the register summary in Table 11-30 on page 158 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 TBLOFF 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 6 5 TBLOFF 4 Reserved • TBLOFF Vector table base offset field. It contains bits[29:7] of the offset of the table base from the bottom of the memory map. Bit[29] determines whether the vector table is in the code or SRAM memory region: 0 = code 1 = SRAM. Bit[29] is sometimes called the TBLBASE bit. When setting TBLOFF, you must align the offset to the number of exception entries in the vector table. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64. Table alignment requirements mean that bits[6:0] of the table offset are always zero. 166 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.6 Application Interrupt and Reset Control Register The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in Table 11-30 on page 158 and Table 11-33 on page 187 for its attributes. To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processor ignores the write. The bit assignments are: 31 30 29 28 27 26 25 24 18 17 16 9 8 On Read: VECTKEYSTAT, On Write: VECTKEY 23 22 21 20 19 On Read: VECTKEYSTAT, On Write: VECTKEY 15 14 13 ENDIANESS 7 12 11 6 5 PRIGROUP 4 3 Reserved • 10 Reserved 2 1 0 SYSRESETREQ VECTCLRACTIVE VECTRESET VECTKEYSTAT Register Key: Reads as 0xFA05 • VECTKEY Register key: On writes, write 0x5FA to VECTKEY, otherwise the write is ignored. • ENDIANESS RO Data endianness bit: 0 = Little-endian ENDIANESS is set from the BIGEND configuration signal during reset. • PRIGROUP R/W Interrupt priority grouping field. This field determines the split of group priority from subpriority, see “Binary point” on page 168. • SYSRESETREQ WO System reset request: 0 = no effect 1 = asserts a proc_reset_signal. This is intended to force a large system reset of all major components except for debug. This bit reads as 0. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 167 • VECTCLRACTIVE WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. • VECTRESET WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. 11.20.6.1 Binary point The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in the Interrupt Priority Registers into separate group priority and subpriority fields. Table 11-31 shows how the PRIGROUP value controls this split. Table 11-31. Priority grouping Interrupt priority level value, PRI_N[7:0] Number of PRIGROUP Binary point (1) Group priority bits Subpriority bits Group priorities Subpriorities b011 bxxxx.0000 [7:4] None 16 1 b100 bxxx.y0000 [7:5] [4] 8 2 b101 bxx.yy0000 [7:6] [5:4] 4 4 b110 bx.yyy0000 [7] [6:4] 2 8 b111 b.yyyy0000 None [7:4] 1 16 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Determining preemption of an exception uses only the group priority field, see “Interrupt priority grouping” on page 66. 168 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.7 System Control Register The SCR controls features of entry to and exit from low power state. See the register summary in Table 11-30 on page 158 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 Reserved 5 4 3 2 1 0 SEVONPEND Reserved SLEEPDEEP SLEEONEXIT Reserved • SEVONPEND Send Event on Pending bit: 0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. • SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = sleep 1 = deep sleep. • SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = do not sleep when returning to Thread mode. 1 = enter sleep, or deep sleep, on return from an ISR. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 169 11.20.8 Configuration and Control Register The CCR controls entry to Thread mode and enables:  the handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults  trapping of divide by zero and unaligned accesses  access to the STIR by unprivileged software, see “Software Trigger Interrupt Register” on page 156. See the register summary in Table 11-30 on page 158 for the CCR attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 STKALIGN BFHFNMIGN Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 Reserved 4 3 DIV_0_TRP UNALIGN_T RP 2 1 0 Reserved USERSETM PEND NONBASET HRDENA • STKALIGN Indicates stack alignment on exception entry: 0 = 4-byte aligned 1 = 8-byte aligned. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. • BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the hard fault and FAULTMASK escalated handlers: 0 = data bus faults caused by load and store instructions cause a lock-up 1 = handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. • DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0 = do not trap divide by 0 1 = trap divide by 0. When this bit is set to 0,a divide by zero returns a quotient of 0. • UNALIGN_TRP Enables unaligned access traps: 0 = do not trap unaligned halfword and word accesses 1 = trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. 170 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. • USERSETMPEND Enables unprivileged software access to the STIR, see “Software Trigger Interrupt Register” on page 156: 0 = disable 1 = enable. • NONEBASETHRDENA Indicates how the processor enters Thread mode: 0 = processor can enter Thread mode only when no exception is active. 1 = processor can enter Thread mode from any level under the control of an EXC_RETURN value, see “Exception return” on page 67. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 171 11.20.9 System Handler Priority Registers The SHPR1-SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. SHPR1-SHPR3 are byte accessible. See the register summary in Table 11-30 on page 158 for their attributes. The system fault handlers and the priority field and register for each handler are: Table 11-32. System fault handler priority fields Handler Field Memory management fault PRI_4 Bus fault PRI_5 Usage fault PRI_6 SVCall PRI_11 PendSV PRI_14 SysTick PRI_15 Register description “System Handler Priority Register 1” on page 173 “System Handler Priority Register 2” on page 174 “System Handler Priority Register 3” on page 174 Each PRI_N field is 8 bits wide, but the processor implements only bits[7:4] of each field, and bits[3:0] read as zero and ignore writes. 172 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.9.1 System Handler Priority Register 1 The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_7: Reserved 23 22 21 20 PRI_6 15 14 13 12 PRI_5 7 6 5 4 PRI_4 • PRI_7 Reserved • PRI_6 Priority of system handler 6, usage fault • PRI_5 Priority of system handler 5, bus fault • PRI_4 Priority of system handler 4, memory management fault SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 173 11.20.9.2 System Handler Priority Register 2 The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI_11 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved • PRI_11 Priority of system handler 11, SVCall 11.20.9.3 System Handler Priority Register 3 The bit assignments are: 31 30 29 28 PRI_15 23 22 21 20 PRI_14 15 14 13 12 Reserved 7 6 5 4 Reserved • PRI_15 Priority of system handler 15, SysTick exception • PRI_14 Priority of system handler 14, PendSV 174 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.10System Handler Control and State Register The SHCSR enables the system handlers, and indicates:  the pending status of the bus fault, memory management fault, and SVC exceptions  the active status of the system handlers. See the register summary in Table 11-30 on page 158 for the SHCSR attributes. The bit assignments are: 31 30 29 28 27 26 25 24 Reserved 23 22 21 20 19 Reserved 18 17 16 USGFAULTENA BUSFAULTENA MEMFAULTENA 15 14 13 12 11 10 9 8 SVCALLPENDE D BUSFAULTPEND ED MEMFAULTPEN DED USGFAULTPEND ED SYSTICKACT PENDSVACT Reserved MONITORACT 7 6 5 4 3 2 1 0 USGFAULTACT Reserved BUSFAULTACT MEMFAULTACT SVCALLAVCT Reserved • USGFAULTENA Usage fault enable bit, set to 1 to enable (1) • BUSFAULTENA Bus fault enable bit, set to 1 to enable (3) • MEMFAULTENA Memory management fault enable bit, set to 1 to enable (3) • SVCALLPENDED SVC call pending bit, reads as 1 if exception is pending (2) • BUSFAULTPENDED Bus fault exception pending bit, reads as 1 if exception is pending (2) • MEMFAULTPENDED Memory management fault exception pending bit, reads as 1 if exception is pending (2) • USGFAULTPENDED Usage fault exception pending bit, reads as 1 if exception is pending (2) • SYSTICKACT SysTick exception active bit, reads as 1 if exception is active (3) • PENDSVACT 1. 2. 3. Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception. Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending status of the exceptions. Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status of the exceptions, but see the Caution in this section. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 175 PendSV exception active bit, reads as 1 if exception is active • MONITORACT Debug monitor active bit, reads as 1 if Debug monitor is active • SVCALLACT SVC call active bit, reads as 1 if SVC call is active • USGFAULTACT Usage fault exception active bit, reads as 1 if exception is active • BUSFAULTACT Bus fault exception active bit, reads as 1 if exception is active • MEMFAULTACT Memory management fault exception active bit, reads as 1 if exception is active If you disable a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault. You can write to this register to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. • Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. • After you have enabled the system handlers, if you have to change the value of a bit in this register you must use a read-modify-write procedure to ensure that you change only the required bit. 176 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.11Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary in Table 11-30 on page 158 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 Usage Fault Status Register: UFSR 23 22 21 20 19 Usage Fault Status Register: UFSR 15 14 13 12 11 Bus Fault Status Register: BFSR 7 6 5 4 3 Memory Management Fault Status Register: MMFSR The following subsections describe the subregisters that make up the CFSR:  “Memory Management Fault Status Register” on page 178  “Bus Fault Status Register” on page 179  “Usage Fault Status Register” on page 181. The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:  access the complete CFSR with a word access to 0xE000ED28  access the MMFSR with a byte access to 0xE000ED28  access the MMFSR and BFSR with a halfword access to 0xE000ED28  access the BFSR with a byte access to 0xE000ED29  access the UFSR with a halfword access to 0xE000ED2A. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 177 11.20.11.1 Memory Management Fault Status Register The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are: 7 6 MMARVALID 5 Reserved 4 3 2 1 0 MSTKERR MUNSTKERR Reserved DACCVIOL IACCVIOL • MMARVALID Memory Management Fault Address Register (MMAR) valid flag: 0 = value in MMAR is not a valid fault address 1 = MMAR holds a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose MMAR value has been overwritten. • MSTKERR Memory manager fault on stacking for exception entry: 0 = no stacking fault 1 = stacking for an exception entry has caused one or more access violations. When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor has not written a fault address to the MMAR. • MUNSTKERR Memory manager fault on unstacking for a return from exception: 0 = no unstacking fault 1 = unstack for an exception return has caused one or more access violations. This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The processor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a fault address to the MMAR. • DACCVIOL Data access violation flag: 0 = no data access violation fault 1 = the processor attempted a load or store at a location that does not permit the operation. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded the MMAR with the address of the attempted access. • IACCVIOL Instruction access violation flag: 0 = no instruction access violation fault 1 = the processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not written a fault address to the MMAR. 178 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.11.2 Bus Fault Status Register The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are: 7 6 BFRVALID 5 Reserved 4 3 2 1 0 STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR • BFARVALID Bus Fault Address Register (BFAR) valid flag: 0 = value in BFAR is not a valid fault address 1 = BFAR holds a valid fault address. The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems if returning to a stacked active bus fault handler whose BFAR value has been overwritten. • STKERR Bus fault on stacking for exception entry: 0 = no stacking fault 1 = stacking for an exception entry has caused one or more bus faults. When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the BFAR. • UNSTKERR Bus fault on unstacking for a return from exception: 0 = no unstacking fault 1 = unstack for an exception return has caused one or more bus faults. This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address to the BFAR. • IMPRECISERR Imprecise data bus error: 0 = no imprecise data bus error 1 = a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When the processor sets this bit to 1, it does not write a fault address to the BFAR. This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects both IMPRECISERR set to 1 and one of the precise fault status bits set to 1. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 179 • PRECISERR Precise data bus error: 0 = no precise data bus error 1 = a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets this bit is 1, it writes the faulting address to the BFAR. • IBUSERR Instruction bus error: 0 = no instruction bus error 1 = instruction bus error. The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting instruction. When the processor sets this bit is 1, it does not write a fault address to the BFAR. 180 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.11.3 Usage Fault Status Register The UFSR indicates the cause of a usage fault. The bit assignments are: 15 14 13 12 11 10 Reserved 7 6 5 4 Reserved 9 8 DIVBYZERO UNALIGNED 3 2 1 0 NOCP INVPC INVSTATE UNDEFINSTR • DIVBYZERO Divide by zero usage fault: 0 = no divide by zero fault, or divide by zero trapping not enabled 1 = the processor has executed an SDIV or UDIV instruction with a divisor of 0. When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see “Configuration and Control Register” on page 170. • UNALIGNED Unaligned access usage fault: 0 = no unaligned access fault, or unaligned access trapping not enabled 1 = the processor has made an unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see “Configuration and Control Register” on page 170. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP. • NOCP No coprocessor usage fault. The processor does not support coprocessor instructions: 0 = no usage fault caused by attempting to access a coprocessor 1 = the processor has attempted to access a coprocessor. • INVPC Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN: 0 = no invalid PC load usage fault 1 = the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. • INVSTATE Invalid state usage fault: 0 = no invalid state usage fault 1 = the processor has attempted to execute an instruction that makes illegal use of the EPSR. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 181 This bit is not set to 1 if an undefined instruction uses the EPSR. • UNDEFINSTR Undefined instruction usage fault: 0 = no undefined instruction usage fault 1 = the processor has attempted to execute an undefined instruction. When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset. 182 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.12Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in Table 11-30 on page 158 for its attributes. This register is read, write to clear. This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0. The bit assignments are: 31 30 DEBUGEVT FORCED 23 22 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 Reserved 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved 1 0 VECTTBL Reserved • DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. • FORCED Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled: 0 = no forced hard fault 1 = forced hard fault. When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault. • VECTTBL Indicates a bus fault on a vector table read during exception processing: 0 = no bus fault on vector table read 1 = bus fault on vector table read. This error is always handled by the hard fault handler. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the exception. The HFSR bits are sticky. This means as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 183 11.20.13Memory Management Fault Address Register The MMFAR contains the address of the location that generated a memory management fault. See the register summary in Table 11-30 on page 158 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS • ADDRESS When the MMARVALID bit of the MMFSR is set to 1, this field holds the address of the location that generated the memory management fault When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Flags in the MMFSR indicate the cause of the fault, and whether the value in the MMFAR is valid. See “Memory Management Fault Status Register” on page 178. 184 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.20.14Bus Fault Address Register The BFAR contains the address of the location that generated a bus fault. See the register summary in Table 1130 on page 158 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS • ADDRESS When the BFARVALID bit of the BFSR is set to 1, this field holds the address of the location that generated the bus fault When an unaligned access faults the address in the BFAR is the one requested by the instruction, even if it is not the address of the fault. Flags in the BFSR indicate the cause of the fault, and whether the value in the BFAR is valid. See “Bus Fault Status Register” on page 179. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 185 11.20.15System control block design hints and tips Ensure software uses aligned accesses of the correct size to access the system control block registers:  except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses  for the CFSR and SHPR1-SHPR3 it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. In a fault handler. to determine the true faulting address:  Read and save the MMFAR or BFAR value.  Read the MMARVALID bit in the MMFSR, or the BFARVALID bit in the BFSR. The MMFAR or BFAR address is valid only if this bit is 1. Software must follow this sequence because another higher priority exception might change the MMFAR or BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMFAR or BFAR value. 186 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.21 System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging the counter does not decrement. The system timer registers are: Table 11-33. System timer registers summary Address Name Type Required privilege Reset value Description 0xE000E010 CTRL RW Privileged 0x00000004 “SysTick Control and Status Register” on page 188 0xE000E014 LOAD RW Privileged 0x00000000 “SysTick Reload Value Register” on page 189 0xE000E018 VAL RW Privileged 0x00000000 “SysTick Current Value Register” on page 190 0xE000E01C 1. CALIB RO Privileged 0x0002904 (1) “SysTick Calibration Value Register” on page 191 SysTick calibration value. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 187 11.21.1 SysTick Control and Status Register The SysTick CTRL register enables the SysTick features. See the register summary in Table 11-33 on page 187 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 19 18 17 24 Reserved 23 22 21 20 Reserved 15 14 13 12 16 COUNTFLAG 11 10 9 8 Reserved 7 6 5 4 3 Reserved 2 1 0 CLKSOURCE TICKINT ENABLE • COUNTFLAG Returns 1 if timer counted to 0 since last time this was read. • CLKSOURCE Indicates the clock source: 0 = MCK/8 1 = MCK • TICKINT Enables SysTick exception request: 0 = counting down to zero does not assert the SysTick exception request 1 = counting down to zero to asserts the SysTick exception request. Software can use COUNTFLAG to determine if SysTick has ever counted to zero. • ENABLE Enables the counter: 0 = counter disabled 1 = counter enabled. When ENABLE is set to 1, the counter loads the RELOAD value from the LOAD register and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the RELOAD value again, and begins counting. 188 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.21.2 SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register summary in Table 11-33 on page 187 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 RELOAD 15 14 13 12 RELOAD 7 6 5 4 -RELOAD • RELOAD Value to load into the VAL register when the counter is enabled and when it reaches 0, see “Calculating the RELOAD value” . 11.21.2.1 Calculating the RELOAD value The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0. The RELOAD value is calculated according to its use:  To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.  To deliver a single SysTick interrupt after a delay of N processor clock cycles, use a RELOAD of value N. For example, if a SysTick interrupt is required after 400 clock pulses, set RELOAD to 400. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 189 11.21.3 SysTick Current Value Register The VAL register contains the current value of the SysTick counter. See the register summary in Table 11-33 on page 187 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT • CURRENT Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SysTick CTRL.COUNTFLAG bit to 0. 190 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.21.4 SysTick Calibration Value Register The CALIB register indicates the SysTick calibration properties. See the register summary in Table 11-33 on page 187 for its attributes. The bit assignments are: 31 30 NOREF SKEW 23 22 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 21 20 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS • NOREF Reads as zero. • SKEW Reads as zero • TENMS Read as 0x00001F40. The SysTick calibration value is fixed at 0x00001F40 (8000), which allows the generation of a time base of 1 ms with SysTick clock at 8 MHz (64/8 = 8 MHz) 11.21.5 SysTick design hints and tips The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 191 11.22 Memory protection unit This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports:  independent attribute settings for each region  overlapping regions  export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines:  eight separate memory regions, 0-7  a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M3 MPU memory map is unified. This means instruction accesses and data accesses have same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault. This causes a fault exception, and might cause termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types, see “Memory regions, types and attributes” on page 54. Table 11-34 shows the possible MPU region attributes. These include Share ability and cache behavior attributes that are not relevant to most microcontroller implementations. See “MPU configuration for a microcontroller” on page 204 for guidelines for programming such an implementation. Table 11-34. Memory attributes summary Memory type Shareability Other attributes Description Stronglyordered - - All accesses to Strongly-ordered memory occur in program order. All Strongly-ordered regions are assumed to be shared. Device Shared - Memory-mapped peripherals that several processors share. Non-shared - Memory-mapped peripherals that only a single processor uses. Normal Shared Normal memory that is shared between several processors. Non-shared Normal memory that only a single processor uses. Use the MPU registers to define the MPU regions and their attributes. The MPU registers are: 192 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Table 11-35. MPU registers summary Address Name Type Required privilege Reset value Description 0xE000ED90 TYPE RO Privileged 0x00000800 “MPU Type Register” on page 194 0xE000ED94 CTRL RW Privileged 0x00000000 “MPU Control Register” on page 195 0xE000ED98 RNR RW Privileged 0x00000000 “MPU Region Number Register” on page 197 0xE000ED9C RBAR RW Privileged 0x00000000 “MPU Region Base Address Register” on page 198 0xE000EDA0 RASR RW Privileged 0x00000000 “MPU Region Attribute and Size Register” on page 199 0xE000EDA4 RBAR_A1 RW Privileged 0x00000000 Alias of RBAR, see “MPU Region Base Address Register” on page 198 0xE000EDA8 RASR_A1 RW Privileged 0x00000000 Alias of RASR, see “MPU Region Attribute and Size Register” on page 199 0xE000EDAC RBAR_A2 RW Privileged 0x00000000 Alias of RBAR, see “MPU Region Base Address Register” on page 198 0xE000EDB0 RASR_A2 RW Privileged 0x00000000 Alias of RASR, see “MPU Region Attribute and Size Register” on page 199 0xE000EDB4 RBAR_A3 RW Privileged 0x00000000 Alias of RBAR, see “MPU Region Base Address Register” on page 198 0xE000EDB8 RASR_A3 RW Privileged 0x00000000 Alias of RASR, see “MPU Region Attribute and Size Register” on page 199 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 193 11.22.1 MPU Type Register The TYPE register indicates whether the MPU is present, and if so, how many regions it supports. See the register summary in Table 11-35 on page 193 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 Reserved 23 22 21 20 IREGION 15 14 13 12 DREGION 7 6 5 4 Reserved • IREGION Indicates the number of supported MPU instruction regions. Always contains 0x00. The MPU memory map is unified and is described by the DREGION field. • DREGION Indicates the number of supported MPU data regions: 0x08 = Eight MPU regions. • SEPARATE Indicates support for unified or separate instruction and date memory maps: 0 = unified. 194 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 0 SEPARATE 11.22.2 MPU Control Register The MPU CTRL register:  enables the MPU  enables the default memory map background region  enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. See the register summary in Table 11-35 on page 193 for the MPU CTRL attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 Reserved 2 1 0 PRIVDEFENA HFNMIENA ENABLE • PRIVDEFENA Enables privileged software access to the default memory map: 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. • HFNMIENA Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers. When the MPU is enabled: 0 = MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit 1 = the MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable. • ENABLE Enables the MPU: 0 = MPU disabled 1 = MPU enabled. When ENABLE and PRIVDEFENA are both set to 1: For privileged accesses, the default memory map is as described in “Memory model” on page 54. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 195 XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can operate. When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the MPU is not implemented, see Table 11-34 on page 192. The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFENA is set to 1. Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities. 196 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.22.3 MPU Region Number Register The RNR selects which memory region is referenced by the RBAR and RASR registers. See the register summary in Table 11-35 on page 193 for its attributes. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 REGION • REGION Indicates the MPU region referenced by the RBAR and RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7. Normally, you write the required region number to this register before accessing the RBAR or RASR. However you can change the region number by writing to the RBAR with the VALID bit set to 1, see “MPU Region Base Address Register” on page 198. This write updates the value of the REGION field. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 197 11.22.4 MPU Region Base Address Register The RBAR defines the base address of the MPU region selected by the RNR, and can update the value of the RNR. See the register summary in Table 11-35 on page 193 for its attributes. Write RBAR with the VALID bit set to 1 to change the current region number and update the RNR. The bit assignments are: 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 N 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR N-1 6 5 Reserved 4 VALID REGION • ADDR Region base address field. The value of N depends on the region size. For more information see “The ADDR field” . • VALID MPU Region Number valid bit: Write: 0 = RNR not changed, and the processor: updates the base address for the region specified in the RNR ignores the value of the REGION field 1 = the processor: updates the value of the RNR to the value of the REGION field updates the base address for the region specified in the REGION field. Always reads as zero. • REGION MPU region field: For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the RNR. 11.22.4.1 The ADDR field The ADDR field is bits[31:N] of the RBAR. The region size, as specified by the SIZE field in the RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4GB, in the RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000. 198 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.22.5 MPU Region Attribute and Size Register The RASR defines the region size and memory attributes of the MPU region specified by the RNR, and enables that region and any subregions. See the register summary in Table 11-35 on page 193 for its attributes. RASR is accessible using word or halfword accesses:  the most significant halfword holds the region attributes  the least significant halfword holds the region size and the region and subregion enable bits. The bit assignments are: 31 30 29 Reserved 23 22 27 XN Reserved 20 19 21 Reserved 15 28 13 12 25 24 AP 18 17 16 S C B 11 10 9 8 3 2 1 TEX 14 26 SRD 7 6 5 4 Reserved SIZE 0 ENABLE • XN Instruction access disable bit: 0 = instruction fetches enabled 1 = instruction fetches disabled. • AP Access permission field, see Table 11-39 on page 201. • TEX, C, B Memory access attributes, see Table 11-37 on page 200. • S Shareable bit, see Table 11-36 on page 200. • SRD Subregion disable bits. For each bit in this field: 0 = corresponding sub-region is enabled 1 = corresponding sub-region is disabled See “Subregions” on page 203 for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. • SIZE Specifies the size of the MPU protection region. The minimum permitted value is 3 (b00010), see See “SIZE field values” on page 200 for more information. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 199 • ENABLE Region enable bit. For information about access permission, see “MPU access permission attributes” . 11.22.5.1 SIZE field values The SIZE field defines the size of the MPU memory region specified by the RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 11-36 gives example SIZE values, with the corresponding region size and value of N in the RBAR. Table 11-36. Example SIZE field values SIZE value Region size Value of N (1) b00100 (4) 32B 5 Minimum permitted size b01001 (9) 1KB 10 - b10011 (19) 1MB 20 - b11101 (29) 1GB 30 - b11111 (31) 4GB b01100 Maximum possible size 1. Note In the RBAR, see “MPU Region Base Address Register” on page 198. 11.22.6 MPU access permission attributes This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and XN, of the RASR, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 11-37 shows the encodings for the TEX, C, B, and S access permission bits. Table 11-37. TEX TEX, C, B, and S encoding C B S Memory type Shareability Other attributes 0 0 x (1) Stronglyordered Shareable - 1 x (1) Device Shareable - Normal Not shareable 0 0 b000 1 Shareable 0 Not shareable Outer and inner write-through. No write allocate. 1 1 Normal 1 200 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Shareable Outer and inner write-back. No write allocate. Table 11-37. TEX TEX, C, B, and S encoding (Continued) C B 0 0 S Memory type Shareability Normal Not shareable 0 1 Shareable (1) 1 x 0 x (1) b001 1 Reserved encoding - Implementation defined attributes. - 0 1 Normal 1 Outer and inner write-back. Write and read allocate. Not shareable 0 x (1) Device 1 x (1) Reserved encoding - 1 x (1) x (1) Reserved encoding - A A b010 0 Normal 1 1. Not shareable Shareable 0 b1B B Other attributes Nonshared Device. Not shareable Shareable The MPU ignores the value of this bit. Table 11-38 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7. Table 11-38. Cache policy for memory attribute encoding Encoding, AA or BB Corresponding cache policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate Table 11-39 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 11-39. AP encoding AP[2:0] Privileged permissions Unprivileged permissions Description 000 No access No access All accesses generate a permission fault 001 RW No access Access from privileged software only 010 RW RO Writes by unprivileged software generate a permission fault 011 RW RW Full access 100 Unpredictable Unpredictable Reserved SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 201 Table 11-39. AP encoding (Continued) AP[2:0] Privileged permissions Unprivileged permissions Description 101 RO No access Reads by privileged software only 110 RO RO Read only, by privileged or unprivileged software 111 RO RO Read only, by privileged or unprivileged software 11.22.7 MPU mismatch When an access violates the MPU permissions, the processor generates a memory management fault, see “Exceptions and interrupts” on page 53. The MMFSR indicates the cause of the fault. See “Memory Management Fault Status Register” on page 178 for more information. 11.22.8 Updating an MPU region To update the attributes for an MPU region, update the RNR, RBAR and RASR registers. You can program each register separately, or use a multiple-word write to program all of these registers. You can use the RBAR and RASR aliases to program up to four regions simultaneously using an STM instruction. 11.22.8.1 Updating an MPU region using separate words Simple code to configure one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Region Base Address Region Size and Enable Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable STRH R2, [R0, #0x8] ; Region Size and Enable Software must use memory barrier instructions:  before MPU setup if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings  after MPU setup if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. 202 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the PPB, which is a Strongly-Ordered memory region. For example, if you want all of the memory access behavior to take effect immediately after the programming sequence, use a DSB instruction and an ISB instruction. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then you do not require an ISB. 11.22.8.2 Updating an MPU region using multi-word writes You can program directly using multi-word writes, depending on how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region Number, address, attribute, size and enable You can do this in two words for pre-packed information. This means that the RBAR contains the required region number and had the VALID bit set to 1, see “MPU Region Base Address Register” on page 198. Use this when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and ; region number combined with VALID (bit 4) set to 1 STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable 11.22.8.3 Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the RASR to disable a subregion, see “MPU Region Attribute and Size Register” on page 199. The least significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes, you must set the SRD field to 0x00, otherwise the MPU behavior is Unpredictable. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 203 11.22.8.4 Example of SRD use Two regions with the same base address overlap. Region one is 128KB, and region two is 512KB. To ensure the attributes from region one apply to the first128KB region, set the SRD field for region two to b00000011 to disable the first two subregions, as Figure 11-9 shows Figure 11-9. SRD use 5HJLRQZLWK VXEUHJLRQV 5HJLRQ %DVHDGGUHVVRIERWKUHJLRQV 2IIVHWIURP EDVHDGGUHVV .% .% .% .% .% .% .% 'LVDEOHGVXEUHJLRQ .% 'LVDEOHGVXEUHJLRQ  11.22.9 MPU design hints and tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers:  except for the RASR, it must use aligned word accesses  for the RASR it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. 11.22.9.1 MPU configuration for a microcontroller Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as follows: Table 11-40. Memory region attributes for a microcontroller Memory region TEX C B S Memory type and attributes Flash memory b000 1 0 0 Normal memory, Non-shareable, write-through Internal SRAM b000 1 0 1 Normal memory, Shareable, write-through External SRAM b000 1 1 1 Normal memory, Shareable, write-back, write-allocate Peripherals b000 0 1 1 Device memory, Shareable In most microcontroller implementations, the share ability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the share ability attribute might be important. In these cases refer to the recommendations of the memory device manufacturer. 204 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.23 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively. Banked register A register that has multiple physical copies, where the state of the processor determines which copy is used. The Stack Pointer, SP (R13) is a banked register. Base register In instruction descriptions, a register specified by a load or store instruction that is used to hold the base value for the instruction’s address calculation. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the address that is sent to memory. See also “Index register” Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested. Condition field A four-bit field in an instruction that specifies a condition under which the instruction can execute. Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing. Context The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions. Coprocessor A processor that supplements the main processor. Cortex-M3 does not support any coprocessors. Debugger A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging. Direct Memory Access (DMA) An operation that accesses main memory directly, without the processor performing any accesses to the data concerned. Doubleword SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 205 A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated. Doubleword-aligned A data item having a memory address that is divisible by eight. Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian (LE)” Exception An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception. Faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction. Exception service routine See “Interrupt handler” . Exception vector See “Interrupt vector” . Flat address mapping A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address. Halfword A 16-bit data item. Illegal instruction An instruction that is architecturally Undefined. Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual implementations. Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility. Index register In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction. See also “Base register” Instruction cycle count The number of cycles that an instruction occupies the Execute stage of the pipeline. Interrupt handler A program that control of the processor is passed to when an interrupt occurs. Interrupt vector 206 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler. Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also, “Condition field” , “Endianness” . Little-endian memory Memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address a byte at a halfword-aligned address is the least significant byte within the halfword at that address. Load/store architecture A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. Memory Protection Unit (MPU) Hardware that controls access permissions to blocks of memory. An MPU does not perform any address translation. Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed. Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP. Region A partition of memory space. Reserved A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as 0. Should Be One (SBO) Write as 1, or all 1s for bit fields, by software. Writing as 0 produces Unpredictable results. Should Be Zero (SBZ) Write as 0, or all 0s for bit fields, by software. Writing as 1 produces Unpredictable results. Should Be Zero or Preserved (SBZP) Write as 0, or all 0s for bit fields, by software, or preserved by writing the same value back that has been previously read from the same field on the same processor. Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts. Thumb instruction SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 207 One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfwordaligned. Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Undefined Indicates an instruction that generates an Undefined instruction exception. Unpredictable (UNP) You cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system. Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor. Word A 32-bit data item. Write Writes are defined as operations that have the semantics of a store. Writes include the Thumb instructions STM, STR, STRH, STRB, and PUSH. 208 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 12. Debug and Test Features 12.1 Description The SAM3 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 12.2 Embedded Characteristics  Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset.  Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access  Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches  Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling  Instrumentation Trace Macrocell (ITM) for support of printf style debugging  IEEE1149.1 JTAG Boundary-can on All Digital Pins Figure 12-1. Debug and Test Block Diagram TMS TCK/SWCLK TDI Boundary TAP JTAGSEL SWJ-DP TDO/TRACESWO Reset and Test POR TST SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 209 12.3 Application Examples 12.3.1 Debug Environment Figure 12-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 12-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM3 SAM3-based Application Board 12.3.2 Test Environment Figure 12-3 shows a test environment example (JTAG Boundary scan). Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. 210 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM3 Chip 2 Chip 1 SAM3-based Application Board In Test 12.4 Debug and Test Pin Description Table 12-1. Debug and Test Signal List Signal Name Function Type Active Level Input/Output Low Reset/Test NRST Microcontroller Reset TST Test Select Input SWD/JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input TDI Test Data In Input TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input JTAGSEL JTAG Selection Input Note: 1. Output (1) High TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding to this PIO line must be enabled to avoid current consumption due to floating input. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 211 12.5 Functional Description 12.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during powerup, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kΩ,so that it can be left unconnected for normal operation. Note that when setting the TST pin to low or high level at power up, it must remain in the same state during the duration of the whole operation. 12.5.2 Debug Architecture Figure 12-4 shows the Debug Architecture used in the SAM3. The Cortex-M3 embeds four functional units for debug:  SWJ-DP (Serial Wire/JTAG Debug Port)  FPB (Flash Patch Breakpoint)  DWT (Data Watchpoint and Trace)  ITM (Instrumentation Trace Macrocell)  TPIU (Trace Port Interface Unit) The debug architecture information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes and debugging tool vendors for Cortex M3-based microcontrollers. For further details on SWJ-DP see the CortexM3 technical reference manual. Figure 12-4. Debug Architecture DWT 4 watchpoints FPB SWJ-DP PC sampler 6 breakpoints data address sampler SWD/JTAG ITM data sampler software trace 32 channels interrupt trace SWO trace TPIU time stamping CPU statistics 12.5.3 Serial Wire/JTAG Debug Port (SWJ-DP) The Cortex-M3 embeds a SWJ-DP Debug port which is the standard CoreSight™ debug port. It combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP), 5 pins. By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and enables SW-DP. 212 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. Table 12-2. SWJ-DP Pin List Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI - TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed. 12.5.3.1 SW-DP and JTAG-DP Selection Mechanism Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by default after reset.  Switch from JTAG-DP to SW-DP. The sequence is: ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 ̶ Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first) ̶  Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 Switch from SWD to JTAG. The sequence is: ̶ ̶ ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first) Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 12.5.4 FPB (Flash Patch Breakpoint) The FPB:  Implements hardware breakpoints  Patches code and data from code space to system space. The FPB unit contains:  Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.  Six instruction comparators for matching against instruction fetches from Code space and remapping to a corresponding area in System space.  Alternatively, comparators can also be configured to generate a Breakpoint instruction to the processor core on a match. 12.5.5 DWT (Data Watchpoint and Trace) The DWT contains four comparators which can be configured to generate the following:  PC sampling packets at set intervals  PC or Data watchpoint packets  Watchpoint event to halt core The DWT contains counters for the items that follow:  Clock cycle (CYCCNT)  Folded instructions SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 213  Load Store Unit (LSU) operations  Sleep Cycles  CPI (all instruction cycles except for the first cycle)  Interrupt overhead 12.5.6 ITM (Instrumentation Trace Macrocell) The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels:  Software trace: Software can write directly to ITM stimulus registers. This can be done thanks to the “printf” function. For more information, refer to Section 12.5.6.1 “How to Configure the ITM”.  Hardware trace: The ITM emits packets generated by the DWT.  Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. 12.5.6.1 How to Configure the ITM The following example describes how to output trace data in asynchronous trace mode.  Configure the TPIU for asynchronous trace mode (refer to Section 12.5.6.3 “5.4.3. How to Configure the TPIU”)  Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register (Address: 0xE0000FB0)  Write 0x00010015 into the Trace Control Register:  ̶ Enable ITM ̶ Enable Synchronization packets ̶ Enable SWO behavior ̶ Fix the ATB ID to 1 Write 0x1 into the Trace Enable Register: ̶  Enable the Stimulus port 0 Write 0x1 into the Trace Privilege Register: ̶  Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit) The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM). The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core. 12.5.6.2 Asynchronous Mode The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous trace mode is only available when the Serial Wire Debug mode is selected since TDO signal is used in JTAG debug mode. Two encoding formats are available for the single pin output:  Manchester encoded stream. This is the reset value.  NRZ_based UART byte structure 12.5.6.3 5.4.3. How to Configure the TPIU This example only concerns the asynchronous trace mode. 214 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15  Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace and debug blocks.  Write 0x2 into the Selected Pin Protocol Register ̶ Select the Serial Wire Output – NRZ  Write 0x100 into the Formatter and Flush Control Register  Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 12.5.7 IEEE® 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low while JTAGSEL is high during power-up and must be kept in this state during the whole boundary scan operation. VDDCORE must be externally supplied between 1.8V and 1.95V. The SAMPLE, EXTEST and BYPASS functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided on Atmel’s web site to set up the test. 12.5.7.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins and associated control signals. Each SAM3 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. For more information, please refer to BDSL files available for the SAM3 Series. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 215 12.5.8 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name SAM3S Chip ID 0x05B2D • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. Chip Name SAM3S 216 JTAG ID Code 0x05B2D03F SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 0 1 13. Reset Controller (RSTC) 13.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 13.2 Block Diagram Figure 13-1. Reset Controller Block Diagram Reset Controller core_backup_reset rstc_irq vddcore_nreset Reset State Manager user_reset NRST nrst_out NRST Manager proc_nreset periph_nreset exter_nreset WDRPROC wd_fault SLCK 13.3 Functional Description 13.3.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:  proc_nreset: Processor reset line. It also resets the Watchdog Timer.  periph_nreset: Affects the whole set of embedded peripherals.  nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDIO, so that its configuration is saved as long as VDDIO is on. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 217 13.3.2 NRST Manager After power-up, NRST is an output during the ERSTL time period defined in the RSTC_MR. When ERSTL has elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal. The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager. Figure 13-2. NRST Manager RSTC_MR URSTIEN RSTC_SR URSTS NRSTL rstc_irq RSTC_MR URSTEN Other interrupt sources user_reset NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 13.3.2.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 13.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 13.3.3 Brownout Manager The Brownout manager is embedded within the Supply Controller, please refer to the product Supply Controller section for a detailed description. 218 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 13.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.3.4.1 General Reset A general reset occurs when a Power-on-reset is detected, a Brownout or a Voltage regulation loss is detected by the Supply controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs. All the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL defaults at value 0x0. Figure 13-3 shows how the General Reset affects the reset signals. Figure 13-3. General Reset State SLCK Any Freq. MCK backup_nreset Processor Startup = 2 cycles proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 219 13.3.4.2 Backup Reset A Backup reset occurs when the chip returns from Backup mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup reset occurs. The field RSTTYP in RSTC_SR is updated to report a Backup Reset. 13.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 13-4. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 13.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: 220  PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.  PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously).  EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 13-5. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. Processor Startup 1 cycle = 2 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 13.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:  If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.  If WDRPROC = 1, only the processor reset is asserted. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 221 The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 13-6. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP Any 0x2 = Watchdog Reset XXX periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 13.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order:  General Reset  Backup Reset  Watchdog Reset  Software Reset  User Reset Particular cases are listed below:  When in User Reset: ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. ̶   222 A software reset is impossible, since the processor reset is being activated. When in Software Reset: ̶ A watchdog event has priority over the current state. ̶ The NRST has no effect. When in Watchdog Reset: ̶ The processor reset is active and so a Software Reset cannot be programmed. ̶ A User Reset cannot be entered. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 13.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields:  RSTTYP field: This field gives the type of the last reset, as explained in previous sections.  SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.  NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.  URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-7). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 13-7. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 223 13.4 Reset Controller (RSTC) User Interface Table 13-1. Register Mapping Offset Register Name Access Reset 0x00 Control Register RSTC_CR Write-only - 0x04 Status Register RSTC_SR Read-only 0x0000_0000 0x08 Mode Register RSTC_MR Read-write 0x0000 0001 224 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 13.4.1 Reset Controller Control Register Name: RSTC_CR Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 225 13.4.2 Reset Controller Status Register Name: RSTC_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP Reset Type Comments 0 0 0 General Reset First power-up Reset 0 0 1 Backup Reset Return from Backup mode 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor reset required by the software 1 0 0 User Reset NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 226 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 13.4.3 Reset Controller Mode Register Name: RSTC_MR Access: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 227 14. Real-time Timer (RTT) 14.1 Description The Real-time Timer is built around a 32-bit counter used to count roll-over events of the 16-bit prescaler which size enables to count elapsed seconds from a 32 kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 14.2 Embedded Characteristics  Real-time Timer, allowing backup of time with different accuracies ̶ 32-bit free-running back-up counter ̶ Integrates a 16-bit programmable prescaler running on slow clock Alarm register capable to generate a wake-up of the system through the Shut Down Controller 14.3 Block Diagram Figure 14-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK RTTINCIEN reload 16-bit Divider set 0 RTT_MR RTTRST RTT_SR 1 RTTINC reset 0 rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set = RTT_AR 228 ALMV SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 rtt_alarm 14.4 Functional Description The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 229 Figure 14-2. RTT Counting APB cycle APB cycle SCLK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 230 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 ALMV+2 ALMV+3 14.5 Real-time Timer (RTT) User Interface Table 14-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read-write 0x0000_8000 0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 231 14.5.1 Real-time Timer Mode Register Name: RTT_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SCLK period. RTPRES ≠ 0: The prescaler period is equal to RTPRES * SCLK period. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 0 = No effect. 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 232 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 14.5.2 Real-time Timer Alarm Register Name: RTT_AR Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 233 14.5.3 Real-time Timer Value Register Name: RTT_VR Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 234 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 14.5.4 Real-time Timer Status Register Name: RTT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 235 15. Real-time Clock (RTC) 15.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. 15.2 236 Embedded Characteristics  Low Power Consumption  Full Asynchronous Design  Two Hundred Year Gregorian Calendar  Programmable Periodic Interrupt  Time, Date and Alarm 32-bit Parallel Load SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.3 Block Diagram Figure 15-1. 15.4 RTC Block Diagram Slow Clock: SLCK 32768 Divider Bus Interface Bus Interface Time Date Entry Control Interrupt Control RTC Interrupt Product Dependencies 15.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 15.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 237 15.5 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099. 15.5.1 Reference Clock The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 15.5.2 Timing The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at oneminute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 15.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition:  If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second.  If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. 15.5.4 Error Checking Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check if it is in range 19 - 20) 2. 238 Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8. Second (check BCD and range 00 - 59) Note: If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be programmed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. 15.5.5 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate Time and Calendar register. Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 239 Figure 15-2. Update Sequence Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD =1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End 240 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.6 Real Time Clock (RTC) User Interface Table 15-1. Offset Register Mapping Register Name Access Reset 0x00 Control Register RTC_CR Read-write 0x0 0x04 Mode Register RTC_MR Read-write 0x0 0x08 Time Register RTC_TIMR Read-write 0x0 0x0C Calendar Register RTC_CALR Read-write 0x01810720 0x10 Time Alarm Register RTC_TIMALR Read-write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read-write 0x01010000 0x18 Status Register RTC_SR Read-only 0x0 0x1C Status Clear Command Register RTC_SCCR Write-only – 0x20 Interrupt Enable Register RTC_IER Write-only – 0x24 Interrupt Disable Register RTC_IDR Write-only – 0x28 Interrupt Mask Register RTC_IMR Read-only 0x0 0x2C Valid Entry Register RTC_VER Read-only 0x0 0x30–0xF8 Reserved Register – – – 0xFC Reserved Register – – – Note: if an offset is not listed in the table it must be considered as reserved. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 241 15.6.1 RTC Control Register Name: RTC_CR Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – 15 14 13 12 11 10 – – – – – – CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register. • UPDCAL: Update Request Calendar Register 0 = No effect. 1 = Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set. • TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL. Value Name Description 0 MINUTE Minute change 1 HOUR Hour change 2 MIDNIGHT Every day at midnight 3 NOON Every day at noon • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) 3 – 242 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.6.2 RTC Mode Register Name: RTC_MR Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. All non-significant bits read zero. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 243 15.6.3 RTC Time Register Name: RTC_TIMR Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0 = AM. 1 = PM. All non-significant bits read zero. 244 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.6.4 RTC Calendar Register Name: RTC_CALR Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • DAY: Current Day in Current Week The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Day in Current Month The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 245 15.6.5 RTC Time Alarm Register Name: RTC_TIMALR Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 HOUREN AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled. • MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. • MINEN: Minute Alarm Enable 0 = The minute-matching alarm is disabled. 1 = The minute-matching alarm is enabled. • HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled. 1 = The hour-matching alarm is enabled. 246 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 23 22 21 18 17 16 MTHEN – – 15 14 13 12 11 10 9 8 – – – – – – – – DATE 20 19 MONTH 7 6 5 4 3 2 1 0 – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled. 1 = The date-matching alarm is enabled. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 247 15.6.7 RTC Status Register Name: RTC_SR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 = Time and calendar registers can be updated. • ALARM: Alarm Flag 0 = No alarm matching condition occurred. 1 = An alarm matching condition has occurred. • SEC: Second Event 0 = No second event has occurred since the last clear. 1 = At least one second event has occurred since the last clear. • TIMEV: Time Event 0 = No time event has occurred since the last clear. 1 = At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). • CALEV: Calendar Event 0 = No calendar event has occurred since the last clear. 1 = At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. 248 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.6.8 RTC Status Clear Command Register Name: RTC_SCCR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • SECCLR: Second Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 249 15.6.9 RTC Interrupt Enable Register Name: RTC_IER Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect. 1 = The alarm interrupt is enabled. • SECEN: Second Event Interrupt Enable 0 = No effect. 1 = The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable 0 = No effect. 1 = The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable 0 = No effect. • 1 = The selected calendar event interrupt is enabled. 250 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.6.10 RTC Interrupt Disable Register Name: RTC_IDR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect. 1 = The alarm interrupt is disabled. • SECDIS: Second Event Interrupt Disable 0 = No effect. 1 = The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable 0 = No effect. 1 = The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable 0 = No effect. 1 = The selected calendar event interrupt is disabled. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 251 15.6.11 RTC Interrupt Mask Register Name: RTC_IMR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled. • ALR: Alarm Interrupt Mask 0 = The alarm interrupt is disabled. 1 = The alarm interrupt is enabled. • SEC: Second Event Interrupt Mask 0 = The second periodic interrupt is disabled. 1 = The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled. 1 = The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled. 1 = The selected calendar event interrupt is enabled. 252 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 15.6.12 RTC Valid Entry Register Name: RTC_VER Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed. • NVCAL: Non-valid Calendar 0 = No invalid data has been detected in RTC_CALR (Calendar Register). 1 = RTC_CALR has contained invalid data since it was last programmed. • NVTIMALR: Non-valid Time Alarm 0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 = RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non-valid Calendar Alarm 0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 = RTC_CALALR has contained invalid data since it was last programmed. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 253 16. Watchdog Timer (WDT) 16.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 16.3 Embedded Characteristics  16-bit key-protected only-once-Programmable Counter  Windowed, prevents the processor to be in a dead-lock on the watchdog access. Block Diagram Figure 16-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR WDD reload Current Value 1/128 SLCK 32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake. 20.2.4 Programmer Handshaking An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high. 20.2.4.1 Write Handshaking For details on the write handshaking sequence, refer to Figure 20-3, Figure 20-4 and Table 20-4. Figure 20-3. SAM3SxB/C (64/100 pins) Parallel Programming Timing, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[7:0] 1 MODE[3:0] Figure 20-4. SAM3SxA (48 pins) Parallel Programming Timing, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[15:0] 1 MODE[3:0] SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 299 Table 20-4. Write Handshake Step Programmer Action Device Action Data I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latches MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Releases MODE and DATA signals Executes command and polls NCMD high Input 5 Sets NCMD signal Executes command and polls NCMD high Input 6 Waits for RDY high Sets RDY Input 20.2.4.2 Read Handshaking For details on the read handshaking sequence, refer to Figure 20-5, Figure 20-6 and Table 20-5. Figure 20-5. SAM3SxB/C (64/100 pins) Parallel Programming Timing, Read Sequence NCMD 12 2 3 RDY 13 NOE 9 5 NVALID 11 7 4 6 Adress IN DATA[7:0] Z 10 8 Data OUT X IN 1 ADDR MODE[3:0] Figure 20-6. SAM3SxA (48 pins) Parallel Programming Timing, Read Sequence NCMD 12 2 3 RDY 13 NOE 9 5 NVALID Adress IN DATA[15:0] 1 MODE[3:0] 300 11 7 4 ADDR SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 6 Z 8 Data OUT 10 X IN Table 20-5. Read Handshake Step Programmer Action Device Action DATA I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal 6 Waits for NVALID low 7 Tristate Sets DATA bus in output mode and outputs the flash contents. Output Clears NVALID signal Output Waits for NOE high Output 8 Reads value on DATA Bus 9 Sets NOE signal 10 Waits for NVALID high Sets DATA bus in input mode X 11 Sets DATA in output mode Sets NVALID signal Input 12 Sets NCMD signal Waits for NCMD high Input 13 Waits for RDY high Sets RDY signal Input Output SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 301 20.2.5 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page 298. Each command is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash. In the following tables, Table 20-6 through Table 20-17  DATA[15:0] pertains to ASAM3SxB/C (64/100 pins)  DATA[7:0] pertains to SAM3SxA (48 pins) 20.2.5.1 Flash Read Command This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 20-6. Read Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE READ 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Read handshaking DATA *Memory Address++ 5 Read handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Read handshaking DATA *Memory Address++ n+3 Read handshaking DATA *Memory Address++ ... ... ... ... Table 20-7. 302 Read Command Step Handshake Sequence MODE[3:0] DATA[7:0] 1 Write handshaking CMDE READ 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking ADDR2 Memory Address 5 Write handshaking ADDR3 Memory Address 6 Read handshaking DATA *Memory Address++ 7 Read handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Table 20-7. Read Command (Continued) Step Handshake Sequence MODE[3:0] DATA[7:0] n+2 Write handshaking ADDR2 Memory Address n+3 Write handshaking ADDR3 Memory Address n+4 Read handshaking DATA *Memory Address++ n+5 Read handshaking DATA *Memory Address++ ... ... ... ... 20.2.5.2 Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:  before access to any page other than the current one  when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 20-8. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE WP or WPL or EWP or EWPL 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking DATA *Memory Address++ 5 Write handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++ ... ... ... ... Table 20-9. Write Command Step Handshake Sequence MODE[3:0] DATA[7:0] 1 Write handshaking CMDE WP or WPL or EWP or EWPL 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking ADDR2 Memory Address 5 Write handshaking ADDR3 Memory Address 6 Write handshaking DATA *Memory Address++ 7 Write handshaking DATA *Memory Address++ ... ... ... ... SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 303 Table 20-9. Write Command (Continued) Step Handshake Sequence MODE[3:0] DATA[7:0] n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking ADDR2 Memory Address n+3 Write handshaking ADDR3 Memory Address n+4 Write handshaking DATA *Memory Address++ n+5 Write handshaking DATA *Memory Address++ ... ... ... ... The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 20.2.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 20-10. Full Erase Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE EA 2 Write handshaking DATA 0 20.2.5.4 Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. In the same way, the Clear Lock command (CLB) is used to clear lock bits. Table 20-11. 304 Set and Clear Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE SLB or CLB 2 Write handshaking DATA Bit Mask SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set.. Table 20-12. Get Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE GLB 2 Read handshaking DATA Lock Bit Mask Status 0 = Lock bit is cleared 1 = Lock bit is set 20.2.5.5 Flash General-purpose NVM Commands General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first GP NVM bit is activated. In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The generalpurpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. Table 20-13. Set/Clear GP NVM Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE SGPB or CGPB 2 Write handshaking DATA GP NVM bit pattern value General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is active when bit n of the bit mask is set.. Table 20-14. Get GP NVM Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE GGPB 2 Read handshaking DATA GP NVM Bit Mask Status 0 = GP NVM bit is cleared 1 = GP NVM bit is set 20.2.5.6 Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Table 20-15. Set Security Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE SSE 2 Write handshaking DATA 0 Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash. In order to erase the Flash, the user must perform the following:  Power-off the chip  Power-on the chip with TST = 0 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 305  Assert Erase during a period of more than 220 ms  Power-off the chip Then it is possible to return to FFPI mode and check that Flash is erased. 20.2.5.7 Memory Write Command This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 20-16. Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE WRAM 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking DATA *Memory Address++ 5 Write handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++ ... ... ... ... Table 20-17. 306 Write Command Write Command Step Handshake Sequence MODE[3:0] DATA[7:0] 1 Write handshaking CMDE WRAM 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking ADDR2 Memory Address 5 Write handshaking ADDR3 Memory Address 6 Write handshaking DATA *Memory Address++ 7 Write handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking ADDR2 Memory Address n+3 Write handshaking ADDR3 Memory Address n+4 Write handshaking DATA *Memory Address++ n+5 Write handshaking DATA *Memory Address++ ... ... ... ... SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 20.2.5.8 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-18. Get Version Command Step Handshake Sequence MODE[3:0] DATA[15:0] or DATA[7:0] 1 Write handshaking CMDE GVE 2 Write handshaking DATA Version SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 307 21. Cyclic Redundancy Check Calculation Unit (CRCCU) 21.1 Description The Cyclic Redundancy Check Calculation Unit (CRCCU) has its own DMA which functions as a Master with the Bus Matrix. 21.2 21.3 Embedded Characteristics  32-bit cyclic redundancy check automatic calculation  CRC calculation between two addresses of the memory CRCCU Block Diagram Figure 21-1. Block Diagram Host Interface Atmel APB Bus Context FSM CRC Register Addr Register Data Register HRDATA AHB Interface HTRANS HSIZE AHB-Layer External Bus Interface 308 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Flash AHB SRAM 21.4 Product Dependencies 21.4.1 Power Management The CRCCU is clocked through the Power Management Controller (PMC), the programmer must first configure the CRCCU in the PMC to enable the CRCCU clock. 21.4.2 Interrupt Source The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU interrupt requires programming the Interrupt Controller before configuring the CRCCU. 21.5 CRCCU Functional Description 21.5.1 CRC Calculation Unit description The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured and activated, this CRC engine performs a checksum computation on a Memory Area. CRC computation is performed from the LSB to MSB bit. Three different polynomials are available CCIT802.3, CASTAGNOLI and CCIT16, see the bitfield description, “PTYPE: Primitive Polynomial” on page 324, for details. 21.5.2 CRC Calculation Unit Operation The CRCCU has a DMA controller that supports programmable CRC memory checks. When enabled, the DMA channel reads a programmable amount of data and computes CRC on the fly. The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL which need to be mapped in the internal SRAM. The addresses of these two registers are pointed at by the CRCCU_DSCR register. Figure 21-2. CRCCU Descriptor Memory Mapping SRAM Memory CRCCU_DSCR+0x0 CRCCU_DSCR+0x4 CRCCU_DSCR+0x8 CRCCU_DSCR+0xC CRCCU_DSCR+0x10 TR_ADDR TR_CTRL Reserved Reserved TR_CRC TR_ADDR defines the start address of memory area targeted for CRC calculation. TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the transfer-completed interrupt enable. To start the CRCCU, the user needs to set the CRC enable bit (ENABLE) in the CRCCU Mode Register (CRCCU_MR), then configure it and finally set the DMA enable bit (DMAEN) in the CRCCU DMA Enable Register (CRCCU_DMA_EN). SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 309 When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in TR_CTRL) located at TR_ADDR start address and computes the checksum. The CRCCU_SR register contains the temporary CRC value. The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decremented if its value is different from zero. Once the value of the BTSIZE field is equal to zero, the CRCCU is disabled by hardware. In this case, the relevant CRCCU DMA Status Register bit, DMASR, is automatically cleared. If the COMPARE field of the CRCCU_MR register is set to true, the TR_CRC (Transfer Reference Register) is compared with the last CRC computed. If a mismatch occurs, an error flag is set and an interrupt is raised (if unmasked). The CRCCU accesses the memory by single access (TRWIDTH size) in order not to limit the bandwidth usage of the system, but the DIVIDER field of the CRCCU Mode Register can be used to lower it by dividing the frequency of the single accesses. In order to compute the CRC for a memory size larger than 256 Kbytes or for non-contiguous memory area, it is possible to re-enable the CRCCU on the new memory area and the CRC will be updated accordingly. Use the RESET field of the CRCCU_CR register to reset the CRCCU Status Register to its default value (0xFFFF_FFFF). 21.6 Transfer Control Registers Memory Mapping Table 21-1. Transfer Control Register Memory Mapping Offset Register Name Access CRCCU_DSCR + 0x0 CRCCU Transfer Address Register TR_ADDR Read-write CRCCU_DSCR + 0x4 CRCCU Transfer Control Register TR_CTRL Read-write CRCCU_DSCR + 0xC - 0x10 Reserved CRCCU_DSCR + 0x10 CRCCU Transfer Reference Register TR_CRC Read-write Note: These Registers are memory mapped 310 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 21.6.1 Transfer Address Register Name: TR_ADDR Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Transfer Address SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 311 21.6.2 Transfer Control Register Name: TR_CTRL Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 IEN 19 – 11 26 – 18 – 10 25 24 17 – 9 16 – 8 3 2 1 0 TRWIDTH BTSIZE BTSIZE • BTSIZE: Buffer Transfer Size • TRWIDTH: Transfer Width Register TRWIDTH Single Transfer Size 00 BYTE 01 HALFWORD 10 WORD • IEN: Context Done Interrupt Enable When set to zero, the transfer done status bit is set at the end of the transfer. 312 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 21.6.3 Transfer Reference Register Name: TR_CRC Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 REFCRC 23 22 21 20 REFCRC 15 14 13 12 REFCRC 7 6 5 4 REFCRC • REFCRC: Reference CRC When Compare mode is enabled, the checksum is compared with that register. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 313 21.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface Table 21-2. Register Mapping Offset Register Name Access Reset CRCCU_DSCR Read-write 0x00000000 0x00000000 CRCCU Descriptor Base Register 0x00000004 Reserved 0x00000008 CRCCU DMA Enable Register CRCCU_DMA_EN Write-only 0x00000000 0x0000000C CRCCU DMA Disable Register CRCCU_DMA_DIS Write-only 0x00000000 0x00000010 CRCCU DMA Status Register CRCCU_DMA_SR Read-only 0x00000000 0x00000014 CRCCU DMA Interrupt Enable Register CRCCU_DMA_IER Write-only 0x00000000 0x00000018 CRCCU DMA Interrupt Disable Register CRCCU_DMA_IDR Write-only 0x00000000 0x0000001C CRCCU DMA Interrupt Mask Register CRCCU_DMA_IMR Read-only 0x00000000 0x00000020 CRCCU DMA Interrupt Status Register CRCCU_DMA_ISR Read-only 0x00000000 0x0024-0x0030 Reserved 0x00000034 CRCCU Control Register CRCCU_CR Write-only 0x00000000 0x00000038 CRCCU Mode Register CRCCU_MR Read-write 0x00000000 0x0000003C CRCCU Status Register CRCCU_SR Read-only 0xFFFFFFFF 0x00000040 CRCCU Interrupt Enable Register CRCCU_IER Write-only 0x00000000 0x00000044 CRCCU Interrupt Disable Register CRCCU_IDR Write-only 0x00000000 0x00000048 CRCCU Interrupt Mask Register CRCCU_IMR Read-only 0x00000000 0x0000004C CRCCU Interrupt Status Register CRCCU_ISR Read-only 0x00000000 314 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 21.7.1 CRCCU Descriptor Base Address Register Name: CRCCU_DSCR Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 3 – 2 – 1 – 8 – 0 – DSCR 23 22 21 20 DSCR 15 14 13 7 – 6 – 5 – 12 DSCR 4 – • DSCR: Descriptor Base Address DSCR needs to be aligned with 512-byte boundaries. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 315 21.7.2 CRCCU DMA Enable Register Name: CRCCU_DMA_EN Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • DMAEN: DMA Enable Register Write one to enable the CRCCU DMA channel. 316 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAEN 21.7.3 CRCCU DMA Disable Register Name: CRCCU_DMA_DIS Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMADIS • DMADIS: DMA Disable Register Write one to disable the DMA channel SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 317 21.7.4 CRCCU DMA Status Register Name: CRCCU_DMA_SR Access: Read-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – • DMASR: DMA Status Register When set to one, this bit indicates that DMA Channel is enabled. 318 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMASR 21.7.5 CRCCU DMA Interrupt Enable Register Name: CRCCU_DMA_IER Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIER • DMAIER: Interrupt Enable register Set bit to one to enable the interrupt. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 319 21.7.6 CRCCU DMA Interrupt Disable Register Name: CRCCU_DMA_IDR Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • DMAIDR: Interrupt Disable register Set to one to disable the interrupt. 320 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIDR 21.7.7 CRCCU DMA Interrupt Mask Register Name: CRCCU_DMA_IMR Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIMR • DMAIMR: Interrupt Mask Register 0: Buffer Transfer Completed interrupt is disabled. 1: Buffer Transfer Completed interrupt is enabled. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 321 21.7.8 CRCCU DMA Interrupt Status Register Name: CRCCU_DMA_ISR Access: Read-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – • DMAISR: Interrupt Status register When DMAISR is set, DMA buffer transfer has terminated. This flag is reset after read. 322 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAISR 21.7.9 CRCCU Control Register Name: CRCCU_CR Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RESET • RESET: CRC Computation Reset When set to one, this bit resets the CRCCU_SR register to 0xFFFF FFFF. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 323 21.7.10 CRCCU Mode Register Name: CRCCU_MR Access: Read Write Reset: 31 – 23 – 15 – 7 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 DIVIDER 26 – 18 – 10 – 2 PTYPE 25 – 17 – 9 – 1 COMPARE 24 – 16 – 8 – 0 ENABLE • ENABLE: CRC Enable • COMPARE: CRC Compare If set to one, this bit indicates that the CRCCU DMA will compare the CRC computed on the data stream with the value stored in the TRC_RC reference register. If a mismatch occurs, the ERRISR bit in the CRCCU_ISR register is set. • PTYPE: Primitive Polynomial Value Name Description 0 CCIT8023 Polynom 0x04C11DB7 1 CASTAGNOLI Polynom 0x1EDC6F41 2 CCIT16 Polynom 0x1021 • DIVIDER: Request Divider CRCCU DMA performs successive transfers. It is possible to reduce the bandwidth drained by the CRCCU DMA by programming the DIVIDER field. The transfer request frequency is divided by 2^(DIVIDER+1). 324 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 21.7.11 CRCCU Status Register Name: CRCCU_SR Access: Read-only Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRC 23 22 21 20 CRC 15 14 13 12 CRC 7 6 5 4 CRC • CRC: Cyclic Redundancy Check Value This register can not be read if the COMPARE field of the CRC_MR register is set to true. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 325 21.7.12 CRCCU Interrupt Enable Register Name: CRCCU_IER Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • ERRIER: CRC Error Interrupt Enable 326 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRIER 21.7.13 CRCCU Interrupt Disable Register Name: CRCCU_IDR Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRIDR • ERRIDR: CRC Error Interrupt Disable SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 327 21.7.14 CRCCU Interrupt Mask Register Name: CRCCU_IMR Access: Write-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • ERRIMR: CRC Error Interrupt Mask 328 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRIMR 21.7.15 CRCCU Interrupt Status Register Name: CRCCU_ISR Access: Read-only Reset: 31 – 23 – 15 – 7 – 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRISR • ERRISR: CRC Error Interrupt Status SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 329 22. SAM3S Boot Program 22.1 Description The SAM-BA® Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 22.2 Hardware and Software Constraints  SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be used for user's code.  USB Requirements: ̶ External Crystal or External Clock(1) with frequency of: 11,289 MHz 12,000 MHz 16,000 MHz 18,432 MHz  UART0 requirements: None Note: 22.3 1. must be 2500 ppm and 1.8V Square Wave Signal. Table 22-1. Pins Driven during Boot Program Execution Peripheral Pin PIO Line UART0 URXD0 PA9 UART0 UTXD0 PA10 Flow Diagram The Boot Program implements the algorithm in Figure 22-1. Figure 22-1. Boot Program Algorithm Flow Diagram No Device Setup No USB Enumeration Successful ? Yes Run SAM-BA Monitor Character # received from UART0? Yes Run SAM-BA Monitor The SAM-BA Boot program seeks to detect a source clock either from the embedded main oscillator with external crystal (main oscillator enabled) or from a supported frequency signal applied to the XIN pin (Main oscillator in bypass mode). If a clock is found from the two possible sources above, the boot program checks to verify that the frequency is one of the supported external frequencies. If the frequency is one of the supported external frequencies, USB activation is allowed, else (no clock or frequency other than one of the supported external frequencies), the internal 330 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 12 MHz RC oscillator is used as main clock and USB clock is not allowed due to frequency drift of the 12 MHz RC oscillator. 22.4 Device Initialization Initialization follows the steps described below: 1. Stack setup 2. Setup the Embedded Flash Controller 3. External Clock detection (crystal or external clock on XIN) 4. If external crystal or clock with supported frequency, allow USB activation 5. Else, does not allow USB activation and use internal 12 MHz RC oscillator 6. Main oscillator frequency detection if no external clock detected 7. Switch Master Clock on Main Oscillator 8. C variable initialization 9. PLLA setup: PLLA is initialized to generate a 96 MHz clock 10. Switch Master Clock on PLLA/2 11. Disable of the Watchdog 12. Initialization of UART0 (115200 bauds, 8, N, 1) 13. Initialization of the USB Device Port (in case of USB activation allowed) 14. Wait for one of the following events a. check if USB device enumeration has occurred b. check if characters have been received in UART0 15. Jump to SAM-BA Monitor (see Section 22.5 ”SAM-BA Monitor”) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 331 22.5 SAM-BA Monitor The SAM-BA boot principle: Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown in Table 22-2. Table 22-2. Command Action Argument(s) Example N set Normal mode No argument N# T set Terminal mode No argument T# O write a byte Address, Value# O200001,CA# o read a byte Address,# o200001,# H write a half word Address, Value# H200002,CAFE# h read a half word Address,# h200002,# W write a word Address, Value# W200000,CAFEDECA# w read a word Address,# w200000,# S send a file Address,# S200000,# R receive a file Address, NbOfBytes# R200000,1234# G go Address# G200200# V display version No argument V#   Mode commands: ̶ Normal mode configures SAM-BA Monitor to send/receive data in binary format, ̶ Terminal mode configures SAM-BA Monitor to send/receive data in ascii format. Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. ̶ ̶ ̶    Output: ‘>’. Address: Address in hexadecimal ̶ Output: The byte, halfword or word read in hexadecimal following by ‘>’ ̶ Address: Address in hexadecimal ̶ Output: ‘>’. There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. Receive a file (R): Receive data into a file from a specified address ̶ ̶  ̶ Send a file (S): Send a file to a specified address ̶  Address: Address in hexadecimal. Value: Byte, halfword or word to write in hexadecimal. Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. Note: 332 Commands Available through the SAM-BA Boot Address: Address in hexadecimal NbOfBytes: Number of bytes in hexadecimal to receive Output: ‘>’ Go (G): Jump to a specified address and execute the code ̶ Address: Address to jump in hexadecimal ̶ Output: ‘>’ Get Version (V): Return the SAM-BA boot version SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 ̶ Output: ‘>’ 22.5.1 UART0 Serial Port Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. See, Section 22.2 ”Hardware and Software Constraints” 22.5.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: ̶ = 01 hex ̶ = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) ̶ = 1’s complement of the blk#. ̶ = 2 bytes CRC16 Figure 22-2 shows a transmission using this protocol. Figure 22-2. Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 22.5.3 USB Device Port The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ® , beginning with Windows 98SE®. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 333 The Vendor ID (VID) is Atmel’s vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. For More details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the USB Implementers Forum: http://www.usb.org/developers/vendor/VID_Only_Form_withCCAuth_102407b.pdf "Unauthorized use of assigned or unassigned USB Vendor ID Numbers and associated Product ID Numbers is strictly prohibited." Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 22.5.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 22-3. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value. GET_STATUS Returns status for the specified recipient. SET_FEATURE Set or Enable a specific feature. CLEAR_FEATURE Clear or Disable a specific feature. The device also handles some class requests defined in the CDC class. Table 22-4. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 22.5.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 22.5.4 In Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. 334 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the EEFC_FSR register). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash. The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008). This function takes one argument in parameter: the command to be sent to the EEFC. This function returns the value of the EEFC_FSR register. IAP software code example: (unsigned int) (*IAP_Function)(unsigned long); void main (void){ unsigned unsigned unsigned unsigned long long long long FlashSectorNum = 200; // flash_cmd = 0; flash_status = 0; EFCIndex = 0; // 0:EEFC0, 1: EEFC1 /* Initialize the function pointer (retrieve function address from NMI vector) */ IAP_Function = ((unsigned long) (*)(unsigned long)) 0x00800008; /* Send your data to the sector here */ /* build the command to send to EEFC */ flash_cmd = (0x5A End of PWM period - If Synchronous Channel -> End of PWM period and UPDULOCK = 1 - If Asynchronous Channel -> End of PWM period - If Synchronous Channel - If UPDM = 0 -> End of PWM period and UPDULOCK = 1 - If UPDM = 1 or 2 -> End of PWM period and end of Update Period 866 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.6.5.4 Changing the Synchronous Channels Update Period It is possible to change the update period of synchronous channels while they are enabled. (See “Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 855 and “Method 3: Automatic write of duty-cycle values and automatic trigger of the update” on page 857.) To prevent an unexpected update of the synchronous channels registers, the user must use the “PWM Sync Channels Update Period Update Register” (PWM_SCUPUPD) to change the update period of synchronous channels while they are still enabled. This register holds the new value until the end of the update period of synchronous channels (when UPRCNT is equal to UPR in “PWM Sync Channels Update Period Register” (PWM_SCUP)) and the end of the current PWM period, then updates the value for the next period. Note: Note: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value is taken into account. Changing the update period does make sense only if there is one or more synchronous channels and if the update method 1 or 2 is selected (UPDM = 1 or 2 in “PWM Sync Channels Mode Register” ). Figure 37-18. Synchronized Update of Update Period Value of Synchronous Channels User's Writing PWM_SCUPUPD Value PWM_SCUP End of PWM period and end of Update Period of Synchronous Channels SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 867 37.6.5.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see Section 37.6.3 “PWM Comparison Units”). To prevent unexpected comparison match, the user must use the “PWM Comparison x Value Update Register” and the “PWM Comparison x Mode Update Register” (PWM_CMPxVUPD and PWM_CMPxMUPD) to change respectively the comparison values and the comparison configurations while the channel 0 is still enabled. These registers hold the new values until the end of the comparison update period (when CUPRCNT is equal to CUPR in “PWM Comparison x Mode Register” (PWM_CMPxM)) and the end of the current PWM period, then update the values for the next period. CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be followed by a write of the register PWM_CMPxMUPD. Note: If the update registers PWM_CMPxVUPD and PWM_CMPxMUPD are written several times between two updates, only the last written value are taken into account. Figure 37-19. Synchronized Update of Comparison Values and Configurations User's Writing User's Writing PWM_CMPxVUPD Value Comparison Value for comparison x PWM_CMPxMUPD Value Comparison configuration for comparison x PWM_CMPxV PWM_CMPxM End of channel0 PWM period and end of Comparison Update Period and and PWM_CMPxM written End of channel0 PWM period and end of Comparison Update Period 868 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.6.5.6 Interrupts Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can be generated at the end of the corresponding channel period (CHIDx in the PWM_ISR1 register), after a fault event (FCHIDx in the PWM_ISR1 register), after a comparison match (CMPMx in the PWM_ISR2 register), after a comparison update (CMPUx in the PWM_ISR2 register) or according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and UNRE in the PWM_ISR2 register). If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the PWM_ISR1 register occurs. If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a read operation in the PWM_ISR2 register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and PWM_IER2 registers. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR1 and PWM_IDR2 registers. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 869 37.6.5.7 Write Protect Registers To prevent any single software error that may corrupt PWM behavior, the registers listed below can be writeprotected by writing the field WPCMD in the “PWM Write Protect Control Register” on page 903 (PWM_WPCR). They are divided into 6 groups:  Register group 0: ̶  “PWM Clock Register” on page 874 Register group 1: ̶     “PWM Disable Register” on page 876 Register group 2: ̶ “PWM Sync Channels Mode Register” on page 882 ̶ “PWM Channel Mode Register” on page 910 ̶ “PWM Stepper Motor Mode Register” on page 902 Register group 3: ̶ “PWM Channel Period Register” on page 914 ̶ “PWM Channel Period Update Register” on page 915 Register group 4: ̶ “PWM Channel Dead Time Register” on page 917 ̶ “PWM Channel Dead Time Update Register” on page 918 Register group 5: ̶ “PWM Fault Mode Register” on page 896 ̶ “PWM Fault Protection Value Register” on page 899 ̶ There are two types of Write Protect:  Write Protect SW, which can be enabled or disabled.  Write Protect HW, which can just be enabled, only a hardware reset of the PWM controller can disable it. Both types of Write Protect can be applied independently to a particular register group by means of the WPCMD and WPRG fields in PWM_WPCR register. If at least one Write Protect is active, the register group is writeprotected. The field WPCMD allows to perform the following actions depending on its value:  0 = Disabling the Write Protect SW of the register groups of which the bit WPRG is at 1.  1 = Enabling the Write Protect SW of the register groups of which the bit WPRG is at 1.  2 = Enabling the Write Protect HW of the register groups of which the bit WPRG is at 1. At any time, the user can determine which Write Protect is active in which register group by the fields WPSWS and WPHWS in the “PWM Write Protect Status Register” on page 905 (PWM_WPSR). If a write access in a write-protected register is detected, then the WPVS flag in the PWM_WPSR register is set and the field WPVSRC indicates in which register the write access has been attempted, through its address offset without the two LSBs. The WPVS and PWM_WPSR fields are automatically reset after reading the PWM_WPSR register. 870 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7 Pulse Width Modulation (PWM) Controller User Interface Table 37-7. Register Mapping Offset Register Name Access Reset 0x00 PWM Clock Register PWM_CLK Read-write 0x0 0x04 PWM Enable Register PWM_ENA Write-only – 0x08 PWM Disable Register PWM_DIS Write-only – 0x0C PWM Status Register PWM_SR Read-only 0x0 0x10 PWM Interrupt Enable Register 1 PWM_IER1 Write-only – 0x14 PWM Interrupt Disable Register 1 PWM_IDR1 Write-only – 0x18 PWM Interrupt Mask Register 1 PWM_IMR1 Read-only 0x0 0x1C PWM Interrupt Status Register 1 PWM_ISR1 Read-only 0x0 0x20 PWM Sync Channels Mode Register PWM_SCM Read-write 0x0 0x24 Reserved – – 0x28 PWM Sync Channels Update Control Register PWM_SCUC Read-write 0x0 0x2C PWM Sync Channels Update Period Register PWM_SCUP Read-write 0x0 0x30 PWM Sync Channels Update Period Update Register PWM_SCUPUPD Write-only 0x0 0x34 PWM Interrupt Enable Register 2 PWM_IER2 Write-only – 0x38 PWM Interrupt Disable Register 2 PWM_IDR2 Write-only – 0x3C PWM Interrupt Mask Register 2 PWM_IMR2 Read-only 0x0 0x40 PWM Interrupt Status Register 2 PWM_ISR2 Read-only 0x0 0x44 PWM Output Override Value Register PWM_OOV Read-write 0x0 0x48 PWM Output Selection Register PWM_OS Read-write 0x0 0x4C PWM Output Selection Set Register PWM_OSS Write-only – 0x50 PWM Output Selection Clear Register PWM_OSC Write-only – 0x54 PWM Output Selection Set Update Register PWM_OSSUPD Write-only – 0x58 PWM Output Selection Clear Update Register PWM_OSCUPD Write-only – 0x5C PWM Fault Mode Register PWM_FMR Read-write 0x0 0x60 PWM Fault Status Register PWM_FSR Read-only 0x0 0x64 PWM Fault Clear Register PWM_FCR Write-only – 0x68 PWM Fault Protection Value Register PWM_FPV Read-write 0x0 0x6C PWM Fault Protection Enable Register PWM_FPE Read-write 0x0 0x70-0x78 Reserved – – 0x7C PWM Event Line 0 Mode Register PWM_EL0MR Read-write 0x0 0x80 PWM Event Line 1 Mode Register PWM_EL1MR Read-write 0x0 0x84-AC Reserved – – 0xB0 PWM Stepper Motor Mode Register Read-write 0x0 0xB4-E0 Reserved – – 0xE4 PWM Write Protect Control Register Write-only – – – – PWM_SMMR – PWM_WPCR SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 871 Table 37-7. Register Mapping (Continued) Offset Register Name Access Reset 0xE8 PWM Write Protect Status Register PWM_WPSR Read-only 0x0 0x100 - 0x128 Reserved for PDC registers – – – 0x12C Reserved – – – 0x130 PWM Comparison 0 Value Register PWM_CMP0V Read-write 0x0 0x134 PWM Comparison 0 Value Update Register PWM_CMP0VUPD Write-only – 0x138 PWM Comparison 0 Mode Register PWM_CMP0M Read-write 0x0 0x13C PWM Comparison 0 Mode Update Register PWM_CMP0MUPD Write-only – 0x140 PWM Comparison 1 Value Register PWM_CMP1V Read-write 0x0 0x144 PWM Comparison 1 Value Update Register PWM_CMP1VUPD Write-only – 0x148 PWM Comparison 1 Mode Register PWM_CMP1M Read-write 0x0 0x14C PWM Comparison 1 Mode Update Register PWM_CMP1MUPD Write-only – 0x150 PWM Comparison 2 Value Register PWM_CMP2V Read-write 0x0 0x154 PWM Comparison 2 Value Update Register PWM_CMP2VUPD Write-only – 0x158 PWM Comparison 2 Mode Register PWM_CMP2M Read-write 0x0 0x15C PWM Comparison 2 Mode Update Register PWM_CMP2MUPD Write-only – 0x160 PWM Comparison 3 Value Register PWM_CMP3V Read-write 0x0 0x164 PWM Comparison 3 Value Update Register PWM_CMP3VUPD Write-only – 0x168 PWM Comparison 3 Mode Register PWM_CMP3M Read-write 0x0 0x16C PWM Comparison 3 Mode Update Register PWM_CMP3MUPD Write-only – 0x170 PWM Comparison 4 Value Register PWM_CMP4V Read-write 0x0 0x174 PWM Comparison 4 Value Update Register PWM_CMP4VUPD Write-only – 0x178 PWM Comparison 4 Mode Register PWM_CMP4M Read-write 0x0 0x17C PWM Comparison 4 Mode Update Register PWM_CMP4MUPD Write-only – 0x180 PWM Comparison 5 Value Register PWM_CMP5V Read-write 0x0 0x184 PWM Comparison 5 Value Update Register PWM_CMP5VUPD Write-only – 0x188 PWM Comparison 5 Mode Register PWM_CMP5M Read-write 0x0 0x18C PWM Comparison 5 Mode Update Register PWM_CMP5MUPD Write-only – 0x190 PWM Comparison 6 Value Register PWM_CMP6V Read-write 0x0 0x194 PWM Comparison 6 Value Update Register PWM_CMP6VUPD Write-only – 0x198 PWM Comparison 6 Mode Register PWM_CMP6M Read-write 0x0 0x19C PWM Comparison 6 Mode Update Register PWM_CMP6MUPD Write-only – 0x1A0 PWM Comparison 7 Value Register PWM_CMP7V Read-write 0x0 0x1A4 PWM Comparison 7 Value Update Register PWM_CMP7VUPD Write-only – 0x1A8 PWM Comparison 7 Mode Register PWM_CMP7M Read-write 0x0 0x1AC PWM Comparison 7 Mode Update Register PWM_CMP7MUPD Write-only – 0x1B0 - 0x1FC Reserved – – 872 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 – Table 37-7. Register Mapping (Continued) Offset Register Name Access Reset 0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register(1) PWM_CMR Read-write 0x0 0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register(1) PWM_CDTY Read-write 0x0 0x200 + ch_num * 0x20 + 0x08 PWM Channel Duty Cycle Update Register(1) PWM_CDTYUPD Write-only – 0x200 + ch_num * 0x20 + 0x0C PWM Channel Period Register(1) PWM_CPRD Read-write 0x0 0x200 + ch_num * 0x20 + 0x10 PWM Channel Period Update Register(1) PWM_CPRDUPD Write-only – 0x200 + ch_num * 0x20 + 0x14 PWM Channel Counter Register(1) PWM_CCNT Read-only 0x0 0x200 + ch_num * 0x20 + 0x18 PWM Channel Dead Time Register(1) PWM_DT Read-write 0x0 Write-only – 0x200 + ch_num * PWM_DTUPD PWM Channel Dead Time Update Register(1) 0x20 + 0x1C Notes: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 873 37.7.1 PWM Clock Register Name: PWM_CLK Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 11 10 DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA This register can only be written if the bits WPSWS0 and WPHWS0 are cleared in “PWM Write Protect Status Register” on page 905. • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor. • PREA, PREB: CLKA, CLKB Source Clock Selection PREA, PREB Divider Input Clock 0 0 0 0 MCK 0 0 0 1 MCK/2 0 0 1 0 MCK/4 0 0 1 1 MCK/8 0 1 0 0 MCK/16 0 1 0 1 MCK/32 0 1 1 0 MCK/64 0 1 1 1 MCK/128 1 0 0 0 MCK/256 1 0 0 1 MCK/512 1 0 1 0 MCK/1024 Other 874 Reserved SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.2 PWM Enable Register Name: PWM_ENA Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 875 37.7.3 PWM Disable Register Name: PWM_DIS Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 This register can only be written if the bits WPSWS1 and WPHWS1 are cleared in “PWM Write Protect Status Register” on page 905. • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x. 876 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.4 PWM Status Register Name: PWM_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 877 37.7.5 PWM Interrupt Enable Register 1 Name: PWM_IER1 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x Interrupt Enable • FCHIDx: Fault Protection Trigger on Channel x Interrupt Enable 878 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.6 PWM Interrupt Disable Register 1 Name: PWM_IDR1 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x Interrupt Disable • FCHIDx: Fault Protection Trigger on Channel x Interrupt Disable SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 879 37.7.7 PWM Interrupt Mask Register 1 Name: PWM_IMR1 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x Interrupt Mask • FCHIDx: Fault Protection Trigger on Channel x Interrupt Mask 880 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.8 PWM Interrupt Status Register 1 Name: PWM_ISR1 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x 0 = No new counter event has occurred since the last read of the PWM_ISR1 register. 1 = At least one counter event has occurred since the last read of the PWM_ISR1 register. • FCHIDx: Fault Protection Trigger on Channel x 0 = No new trigger of the fault protection since the last read of the PWM_ISR1 register. 1 = At least one trigger of the fault protection since the last read of the PWM_ISR1 register. Note: Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 881 37.7.9 PWM Sync Channels Mode Register Name: PWM_SCM Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 PTRCS 21 20 PTRM 19 – 18 – 17 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 16 UPDM This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on page 905. • SYNCx: Synchronous Channel x 0 = Channel x is not a synchronous channel. 1 = Channel x is a synchronous channel. • UPDM: Synchronous Channels Update Mode 0 = Manual write of double buffer registers and manual update of synchronous channels. The update occurs at the beginning of the next PWM period, when the bit UPDULOCK in “PWM Sync Channels Update Control Register” on page 883 is set. 1 = Manual write of double buffer registers and automatic update of synchronous channels. The update occurs when the Update Period is elapsed. 2 = Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels. The update occurs when the Update Period is elapsed. 3 = Reserved. • PTRM: PDC Transfer Request Mode UPDM PTRM WRDY Flag and PDC Transfer Request 0 x The WRDY flag in “PWM Interrupt Status Register 2” on page 889 and the PDC transfer request are never set to 1. 1 x The WRDY flag in “PWM Interrupt Status Register 2” on page 889 is set to 1 as soon as the update period is elapsed, the PDC transfer request is never set to 1. 0 The WRDY flag in “PWM Interrupt Status Register 2” on page 889 and the PDC transfer request are set to 1 as soon as the update period is elapsed. 1 The WRDY flag in “PWM Interrupt Status Register 2” on page 889 and the PDC transfer request are set to 1 as soon as the selected comparison matches. 2 • PTRCS: PDC Transfer Request Comparison Selection Selection of the comparison used to set the flag WRDY and the corresponding PDC transfer request. 882 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.10 PWM Sync Channels Update Control Register Name: PWM_SCUC Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 UPDULOCK • UPDULOCK: Synchronous Channels Update Unlock 0 = No effect 1 = If the UPDM field is set to “0” in “PWM Sync Channels Mode Register” on page 882, writing the UPDULOCK bit to “1” triggers the update of the period value, the duty-cycle and the dead-time values of synchronous channels at the beginning of the next PWM period. If the field UPDM is set to “1” or “2”, writing the UPDULOCK bit to “1” triggers only the update of the period value and of the dead-time values of synchronous channels. This bit is automatically reset when the update is done. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 883 37.7.11 PWM Sync Channels Update Period Register Name: PWM_SCUP Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UPRCNT UPR • UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register” on page 882). This time is equal to UPR+1 periods of the synchronous channels. • UPRCNT: Update Period Counter Reports the value of the Update Period Counter. 884 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.12 PWM Sync Channels Update Period Update Register Name: PWM_SCUPUPD Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels. • UPRUPD: Update Period Update Defines the wanted time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register” on page 882). This time is equal to UPR+1 periods of the synchronous channels. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 885 37.7.13 PWM Interrupt Enable Register 2 Name: PWM_IER2 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY • WRDY: Write Ready for Synchronous Channels Update Interrupt Enable • ENDTX: PDC End of TX Buffer Interrupt Enable • TXBUFE: PTX Buffer Empty Interrupt Enable • UNRE: Synchronous Channels Update Underrun Error Interrupt Enable • CMPMx: Comparison x Match Interrupt Enable • CMPUx: Comparison x Update Interrupt Enable 886 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.14 PWM Interrupt Disable Register 2 Name: PWM_IDR2 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY • WRDY: Write Ready for Synchronous Channels Update Interrupt Disable • ENDTX: PDC End of TX Buffer Interrupt Disable • TXBUFE: PDC TX Buffer Empty Interrupt Disable • UNRE: Synchronous Channels Update Underrun Error Interrupt Disable • CMPMx: Comparison x Match Interrupt Disable • CMPUx: Comparison x Update Interrupt Disable SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 887 37.7.15 PWM Interrupt Mask Register 2 Name: PWM_IMR2 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY • WRDY: Write Ready for Synchronous Channels Update Interrupt Mask • ENDTX: PDC End of TX Buffer Interrupt Mask • TXBUFE: PDC TX Buffer Empty Interrupt Mask • UNRE: Synchronous Channels Update Underrun Error Interrupt Mask • CMPMx: Comparison x Match Interrupt Mask • CMPUx: Comparison x Update Interrupt Mask 888 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.16 PWM Interrupt Status Register 2 Name: PWM_ISR2 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 TXBUFE 1 ENDTX 0 WRDY • WRDY: Write Ready for Synchronous Channels Update 0 = New duty-cycle and dead-time values for the synchronous channels cannot be written. 1 = New duty-cycle and dead-time values for the synchronous channels can be written. • ENDTX: PDC End of TX Buffer 0 = The Transmit Counter register has not reached 0 since the last write of the PDC. 1 = The Transmit Counter register has reached 0 since the last write of the PDC. • TXBUFE: PDC TX Buffer Empty 0 = PWM_TCR or PWM_TCNR has a value other than 0. 1 = Both PWM_TCR and PWM_TCNR have a value other than 0. • UNRE: Synchronous Channels Update Underrun Error 0 = No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. 1 = At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. • CMPMx: Comparison x Match 0 = The comparison x has not matched since the last read of the PWM_ISR2 register. 1 = The comparison x has matched at least one time since the last read of the PWM_ISR2 register. • CMPUx: Comparison x Update 0 = The comparison x has not been updated since the last read of the PWM_ISR2 register. 1 = The comparison x has been updated at least one time since the last read of the PWM_ISR2 register. Note: Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 889 37.7.17 PWM Output Override Value Register Name: PWM_OOV Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OOVL3 18 OOVL2 17 OOVL1 16 OOVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OOVH3 2 OOVH2 1 OOVH1 0 OOVH0 • OOVHx: Output Override Value for PWMH output of the channel x 0 = Override value is 0 for PWMH output of channel x. 1 = Override value is 1 for PWMH output of channel x. • OOVLx: Output Override Value for PWML output of the channel x 0 = Override value is 0 for PWML output of channel x. 1 = Override value is 1 for PWML output of channel x. 890 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.18 PWM Output Selection Register Name: PWM_OS Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSL3 18 OSL2 17 OSL1 16 OSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSH3 2 OSH2 1 OSH1 0 OSH0 • OSHx: Output Selection for PWMH output of the channel x 0 = Dead-time generator output DTOHx selected as PWMH output of channel x. 1 = Output override value OOVHx selected as PWMH output of channel x. • OSLx: Output Selection for PWML output of the channel x 0 = Dead-time generator output DTOLx selected as PWML output of channel x. 1 = Output override value OOVLx selected as PWML output of channel x. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 891 37.7.19 PWM Output Selection Set Register Name: PWM_OSS Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSL3 18 OSSL2 17 OSSL1 16 OSSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSH3 2 OSSH2 1 OSSH1 0 OSSH0 • OSSHx: Output Selection Set for PWMH output of the channel x 0 = No effect. 1 = Output override value OOVHx selected as PWMH output of channel x. • OSSLx: Output Selection Set for PWML output of the channel x 0 = No effect. 1 = Output override value OOVLx selected as PWML output of channel x. 892 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.20 PWM Output Selection Clear Register Name: PWM_OSC Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCL3 18 OSCL2 17 OSCL1 16 OSCL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCH3 2 OSCH2 1 OSCH1 0 OSCH0 • OSCHx: Output Selection Clear for PWMH output of the channel x 0 = No effect. 1 = Dead-time generator output DTOHx selected as PWMH output of channel x. • OSCLx: Output Selection Clear for PWML output of the channel x 0 = No effect. 1 = Dead-time generator output DTOLx selected as PWML output of channel x. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 893 37.7.21 PWM Output Selection Set Update Register Name: PWM_OSSUPD Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSUPL3 18 OSSUPL2 17 OSSUPL1 16 OSSUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSUPH3 2 OSSUPH2 1 OSSUPH1 0 OSSUPH0 • OSSUPHx: Output Selection Set for PWMH output of the channel x 0 = No effect. 1 = Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period. • OSSUPLx: Output Selection Set for PWML output of the channel x 0 = No effect. 1 = Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period. 894 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.22 PWM Output Selection Clear Update Register Name: PWM_OSCUPD Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCUPL3 18 OSCUPL2 17 OSCUPL1 16 OSCUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCUPH3 2 OSCUPH2 1 OSCUPH1 0 OSCUPH0 • OSCUPHx: Output Selection Clear for PWMH output of the channel x 0 = No effect. 1 = Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period. • OSCUPLx: Output Selection Clear for PWML output of the channel x 0 = No effect. 1 = Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 895 37.7.23 PWM Fault Mode Register Name: PWM_FMR Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 FFIL 15 14 13 12 FMOD 7 6 5 4 FPOL This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 905. • FPOL: Fault Polarity (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The fault y becomes active when the fault input y is at 0. 1 = The fault y becomes active when the fault input y is at 1. • FMOD: Fault Activation Mode (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The fault y is active as long as bit y of FPOL field is set. 1 = The fault y becomes active as soon as bit y of FPOL field is set. The fault y stays active until bit y of FPOL field is unset AND until it is cleared in “PWM Fault Clear Register” on page 898. • FFIL: Fault Filtering (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The fault input y is not filtered. 1 = The fault input y is filtered. CAUTION: To prevent an unexpected activation of the status flag FSy in the “PWM Fault Status Register” on page 897, the bit FMODy can be set to “1” only if the FPOLy bit has been previously configured to its final value. 896 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.24 PWM Fault Status Register Name: PWM_FSR Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 FS 7 6 5 4 FIV • FIV: Fault Input Value (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The current sampled value of the fault input y is 0 (after filtering if enabled). 1 = The current sampled value of the fault input y is 1 (after filtering if enabled). • FS: Fault Status (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = The fault y is not currently active. 1 = The fault y is currently active. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 897 37.7.25 PWM Fault Clear Register Name: PWM_FCR Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 FCLR • FCLR: Fault Clear (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = No effect. 1 = If bit y of FMOD field is set to 1 and if the fault input y is not at the level defined by the bit y of FPOL field, the fault y is cleared and becomes inactive (FMOD and FPOL fields belong to “PWM Fault Mode Register” on page 896), else writing this bit to 1 has no effect. 898 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.26 PWM Fault Protection Value Register Name: PWM_FPV Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPVL3 18 FPVL2 17 FPVL1 16 FPVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPVH3 2 FPVH2 1 FPVH1 0 FPVH0 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 905. • FPVHx: Fault Protection Value for PWMH output on channel x 0 = PWMH output of channel x is forced to 0 when fault occurs. 1 = PWMH output of channel x is forced to 1 when fault occurs. • FPVLx: Fault Protection Value for PWML output on channel x 0 = PWML output of channel x is forced to 0 when fault occurs. 1 = PWML output of channel x is forced to 1 when fault occurs. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 899 37.7.27 PWM Fault Protection Enable Register Name: PWM_FPE Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page 905. Only the first 6 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant. • FPEx: Fault Protection Enable for channel x (fault input bit varies from 0 to 5) For each field bit y (fault input number): 0 = Fault y is not used for the Fault Protection of channel x. 1 = Fault y is used for the Fault Protection of channel x. CAUTION: To prevent an unexpected activation of the Fault Protection, the bit y of FPEx field can be set to “1” only if the corresponding FPOL bit has been previously configured to its final value in “PWM Fault Mode Register” on page 896. 900 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.28 PWM Event Line x Register Name: PWM_ELxMR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CSEL7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0 • CSELy: Comparison y Selection 0 = A pulse is not generated on the event line x when the comparison y matches. 1 = A pulse is generated on the event line x when the comparison y match. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 901 37.7.29 PWM Stepper Motor Mode Register Name: PWM_SMMR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 18 17 DOWN1 16 DOWN0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 GCEN1 0 GCEN0 • GCENx: Gray Count ENable 0 = Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1] 1 = enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1. • DOWNx: DOWN Count 0 = Up counter. 1 = Down counter. 902 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.30 PWM Write Protect Control Register Name: PWM_WPCR Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WPRG1 2 WPRG0 1 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 WPRG5 6 WPRG4 5 WPRG3 4 WPRG2 0 WPCMD • WPCMD: Write Protect Command This command is performed only if the WPKEY value is correct. 0 = Disable the Write Protect SW of the register groups of which the bit WPRGx is at 1. 1 = Enable the Write Protect SW of the register groups of which the bit WPRGx is at 1. 2 = Enable the Write Protect HW of the register groups of which the bit WPRGx is at 1. 3 = No effect. Note: Only a hardware reset of the PWM controller can disable the Write Protect HW. • WPRGx: Write Protect Register Group x 0 = The WPCMD command has no effect on the register group x. 1 = The WPCMD command is applied to the register group x. • WPKEY: Write Protect Key Should be written at value 0x50574D (“PWM” in ASCII). Writing any other value in this field aborts the write operation of the WPCMD field. Always reads as 0. List of register groups: • Register group 0: – “PWM Clock Register” on page 874 • Register group 1: – “PWM Disable Register” on page 876 • Register group 2: – “PWM Sync Channels Mode Register” on page 882 – “PWM Channel Mode Register” on page 910 – “PWM Stepper Motor Mode Register” on page 902 • Register group 3: – “PWM Channel Period Register” on page 914 – “PWM Channel Period Update Register” on page 915 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 903 • Register group 4: – “PWM Channel Dead Time Register” on page 917 – “PWM Channel Dead Time Update Register” on page 918 • Register group 5: – “PWM Fault Mode Register” on page 896 – “PWM Fault Protection Value Register” on page 899 904 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.31 PWM Write Protect Status Register Name: PWM_WPSR Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 WPVSRC 23 22 21 20 WPVSRC 15 – 14 – 13 WPHWS5 12 WPHWS4 11 WPHWS3 10 WPHWS2 9 WPHWS1 8 WPHWS0 7 WPVS 6 – 5 WPSWS5 4 WPSWS4 3 WPSWS3 2 WPSWS2 1 WPSWS1 0 WPSWS0 • WPSWSx: Write Protect SW Status 0 = The Write Protect SW x of the register group x is disabled. 1 = The Write Protect SW x of the register group x is enabled. • WPHWSx: Write Protect HW Status 0 = The Write Protect HW x of the register group x is disabled. 1 = The Write Protect HW x of the register group x is enabled. • WPVS: Write Protect Violation Status 0 = No Write Protect violation has occurred since the last read of the PWM_WPSR register. 1 = At least one Write Protect violation has occurred since the last read of the PWM_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset) in which a write access has been attempted. Note: The two LSBs of the address offset of the write-protected register are not reported Note: Reading PWM_WPSR automatically clears WPVS and WPVSRC fields. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 905 37.7.32 PWM Comparison x Value Register Name: Access: PWM_CMPxV Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVM 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 16 bits (channel counter size) of field CV are significant. • CV: Comparison x Value Define the comparison x value to be compared with the counter of the channel 0. • CVM: Comparison x Value Mode 0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing. 1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing. Note: This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in “PWM Channel Mode Register” on page 910) 906 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.33 PWM Comparison x Value Update Register Name: Access: PWM_CMPxVUPD Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVMUPD 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match. Only the first 16 bits (channel counter size) of field CVUPD are significant. • CVUPD: Comparison x Value Update Define the comparison x value to be compared with the counter of the channel 0. • CVMUPD: Comparison x Value Mode Update 0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing. 1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing. Note: This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in “PWM Channel Mode Register” on page 910) CAUTION: to be taken into account, the write of the register PWM_CMPxVUPD must be followed by a write of the register PWM_CMPxMUPD. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 907 37.7.34 PWM Comparison x Mode Register Name: Access: PWM_CMPxM Read-write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 21 20 19 18 CUPRCNT 15 14 13 6 24 – 17 16 9 8 1 – 0 CEN CUPR 12 11 10 CPRCNT 7 25 – CPR 5 4 CTR 3 – 2 – • CEN: Comparison x Enable 0 = The comparison x is disabled and can not match. 1 = The comparison x is enabled and can match. • CTR: Comparison x Trigger The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR. • CPR: Comparison x Period CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter. • CPRCNT: Comparison x Period Counter Reports the value of the comparison x period counter. Note: The field CPRCNT is read-only • CUPR: Comparison x Update Period Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter. • CUPRCNT: Comparison x Update Period Counter Reports the value of the comparison x update period counter. Note: The field CUPRCNT is read-only 908 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.35 PWM Comparison x Mode Update Register Name: Access: PWM_CMPxMUPD Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 – 11 7 6 5 4 3 – CTRUPD 25 – 24 – 17 16 9 8 1 – 0 CENUPD CUPRUPD 10 CPRUPD 2 – This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x match. • CENUPD: Comparison x Enable Update 0 = The comparison x is disabled and can not match. 1 = The comparison x is enabled and can match. • CTRUPD: Comparison x Trigger Update The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR. • CPRUPD: Comparison x Period Update CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter. • CUPRUPD: Comparison x Update Period Update Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 909 37.7.36 PWM Channel Mode Register Name: PWM_CMRx [x=0..3] Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 DTLI 17 DTHI 16 DTE 15 – 14 – 13 – 12 – 11 – 10 CES 9 CPOL 8 CALG 7 – 6 – 5 – 4 – 3 2 1 0 CPRE This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on page 905. • CPRE: Channel Pre-scaler CPRE Channel Pre-scaler 0 0 0 0 MCK 0 0 0 1 MCK/2 0 0 1 0 MCK/4 0 0 1 1 MCK/8 0 1 0 0 MCK/16 0 1 0 1 MCK/32 0 1 1 0 MCK/64 0 1 1 1 MCK/128 1 0 0 0 MCK/256 1 0 0 1 MCK/512 1 0 1 0 MCK/1024 1 0 1 1 CLKA 1 1 0 0 CLKB Other Reserved • CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned. • CPOL: Channel Polarity 0 = The OCx output waveform (output from the comparator) starts at a low level. 1 = The OCx output waveform (output from the comparator) starts at a high level. 910 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 • CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in the “PWM Interrupt Status Register 1” on page 881). CALG = 0 (Left Alignment): 0/1 = The channel counter event occurs at the end of the PWM period. CALG = 1 (Center Alignment): 0 = The channel counter event occurs at the end of the PWM period. 1 = The channel counter event occurs at the end of the PWM period and at half the PWM period. • DTE: Dead-Time Generator Enable 0 = The dead-time generator is disabled. 1 = The dead-time generator is enabled. • DTHI: Dead-Time PWMHx Output Inverted 0 = The dead-time PWMHx output is not inverted. 1 = The dead-time PWMHx output is inverted. • DTLI: Dead-Time PWMLx Output Inverted 0 = The dead-time PWMLx output is not inverted. 1 = The dead-time PWMLx output is inverted. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 911 37.7.37 PWM Channel Duty Cycle Register Name: PWM_CDTYx [x=0..3] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (channel counter size) are significant. • CDTY: Channel Duty-Cycle Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx). 912 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.38 PWM Channel Duty Cycle Update Register Name: PWM_CDTYUPDx [x=0..3] Access: Write-only. 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle. Only the first 16 bits (channel counter size) are significant. • CDTYUPD: Channel Duty-Cycle Update Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx). SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 913 37.7.39 PWM Channel Period Register Name: PWM_CPRDx [x=0..3] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register” on page 905. Only the first 16 bits (channel counter size) are significant. • CPRD: Channel Period If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (-----------------------------X × CPRD )MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (----------------------------------------CRPD × DIVA )( CRPD × DIVB ) or -----------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (---------------------------------------2 × X × CPRD ) MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (--------------------------------------------------2 × CPRD × DIVA ) ( 2 × CPRD × DIVB ) or --------------------------------------------------MCK MCK 914 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.40 PWM Channel Period Update Register Name: PWM_CPRDUPDx [x=0..3] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRDUPD 15 14 13 12 CPRDUPD 7 6 5 4 CPRDUPD This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register” on page 905. This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform period. Only the first 16 bits (channel counter size) are significant. • CPRDUPD: Channel Period Update If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (-------------------------------------------X × CPRDUPD ) MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (------------------------------------------------------CRPDUPD × DIVA )( CRPDUPD × DIVB ) or -------------------------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (----------------------------------------------------2 × X × CPRDUPD -) MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2 × CPRDUPD × DIVA -) ( 2 × CPRDUPD × DIVB ) ---------------------------------------------------------------or ----------------------------------------------------------------MCK MCK SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 915 37.7.41 PWM Channel Counter Register Name: PWM_CCNTx [x=0..3] Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 16 bits (channel counter size) are significant. • CNT: Channel Counter Register Channel counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register). • the channel counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. 916 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 37.7.42 PWM Channel Dead Time Register Name: PWM_DTx [x=0..3] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page 905. Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant. • DTH: Dead-Time Value for PWMHx Output Defines the dead-time value for PWMHx output. This value must be defined between 0 and CPRD-CDTY (PWM_CPRx and PWM_CDTYx). • DTL: Dead-Time Value for PWMLx Output Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 917 37.7.43 PWM Channel Dead Time Update Register Name: PWM_DTUPDx [x=0..3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page 905. This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the dead-time values. Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant. • DTHUPD: Dead-Time Value Update for PWMHx Output Defines the dead-time value for PWMHx output. This value must be defined between 0 and CPRD-CDTY (PWM_CPRx and PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period. • DTLUPD: Dead-Time Value Update for PWMLx Output Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period. 918 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38. USB Device Port (UDP) 38.1 Description The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Table 38-1. USB Endpoint Description Mnemonic Dual-Bank(1) Max. Endpoint Size Endpoint Type 0 EP0 No 64 Control/Bulk/Interrupt 1 EP1 Yes 64 Bulk/Iso/Interrupt 2 EP2 Yes 64 Bulk/Iso/Interrupt 3 EP3 No 64 Control/Bulk/Interrupt 4 EP4 Yes 512 Bulk/Iso/Interrupt 5 EP5 Yes 512 Bulk/Iso/Interrupt 6 EP6 Yes 64 Bulk/Iso/Interrupt Endpoint Number 7 Note: EP7 Yes 64 Bulk/Iso/Interrupt 1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode. Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on the product, an external signal can be used to send a wake up to the USB host controller. 38.2 920 Embedded Characteristics  USB V2.0 full-speed compliant,12 Mbits per second.  Embedded USB V2.0 full-speed transceiver  Embedded 2688-byte dual-port RAM for endpoints  Eight endpoints ̶ Endpoint 0: 64 bytes ̶ Endpoint 1 and 2: 64 bytes ping-pong ̶ Endpoint 3: 64 bytes ̶ Endpoint 4 and 5: 512 bytes ping-pong ̶ Endpoint 6 and 7: 64 bytes ping-pong ̶ Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints  Suspend/resume logic  Integrated Pull-up on DDP  Pull-down resistor on DDM and DDP when disabled SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38.3 Block Diagram Figure 38-1. Block Diagram Atmel Bridge MCK USB Device APB to MCU Bus txoen U s e r UDPCK I n t e r f a c e udp_int W r a p p e r FIFO eopn Serial Interface Engine 12 MHz txd rxdm Embedded USB Transceiver DP DM rxd SIE rxdp Suspend/Resume Logic Master Clock Domain external_resume Dual Port RAM W r a p p e r Recovered 12 MHz Domain Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then notified that the device asks for a resume. This optional feature must also be negotiated with the host during the enumeration. 38.3.1 Signal Description Table 38-2. Signal Names Signal Name Description Type UDPCK 48 MHz clock input MCK Master clock input udp_int Interrupt line connected to the Advanced Interrupt Controller (AIC) input DDP USB D+ line I/O DDM USB D- line I/O SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 921 38.4 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pull-up on DP must be disabled in order to prevent feeding current to the host. The application should disconnect the transceiver, then remove the pull-up. 38.4.1 I/O Lines The USB pins are shared with PIO lines. By default, the USB function is activated, and pins DDP and DDM are used for USB. To configure DDP or DDM as PIOs, the user needs to configure the system I/O configuration register (CCFG_SYSIO) in the MATRIX. 38.4.2 Power Management The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of ± 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain). WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register. 38.4.3 Interrupt The USB device interface has an interrupt line connected to the Interrupt Controller. Handling the USB device interrupt requires programming the Interrupt Controller before configuring the UDP. 922 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38.5 Typical Connection Figure 38-2. Board Schematic to Interface Device Peripheral PIO 5V Bus Monitoring 27 K 47 K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 38.5.1 USB Device Transceiver The USB device transceiver is embedded in the product. A few discrete components are required as follows:  the application detects all device states as defined in chapter 9 of the USB specification;  to reduce power consumption the host is disconnected  for line termination. ̶ VBUS monitoring 38.5.2 VBUS Monitoring VBUS monitoring is required to detect host connection. VBUS monitoring is done using a standard PIO with internal pull-up disabled. When the host is switched off, it should be considered as a disconnect, the pull-up must be disabled in order to prevent powering the host through the pull-up resistor. When the host is disconnected and the transceiver is enabled, then DDP and DDM are floating. This may lead to over consumption. A solution is to enable the integrated pull-down by disabling the transceiver (TXVDIS = 1) and then remove the pull-up (PUON = 0). A termination serial resistor must be connected to DDP and DDM. The resistor value is defined in the electrical specification of the product (REXT). SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 923 38.6 Functional Description 38.6.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 38-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.0 Software Client 1 Software Client 2 Data Flow: Control Transfer EP0 Data Flow: Isochronous In Transfer USB Device 2.0 EP1 Block 1 Data Flow: Isochronous Out Transfer EP2 Data Flow: Control Transfer EP0 Data Flow: Bulk In Transfer USB Device 2.0 EP4 Block 2 Data Flow: Bulk Out Transfer EP5 USB Device endpoint configuration requires that in the first instance Control Transfer must be EP0. The Control Transfer endpoint EP0 is always used when a USB device is first configured (USB v. 2.0 specifications). 38.6.1.1 USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device. Table 38-4. USB Communication Flow Transfer Direction Bandwidth Supported Endpoint Size Error Detection Retrying Bidirectional Not guaranteed 8, 16, 32, 64 Yes Automatic Isochronous Unidirectional Guaranteed 512 Yes No Interrupt Unidirectional Not guaranteed ≤ 64 Yes Yes Bulk Unidirectional Not guaranteed 8, 16, 32, 64 Yes Yes Control 38.6.1.2 USB Bus Transactions Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing across the bus in packets: 1. Setup Transaction 924 2. Data IN Transaction 3. Data OUT Transaction SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38.6.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 38-5. USB Transfer Events Control Transfers(1) (3) Interrupt IN Transfer  Setup transaction > Data IN transactions > Status OUT transaction  Setup transaction > Data OUT transactions > Status IN transaction   Setup transaction > Status IN transaction Data IN transaction > Data IN transaction  Data OUT transaction > Data OUT transaction  Data IN transaction > Data IN transaction  Data OUT transaction > Data OUT transaction  Data IN transaction > Data IN transaction  Data OUT transaction > Data OUT transaction (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes: 1. 2. 3. Control transfer must use endpoints with no ping-pong attributes. Isochronous transfers must use endpoints with ping-pong attributes. Control transfers can be aborted using a stall handshake. A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 925 Figure 38-4. Control Read and Write Sequences Setup Stage Control Read Setup TX Data Stage Data OUT TX Setup Stage Control Write No Data Control Notes: Setup TX Status Stage Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Data IN TX Status IN TX Status Stage Status OUT TX 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 38.6.2 Handling Transactions with USB V2.0 Device Peripheral 38.6.2.1 Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint:  The USB device automatically acknowledges the setup packet?  RXSETUP is set in the UDP_CSRx register  An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. 926 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Figure 38-5. Setup Transaction Followed by a Data OUT Transaction Setup Received USB Bus Packets Setup PID Data Setup Setup Handled by Firmware ACK PID RXSETUP Flag Data OUT PID Data Out Received NAK PID Data OUT Data OUT ACK PID Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) FIFO (DPR) Content Data OUT PID XX Data Setup XX Data OUT 38.6.2.2 Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with pingpong attributes. Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx register (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 7. The application clears the TXCOMP in the endpoint’s UDP_CSRx. After the last packet has been sent, the application must clear TXCOMP once this has been set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 927 Figure 38-6. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX USB Bus Packets Data IN PID Microcontroller Load Data in FIFO Data IN 1 ACK PID Data IN PID NAK PID Data is Sent on USB Bus Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (UDP_CSRx) Set by the firmware Cleared by Hw Set by the firmware Cleared by Hw Interrupt Pending Interrupt Pending TXCOMP Flag (UDP_CSRx) Payload in FIFO Cleared by Firmware DPR access by the hardware DPR access by the firmware FIFO (DPR) Content Data IN 1 Load In Progress Cleared by Firmware Data IN 2 Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 38-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints Microcontroller 1st Data Payload USB Device Write Bank 0 Endpoint 1 USB Bus Read Read and Write at the Same Time 2nd Data Payload Bank 0 Endpoint 1 Bank 0 Endpoint 1 Bank 1 Endpoint 1 2nd Data Payload Bank 0 Endpoint 1 3rd Data Payload 3rd Data Payload 928 Data IN Packet Bank 1 Endpoint 1 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 1st Data Payload Data IN Packet Data IN Packet When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 38-8. Data IN Transfer for Ping-pong Endpoint Microcontroller Load Data IN Bank 0 USB Bus Packets Data IN PID TXPKTRDY Flag (UDP_MCSRx) Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 ACK PID Data IN FIFO (DPR) Written by Microcontroller Bank 0 FIFO (DPR) Bank 1 Data IN PID Cleared by USB Device, Data Payload Fully Transmitted Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (UDP_CSRx) Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 Data IN ACK PID Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device Set by USB Device Interrupt Cleared by Firmware Read by USB Device Written by Microcontroller Written by Microcontroller Read by USB Device Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the bandwidth. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. 38.6.2.3 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 929 Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s UDP_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 38-9. USB Bus Packets Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Data OUT PID ACK PID Data OUT 1 Data OUT2 PID RX_DATA_BK0 (UDP_CSRx) NAK PID Data OUT PID Data OUT2 ACK PID Interrupt Pending Set by USB Device FIFO (DPR) Content Data OUT2 Host Resends the Next Data Payload Data OUT 1 Written by USB Device Data OUT 1 Microcontroller Read Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. 930 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Figure 38-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller USB Device Write USB Bus Read Data IN Packet Bank 0 Endpoint 1 1st Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Data IN Packet nd 2 Data Payload Bank 1 Endpoint 1 Bank 0 Endpoint 1 Data IN Packet Write and Read at the Same Time 1st Data Payload 2nd Data Payload 3rd Data Payload 3rd Data Payload Bank 0 Endpoint 1 When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 931 Figure 38-11. Data OUT Transfer for Ping-pong Endpoint Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Host Sends First Data Payload USB Bus Packets Data OUT PID RX_DATA_BK0 Flag (UDP_CSRx) Data OUT 1 ACK PID Data OUT PID Data OUT 2 FIFO (DPR) Bank 0 Data OUT 3 A P Cleared by Firmware Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 RX_DATA_BK1 Flag (UDP_CSRx) Data OUT PID Cleared by Firmware Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 ACK PID Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload Interrupt Pending Data OUT1 Data OUT 1 Data OUT 3 Write by USB Device Read By Microcontroller Write In Progress FIFO (DPR) Bank 1 Data OUT 2 Write by USB Device Data OUT 2 Read By Microcontroller Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 38.6.2.4 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)  A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)  To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. 932 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Figure 38-12. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 38-13. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID Set by Firmware FORCESTALL Interrupt Pending STALLSENT Cleared by Firmware Set by USB Device SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 933 38.6.2.5 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availability refer to Table 38-1 ”USB Endpoint Description”. Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.  TXPKTRDY is not set: ̶  Reset the endpoint to clear the FIFO (pointers). (See, Section 38.7.9 ”UDP Reset Endpoint Register”.) TXPKTRDY has already been set: ̶ Clear TXPKTRDY so that no packet is ready to be sent ̶ Reset the endpoint to clear the FIFO (pointers). (See, Section 38.7.9 ”UDP Reset Endpoint Register”.) Endpoints With Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set.  TXPKTRDY is not set:  TXPKTRDY has already been set: ̶ 934 Reset the endpoint to clear the FIFO (pointers). (See, Section 38.7.9 ”UDP Reset Endpoint Register”.) ̶ Clear TXPKTRDY and read it back until actually read at 0. ̶ Set TXPKTRDY and read it back until actually read at 1. ̶ Clear TXPKTRDY so that no packet is ready to be sent. ̶ Reset the endpoint to clear the FIFO (pointers). (See, Section 38.7.9 ”UDP Reset Endpoint Register”.) SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 38-14. USB Device State Diagram Attached Hub Reset or Deconfigured Hub Configured Bus Inactive Suspended Powered Bus Activity Power Interruption Reset Bus Inactive Suspended Default Bus Activity Reset Address Assigned Bus Inactive Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Configured Suspended Bus Activity Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a USB mouse. The wake up feature is not mandatory for all devices and must be negotiated with the host. 38.6.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 935 38.6.3.2 Entering Attached State To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pull-up connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled. 38.6.3.3 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software must:  Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer.  Configure the interrupt mask register which has been reset by the USB reset detection  Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register. In this state UDPCK and MCK must be enabled. Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have been reset. 38.6.3.4 From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new address, and sets the FEN bit in the UDP_FADDR register. 38.6.3.5 From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 38.6.3.6 Entering in Suspend State When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks can be switched off. Resume event is asynchronously detected. MCK and UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register. 936 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 38.6.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pull-up shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the UDP_TXVC register. 38.6.3.8 Sending a Device Remote Wakeup In Suspend state it is possible to wake up the host sending an external resume.  The device must wait at least 5 ms after being entered in suspend before sending an external resume.  The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host.  The device must force a K state from 1 to 15 ms to resume the host Before sending a K state to the host, MCK, UDPCK and the transceiver must be enabled. Then to enable the remote wakeup feature, the RMWUPE bit in the UDP_GLB_STAT register must be enabled. To force the K state on the line, a transition of the ESR bit from 0 to 1 has to be done in the UDP_GLB_STAT register. This transition must be accomplished by first writing a 0 in the ESR bit and then writing a 1. The K state is automatically generated and released according to the USB 2.0 specification. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 937 38.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 38-6. Register Mapping Offset Register Name Access Reset 0x000 Frame Number Register UDP_FRM_NUM Read-only 0x0000_0000 0x004 Global State Register UDP_GLB_STAT Read-write 0x0000_0010 0x008 Function Address Register UDP_FADDR Read-write 0x0000_0100 0x00C Reserved – – – 0x010 Interrupt Enable Register UDP_IER Write-only 0x014 Interrupt Disable Register UDP_IDR Write-only 0x018 Interrupt Mask Register UDP_IMR Read-only 0x0000_1200 0x01C Interrupt Status Register UDP_ISR Read-only –(1) 0x020 Interrupt Clear Register UDP_ICR Write-only 0x024 Reserved – – – 0x028 Reset Endpoint Register UDP_RST_EP Read-write 0x0000_0000 0x02C Reserved – – – 0x030 Endpoint Control and Status Register 0 UDP_CSR0 Read-write 0x0000_0000 ... ... ... ... ... 0x030 + 0x4 * (7 - 1) Endpoint Control and Status Register 7 UDP_CSR7 Read-write 0x0000_0000 0x050 Endpoint FIFO Data Register 0 UDP_FDR0 Read-write 0x0000_0000 ... ... ... ... ... 0x050 + 0x4 * (7 - 1) Endpoint FIFO Data Register 7 UDP_FDR7 Read-write 0x0000_0000 0x070 Reserved – – – Read-write 0x0000_0100 – – 0x074 Transceiver Control Register UDP_TXVC 0x078 - 0xFC Reserved – Notes: 938 1. Reset values are not defined for UDP_ISR. 2. See Warning above the ”Register Mapping” on this page. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 (2) 38.7.1 UDP Frame Number Register Name: UDP_FRM_NUM Access: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). • FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. • FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 939 38.7.2 UDP Global State Register Name: UDP_GLB_STAT Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 RMWUPE 3 RSMINPR 2 ESR 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • ESR: Enable Send Resume 0 = Mandatory value prior to starting any Remote Wake Up procedure. 1 = Starts the Remote Wake Up procedure if this bit value was 0 and if RMWUPE is enabled. • RMWUPE: Remote Wake Up Enable 0 = The Remote Wake Up feature of the device is disabled. 1 = The Remote Wake Up feature of the device is enabled. 940 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38.7.3 UDP Function Address Register Name: UDP_FADDR Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. • FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 941 38.7.4 UDP Interrupt Enable Register Name: UDP_IER Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 – 11 SOFINT 10 EXTRSM 9 8 RXRSM RXSUSP 7 EP7INT 6 EP6INT 5 EP5INT 4 EP4INT 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Enable Endpoint 0 Interrupt • EP1INT: Enable Endpoint 1 Interrupt • EP2INT: Enable Endpoint 2Interrupt • EP3INT: Enable Endpoint 3 Interrupt • EP4INT: Enable Endpoint 4 Interrupt • EP5INT: Enable Endpoint 5 Interrupt • EP6INT: Enable Endpoint 6 Interrupt • EP7INT: Enable Endpoint 7 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. • RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt. • RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt. • SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. • WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt. 942 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38.7.5 UDP Interrupt Disable Register Name: UDP_IDR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 – 11 SOFINT 10 EXTRSM 9 8 RXRSM RXSUSP 7 EP7INT 6 EP6INT 5 EP5INT 4 EP4INT 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Disable Endpoint 0 Interrupt • EP1INT: Disable Endpoint 1 Interrupt • EP2INT: Disable Endpoint 2 Interrupt • EP3INT: Disable Endpoint 3 Interrupt • EP4INT: Disable Endpoint 4 Interrupt • EP5INT: Disable Endpoint 5 Interrupt • EP6INT: Disable Endpoint 6 Interrupt • EP7INT: Disable Endpoint 7 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. • RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt. • RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt. • SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt • WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 943 38.7.6 UDP Interrupt Mask Register Name: UDP_IMR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 BIT12 11 SOFINT 10 EXTRSM 9 8 RXRSM RXSUSP 7 EP7INT 6 EP6INT 5 EP5INT 4 EP4INT 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Mask Endpoint 0 Interrupt • EP1INT: Mask Endpoint 1 Interrupt • EP2INT: Mask Endpoint 2 Interrupt • EP3INT: Mask Endpoint 3 Interrupt • EP4INT: Mask Endpoint 4 Interrupt • EP5INT: Mask Endpoint 5 Interrupt • EP6INT: Mask Endpoint 6 Interrupt • EP7INT: Mask Endpoint 7 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. • RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled. • RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled. • SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. • BIT12: UDP_IMR Bit 12 Bit 12 of UDP_IMR cannot be masked and is always read at 1. 944 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 • WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 945 38.7.7 UDP Interrupt Status Register Name: UDP_ISR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 EXTRSM 9 8 RXRSM RXSUSP 7 EP7INT 6 EP6INT 5 EP5INT 4 EP4INT 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT • EP0INT: Endpoint 0 Interrupt Status • EP1INT: Endpoint 1 Interrupt Status • EP2INT: Endpoint 2 Interrupt Status • EP3INT: Endpoint 3 Interrupt Status • EP4INT: Endpoint 4 Interrupt Status • EP5INT: Endpoint 5 Interrupt Status • EP6INT: Endpoint 6 Interrupt Status • EP7INT: Endpoint 7Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit. • RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. 946 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 • RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register. • SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. • WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR register. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 947 38.7.8 UDP Interrupt Clear Register Name: UDP_ICR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 EXTRSM 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt. • SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. • ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt. • WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 948 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 38.7.9 UDP Reset Endpoint Register Name: UDP_RST_EP Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 EP7 6 EP6 5 EP5 4 EP4 3 EP3 2 EP2 1 EP1 0 EP0 • EP0: Reset Endpoint 0 • EP1: Reset Endpoint 1 • EP2: Reset Endpoint 2 • EP3: Reset Endpoint 3 • EP4: Reset Endpoint 4 • EP5: Reset Endpoint 5 • EP6: Reset Endpoint 6 • EP7: Reset Endpoint 7 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register. Resetting the endpoint is a two-step operation: 1. Set the corresponding EPx field. 2. Clear the corresponding EPx field. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 949 38.7.10 UDP Endpoint Control and Status Register Name: UDP_CSRx [x = 0..7] Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 25 RXBYTECNT 24 19 18 17 16 RXBYTECNT 15 EPEDS 14 – 13 – 12 – 11 DTGLE 10 9 EPTYPE 8 7 6 RX_DATA_ BK1 5 FORCE STALL 4 3 STALLSENT ISOERROR 2 1 RX_DATA_ BK0 0 DIR TXPKTRDY RXSETUP TXCOMP WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write operation before executing another write by polling the bits which must be set/cleared. #if defined ( __ICCARM__ ) #define nop() (__no_operation()) #elif defined #define nop() ( __GNUC__ ) __asm__ __volatile__ ( "nop" ) #endif /// Bitmap for all status bits in CSR that are not effected by a value 1. #define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0\ | AT91C_UDP_RX_DATA_BK1\ | AT91C_UDP_STALLSENT\ | AT91C_UDP_RXSETUP\ | AT91C_UDP_TXCOMP /// Sets the specified bit(s) in the UDP_CSR register. /// \param endpoint The endpoint number of the CSR to process. /// \param flags The bitmap to set to 1. #define SET_CSR(endpoint, flags) \ { \ volatile unsigned int reg; \ reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \ reg |= REG_NO_EFFECT_1_ALL; \ reg |= (flags); \ AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \ for( nop_count=0; nop_countUDP_CSR[endpoint]; \ reg |= REG_NO_EFFECT_1_ALL; \ reg &= ~(flags); \ AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \ for( nop_count=0; nop_count ‘technical’ 7536 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 Change Request Ref. Doc. Rev. 6500B Comments Overview: “Packages” on page 3, package size or pitch updated. 7214 Table 1-1, “Configuration Summary”, ADC column updated, footnote gives precision on reserved channel. 6981 Table 4-2, “100-ball TFBGA SAM3S4/S2/S1C Pinout”, pinout information is available. 7201 Figure 5-2, "Single Supply", Figure 5-3, "Core Externally Supplied.", updated notes below figures. 7243/rfo Figure 5-3, "Core Externally Supplied.", Figure 5-4, "Backup Battery", ADC,DAC, Analog Comparator supply is 2.0V-3.6V. Section 8.1.3.8 “Unique Identifier”, Each device integrates its own 128-bit unique identifier. 7307 ACC: Section 39.2 “Embedded Characteristics”, references to “window function” removed. 7103 Table 39-1, “Analog Comparator Controller Block Diagram”, signal names beginning as “AD” updated and hidden parts at top of block diagram revealed. Section 39.7.2 “ACC Mode Register”, SELMINUS bitfield description relocated in front of SELPLUS 6968 6865 ADC: Section 40.7 “Analog-to-Digital Converter (ADC) User Interface”, bitfield descriptions updated. (TRGEN, LOWRES, SLEEP, FWUP, FREERUN, ANACH, USEQ. TSMODE, TSAV, TRGMOD) 6796 CHIPID: Section 28.2.1 “Chip ID Register”, bitfields updated. 6796 “EPROC: Embedded Processor”, “ARCH: Architecture Identifier”, updated. 6967/7166 “SRAMSIZ: Internal SRAM Size”, replaced. 7215 Table 28-1, “ATSAM3S Chip IDs Register”, updated. CKGR/PMC: 7129 Section 26.5.1 “4/8/12 MHz Fast RC Oscillator”, two paragraphs removed. Section 26.5.2 “4/8/12 MHz Fast RC Oscillator Clock Frequency Adjustment”, added to datasheet Section 26.6.1 “Divider and Phase Lock Loop Programming”, added restraints on changing 4/8/12 MHz Fast RC 7130 oscillator at end of section. 7127 Section 27.12 “Main Crystal Clock Failure Detector”, added 3rd paragraph (“A failure is detected...”) & 6th paragraph (“It takes 2 slow clock...”) GPBR: Section 18.2 “Embedded Features”, there are eight general purpose backup registers on SAM3S devices. 7029 HSMCI: Section 36.2 “Embedded Characteristics”, updated; Compatibility with SDIO Specification V2.0. 7091 Section 36.11 “HSMCI Boot Operation Mode”, added “...not possible to boot directly on SD-CARD...” 6745 Table 37-8, “Register Mapping”, Reserved offsets updated. rfo: Section 36.14 “Hig Speed MultiMedia Card Interface (HSMCI) User Interface”, bitfield description s and tables updated. Table 37-8, “Register Mapping” and Section 36.14.19 “HSMCI FIFOx Memory Aperture”, HSMCI_FIFOx offset error corrected. 7253 PIO: Figure 29-3, "I/O Line Control Logic", Section 29.5.9 “Input Glitch and Debouncing Filters”, Section 29.7.26 “PIO 6875 Input Filter Slow Clock Disable Register”, Section 29.7.27 “PIO Input Filter Slow Clock Enable Register”, Section 29.7.28 “PIO Input Filter Slow Clock Status Register”; acronyms for ‘IFSxxx’ registers changed. Table 29-3, “Register Mapping”, Reserved addresses updated below Schmitt Trigger line. SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 7258 1103 Doc. Rev. 6500B Comments (Continued) Change Request Ref. RTC: Section 15.4.2 “Interrupt”, updated. 7071 SPI: Section 31.8.9 “SPI Chip Select Register”, after bit description “SCBR: Serial Clock Baud Rate” on page 611, added a note concerning data transfer. 7247 Section 31.8.3 “SPI Receive Data Register”, after bit description “PCS: Peripheral Chip Select” on page 603, added a note on requirements. Section 31.7.3.5 “Peripheral Selection”, added a paragraph at the end of the section. 7263 TC: Figure 35-3, "Clock Selection" and Figure 35-5, "Capture Mode", updated w/ synchronous edge detection. 7096 Section 35.7.2 “TC Block Mode Register”, updated Name and Description columns in TC0XC0S, TXC1XC1S, TXC2XC2S bitfield description tables. 7167 Section 35.7.11 “TC Channel Mode Register: Waveform Mode”In the TC_CMR register “WAVSEL: Waveform Selection” bitfield description 7190 UART: “CD: Clock Divisor”, bitfield description updated in UART_BRGR. 7187 Figure 33-1, "UART Functional Block Diagram", updated. 7285 UDP: Section 38.3.1 “Signal Description”, added to datasheet. rfo Section 38.4.1 “I/O Lines”, updated. 6773 Global; references to “DP”, “DM”, changed to “DPP”, “DMM”. rfo Table 38-6, “Register Mapping”, Offsets and Names for UDP_CSRY and Endpoint UDP_FDRY updated w/endpoint info. 6895 Section 38.7.10 “UDP Endpoint Control and Status Register”, code updated. 6896 USART: “CD: Clock Divider”, bitfield description, baud rate formula corrected in US_BRGR. 7186 Section 34.7.1 “Baud Rate Generator”, updated “The frequency of the signal provided on SCK...” 7096 Section 34.7.1.3 “Baud Rate in Synchronous Mode or SPI Mode”, updated, “the receive part limits the SCK...” Confusing text references to “DMAC/PDC“ replaced by PDC. 1104 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 7284 Change Request Ref. Doc. Rev. 6500B Comments (Continued) Electrical Characteristics: Table 42-2, “DC Characteristics” VOH/VOL Min/Max values swapped. 7208 Table 42-23, “4/8/12 MHz RC Oscillators Characteristics”, updated. rfo Table 42-7, “DC Flash Characteristics”, 1st cell , ISB deleted. rfo Table 42-27, “3 to 20 MHz Crystal Oscillator Characteristics”, CLEXT line modified. rfo Section 42.11 “AC Characteristics”, updated the following tables 7225 Table 42-52, “SPI Timings”, Table 42-53, “SSC Timings”, Table 42-54, “SMC Read Signals - NRD Controlled (READ_MODE = 1)”, Table 42-55, “SMC Read Signals - NCS Controlled (READ_MODE= 0)”, Table 42-56, “SMC Write Signals - NWE Controlled (WRITE_MODE = 1)”, Table 42-57, “SMC Write NCS Controlled (WRITE_MODE = 0)”, Table 42-58, “USART SPI Timings”, Table 42-60, “Embedded Flash Wait State VDDCORE set at 1.65V”, Table 42-61, “Embedded Flash Wait State VDDCORE set at 1.80V” Section 42.11.3.1 “Maximum SPI Frequency”, the following changes: rfo “Master Read Mode” ...FSPCKMax = 33 MHz... “Slave Write Mode” ...2x(SPI6max(orSPI9max) ......FSPCK Max = 25 MHz... Section 42.11.7 “USART in SPI Mode Timings”, all figures, tables and titles renamed USART from UART. Figure 42-32, Figure 42-32, updated with text on line drives. Table 42-34, “Analog Power Supply Characteristics”, updated IVDDANA line. Table 42-35, “Channel Conversion Time and ADC Clock”, fADC, tCP_A, tSTART-UP lines updated & added tSETTLING rfo Table 42-36, “External Voltage Reference Input”, removed ADVREF Settling Time. Table 42-41, “Analog Inputs”, Input Capacitance, Max value updated. Section 42.7.1 “Track and Hold Time versus Source Output Impedance”, replaced text below figure. Figure 42-34, SPI14 and SPI15 repositioned in respect to SCK rising and falling. 7320 Table 42-58, “USART SPI Timings”, all references to SPCK changed to SCK. Min values updated. Errata: Section 45. “Marking”, added to the datasheet. 7207/7316 Change Request Ref. Doc. Rev. 6500A Comments First Issue SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 1105 Table of Contents Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.3 5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6. SAM3S4/S2/S1C Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SAM3S4/S2/S1B Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SAM3S4/2/1A Package and Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Powering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 21 23 26 26 Input/Output Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 6.2 6.3 6.4 6.5 General Purpose I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 30 30 30 7. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1 8.2 9. Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 External Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1 9.2 System Controller and Peripherals Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Power-on-Reset, Brownout and Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 10.2 10.3 Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 APB/AHB bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Peripheral Signal Multiplexing on I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11. ARM Cortex® M3 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.1 11.2 11.3 1106 About this section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 About the Cortex-M3 processor and core peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 11.21 11.22 11.23 Memory model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Intrinsic functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 About the instruction descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 General data processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Multiply and divide instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Saturating instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Bitfield instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Branch and control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 About the Cortex-M3 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Nested Vectored Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 System control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 System timer, SysTick. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12. Debug and Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.1 12.2 12.3 12.4 12.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 209 210 211 212 13. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 13.1 13.2 13.3 13.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 217 217 224 14. Real-time Timer (RTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.1 14.2 14.3 14.4 14.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 228 228 229 231 15. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 15.1 15.2 15.3 15.4 15.5 15.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real Time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 236 237 237 238 241 16. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 16.1 16.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 1107 16.3 16.4 16.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 17. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 17.1 17.2 17.3 17.4 17.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 261 262 263 269 18. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 18.1 18.2 18.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Embedded Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 General Purpose Backup Registers (GPBR) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 19. Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 19.1 19.2 19.3 19.4 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced Embedded Flash Controller (EEFC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 280 280 291 20. Fast Flash Programming Interface (FFPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 20.1 20.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Parallel Fast Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 21. Cyclic Redundancy Check Calculation Unit (CRCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 21.1 21.2 21.3 21.4 21.5 21.6 21.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRCCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRCCU Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Control Registers Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface . . . . . . . . . . . . . . . . . . . . . . 308 308 308 309 309 310 314 22. SAM3S Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 22.1 22.2 22.3 22.4 22.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware and Software Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 330 330 331 332 23. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Bus Granting Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Matrix (MATRIX) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 336 337 337 338 339 340 341 24. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 1108 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 24.9 24.10 24.11 24.12 24.13 24.14 24.15 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection to External Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Read and Write Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambling/Unscrambling Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 349 350 350 351 352 353 356 364 364 369 373 379 381 384 25. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 25.1 25.2 25.3 25.4 25.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Peripheral DMA Controller (PDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 26. Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 26.1 26.2 26.3 26.4 26.5 26.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divider and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 410 411 411 412 415 27. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 27.1 27.2 27.3 27.4 27.5 27.6 27.7 27.8 27.9 27.10 27.11 27.12 27.13 27.14 27.15 27.16 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SysTick Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Free Running Processor Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Clock Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Crystal Clock Failure Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Switching Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protection Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Controller (PMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 418 419 419 420 420 420 421 421 421 421 422 423 425 429 430 28. Chip Identifier (CHIPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 28.1 28.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 1109 29. Parallel Input/Output Controller (PIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 29.1 29.2 29.3 29.4 29.5 29.6 29.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 467 468 469 469 481 482 30. Synchronous Serial Controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 30.9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 SSC Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Synchronous Serial Controller (SSC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 31. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 31.1 31.2 31.3 31.4 31.5 31.6 31.7 31.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 582 583 583 584 584 584 599 32. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 32.1 32.2 32.3 32.4 32.5 32.6 32.7 32.8 32.9 32.10 32.11 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-wire Interface (TWI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 615 616 616 617 617 618 618 631 634 642 33. Universal Asynchronous Receiver Transceiver (UART) . . . . . . . . . . . . . . . . . . . . . . . . . 657 33.1 33.2 33.3 33.4 33.5 33.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . . . . . . . . . . . . . . . . . . 657 657 658 658 658 664 34. Universal Synchronous Asynchronous Receiver Transmitter (USART) . . . . . . . . . 675 1110 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 34.1 34.2 34.3 34.4 34.5 34.6 34.7 34.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface . . . . . . . . . 675 675 676 677 678 679 679 715 35. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 35.1 35.2 35.3 35.4 35.5 35.6 35.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter (TC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 744 745 746 746 746 766 36. High Speed MultiMedia Card Interface (HSMCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 36.1 36.2 36.3 36.4 36.5 36.6 36.7 36.8 36.9 36.10 36.11 36.12 36.13 36.14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 High Speed MultiMedia Card Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 SD/SDIO Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 HSMCI Boot Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 HSMCI Transfer Done Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 Write Protection Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 Hig Speed MultiMedia Card Interface (HSMCI) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 37. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 37.1 37.2 37.3 37.4 37.5 37.6 37.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulation (PWM) Controller User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 840 841 841 842 842 872 38. USB Device Port (UDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 38.1 38.2 38.3 38.4 38.5 38.6 38.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Device Port (UDP) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 920 921 922 923 924 938 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 1111 39. Analog Comparator Controller (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 39.1 39.2 39.3 39.4 39.5 39.6 39.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 Analog Comparator Controller (ACC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961 40. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 40.1 40.2 40.3 40.4 40.5 40.6 40.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972 972 973 973 973 974 984 41. Digital-to-Analog Converter Controller (DACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 41.1 41.2 41.3 41.4 41.5 41.6 41.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 Digital-to-Analog Converter (DACC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 42. SAM3S4/2/1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 42.1 42.2 42.3 42.4 42.5 42.6 42.7 42.8 42.9 42.10 42.11 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillators Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLLA, PLLB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-Bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-Bit DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 1031 1037 1045 1052 1053 1055 1060 1062 1062 1063 43. SAM3S4/2/1 Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 43.1 43.2 43.3 43.4 43.5 43.6 100-lead LQFP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 100-ball TFBGA Mechanical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 64- and 48-lead LQFP Mechanical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 64- and 48-lead QFN Mechanical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 Packaging Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 44. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091 45. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093 46. SAM3S Series Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 1112 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 46.1 46.2 Errata Revision A Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 Errata Revision B Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106 SAM3S [DATASHEET] Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15 1113 ARM Connected Logo XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-6500F-ATARM-SAM-3S4-3S2-3S1-Datasheet_13-Feb-15. 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