SAM4CM Series
Atmel | SMART ARM-based Flash MCU
DATASHEET
Description
The Atmel ® | SMART SAM4CM series represents a family of system-on-chip
solutions for residential and polyphase metering applications. The devices offer
up to class 0.2 metrology accuracy over a dynamic range of 3000:1 within the
industrial temperature range and are compliant with ANSI C12.20-2002 and IEC
62053-22 standards.
A seamless extension of Atmel's SAM4, SAM4CP and SAM4C family of
microcontrollers and solutions for smart grid security and communications
applications, these metrology-enabled devices offer an unprecedented level of
integration and flexibility with dual 32-bit ARM® Cortex®-M4 RISC processors
running at a maximum speed of 120 MHz each(1), up to 2 Mbytes of embedded
Flash, 304 Kbytes of SRAM and on-chip cache.
The unique dual ARM Cortex-M4 architecture supports implementation of signal
processing, application and communications firmware in independent partitions,
and offers the ability to extend program and data memory via parallel external bus
interface (EBI) to ensure scalability of the design to meet future requirements.
The peripheral set includes metrology-specific precision voltage reference, up to
seven (7) simultaneously sampled Sigma-Delta ADC subsystems supporting
three (3) voltage and four (4) current measurement channels (polyphase versions
only), an extensive set of embedded cryptographic features, anti-tamper, Floating
Point Unit (FPU), four USARTs, two UARTs, two TWIs, four SPIs, three 16-bit
PWMs, two 3-channel general-purpose 16-bit timers, 6-channel 10-bit ADC,
battery-backed RTC with 1.9V).
Core voltage regulator supply, LCD voltage regulator supply, ADC and programmable
voltage reference supply.
Restrictions on range may apply. Refer to Section 46. “Electrical Characteristics”.
LCD voltage regulator output.
VDDLCD
2.5V to 3.6V
External LCD power supply input (LCD regulator not used).
VDDIO/VDDIN must be supplied when the LCD Controller is used.
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Power Supply Voltage Ranges(1) (Continued)
Table 5-1.
Power Supply
Comments
VDDPLL
1.08V to 1.32V
PLLA and PLLB supply.
VDDCORE
1.08V to 1.32V
Core logic, processors, memories and analog peripherals supply.
VDDIN_AFE
3.00V to 3.60V
EMAFE regulator input.
VDDA
2.70 to 2.90V
Notes:
5.1.1
Range
1.
2.
EMAFE regulator output (2.8V).
EMAFE analog functions power supply input.
In all power modes except Backup mode, all power supply inputs must be powered.
VDDBU must be powered from an external source to ensure proper start-up. The external source must meet the
timing and voltage level requirements described in Section 46.2.2 “Recommended Power Supply Conditions at
Powerup”.
Core Voltage Regulator
The core voltage regulator is managed by the Supply Controller.
It features two operating modes:
In Normal mode, the quiescent current of the voltage regulator is less than 500 µA when sourcing maximum
load current, i.e. 120 mA. Internal adaptive biasing adjusts the regulator quiescent current depending on the
required load current. In Wait Mode, quiescent current is only 5 µA.
In Backup mode, the voltage regulator consumes less than 100 nA while its output (VDDOUT) is driven
internally to GND.
The default output voltage is 1.20V and the start-up time to reach Normal mode is less than 500 µs.
For further information, refer to Table 46-16 “Core Voltage Regulator Characteristics”.
5.1.2
LCD Voltage Regulator
The SAM4CM embeds an adjustable LCD voltage regulator that is managed by the Supply Controller.
This internal regulator is designed to supply the Segment LCD outputs. The LCD regulator output voltage is
software selectable with 16 levels to adjust the display contrast.
If not used, its output (VDDLCD) can be bypassed (Hi-z mode) and an external power supply can be provided onto
the VDDLCD pin. In this case, VDDIO still needs to be supplied.
The LCD voltage regulator can be used in all power modes (Backup, Wait, Sleep and Active).
For further information, refer to Table 46-18 “LCD Voltage Regulator Characteristics”.
5.1.3
Automatic Power Switch
The SAM4CM features an automatic power switch between VDDBU and VDDIO. When VDDIO is present, the
backup zone power supply is powered by VDDIO and current consumption on VDDBU is about zero (around
100 nA, typ.). When VDDIO is removed, the backup area of the device is supplied from VDDBU. Switching
between VDDIO and VDDBU is transparent to the user.
5.1.4
EMAFE Voltage Regulator
The SAM4CM series embeds a 2.8V voltage regulator to supply its Energy Metering Analog Front-End (the VDDA
pin). This regulator is under software control. When the EMAFE voltage regulator is turned off, its output stage is
placed in High-impedance mode and thus can be forced by an external voltage source.
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5.1.5
Typical Powering Schematics
The SAM4CM series supports 1.6V to 3.6V single-supply operation. Restrictions on this range may apply
depending on enabled features. Refer to Section 46. “Electrical Characteristics”.
Note:
5.1.5.1
Figure 5-2, Figure 5-3 and Figure 5-4 show simplified schematics of the power section.
Single Supply Operation
Figure 5-2 below shows a typical power supply scheme with a single power source. VDDIO, VDDIN, VDDIN_AFE
and VDDBU are derived from the main power source (typically a 3.3V regulator output) while VDDCORE,
VDDPLL, VDDLCD, and VDDA are fed by the embedded regulator outputs.
Figure 5-2.
Single Supply Operation
SAM4CM
VDDBU
Backup Region
RC OSC 32 kHz
AUTOMATIC
POWER
SWITCH
VDDIO
XTAL OSC 32 kHz
RTC, RTT, RSTC,
Backup, Reg, ...
(1) VDDLCD
LCD Voltage
Regulator
Main
Supply
IN
OUT
3.3V
VDDIN
10-bit ADC,
Temp. Sensor,
Voltage Ref.
Voltage
Regulator
VDDOUT
Core Voltage
Regulator
LCD Analog
Buffers
+
Switch Array
VDDA Voltage
Regulator
Energy Metering
Analog-Front-End
VDDCORE
VDDPLL
VDDIN_AFE
VDDA
Note:
16
1.
Internal LCD Voltage Regulator can be disabled to save its operating current. VDDLCD must then be provided
externally.
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5.1.5.2
Single Supply Operation with Backup Battery
Figure 5-3 shows the single-supply operation schematic from Figure 5-2, improved by adding a backup capability.
VDDBU is supplied with a separate backup battery while VDDIO, VDDIN and VDDIN_AFE are still connected to
the main power source. Note that the TMP1 and RTCOUT0 pins cannot be used in Backup mode as they are
referred to VDDIO, which is not powered in this application case. To keep using these pins in Backup mode,
VDDIO must be maintained.
Figure 5-3.
Single Supply Operation with Backup Battery
SAM4CM
Backup
Battery
Backup Power Supply
(1.6V-3.6V)
VDDBU
Backup Region
RC OSC 32 kHz
+
AUTOMATIC
POWER
SWITCH
-
VDDIO
XTAL OSC 32 kHz
RTC, RTT, RSTC,
Backup, Reg, ...
VDDLCD
LCD Voltage
Regulator
Main
Supply
IN
OUT
VDDIN
10-bit ADC,
Temp. Sensor,
Voltage Ref.
Voltage
Regulator
EN
VDDOUT
Core Voltage
Regulator
LCD Analog
Buffers
+
Switch Array
VDDA Voltage
Regulator
Energy Metering
Analog-Front-End
VDDCORE
VDDPLL
VDDIN_AFE
VDDA
SHDN (1)
External Wake-up Signal
Note:
1.
FWUP
Example with the SHDN pin used to control the main regulator enable pin. SHDN defaults to VDDBU at startup
and when the device wakes up from a wake-up event (external pin, RTC alarm, etc.). When the device is
in Backup mode, SHDN defaults to 0.
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5.1.5.3
Single Power Supply using One Main Battery and LCD Controller in Backup Mode
Figure 5-4 below shows a typical power supply scheme that maintains VDDBU, VDDIO, and VDDLCD when
entering Backup mode. This is useful to enable the display and/or some supplementary wake-up sources in
Backup mode when the main voltage is not present.
In this power supply scheme, the SAM4CM can wake up both from an internal wake-up source, such as RTT, RTC
and VDDIO Supply Monitor, and from an external source, such as generic wake-up pins (WKUPx), anti-tamper
inputs (TMP0/1) or force wake-up (FWUP).
Note:
The VDDIO supply monitor only wakes up the device from Backup mode on a negative-going VDDIO supply (as system alert). As a result, the supply monitor cannot be used to wake up the device when the VDDIO supply is rising at
power cycle. Refer to Section 20. “Supply Controller (SUPC)” for more information on the VDDIO supply monitor.
Figure 5-4.
Single Power Supply using Battery and LCD Controller in Backup Mode
SAM4CM
VDDBU
Backup Region
RC OSC 32 kHz
AUTOMATIC
POWER
SWITCH
VDDIO
(1)
Main
Supply
XTAL OSC 32 kHz
RTC, RTT, RSTC,
Backup, Reg, ...
VDDLCD
LCD Voltage
Regulator
IN
OUT
Voltage
Regulator
VDDIN
Automatic
Power Switch
10-bit ADC,
Temp. Sensor,
Voltage Ref.
Core Voltage
Regulator
LCD Analog
Buffers
+
Switch Array
VDDA Voltage
Regulator
Energy Metering
Analog-Front-End
EN
State
VDDOUT
+
Battery
-
VDDCORE
VDDPLL
VDDIN_AFE
VDDA
RTCOUT0 (2)
WKUPx
State = 0 when main power is OFF
FWUP (3)
SHDN
Notes:
1.
2.
3.
18
Internal LCD Voltage Regulator can be disabled to save its operating current. VDDLCD must then be provided
externally.
RTCOUT0 signal is used to make a dynamic wake-up. WKUPx pin is pulled-up with a low duty cycle to avoid
battery discharge by permanent activation of the switch.
The State output of the automatic power switch indicates to the device that the main power is back and forces its
wake-up.
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5.1.5.4
Wake-up, Anti-tamper and RTCOUT0 Pins
In all power supply figures shown above, if generic wake-up pins other than WKUP0/TMP0 are used either as a
wake-up or a fast startup input, or as anti-tamper inputs, VDDIO must be present. This also applies to the
RTCOUT0 pin.
5.1.5.5
General-purpose IO (GPIO) State in Low-power Modes
In dual-power supply schemes shown in Figure 5-3 and Figure 5-4, where Backup or Wait mode must be used,
configuration of the GPIO lines is maintained in the same state as before entering Backup or Wait mode. Thus, to
avoid extra current consumption on the VDDIO power rail, the user must configure the GPIOs either as an input
with pull-up or pull-down enabled, or as an output with low or high level to comply with external components.
5.1.5.6
Default General-purpose IOs (GPIO) State after Reset
The reset state of the GPIO lines after reset is given in Table 11-5 “Multiplexing on PIO Controller A (PIOA)”,
Section 11-6 “Multiplexing on PIO Controller B (PIOB)” and Table 11-7 “Multiplexing on PIO Controller C (PIOC)”.
For further details about the GPIO and system lines, wake-up sources and wake-up time, and typical power
consumption in different low-power modes, refer to Table 5-2 “Low-power Mode Configuration Summary”.
5.2
Clock System Overview
Figure 5-5 illustrates the typical operation of the whole SAM4CM clock system in case of single crystal
(32.768 kHz) applications. Note:
The 32 kHz crystal oscillator can be the source clock of the 8 MHz digital PLL (PLLA).
The 8 MHz clock can feed the high frequency PLL (PLLB) input.
The output of the PLLB can be used as a main clock for both cores and the peripherals.
Full details of the clock system are provided in Section 29. “Clock Generator” and Section 30. “Power Management
Controller (PMC)”.
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Figure 5-5.
20
Processor Clock
int
XTALSEL
Sleep Mode
(Supply Controller)
SLCK
Master Clock Controller
(PMC_MCKR)
SYSTICK
Embedded
32 kHz
RC Oscillator
Prescaler
/1,/2,/3,/4,/8,
/16,/32,/64
PLLACK
0
PLLBCK
Slow Clock
FCLK
SLCK
XIN32
CSS
1
32.768 kHz
Crystal
Oscillator
Processor
SysTick Clock
Divider / 8
MAINCK
Processor
Free Running Clock
MCK
PRES
Peripherals
Clock Controller
(PMC_PCERx /
PMC_PCR)
32.768 kHz
Processor
Bus Master Clock
ON/OFF
periph_clk[n] Where n is an index
for the processor
system peripherals
MOSCSEL
ON/OFF
periph_clk[n+1]
XOUT32
Embedded
4/8/12 MHz
Fast
RC Oscillator
0
Main
Clock
MAINCK
ON/OFF
periph_clk[n+2]
Core 0 (CM4-P0 Clock System)
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
XIN
XOUT
1
ON/OFF
periph_clk[m]
SLCK
MAINCK
Where m is an index
for the coprocessor
system peripherals
Master Clock Controller
(PMC_MCKR)
PLLACK
PLLA
PLLADIV2
PLLA Clock
PLLACK
Prescaler
PLLBCK
8.192 MHz
PLLB and
Divider /2
0
SRCB
periph_clk[m+2]
PMC_SCER/SCDR
CPCK= ON/OFF
CPCSS
1
ON/OFF
divide by 1 to 16
MCK
Coprocessor
Clock
Controller
CPPRES
PLLB Clock
PLLBCK
Sleep Mode
PLLBDIV2
Up to120 MHz
PMC_SCER/SCDR
CPBMCK= ON/OFF
Divider / 8
CPHCLK
CPSYSTICK
CPFCLK
Status
Power
Control
Management
Controller
Coprocessor Clock
int
CPBMCK
Coprocessor
SysTick Clock
Coprocessor
Free Running Clock
Coprocessor
Bus Master Clock
Core 1 (CM4-P1 Clock System)
Global Clock System
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HCLK
Processor
Clock
Controller
Clock Generator
5.3
System State at Power-up
5.3.1
Device Configuration after the First Power-up
At the first power-up, the SAM4CM boots from the ROM. The device configuration is defined by the SAM-BA boot
program.
5.3.2
Device Configuration after a Power Cycle when Booting from Flash Memory
After a power cycle of all the power supply rails, the system peripherals, such as the Flash Controller, the Clock
Generator, the Power Management Controller and the Supply Controller, are in the following states:
5.3.3
Slow Clock (SLCK) source is the internal 32 kHz RC Oscillator (32 kHz crystal oscillator is disabled)
Main Clock (MAINCK) source is set to the 4 MHz internal RC Oscillator
3–20 MHz crystal oscillator and PLLs are disabled
Core Brownout Detector and Core Reset are enabled
Backup Power-on-reset is enabled
VDDIO Supply Monitor is disabled
Flash Wait State (FWS) bit in the EEFC Flash Mode Register is set to 0
Core 0 Cache Controller (CMCC0) is enabled (only used if the application link address for the Core 0 is
0x11000000)
Sub-system 1 is in the reset state and not clocked
Device Configuration after a Reset
After a reset or a wake-up from Backup mode, the following system peripherals default to the same state as after a
power cycle:
Main Clock (MAINCK) source is set to the 4 MHz internal RC oscillator
3–20 MHz crystal oscillator and PLLs are disabled
Flash Wait State (FWS) bit in the EEFC Flash Mode Register is set to 0
Core 0 Cache Controller (CMCC0) is enabled (only used if the application link address for the Core 0 is
0x11000000)
Sub-system 1 is in the reset state and not clocked
The states of the other peripherals are saved in the backup area managed by the Supply Controller as long as
VDDBU is maintained during device reset:
5.4
Slow Clock (SLCK) source selection is written in SUPC_ CR.XTALSEL.
Core Brownout Detector enable/disable is written in SUPC_MR.BODDIS.
Backup Power-on-reset enable/disable is written in the SUPC_MR.BUPPOREN.
VDDIO Supply Monitor mode is written in the SUPC_SMMR.
Active Mode
Active mode is the normal running mode, with the single core or the dual cores executing code. The system clock
can be the fast RC oscillator, the main crystal oscillator or the PLLs. The Power Management Controller (PMC)
can be used to adapt the frequency and to disable the peripheral clocks when unused.
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5.5
Low-power Modes
The various low-power modes (Backup, Wait and Sleep modes) of the SAM4CM are described below. Note that
the Segmented LCD Controller can be used in all low-power modes.
Note:
5.5.1
The Wait For Event instruction (WFE) of the Cortex-M4 core can be used to enter any of the low-power modes,
however this may add complexity to the design of application state machines. This is due to the fact that the WFE
instruction is associated with an event flag of the Cortex core that cannot be managed by the software application. The
event flag can be set by interrupts, a debug event or an event signal from another processor. When an event occurs
just before WFE execution, the processor takes it into account and does not enter Low-power mode. Atmel has made
provision to avoid using the WFE instruction. The workarounds to ease application design, including the use of the
WFE instruction, are given in the following description of the low-power mode sequences.
Backup Mode
The purpose of Backup mode is to achieve the lowest possible power consumption in a system that executes
periodic wake-ups to perform tasks but which does not require fast start-up time. The total current consumption is
0.5 µA typical on VDDBU.
The Supply Controller, power-on reset, RTT, RTC, backup registers and the 32 kHz oscillator (RC or crystal
oscillator selected by software in the Supply Controller) are running. The regulator and the core supplies are off.
The power-on-reset on VDDBU can be deactivated by software.
Wake-up from Backup mode can be done through the Force Wake-up (FWUP) pin, WKUP0, WKUP1 to WKUP12
pins, the VDDIO Supply Monitor (SM) if VDDIO is supplied, or through an RTT or RTC wake-up event. Wake-up
pins multiplexed with anti-tampering functions are additional possible sources of a wake-up if an anti-tampering
event is detected. The TMP0 pad is supplied by the backup power supply (VDDBU). TMP1 is supplied by VDDIO.
The LCD Controller can be used in Backup mode. The purpose is to maintain the displayed message on the LCD
display after entering Backup mode. The current consumption on VDDIN to maintain the LCD is 10 µA typical.
Refer to Section 46. “Electrical Characteristics”.
In case the VDDIO power supply is maintained with VDDBU when entering Backup mode, it is up to the application
to configure all PIO lines in a stable and known state to avoid extra power consumption or possible current path
with the input/output lines of the external on-board devices.
5.5.1.1
Entering and Exiting Backup Mode
To enter Backup mode, follow the steps in the sequence below:
1.
Depending on the application, set the PIO lines in the correct mode and configuration (input pull-up or pulldown, output low or high levels).
2.
Disable the Main Crystal Oscillator (enabled by SAM-BA boot if the device is booting from ROM).
3.
Configure PA30/PA31 (XIN/XOUT) into PIO mode depending on their use.
4.
Disable the JTAG lines using the SFR1 register in Matrix 0 (by default, internal pull-up or pull-down is
disabled on JTAG lines).
5.
Enable the RTT in 1 Hz mode.
6.
Disable Normal mode of the RTT (RTT will run in 1 Hz mode).
7.
To reduce power consumption, disable the POR backup if not needed.
Note:
8.
22
The POR BU provides critical functionality to ensure the MCU backup logic will be properly reset in the event VDDBU
drops below the minimum specification. If this protection is not necessary, the backup POR may be disabled to reduce
power consumption.
Disable the Core brownout detector.
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9.
Select one of the following methods to complete the sequence:
a. To enter Backup mode using the VROFF bit:
Write a 1 to the VROFF bit of SUPC_CR.
b. To enter Backup mode using the WFE instruction:
Write a 1 to the SLEEPDEEP bit of the Cortex-M4 processor.
Execute the WFE instruction of the processor.
After this step, the core voltage regulator is shut down and the SHDN pin goes low. The digital internal logic (cores,
peripherals and memories) is not powered. The LCD controller can be enabled if needed before entering Backup
mode.
Whether the VROFF bit or the WFE instruction was used to enter Backup mode, the system exits Backup mode if
one of the following enabled wake-up events occurs:
WKUP[0–13] pins
Force Wake-up pin
VDDIO Supply Monitor (if VDDIO is present, and VDDIO supply falling)
Anti-tamper event detection
RTC alarm
RTT alarm
After exiting Backup mode, the device is in the reset state. Only the configuration of the backup area peripherals
remains unchanged.
Note that the device does not automatically enter Backup mode if VDDIN is disconnected, or if it falls below
minimum voltage. The Shutdown pin (SHDN) remains high in this case.
For current consumption in Backup mode, refer to Section 46. “Electrical Characteristics”.
5.5.2
Wait Mode
The purpose of Wait mode is to achieve very low power consumption while maintaining the whole device in a
powered state for a start-up time of a few µs. For current consumption in Wait mode, refer to Section 46. “Electrical
Characteristics”.
In Wait mode, the bus and peripheral clocks of Sub-system 0 and Sub-system 1 (MCK/CPBMCK), the clocks of
Core 0 and Core 1 (HCLK/CPHCLK) are stopped when Wait mode is entered (refer to Section 5.5.2.1 “Entering
and Exiting Wait Mode”). However, the power supply of core, peripherals and memories are maintained using
Standby mode of the core voltage regulator.
The SAM4CM is able to handle external and internal events in order to perform a wake-up. This is done by
configuring the external WKUPx lines as fast startup wake-up pins (refer to Section 5.7 “Fast Start-up”). RTC
alarm, RTT alarm and anti-tamper events can also wake up the device.
Wait mode can be used together with Flash in Read-Idle mode, Standby mode or Deep Power-down mode to
further reduce the current consumption. Flash in Read-Idle mode provides a faster start-up; Standby mode offers
lower power consumption.
5.5.2.1
Entering and Exiting Wait Mode
1.
Stop Sub-system 1.
2.
Select the 4/8/12 MHz fast RC Oscillator as Main Clock(1).
3.
Disable the PLL if enabled.
4.
Clear the internal wake-up sources.
5.
Depending on the application, set the PIO lines in the correct mode and configuration (input pull-up or pulldown, output low or high level).
6.
Disable the Main Crystal Oscillator (enabled by SAM-BA boot if device is booting from ROM).
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7.
Configure PA30/PA31 (XIN/XOUT) into PIO mode according to their use.
8.
Disable the JTAG lines using the SFR1 register in Matrix 0 (by default, internal pull-up or pull-down is
disabled on JTAG lines).
9.
Set the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR)(2).
10. Set the Flash Wait State (FWS) bit in the EEFC Flash Mode Register to 0.
11. Select one of the following methods to complete the sequence:
a. To enter Wait mode using the WAITMODE bit:
Set the WAITMODE bit to 1 in the PMC Main Oscillator Register (CKGR_MOR).
Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR).
b. To enter Wait mode using the WFE instruction:
Select the 4/8/12 MHz fast RC Oscillator as Main Clock.
Set the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR).
Set Flash Wait State at 0.
Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR).
Write a 0 to the SLEEPDEEP bit of the Cortex-M4 processor.
Execute the Wait-For-Event (WFE) instruction of the processor.
Notes:
1. Any frequency can be chosen. The 12 MHz frequency will provide a faster start-up compared to the 4 MHz, but
with the increased current consumption (in the µA range). Refer to Section 46. “Electrical Characteristics”.
2. Depending on the Flash Low-power Mode (FLPM) value, the Flash enters three different modes:
If FLPM = 0, the Flash enters Stand-by mode (Low consumption)
If FLPM = 1, the Flash enters Deep Power-down mode (Extra low consumption)
If FLPM = 2, the Flash enters Idle mode. Memory is ready for Read access
Whether the WAITMODE bit or the WFE instruction was used to enter Wait mode, the system exits Wait mode if
one of the following enabled wake-up events occurs:
WKUP[0–13] pins in Fast wake-up mode
Anti-tamper event detection
RTC alarm
RTT alarm
After exiting Wait mode, the PIO controller has the same configuration state as before entering Wait mode. The
SAM4CM is clocked back to the RC oscillator frequency which was used before entering Wait mode. The core will
start fetching from Flash at this frequency. Depending on the configuration of the Flash Low-power Mode (FLPM)
bits used to enter Wait mode, the application has to reconfigure it back to Read-idle mode.
5.5.3
Sleep Mode
The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode,
only the core clocks of CM4P0 and/or CM4P1 are stopped. Some of the peripheral clocks can be enabled
depending on the application needs. The current consumption in this mode is application dependent. This mode is
entered using Wait for Interrupt (WFI) or Wait for Event (WFE) instructions of the Cortex-M4.
The processor can be awakened from an interrupt if the WFI instruction of the Cortex-M4 is used to enter Sleep
mode, or from a wake-up event if the WFE instruction is used. The WFI instruction can also be used to enter Sleep
mode with the SLEEPONEXIT bit set to 1 in the System Control Register (SCB_SCR) of the Cortex-M. If the
SLEEPONEXIT bit of the SCB_SCR is set to 1, when the processor completes the execution of an exception
handler, it returns to Thread mode and immediately enters Sleep mode. This mechanism can be used in
applications that require the processor to run only when an exception occurs. Setting the SLEEPONEXIT bit to 1
enables an interrupt-driven application in order to avoid returning to an empty main application.
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5.5.4
Low-power Mode Summary Table
The modes detailed above are the main low-power modes. Table 5-2 below provides a configuration summary of
the low-power modes. For more information on power consumption, refer to Section 46. “Electrical
Characteristics”.
Table 5-2.
Low-power Mode Configuration Summary
SUPC,
32 kHz
Oscillator
RTC, RTT
Backup
Registers
POR
(Backup
Region)
Mode
Core
Regulator
/
Core 0/1
Core
PIO State
PIO State
LCD
Regulator
Memory
at
in Lowpower Mode
at
Peripherals
Potential
Wake-up Sources
Wake-up
Wake-up
Typical
Wake-up
Time(1)
- FWUP pin
Backup
Mode
ON
OFF/OFF
OFF / OFF
(Not powered)
- WKUP0-13 pins(5)
- Supply Monitor
Reset
Previous state
saved
Reset state(7)
< 1.5 ms
Reset
Previous state
saved
Unchanged
(LCD Pins)/
Inputs with pull
ups
< 1.5 ms
Clocked back
Previous state
saved
Unchanged
< 10 µs
Clocked back
Previous state
saved
Unchanged
< 75 µs
Clocked back
Previous state
saved
Unchanged
(3)
(5)
- Anti-tamper inputs
- RTC or RTT alarm
- FWUP pin
Backup
Mode with
LCD
ON
OFF/ON
OFF / OFF
(Not powered)
- WKUP0-13 pins(5)
- Supply Monitor
(5)
- Anti-tamper inputs
- RTC or RTT alarm
Wait Mode
ON
Flash in
Standby
Mode(6)
ON/(4)
Core 0 and 1,
memories and
peripherals:
Any event from:
- Fast start-up through
WKUP0-13 pins
Powered, but Not - Anti-tamper inputs(5)
clocked
- RTC or RTT alarm
Wait Mode
Flash in
Deep
Powerdown
Mode(6)
ON
(4)
ON/
Core 0 and 1,
memories and
peripherals:
Any event from:
- Fast start-up through
WKUP0-13 pins
(5)
Powered, but Not - Anti-tamper inputs
clocked
- RTC or RTT alarm
Entry mode = WFI
Any enabled Interrupts;
Sleep Mode
ON
(4)
ON/
Core 0 and/or
Core 1:
Powered
(Not clocked)(2)
Entry mode = WFE
Any enabled event:
- Fast start-up through
WKUP0-13 pins
- Anti-tamper inputs(5)
- RTC or RTT alarm
Notes:
1.
2.
3.
4.
When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the
device works from the 4, 8 or 12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed
in the system. The wake-up time is defined as the time taken for wake-up until the first instruction is fetched.
In this mode, the core is supplied and not clocked but some peripherals can be clocked.
Depends on MCK frequency.
LCD voltage regulator can be OFF if VDDLCD is supplied externally thus saving current consumption of the LCD
voltage regulator.
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25
5.
6.
7.
5.6
Refer to Table 3-1 “Signal Description List”. Some anti-tamper pin pads are VDDIO-powered.
Fast RC Oscillator set to 4 MHz frequency.
Refer to PIO Controller Multiplexing tables in Section 11.4 “Peripheral Signal Multiplexing on I/O Lines”.
Wake-up Sources
Wake-up events allow the device to exit Backup mode. When a wake-up event is detected, the Supply Controller
performs a sequence which automatically reenables the core power supply and all digital logic.
5.7
Fast Start-up
The SAM4CM allows the processor to restart in a few microseconds while the processor is in Wait mode or in
Sleep mode. A fast start-up occurs upon detection of one of the wake-up inputs.
The fast restart circuitry is fully asynchronous and provides a fast start-up signal to the Power Management
Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 4/8/12
MHz Fast RC oscillator, switches the master clock on this 4 MHz clock and re-enables the processor clock.
6.
Input/Output Lines
The SAM4CM has two types of input/output (I/O) lines—general-purpose I/Os (GPIO) and system I/Os. GPIOs
have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used
whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase
or analog inputs.
6.1
General-Purpose I/O Lines
General-purpose I/O (GPIO) lines are managed by PIO Controllers. All I/Os have several input or output modes
such as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input
change interrupt. Programming of these modes is performed independently for each I/O line through the PIO
controller user interface. Refer to Section 32. “Parallel Input/Output Controller (PIO)” for details.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail when used as GPIOs.
When used as extra functions such as LCD or Analog modes, GPIO lines have either VDDLCD or VDDIN voltage
range.
Each I/O line embeds an ODT (On-die Termination), shown in Figure 6-1 below. ODT consists of an internal series
resistor termination scheme for impedance matching between the driver output (SAM4CM) and the PCB trace
impedance preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby
reducing EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between
devices or between boards. Finally, ODT helps diminish signal integrity issues.
Figure 6-1.
On-die Termination
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.
Rodt
Receiver
SAM4 Driver with
Zout ~ 10 Ohms
26
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
PCB Trace
Z0 ~ 50 Ohms
6.2
System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG and other features.
Table 6-1 describes the system I/O lines shared with PIO lines. These pins are software-configurable as generalpurpose I/O or system pins. At start-up, the default function of these pins is always used.
Table 6-1.
System I/O Configuration Pin List
SYSTEM_IO
Bit Number
Default Function
after Reset
Other Function
Constraints
for Normal Start
0
TDI
PB0
–
1
TDO/TRACESWO
PB1
–
In Matrix User Interface Registers
2
TMS/SWDIO
PB2
–
3
TCK/SWCLK
PB3
–
(Refer to Section 26.9.4 “System I/O
Configuration Register”)
4
ERASE
PC9
Low level at Start-up(1)
–
PA31
XIN
–
–
PA30
XOUT
–
Configuration
(2)
Notes:
1. If PC9 is used as PIO input in user applications, a low level must be ensured at start-up to prevent Flash erase before the
user application sets PC9 into PIO mode.
2. Refer to Section 29.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator”.
6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) and Serial Wire Debug Port (SW-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/TRACESWO, TDI and commonly provided on a standard
20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to
Table 11-6 “Multiplexing on PIO Controller B (PIOB)”.
At start-up, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Refer to
Section 13. “Debug and Test Features”.
SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins when the debug
port is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general
IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the
pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it
must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and
enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be
used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, refer to Section 13.
“Debug and Test Features”. The SW-DP/SWJ-DP pins are used for debug access to both cores.
6.3
TST Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the
SAM4CM series. For details on entering Fast Programming mode, refer to Section 23. “Fast Flash Programming
Interface (FFPI)”. For more information on the manufacturing and test modes, refer to Section 13. “Debug and Test
Features”.
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27
6.4
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset
signal to the external components, or asserted low externally to reset the microcontroller. It resets the core and the
peripherals, with the exception of the Backup region (RTC, RTT and Supply Controller). There is no constraint on
the length of the reset pulse, and the Reset Controller can guarantee a minimum pulse length. The NRST pin
integrates a permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an
input.
6.5
TMPx Pins: Anti-tamper Pins
Anti-tamper pins detect intrusion—for example, into a smart meter case. Upon detection through a tamper switch,
automatic, asynchronous and immediate clear of registers in the backup area, and time stamping in the RTC are
performed. Anti-tamper pins can be used in all modes. Date and number of tampering events are stored
automatically. Anti-tampering events can be programmed so that half of the General-purpose Backup Registers
(GPBR) are erased automatically. The TMP1 signal is referred to VDDIO, meaning that it is effective only if VDDIO
is supplied, whereas TMP0 is in the VDDBU domain.
6.6
RTCOUT0 Pin
The RTCOUT0 pin shared in the PIO (supplied by VDDIO) can be used to generate waveforms from the RTC in
order to take advantage of the RTC inherent prescalers while the RTC is the only powered circuitry (Low-power
mode, Backup mode) or in any active mode. Entering Backup or low-power operating modes does not affect the
waveform generation outputs (VDDIO still must be supplied). Anti-tampering pin detection can be synchronized
with this signal.
Note:
6.7
To use the RTCOUT0 signal during application development using JTAG-ICE interface, the programmer must use
Serial Wire Debug (SWD) mode. In this case, the TDO pin is not used as a JTAG signal by the ICE interface.
Shutdown (SHDN) Pin
The SHDN pin designates the Backup mode of operation. When the device is in Backup mode, SHDN = 0. In any
other mode, SHDN = 1 (VDDBU). This pin is designed to control the enable pin of the main external voltage
regulator. When the device enters Backup mode, the SHDN pin disables the external voltage regulator and, upon
the wake-up event, it re-enables the voltage regulator.
The SHDN pin is asserted low when the VROFF bit in the Supply Controller Control Register (SUPC_CR) is set
to 1.
6.8
Force Wake-up (FWUP) Pin
The FWUP pin can be used as a wake-up source in all low-power modes as it is supplied by VDDBU.
6.9
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read
as logic level 1). The ERASE pin and the ROM code ensure an in-situ reprogrammability of the Flash content
without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to
reprogram the Flash content. The ERASE pin integrates a pull-down resistor of about 100 kΩ into GND, so that it
can be left unconnected for normal operations.
This pin is debounced by SLCK to improve the glitch tolerance. When the ERASE pin is tied high during less than
100 ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase
operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At start-up, the ERASE pin is not
configured as a PIO pin. If the ERASE pin is used as a standard I/O, the start-up level of this pin must be low to
28
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
prevent unwanted erasing. Refer to Section 11.3 “APB/AHB Bridge”. If the ERASE pin is used as a standard I/O
output, asserting the pin to low does not erase the Flash.
To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in
the AC Flash Characteristics in Section “Electrical Characteristics”.
The erase operation is not performed when the system is in Wait mode with the Flash in Deep Power-down mode.
To make sure that the erase operation is performed after power-up, the system must not reconfigure the ERASE
pin as GPIO or enter Wait mode with Flash in Deep Power-down mode before the ERASE pin assertion time has
elapsed.
With the following sequence, in any case, the erase operation is performed:
1.
Assert the ERASE pin (High).
2.
Assert the NRST pin (Low).
3.
Power cycle the device.
4.
Maintain the ERASE pin high for at least the minimum assertion time.
SAM4CM Series [DATASHEET]
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29
7.
Product Mapping and Peripheral Access
Figure 7-1 shows the default memory mapping of the ARM Cortex-M core.
Figure 7-1.
Cortex-M Memory Mapping
0xFFFFFFFF
System level
0xE0000000
Private peripherals including
build-in interrupt controller
(NVIC), MPU control
registers, and debug
components
0xDFFFFFFF
External device
Mainly used as external
peripherals
External RAM
Mainly used as external
memory
0xA0000000
0x9FFFFFFF
0x60000000
0x5FFFFFFF
0x40000000
0x3FFFFFFF
0x20000000
0x1FFFFFFF
0x00000000
30
Peripherals
Mainly used as peripherals
SRAM
Mainly used as static RAM
CODE
Mainly used for program
code. Also provides exception
vector table after power up
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 7-2.
SAM4CM16/8/4 Memory Mapping of CODE and SRAM Area
0x00000000
Address memory space
Code
0x20000000
0x20000000
Internal SRAM
Internal SRAM
0x00000000
SRAM0
Code
Boot Memory (1)
(Code - Non-cached)
0x40000000
0x01000000
0x20080000
Internal Flash
(Code - Non-cached)
Peripherals
SRAM1 (2)
0x02000000
0x20100000
SRAM2
Internal ROM
0x60000000
0x03000000
0x20180000
CPKCC ROM
External SRAM
0x04000000
0x20190000
Reserved
EBI Chip Select 0
(Code - Non-cached)
EBI Chip Select 1
(Code - Non-cached)
0xA0000000
0x05000000
0x20191000
CPKCC SRAM
EBI Chip Select 2
(Code - Non-cached)
External devices
0x06000000
0x20192000
Reserved
0xE0000000
EBI Chip Select 3
(Code - Non-cached)
0x07000000
0x20200000
Cortex-M
Private Peripheral Bus
Undefined (Abort)
0x3FFFFFFF
Undefined (Abort)
0x10000000
Undefined (Abort)
0xE0100000
0x11000000
Reserved
0x12000000
offset
block
peripheral
0xFFFFFFFF
Internal Flash
(Code - Cached)
Undefined (Abort)
ID
0x13000000
EBI Chip Select 0
(Code - Cached)
0x14000000
EBI Chip Select 1
(Code - Cached)
0x15000000
EBI Chip Select 2
(Code - Cached)
0x16000000
EBI Chip Select 3
(Code - Cached)
0x17000000
Undefined (Abort)
0x1FFFFFFF
Notes:
1.
2.
Boot Memory for Core 0.
Boot Memory for Core 1 at 0x00000000.
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31
Figure 7-3.
SAM4CM32 Memory Mapping of CODE and SRAM Area
0x00000000
Address memory space
Code
Code
0x20000000
0x00000000
0x20000000
Boot Memory (1)
(Code - Non-cached)
Internal SRAM
Internal SRAM
0x01000000
SRAM0
Internal Flash - Plane 0
(Code - Non-cached)
0x40000000
0x01100000
0x20080000
SRAM1 (2)
Internal Flash - Plane 1
(Code - Non-cached)
Peripherals
0x02000000
0x20100000
SRAM2
Internal ROM
0x60000000
0x03000000
0x20180000
CPKCC ROM
External SRAM
0x04000000
0x20190000
Reserved
EBI Chip Select 0
(Code - Non-cached)
EBI Chip Select 1
(Code - Non-cached)
0xA0000000
0x05000000
0x20191000
CPKCC SRAM
EBI Chip Select 2
(Code - Non-cached)
External devices
0x06000000
0x20192000
Reserved
0xE0000000
EBI Chip Select 3
(Code - Non-cached)
0x07000000
0x20200000
Cortex-M
Private Peripheral Bus
Undefined (Abort)
0x3FFFFFFF
Undefined (Abort)
0x10000000
Undefined (Abort)
0xE0100000
0x11000000
Reserved
0x12000000
offset
block
peripheral
0xFFFFFFFF
ID
Internal Flash
(Code - Cached)
Undefined (Abort)
0x13000000
EBI Chip Select 0
(Code - Cached)
0x14000000
EBI Chip Select 1
(Code - Cached)
0x15000000
EBI Chip Select 2
(Code - Cached)
0x16000000
EBI Chip Select 3
(Code - Cached)
0x17000000
Undefined (Abort)
0x1FFFFFFF
Notes:
32
1.
2.
Boot Memory for Core 0.
Boot Memory for Core 1 at 0x00000000.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
In Figure 7-2 and Figure 7-3 above, ‘Code’ means ‘Program Code over I-Code bus’ and ‘Program Data over DCode bus’.
SRAM1 is at the address 0x20080000 (through S-bus) and the address 0x00000000 (through I/D Bus) for Core1.
Instruction fetch from Core 1 to the SRAM address range is possible but leads to reduced performance due to the
fact that instructions and read/write data go through the System Bus (S-Bus). Maximum performance for Core 1
(Metrology Core) is obtained by mapping the instruction code to the address 0x00000000 (SRAM1 through I/DCode) and read/write data from the address 0x20100000 (SRAM2 through S-Bus).
For Core 0 (Application Core), maximum performance is achieved when the instruction code is mapped to the
Flash address and read/write data is mapped into SRAM0.
Each core can access the following memories and peripherals:
Core 0 (Application Core):
̶
All internal memories
̶
External memories or memory devices mapped on SMC 0 or SMC 1
̶
All internal peripherals
Core 1 (Metrology/Coprocessor Core):
̶
All internal memories
̶
External memories or memory devices mapped on SMC 0 or SMC 1
̶
All internal peripherals
Note that Peripheral DMA 0 on Matrix 0 cannot access SRAM1 or SRAM2, Peripheral DMA 1 on Matrix 1 cannot
access SRAM0, SRAM2 or SRAM0 can be the Data RAM for Inter-core Communication.
If Core 1 is not to be used (clock stopped and reset active), all the peripherals, SRAM1 and SRAM2 of the Subsystem 1 can be used by the Application Core (Core 0) as long as the peripheral bus clock and reset are
configured.
Refer to Section 26. “Bus Matrix (MATRIX)” for more details about memory mapping and memory access versus
Matrix masters/slaves.
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33
Figure 7-4.
SAM4CM16/8/4 Memory Mapping of the Peripherals Area
Address memory space
0x00000000
Peripherals
0x40000000
0x400E0000
System Controller
SMC0
AES
Code
36
0x40004000
10
0x400E0200
MATRIX0
Reserved
0x20000000
0x400E0400
0x40008000
PMC
SPI0
Internal SRAM
21
0x4000C000
5
0x400E0600
UART0
Reserved
0x40000000
TC0
Peripherals
TC0
TC0
0x40014000
0xA0000000
24
0x400E0A00
25
0x400E0C00
Reserved
EFC
0x400E0E00
PIOA
TC4
27
+0x80
TC1
11
0x400E1000
PIOB
TC5
28
0x40018000
12
0x400E1200
Reserved
TWI0
Cortex-M
Private
Peripheral Bus
0x4001C000
19
0x400E1400
20
+0x10
SYSC
TWI1
0xE0100000
0x40020000
Reserved
SYSC
USART0
14
0x40028000
reserved
0x400E4000
0x40038000
ADC
29
SLCDC
32
0x40040000
CPKCC
ICM
38
0x48008000
34
0x40048000
PWM
TRNG
41
0x4800C000
33
0x4004C000
PIOC
IPC0
37
0x48010000
31
0x40050000
MATRIX1
Reserved
0x48014000
0x4007C000
IPC1
CMCC0
39
0x48018000
0x40080000
CMCC1
Reserved
0x4801C000
0x400E0000
SMC1
System Controller
43
0x48020000
0x400E4000
Reserved
0x5FFFFFFF
35
0x40044000
UART1
Reserved
0x48000000
Reserved
0x48004000
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
GPBR
0x400E1600
Reserved
0x4003C000
2
SYSC
17
RTC
+0x90
USART3
0x40034000
4
SYSC
16
WDT
+0x60
USART2
0x40030000
3
SYSC
15
0x4002C000
RTT
+0x50
USART1
0x48004000
SUPC
+0x30
0x40024000
0xFFFFFFFF
RSTC
1
SYSC
Reserved
34
6
Reserved
TC3
26
TC1
0xE0000000
0x400E0800
TC2
TC1
+0x40
External devices
23
TC1
+0x80
External SRAM
CHIPID
TC0
+0x40
0x60000000
8
0x400E0740
0x40010000
Figure 7-5.
SAM4CM32 Memory Mapping of the Peripherals Area
Address memory space
0x00000000
Peripherals
0x40000000
0x400E0000
System Controller
SMC0
AES
Code
36
0x40004000
10
0x400E0200
MATRIX0
Reserved
0x20000000
0x400E0400
0x40008000
PMC
SPI0
Internal SRAM
21
0x4000C000
5
0x400E0600
UART0
Reserved
0x40000000
TC0
Peripherals
TC0
TC0
0x40014000
0xA0000000
24
0x400E0A00
25
0x400E0C00
Reserved
EFC0
7
0x400E0E00
PIOA
TC4
27
+0x80
TC1
6
EFC1
TC3
26
TC1
0xE0000000
0x400E0800
TC2
TC1
+0x40
External devices
23
TC1
+0x80
External SRAM
CHIPID
TC0
+0x40
0x60000000
8
0x400E0740
0x40010000
11
0x400E1000
PIOB
TC5
28
0x40018000
12
0x400E1200
Reserved
TWI0
Cortex-M
Private
Peripheral Bus
0x4001C000
19
0x400E1400
20
+0x10
SYSC
TWI1
0xE0100000
0x40020000
Reserved
Reserved
SUPC
+0x30
0x40024000
SYSC
USART0
0xFFFFFFFF
RSTC
1
SYSC
14
0x40028000
15
2
SYSC
17
RTC
+0x90
USART3
0x40034000
4
SYSC
16
WDT
+0x60
USART2
0x40030000
3
SYSC
USART1
0x4002C000
RTT
+0x50
GPBR
0x400E1600
reserved
Reserved
0x400E4000
0x40038000
ADC
29
0x4003C000
SLCDC
32
0x40040000
CPKCC
0x48004000
ICM
38
0x48008000
34
0x40048000
PWM
TRNG
41
0x4800C000
33
0x4004C000
PIOC
IPC0
37
0x48010000
31
0x40050000
MATRIX1
Reserved
0x48014000
0x4007C000
IPC1
CMCC0
39
0x48018000
0x40080000
CMCC1
Reserved
0x4801C000
0x400E0000
SMC1
System Controller
43
0x48020000
0x400E4000
Reserved
0x5FFFFFFF
35
0x40044000
UART1
Reserved
0x48000000
Reserved
0x48004000
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Figure 7-6.
SAM4CM32/16/8/4 Memory Mapping of External SRAM and External Devices Area
0x00000000
Address memory space
0x60000000
Code
0x62000000
External devices
Internal SRAM
EBI Chip Select 0
(External Device)
0x64000000
Peripherals
0xA2000000
0x60000000
EBI Chip Select 2
(External Device)
External SRAM
0xA3000000
EBI Chip Select 3
(External Device)
0xA0000000
0xA4000000
Undefined (Abort)
External devices
0xDFFFFFFF
0xE0000000
Cortex-M
Private Peripheral Bus
offset
0xE0100000
block
peripheral
ID
Reserved
0xFFFFFFFF
36
EBI Chip Select 2
0x63000000
EBI Chip Select 3
0x40000000
0xA1000000
EBI Chip Select 1
(External Device)
EBI Chip Select 0
0x61000000
EBI Chip Select 1
0x20000000
0xA0000000
External SRAM
SAM4CM Series [DATASHEET]
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Undefined (Abort)
0x9FFFFFFF
8.
Memories
The memory map shown in Figure 7-2 is common to both Cortex-M4 processors with the exception of the “Boot
Memory” block. For more information on Boot Memory, refer to Section 8.1.5 “Boot Strategy”.
Each processor uses its own ARM Private Peripheral Bus (PPB) for the NVIC and other system functions.
8.1
Embedded Memories
8.1.1
Internal SRAM
The SAM4CM embeds a total of up to 304 Kbytes high-speed SRAM with zero wait state access time.
SRAM0 on Matrix0 is up to 256 Kbytes. It is dedicated to the application processor (CM4P0) or other peripherals
on Matrix0 but can be identified and used by masters on Matrix1.
SRAM1 on Matrix1 is up to 32 Kbytes. It is mainly dedicated to be the code region of the CM4P1 processor but can
be identified and used by Matrix0.
SRAM2 on Matrix1 is up to 16 Kbytes. It is mainly dedicated to be the data region of the CM4P1 processor or other
peripherals on Matrix1 but can be identified and used by masters on Matrix0.
Refer to Section 26. “Bus Matrix (MATRIX)” for more details.
If the CM4P1 processor is in the reset state and not used, the application core may use it.
The SRAM is located in the bit band region. The bit band alias region is from 0x2200 0000 to 0x23FF_FFFF.
8.1.2
System ROM
The SAM4CM embeds an Internal ROM for the master processor (CM4P0), which contains the SAM Boot
Assistant (SAM-BA®), In Application Programming routines (IAP), and Fast Flash Programming Interface (FFPI).
The ROM is always mapped at the address 0x02000000.
8.1.3
CPKCC ROM
The ROM contains a cryptographic library using the CPKCC cryptographic accelerator peripheral (CPKCC) to
provide support for Rivest Shamir Adleman (RSA), Elliptic Curve Cryptography (ECC), Digital Signature Algorithm
(DSA) and Elliptic Curve Digital Signature Algorithm (ECDSA).
8.1.4
8.1.4.1
Embedded Flash
Flash Overview
The embedded Flash is the boot memory for the Cortex-M4 Core 0 (CM4P0). The Flash memory can be accessed
through the Cache Memory Controller (CMCC0) of the CM4P0 and can also be identified by the Cortex-M4F Core
1 (CM4P1) through its Cache Memory Controller (CMCC1).
The SAM4CM32 features a dual-plane Flash to program or erase a memory plane while reading from the other
plane. The dual-plane capability also provides the dual boot scheme. The benefit of the dual plane and the dual
boot is that the firmware can be upgraded while the main application is running and that it is possible to switch to
the new firmware in the other plane. Figure 8-1 below shows the operating principle of firmware upgrade by using
the dual bank/dual boot.
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Figure 8-1.
Dual Bank and Dual Boot Firmware Upgrade
RESET VECTOR
Bank 1
v1.0
Bank 2
v1.1
RESET VECTOR
Wired / Wireless Stream
Normal operation from Bank 1
while simultaneously remotely
programming Bank 2
Bank 1
v1.0
Bank 1
v1.0
Bank 2
corrupt
Bank 2
v1.1
RESET VECTOR
Power or comms failure cause
Bank 2 program fail while Bank
1 continues to operate and
requests retransmission
Reprogramming
successful, device now
executes from Bank 2,Bank
1 available for next update
The memory plane is organized in sectors. Each sector has a size of 64 Kbytes. The first sector of 64 Kbytes is
divided into 3 smaller sectors.
The three smaller sectors are organized in 2 sectors of 8 Kbytes and 1 sector of 48 Kbytes. Refer to Figure 8-2
below.
The Flash memory has built-in error code correction providing 2-bit error detection and 1-bit correction per
128 bits.
Figure 8-2.
Memory Plane Organization
Sector size
38
Sector name
8 Kbytes
Small Sector 0
8 Kbytes
Small Sector 1
48 Kbytes
Larger Sector
64 Kbytes
Sector 1
64 Kbytes
Sector n
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Sector 0
Each sector is organized in pages of 512 bytes.
For sector 0:
The small sector 0 has 16 pages of 512 bytes, 8 Kbytes in total
The small sector 1 has 16 pages of 512 bytes, 8 Kbytes in total
The larger sector has 96 pages of 512 bytes, 48 Kbytes in total
From sector 1 to n:
The rest of the array is composed of 64-Kbyte sectors where each sector comprises 128 pages of 512 bytes. Refer
to Figure 8-3 below.
Figure 8-3.
Flash Sector Organization
A sector size is 64 Kbytes
16 pages of 512 bytes
Small sector 0
16 pages of 512 bytes
Small sector 1
Sector 0
96 pages of 512 bytes
Sector n
Table 8-1.
Larger sector
128 pages of 512 bytes
SAM4CM Flash Size
Device
Flash (Kbytes)
SAM4CM4
256
SAM4CM8
512
SAM4CM16
1024
SAM4CM32
2048 (2 × 1024)
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Figure 8-4 illustrates the organization of the Flash depending on its size.
Figure 8-4.
Flash Size
Flash 2 Mbytes
Flash 1 Mbyte
Flash 512 Kbytes
Flash 256 Kbytes
2 * 8 Kbytes
2 * 8 Kbytes
2 * 8 Kbytes
2 * 8 Kbytes
1 * 48 Kbytes
1 * 48 Kbytes
1 * 48 Kbytes
1 * 48 Kbytes
15 * 64 Kbytes
15 * 64 Kbytes
7 * 64 Kbytes
3 * 64 Kbytes
Plane 0
2 * 8 Kbytes
1 * 48 Kbytes
Plane 1
15 * 64 Kbytes
The following erase commands can be used depending on the sector size:
8-Kbyte small sector
̶
Erase and write page (EWP)
̶
Erase and write page and lock (EWPL)
̶
Erase sector (ES) with FARG set to a page number in the sector to erase
̶
Erase pages (EPA) with FARG [1:0] = 0 to erase four pages or FARG [1:0] = 1 to erase eight pages.
FARG [1:0] = 2 and FARG [1:0] = 3 must not be used.
48-Kbyte and 64-Kbyte sectors
̶
One block of 8 pages inside any sector, with the command Erase pages (EPA) with FARG[1:0] = 1
̶
One block of 16 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 2
̶
One block of 32 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 3
̶
One sector with the command Erase sector (ES) and FARG set to a page number in the sector to
erase
Entire memory plane
̶
8.1.4.2
The entire Flash, with the command Erase all (EA)
Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller manages accesses performed by masters of the system. It enables
reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block. It manages the programming,
erasing, locking and unlocking sequences of the Flash using the full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
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8.1.4.3
Flash Speed
The user must set the number of wait states depending on the frequency used on the SAM4CM.
For more details, refer to Section 46.6 “Embedded Flash Characteristics”.
8.1.4.4
Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of
several consecutive pages, and each lock region has its associated lock bit.
Table 8-2.
Lock Bit Number
Product
Number of Lock Bits
Lock Region Size
SAM4CM32
256 (128 + 128)
8 Kbytes
SAM4CM16
128
8 Kbytes
SAM4CM8
64
8 Kbytes
SAM4CM4
32
8 Kbytes
The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables
the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.1.4.5
Security Bit
The SAM4CM features a security bit based on a specific General-purpose NVM bit (GPNVM bit 0). When the
security is enabled, any access to the Flash, SRAM, core registers and internal peripherals, either through the SWDP/JTAG-DP interface or through the Fast Flash Programming Interface, is forbidden. This ensures the
confidentiality of the code programmed in the Flash.
This security bit can only be enabled through the command “Set General-purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash
erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal
Peripherals are permitted.
8.1.4.6
Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory-configured and cannot be changed
by the user. The ERASE pin has no effect on the unique identifier.
8.1.4.7
User Signature
The memory has one additional reprogrammable page that can be used as page signature by the user. It is
accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the
User Signature page.
8.1.4.8
Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or
through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial
programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
8.1.4.9
SAM-BA Boot
The SAM-BA Boot is a default Boot Program for the master processor (CM4P0) which provides an easy way to
program in-situ the on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART0.
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The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
8.1.4.10 GPNVM Bits
The SAM4CM features two (SAM4CM16/SAM4CM8/SAM4CM4) or three (SAM4CM32) GPNVM bits. These bits
can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC
User Interface (refer to Section 22. “Enhanced Embedded Flash Controller (EEFC)”).
Table 8-3.
8.1.5
General-purpose Nonvolatile Memory Bits
GPNVM Bit
Function
0
Security bit
1
Boot mode selection
2
Memory Plane Boot Selection (Plane 0 or Plane 1) (SAM4CM32 only)
Boot Strategy
Figure 8-5 below shows a load view of the memory at boot time.
Figure 8-5.
Simplified Load View at Boot Time
Flash
Core 0
Application
ICode / DCode Bus
Core 0
Application Core
(Cortex-M4)
Core1
Application
(Binary Img.)
ICode / DCode Bus
Core 1
Metrology Core
(Cortex-M4F)
FPU
SRAM1
NVIC
SRAM2
MPU
S-Bus
NVIC
S-Bus
SRAM0
Clock & Reset
Control
Sub-system 0
Note:
8.1.5.1
Sub-system 1
Matrices, AHB and APB Bridges are not represented.
Application Core (Core 0) Boot Process
The application processor (CM4P0) always boots at the address 0x0. To ensure maximum boot possibilities, the
memory layout can be changed using a General-purpose NVM (GPNVM) bit. A GPNVM bit is used to boot either
on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set through the commands “Clear
General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface. Setting GPNVM Bit 1
selects the boot from Flash whereas clearing this bit selects the boot from ROM. Asserting ERASE clears the
GPNVM Bit 1 and thus selects the boot from the ROM by default.
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8.1.5.2
Metrology/Coprocessor Core (Core 1) Boot Process
After reset, the Sub-system 1 is hold in reset and with no clock. It is up to the Master Application (Core 0
Application) running on the Core 0 to enable the Sub-system 1. Then the application code can be downloaded into
the CM4P1 Boot memory (SRAM1), and CM4P0 can afterwards de-assert the CM4P1 reset line. The secondary
processor (CM4P1) always identifies SRAM1 as “Boot memory”.
8.1.5.3
Sub-system 1 Startup Sequence
After the Core 0 is booted from Flash, the Core 0 application must perform the following steps:
1.
Enable Core 1 System Clock (Bus and peripherals).
2.
Enable Core 1 Clock.
3.
Release Core 1 System Reset (Bus and peripherals).
4.
Enable SRAM1 and SRAM2 Clock.
5.
Copy Core 1 Application from Flash into SRAM1.
6.
Release Core 1 Reset.
After Step 6, the Core 1 boots from SRAM1 memory.
Pseudo-code:
1- // Enable Coprocessor Bus Master Clock (PMC_SCER.CPBMCK).
2- // Enable Coprocessor Clocks (PMC_SCER.CPCK).
// Set Coprocessor Clock Prescaler and Source (PMC_MCKR.CPPRES).
// Choose coprocessor main clock source (PMC_MCKR.CPCSS).
3- // Release coprocessor peripheral reset (RSTC_CPMR.CPEREN).
4- // Enable Core 1 SRAM1 and SRAM2 Memories (PMC_PCER.PID42).
5- // Copy Core 1 application code from Flash into SRAM1.
6- // Release coprocessor reset (RSTC_CPMR.CPROCEN).
8.1.5.4
Sub-system 1 Start-up Time
Table 8-4 provides the start-up time of sub-system 1 in terms of the number of clock cycles for different CPU
speeds. The figures in this table take into account the time to copy 16 Kbytes of code from Flash into SRAM1 using
the ‘memcopy’ function from the standard C library and to release Core 1 reset signal. The start-up time of the
device from power-up is not taken into account.
Table 8-4.
Sub-system 1 Start-up Time
Core Clock (MHz)
Flash Wait State
Core Clock Cycles
Time
21
0
44122
2.1 ms
42
1
45158
1.07 ms
63
2
46203
735 µs
85
3
47242
55 µs
106
4
48284
455 µs
120
5
49329
411 µs
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8.1.5.5
Typical Execution View
Figure 8-6 provides the code execution view for both Cortex-M4 cores. AHB to APB, AHB to AHB and Matrices are
not represented in this view.
Figure 8-6.
Execution View
SRAM0
Core 0,
RW Data,
Stack, Heap
Flash
SRAM1
S-Bus
ICode / DCode Bus
ICode / DCode Bus
Cache
Ctrl.
(CMCC0)
Core 0
Code,
RO Data
Cache
Ctrl.
ICode / DCode Bus
(CMCC1)
Core 0
Core 1
Code,
RO Data
Core 1
Application
Core
(Cortex-M4)
Core 1
Application
Binary
Metrology
Core
(Cortex-M4F)
MPU
NVIC
SRAM2
Core 1,
RW Data,
Stack, Heap
S-Bus
Core 1
Code,
RO Data
FPU
NVIC
S-Bus
Core 0 Core 1
Msg. Buffer (1)
Sub-system 0
Notes:
8.2
1.
2.
Sub-system 1
SRAM0 can also be used as Message Buffer Exchange.
Matrices, AHB and APB Bridges are not represented.
External Memories
The SAM4CM External Bus Interface (EBI) provides the interface to a wide range of external memories and to any
parallel peripheral. Code execution in memories connected to the EBI may benefit from the use of the cache
memories. Refer to Figure 7-2 and Figure 7-3.
The Static Memory Controllers (SMC0/1) / External Bus Interface (EBI) can be used by either the CM4P0 or
CM4P1 but only one path is optimized, CM4P0 ↔ SMC0 or CM4P1 ↔ SMC1.
The SMC0 and SMC1 use the same pins on the EBI. Only one interface can be used at any time.
The selection of the interface is made in the Matrix User Interface Registers (in the System I/O Configuration
Register).
The SMC0 is used by default.
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9.
Real-time Event Management
The events generated by peripherals are designed to be directly routed to peripherals managing/using these
events without processor intervention. Peripherals receiving events contain logic to select the required event.
9.1
Embedded Characteristics
9.2
Timers generate event triggers which are directly routed to event managers, such as ADC, to start
measurement/conversion without processor intervention
UART, USART, SPI, TWI, and PIO generate event triggers directly connected to Peripheral DMA controller
(PDC) for data transfer without processor intervention
PMC Security Event (Clock Failure Detection) can be programmed to switch the MCK on reliable main RC
internal clock
Real-time Event Mapping List
Table 9-1.
Real-time Event Mapping List
Function
Application
Description
Event Source
Event Destination
Safety
General-purpose
Automatic switch to reliable main
RC oscillator in case of main crystal
clock failure(1)
Power Management Controller
(PMC)
PMC
Security
General-purpose
Immediate (asynchronous) clear of
first half of GPBR on tamper
detection through pins(2)
Anti-tamper Inputs (TMPx)
GPBR
TC Output 0
TC Output 1
Measurement
trigger
General-purpose
Trigger source selection in ADC(3)
TC Output 2
TC Output 3
ADC
TC Output 4
TC Output 5
Notes:
1. Refer to Section 30.13 “Main Clock Failure Detector”.
2. Refer to Section 20.4.9.3 “Low-power Debouncer Inputs (Tamper Detection Pins)” and Section 21.3.1 “General Purpose
Backup Register x”.
3. Refer to Section 40.7.2 “ADC Mode Register”.
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10.
System Controller
The System Controller comprises a set of peripherals. It handles key elements of the system, such as power,
resets, clocks, time, interrupts, watchdog, reinforced safety watchdog, etc.
10.1
System Controller and Peripheral Mapping
Refer to Figure 7-4.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2
Power Supply Monitoring
The SAM4CM embeds Supply Monitor, Power-on-Reset and Brownout detectors for power supplies monitoring
allowing to warn and/or reset the chip.
10.2.1 Power-on-Reset on VDDCORE
The Power-on reset monitors VDDCORE. It is always activated and monitors voltage at start-up but also during
power-down. If VDDCORE goes below the threshold voltage, the entire chip (except VDDBU domain) is reset. For
more information, refer to Section 46. “Electrical Characteristics”.
10.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the
Supply Controller (SUPC_MR).
If VDDCORE goes below the threshold voltage, the reset of the core is asserted.
10.2.3 Power-on Reset on VDDIO
The Power-on reset monitors VDDIO. It is always activated and monitors voltage at start-up but also during powerdown. If VDDIO goes below the threshold voltage, only the IOs state and the Embedded Flash are reset, but the
cores and peripherals are not. Voltage detection is not programmable.
10.2.4 Supply Monitor on VDDIO
The supply monitor on VDDIO is fully programmable with 16 steps for the threshold (between 1.6V to 3.4V). It
provides the user the flexibility to set a voltage level detection higher then the power-on-reset on VDDIO. Either a
reset or an interrupt can be generated upon detection. It can be activated by software and it is controlled by the
Supply Controller (SUPC). A sample mode is possible. It divides the supply monitor power consumption by a factor
of up to 2048.
The supply monitor is used as “system alert” in case VDDIO supply is falling. It can be used while the device is in
Backup mode to wake up the device if VDDIO is falling.
10.2.5 Power-on Reset and Brownout Detector on VDDBU
The Power-on reset monitors VDDBU. It is active by default and monitors voltage at start-up but also during
power-down. It can be deactivated by software through the Supply Controller (SUPC_MR). If VDDBU goes below
the threshold voltage, the entire chip is reset.
10.2.6 Power-on Reset on EMAFE Internal VDDIO
The EMAFE Power-on reset monitors VDDIO. It is always activated and monitors voltage at start-up but also
during power-down. If VDDIO goes below the threshold voltage, EMAFE registers are reset and the EMAFE
regulator is shut down. Note that this POR does not reset the rest of the product. Only the EMAFE related registers
are reset.
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10.3
Reset Controller
The Reset Controller uses the power-on-reset, supply monitor and brownout detector cells.
The Reset Controller returns the source of the last reset to the software. Refer to description of field RSTTYP in
Section 15.5.2 “Reset Controller Status Register”.
The Reset Controller controls the internal resets of the system (or independent reset of CM4P1 processor) and the
NRST pin input/output. It shapes a reset signal for the external devices, simplifying to a minimum connection of a
push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved during Backup mode as it is supplied by VDDBU.
10.4
Supply Controller (SUPC)
The Supply Controller controls the power supplies of each section of the processor.
The Supply Controller starts up the device by sequentially enabling the internal power switches and the Voltage
Regulator, then it generates the proper reset signals to the core power supply.
It also sets the system in different low-power modes, wakes it up from a wide range of events.
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11.
Peripherals
11.1
Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers. A peripheral identifier is required for the control of the peripheral
interrupt with the Nested Vectored Interrupt Controller, and for the control of the peripheral clock with the Power
Management Controller.
The two ARM Cortex-M4 processors share the same interrupt mapping, and thus, they share all the interrupts of
the peripherals.
Note:
Table 11-1.
Some peripherals are on the Bus Matrix 0/AHB to APB Bridge 0 and other peripherals are on the Bus Matrix 1/ AHB to
APB Bridge 1. If Core 0 needs to access a peripheral on the Bus Matrix 1/AHB to APB Bridge 1, the Core 0 application
must enable the Core 1 System Clock (Bus and peripherals) and release Core 1 System Reset (Bus and peripherals).
Peripherals on Sub-system 0 or Sub-system 1 are mentioned in the Instance description table that follows.
Peripheral Identifiers
Instance ID
Instance Name
NVIC Interrupt
PMC
Clock Control
0
SUPC
X
–
Supply Controller
1
RSTC
X
–
Reset Controller
2
RTC
X
–
Real-time Clock
3
RTT
X
–
Real-time Timer
4
WDT
X
–
Watchdog Timer
5
PMC
X
–
Power Management Controller
6
EFC0
X
–
Enhanced Embedded Flash Controller 0
7
EFC1
X
–
Enhanced Embedded Flash Controller 1
8
UART0
X
X
UART 0 (Sub-system 0 Clock)
9
–
–
–
Reserved
10
SMC0
–
X
Static Memory Controller 0 (Sub-system 0 Clock)
11
PIOA
X
X
Parallel I/O Controller A (Sub-system 0 Clock)
12
PIOB
X
X
Parallel I/O Controller B (Sub-system 0 Clock)
13
–
–
–
Reserved
14
USART0
X
X
USART 0 (Sub-system 0 Clock)
15
USART1
X
X
USART 1 (Sub-system 0 Clock)
16
USART2
X
X
USART 2 (Sub-system 0 Clock)
17
USART3
X
X
USART 3 (Sub-system 0 Clock)
18
–
–
–
Reserved
19
TWI0
X
X
Two Wire Interface 0 (Sub-system 0 Clock)
20
TWI1
X
X
Two Wire Interface 1 (Sub-system 0 Clock)
21
SPI0
X
X
Serial Peripheral Interface 0 (Sub-system 0 Clock)
22
–
–
–
Reserved
23
TC0
X
X
Timer/Counter 0 (Sub-system 0 Clock)
24
TC1
X
X
Timer/Counter 1 (Sub-system 0 Clock)
25
TC2
X
X
Timer/Counter 2 (Sub-system 0 Clock)
26
TC3
X
X
Timer/Counter 3 (Sub-system 0 Clock)
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Instance Description
Table 11-1.
Peripheral Identifiers (Continued)
Instance ID
Instance Name
NVIC Interrupt
PMC
Clock Control
27
TC4
X
X
Timer/Counter 4 (Sub-system 0 Clock)
28
TC5
X
X
Timer/Counter 5 (Sub-system 0 Clock)
29
ADC
X
X
Analog-to-Digital Converter (Sub-system 0 Clock)
30
ARM
X
–
FPU signals (only on CM4P1 core): FPIXC, FPOFC,
FPUFC, FPIOC, FPDZC, FPIDC, FPIXC
31
IPC0
X
X
Interprocessor communication 0 (Sub-system 0
Clock)
32
SLCDC
X
X
Segment LCD Controller (Sub-system 0 Clock)
33
TRNG
X
X
True Random Generator (Sub-system 0 Clock)
34
ICM
X
X
Integrity Check Module (Sub-system 0 Clock)
35
CPKCC
X
X
Classical Public Key Cryptography Controller (Subsystem 0 Clock)
36
AES
X
X
Advanced Enhanced Standard (Sub-system 0 Clock)
37
PIOC
X
X
Parallel I/O Controller C (Sub-system 1 Clock)
38
UART1
X
X
UART 1 (Sub-system 1 Clock)
39
IPC1
X
X
Interprocessor communication 1 (Sub-system 1
Clock)
40
–
–
–
Reserved
41
PWM
X
X
Pulse Width Modulation (Sub-system 1 Clock)
42
SRAM
–
X
SRAM1 (I/D Code bus of CM4P1), SRAM2 (System
bus of CM4P1) (Sub-system 1 Clock)
43
SMC1
–
X
Static Memory Controller 1 (Sub-system 1 Clock)
Instance Description
SAM4CM Series [DATASHEET]
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49
11.2
Peripheral DMA Controller (PDC)
Two Peripheral DMA Controllers (PDC) are available:
PDC0—dedicated to peripherals on APB0
PDC1—dedicated to peripherals on APB1
Features of the PDC include:
Data transfer handling between peripherals and memories
Low bus arbitration overhead
̶
One master clock cycle needed for a transfer from memory to peripheral
̶
Two master clock cycles needed for a transfer from peripheral to memory
Next Pointer management to reduce interrupt latency requirement
Note that Peripheral DMA 0 on Matrix 0 cannot access SRAM1 or SRAM2. Peripheral DMA 1 on Matrix 1 cannot
access SRAM0.
The PDC handles transfer requests from the channel according to the following priorities (Low to High priorities):
Table 11-2.
Channel T/R
AES
Transmit
TWI0
Transmit
UART0
Transmit
USART1
Transmit
USART0
Transmit
USART2
Transmit
USART3
Transmit
SPI0
Transmit
AES
Receive
TWI0
Receive
UART0
Receive
USART3
Receive
USART2
Receive
USART1
Receive
USART0
Receive
ADC
Receive
SPI0
Receive
Table 11-3.
50
Peripheral DMA Controller (PDC0)
Instance Name
Peripheral DMA Controller (PDC1)
Instance Name
Channel T/R
UART1
Transmit
UART1
Receive
SAM4CM Series [DATASHEET]
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11.3
APB/AHB Bridge
The SAM4CM embeds two peripheral bridges—one on each Matrix, with Matrix 0 for CM4P0 and Matrix 1 for
CM4P1.
The peripherals of the bridge corresponding to CM4P0 (APB0) are clocked by MCK, and the peripherals of the
bridge corresponding to CM4P1 (APB1) are clocked by CPBMCK.
11.4
Peripheral Signal Multiplexing on I/O Lines
The SAM4CM can multiplex the I/O lines of the peripheral set.
The SAM4CM PIO Controllers control up to 32 lines. Each line can be assigned to one of two peripheral functions:
A or B. The multiplexing tables that follow define how the I/O lines of the peripherals A and B are multiplexed on
the PIO Controllers. The column “Comments” has been inserted in this table for the user’s own comments; it may
be used to track how pins are defined in an application.
Note that some peripheral functions which are output only may be duplicated within the tables.
11.4.1 Pad Features
In Table 11-5 to Table 11-7, the column “Feature” indicates whether the corresponding I/O line has programmable
Pull-up, Pull-down and/or Schmitt Trigger. Table 11-4 provides the key to the abbreviations used.
Table 11-4.
I/O Line Features Abbreviations
Abbreviation
Definition
PUP(P)
Programmable Pull-up
PUP(NP)
Non-programmable Pull-up
PDN(P)
Programmable Pull-down
PDN(NP)
Non-programmable Pull-down
ST(P)
Programmable Schmitt Trigger
ST(NP)
Non-programmable Schmitt Trigger
LDRV(P)
Programmable Low Drive
LDRV(NRP)
Non-programmable Low Drive
HDRV(P)
Programmable High Drive
HDRV(NP)
Non-programmable High Drive
MaxDRV(NP)
Non-programmable Maximum Drive
11.4.2 Reset State
In Table 11-5 to Table 11-7, the column “Reset State” indicates the reset state of the line.
PIO or signal name— Indicates whether the PIO line resets in I/O mode or in peripheral mode.
If “PIO” is mentioned, the PIO line is in general-purpose I/O (GPIO). If a signal name is mentioned in the
“Reset State” column, the PIO line is assigned to this function.
I or O— Indicates whether the signal is input or output state.
PU or PD— Indicates whether Pull-up, Pull-down or nothing is enabled.
ST— Indicates that Schmitt Trigger is enabled.
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51
11.4.3 PIO Controller A Multiplexing
Table 11-5.
Multiplexing on PIO Controller A (PIOA)
I/O Line Peripheral A Peripheral B Peripheral C
Extra
Function
System
Function
Feature
Reset State
- PUP(P) / PDN(P)
- ST(P)
- MaxDRV(NP)
PA0
RTS3
PCK2
A10
COM0
WKUP5
PA1
CTS3
NCS1
A9
COM1
–
PA2
SCK3
NCS2
A8
COM2
–
PA3
RXD3
NCS3
A7
COM3
WKUP6
PA4
TXD3
–
A6
COM4/AD1
–
PA5
SPI0_NPCS0
–
A5
COM5/AD2
–
PA6
SPI0_MISO
–
A4
SEG0
–
PA7
SPI0_MOSI
–
A3
SEG1
–
PA8
SPI0_SPCK
–
A2
SEG2
–
PA9
RXD2
–
A1
SEG3
WKUP2
PA10
TXD2
–
A0/NBS0
SEG4
–
PA11
RXD1
–
A23
SEG5
WKUP9
PA12
TXD1
–
SEG6/AD0
–
PA13
SCK2
TIOA0
SEG7
–
PA14
RTS2
TIOB0
A20
SEG8
WKUP3
PA15
CTS2
TIOA4
A19
SEG9
–
PA16
SCK1
TIOB4
A18
SEG10
–
PA17
RTS1
TCLK4
A17
SEG11
WKUP7
PA18
CTS1
TIOA5
A16
SEG12
–
PA19
RTS0
TCLK5
A15
SEG13
WKUP4
PA20
CTS0
TIOB5
A14
SEG14
–
PA21
SPI0_NPCS1
–
A13
SEG15
–
PA22
SPI0_NPCS2
–
A12
SEG16
–
PA23
SPI0_NPCS3
–
A11
SEG17
–
PA24
TWD0
–
A10
SEG18
WKUP1
PA25
TWCK0
–
A9
SEG19
–
PA26
–
–
A8
SEG20
–
PA27
–
–
NCS0
SEG21
–
PA28
–
–
NRD
SEG22
–
PA30
PCK1
–
A15
–
XOUT
- PUP(P) / PDN(P)
- ST(P)
- LDRV(P) / HDRV(P)
XOUT
PA31
PCK0
–
A14
–
XIN
- PUP(P) / PDN(P)
- ST(P)
- LDRV(P) / HDRV(P)
XIN
52
A22/
NANDCLE
A21/
NANDALE
- PUP(P) / PDN(P)
- ST(P)
- LDRV(P) / HDRV(P)
- PUP(P) / PDN(P)
- ST(P)
- MaxDRV(NP)
PIO, I, PU
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
- PUP(P) / PDN(P)
- ST(P)
- LDRV(P) / HDRV(P)
Comments
11.4.4 PIO Controller B Multiplexing
Table 11-6.
I/O
Line
Multiplexing on PIO Controller B (PIOB)
Peripheral
A
Peripheral
B
Peripheral
C
Extra
Function
System
Function
Feature
Reset State
Comments
- PUP(P) / PDN(P)
PB0
TWD1
–
–
–
TDI
- ST(P)
JTAG, I
- LDRV(P) /
HDRV(P)
TDO/
- PUP(P)/PDN(P)
TRACESWO
- LDRV(NP)
PB1
TWCK1
–
–
RTCOUT0
PB2
–
–
–
–
TMS/SWDIO
PB3
–
–
–
–
TCK/SWCLK
PB4
URXD0
TCLK0
A17
–
WKUP8
PB5
UTXD0
–
A16
–
–
PB6
–
–
D0
SEG24
–
PB7
TIOA1
–
D1
SEG25
–
JTAG, O
JTAG, I
PB8
TIOB1
–
D2
SEG26
–
PB9
TCLK1
–
D3
SEG27
–
PB10
TIOA2
–
D4
SEG28
–
PB11
TIOB2
–
D5
SEG29
–
PB12
TCLK2
–
D6
SEG30
–
- PUP(P) / PDN(P)
- ST(P)
- LDRV(P) /
HDRV(P)
PIO, I, PU
- PUP(P) / PDN(P)
PB13
PCK0
–
D7
SEG31/AD3
–
- ST(P)
- MaxDRV(NP)
PB14
–
–
PB15
–
–
NWR0/
NWE
NWR1/
NBS1
SEG32
–
SEG33
–
- PUP(P) / PDN(P)
WKUP10/
PB16
RXD0
–
D8
SEG34
PB17
TXD0
–
D9
SEG35
–
PB18
SCK0
PCK2
D10
SEG36
–
PB19
–
–
D11
SEG37
–
PB21
–
–
D13
SEG39
WKUP11
TMP1
TMP1 is available
only in SAM4CMS
devices.
- ST(P)
- LDRV(P) /
HDRV(P)
PIO, I, PD
SAM4CM Series [DATASHEET]
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53
11.4.5 PIO Controller C Multiplexing
Table 11-7.
Multiplexing on PIO Controller C (PIOC)
I/O
Line
Peripheral A
Peripheral B
Peripheral C
Extra
Function
System
Function
PC0
UTXD1
PWM0
–
–
–
- PUP(P)
- MaxDRV(NP)
PC1
URXD1
PWM1
–
–
WKUP12
- PUP(P) / PDN(P)
- ST(P)
- LDRV(P) / HDRV(P)
PC6
PWM0
–
–
–
–
PC7
PWM1
–
–
–
–
PC9
PWM3
–
–
–
ERASE
54
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Feature
- PUP(P) / PDN(P)
- ST(P)
- LDRV(P) / HDRV(P)
Reset State
PIO, I, PU
ERASE, PD
Comments
12.
ARM Cortex-M4 Processor
12.1
Description
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers
significant benefits to developers, including outstanding processing performance combined with fast interrupt
handling, enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core,
system and memories, ultra-low power consumption with integrated sleep modes, and platform security
robustness, with integrated memory protection unit (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power
efficiency through an efficient instruction set and extensively optimized design, providing high-end processing
hardware including IEEE754-compliant single-precision floating-point computation, a range of single-cycle and
SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware
division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system
components that reduce processor area while significantly improving interrupt handling and system debug
capabilities. The Cortex-M4 processor implements a version of the Thumb® instruction set based on Thumb-2
technology, ensuring high code density and reduced program memory requirements. The Cortex-M4 instruction
set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of
8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt
performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs),
dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the
ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in
assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces
the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that
enables the entire device to be rapidly powered down while still retaining program state.
12.1.1 System Level Interface
The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency
memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables
faster peripheral controls, system spinlocks and thread-safe Boolean data handling.
The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling
applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task
basis. Such requirements are becoming critical in many embedded applications such as automotive.
12.1.2 Integrated Configurable Debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of
the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is
ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints
and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial
Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information
through a single pin.
SAM4CM Series [DATASHEET]
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55
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers
can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the
CODE memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be
patched if a small programmable memory, for example flash, is available in the device. During initialization, the
application in ROM detects, from the programmable memory, whether a patch is required. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed, the
accesses are redirected to a remap table specified in the FPB configuration, which means the program in the nonmodifiable ROM can be patched.
12.2
Embedded Characteristics
Tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
IEEE754-compliant single-precision FPU
Code-patch ability for ROM system updates
Power control optimization of system components
Integrated sleep modes for low power consumption
Fast code execution permits slower processor clock or increases sleep mode time
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory Protection Unit (MPU) for safety-critical applications
Extensive debug and trace capabilities:
̶
12.3
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing,
and code profiling.
Block Diagram
Figure 12-1.
Typical Cortex-M4F Implementation
Cortex-M4F
Processor
FPU
NVIC
Debug
Access
Port
Processor
Core
Memory
Protection Unit
Flash
Patch
Serial
Wire
Viewer
Data
Watchpoints
Bus Matrix
Code
Interface
56
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
SRAM and
Peripheral Interface
12.4
Cortex-M4 Models
12.4.1 Programmers Model
This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it
contains information about the processor modes and privilege levels for software execution and stacks.
12.4.1.1 Processor Modes and Privilege Levels for Software Execution
The processor modes are:
Thread mode
Used to execute application software. The processor enters the Thread mode when it comes out of reset.
Handler mode
Used to handle exceptions. The processor returns to the Thread mode when it has finished exception
processing.
The privilege levels for software execution are:
Unprivileged
The software:
̶
Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
̶
Cannot access the System Timer, NVIC, or System Control Block
̶
Might have a restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
Privileged
The software can use all the instructions and has access to all resources. Privileged software executes at
the privileged level.
In Thread mode, the Control Register controls whether the software execution is privileged or unprivileged, see
“Control Register”. In Handler mode, software execution is always privileged.
Only privileged software can write to the Control Register to change the privilege level for software execution in
Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to
privileged software.
12.4.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked
item in memory When the processor pushes a new item onto the stack, it decrements the stack pointer and then
writes the item to the new memory location. The processor implements two stacks, the main stack and the process
stack, with a pointer for each held in independent registers, see “Stack Pointer”.
In Thread mode, the Control Register controls whether the processor uses the main stack or the process stack,
see “Control Register”.
In Handler mode, the processor always uses the main stack.
The options for processor operations are:
Table 12-1.
Processor
Mode
Summary of Processor Mode, Execution Privilege Level, and Stack Use Options
Used to Execute
Privilege Level for
Software Execution
Thread
Applications
Privileged or unprivileged
Handler
Exception handlers
Always privileged
Note:
1.
Stack Used
(1)
Main stack or process stack(1)
Main stack
See “Control Register”.
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12.4.1.3 Core Registers
Figure 12-2.
Processor Core Registers
R0
R1
R2
R3
Low registers
R4
R5
R6
General-purpose registers
R7
R8
R9
High registers
R10
R11
R12
Stack Pointer
SP (R13)
Link Register
LR (R14)
Program Counter
PC (R15)
PSR
PSP‡
MSP‡
‡
Banked version of SP
Program status register
PRIMASK
FAULTMASK
Exception mask registers
Special registers
BASEPRI
CONTROL
Table 12-2.
CONTROL register
Processor Core Registers
Register
Name
Access(1)
Required Privilege(2)
Reset
General-purpose registers
R0–R12
Read/Write
Either
Unknown
Stack Pointer
MSP
Read/Write
Privileged
See description
Stack Pointer
PSP
Read/Write
Either
Unknown
Link Register
LR
Read/Write
Either
0xFFFFFFFF
Program Counter
PC
Read/Write
Either
See description
Program Status Register
PSR
Read/Write
Privileged
0x01000000
Application Program Status Register
APSR
Read/Write
Either
0x00000000
Interrupt Program Status Register
IPSR
Read-only
Privileged
0x00000000
Execution Program Status Register
EPSR
Read-only
Privileged
0x01000000
Priority Mask Register
PRIMASK
Read/Write
Privileged
0x00000000
Fault Mask Register
FAULTMASK
Read/Write
Privileged
0x00000000
Base Priority Mask Register
BASEPRI
Read/Write
Privileged
0x00000000
Control Register
CONTROL
Read/Write
Privileged
0x00000000
Notes:
58
1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.4.1.4 General-purpose Registers
R0–R12 are 32-bit general-purpose registers for data operations.
12.4.1.5 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the Control Register indicates the stack pointer to
use:
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address 0x00000000.
12.4.1.6 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and
exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.
12.4.1.7 Program Counter
The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads
the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loaded into the
EPSR T-bit at reset and must be 1.
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59
12.4.1.8 Program Status Register
Name:
PSR
Access:
Read/Write
Reset:
0x000000000
31
N
30
Z
29
C
28
V
27
Q
26
23
22
21
20
25
24
T
19
18
17
16
12
11
10
9
–
8
ISR_NUMBER
4
3
2
1
0
ICI/IT
–
15
14
13
ICI/IT
7
6
5
ISR_NUMBER
The Program Status Register (PSR) combines:
• Application Program Status Register (APSR)
• Interrupt Program Status Register (IPSR)
• Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR.
The PSR accesses these registers individually or as a combination of any two or all three registers, using the register
name as an argument to the MSR or MRS instructions. For example:
• Read of all the registers using PSR with the MRS instruction
• Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction.
The PSR combinations and attributes are:
Name
Access
Combination
PSR
Read/Write(1)(2)
APSR, EPSR, and IPSR
IEPSR
Read-only
EPSR and IPSR
IAPSR
APSR and IPSR
(2)
APSR and EPSR
Read/Write
EAPSR
Notes:
(1)
Read/Write
1. The processor ignores writes to the IPSR bits.
2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
See the instruction descriptions “MRS” and “MSR” for more information about how to access the program status registers.
60
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.4.1.9
Application Program Status Register
Name:
APSR
Access:
Read/Write
Reset:
0x000000000
31
N
30
Z
23
22
29
C
28
V
27
Q
26
21
20
19
18
–
15
14
25
–
24
17
16
GE[3:0]
13
12
11
10
9
8
3
2
1
0
–
7
6
5
4
–
The APSR contains the current state of the condition flags from previous instruction executions.
• N: Negative Flag
0: Operation result was positive, zero, greater than, or equal
1: Operation result was negative or less than.
• Z: Zero Flag
0: Operation result was not zero
1: Operation result was zero.
• C: Carry or Borrow Flag
Carry or borrow flag:
0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit
1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
• V: Overflow Flag
0: Operation did not result in an overflow
1: Operation resulted in an overflow.
• Q: DSP Overflow and Saturation Flag
Sticky saturation flag:
0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero
1: Indicates when an SSAT or USAT instruction results in saturation.
This bit is cleared to zero by software using an MRS instruction.
• GE[19:16]: Greater Than or Equal Flags
See “SEL” for more information.
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12.4.1.10 Interrupt Program Status Register
Name:
IPSR
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
–
23
22
21
20
–
15
14
13
12
–
11
10
9
8
ISR_NUMBER
7
6
5
4
3
2
1
0
ISR_NUMBER
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
• ISR_NUMBER: Number of the Current Exception
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7–10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
56 = IRQ40
See “Exception Types” for more information.
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12.4.1.11
Execution Program Status Register
Name:
EPSR
Access:
Read/Write
Reset:
0x000000000
31
23
30
22
29
–
28
21
20
27
26
25
24
T
16
ICI/IT
19
18
17
11
10
9
–
15
14
13
12
ICI/IT
7
6
5
8
–
4
3
2
1
0
–
The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to
write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR
value in the stacked PSR to indicate the operation that is at fault. See “Exception Entry and Return”.
• ICI: Interruptible-continuable Instruction
When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, or VPOP instruction,
the processor:
– Stops the load multiple or store multiple instruction operation temporarily
– Stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
– Returns to the register pointed to by bits[15:12]
– Resumes the execution of the multiple load or store instruction.
When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.
• IT: If-Then Instruction
Indicates the execution state bits of the IT instruction.
The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional.
The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” for more
information.
• T: Thumb State
The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0:
– Instructions BLX, BX and POP{PC}
– Restoration from the stacked xPSR value on an exception return
– Bit[0] of the vector value on an exception entry or reset.
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See “Lockup” for more information.
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12.4.1.12 Exception Mask Registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they
might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the
value of PRIMASK or FAULTMASK. See “MRS”, “MSR”, and “CPS” for more information.
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12.4.1.13 Priority Mask Register
Name:
PRIMASK
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PRIMASK
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
–
The PRIMASK register prevents the activation of all exceptions with a configurable priority.
• PRIMASK
0: No effect
1: Prevents the activation of all exceptions with a configurable priority.
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12.4.1.14 Fault Mask Register
Name:
FAULTMASK
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
FAULTMASK
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
–
The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI).
• FAULTMASK
0: No effect.
1: Prevents the activation of all exceptions except for NMI.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
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12.4.1.15 Base Priority Mask Register
Name:
BASEPRI
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
BASEPRI
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it
prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.
• BASEPRI
Priority mask bits:
0x0000: No effect
Nonzero: Defines the base priority for exception processing
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this
field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” for more information. Remember that higher
priority field values correspond to lower exception priorities.
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12.4.1.16 Control Register
Name:
CONTROL
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
FPCA
1
SPSEL
0
nPRIV
–
23
22
21
20
–
15
14
13
12
–
7
6
5
–
4
The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread
mode and indicates whether the FPU state is active.
• FPCA: Floating-point Context Active
Indicates whether the floating-point context is currently active:
0: No floating-point context active.
1: Floating-point context active.
The Cortex-M4 uses this bit to determine whether to preserve the floating-point state when processing an exception.
• SPSEL: Active Stack Pointer
Defines the current stack:
0: MSP is the current stack pointer.
1: PSP is the current stack pointer.
In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception
return.
• nPRIV: Thread Mode Privilege Level
Defines the Thread mode privilege level:
0: Privileged.
1: Unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the Control
Register when in Handler mode. The exception entry and return mechanisms update the Control Register based on the
EXC_RETURN value.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and
exception handlers use the main stack.
By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
• Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR”, or
• Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 12-10.
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Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures
that instructions after the ISB execute using the new stack pointer. See “ISB”.
12.4.1.17 Exceptions and Interrupts
The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored
Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software
control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and
“Exception Return” for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more
information.
12.4.1.18 Data Types
The processor supports the following data types:
32-bit words
16-bit halfwords
8-bit bytes
The processor manages all data memory accesses as little-endian. Instruction memory and Private
Peripheral Bus (PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” for
more information.
12.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)
For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:
A common way to:
̶
Access peripheral registers
̶
Define exception vectors
The names of:
̶
The registers of the core peripherals
̶
The core exception vectors
A device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor.
The CMSIS simplifies the software development by enabling the reuse of template code and the combination of
CMSIS-compliant software components from various middleware vendors. Software vendors can expand the
CMSIS to include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS
functions that address the processor core and the core peripherals.
Note:
This document uses the register short names defined by the CMSIS. In a few cases, these differ from the architectural
short names that might be used in other documents.
The following sections give more information about the CMSIS:
Section 12.5.3 ”Power Management Programming Hints”
Section 12.6.2 ”CMSIS Functions”
Section 12.8.2.1 ”NVIC Programming Hints”.
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12.4.2 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the bit-banding
features. The processor has a fixed memory map that provides up to 4 GB of addressable memory.
Figure 12-3.
Memory Map
0xFFFFFFFF
Vendor-specific
511 MB
memory
Private peripheral
1.0 MB
bus
External device
0xE0100000
0xE00FFFFF
0xE000 0000
0x DFFFFFFF
1.0 GB
0xA0000000
0x9FFFFFFF
External RAM
0x43FFFFFF
1.0 GB
32 MB Bit-band alias
0x60000000
0x5FFFFFFF
0x42000000
0x400FFFFF
0x40000000
Peripheral
0.5 GB
1 MB Bit-band region
0x40000000
0x3FFFFFFF
0x23FFFFFF
32 MB Bit-band alias
SRAM
0.5 GB
0x20000000
0x1FFFFFFF
0x22000000
Code
0x200FFFFF
0x20000000
1 MB Bit-band region
0.5 GB
0x00000000
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit
data, see “Bit-banding”.
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers.
This memory mapping is generic to ARM Cortex-M4 products. To get the specific memory mapping of this product,
refer to Section 8. ”Memories”.
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12.4.2.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region has a defined
memory type, and some regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
Memory Types
Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
Device
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered
memory.
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can
buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
Additional Memory Attributes
Shareable
For a shareable memory region, the memory system provides data synchronization between bus masters in
a system with multiple bus masters, for example, a processor with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, the software must ensure data
coherency between the bus masters.
Execute Never (XN)
Means the processor prevents instruction accesses. A fault exception is generated only on execution of an
instruction executed from an XN region.
12.4.2.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions, providing
this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on
two memory accesses completing in program order, the software must insert a memory barrier instruction between
the memory access instructions, see “Software Ordering of Memory Accesses”.
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered
memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of
the memory accesses is described below.
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Table 12-3.
Ordering of the Memory Accesses Caused by Two Instructions
A2
Device Access
Normal
Access
Nonshareable
Shareable
Stronglyordered
Access
Normal Access
–
–
–
–
Device access, non-shareable
–
<
–
<
Device access, shareable
–
–
<
<
Strongly-ordered access
–
<
<
<
A1
Where:
–
Means that the memory system does not guarantee the ordering of the accesses.
<
Means that accesses are observed in program order, that is, A1 is always observed
before A2.
12.4.2.3 Behavior of Memory Accesses
The following table describes the behavior of accesses to each region in the memory map.
Table 12-4.
Memory Access Behavior
Address Range
Memory Region
Memory
Type
XN
0x00000000–0x1FFFFFFF
Code
Normal(1)
–
Executable region for program code. Data can also be
put here.
0x20000000–0x3FFFFFFF
SRAM
Normal (1)
–
Executable region for data. Code can also be put here.
This region includes bit band and bit band alias areas,
see Table 12-6.
0x40000000–0x5FFFFFFF
Peripheral
Device (1)
XN
This region includes bit band and bit band alias areas,
see Table 12-6.
0x60000000–0x9FFFFFFF
External RAM
Normal (1)
–
0xA0000000–0xDFFFFFFF
External device
Device (1)
XN
External Device memory
0xE0000000–0xE00FFFFF
Private Peripheral Bus
Stronglyordered (1)
XN
This region includes the NVIC, system timer, and system
control block.
0xE0100000–0xFFFFFFFF
Reserved
Device (1)
XN
Reserved
Note:
Description
Executable region for data
1. See “Memory Regions, Types and Attributes” for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs
always use the Code region. This is because the processor has separate buses that enable instruction fetches and
data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more information, see
“Memory Protection Unit (MPU)”.
Additional Memory Access Constraints For Shared Memory
When a system includes shared memory, some memory regions have additional access constraints, and some
regions are subdivided, as Table 12-5 shows.
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Table 12-5.
Memory Region Shareability Policies
Address Range
0x00000000–0x1FFFFFFF
Memory Region
Memory Type
Code
Shareability
Normal
(1)
–
(1)
–
0x20000000–0x3FFFFFFF
SRAM
Normal
0x40000000–0x5FFFFFFF
Peripheral
Device (1)
–
External RAM
Normal (1)
–
External device
Device (1)
0xE0000000–0xE00FFFFF
Private Peripheral Bus
Strongly-ordered(1)
Shareable (1)
0xE0100000–0xFFFFFFFF
Vendor-specific device
Device (1)
–
0x60000000–0x7FFFFFFF
0x80000000–0x9FFFFFFF
0xA0000000–0xBFFFFFFF
0xC0000000–0xDFFFFFFF
Notes:
Shareable (1)
Non-shareable (1)
1. See “Memory Regions, Types and Attributes” for more information.
Instruction Prefetch and Branch Prediction
The Cortex-M4 processor:
Prefetches instructions ahead of execution
Speculatively prefetches from branch target addresses.
12.4.2.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory
transactions. This is because:
The processor can reorder some memory accesses to improve efficiency, providing this does not affect the
behavior of the instruction sequence.
The processor has multiple bus interfaces
Memory or devices in the memory map have different wait states
Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the
order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include
memory barrier instructions to force that ordering. The processor provides the following memory barrier
instructions:
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before
subsequent memory transactions. See “DMB”.
DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete
before subsequent instructions execute. See “DSB”.
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is
recognizable by subsequent instructions. See “ISB”.
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MPU Programming
Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by
subsequent instructions.
12.4.2.5 Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band
regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:
Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 12-6.
Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in
Table 12-7.
Table 12-6.
SRAM Memory Bit-banding Regions
Address Range
Memory Region
Instruction and Data Accesses
0x20000000–0x200FFFFF
SRAM bit-band region
Direct accesses to this memory range behave as SRAM memory accesses,
but this region is also bit-addressable through bit-band alias.
0x22000000–0x23FFFFFF
SRAM bit-band alias
Data accesses to this region are remapped to bit-band region. A write
operation is performed as read-modify-write. Instruction accesses are not
remapped.
Table 12-7.
Peripheral Memory Bit-banding Regions
Address Range
Memory Region
Instruction and Data Accesses
0x40000000–0x400FFFFF
Peripheral bit-band alias
Direct accesses to this memory range behave as peripheral memory
accesses, but this region is also bit-addressable through bit-band alias.
0x42000000–0x43FFFFFF
Peripheral bit-band region
Data accesses to this region are remapped to bit-band region. A write
operation is performed as read-modify-write. Instruction accesses are not
permitted.
Notes:
1. A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band
region.
2. Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size of the
instruction making the bit-band access.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
Bit_word_offset is the position of the target bit in the bit-band memory region.
Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
Bit_band_base is the starting address of the alias region.
Byte_offset is the number of the byte in the bit-band region that contains the targeted bit.
Bit_number is the bit position, 0–7, of the targeted bit.
Figure 12-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bitband region:
74
The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0 =
0x22000000 + (0xFFFFF*32) + (0*4).
The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC =
0x22000000 + (0xFFFFF*32) + (7*4).
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The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 =
0x22000000 + (0*32) + (0*4).
The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C =
0x22000000+ (0*32) + (7*4).
Figure 12-4.
Bit-band Mapping
32 MB alias region
0x23FFFFFC
0x23FFFFF8
0x23FFFFF4
0x23FFFFF0
0x23FFFFEC
0x23FFFFE8
0x23FFFFE4
0x23FFFFE0
0x2200001C
0x22000018
0x22000014
0x22000010
0x2200000C
0x22000008
0x22000004
0x22000000
1 MB SRAM bit-band region
7
6
5
4
3
2
1
0
7
6
0x200FFFFF
7
6
5
4
3
2
5
4
3
2
1
0
7
6
0x200FFFFE
1
0
0x20000003
7
6
5
4
3
2
0x20000002
5
4
3
2
1
0
7
6
0x200FFFFD
1
0
7
6
5
4
3
2
5
4
3
2
1
0
1
0
0x200FFFFC
1
0
7
0x20000001
6
5
4
3
2
0x20000000
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bitband region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0
writes a 0 to the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF.
Writing 0x00 has the same effect as writing 0x0E.
Reading a word in the alias region:
0x00000000 indicates that the targeted bit in the bit-band region is set to 0
0x00000001 indicates that the targeted bit in the bit-band region is set to 1
Directly Accessing a Bit-band Region
“Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band
regions.
12.4.2.6 Memory Endianness
The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example,
bytes 0–3 hold the first stored word, and bytes 4–7 hold the second stored word. “Little-endian Format” describes
how words of data are stored in memory.
Little-endian Format
In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and
the most significant byte at the highest-numbered byte. For example:
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Figure 12-5.
Little-endian Format
Memory
7
Register
0
31
Address A
B0
A+1
B1
A+2
B2
A+3
B3
lsbyte
24 23
B3
16 15
B2
8 7
B1
0
B0
msbyte
12.4.2.7 Synchronization Primitives
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking
mechanism that a thread or process can use to obtain exclusive access to a memory location. The software can
use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that
location.
A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a
register. If this bit is:
0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds,
1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX
The halfword instructions LDREXH and STREXH
The byte instructions LDREXB and STREXB.
The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, the software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2.
Update the value, as required.
3.
Use a Store-Exclusive instruction to attempt to write the new value back to the memory location
4.
Test the returned status bit. If this bit is:
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of date. The
software must retry the read-modify-write sequence.
The software can use the synchronization primitives to implement a semaphore as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore
is free.
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2.
If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore
address.
3.
If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the
software has claimed the semaphore. However, if the Store-Exclusive instruction failed, another process
might have claimed the semaphore after the software performed the first step.
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The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a LoadExclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory
locations addressed by exclusive accesses by each processor.
The processor removes its exclusive access tag if:
It executes a CLREX instruction
It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
An exception occurs. This means that the processor can resolve semaphore conflicts between different
threads.
In a multiprocessor implementation:
Executing a CLREX instruction removes only the local exclusive access tag for the processor
Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all
global exclusive access tags for the processor.
For more information about the synchronization primitive instructions, see “LDREX and STREX” and “CLREX”.
12.4.2.8 Programming Hints for the Synchronization Primitives
ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for
generation of these instructions:
Table 12-8.
CMSIS Functions for Exclusive Access Instructions
Instruction
CMSIS Function
LDREX
uint32_t __LDREXW (uint32_t *addr)
LDREXH
uint16_t __LDREXH (uint16_t *addr)
LDREXB
uint8_t __LDREXB (uint8_t *addr)
STREX
uint32_t __STREXW (uint32_t value, uint32_t *addr)
STREXH
uint32_t __STREXH (uint16_t value, uint16_t *addr)
STREXB
uint32_t __STREXB (uint8_t value, uint8_t *addr)
CLREX
void __CLREX (void)
The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic
function. For example, the following C code generates the required LDREXB operation:
__ldrex((volatile char *) 0xFF);
12.4.3 Exception Model
This section describes the exception model.
12.4.3.1 Exception States
Each exception is in one of the following states:
Inactive
The exception is not active and not pending.
Pending
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to
pending.
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Active
An exception is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in
the active state.
Active and Pending
The exception is being serviced by the processor and there is a pending exception from the same source.
12.4.3.2 Exception Types
The exception types are:
Reset
Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception.
When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset
is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution
restarts as privileged execution in Thread mode.
Non Maskable Interrupt (NMI)
A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest
priority exception other than reset. It is permanently enabled and has a fixed priority of -2.
NMIs cannot be:
Masked or prevented from activation by any other exception.
Preempted by any exception other than Reset.
Hard Fault
A hard fault is an exception that occurs because of an error during exception processing, or because an exception
cannot be managed by any other exception mechanism. Hard Faults have a fixed priority of -1, meaning they have
higher priority than any exception with configurable priority.
Memory Management Fault (MemManage)
A Memory Management Fault is an exception that occurs because of a memory protection related fault. The MPU
or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions.
This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is
disabled.
Bus Fault
A Bus Fault is an exception that occurs because of a memory related fault for an instruction or data memory
transaction. This might be from an error detected on a bus in the memory system.
Usage Fault
A Usage Fault is an exception that occurs because of a fault related to an instruction execution. This includes:
An undefined instruction
An illegal unaligned access
An invalid state on instruction execution
An error on exception return.
The following can cause a Usage Fault when the core is configured to report them:
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An unaligned address on word and halfword memory access
A division by zero.
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SVCall
A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications
can use SVC instructions to access OS kernel functions and device drivers.
PendSV
PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context
switching when no other exception is active.
SysTick
A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate
a SysTick exception. In an OS environment, the processor can use this exception as system tick.
Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are
asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the
processor.
Table 12-9.
Properties of the Different Exception Types
Exception
Number (1)
Irq Number (1)
Exception Type
Priority
Vector Address
or Offset (2)
Activation
1
–
Reset
-3, the highest
0x00000004
Asynchronous
2
-14
NMI
-2
0x00000008
Asynchronous
3
-13
Hard fault
-1
0x0000000C
–
4
-12
Memory
management fault
Configurable (3)
0x00000010
Synchronous
5
-11
Bus fault
Configurable (3)
0x00000014
Synchronous when precise,
asynchronous when imprecise
6
-10
Usage fault
Configurable (3)
0x00000018
Synchronous
7–10
–
–
–
Reserved
–
0x0000002C
Synchronous
11
-5
SVCall
Configurable
12–13
–
–
–
(3)
Reserved
–
(3)
0x00000038
Asynchronous
0x0000003C
14
-2
PendSV
Configurable
15
-1
SysTick
Configurable (3)
16 and above
Notes:
0 and above
Interrupt (IRQ)
(4)
Configurable
Asynchronous
0x00000040 and above
(5)
Asynchronous
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other
than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register”.
2. See “Vector Table” for more information
3. See “System Handler Priority Registers”
4. See “Interrupt Priority Registers”
5. Increasing in steps of 4.
For an asynchronous exception, other than reset, the processor can execute another instruction between when the
exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 12-9 shows as having configurable priority, see:
“System Handler Control and State Register”
“Interrupt Clear-enable Registers”.
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For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault
Handling”.
12.4.3.3 Exception Handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ40 are the exceptions handled by ISRs.
Fault Handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault
handlers.
System Handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by
system handlers.
12.4.3.4 Vector Table
The vector table contains the reset value of the stack pointer, and the start addresses, also called exception
vectors, for all exception handlers. Figure 12-6 shows the order of the exception vectors in the vector table. The
least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code.
Figure 12-6.
Vector Table
Exception number IRQ number
255
239
.
.
.
18
2
17
1
16
0
15
-1
14
-2
13
Offset
0x03FC
.
.
.
0x004C
0x0048
0x0044
0x0040
0x003C
0x0038
12
11
Vector
IRQ239
.
.
.
IRQ2
IRQ1
IRQ0
SysTick
PendSV
Reserved
Reserved for Debug
-5
10
0x002C
9
SVCall
Reserved
8
7
6
-10
5
-11
4
-12
3
-13
2
-14
1
0x0018
0x0014
0x0010
0x000C
0x0008
0x0004
0x0000
Usage fault
Bus fault
Memory management fault
Hard fault
NMI
Reset
Initial SP value
On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the SCB_VTOR
to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80,
see “Vector Table Offset Register”.
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12.4.3.5 Exception Priorities
As Table 12-9 shows, all exceptions have an associated priority, with:
A lower priority value indicating a higher priority
Configurable priorities for all exceptions except Reset, Hard fault and NMI.
If the software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0.
For information about configuring exception priorities see “System Handler Priority Registers”, and “Interrupt
Priority Registers”.
Note:
Configurable priority values are in the range 0–15. This means that the Reset, Hard fault, and NMI exceptions, with
fixed negative priority values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has
higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception number
takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is
processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority
exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not
preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.
12.4.3.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each
interrupt priority register entry into two fields:
An upper field that defines the group priority
A lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an
interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not
preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they
are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the
lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see “Application
Interrupt and Reset Control Register”.
12.4.3.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
Preemption
When the processor is executing an exception handler, an exception can preempt the exception handler if its
priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” for more
information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” for
more information.
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Return
This occurs when the exception handler is completed, and:
There is no pending exception with sufficient priority to be serviced
The completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
See “Exception Return” for more information.
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending
exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the
new exception handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous
exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that
exception. State saving is not affected by late arrival because the state saved is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the
first instruction of the exception handler of the original exception enters the execute stage of the processor. On
return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.
Exception Entry
An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in
Thread mode, or the new exception is of a higher priority than the exception being handled, in which case the new
exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means that the exception has more priority than any limits set by the mask registers, see
“Exception Mask Registers”. An exception with less priority than this is pending but is not handled by the
processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the
processor pushes information onto the current stack. This operation is referred as stacking and the structure of
eight data words is referred to as stack frame.
When using floating-point routines, the Cortex-M4 processor automatically stacks the architected floating-point
state on exception entry. Figure 12-7 shows the Cortex-M4 stack frame layout when floating-point state is
preserved on the stack as the result of an interrupt or an exception.
Note:
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Where stack space for floating-point state is not allocated, the stack frame is the same as that of ARMv7-M
implementations without an FPU. Figure 12-7 shows this stack frame also.
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Figure 12-7.
Exception Stack Frame
...
{aligner}
FPSCR
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
xPSR
PC
LR
R12
R3
R2
R1
R0
Pre-IRQ top of stack
Decreasing
memory
address
IRQ top of stack
Exception frame with
floating-point storage
...
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
Pre-IRQ top of stack
IRQ top of stack
Exception frame without
floating-point storage
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the
stack frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR).
The stack frame includes the return address. This is the address of the next instruction in the interrupted program.
This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start
address from the vector table. When stacking is complete, the processor starts executing the exception handler. At
the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer
corresponds to the stack frame and what operation mode the processor was in before the entry occurred.
If no higher priority exception occurs during the exception entry, the processor starts executing the exception
handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during the exception entry, the processor starts executing the exception
handler for this exception and does not change the pending status of the earlier exception. This is the late arrival
case.
Exception Return
An Exception return occurs when the processor is in Handler mode and executes one of the following instructions
to load the EXC_RETURN value into the PC:
An LDM or POP instruction that loads the PC
An LDR instruction with the PC as the destination.
A BX instruction using any register.
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EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value
to detect when the processor has completed an exception handler. The lowest five bits of this value provide
information on the return stack and processor mode. Table 12-10 shows the EXC_RETURN values with a
description of the exception return behavior.
All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the
processor that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 12-10.
Exception Return Behavior
EXC_RETURN[31:0]
Description
0xFFFFFFF1
Return to Handler mode, exception return uses non-floating-point state
from the MSP and execution uses MSP after return.
0xFFFFFFF9
Return to Thread mode, exception return uses state from MSP and
execution uses MSP after return.
0xFFFFFFFD
Return to Thread mode, exception return uses state from the PSP and
execution uses PSP after return.
0xFFFFFFE1
Return to Handler mode, exception return uses floating-point-state from
MSP and execution uses MSP after return.
0xFFFFFFE9
Return to Thread mode, exception return uses floating-point state from
MSP and execution uses MSP after return.
0xFFFFFFED
Return to Thread mode, exception return uses floating-point state from PSP
and execution uses PSP after return.
12.4.3.8 Fault Handling
Faults are a subset of the exceptions, see “Exception Model”. The following generate a fault:
A bus error on:
̶
An instruction fetch or vector table load
̶
A data access
An internally-detected error such as an undefined instruction
An attempt to execute an instruction from a memory region marked as Non-Executable (XN).
A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
Fault Types
Table 12-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the
register bit that indicates that the fault has occurred. See “Configurable Fault Status Register” for more information
about the fault status registers.
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Table 12-11.
Faults
Fault
Handler
Bus error on a vector read
Bit Name
Fault Status Register
VECTTBL
Hard fault
“Hard Fault Status Register”
Fault escalated to a hard fault
FORCED
MPU or default memory map mismatch:
–
on instruction access
on data access
during exception stacking
IACCVIOL
Memory
management
fault
–
(1)
DACCVIOL(2)
MSTKERR
during exception unstacking
MUNSTKERR
during lazy floating-point state preservation
MLSPERR(3)
Bus error:
–
during exception stacking
STKERR
during exception unstacking
UNSTKERR
during instruction prefetch
Bus fault
Precise data bus error
PRECISERR
Imprecise data bus error
IMPRECISERR
Attempt to access a coprocessor
NOCP
Undefined instruction
UNDEFINSTR
Attempt to enter an invalid instruction set state
“BFSR: Bus Fault Status Subregister”
INVSTATE
Usage fault
“UFSR: Usage Fault Status Subregister”
Invalid EXC_RETURN value
INVPC
Illegal unaligned load or store
UNALIGNED
Divide By 0
DIVBYZERO
Notes:
–
IBUSERR
LSPERR(3)
during lazy floating-point state preservation
“MMFSR: Memory Management Fault Status
Subregister”
1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with
ICI continuation.
3. Only present in a Cortex-M4F device
Fault Escalation and Hard Faults
All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority
Registers”. The software can disable the execution of the handlers for these faults, see “System Handler Control
and State Register”.
Usually, the exception priority, together with the values of the exception mask registers, determines whether the
processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in
“Exception Model”.
In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and
the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs
because a fault handler cannot preempt itself; it must have the same priority as the current priority level.
A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the
handler for the new fault cannot preempt the currently executing fault handler.
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An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a
hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack
push for the handler failed. The fault handler operates but the stack contents are corrupted.
Note:
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than
Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault
address register indicates the address accessed by the operation that caused the fault, as shown in Table 12-12.
Table 12-12.
Fault Status and Fault Address Registers
Handler
Status Register
Name
Address Register
Name
Register Description
Hard fault
SCB_HFSR
–
“Hard Fault Status Register”
Memory
management fault
MMFSR
SCB_MMFAR
Bus fault
BFSR
SCB_BFAR
Usage fault
UFSR
–
“MMFSR: Memory Management Fault Status Subregister”
“MemManage Fault Address Register”
“BFSR: Bus Fault Status Subregister”
“Bus Fault Address Register”
“UFSR: Usage Fault Status Subregister”
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the
processor is in lockup state, it does not execute any instructions. The processor remains in lockup state until
either:
It is reset
An NMI occurs
It is halted by a debugger.
Note:
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If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup
state.
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12.5
Power Management
The Cortex-M4 processor sleep modes reduce the power consumption:
Sleep mode stops the processor clock
Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register”.
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep
mode.
12.5.1 Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor.
Therefore, the software must be able to put the processor back into sleep mode after such an event. A program
might have an idle loop to put the processor back to sleep mode.
12.5.1.1 Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a
WFI instruction it stops executing instructions and enters sleep mode. See “WFI” for more information.
12.5.1.2 Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event
register. When the processor executes a WFE instruction, it checks this register:
If the register is 0, the processor stops executing instructions and enters sleep mode
If the register is 1, the processor clears the register to 0 and continues executing instructions without
entering sleep mode.
See “WFE” for more information.
12.5.1.3 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception
handler, it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that
only require the processor to run when an exception occurs.
12.5.2 Wakeup from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.
12.5.2.1 Wakeup from WFI or Sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception
entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it
executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an
interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes
up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information
about PRIMASK and FAULTMASK, see “Exception Mask Registers”.
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12.5.2.2 Wakeup from WFE
The processor wakes up if:
It detects an exception with sufficient priority to cause an exception entry
It detects an external event signal. See “External Event Input”
In a multiprocessor system, another processor in the system executes an SEV instruction.
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes
up the processor, even if the interrupt is disabled or has insufficient priority to cause an exception entry. For more
information about the SCR, see “System Control Register”.
12.5.2.3 External Event Input
The processor provides an external event input signal. Peripherals can drive this signal, either to wake the
processor from WFE, or to set the internal WFE event register to 1 to indicate that the processor must not enter
sleep mode on a later WFE instruction. See “Wait for Event” for more information.
12.5.3 Power Management Programming Hints
ISO/IEC C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following functions for
these instructions:
void __WFE(void) // Wait for Event
void __WFI(void) // Wait for Interrupt
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12.6
Cortex-M4 Instruction Set
12.6.1 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions.
Angle brackets, , enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 12-13.
Cortex-M4 Instructions
Mnemonic
Operands
Description
Flags
ADC, ADCS
{Rd,} Rn, Op2
Add with Carry
N,Z,C,V
ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V
ADD, ADDW
{Rd,} Rn, #imm12
Add
N,Z,C,V
ADR
Rd, label
Load PC-relative address
–
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
ASR, ASRS
Rd, Rm,
Arithmetic Shift Right
N,Z,C
B
label
Branch
–
BFC
Rd, #lsb, #width
Bit Field Clear
–
BFI
Rd, Rn, #lsb, #width
Bit Field Insert
–
BIC, BICS
{Rd,} Rn, Op2
Bit Clear
N,Z,C
BKPT
#imm
Breakpoint
–
BL
label
Branch with Link
–
BLX
Rm
Branch indirect with Link
–
BX
Rm
Branch indirect
–
CBNZ
Rn, label
Compare and Branch if Non Zero
–
CBZ
Rn, label
Compare and Branch if Zero
–
CLREX
–
Clear Exclusive
–
CLZ
Rd, Rm
Count leading zeros
–
CMN
Rn, Op2
Compare Negative
N,Z,C,V
CMP
Rn, Op2
Compare
N,Z,C,V
CPSID
i
Change Processor State, Disable Interrupts
–
CPSIE
i
Change Processor State, Enable Interrupts
–
DMB
–
Data Memory Barrier
–
DSB
–
Data Synchronization Barrier
–
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
–
Instruction Synchronization Barrier
–
IT
–
If-Then condition block
–
LDM
Rn{!}, reglist
Load Multiple registers, increment after
–
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Table 12-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
LDMDB, LDMEA
Rn{!}, reglist
Load Multiple registers, decrement before
–
LDMFD, LDMIA
Rn{!}, reglist
Load Multiple registers, increment after
–
LDR
Rt, [Rn, #offset]
Load Register with word
–
LDRB, LDRBT
Rt, [Rn, #offset]
Load Register with byte
–
LDRD
Rt, Rt2, [Rn, #offset]
Load Register with two bytes
–
LDREX
Rt, [Rn, #offset]
Load Register Exclusive
–
LDREXB
Rt, [Rn]
Load Register Exclusive with byte
–
LDREXH
Rt, [Rn]
Load Register Exclusive with halfword
–
LDRH, LDRHT
Rt, [Rn, #offset]
Load Register with halfword
–
LDRSB, DRSBT
Rt, [Rn, #offset]
Load Register with signed byte
–
LDRSH, LDRSHT
Rt, [Rn, #offset]
Load Register with signed halfword
–
LDRT
Rt, [Rn, #offset]
Load Register with word
–
LSL, LSLS
Rd, Rm,
Logical Shift Left
N,Z,C
LSR, LSRS
Rd, Rm,
Logical Shift Right
N,Z,C
MLA
Rd, Rn, Rm, Ra
Multiply with Accumulate, 32-bit result
–
MLS
Rd, Rn, Rm, Ra
Multiply and Subtract, 32-bit result
–
MOV, MOVS
Rd, Op2
Move
N,Z,C
MOVT
Rd, #imm16
Move Top
–
MOVW, MOV
Rd, #imm16
Move 16-bit constant
N,Z,C
MRS
Rd, spec_reg
Move from special register to general register
–
MSR
spec_reg, Rm
Move from general register to special register
N,Z,C,V
MUL, MULS
{Rd,} Rn, Rm
Multiply, 32-bit result
N,Z
MVN, MVNS
Rd, Op2
Move NOT
N,Z,C
NOP
–
No Operation
–
ORN, ORNS
{Rd,} Rn, Op2
Logical OR NOT
N,Z,C
ORR, ORRS
{Rd,} Rn, Op2
Logical OR
N,Z,C
PKHTB, PKHBT
{Rd,} Rn, Rm, Op2
Pack Halfword
–
POP
reglist
Pop registers from stack
–
PUSH
reglist
Push registers onto stack
–
QADD
{Rd,} Rn, Rm
Saturating double and Add
Q
QADD16
{Rd,} Rn, Rm
Saturating Add 16
–
QADD8
{Rd,} Rn, Rm
Saturating Add 8
–
QASX
{Rd,} Rn, Rm
Saturating Add and Subtract with Exchange
–
QDADD
{Rd,} Rn, Rm
Saturating Add
Q
QDSUB
{Rd,} Rn, Rm
Saturating double and Subtract
Q
QSAX
{Rd,} Rn, Rm
Saturating Subtract and Add with Exchange
–
QSUB
{Rd,} Rn, Rm
Saturating Subtract
Q
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Table 12-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
QSUB16
{Rd,} Rn, Rm
Saturating Subtract 16
–
QSUB8
{Rd,} Rn, Rm
Saturating Subtract 8
–
RBIT
Rd, Rn
Reverse Bits
–
REV
Rd, Rn
Reverse byte order in a word
–
REV16
Rd, Rn
Reverse byte order in each halfword
–
REVSH
Rd, Rn
Reverse byte order in bottom halfword and sign extend
–
ROR, RORS
Rd, Rm,
Rotate Right
N,Z,C
RRX, RRXS
Rd, Rm
Rotate Right with Extend
N,Z,C
RSB, RSBS
{Rd,} Rn, Op2
Reverse Subtract
N,Z,C,V
SADD16
{Rd,} Rn, Rm
Signed Add 16
GE
SADD8
{Rd,} Rn, Rm
Signed Add 8 and Subtract with Exchange
GE
SASX
{Rd,} Rn, Rm
Signed Add
GE
SBC, SBCS
{Rd,} Rn, Op2
Subtract with Carry
N,Z,C,V
SBFX
Rd, Rn, #lsb, #width
Signed Bit Field Extract
–
SDIV
{Rd,} Rn, Rm
Signed Divide
–
SEL
{Rd,} Rn, Rm
Select bytes
–
SEV
–
Send Event
–
SHADD16
{Rd,} Rn, Rm
Signed Halving Add 16
–
SHADD8
{Rd,} Rn, Rm
Signed Halving Add 8
–
SHASX
{Rd,} Rn, Rm
Signed Halving Add and Subtract with Exchange
–
SHSAX
{Rd,} Rn, Rm
Signed Halving Subtract and Add with Exchange
–
SHSUB16
{Rd,} Rn, Rm
Signed Halving Subtract 16
–
SHSUB8
{Rd,} Rn, Rm
Signed Halving Subtract 8
–
SMLABB, SMLABT,
SMLATB, SMLATT
Rd, Rn, Rm, Ra
Signed Multiply Accumulate Long (halfwords)
Q
SMLAD, SMLADX
Rd, Rn, Rm, Ra
Signed Multiply Accumulate Dual
Q
SMLAL
RdLo, RdHi, Rn, Rm
Signed Multiply with Accumulate (32 × 32 + 64), 64-bit result
–
SMLALBB, SMLALBT,
SMLALTB, SMLALTT
RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long, halfwords
–
SMLALD, SMLALDX
RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long Dual
–
SMLAWB, SMLAWT
Rd, Rn, Rm, Ra
Signed Multiply Accumulate, word by halfword
Q
SMLSD
Rd, Rn, Rm, Ra
Signed Multiply Subtract Dual
Q
SMLSLD
RdLo, RdHi, Rn, Rm
Signed Multiply Subtract Long Dual
SMMLA
Rd, Rn, Rm, Ra
Signed Most significant word Multiply Accumulate
–
SMMLS, SMMLR
Rd, Rn, Rm, Ra
Signed Most significant word Multiply Subtract
–
SMMUL, SMMULR
{Rd,} Rn, Rm
Signed Most significant word Multiply
–
SMUAD
{Rd,} Rn, Rm
Signed dual Multiply Add
Q
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Table 12-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
SMULBB, SMULBT
SMULTB, SMULTT
{Rd,} Rn, Rm
Signed Multiply (halfwords)
–
SMULL
RdLo, RdHi, Rn, Rm
Signed Multiply (32 × 32), 64-bit result
–
SMULWB, SMULWT
{Rd,} Rn, Rm
Signed Multiply word by halfword
–
SMUSD, SMUSDX
{Rd,} Rn, Rm
Signed dual Multiply Subtract
–
SSAT
Rd, #n, Rm {,shift #s}
Signed Saturate
Q
SSAT16
Rd, #n, Rm
Signed Saturate 16
Q
SSAX
{Rd,} Rn, Rm
Signed Subtract and Add with Exchange
GE
SSUB16
{Rd,} Rn, Rm
Signed Subtract 16
–
SSUB8
{Rd,} Rn, Rm
Signed Subtract 8
–
STM
Rn{!}, reglist
Store Multiple registers, increment after
–
STMDB, STMEA
Rn{!}, reglist
Store Multiple registers, decrement before
–
STMFD, STMIA
Rn{!}, reglist
Store Multiple registers, increment after
–
STR
Rt, [Rn, #offset]
Store Register word
–
STRB, STRBT
Rt, [Rn, #offset]
Store Register byte
–
STRD
Rt, Rt2, [Rn, #offset]
Store Register two words
–
STREX
Rd, Rt, [Rn, #offset]
Store Register Exclusive
–
STREXB
Rd, Rt, [Rn]
Store Register Exclusive byte
–
STREXH
Rd, Rt, [Rn]
Store Register Exclusive halfword
–
STRH, STRHT
Rt, [Rn, #offset]
Store Register halfword
–
STRT
Rt, [Rn, #offset]
Store Register word
–
SUB, SUBS
{Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW
{Rd,} Rn, #imm12
Subtract
N,Z,C,V
SVC
#imm
Supervisor Call
–
SXTAB
{Rd,} Rn, Rm,{,ROR #}
Extend 8 bits to 32 and add
–
SXTAB16
{Rd,} Rn, Rm,{,ROR #}
Dual extend 8 bits to 16 and add
–
SXTAH
{Rd,} Rn, Rm,{,ROR #}
Extend 16 bits to 32 and add
–
SXTB16
{Rd,} Rm {,ROR #n}
Signed Extend Byte 16
–
SXTB
{Rd,} Rm {,ROR #n}
Sign extend a byte
–
SXTH
{Rd,} Rm {,ROR #n}
Sign extend a halfword
–
TBB
[Rn, Rm]
Table Branch Byte
–
TBH
[Rn, Rm, LSL #1]
Table Branch Halfword
–
TEQ
Rn, Op2
Test Equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UADD16
{Rd,} Rn, Rm
Unsigned Add 16
GE
UADD8
{Rd,} Rn, Rm
Unsigned Add 8
GE
USAX
{Rd,} Rn, Rm
Unsigned Subtract and Add with Exchange
GE
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Table 12-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
UHADD16
{Rd,} Rn, Rm
Unsigned Halving Add 16
–
UHADD8
{Rd,} Rn, Rm
Unsigned Halving Add 8
–
UHASX
{Rd,} Rn, Rm
Unsigned Halving Add and Subtract with Exchange
–
UHSAX
{Rd,} Rn, Rm
Unsigned Halving Subtract and Add with Exchange
–
UHSUB16
{Rd,} Rn, Rm
Unsigned Halving Subtract 16
–
UHSUB8
{Rd,} Rn, Rm
Unsigned Halving Subtract 8
–
UBFX
Rd, Rn, #lsb, #width
Unsigned Bit Field Extract
–
UDIV
{Rd,} Rn, Rm
Unsigned Divide
–
UMAAL
RdLo, RdHi, Rn, Rm
Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32),
64-bit result
–
UMLAL
RdLo, RdHi, Rn, Rm
Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result
–
UMULL
RdLo, RdHi, Rn, Rm
Unsigned Multiply (32 × 32), 64-bit result
–
UQADD16
{Rd,} Rn, Rm
Unsigned Saturating Add 16
–
UQADD8
{Rd,} Rn, Rm
Unsigned Saturating Add 8
–
UQASX
{Rd,} Rn, Rm
Unsigned Saturating Add and Subtract with Exchange
–
UQSAX
{Rd,} Rn, Rm
Unsigned Saturating Subtract and Add with Exchange
–
UQSUB16
{Rd,} Rn, Rm
Unsigned Saturating Subtract 16
–
UQSUB8
{Rd,} Rn, Rm
Unsigned Saturating Subtract 8
–
USAD8
{Rd,} Rn, Rm
Unsigned Sum of Absolute Differences
–
USADA8
{Rd,} Rn, Rm, Ra
Unsigned Sum of Absolute Differences and Accumulate
–
USAT
Rd, #n, Rm {,shift #s}
Unsigned Saturate
Q
USAT16
Rd, #n, Rm
Unsigned Saturate 16
Q
UASX
{Rd,} Rn, Rm
Unsigned Add and Subtract with Exchange
GE
USUB16
{Rd,} Rn, Rm
Unsigned Subtract 16
GE
USUB8
{Rd,} Rn, Rm
Unsigned Subtract 8
GE
UXTAB
{Rd,} Rn, Rm,{,ROR #}
Rotate, extend 8 bits to 32 and Add
–
UXTAB16
{Rd,} Rn, Rm,{,ROR #}
Rotate, dual extend 8 bits to 16 and Add
–
UXTAH
{Rd,} Rn, Rm,{,ROR #}
Rotate, unsigned extend and Add Halfword
–
UXTB
{Rd,} Rm {,ROR #n}
Zero extend a byte
–
UXTB16
{Rd,} Rm {,ROR #n}
Unsigned Extend Byte 16
–
UXTH
{Rd,} Rm {,ROR #n}
Zero extend a halfword
–
VABS.F32
Sd, Sm
Floating-point Absolute
–
VADD.F32
{Sd,} Sn, Sm
Floating-point Add
–
VCMP.F32
Sd,
Compare two floating-point registers, or one floating-point register
and zero
FPSCR
VCMPE.F32
Sd,
Compare two floating-point registers, or one floating-point register
and zero with Invalid Operation check
FPSCR
VCVT.S32.F32
Sd, Sm
Convert between floating-point and integer
–
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Table 12-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
VCVT.S16.F32
Sd, Sd, #fbits
Convert between floating-point and fixed point
–
VCVTR.S32.F32
Sd, Sm
Convert between floating-point and integer with rounding
–
VCVT.F32.F16
Sd, Sm
Converts half-precision value to single-precision
–
VCVTT.F32.F16
Sd, Sm
Converts single-precision register to half-precision
–
VDIV.F32
{Sd,} Sn, Sm
Floating-point Divide
–
VFMA.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Accumulate
–
VFNMA.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply Accumulate
–
VFMS.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Subtract
–
VFNMS.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply Subtract
–
VLDM.F
Rn{!}, list
Load Multiple extension registers
–
VLDR.F
, [Rn]
Load an extension register from memory
–
VLMA.F32
{Sd,} Sn, Sm
Floating-point Multiply Accumulate
–
VLMS.F32
{Sd,} Sn, Sm
Floating-point Multiply Subtract
–
VMOV.F32
Sd, #imm
Floating-point Move immediate
–
VMOV
Sd, Sm
Floating-point Move register
–
VMOV
Sn, Rt
Copy ARM core register to single precision
–
VMOV
Sm, Sm1, Rt, Rt2
Copy 2 ARM core registers to 2 single precision
–
VMOV
Dd[x], Rt
Copy ARM core register to scalar
–
VMOV
Rt, Dn[x]
Copy scalar to ARM core register
–
VMRS
Rt, FPSCR
Move FPSCR to ARM core register or APSR
N,Z,C,V
VMSR
FPSCR, Rt
Move to FPSCR from ARM Core register
FPSCR
VMUL.F32
{Sd,} Sn, Sm
Floating-point Multiply
–
VNEG.F32
Sd, Sm
Floating-point Negate
–
VNMLA.F32
Sd, Sn, Sm
Floating-point Multiply and Add
–
VNMLS.F32
Sd, Sn, Sm
Floating-point Multiply and Subtract
–
VNMUL
{Sd,} Sn, Sm
Floating-point Multiply
–
VPOP
list
Pop extension registers
–
VPUSH
list
Push extension registers
–
VSQRT.F32
Sd, Sm
Calculates floating-point Square Root
–
VSTM
Rn{!}, list
Floating-point register Store Multiple
–
VSTR.F
Sd, [Rn]
Stores an extension register to memory
–
VSUB.F
{Sd,} Sn, Sm
Floating-point Subtract
–
WFE
–
Wait For Event
–
WFI
–
Wait For Interrupt
–
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12.6.2 CMSIS Functions
ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can
generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler
does not support an appropriate intrinsic function, the user might have to use inline assembler to access some
instructions.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly
access:
Table 12-14.
CMSIS Functions to Generate some Cortex-M4 Instructions
Instruction
CMSIS Function
CPSIE I
void __enable_irq(void)
CPSID I
void __disable_irq(void)
CPSIE F
void __enable_fault_irq(void)
CPSID F
void __disable_fault_irq(void)
ISB
void __ISB(void)
DSB
void __DSB(void)
DMB
void __DMB(void)
REV
uint32_t __REV(uint32_t int value)
REV16
uint32_t __REV16(uint32_t int value)
REVSH
uint32_t __REVSH(uint32_t int value)
RBIT
uint32_t __RBIT(uint32_t int value)
SEV
void __SEV(void)
WFE
void __WFE(void)
WFI
void __WFI(void)
The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR
instructions:
Table 12-15.
CMSIS Intrinsic Functions to Access the Special Registers
Special Register
Access
CMSIS Function
Read
uint32_t __get_PRIMASK (void)
Write
void __set_PRIMASK (uint32_t value)
Read
uint32_t __get_FAULTMASK (void
Write
void __set_FAULTMASK (uint32_t value)
Read
uint32_t __get_BASEPRI (void)
Write
void __set_BASEPRI (uint32_t value)
Read
uint32_t __get_CONTROL (void)
Write
void __set_CONTROL (uint32_t value)
Read
uint32_t __get_MSP (void)
Write
void __set_MSP (uint32_t TopOfMainStack)
Read
uint32_t __get_PSP (void)
Write
void __set_PSP (uint32_t TopOfProcStack)
PRIMASK
FAULTMASK
BASEPRI
CONTROL
MSP
PSP
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12.6.3 Instruction Descriptions
12.6.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions
act on the operands and often store the result in a destination register. When there is a destination register in the
instruction, it is usually specified before the operands.
Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand”.
12.6.3.2 Restrictions when Using PC or SP
Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands
or destination register can be used. See instruction descriptions for more information.
Note:
Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution,
because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb instructions.
12.6.3.3 Flexible Second Operand
Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the
descriptions of the syntax of each instruction.
Operand2 can be a:
“Constant”
“Register with Optional Shift”
Constant
Specify an Operand2 constant in the form:
#constant
where constant can be:
Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
Any constant of the form 0x00XY00XY
Any constant of the form 0xXY00XY00
Any constant of the form 0xXYXYXYXY.
Note:
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are described in
the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS,
TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be
produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other
constant.
Instruction Substitution
The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant
that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the
equivalent instruction CMN Rd, #0x2.
Register with Optional Shift
Specify an Operand2 register in the form:
Rm {, shift}
where:
96
Rm
is the register holding the data for the second operand.
shift
is an optional shift to be applied to Rm. It can be one of:
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ASR #n
arithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL #n
logical shift left n bits, 1 ≤ n ≤ 31.
LSR #n
logical shift right n bits, 1 ≤ n ≤ 32.
ROR #n
rotate right n bits, 1 ≤ n ≤ 31.
RRX
rotate right one bit, with extend.
-
if omitted, no shift occurs, equivalent to LSL #0.
If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm.
If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the
instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also
updates the carry flag when used with certain instructions. For information on the shift operations and how they
affect the carry flag, see “Flexible Second Operand”.
12.6.3.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits, the shift length.
Register shift can be performed:
Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register
During the calculation of Operand2 by the instructions that specify the second operand as a register with
shift. See “Flexible Second Operand”. The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs.
Register shift operations update the carry flag except when the specified shift length is 0. The following
subsections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is
the register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the
right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the
result. See Figure 12-8.
The ASR #n operation can be used to divide the value in the register Rm by 2n, with the result being rounded
towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the
register Rm.
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 12-8.
ASR #3
LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the righthand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 12-9.
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The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an
unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the
register Rm.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 12-9.
LSR #3
&DUU\
)ODJ
LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand
32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 12-10.
The LSL #n operation can be used to multiply the value in the register Rm by 2n, if the value is regarded as an
unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 12-10. LSL #3
&DUU\
)ODJ
ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand
32-n bits of the result; and it moves the right-hand n bits of the register into the left-hand n bits of the result. See
Figure 12-11.
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register
Rm.
98
If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated
to bit[31] of Rm.
ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
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Figure 12-11. ROR #3
&DUU\
)ODJ
RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into
bit[31] of the result. See Figure 12-12.
When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 12-12. RRX
&DUU\
)ODJ
12.6.3.5 Address Alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word
access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.
The Cortex-M4 processor supports unaligned access only for the following instructions:
LDR, LDRT
LDRH, LDRHT
LDRSH, LDRSHT
STR, STRT
STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an unaligned access, and
therefore their accesses must be address-aligned. For more information about usage faults, see “Fault Handling”.
Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not
support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned.
To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control
Register to trap all unaligned accesses, see “Configuration and Control Register”.
12.6.3.6 PC-relative Expressions
A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is
represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the
required offset from the label and the address of the current instruction. If the offset is too big, the assembler
produces an error.
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4
bytes.
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For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4
bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a
number, or an expression of the form [PC, #number].
12.6.3.7 Conditional Execution
Most data processing instructions can optionally update the condition flags in the Application Program Status
Register (APSR) according to the result of the operation, see “Application Program Status Register”. Some
instructions update all flags, and some only update a subset. If a flag is not updated, the original value is
preserved. See the instruction descriptions for the flags they affect.
An instruction can be executed conditionally, based on the condition flags set in another instruction, either:
Immediately after the instruction that updated the flags
After any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition code suffixes to
instructions. See Table 12-16 for a list of the suffixes to add to instructions to make them conditional instructions.
The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a
conditional instruction fails, the instruction:
Does not execute
Does not write any value to its destination register
Does not affect any of the flags
Does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” for
more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might
automatically insert an IT instruction if there are conditional instructions outside the IT block.
The CBZ and CBNZ instructions are used to compare the value of a register against zero and branch on the result.
This section describes:
“Condition Flags”
“Condition Code Suffixes”.
Condition Flags
The APSR contains the following condition flags:
N
Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z
Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C
Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V
Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR, see “Program Status Register”.
A carry occurs:
If the result of an addition is greater than or equal to 232
If the result of a subtraction is positive or zero
As the result of an inline barrel shifter operation in a move or logical instruction.
An overflow occurs when the sign of the result, in bit[31], does not match the sign of the result, had the operation
been performed at infinite precision, for example:
100
If adding two negative values results in a positive value
If adding two positive values results in a negative value
If subtracting a positive value from a negative value generates a positive value
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If subtracting a negative value from a positive value generates a negative value.
The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is
discarded. See the instruction descriptions for more information.
Note:
Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more
information.
Condition Code Suffixes
The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}.
Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if
the condition code flags in the APSR meet the specified condition. Table 12-16 shows the condition codes to use.
A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code.
Table 12-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.
Table 12-16.
Condition Code Suffixes
Suffix
Flags
Meaning
EQ
Z=1
Equal
NE
Z=0
Not equal
CS or HS
C=1
Higher or same, unsigned ≥
CC or LO
C=0
Lower, unsigned <
MI
N=1
Negative
PL
N=0
Positive or zero
VS
V=1
Overflow
VC
V=0
No overflow
HI
C = 1 and Z = 0
Higher, unsigned >
LS
C = 0 or Z = 1
Lower or same, unsigned ≤
GE
N=V
Greater than or equal, signed ≥
LT
N != V
Less than, signed <
GT
Z = 0 and N = V
Greater than, signed >
LE
Z = 1 and N != V
Less than or equal, signed ≤
AL
Can have any value
Always. This is the default when no suffix is specified.
Absolute Value
The example below shows the use of a conditional instruction to find the absolute value of a number. R0 =
ABS(R1).
MOVS
R0, R1
; R0 = R1, setting flags
IT
MI
; IT instruction for the negative condition
RSBMI
R0, R1, #0
; If negative, R0 = -R1
Compare and Update Value
The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is
greater than R1 and R2 is greater than R3.
CMP
R0, R1
; Compare R0 and R1, setting flags
ITT
GT
; IT instruction for the two GT conditions
CMPGT
R2, R3
; If 'greater than', compare R2 and R3, setting flags
MOVGT
R4, R5
; If still 'greater than', do R4 = R5
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12.6.3.8 Instruction Width Selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the
operands and destination register specified. For some of these instructions, the user can force a specific
instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix
forces a 16-bit instruction encoding.
If the user specifies an instruction width suffix and the assembler cannot generate an instruction encoding of the
requested width, it generates an error.
Note:
In some cases, it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or
literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the
right size encoding.
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any.
The example below shows instructions with the instruction width suffix.
BCS.W label
; creates a 32-bit instruction even for a short
; branch
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
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12.6.4 Memory Access Instructions
The table below shows the memory access instructions.
Table 12-17.
Memory Access Instructions
Mnemonic
Description
ADR
Load PC-relative address
CLREX
Clear Exclusive
LDM{mode}
Load Multiple registers
LDR{type}
Load Register using immediate offset
LDR{type}
Load Register using register offset
LDR{type}T
Load Register with unprivileged access
LDR
Load Register using PC-relative address
LDRD
Load Register Dual
LDREX{type}
Load Register Exclusive
POP
Pop registers from stack
PUSH
Push registers onto stack
STM{mode}
Store Multiple registers
STR{type}
Store Register using immediate offset
STR{type}
Store Register using register offset
STR{type}T
Store Register with unprivileged access
STREX{type}
Store Register Exclusive
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12.6.4.1 ADR
Load PC-relative address.
Syntax
ADR{cond} Rd, label
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
label
is a PC-relative expression. See “PC-relative Expressions”.
Operation
ADR determines the address by adding an immediate value to the PC, and writes the result to the destination
register.
ADR produces position-independent code, because the address is PC-relative.
If ADR is used to generate a target address for a BX or BLX instruction, ensure that bit[0] of the address generated
is set to 1 for correct execution.
Values of label must be within the range of −4095 to +4095 from the address in the PC.
Note:
The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not wordaligned. See “Instruction Width Selection”.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
ADR
104
R1, TextMessage
; Write address value of a location labelled as
; TextMessage to R1
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12.6.4.2 LDR and STR, Immediate Offset
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
Syntax
op{type}{cond} Rt,
op{type}{cond} Rt,
op{type}{cond} Rt,
opD{cond} Rt, Rt2,
opD{cond} Rt, Rt2,
opD{cond} Rt, Rt2,
[Rn {, #offset}]
[Rn, #offset]!
[Rn], #offset
[Rn {, #offset}]
[Rn, #offset]!
[Rn], #offset
;
;
;
;
;
;
immediate offset
pre-indexed
post-indexed
immediate offset, two words
pre-indexed, two words
post-indexed, two words
where:
op
is one of:
LDR
Load Register.
STR
Store Register.
type
is one of:
B
unsigned byte, zero extend to 32 bits on loads.
SB
signed byte, sign extend to 32 bits (LDR only).
H
unsigned halfword, zero extend to 32 bits on loads.
SH
signed halfword, sign extend to 32 bits (LDR only).
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution”.
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an offset from Rn. If offset is omitted, the address is the contents of Rn.
Rt2
is the additional register to load or store for two-word operations.
Operation
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
Offset Addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the
address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is:
[Rn, #offset]
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Pre-indexed Addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the
address for the memory access and written back into the register Rn. The assembly language syntax for this mode
is:
[Rn, #offset]!
Post-indexed Addressing
The address obtained from the register Rn is used as the address for the memory access. The offset value is
added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for
this mode is:
[Rn], #offset
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed
or unsigned. See “Address Alignment”.
The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Table 12-18.
Offset Ranges
Instruction Type
Immediate Offset
Pre-indexed
Post-indexed
Word, halfword, signed
halfword, byte, or signed byte
-255 to 4095
-255 to 255
-255 to 255
Two words
multiple of 4 in the
range -1020 to 1020
multiple of 4 in the
range -1020 to 1020
multiple of 4 in the
range -1020 to 1020
Restrictions
For load instructions:
Rt can be SP or PC for word loads only
Rt must be different from Rt2 for two-word loads
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution
A branch occurs to the address created by changing bit[0] of the loaded value to 0
If the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
Rt can be SP for word stores only
Rt must not be PC
Rn must not be PC
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
Condition Flags
These instructions do not change the flags.
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Examples
LDR
LDRNE
R8, [R10]
R2, [R5, #960]!
STR
R2, [R9,#const-struc]
STRH
R3, [R4], #4
LDRD
R8, R9, [R3, #0x20]
STRD
R0, R1, [R8], #-16
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Loads R8 from the address in R10.
Loads (conditionally) R2 from a word
960 bytes above the address in R5, and
increments R5 by 960.
const-struc is an expression evaluating
to a constant in the range 0-4095.
Store R3 as halfword data into address in
R4, then increment R4 by 4
Load R8 from a word 32 bytes above the
address in R3, and load R9 from a word 36
bytes above the address in R3
Store R0 to address in R8, and store R1 to
a word 4 bytes above the address in R8,
and then decrement R8 by 16.
12.6.4.3 LDR and STR, Register Offset
Load and Store with register offset.
Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op
is one of:
LDR
Load Register.
STR
Store Register.
type
is one of:
B
unsigned byte, zero extend to 32 bits on loads.
SB
signed byte, sign extend to 32 bits (LDR only).
H
unsigned halfword, zero extend to 32 bits on loads.
SH
signed halfword, sign extend to 32 bits (LDR only).
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution”.
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
Rm
is a register containing a value to be used as the offset.
LSL #n
is an optional shift, with n in the range 0 to 3.
Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the
register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment”.
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Restrictions
In these instructions:
Rn must not be PC
Rm must not be SP and must not be PC
Rt can be SP only for word loads and word stores
Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
STR
LDRSB
STR
108
R0, [R5, R1]
;
;
R0, [R5, R1, LSL #1] ;
;
;
R0, [R1, R2, LSL #2] ;
;
Store value of R0 into an address equal to
sum of R5 and R1
Read byte value from an address equal to
sum of R5 and two times R1, sign extended it
to a word value and put it in R0
Stores R0 to an address equal to sum of R1
and four times R2
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12.6.4.4 LDR and STR, Unprivileged
Load and Store with unprivileged access.
Syntax
op{type}T{cond} Rt, [Rn {, #offset}]
; immediate offset
where:
op
is one of:
LDR
Load Register.
STR
Store Register.
type is one of:
B
unsigned byte, zero extend to 32 bits on loads.
SB
signed byte, sign extend to 32 bits (LDR only).
H
unsigned halfword, zero extend to 32 bits on loads.
SH
signed halfword, sign extend to 32 bits (LDR only).
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution”.
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
Operation
These load and store instructions perform the same function as the memory access instructions with immediate
offset, see “LDR and STR, Immediate Offset”. The difference is that these instructions have only unprivileged
access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as normal memory access
instructions with immediate offset.
Restrictions
In these instructions:
Rn must not be PC
Rt must not be SP and must not be PC.
Condition Flags
These instructions do not change the flags.
Examples
STRBTEQ
R4, [R7]
LDRHT
R2, [R2, #8]
;
;
;
;
Conditionally store least significant byte in
R4 to an address in R7, with unprivileged access
Load halfword value from an address equal to
sum of R2 and 8 into R2, with unprivileged access
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12.6.4.5 LDR, PC-relative
Load register from memory.
Syntax
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
; Load two words
where:
type
is one of:
B
unsigned byte, zero extend to 32 bits.
SB
signed byte, sign extend to 32 bits.
H
unsigned halfword, zero extend to 32 bits.
SH
signed halfword, sign extend to 32 bits.
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution”.
Rt
is the register to load or store.
Rt2
is the second register to load or store.
label
is a PC-relative expression. See “PC-relative Expressions”.
Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label
or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment”.
label must be within a limited range of the current instruction. The table below shows the possible offsets between
label and the PC.
Table 12-19.
Offset Ranges
Instruction Type
Offset Range
Word, halfword, signed halfword, byte, signed byte
-4095 to 4095
Two words
-1020 to 1020
The user might have to use the .W suffix to get the maximum offset range. See “Instruction Width Selection”.
Restrictions
In these instructions:
110
Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2.
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When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDR
R0, LookUpTable
LDRSB
R7, localdata
;
;
;
;
;
Load R0 with a word of data from an address
labelled as LookUpTable
Load a byte value from an address labelled
as localdata, sign extend it to a word
value, and put it in R7
12.6.4.6 LDM and STM
Load and Store Multiple registers.
Syntax
op{addr_mode}{cond} Rn{!}, reglist
where:
op
is one of:
LDM
Load Multiple registers.
STM
Store Multiple registers.
addr_mode
is any one of the following:
IA
Increment address After each access. This is the default.
DB
Decrement address Before each access.
cond
is an optional condition code, see “Conditional Execution”.
Rn
is the register on which the memory addresses are based.
!
is an optional writeback suffix.
If ! is present, the final address, that is loaded from or stored to, is written back into Rn.
reglist
is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma separated if it contains more
than one register or register range, see “Examples”.
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending
stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending
stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks
Operation
LDM instructions load the registers in reglist with word values from memory addresses based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses based on Rn.
For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte
intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in
order of increasing register numbers, with the lowest numbered register using the lowest memory address and the
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highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4
* (n-1) is written back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals
ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of
decreasing register numbers, with the highest numbered register using the highest memory address and the
lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 *
(n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See “PUSH and POP”for details.
Restrictions
In these instructions:
Rn must not be PC
reglist must not contain SP
In any STM instruction, reglist must not contain PC
In any LDM instruction, reglist must not contain PC if it contains LR
reglist must not contain Rn if the writeback suffix is specified.
When PC is in reglist in an LDM instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDM
STMDB
R8,{R0,R2,R9}
; LDMIA is a synonym for LDM
R1!,{R3-R6,R11,R12}
Incorrect Examples
STM
LDM
112
R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
R2, {}
; There must be at least one register in the list
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12.6.4.7 PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
Syntax
PUSH{cond} reglist
POP{cond} reglist
where:
cond
is an optional condition code, see “Conditional Execution”.
reglist
is a non-empty list of registers, enclosed in braces. It can contain register
ranges. It must be comma separated if it contains more than one register or
register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based
on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred
mnemonics in these cases.
Operation
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered
register using the highest memory address and the lowest numbered register using the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register
using the lowest memory address and the highest numbered register using the highest memory address.
See “LDM and STM” for more information.
Restrictions
In these instructions:
reglist must not contain SP
For the PUSH instruction, reglist must not contain PC
For the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
PUSH
PUSH
POP
{R0,R4-R7}
{R2,LR}
{R0,R10,PC}
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12.6.4.8 LDREX and STREX
Load and Store Register Exclusive.
Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register for the returned status.
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
Operation
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address.
The address used in any Store-Exclusive instruction must be the same as the address in the most recently
executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same
data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a
Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see
“Synchronization Primitives”.
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the
store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is
guaranteed that no other process in the system has accessed the memory location between the Load-exclusive
and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and StoreExclusive instruction to a minimum.
The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding
Load-Exclusive instruction is unpredictable.
Restrictions
In these instructions:
114
Do not use PC
Do not use SP for Rd and Rt
For STREX, Rd must be different from both Rt and Rn
The value of offset must be a multiple of four in the range 0–1020.
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Condition Flags
These instructions do not change the flags.
Examples
MOV
LDREX
CMP
ITT
STREXEQ
CMPEQ
BNE
....
R1,
R0,
R0,
EQ
R0,
R0,
try
#0x1
[LockAddr]
#0
R1, [LockAddr]
#0
;
;
;
;
;
;
;
;
Initialize the ‘lock taken’ value try
Load the lock value
Is the lock free?
IT instruction for STREXEQ and CMPEQ
Try and claim the lock
Did this succeed?
No – try again
Yes – we have the lock
12.6.4.9 CLREX
Clear Exclusive.
Syntax
CLREX{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write a 1 to its destination register and fail
to perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception
occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization
operation.
See “Synchronization Primitives” for more information.
Condition Flags
These instructions do not change the flags.
Examples
CLREX
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12.6.5 General Data Processing Instructions
The table below shows the data processing instructions.
Table 12-20.
116
Data Processing Instructions
Mnemonic
Description
ADC
Add with Carry
ADD
Add
ADDW
Add
AND
Logical AND
ASR
Arithmetic Shift Right
BIC
Bit Clear
CLZ
Count leading zeros
CMN
Compare Negative
CMP
Compare
EOR
Exclusive OR
LSL
Logical Shift Left
LSR
Logical Shift Right
MOV
Move
MOVT
Move Top
MOVW
Move 16-bit constant
MVN
Move NOT
ORN
Logical OR NOT
ORR
Logical OR
RBIT
Reverse Bits
REV
Reverse byte order in a word
REV16
Reverse byte order in each halfword
REVSH
Reverse byte order in bottom halfword and sign extend
ROR
Rotate Right
RRX
Rotate Right with Extend
RSB
Reverse Subtract
SADD16
Signed Add 16
SADD8
Signed Add 8
SASX
Signed Add and Subtract with Exchange
SSAX
Signed Subtract and Add with Exchange
SBC
Subtract with Carry
SHADD16
Signed Halving Add 16
SHADD8
Signed Halving Add 8
SHASX
Signed Halving Add and Subtract with Exchange
SHSAX
Signed Halving Subtract and Add with Exchange
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Table 12-20.
Data Processing Instructions (Continued)
Mnemonic
Description
SHSUB16
Signed Halving Subtract 16
SHSUB8
Signed Halving Subtract 8
SSUB16
Signed Subtract 16
SSUB8
Signed Subtract 8
SUB
Subtract
SUBW
Subtract
TEQ
Test Equivalence
TST
Test
UADD16
Unsigned Add 16
UADD8
Unsigned Add 8
UASX
Unsigned Add and Subtract with Exchange
USAX
Unsigned Subtract and Add with Exchange
UHADD16
Unsigned Halving Add 16
UHADD8
Unsigned Halving Add 8
UHASX
Unsigned Halving Add and Subtract with Exchange
UHSAX
Unsigned Halving Subtract and Add with Exchange
UHSUB16
Unsigned Halving Subtract 16
UHSUB8
Unsigned Halving Subtract 8
USAD8
Unsigned Sum of Absolute Differences
USADA8
Unsigned Sum of Absolute Differences and Accumulate
USUB16
Unsigned Subtract 16
USUB8
Unsigned Subtract 8
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12.6.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
; ADD and SUB only
where:
op
is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see “Conditional Execution”.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options.
imm12
is any value in the range 0–4095.
Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is
reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide
range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see “Multiword arithmetic examples” below.
See also “ADR”.
Note:
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses
the imm12 operand.
Restrictions
In these instructions:
Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
118
̶
Rn must also be SP
̶
Any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
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Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
̶
The user must not specify the S suffix
̶
Rm must not be PC and must not be SP
̶
If the instruction is conditional, it must be the last instruction in the IT block
With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only
with the additional restrictions:
̶
The user must not specify the S suffix
̶
The second operand must be a constant in the range 0 to 4095.
̶
Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00
before performing the calculation, making the base address for the calculation word-aligned.
̶
Note: To generate the address of an instruction, the constant based on the value of the PC must be
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the
PC, because the assembler automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition Flags
If S is specified, these instructions update the N, Z, C and V flags according to the result.
Examples
ADD
SUBS
RSB
ADCHI
R2, R1, R3
R8, R6, #240
R4, R4, #1280
R11, R0, R3
;
;
;
;
Sets the flags on the result
Subtracts contents of R4 from 1280
Only executed if C flag set and Z
flag clear.
Multiword Arithmetic Examples
The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit
integer contained in R0 and R1, and place the result in R4 and R5.
64-bit Addition Example
ADDS
R4, R0, R2
ADC
R5, R1, R3
; add the least significant words
; add the most significant words with carry
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a
96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the
result in R6, R9, and R2.
96-bit Subtraction Example
SUBS
R6, R6, R9
SBCS
R9, R2, R1
SBC
R2, R8, R11
; subtract the least significant words
; subtract the middle words with carry
; subtract the most significant words with carry
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12.6.5.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
Syntax
op{S}{cond} {Rd,} Rn, Operand2
where:
op
is one of:
AND logical AND.
ORR logical OR, or bit set.
EOR logical Exclusive OR.
BIC logical AND NOT, or bit clear.
ORN logical OR NOT.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see “Conditional Execution”.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options.
Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn
and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in
the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in
the value of Operand2.
Restrictions
Do not use SP and do not use PC.
Condition Flags
If S is specified, these instructions:
120
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
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Examples
AND
ORREQ
ANDS
EORS
BIC
ORN
ORNS
R9, R2, #0xFF00
R2, R0, R5
R9, R8, #0x19
R7, R11, #0x18181818
R0, R1, #0xab
R7, R11, R14, ROR #4
R7, R11, R14, ASR #32
12.6.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op
is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see “Conditional Execution”.
Rd
is the destination register.
Rm
is the register holding the value to be shifted.
Rs
is the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n
is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 0 to 31
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by
constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on
what result is generated by the different instructions, see “Shift Operations”.
Restrictions
Do not use SP and do not use PC.
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Condition Flags
If S is specified:
These instructions update the N and Z flags according to the result
The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations”.
Examples
ASR
SLS
LSR
ROR
RRX
R7,
R1,
R4,
R4,
R4,
R8,
R2,
R5,
R5,
R5
#9
#3
#6
R6
;
;
;
;
;
Arithmetic shift right by 9 bits
Logical shift left by 3 bits with flag update
Logical shift right by 6 bits
Rotate right by the value in the bottom byte of R6
Rotate right with extend.
12.6.5.4 CLZ
Count Leading Zeros.
Syntax
CLZ{cond} Rd, Rm
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rm
is the operand register.
Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result
value is 32 if no bits are set and zero if bit[31] is set.
Restrictions
Do not use SP and do not use PC.
Condition Flags
This instruction does not change the flags.
Examples
CLZ
CLZNE
122
R4,R9
R2,R3
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12.6.5.5 CMP and CMN
Compare and Compare Negative.
Syntax
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond
is an optional condition code, see “Conditional Execution”.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options.
Operation
These instructions compare the value in a register with Operand2. They update the condition flags on the result,
but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction,
except that the result is discarded.
Restrictions
In these instructions:
Do not use PC
Operand2 must not be SP.
Condition Flags
These instructions update the N, Z, C and V flags according to the result.
Examples
CMP
CMN
CMPGT
R2, R9
R0, #6400
SP, R7, LSL #2
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12.6.5.6 MOV and MVN
Move and Move NOT.
Syntax
MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see “Conditional Execution”.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options.
imm16
is any value in the range 0–65535.
Operation
The MOV instruction copies the value of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the
corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See “ASR, LSL, LSR, ROR, and RRX”.
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and
places the result into Rd.
The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 operand.
Restrictions
SP and PC only can be used in the MOV instruction, with the following restrictions:
The second operand must be a register without shift
The S suffix must not be specified.
When Rd is PC in a MOV instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX
instruction to branch for software portability to the ARM instruction set.
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Condition Flags
If S is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
MOVS
MOV
MOVS
MOV
MOV
MVNS
R11, #0x000B
R1, #0xFA05
R10, R12
R3, #23
R8, SP
R2, #0xF
;
;
;
;
;
;
;
Write value of 0x000B to R11, flags get updated
Write value of 0xFA05 to R1, flags are not updated
Write value in R12 to R10, flags get updated
Write value of 23 to R3
Write value of stack pointer to R8
Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
to the R2 and update flags.
12.6.5.7 MOVT
Move Top.
Syntax
MOVT{cond} Rd, #imm16
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
imm16
is a 16-bit immediate constant.
Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write
does not affect Rd[15:0].
The MOV, MOVT instruction pair enables to generate any 32-bit constant.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MOVT
R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged.
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12.6.5.8 REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
Syntax
op{cond} Rd, Rn
where:
op
is any of:
REV Reverse byte order in a word.
REV16 Reverse byte order in each halfword independently.
REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits.
RBIT Reverse the bit order in a 32-bit word.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the register holding the operand.
Operation
Use these instructions to change endianness of data:
REV converts either:
32-bit big-endian data into little-endian data
32-bit little-endian data into big-endian data.
REV16 converts either:
16-bit big-endian data into little-endian data
16-bit little-endian data into big-endian data.
REVSH converts either:
16-bit signed big-endian data into 32-bit signed little-endian data
16-bit signed little-endian data into 32-bit signed big-endian data.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
REV
REV16
REVSH
REVHS
RBIT
126
R3,
R0,
R0,
R3,
R7,
R7;
R0;
R5;
R7;
R8;
Reverse
Reverse
Reverse
Reverse
Reverse
byte order of value in R7 and write it to R3
byte order of each 16-bit halfword in R0
Signed Halfword
with Higher or Same condition
bit order of value in R8 and write the result to R7.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.9 SADD16 and SADD8
Signed Add 16 and Signed Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SADD16 Performs two 16-bit signed integer additions.
SADD8 Performs four 8-bit signed integer additions.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
Use these instructions to perform a halfword or byte add in parallel:
The SADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2.
Writes the result in the corresponding halfwords of the destination register.
The SADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
Writes the result in the corresponding bytes of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R1, R0
SADD8
;
;
;
R4, R0, R5 ;
;
Adds the halfwords in R0 to the corresponding
halfwords of R1 and writes to corresponding halfword
of R1.
Adds bytes of R0 to the corresponding byte in R5 and
writes to the corresponding byte in R4.
SAM4CM Series [DATASHEET]
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12.6.5.10 SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SHADD16 Signed Halving Add 16.
SHADD8 Signed Halving Add 8.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the
destination register:
The SHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2.
Shuffles the result by one bit to the right, halving the data.
3.
Writes the halfword results in the destination register.
The SHADDB8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2.
Shuffles the result by one bit to the right, halving the data.
3.
Writes the byte results in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0
SHADD8
128
;
;
;
R4, R0, R5 ;
;
Adds halfwords in R0 to corresponding halfword of R1
and writes halved result to corresponding halfword in
R1
Adds bytes of R0 to corresponding byte in R5 and
writes halved result to corresponding byte in R4.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.11 SHASX and SHSAX
Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
where:
op
is any of:
SHASX Add and Subtract with Exchange and Halving.
SHSAX Subtract and Add with Exchange and Halving.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2.
Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
3.
Subtracts the top halfword of the second operand from the bottom highword of the first operand.
4.
Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
The SHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2.
Writes the halfword result of the addition to the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
3.
Adds the bottom halfword of the first operand with the top halfword of the second operand.
4.
Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
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130
Examples
SHASX
R7, R4, R2
SHSAX
R0, R3, R5
;
;
;
;
;
;
;
;
Adds top halfword of R4 to bottom halfword of R2
and writes halved result to top halfword of R7
Subtracts top halfword of R2 from bottom halfword of
R4 and writes halved result to bottom halfword of R7
Subtracts bottom halfword of R5 from top halfword
of R3 and writes halved result to top halfword of R0
Adds top halfword of R5 to bottom halfword of R3 and
writes halved result to bottom halfword of R0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.12 SHSUB16 and SHSUB8
Signed Halving Subtract 16 and Signed Halving Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SHSUB16 Signed Halving Subtract 16.
SHSUB8 Signed Halving Subtract 8.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the
destination register:
The SHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfwords of the first operand.
2.
Shuffles the result by one bit to the right, halving the data.
3.
Writes the halved halfword results in the destination register.
The SHSUBB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand,
2.
Shuffles the result by one bit to the right, halving the data,
3.
Writes the corresponding signed byte results in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SHSUB16 R1, R0
SHSUB8
;
;
R4, R0, R5 ;
;
Subtracts halfwords in R0 from corresponding halfword
of R1 and writes to corresponding halfword of R1
Subtracts bytes of R0 from corresponding byte in R5,
and writes to corresponding byte in R4.
SAM4CM Series [DATASHEET]
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12.6.5.13 SSUB16 and SSUB8
Signed Subtract 16 and Signed Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SSUB16 Performs two 16-bit signed integer subtractions.
SSUB8 Performs four 8-bit signed integer subtractions.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to change endianness of data:
The SSUB16 instruction:
1. Subtracts each halfword from the second operand from the corresponding halfword of the first operand
2.
Writes the difference result of two signed halfwords in the corresponding halfword of the destination register.
The SSUB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand
2.
Writes the difference result of four signed bytes in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SSUB16 R1, R0
SSUB8
132
;
;
R4, R0, R5 ;
;
Subtracts halfwords in R0 from corresponding halfword
of R1 and writes to corresponding halfword of R1
Subtracts bytes of R5 from corresponding byte in
R0, and writes to corresponding byte of R4.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.14 SASX and SSAX
Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rm, Rn
where:
op
is any of:
SASX Signed Add and Subtract with Exchange.
SSAX Signed Subtract and Add with Exchange.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SASX instruction:
1. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
2.
Writes the signed result of the addition to the top halfword of the destination register.
3.
Subtracts the signed bottom halfword of the second operand from the top signed highword of the first
operand.
4.
Writes the signed result of the subtraction to the bottom halfword of the destination register.
The SSAX instruction:
1. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first
operand.
2.
Writes the signed result of the addition to the bottom halfword of the destination register.
3.
Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
4.
Writes the signed result of the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SASX
SSAX
R0, R4, R5 ;
;
;
;
R7, R3, R2 ;
;
;
;
Adds top halfword of R4 to bottom halfword of R5 and
writes to top halfword of R0
Subtracts bottom halfword of R5 from top halfword of R4
and writes to bottom halfword of R0
Subtracts top halfword of R2 from bottom halfword of R3
and writes to bottom halfword of R7
Adds top halfword of R3 with bottom halfword of R2 and
writes to top halfword of R7.
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12.6.5.15 TST and TEQ
Test bits and Test Equivalence.
Syntax
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where
cond
is an optional condition code, see “Conditional Execution”.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options.
Operation
These instructions test the value in a register against Operand2. They update the condition flags based on the
result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the
same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1
and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2.
This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the
sign bits of the two operands.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
TST
TEQEQ
134
R0, #0x3F8 ;
;
R10, R9
;
;
Perform bitwise AND of R0 value to 0x3F8,
APSR is updated but result is discarded
Conditionally test if value in R10 is equal to
value in R9, APSR is updated but result is discarded.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.16 UADD16 and UADD8
Unsigned Add 16 and Unsigned Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
UADD16 Performs two 16-bit unsigned integer additions.
UADD8 Performs four 8-bit unsigned integer additions.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
Use these instructions to add 16- and 8-bit unsigned data:
The UADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2.
Writes the unsigned result in the corresponding halfwords of the destination register.
The UADD16 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2.
Writes the unsigned result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
UADD16 R1, R0
UADD8
R4, R0, R5
;
;
;
;
Adds halfwords in R0 to corresponding halfword of R1,
writes to corresponding halfword of R1
Adds bytes of R0 to corresponding byte in R5 and
writes to corresponding byte in R4.
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12.6.5.17 UASX and USAX
Add and Subtract with Exchange and Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
UASX Add and Subtract with Exchange.
USAX Subtract and Add with Exchange.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The UASX instruction:
1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand.
2.
Writes the unsigned result from the subtraction to the bottom halfword of the destination register.
3.
Adds the top halfword of the first operand with the bottom halfword of the second operand.
4.
Writes the unsigned result of the addition to the top halfword of the destination register.
The USAX instruction:
1. Adds the bottom halfword of the first operand with the top halfword of the second operand.
2.
Writes the unsigned result of the addition to the bottom halfword of the destination register.
3.
Subtracts the bottom halfword of the second operand from the top halfword of the first operand.
4.
Writes the unsigned result from the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UASX
USAX
136
R0, R4, R5 ;
;
;
;
R7, R3, R2 ;
;
;
;
Adds top halfword of R4 to bottom halfword of R5 and
writes to top halfword of R0
Subtracts bottom halfword of R5 from top halfword of R0
and writes to bottom halfword of R0
Subtracts top halfword of R2 from bottom halfword of R3
and writes to bottom halfword of R7
Adds top halfword of R3 to bottom halfword of R2 and
writes to top halfword of R7.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.18 UHADD16 and UHADD8
Unsigned Halving Add 16 and Unsigned Halving Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
UHADD16 Unsigned Halving Add 16.
UHADD8 Unsigned Halving Add 8.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the register holding the first operand.
Rm
is the register holding the second operand.
Operation
Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the
destination register:
The UHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2.
Shuffles the halfword result by one bit to the right, halving the data.
3.
Writes the unsigned results to the corresponding halfword in the destination register.
The UHADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2.
Shuffles the byte result by one bit to the right, halving the data.
3.
Writes the unsigned results in the corresponding byte in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
UHADD16 R7, R3
UHADD8
R4, R0, R5
;
;
;
;
;
Adds halfwords in R7 to corresponding halfword of R3
and writes halved result to corresponding halfword
in R7
Adds bytes of R0 to corresponding byte in R5 and
writes halved result to corresponding byte in R4.
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12.6.5.19 UHASX and UHSAX
Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
UHASX Add and Subtract with Exchange and Halving.
UHSAX Subtract and Add with Exchange and Halving.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The UHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2.
Shifts the result by one bit to the right causing a divide by two, or halving.
3.
Writes the halfword result of the addition to the top halfword of the destination register.
4.
Subtracts the top halfword of the second operand from the bottom highword of the first operand.
5.
Shifts the result by one bit to the right causing a divide by two, or halving.
6.
Writes the halfword result of the division in the bottom halfword of the destination register.
The UHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2.
Shifts the result by one bit to the right causing a divide by two, or halving.
3.
Writes the halfword result of the subtraction in the top halfword of the destination register.
4.
Adds the bottom halfword of the first operand with the top halfword of the second operand.
5.
Shifts the result by one bit to the right causing a divide by two, or halving.
6.
Writes the halfword result of the addition to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UHASX
UHSAX
138
R7, R4, R2 ;
;
;
;
R0, R3, R5 ;
;
;
;
Adds top halfword of R4 with bottom halfword of R2
and writes halved result to top halfword of R7
Subtracts top halfword of R2 from bottom halfword of
R7 and writes halved result to bottom halfword of R7
Subtracts bottom halfword of R5 from top halfword of
R3 and writes halved result to top halfword of R0
Adds top halfword of R5 to bottom halfword of R3 and
writes halved result to bottom halfword of R0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.20 UHSUB16 and UHSUB8
Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
UHSUB16 Performs two unsigned 16-bit integer additions, halves the results,
and writes the results to the destination register.
UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and
writes the results to the destination register.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the
destination register:
The UHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfword of the first operand.
2.
Shuffles each halfword result to the right by one bit, halving the data.
3.
Writes each unsigned halfword result to the corresponding halfwords in the destination register.
The UHSUB8 instruction:
1. Subtracts each byte of second operand from the corresponding byte of the first operand.
2.
Shuffles each byte result by one bit to the right, halving the data.
3.
Writes the unsigned byte results to the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
UHSUB16 R1, R0
UHSUB8
R4, R0, R5
;
;
;
;
Subtracts halfwords in R0 from corresponding halfword of
R1 and writes halved result to corresponding halfword in R1
Subtracts bytes of R5 from corresponding byte in R0 and
writes halved result to corresponding byte in R4.
SAM4CM Series [DATASHEET]
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12.6.5.21 SEL
Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the
values of the GE flags.
Syntax
SEL{}{} {,} ,
where:
c, q
are standard assembler syntax fields.
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
The SEL instruction:
1. Reads the value of each bit of APSR.GE.
2.
Depending on the value of APSR.GE, assigns the destination register the value of either the first or second
operand register.
Restrictions
None.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R0, R1, R2
SEL
R0, R0, R3
140
; Set GE bits based on result
; Select bytes from R0 or R3, based on GE.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.5.22 USAD8
Unsigned Sum of Absolute Differences
Syntax
USAD8{cond}{Rd,} Rn, Rm
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
The USAD8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand
register.
2.
Adds the absolute values of the differences together.
3.
Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
USAD8 R1, R4, R0 ;
;
USAD8 R0, R5
;
;
Subtracts each byte in R0 from corresponding byte of R4
adds the differences and writes to R1
Subtracts bytes of R5 from corresponding byte in R0,
adds the differences and writes to R0.
SAM4CM Series [DATASHEET]
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12.6.5.23 USADA8
Unsigned Sum of Absolute Differences and Accumulate
Syntax
USADA8{cond}{Rd,} Rn, Rm, Ra
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Ra
is the register that contains the accumulation value.
Operation
The USADA8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand
register.
2.
Adds the unsigned absolute differences together.
3.
Adds the accumulation value to the sum of the absolute differences.
4.
Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
USADA8 R1, R0, R6
USADA8 R4, R0, R5, R2
142
;
;
;
;
Subtracts bytes in R0 from corresponding halfword of R1
adds differences, adds value of R6, writes to R1
Subtracts bytes of R5 from corresponding byte in R0
adds differences, adds value of R2 writes to R4.
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12.6.5.24 USUB16 and USUB8
Unsigned Subtract 16 and Unsigned Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where
op
is any of:
USUB16 Unsigned Subtract 16.
USUB8 Unsigned Subtract 8.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register:
The USUB16 instruction:
1. Subtracts each halfword from the second operand register from the corresponding halfword of the first
operand register.
2.
Writes the unsigned result in the corresponding halfwords of the destination register.
The USUB8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand
register.
2.
Writes the unsigned byte result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
USUB16 R1, R0
;
;
;
;
Subtracts halfwords in R0 from corresponding halfword of R1
and writes to corresponding halfword in R1USUB8 R4, R0, R5
Subtracts bytes of R5 from corresponding byte in R0 and
writes to the corresponding byte in R4.
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12.6.6 Multiply and Divide Instructions
The table below shows the multiply and divide instructions.
Table 12-21.
Multiply and Divide Instructions
Mnemonic
Description
MLA
Multiply with Accumulate, 32-bit result
MLS
Multiply and Subtract, 32-bit result
MUL
Multiply, 32-bit result
SDIV
Signed Divide
SMLA[B,T]
Signed Multiply Accumulate (halfwords)
SMLAD, SMLADX
Signed Multiply Accumulate Dual
SMLAL
Signed Multiply with Accumulate (32 × 32 + 64), 64-bit result
SMLAL[B,T]
Signed Multiply Accumulate Long (halfwords)
SMLALD, SMLALDX
Signed Multiply Accumulate Long Dual
SMLAW[B|T]
Signed Multiply Accumulate (word by halfword)
SMLSD
Signed Multiply Subtract Dual
SMLSLD
Signed Multiply Subtract Long Dual
SMMLA
Signed Most Significant Word Multiply Accumulate
SMMLS, SMMLSR
Signed Most Significant Word Multiply Subtract
SMUAD, SMUADX
Signed Dual Multiply Add
SMUL[B,T]
Signed Multiply (word by halfword)
SMMUL, SMMULR
Signed Most Significant Word Multiply
SMULL
Signed Multiply (32x32), 64-bit result
SMULWB, SMULWT
Signed Multiply (word by halfword)
SMUSD, SMUSDX
Signed Dual Multiply Subtract
UDIV
Unsigned Divide
UMAAL
Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result
UMLAL
Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result
UMULL
Unsigned Multiply (32 × 32), 64-bit result
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12.6.6.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result.
Syntax
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond
is an optional condition code, see “Conditional Execution”.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
of the operation, see “Conditional Execution”.
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm
are registers holding the values to be multiplied.
Ra
is a register holding the value to be added or subtracted from.
Operation
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in
Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least
significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and
places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or unsigned.
Restrictions
In these instructions, do not use SP and do not use PC.
If the S suffix is used with the MUL instruction:
Rd, Rn, and Rm must all be in the range R0 to R7
Rd must be the same as Rm
The cond suffix must not be used.
Condition Flags
If S is specified, the MUL instruction:
Updates the N and Z flags according to the result
Does not affect the C and V flags.
Examples
MUL
MLA
MULS
MULLT
MLS
R10, R2, R5
R10, R2, R1, R5
R0, R2, R2
R2, R3, R2
R4, R5, R6, R7
;
;
;
;
;
Multiply, R10
Multiply with
Multiply with
Conditionally
Multiply with
= R2 x R5
accumulate, R10 =
flag update, R0 =
multiply, R2 = R3
subtract, R4 = R7
(R2 x R1) + R5
R2 x R2
x R2
- (R5 x R6)
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12.6.6.2 UMULL, UMAAL, UMLAL
Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op
is one of:
UMULL Unsigned Long Multiply.
UMAAL Unsigned Long Multiply with Accumulate Accumulate.
UMLAL Unsigned Long Multiply, with Accumulate.
cond
is an optional condition code, see “Conditional Execution”.
RdHi, RdLo
are the destination registers. For UMAAL, UMLAL and UMLAL they also hold
the accumulating value.
Rn, Rm
are registers holding the first and second operands.
Operation
These instructions interpret the values from Rn and Rm as unsigned 32-bit integers.
The UMULL instruction:
Multiplies the two unsigned integers in the first and second operands.
Writes the least significant 32 bits of the result in RdLo.
Writes the most significant 32 bits of the result in RdHi.
The UMAAL instruction:
Multiplies the two unsigned 32-bit integers in the first and second operands.
Adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication.
Adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition.
Writes the top 32-bits of the result to RdHi.
Writes the lower 32-bits of the result to RdLo.
The UMLAL instruction:
Multiplies the two unsigned integers in the first and second operands.
Adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.
Writes the result back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL
R0, R4, R5, R6
UMAAL
R3, R6, R2, R7
UMLAL
R2, R1, R3, R5
146
;
;
;
;
;
Multiplies R5 and R6, writes the top 32 bits to R4
and the bottom 32 bits to R0
Multiplies R2 and R7, adds R6, adds R3, writes the
top 32 bits to R6, and the bottom 32 bits to R3
Multiplies R5 and R3, adds R1:R2, writes to R1:R2.
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12.6.6.3 SMLA and SMLAW
Signed Multiply Accumulate (halfwords).
Syntax
op{XY}{cond} Rd, Rn, Rm
op{Y}{cond} Rd, Rn, Rm, Ra
where:
op
is one of:
SMLA Signed Multiply Accumulate Long (halfwords).
X and Y specifies which half of the source registers Rn and Rm are used as the
first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used
SMLAW Signed Multiply Accumulate (word by halfword).
Y specifies which half of the source register Rm is used as the second multiply
operand.
If Y is T, then the top halfword, bits [31:16] of Rm is used.
If Y is B, then the bottom halfword, bits [15:0] of Rm is used.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm
are registers holding the values to be multiplied.
Ra
is a register holding the value to be added or subtracted from.
Operation
The SMALBB, SMLABT, SMLATB, SMLATT instructions:
Multiplies the specified signed halfword, top or bottom, values from Rn and Rm.
Adds the value in Ra to the resulting 32-bit product.
Writes the result of the multiplication and addition in Rd.
The non-specified halfwords of the source registers are ignored.
The SMLAWB and SMLAWT instructions:
Multiply the 32-bit signed values in Rn with:
̶
̶
The top signed halfword of Rm, T instruction suffix.
The bottom signed halfword of Rm, B instruction suffix.
Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product
Writes the result of the multiplication and addition in Rd.
The bottom 16 bits of the 48-bit product are ignored.
If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No
overflow can occur during the multiplication.
Restrictions
In these instructions, do not use SP and do not use PC.
Condition Flags
If an overflow is detected, the Q flag is set.
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Examples
SMLABB
SMLATB
SMLATT
SMLABT
SMLABT
SMLAWB
SMLAWT
148
R5, R6, R4, R1
;
;
R5, R6, R4, R1 ;
;
R5, R6, R4, R1 ;
;
R5, R6, R4, R1 ;
;
R4, R3, R2
;
;
R10, R2, R5, R3 ;
;
R10, R2, R1, R5 ;
;
Multiplies bottom halfwords of R6 and R4, adds
R1 and writes to R5
Multiplies top halfword of R6 with bottom halfword
of R4, adds R1 and writes to R5
Multiplies top halfwords of R6 and R4, adds
R1 and writes the sum to R5
Multiplies bottom halfword of R6 with top halfword
of R4, adds R1 and writes to R5
Multiplies bottom halfword of R4 with top halfword of
R3, adds R2 and writes to R4
Multiplies R2 with bottom halfword of R5, adds
R3 to the result and writes top 32-bits to R10
Multiplies R2 with top halfword of R1, adds R5
and writes top 32-bits to R10.
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12.6.6.4 SMLAD
Signed Multiply Accumulate Long Dual
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
;
where:
op
is one of:
SMLAD Signed Multiply Accumulate Dual.
SMLADX Signed Multiply Accumulate Dual Reverse.
X specifies which halfword of the source register Rn is used as the multiply
operand.
If X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register holding the values to be multiplied.
Rm
the second operand register.
Ra
is the accumulate value.
Operation
The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values. The SMLAD and
SMLADX instructions:
If X is not present, multiply the top signed halfword value in Rn with the top signed halfword of Rm and the
bottom signed halfword values in Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and
the bottom signed halfword values in Rn with the top signed halfword of Rm.
Add both multiplication results to the signed 32-bit value in Ra.
Writes the 32-bit signed result of the multiplication and addition to Rd.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SMLAD
R10, R2, R1, R5 ;
;
;
SMLALDX R0, R2, R4, R6 ;
;
;
;
Multiplies two halfword values in R2 with
corresponding halfwords in R1, adds R5 and
writes to R10
Multiplies top halfword of R2 with bottom
halfword of R4, multiplies bottom halfword of R2
with top halfword of R4, adds R6 and writes to
R0.
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12.6.6.5 SMLAL and SMLALD
Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate
Long Dual.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
op{XY}{cond} RdLo, RdHi, Rn, Rm
op{X}{cond} RdLo, RdHi, Rn, Rm
where:
op
is one of:
MLAL Signed Multiply Accumulate Long.
SMLAL Signed Multiply Accumulate Long (halfwords, X and Y).
X and Y specify which halfword of the source registers Rn and Rm are used as
the first and second multiply operand:
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMLALD Signed Multiply Accumulate Long Dual.
SMLALDX Signed Multiply Accumulate Long Dual Reversed.
If the X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond
is an optional condition code, see “Conditional Execution”.
RdHi, RdLo
are the destination registers.
RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer.
For SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD and SMLA
LDX, they also hold the accumulating value.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMLAL instruction:
Multiplies the two’s complement signed word values from Rn and Rm.
Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The SMLALBB, SMLALBT, SMLALTB and SMLALTT instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The non-specified halfwords of the source registers are ignored.
The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement
signed 16-bit integers. These instructions:
150
If X is not present, multiply the top signed halfword value of Rn with the top signed halfword of Rm and the
bottom signed halfword values of Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value of Rn with the bottom signed halfword of Rm and
the bottom signed halfword values of Rn with the top signed halfword of Rm.
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Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit
product.
Write the 64-bit product in RdLo and RdHi.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMLAL
R4, R5, R3, R8
SMLALBT
R2, R1, R6, R7
SMLALTB
R2, R1, R6, R7
SMLALD
R6, R8, R5, R1
SMLALDX
R6, R8, R5, R1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Multiplies R3 and R8, adds R5:R4 and writes to
R5:R4
Multiplies bottom halfword of R6 with top
halfword of R7, sign extends to 32-bit, adds
R1:R2 and writes to R1:R2
Multiplies top halfword of R6 with bottom
halfword of R7,sign extends to 32-bit, adds R1:R2
and writes to R1:R2
Multiplies top halfwords in R5 and R1 and bottom
halfwords of R5 and R1, adds R8:R6 and writes to
R8:R6
Multiplies top halfword in R5 with bottom
halfword of R1, and bottom halfword of R5 with
top halfword of R1, adds R8:R6 and writes to
R8:R6.
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12.6.6.6 SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
where:
op
is one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
SMLAW Signed Multiply Accumulate (word by halfword).
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Ra
is the register holding the accumulate value.
Operation
The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This
instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the signed accumulate value to the result of the subtraction.
Writes the result of the addition to the destination register.
The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords.
This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.
Writes the 64-bit result of the addition to the RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the
multiplications or subtraction.
For the Thumb instruction set, these instructions do not affect the condition code flags.
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Examples
SMLSD
R0, R4, R5, R6 ;
;
;
;
SMLSDX R1, R3, R2, R0 ;
;
;
;
SMLSLD R3, R6, R2, R7 ;
;
;
;
SMLSLDX R3, R6, R2, R7 ;
;
;
;
Multiplies bottom halfword of R4 with bottom
halfword of R5, multiplies top halfword of R4
with top halfword of R5, subtracts second from
first, adds R6, writes to R0
Multiplies bottom halfword of R3 with top
halfword of R2, multiplies top halfword of R3
with bottom halfword of R2, subtracts second from
first, adds R0, writes to R1
Multiplies bottom halfword of R6 with bottom
halfword of R2, multiplies top halfword of R6
with top halfword of R2, subtracts second from
first, adds R6:R3, writes to R6:R3
Multiplies bottom halfword of R6 with top
halfword of R2, multiplies top halfword of R6
with bottom halfword of R2, subtracts second from
first, adds R6:R3, writes to R6:R3.
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12.6.6.7 SMMLA and SMMLS
Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract
Syntax
op{R}{cond} Rd, Rn, Rm, Ra
where:
op
is one of:
SMMLA Signed Most Significant Word Multiply Accumulate.
SMMLS Signed Most Significant Word Multiply Subtract.
If the X is omitted, the multiplications are bottom × bottom and top × top.
R
is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second multiply operands.
Ra
is the register holding the accumulate value.
Operation
The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLA instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Adds the value of Ra to the signed extracted value.
Writes the result of the addition in Rd.
The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLS instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Subtracts the extracted value of the result from the value in Ra.
Writes the result of the subtraction in Rd.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
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Examples
SMMLA
R0, R4, R5, R6
SMMLAR R6, R2, R1, R4
SMMLSR R3, R6, R2, R7
SMMLS
R4, R5, R3, R8
;
;
;
;
;
;
;
;
Multiplies R4 and R5, extracts top
R6, truncates and writes to R0
Multiplies R2 and R1, extracts top
R4, rounds and writes to R6
Multiplies R6 and R2, extracts top
subtracts R7, rounds and writes to
Multiplies R5 and R3, extracts top
subtracts R8, truncates and writes
32 bits, adds
32 bits, adds
32 bits,
R3
32 bits,
to R4.
12.6.6.8 SMMUL
Signed Most Significant Word Multiply
Syntax
op{R}{cond} Rd, Rn, Rm
where:
op
is one of:
SMMUL Signed Most Significant Word Multiply.
R
is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The
SMMUL instruction:
Multiplies the values from Rn and Rm.
Optionally rounds the result, otherwise truncates the result.
Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction:
do not use SP and do not use PC.
Condition Flags
This instruction does not affect the condition code flags.
Examples
SMULL
SMULLR
R0, R4, R5
R6, R2
;
;
;
;
Multiplies
and writes
Multiplies
and writes
R4
to
R6
to
and R5, truncates top 32 bits
R0
and R2, rounds the top 32 bits
R6.
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12.6.6.9 SMUAD and SMUSD
Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax
op{X}{cond} Rd, Rn, Rm
where:
op
is one of:
SMUAD Signed Dual Multiply Add.
SMUADX Signed Dual Multiply Add Reversed.
SMUSD Signed Dual Multiply Subtract.
SMUSDX Signed Dual Multiply Subtract Reversed.
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each
operand. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Adds the two multiplication results together.
Writes the result of the addition to the destination register.
The SMUSD instruction interprets the values from the first and second operands as two’s complement signed
integers. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.
Writes the result of the subtraction to the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
Sets the Q flag if the addition overflows. The multiplications cannot overflow.
156
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Examples
SMUAD
R0, R4, R5
SMUADX
R3, R7, R4
SMUSD
R3, R6, R2
SMUSDX
R4, R5, R3
;
;
;
;
;
;
;
;
;
;
;
;
Multiplies bottom halfword of R4 with the bottom
halfword of R5, adds multiplication of top halfword
of R4 with top halfword of R5, writes to R0
Multiplies bottom halfword of R7 with top halfword
of R4, adds multiplication of top halfword of R7
with bottom halfword of R4, writes to R3
Multiplies bottom halfword of R4 with bottom halfword
of R6, subtracts multiplication of top halfword of R6
with top halfword of R3, writes to R3
Multiplies bottom halfword of R5 with top halfword of
R3, subtracts multiplication of top halfword of R5
with bottom halfword of R3, writes to R4.
12.6.6.10 SMUL and SMULW
Signed Multiply (halfwords) and Signed Multiply (word by halfword)
Syntax
op{XY}{cond} Rd,Rn, Rm
op{Y}{cond} Rd. Rn, Rm
For SMULXY only:
op
is one of:
SMUL{XY}
Signed Multiply (halfwords).
X and Y specify which halfword of the source registers Rn and Rm is used as
the first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0] of Rn is used.
If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot
tom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMULW{Y}
Signed Multiply (word by halfword).
Y specifies which halfword of the source register Rm is used as the second multiply operand.
If Y is B, then the bottom halfword (bits [15:0]) of Rm is used.
If Y is T, then the top halfword (bits [31:16]) of Rm is used.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMULBB, SMULTB, SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed
16-bit integers. These instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Writes the 32-bit result of the multiplication in Rd.
The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two
halfword 16-bit signed integers. These instructions:
Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.
Writes the signed most significant 32 bits of the 48-bit result in the destination register.
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Restrictions
In these instructions:
158
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Examples
SMULBT
R0, R4, R5
SMULBB
R0, R4, R5
SMULTT
R0, R4, R5
SMULTB
R0, R4, R5
SMULWT
R4, R5, R3
SMULWB
R4, R5, R3
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Multiplies the bottom halfword of R4 with the
top halfword of R5, multiplies results and
writes to R0
Multiplies the bottom halfword of R4 with the
bottom halfword of R5, multiplies results and
writes to R0
Multiplies the top halfword of R4 with the top
halfword of R5, multiplies results and writes
to R0
Multiplies the top halfword of R4 with the
bottom halfword of R5, multiplies results and
and writes to R0
Multiplies R5 with the top halfword of R3,
extracts top 32 bits and writes to R4
Multiplies R5 with the bottom halfword of R3,
extracts top 32 bits and writes to R4.
SAM4CM Series [DATASHEET]
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12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit
result.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op
is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
cond
is an optional condition code, see “Conditional Execution”.
RdHi, RdLo
are the destination registers. For UMLAL and SMLAL they also hold the accumulating value.
Rn, Rm
are registers holding the operands.
Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and
places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers,
adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to
RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the
result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result
back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL
SMLAL
R0, R4, R5, R6
R4, R5, R3, R8
; Unsigned (R4,R0) = R5 x R6
; Signed (R5,R4) = (R5,R4) + R3 x R8
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12.6.6.12 SDIV and UDIV
Signed Divide and Unsigned Divide.
Syntax
SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn
is the register holding the value to be divided.
Rm
is a register holding the divisor.
Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SDIV
UDIV
160
R0, R2, R4
R8, R8, R1
; Signed divide, R0 = R2/R4
; Unsigned divide, R8 = R8/R1
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.7 Saturating Instructions
The table below shows the saturating instructions.
Table 12-22.
Saturating Instructions
Mnemonic
Description
SSAT
Signed Saturate
SSAT16
Signed Saturate Halfword
USAT
Unsigned Saturate
USAT16
Unsigned Saturate Halfword
QADD
Saturating Add
QSUB
Saturating Subtract
QSUB16
Saturating Subtract 16
QASX
Saturating Add and Subtract with Exchange
QSAX
Saturating Subtract and Add with Exchange
QDADD
Saturating Double and Add
QDSUB
Saturating Double and Subtract
UQADD16
Unsigned Saturating Add 16
UQADD8
Unsigned Saturating Add 8
UQASX
Unsigned Saturating Add and Subtract with Exchange
UQSAX
Unsigned Saturating Subtract and Add with Exchange
UQSUB16
Unsigned Saturating Subtract 16
UQSUB8
Unsigned Saturating Subtract 8
For signed n-bit saturation, this means that:
If the value to be saturated is less than -2n-1, the result returned is -2n-1
If the value to be saturated is greater than 2n-1-1, the result returned is 2n-1-1
Otherwise, the result returned is the same as the value to be saturated.
For unsigned n-bit saturation, this means that:
If the value to be saturated is less than 0, the result returned is 0
If the value to be saturated is greater than 2n-1, the result returned is 2n-1
Otherwise, the result returned is the same as the value to be saturated.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, the
MSR instruction must be used; see “MSR”.
To read the state of the Q flag, the MRS instruction must be used; see “MRS”.
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12.6.7.1 SSAT and USAT
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.
Syntax
op{cond} Rd, #n, Rm {, shift #s}
where:
op
is one of:
SSAT Saturates a signed value to a signed range.
USAT Saturates a signed value to an unsigned range.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
n
specifies the bit position to saturate to:
n ranges from 1
n ranges from 0 to 31 for USAT.
to 32 for SSAT
Rm
is the register containing the value to saturate.
shift #s
is an optional shift applied to Rm before saturating. It must be one of the
following:
ASR #s
where s is in the range 1 to 31.
LSL #s
where s is in the range 0 to 31.
Operation
These instructions saturate to a signed or unsigned n-bit value.
The SSAT instruction applies the specified shift, then saturates to the signed range
-2n–1 ≤ x ≤ 2n–1-1.
The USAT instruction applies the specified shift, then saturates to the unsigned range 0 ≤ x ≤ 2n-1.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
162
SSAT
R7, #16, R7, LSL #4
USATNE
R0, #7, R5
;
;
;
;
;
Logical shift left value in R7 by 4, then
saturate it as a signed 16-bit value and
write it back to R7
Conditionally saturate value in R5 as an
unsigned 7 bit value and write it to R0.
SAM4CM Series [DATASHEET]
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12.6.7.2 SSAT16 and USAT16
Signed Saturate and Unsigned Saturate to any bit position for two halfwords.
Syntax
op{cond} Rd, #n, Rm
where:
op
is one of:
SSAT16 Saturates a signed halfword value to a signed range.
USAT16 Saturates a signed halfword value to an unsigned range.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
n
specifies the bit position to saturate to:
n ranges from 1
n ranges from 0 to 15 for USAT.
to 16 for SSAT
Rm
is the register containing the value to saturate.
Operation
The SSAT16 instruction:
Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two signed 16-bit halfwords to the destination register.
The USAT16 instruction:
Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two unsigned halfwords in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
SSAT16
USAT16NE
R7, #9, R2
R0, #13, R5
;
;
;
;
;
;
Saturates the top and bottom highwords of R2
as 9-bit values, writes to corresponding halfword
of R7
Conditionally saturates the top and bottom
halfwords of R5 as 13-bit values, writes to
corresponding halfword of R0.
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12.6.7.3 QADD and QSUB
Saturating Add and Saturating Subtract, signed.
Syntax
op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
QADD Saturating 32-bit add.
QADD8 Saturating four 8-bit integer additions.
QADD16 Saturating two 16-bit integer additions.
QSUB Saturating 32-bit subtraction.
QSUB8 Saturating four 8-bit integer subtraction.
QSUB16 Saturating two 16-bit integer subtraction.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
These instructions add or subtract two, four or eight values from the first and second operands and then writes a
signed saturated value in the destination register.
The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed
range -2n–1 ≤ x ≤ 2n–1-1, where x is given by the number of bits applied in the instruction, 32, 16 or 8.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit
and 16-bit QADD and QSUB instructions always leave the Q flag unchanged.
To clear the Q flag to 0, the MSR instruction must be used; see “MSR”.
To read the state of the Q flag, the MRS instruction must be used; see “MRS”.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
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Examples
QADD16
R7, R4, R2
QADD8
R3, R1, R6
QSUB16
R4, R2, R3
QSUB8
R4, R2, R5
;
;
;
;
;
;
;
;
;
;
;
;
Adds halfwords of R4 with corresponding halfword of
R2, saturates to 16 bits and writes to
corresponding halfword of R7
Adds bytes of R1 to the corresponding bytes of R6,
saturates to 8 bits and writes to corresponding
byte of R3
Subtracts halfwords of R3 from corresponding
halfword of R2, saturates to 16 bits, writes to
corresponding halfword of R4
Subtracts bytes of R5 from the corresponding byte
in R2, saturates to 8 bits, writes to corresponding
byte of R4.
12.6.7.4 QASX and QSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed.
Syntax
op{cond} {Rd}, Rm, Rn
where:
op
is one of:
QASX Add and Subtract with Exchange and Saturate.
QSAX Subtract and Add with Exchange and Saturate.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The QASX instruction:
1. Adds the top halfword of the source operand with the bottom halfword of the second operand.
2.
Subtracts the top halfword of the second operand from the bottom highword of the first operand.
3.
Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1,
where x equals 16, to the bottom halfword of the destination register.
4.
Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.
The QSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2.
Adds the bottom halfword of the source operand with the top halfword of the second operand.
3.
Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register.
4.
Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1,
where x equals 16, to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
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Examples
QASX
QSAX
166
R7, R4, R2 ;
;
;
;
;
R0, R3, R5 ;
;
;
;
Adds top halfword of R4 to bottom halfword of R2,
saturates to 16 bits, writes to top halfword of R7
Subtracts top highword of R2 from bottom halfword of
R4, saturates to 16 bits and writes to bottom halfword
of R7
Subtracts bottom halfword of R5 from top halfword of
R3, saturates to 16 bits, writes to top halfword of R0
Adds bottom halfword of R3 to top halfword of R5,
saturates to 16 bits, writes to bottom halfword of R0.
SAM4CM Series [DATASHEET]
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12.6.7.5 QDADD and QDSUB
Saturating Double and Add and Saturating Double and Subtract, signed.
Syntax
op{cond} {Rd}, Rm, Rn
where:
op
is one of:
QDADD Saturating Double and Add.
QDSUB Saturating Double and Subtract.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rm, Rn
are registers holding the first and second operands.
Operation
The QDADD instruction:
Doubles the second operand value.
Adds the result of the doubling to the signed saturated value in the first operand.
Writes the result to the destination register.
The QDSUB instruction:
Doubles the second operand value.
Subtracts the doubled value from the signed saturated value in the first operand.
Writes the result to the destination register.
Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range –
231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR.
Restrictions
Do not use SP and do not use PC.
Condition Flags
If saturation occurs, these instructions set the Q flag to 1.
Examples
QDADD
R7, R4, R2
QDSUB
R0, R3, R5
;
;
;
;
Doubles and saturates R4 to 32 bits, adds R2,
saturates to 32 bits, writes to R7
Subtracts R3 doubled and saturated to 32 bits
from R5, saturates to 32 bits, writes to R0.
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12.6.7.6 UQASX and UQSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned.
Syntax
op{cond} {Rd}, Rm, Rn
where:
type
is one of:
UQASX Add and Subtract with Exchange and Saturate.
UQSAX Subtract and Add with Exchange and Saturate.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The UQASX instruction:
1. Adds the bottom halfword of the source operand with the top halfword of the second operand.
2.
Subtracts the bottom halfword of the second operand from the top highword of the first operand.
3.
Saturates the results of the sum and writes a 16-bit unsigned integer in the range
0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.
4.
Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where
x equals 16, to the bottom halfword of the destination register.
The UQSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2.
Adds the bottom halfword of the first operand with the top halfword of the second operand.
3.
Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where
x equals 16, to the top halfword of the destination register.
4.
Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x
equals 16, to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQASX
R7, R4, R2
UQSAX
R0, R3, R5
168
;
;
;
;
;
;
;
;
Adds top halfword of R4 with bottom halfword of R2,
saturates to 16 bits, writes to top halfword of R7
Subtracts top halfword of R2 from bottom halfword of
R4, saturates to 16 bits, writes to bottom halfword of R7
Subtracts bottom halfword of R5 from top halfword of R3,
saturates to 16 bits, writes to top halfword of R0
Adds bottom halfword of R4 to top halfword of R5
saturates to 16 bits, writes to bottom halfword of R0.
SAM4CM Series [DATASHEET]
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12.6.7.7 UQADD and UQSUB
Saturating Add and Saturating Subtract Unsigned.
Syntax
op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
UQADD8 Saturating four unsigned 8-bit integer additions.
UQADD16 Saturating two unsigned 16-bit integer additions.
UDSUB8 Saturating four unsigned 8-bit integer subtractions.
UQSUB16 Saturating two unsigned 16-bit integer subtractions.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
These instructions add or subtract two or four values and then writes an unsigned saturated value in the
destination register.
The UQADD16 instruction:
Adds the respective top and bottom halfwords of the first and second operands.
Saturates the result of the additions for each halfword in the destination register to the unsigned range
0 ≤ x ≤ 216-1, where x is 16.
The UQADD8 instruction:
Adds each respective byte of the first and second operands.
Saturates the result of the addition for each byte in the destination register to the unsigned range 0 ≤ x ≤ 281, where x is 8.
The UQSUB16 instruction:
Subtracts both halfwords of the second operand from the respective halfwords of the first operand.
Saturates the result of the differences in the destination register to the unsigned range 0 ≤ x ≤ 216-1, where x
is 16.
The UQSUB8 instructions:
Subtracts the respective bytes of the second operand from the respective bytes of the first operand.
Saturates the results of the differences for each byte in the destination register to the unsigned range
0 ≤ x ≤ 28-1, where x is 8.
Restrictions
Do not use SP and do not use PC.
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Condition Flags
These instructions do not affect the condition code flags.
Examples
UQADD16
R7, R4, R2
UQADD8
R4, R2, R5
UQSUB16
R6, R3, R0
UQSUB8
R1, R5, R6
170
;
;
;
;
;
;
;
;
;
Adds halfwords in R4 to corresponding halfword in R2,
saturates to 16 bits, writes to corresponding halfword of R7
Adds bytes of R2 to corresponding byte of R5, saturates
to 8 bits, writes to corresponding bytes of R4
Subtracts halfwords in R0 from corresponding halfword
in R3, saturates to 16 bits, writes to corresponding
halfword in R6
Subtracts bytes in R6 from corresponding byte of R5,
saturates to 8 bits, writes to corresponding byte of R1.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
12.6.8 Packing and Unpacking Instructions
The table below shows the instructions that operate on packing and unpacking data.
Table 12-23.
Packing and Unpacking Instructions
Mnemonic
Description
PKH
Pack Halfword
SXTAB
Extend 8 bits to 32 and add
SXTAB16
Dual extend 8 bits to 16 and add
SXTAH
Extend 16 bits to 32 and add
SXTB
Sign extend a byte
SXTB16
Dual extend 8 bits to 16 and add
SXTH
Sign extend a halfword
UXTAB
Extend 8 bits to 32 and add
UXTAB16
Dual extend 8 bits to 16 and add
UXTAH
Extend 16 bits to 32 and add
UXTB
Zero extend a byte
UXTB16
Dual zero extend 8 bits to 16 and add
UXTH
Zero extend a halfword
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12.6.8.1 PKHBT and PKHTB
Pack Halfword
Syntax
op{cond} {Rd}, Rn, Rm {, LSL #imm}
op{cond} {Rd}, Rn, Rm {, ASR #imm}
where:
op
is one of:
PKHBT Pack Halfword, bottom and top with shift.
PKHTB Pack Halfword, top and bottom with shift.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register
Rm
is the second operand register holding the value to be optionally shifted.
imm
is the shift length. The type of shift length depends on the instruction:
For PKHBT
LSL a left shift with a shift length from 1 to 31, 0 means no shift.
For PKHTB
ASR an arithmetic shift right with a shift length from 1 to 32,
a shift of 32-bits is encoded as 0b00000.
Operation
The PKHBT instruction:
1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination
register.
2.
If shifted, the shifted value of the second operand is written to the top halfword of the destination register.
The PKHTB instruction:
1. Writes the value of the top halfword of the first operand to the top halfword of the destination register.
2.
If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
PKHBT
R3, R4, R5 LSL #0
PKHTB
R4, R0, R2 ASR #1
172
;
;
;
;
;
;
Writes bottom halfword of R4 to bottom halfword of
R3, writes top halfword of R5, unshifted, to top
halfword of R3
Writes R2 shifted right by 1 bit to bottom halfword
of R4, and writes top halfword of R0 to top
halfword of R4.
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12.6.8.2 SXT and UXT
Sign extend and Zero extend.
Syntax
op{cond} {Rd,} Rm {, ROR #n}
op{cond} {Rd}, Rm {, ROR #n}
where:
op
is one of:
SXTB Sign extends an 8-bit value to a 32-bit value.
SXTH Sign extends a 16-bit value to a 32-bit value.
SXTB16 Sign extends two 8-bit values to two 16-bit values.
UXTB Zero extends an 8-bit value to a 32-bit value.
UXTH Zero extends a 16-bit value to a 32-bit value.
UXTB16 Zero extends two 8-bit values to two 16-bit values.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rm
is the register holding the value to extend.
ROR #n
is one of:
ROR #8 Value from Rm is rotated right 8 bits.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2.
Extract bits from the resulting value:
̶
SXTB extracts bits[7:0] and sign extends to 32 bits.
̶
UXTB extracts bits[7:0] and zero extends to 32 bits.
̶
SXTH extracts bits[15:0] and sign extends to 32 bits.
̶
UXTH extracts bits[15:0] and zero extends to 32 bits.
̶
SXTB16 extracts bits[7:0] and sign extends to 16 bits,
and extracts bits [23:16] and sign extends to 16 bits.
̶
UXTB16 extracts bits[7:0] and zero extends to 16 bits,
and extracts bits [23:16] and zero extends to 16 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH
R4, R6, ROR #16
UXTB
R3, R10
;
;
;
;
Rotates R6 right by 16 bits, obtains bottom halfword of
of result, sign extends to 32 bits and writes to R4
Extracts lowest byte of value in R10, zero extends, and
writes to R3.
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12.6.8.3 SXTA and UXTA
Signed and Unsigned Extend and Add
Syntax
op{cond} {Rd,} Rn, Rm {, ROR #n}
op{cond} {Rd,} Rn, Rm {, ROR #n}
where:
op
is one of:
SXTAB Sign extends an 8-bit value to a 32-bit value and add.
SXTAH Sign extends a 16-bit value to a 32-bit value and add.
SXTAB16 Sign extends two 8-bit values to two 16-bit values and add.
UXTAB Zero extends an 8-bit value to a 32-bit value and add.
UXTAH Zero extends a 16-bit value to a 32-bit value and add.
UXTAB16 Zero extends two 8-bit values to two 16-bit values and add.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the register holding the value to rotate and extend.
ROR #n
is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2.
Extract bits from the resulting value:
̶
SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits.
̶
̶
̶
̶
̶
3.
UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits.
SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits.
UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits.
SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits,
and extracts bits [23:16] from Rm and sign extends to 16 bits.
UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits,
and extracts bits [23:16] from Rm and zero extends to 16 bits.
Adds the signed or zero extended value to the word or corresponding halfword of Rn and writes the result in
Rd.
Restrictions
Do not use SP and do not use PC.
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Condition Flags
These instructions do not affect the flags.
Examples
SXTAH
UXTAB
R4, R8, R6, ROR #16 ;
;
;
R3, R4, R10
;
;
Rotates R6 right by 16 bits, obtains bottom
halfword, sign extends to 32 bits, adds
R8,and writes to R4
Extracts bottom byte of R10 and zero extends
to 32 bits, adds R4, and writes to R3.
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12.6.9 Bitfield Instructions
The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields.
Table 12-24.
176
Packing and Unpacking Instructions
Mnemonic
Description
BFC
Bit Field Clear
BFI
Bit Field Insert
SBFX
Signed Bit Field Extract
SXTB
Sign extend a byte
SXTH
Sign extend a halfword
UBFX
Unsigned Bit Field Extract
UXTB
Zero extend a byte
UXTH
Zero extend a halfword
SAM4CM Series [DATASHEET]
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12.6.9.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
Syntax
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the source register.
lsb
is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width
is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are
unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit
position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
BFC
BFI
R4, #8, #12
R9, R2, #8, #12
; Clear bit 8 to bit 19 (12 bits) of R4 to 0
; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2.
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12.6.9.2 SBFX and UBFX
Signed Bit Field Extract and Unsigned Bit Field Extract.
Syntax
SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rn
is the source register.
lsb
is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width
is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination
register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SBFX
UBFX
178
R0, R1, #20, #4
;
;
R8, R11, #9, #10 ;
;
Extract bit 20 to bit 23 (4 bits) from R1 and sign
extend to 32 bits and then write the result to R0.
Extract bit 9 to bit 18 (10 bits) from R11 and zero
extend to 32 bits and then write the result to R8.
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12.6.9.3 SXT and UXT
Sign extend and Zero extend.
Syntax
SXTextend{cond} {Rd,} Rm {, ROR #n}
UXTextend{cond} {Rd}, Rm {, ROR #n}
where:
extend
is one of:
B Extends an 8-bit value to a 32-bit value.
H Extends a 16-bit value to a 32-bit value.
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
Rm
is the register holding the value to extend.
ROR #n
is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2.
Extract bits from the resulting value:
̶
SXTB extracts bits[7:0] and sign extends to 32 bits.
̶
UXTB extracts bits[7:0] and zero extends to 32 bits.
̶
SXTH extracts bits[15:0] and sign extends to 32 bits.
̶
UXTH extracts bits[15:0] and zero extends to 32 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH
R4, R6, ROR #16
UXTB
R3, R10
;
;
;
;
;
Rotate R6 right by 16 bits, then obtain the lower
halfword of the result and then sign extend to
32 bits and write the result to R4.
Extract lowest byte of the value in R10 and zero
extend it, and write the result to R3.
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12.6.10 Branch and Control Instructions
The table below shows the branch and control instructions.
Table 12-25.
180
Branch and Control Instructions
Mnemonic
Description
B
Branch
BL
Branch with Link
BLX
Branch indirect with Link
BX
Branch indirect
CBNZ
Compare and Branch if Non Zero
CBZ
Compare and Branch if Zero
IT
If-Then
TBB
Table Branch Byte
TBH
Table Branch Halfword
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12.6.10.1 B, BL, BX, and BLX
Branch instructions.
Syntax
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B
is branch (immediate).
BL
is branch with link (immediate).
BX
is branch indirect (register).
BLX
is branch indirect with link (register).
cond
is an optional condition code, see “Conditional Execution”.
label
is a PC-relative expression. See “PC-relative Expressions”.
Rm
is a register that indicates an address to branch to. Bit[0] of the value in Rm
must be 1, but the address to branch to is created by changing bit[0] to 0.
Operation
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
The BL and BLX instructions write the address of the next instruction to LR (the link register, R14).
The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch
instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT”.
The table below shows the ranges for the various branch instructions.
Table 12-26.
Branch Ranges
Instruction
Branch Range
B label
−16 MB to +16 MB
Bcond label (outside IT block)
−1 MB to +1 MB
Bcond label (inside IT block)
−16 MB to +16 MB
BL{cond} label
−16 MB to +16 MB
BX{cond} Rm
Any value in register
BLX{cond} Rm
Any value in register
The .W suffix might be used to get the maximum branch range. See “Instruction Width Selection”.
Restrictions
The restrictions are:
Do not use PC in the BLX instruction
For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address
created by changing bit[0] to 0
When any of these instructions is inside an IT block, it must be the last instruction of the IT block.
Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer
branch range when it is inside an IT block.
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Condition Flags
These instructions do not change the flags.
Examples
182
B
BLE
B.W
BEQ
BEQ.W
BL
loopA
ng
target
target
target
funC
BX
BXNE
BLX
LR
R0
R0
;
;
;
;
;
;
;
;
;
;
Branch to loopA
Conditionally branch to label ng
Branch to target within 16MB range
Conditionally branch to target
Conditionally branch to target within 1MB
Branch with link (Call) to function funC, return address
stored in LR
Return from function call
Conditionally branch to address stored in R0
Branch with link and exchange (Call) to a address stored in R0.
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12.6.10.2 CBZ and CBNZ
Compare and Branch on Zero, Compare and Branch on Non-Zero.
Syntax
CBZ Rn, label
CBNZ Rn, label
where:
Rn
is the register holding the operand.
label
is the branch destination.
Operation
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of
instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP
Rn, #0
BEQ
label
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP
Rn, #0
BNE
label
Restrictions
The restrictions are:
Rn must be in the range of R0 to R7
The branch destination must be within 4 to 130 bytes after the instruction
These instructions must not be used inside an IT block.
Condition Flags
These instructions do not change the flags.
Examples
CBZ
CBNZ
R5, target
R0, target
; Forward branch if R5 is zero
; Forward branch if R0 is not zero
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12.6.10.3 IT
If-Then condition instruction.
Syntax
IT{x{y{z}}} cond
where:
x
specifies the condition switch for the second instruction in the IT block.
y
specifies the condition switch for the third instruction in the IT block.
z
specifies the condition switch for the fourth instruction in the IT block.
cond
specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT block can be either:
T
Then. Applies the condition cond to the instruction.
E
Else. Applies the inverse condition of cond to the instruction.
It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in
the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E.
Operation
The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some
of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT
block.
The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their
syntax.
The assembler might be able to generate the required IT instructions for conditional instructions automatically, so
that the user does not have to write them. See the assembler documentation for details.
A BKPT instruction in an IT block is always executed, even if its condition fails.
Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an
exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked
PSR.
Instructions designed for use for exception returns can be used as normal to return from the exception, and
execution of the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to
branch to an instruction in an IT block.
Restrictions
The following instructions are not permitted in an IT block:
IT
CBZ and CBNZ
CPSID and CPSIE.
Other restrictions when using an IT block are:
184
A branch or any instruction that modifies the PC must either be outside an IT block or must be the last
instruction inside the IT block. These are:
̶
ADD PC, PC, Rm
̶
MOV PC, Rm
̶
B, BL, BX, BLX
̶
Any LDM, LDR, or POP instruction that writes to the PC
̶
TBB and TBH
Do not branch to any instruction inside an IT block, except when returning from an exception handler
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All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside
an IT block but has a larger branch range if it is inside one
Each instruction inside the IT block must specify a condition code suffix that is either the same or logical
inverse as for the other instructions in the block.
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler
directives within them.
Condition Flags
This instruction does not change the flags.
Example
ITTE
ANDNE
ADDSNE
MOVEQ
NE
R0, R0, R1
R2, R2, #1
R2, R3
;
;
;
;
Next 3 instructions are conditional
ANDNE does not update condition flags
ADDSNE updates condition flags
Conditional move
CMP
R0, #9
ITE
ADDGT
ADDLE
GT
R1, R0, #55
R1, R0, #48
;
;
;
;
;
Convert R0 hex value (0 to 15) into ASCII
('0'-'9', 'A'-'F')
Next 2 instructions are conditional
Convert 0xA -> 'A'
Convert 0x0 -> '0'
IT
ADDGT
GT
R1, R1, #1
; IT block with only one conditional instruction
; Increment R1 conditionally
ITTEE
MOVEQ
ADDEQ
ANDNE
BNE.W
EQ
R0, R1
R2, R2, #10
R3, R3, #1
dloop
;
;
;
;
;
;
IT
ADD
NE
R0, R0, R1
; Next instruction is conditional
; Syntax error: no condition code used in IT block
Next 4 instructions are conditional
Conditional move
Conditional add
Conditional AND
Branch instruction can only be used in the last
instruction of an IT block
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12.6.10.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
Syntax
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn
is the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately
following the TBB or TBH instruction.
Rm
is the index register. This contains an index into the table. For halfword tables,
LSL #1 doubles the value in Rm to form the right offset into the table.
Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword
offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch
offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the
unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the
address of the byte immediately after the TBB or TBH instruction.
Restrictions
The restrictions are:
Rn must not be SP
Rm must not be SP and must not be PC
When any of these instructions is used inside an IT block, it must be the last instruction of the IT block.
Condition Flags
These instructions do not change the flags.
186
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Examples
ADR.W
TBB
R0, BranchTable_Byte
[R0, R1]
; R1 is the index, R0 is the base address of the
; branch table
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
DCB
0
; Case1 offset calculation
DCB
((Case2-Case1)/2) ; Case2 offset calculation
DCB
((Case3-Case1)/2) ; Case3 offset calculation
TBH
[PC, R1, LSL #1]
; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI
((CaseA - BranchTable_H)/2)
DCI
((CaseB - BranchTable_H)/2)
DCI
((CaseC - BranchTable_H)/2)
; CaseA offset calculation
; CaseB offset calculation
; CaseC offset calculation
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
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12.6.11 Floating-point Instructions
The table below shows the floating-point instructions.
These instructions are only available if the FPU is included, and enabled, in the system. See “Enabling the FPU”
for information about enabling the floating-point unit.
Table 12-27.
188
Floating-point Instructions
Mnemonic
Description
VABS
Floating-point Absolute
VADD
Floating-point Add
VCMP
Compare two floating-point registers, or one floating-point register and zero
VCMPE
Compare two floating-point registers, or one floating-point register and zero with Invalid
Operation check
VCVT
Convert between floating-point and integer
VCVT
Convert between floating-point and fixed point
VCVTR
Convert between floating-point and integer with rounding
VCVTB
Converts half-precision value to single-precision
VCVTT
Converts single-precision register to half-precision
VDIV
Floating-point Divide
VFMA
Floating-point Fused Multiply Accumulate
VFNMA
Floating-point Fused Negate Multiply Accumulate
VFMS
Floating-point Fused Multiply Subtract
VFNMS
Floating-point Fused Negate Multiply Subtract
VLDM
Load Multiple extension registers
VLDR
Loads an extension register from memory
VLMA
Floating-point Multiply Accumulate
VLMS
Floating-point Multiply Subtract
VMOV
Floating-point Move Immediate
VMOV
Floating-point Move Register
VMOV
Copy ARM core register to single precision
VMOV
Copy 2 ARM core registers to 2 single precision
VMOV
Copies between ARM core register to scalar
VMOV
Copies between Scalar to ARM core register
VMRS
Move to ARM core register from floating-point System Register
VMSR
Move to floating-point System Register from ARM Core register
VMUL
Multiply floating-point
VNEG
Floating-point negate
VNMLA
Floating-point multiply and add
VNMLS
Floating-point multiply and subtract
VNMUL
Floating-point multiply
VPOP
Pop extension registers
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Floating-point Instructions (Continued)
Mnemonic
Description
VPUSH
Push extension registers
VSQRT
Floating-point square root
VSTM
Store Multiple extension registers
VSTR
Stores an extension register to memory
VSUB
Floating-point Subtract
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12.6.11.1 VABS
Floating-point Absolute.
Syntax
VABS{cond}.F32 Sd, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd, Sm
are the destination floating-point value and the operand floating-point value.
Operation
This instruction:
1. Takes the absolute value of the operand floating-point register.
2.
Places the results in the destination floating-point register.
Restrictions
There are no restrictions.
Condition Flags
The floating-point instruction clears the sign bit.
Examples
VABS.F32 S4, S6
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12.6.11.2 VADD
Floating-point Add
Syntax
VADD{cond}.F32 {Sd,} Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd,
is the destination floating-point value.
Sn, Sm
are the operand floating-point values.
Operation
This instruction:
1. Adds the values in the two floating-point operand registers.
2.
Places the results in the destination floating-point register.
Restrictions
There are no restrictions.
Condition Flags
This instruction does not change the flags.
Examples
VADD.F32 S4, S6, S7
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12.6.11.3 VCMP, VCMPE
Compares two floating-point registers, or one floating-point register and zero.
Syntax
VCMP{E}{cond}.F32 Sd, Sm
VCMP{E}{cond}.F32 Sd, #0.0
where:
cond
is an optional condition code, see “Conditional Execution”.
E
If present, any NaN operand causes an Invalid Operation exception.
Otherwise, only a signaling NaN causes the exception.
Sd
is the floating-point operand to compare.
Sm
is the floating-point operand that is compared with.
Operation
This instruction:
1. Compares:
2.
̶
Two floating-point registers.
̶
One floating-point register and zero.
Writes the result to the FPSCR flags.
Restrictions
This instruction can optionally raise an Invalid Operation exception if either operand is any type of NaN. It always raises
an Invalid Operation exception if either operand is a signaling NaN.
Condition Flags
When this instruction writes the result to the FPSCR flags, the values are normally transferred to the ARM flags by a
subsequent VMRS instruction, see “VMRS”.
Examples
VCMP.F32
VCMP.F32
192
S4, #0.0
S4, S2
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12.6.11.4 VCVT, VCVTR between Floating-point and Integer
Converts a value in a register from floating-point to a 32-bit integer.
Syntax
VCVT{R}{cond}.Tm.F32 Sd, Sm
VCVT{cond}.F32.Tm Sd, Sm
where:
R
If R is specified, the operation uses the rounding mode specified by the FPSCR.
If R is omitted, the operation uses the Round towards Zero rounding mode.
cond
is an optional condition code, see “Conditional Execution”.
Tm
is the data type for the operand. It must be one of:
S32 signed 32-
U32
unsigned 32-bit value.
bit value.
Sd, Sm
are the destination register and the operand register.
Operation
These instructions:
1. Either
2.
̶
Convert a value in a register from floating-point value to a 32-bit integer.
̶
Convert from a 32-bit integer to floating-point value.
Place the result in a second register.
The floating-point to integer operation normally uses the Round towards Zero rounding mode, but can optionally
use the rounding mode specified by the FPSCR.
The integer to floating-point operation uses the rounding mode specified by the FPSCR.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.5 VCVT between Floating-point and Fixed-point
Converts a value in a register from floating-point to and from fixed-point.
Syntax
VCVT{cond}.Td.F32 Sd, Sd, #fbits
VCVT{cond}.F32.Td Sd, Sd, #fbits
where:
cond
is an optional condition code, see “Conditional Execution”.
Td
is the data type for the fixed-point number. It must be one of:
S16
U16
signed 16-bit value.
unsigned 16-bit value.
S32
U32
signed 32-bit value.
unsigned 32-bit value.
Sd
is the destination register and the operand register.
fbits
is the number of fraction bits in the fixed-point number:
If Td is S16 or U16, fbits must be in the range 0–16.
If Td is S32 or U32, fbits must be in the range 1–32.
Operation
These instructions:
1. Either
̶
̶
2.
Converts a value in a register from floating-point to fixed-point.
Converts a value in a register from fixed-point to floating-point.
Places the result in a second register.
The floating-point values are single-precision.
The fixed-point value can be 16-bit or 32-bit. Conversions from fixed-point values take their operand from the loworder bits of the source register and ignore any remaining bits.
Signed conversions to fixed-point values sign-extend the result value to the destination register width.
Unsigned conversions to fixed-point values zero-extend the result value to the destination register width.
The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floatingpoint operation uses the Round to Nearest rounding mode.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.6 VCVTB, VCVTT
Converts between a half-precision value and a single-precision value.
Syntax
VCVT{y}{cond}.F32.F16 Sd, Sm
VCVT{y}{cond}.F16.F32 Sd, Sm
where:
y
Specifies which half of the operand register Sm or destination register Sd is used for the
operand or destination:
- If y is B, then the bottom half, bits [15:0], of Sm or Sd is used.
- If y is T, then the top half, bits [31:16], of Sm or Sd is used.
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination register.
Sm
is the operand register.
Operation
This instruction with the.F16.32 suffix:
1. Converts the half-precision value in the top or bottom half of a single-precision. register to singleprecision.
2.
Writes the result to a single-precision register.
This instruction with the.F32.F16 suffix:
1. Converts the value in a single-precision register to half-precision.
2.
Writes the result into the top or bottom half of a single-precision register, preserving the other half of the
target register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.7 VDIV
Divides floating-point values.
Syntax
VDIV{cond}.F32 {Sd,} Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination register.
Sn, Sm
are the operand registers.
Operation
This instruction:
1. Divides one floating-point value by another floating-point value.
2.
Writes the result to the floating-point destination register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.8 VFMA, VFMS
Floating-point Fused Multiply Accumulate and Subtract.
Syntax
VFMA{cond}.F32 {Sd,} Sn, Sm
VFMS{cond}.F32 {Sd,} Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination register.
Sn, Sm
are the operand registers.
Operation
The VFMA instruction:
1. Multiplies the floating-point values in the operand registers.
2.
Accumulates the results into the destination register.
The result of the multiply is not rounded before the accumulation.
The VFMS instruction:
1. Negates the first operand register.
2.
Multiplies the floating-point values of the first and second operand registers.
3.
Adds the products to the destination register.
4.
Places the results in the destination register.
The result of the multiply is not rounded before the addition.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.9 VFNMA, VFNMS
Floating-point Fused Negate Multiply Accumulate and Subtract.
Syntax
VFNMA{cond}.F32 {Sd,} Sn, Sm
VFNMS{cond}.F32 {Sd,} Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination register.
Sn, Sm
are the operand registers.
Operation
The VFNMA instruction:
1. Negates the first floating-point operand register.
2.
Multiplies the first floating-point operand with second floating-point operand.
3.
Adds the negation of the floating -point destination register to the product
4.
Places the result into the destination register.
The result of the multiply is not rounded before the addition.
The VFNMS instruction:
1. Multiplies the first floating-point operand with second floating-point operand.
2.
Adds the negation of the floating-point value in the destination register to the product.
3.
Places the result in the destination register.
The result of the multiply is not rounded before the addition.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.10 VLDM
Floating-point Load Multiple
Syntax
VLDM{mode}{cond}{.size} Rn{!}, list
where:
mode
is the addressing mode:
- IA
Increment After. The consecutive addresses start at the address specified in Rn.
- DB
Decrement Before. The consecutive addresses end just before the
address specified in Rn.
cond
is an optional condition code, see “Conditional Execution”.
size
is an optional data size specifier.
Rn
is the base register. The SP can be used
!
is the command to the instruction to write a modified value back to Rn. This is
required if mode == DB, and is optional if mode == IA.
list
is the list of extension registers to be loaded, as a list of consecutively numbered
doubleword or singleword registers, separated by commas and surrounded by
brackets.
Operation
This instruction loads:
Multiple extension registers from consecutive memory locations using an address from an ARM core register
as the base address.
Restrictions
The restrictions are:
If size is present, it must be equal to the size in bits, 32 or 64, of the registers in list.
For the base address, the SP can be used.
In the ARM instruction set, if ! is not specified the PC can be used.
list must contain at least one register. If it contains doubleword registers, it must not contain more than 16
registers.
If using the Decrement Before addressing mode, the write back flag, !, must be appended to the base
register specification.
Condition Flags
These instructions do not change the flags.
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12.6.11.11 VLDR
Loads a single extension register from memory
Syntax
VLDR{cond}{.64}
VLDR{cond}{.64}
VLDR{cond}{.64}
VLDR{cond}{.32}
VLDR{cond}{.32}
VLDR{cond}{.32}
Dd,
Dd,
Dd,
Sd,
Sd,
Sd,
[Rn{#imm}]
label
[PC, #imm}]
[Rn {, #imm}]
label
[PC, #imm]
where:
cond
is an optional condition code, see “Conditional Execution”.
64, 32
are the optional data size specifiers.
Dd
is the destination register for a doubleword load.
Sd
is the destination register for a singleword load.
Rn
is the base register. The SP can be used.
imm
is the + or - immediate offset used to form the address.
Permitted address values are multiples of 4 in the range 0 to 1020.
label
is the label of the literal data item to be loaded.
Operation
This instruction:
Loads a single extension register from memory, using a base address from an ARM core register, with an
optional offset.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.12 VLMA, VLMS
Multiplies two floating-point values, and accumulates or subtracts the results.
Syntax
VLMA{cond}.F32 Sd, Sn, Sm
VLMS{cond}.F32 Sd, Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination floating-point value.
Sn, Sm
are the operand floating-point values.
Operation
The floating-point Multiply Accumulate instruction:
1. Multiplies two floating-point values.
2.
Adds the results to the destination floating-point value.
The floating-point Multiply Subtract instruction:
1. Multiplies two floating-point values.
2.
Subtracts the products from the destination floating-point value.
3.
Places the results in the destination register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.13 VMOV Immediate
Move floating-point Immediate
Syntax
VMOV{cond}.F32 Sd, #imm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the branch destination.
imm
is a floating-point constant.
Operation
This instruction copies a constant value to a floating-point register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.14 VMOV Register
Copies the contents of one register to another.
Syntax
VMOV{cond}.F64 Dd, Dm
VMOV{cond}.F32 Sd, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Dd
is the destination register, for a doubleword operation.
Dm
is the source register, for a doubleword operation.
Sd
is the destination register, for a singleword operation.
Sm
is the source register, for a singleword operation.
Operation
This instruction copies the contents of one floating-point register to another.
Restrictions
There are no restrictions
Condition Flags
These instructions do not change the flags.
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12.6.11.15 VMOV Scalar to ARM Core Register
Transfers one word of a doubleword floating-point register to an ARM core register.
Syntax
VMOV{cond} Rt, Dn[x]
where:
cond
is an optional condition code, see “Conditional Execution”.
Rt
is the destination ARM core register.
Dn
is the 64-bit doubleword register.
x
Specifies which half of the doubleword register to use:
- If x is 0, use lower half of doubleword register
- If x is 1, use upper half of doubleword register.
Operation
This instruction transfers:
One word from the upper or lower half of a doubleword floating-point register to an ARM core register.
Restrictions
Rt cannot be PC or SP.
Condition Flags
These instructions do not change the flags.
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12.6.11.16 VMOV ARM Core Register to Single Precision
Transfers a single-precision register to and from an ARM core register.
Syntax
VMOV{cond} Sn, Rt
VMOV{cond} Rt, Sn
where:
cond
is an optional condition code, see “Conditional Execution”.
Sn
is the single-precision floating-point register.
Rt
is the ARM core register.
Operation
This instruction transfers:
The contents of a single-precision register to an ARM core register.
The contents of an ARM core register to a single-precision register.
Restrictions
Rt cannot be PC or SP.
Condition Flags
These instructions do not change the flags.
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12.6.11.17 VMOV Two ARM Core Registers to Two Single Precision
Transfers two consecutively numbered single-precision registers to and from two ARM core registers.
Syntax
VMOV{cond} Sm, Sm1, Rt, Rt2
VMOV{cond} Rt, Rt2, Sm, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sm
is the first single-precision register.
Sm1
is the second single-precision register.
This is the next single-precision register after Sm.
Rt
is the ARM core register that Sm is transferred to or from.
Rt2
is the The ARM core register that Sm1 is transferred to or from.
Operation
This instruction transfers:
The contents of two consecutively numbered single-precision registers to two ARM core registers.
The contents of two ARM core registers to a pair of single-precision registers.
Restrictions
The restrictions are:
The floating-point registers must be contiguous, one after the other.
The ARM core registers do not have to be contiguous.
Rt cannot be PC or SP.
Condition Flags
These instructions do not change the flags.
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12.6.11.18 VMOV ARM Core Register to Scalar
Transfers one word to a floating-point register from an ARM core register.
Syntax
VMOV{cond}{.32} Dd[x], Rt
where:
cond
is an optional condition code, see “Conditional Execution”.
32
is an optional data size specifier.
Dd[x]
is the destination, where [x] defines which half of the doubleword is transferred,
as follows:
If x is 0, the lower half is extracted
If x is 1, the upper half is extracted.
Rt
is the source ARM core register.
Operation
This instruction transfers one word to the upper or lower half of a doubleword floating-point register from an ARM
core register.
Restrictions
Rt cannot be PC or SP.
Condition Flags
These instructions do not change the flags.
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12.6.11.19 VMRS
Move to ARM Core register from floating-point System Register.
Syntax
VMRS{cond} Rt, FPSCR
VMRS{cond} APSR_nzcv, FPSCR
where:
cond
is an optional condition code, see “Conditional Execution”.
Rt
is the destination ARM core register. This register can be R0–R14.
APSR_nzcv transfers floating-point flags to the APSR flags.
Operation
This instruction performs one of the following actions:
Copies the value of the FPSCR to a general-purpose register.
Copies the value of the FPSCR flag bits to the APSR N, Z, C, and V flags.
Restrictions
Rt cannot be PC or SP.
Condition Flags
These instructions optionally change the flags: N, Z, C, V
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12.6.11.20 VMSR
Move to floating-point System Register from ARM Core register.
Syntax
VMSR{cond} FPSCR, Rt
where:
cond
is an optional condition code, see “Conditional Execution”.
Rt
is the general-purpose register to be transferred to the FPSCR.
Operation
This instruction moves the value of a general-purpose register to the FPSCR. See “Floating-point Status Control
Register” for more information.
Restrictions
The restrictions are:
Rt cannot be PC or SP.
Condition Flags
This instruction updates the FPSCR.
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12.6.11.21 VMUL
Floating-point Multiply.
Syntax
VMUL{cond}.F32 {Sd,} Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination floating-point value.
Sn, Sm
are the operand floating-point values.
Operation
This instruction:
1. Multiplies two floating-point values.
2.
Places the results in the destination register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.22 VNEG
Floating-point Negate.
Syntax
VNEG{cond}.F32 Sd, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination floating-point value.
Sm
is the operand floating-point value.
Operation
This instruction:
1. Negates a floating-point value.
2.
Places the results in a second floating-point register.
The floating-point instruction inverts the sign bit.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.23 VNMLA, VNMLS, VNMUL
Floating-point multiply with negation followed by add or subtract.
Syntax
VNMLA{cond}.F32 Sd, Sn, Sm
VNMLS{cond}.F32 Sd, Sn, Sm
VNMUL{cond}.F32 {Sd,} Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination floating-point register.
Sn, Sm
are the operand floating-point registers.
Operation
The VNMLA instruction:
1. Multiplies two floating-point register values.
2.
Adds the negation of the floating-point value in the destination register to the negation of the product.
3.
Writes the result back to the destination register.
The VNMLS instruction:
1. Multiplies two floating-point register values.
2.
Adds the negation of the floating-point value in the destination register to the product.
3.
Writes the result back to the destination register.
The VNMUL instruction:
1. Multiplies together two floating-point register values.
2.
Writes the negation of the result to the destination register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.24 VPOP
Floating-point extension register Pop.
Syntax
VPOP{cond}{.size} list
where:
cond
is an optional condition code, see “Conditional Execution”.
size
is an optional data size specifier.
If present, it must be equal to the size in bits, 32 or 64, of the registers in list.
list
is the list of extension registers to be loaded, as a list of consecutively numbered
doubleword or singleword registers, separated by commas and surrounded by
brackets.
Operation
This instruction loads multiple consecutive extension registers from the stack.
Restrictions
The list must contain at least one register, and not more than sixteen registers.
Condition Flags
These instructions do not change the flags.
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12.6.11.25 VPUSH
Floating-point extension register Push.
Syntax
VPUSH{cond}{.size} list
where:
cond
is an optional condition code, see “Conditional Execution”.
size
is an optional data size specifier.
If present, it must be equal to the size in bits, 32 or 64, of the registers in list.
list
is a list of the extension registers to be stored, as a list of consecutively numbered
doubleword or singleword registers, separated by commas and sur
rounded by brackets.
Operation
This instruction:
Stores multiple consecutive extension registers to the stack.
Restrictions
The restrictions are:
list must contain at least one register, and not more than sixteen.
Condition Flags
These instructions do not change the flags.
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12.6.11.26 VSQRT
Floating-point Square Root.
Syntax
VSQRT{cond}.F32 Sd, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination floating-point value.
Sm
is the operand floating-point value.
Operation
This instruction:
Calculates the square root of the value in a floating-point register.
Writes the result to another floating-point register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.11.27 VSTM
Floating-point Store Multiple.
Syntax
VSTM{mode}{cond}{.size} Rn{!}, list
where:
mode
is the addressing mode:
- IA
Increment After. The consecutive addresses start at the address
specified in Rn.
This is the default and can be omitted.
- DB Decrement Before. The consecutive addresses end just before the
address specified in Rn.
cond
is an optional condition code, see “Conditional Execution”.
size
is an optional data size specifier.
If present, it must be equal to the size in bits, 32 or 64, of the registers in list.
Rn
is the base register. The SP can be used
!
is the function that causes the instruction to write a modified value back to Rn.
Required if mode == DB.
list
is a list of the extension registers to be stored, as a list of consecutively
numbered doubleword or singleword registers, separated by commas and
surrounded by brackets.
Operation
This instruction:
Stores multiple extension registers to consecutive memory locations using a base address from an ARM
core register.
Restrictions
The restrictions are:
list must contain at least one register.
If it contains doubleword registers it must not contain more than 16 registers.
Use of the PC as Rn is deprecated.
Condition Flags
These instructions do not change the flags.
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12.6.11.28 VSTR
Floating-point Store.
Syntax
VSTR{cond}{.32} Sd, [Rn{, #imm}]
VSTR{cond}{.64} Dd, [Rn{, #imm}]
where
cond
is an optional condition code, see “Conditional Execution”.
32, 64
are the optional data size specifiers.
Sd
is the source register for a singleword store.
Dd
is the source register for a doubleword store.
Rn
is the base register. The SP can be used.
imm
is the + or - immediate offset used to form the address. Values are multiples of 4
in the range 0–1020. imm can be omitted, meaning an offset of +0.
Operation
This instruction:
Stores a single extension register to memory, using an address from an ARM core register, with an optional
offset, defined in imm.
Restrictions
The restrictions are:
The use of PC for Rn is deprecated.
Condition Flags
These instructions do not change the flags.
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12.6.11.29 VSUB
Floating-point Subtract.
Syntax
VSUB{cond}.F32 {Sd,} Sn, Sm
where:
cond
is an optional condition code, see “Conditional Execution”.
Sd
is the destination floating-point value.
Sn, Sm
are the operand floating-point value.
Operation
This instruction:
1. Subtracts one floating-point value from another floating-point value.
2.
Places the results in the destination floating-point register.
Restrictions
There are no restrictions.
Condition Flags
These instructions do not change the flags.
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12.6.12 Miscellaneous Instructions
The table below shows the remaining Cortex-M4 instructions.
Table 12-28.
Miscellaneous Instructions
Mnemonic
Description
BKPT
Breakpoint
CPSID
Change Processor State, Disable Interrupts
CPSIE
Change Processor State, Enable Interrupts
DMB
Data Memory Barrier
DSB
Data Synchronization Barrier
ISB
Instruction Synchronization Barrier
MRS
Move from special register to register
MSR
Move from register to special register
NOP
No Operation
SEV
Send Event
SVC
Supervisor Call
WFE
Wait For Event
WFI
Wait For Interrupt
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12.6.12.1 BKPT
Breakpoint.
Syntax
BKPT #imm
where:
imm
is an expression evaluating to an integer in the range 0–255 (8-bit value).
Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system
state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional information about the
breakpoint.
The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition
specified by the IT instruction.
Condition Flags
This instruction does not change the flags.
Examples
BKPT 0xAB
Note:
; Breakpoint with immediate value set to 0xAB (debugger can
; extract the immediate value by locating it using the PC)
ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other
than Semi-hosting.
12.6.12.2 CPS
Change Processor State.
Syntax
CPSeffect iflags
where:
effect
is one of:
IE
Clears the special purpose register.
ID
Sets the special purpose register.
iflags
is a sequence of one or more flags:
i
Set or clear PRIMASK.
f
Set or clear FAULTMASK.
Operation
CPS changes the PRIMASK and FAULTMASK special register values. See “Exception Mask Registers” for more
information about these registers.
Restrictions
The restrictions are:
220
Use CPS only from privileged software, it has no effect if used in unprivileged software
CPS cannot be conditional and so must not be used inside an IT block.
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Condition Flags
This instruction does not change the condition flags.
Examples
CPSID
CPSID
CPSIE
CPSIE
i
f
i
f
;
;
;
;
Disable interrupts and configurable fault handlers (set PRIMASK)
Disable interrupts and all fault handlers (set FAULTMASK)
Enable interrupts and configurable fault handlers (clear PRIMASK)
Enable interrupts and fault handlers (clear FAULTMASK)
12.6.12.3 DMB
Data Memory Barrier.
Syntax
DMB{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order,
before the DMB instruction are completed before any explicit memory accesses that appear, in program order,
after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access
memory.
Condition Flags
This instruction does not change the flags.
Examples
DMB
; Data Memory Barrier
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12.6.12.4 DSB
Data Synchronization Barrier.
Syntax
DSB{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program
order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory
accesses before it complete.
Condition Flags
This instruction does not change the flags.
Examples
DSB ; Data Synchronisation Barrier
12.6.12.5 ISB
Instruction Synchronization Barrier.
Syntax
ISB{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions
following the ISB are fetched from memory again, after the ISB instruction has been completed.
Condition Flags
This instruction does not change the flags.
Examples
ISB
222
; Instruction Synchronisation Barrier
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12.6.12.6 MRS
Move the contents of a special register to a general-purpose register.
Syntax
MRS{cond} Rd, spec_reg
where:
cond
is an optional condition code, see “Conditional Execution”.
Rd
is the destination register.
spec_reg
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to
clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be saved, including
relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These
operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence.
Note:
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See “MSR”.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MRS
R0, PRIMASK ; Read PRIMASK value and write it to R0
12.6.12.7 MSR
Move the contents of a general-purpose register into the specified special register.
Syntax
MSR{cond} spec_reg, Rn
where:
cond
is an optional condition code, see “Conditional Execution”.
Rn
is the source register.
spec_reg
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
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Operation
The register access operation in MSR depends on the privilege level. Unprivileged software can only access the
APSR. See “Application Program Status Register”. Privileged software can access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
Note:
When the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
Rn is non-zero and the current BASEPRI value is 0
Rn is non-zero and less than the current BASEPRI value.
See “MRS”.
Restrictions
Rn must not be SP and must not be PC.
Condition Flags
This instruction updates the flags explicitly based on the value in Rn.
Examples
MSR
CONTROL, R1 ; Read R1 value and write it to the CONTROL register
12.6.12.8 NOP
No Operation.
Syntax
NOP{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the
pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
Condition Flags
This instruction does not change the flags.
Examples
NOP
224
; No operation
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12.6.12.9 SEV
Send Event.
Syntax
SEV{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register to 1, see “Power Management”.
Condition Flags
This instruction does not change the flags.
Examples
SEV ; Send Event
12.6.12.10 SVC
Supervisor Call.
Syntax
SVC{cond} #imm
where:
cond
is an optional condition code, see “Conditional Execution”.
imm
is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The SVC instruction causes the SVC exception.
imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service
is being requested.
Condition Flags
This instruction does not change the flags.
Examples
SVC
0x32
; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
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12.6.12.11 WFE
Wait For Event.
Syntax
WFE{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
WFE is a hint instruction.
If the event register is 0, WFE suspends execution until one of the following events occurs:
An exception, unless masked by the exception mask registers or the current priority level
An exception enters the Pending state, if SEVONPEND in the System Control Register is set
A Debug Entry request, if Debug is enabled
An event signaled by a peripheral or another processor in a multiprocessor system using the SEV
instruction.
If the event register is 1, WFE clears it to 0 and returns immediately.
For more information, see “Power Management”.
Condition Flags
This instruction does not change the flags.
Examples
WFE
; Wait for event
12.6.12.12 WFI
Wait for Interrupt.
Syntax
WFI{cond}
where:
cond
is an optional condition code, see “Conditional Execution”.
Operation
WFI is a hint instruction that suspends execution until one of the following events occurs:
An exception
A Debug Entry request, regardless of whether Debug is enabled.
Condition Flags
This instruction does not change the flags.
Examples
WFI ; Wait for interrupt
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12.7
Cortex-M4 Core Peripherals
12.7.1 Peripherals
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low
latency interrupt processing. See Section 12.8 ”Nested Vectored Interrupt Controller (NVIC)”.
System Control Block (SCB)
The System Control Block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions. See Section 12.9 ”System Control Block (SCB)”.
System Timer (SysTick)
The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System
(RTOS) tick timer or as a simple counter. See Section 12.10 ”System Timer (SysTick)”.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region.
See Section 12.11 ”Memory Protection Unit (MPU)”.
Floating-point Unit (FPU)
The Floating-point Unit (FPU) provides IEEE754-compliant operations on single-precision, 32-bit, floatingpoint values. See Section 12.12 ”Floating Point Unit (FPU)”.
12.7.2 Address Map
The address map of the Private peripheral bus (PPB) is given in the following table.
Table 12-29.
Core Peripheral Register Regions
Address
Core Peripheral
0xE000E008–0xE000E00F
System Control Block
0xE000E010–0xE000E01F
System Timer
0xE000E100–0xE000E4EF
Nested Vectored Interrupt Controller
0xE000ED00–0xE000ED3F
System control block
0xE000ED90–0xE000EDB8
Memory Protection Unit
0xE000EF00–0xE000EF03
Nested Vectored Interrupt Controller
0xE000EF30–0xE000EF44
Floating-point Unit
In register descriptions:
The required privilege gives the privilege level required to access the register, as follows:
̶
Privileged: Only privileged software can access the register.
̶
Unprivileged: Both unprivileged and privileged software can access the register.
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12.8
Nested Vectored Interrupt Controller (NVIC)
This section describes the NVIC and the registers it uses. The NVIC supports:
Up to 41 interrupts
A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so
level 0 is the highest interrupt priority.
Level detection of interrupt signals
Dynamic reprioritization of interrupts
Grouping of priority values into group priority and subpriority fields
Interrupt tail-chaining
An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction overhead. This provides low latency exception handling.
12.8.1 Level-sensitive Interrupts
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral
deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware
and Software Control of Interrupts”). For a level-sensitive interrupt, if the signal is not deasserted before the
processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR
again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.
12.8.1.1 Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
The NVIC detects a rising edge on the interrupt signal
A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending
Registers”, or to the NVIC_STIR to make an interrupt pending, see “Software Trigger Interrupt Register”.
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active.
Then:
̶
228
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to
inactive.
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not
change. Otherwise, the state of the interrupt changes to inactive.
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12.8.2 NVIC Design Hints and Tips
Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from
taking that interrupt.
Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector
table are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the
“Vector Table Offset Register”.
12.8.2.1 NVIC Programming Hints
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides
the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 12-30.
CMSIS Functions for NVIC Control
CMSIS Interrupt Control Function
Description
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
Set the priority grouping
void NVIC_EnableIRQ(IRQn_t IRQn)
Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn)
Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
Return true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn)
Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
Clear IRQn pending status
uint32_t NVIC_GetActive (IRQn_t IRQn)
Return the IRQ number of the active interrupt
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn)
Read priority of IRQn
void NVIC_SystemReset (void)
Reset the system
The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS
documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit
integers, so that:
̶
The array ISER[0] to ISER[1] corresponds to the registers ISER0–ISER1
̶
The array ICER[0] to ICER[1] corresponds to the registers ICER0–ICER1
̶
The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0–ISPR1
̶
The array ICPR[0] to ICPR[1] corresponds to the registers ICPR0–ICPR1
̶
The array IABR[0] to IABR[1] corresponds to the registers IABR0–IABR1
The Interrupt Priority Registers (IPR0–IPR10) provide an 8-bit priority field for each interrupt and each
register holds four priority fields.
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The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. Table 12-31
shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables
that have one bit per interrupt.
Table 12-31.
Mapping of Interrupts
CMSIS Array Elements (1)
Interrupts
Set-enable
Clear-enable
Set-pending
Clear-pending
Active Bit
0–31
ISER[0]
ICER[0]
ISPR[0]
ICPR[0]
IABR[0]
32–41
ISER[1]
ICER[1]
ISPR[1]
ICPR[1]
IABR[1]
Note:
230
1.
Each array element corresponds to a single NVIC register, for example the ICER[0] element corresponds to the
ICER0.
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12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface
Table 12-32.
Nested Vectored Interrupt Controller (NVIC) Register Mapping
Offset
Register
Name
Access
Reset
0xE000E100
Interrupt Set-enable Register 0
NVIC_ISER0
Read/Write
0x00000000
...
...
...
...
...
0xE000E11C
Interrupt Set-enable Register 7
NVIC_ISER7
Read/Write
0x00000000
0XE000E180
Interrupt Clear-enable Register 0
NVIC_ICER0
Read/Write
0x00000000
...
...
...
...
...
0xE000E19C
Interrupt Clear-enable Register 7
NVIC_ICER7
Read/Write
0x00000000
0XE000E200
Interrupt Set-pending Register 0
NVIC_ISPR0
Read/Write
0x00000000
...
...
...
...
...
0xE000E21C
Interrupt Set-pending Register 7
NVIC_ISPR7
Read/Write
0x00000000
0XE000E280
Interrupt Clear-pending Register 0
NVIC_ICPR0
Read/Write
0x00000000
...
...
...
...
...
0xE000E29C
Interrupt Clear-pending Register 7
NVIC_ICPR7
Read/Write
0x00000000
0xE000E300
Interrupt Active Bit Register 0
NVIC_IABR0
Read/Write
0x00000000
...
...
...
...
...
0xE000E31C
Interrupt Active Bit Register 7
NVIC_IABR7
Read/Write
0x00000000
0xE000E400
Interrupt Priority Register 0
NVIC_IPR0
Read/Write
0x00000000
...
...
...
...
...
26
Interrupt Priority Register 10
NVIC_IPR10
Read/Write
0x00000000
0xE000EF00
Software Trigger Interrupt Register
NVIC_STIR
Write-only
0x00000000
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12.8.3.1 Interrupt Set-enable Registers
Name:
NVIC_ISERx [x=0..7]
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SETENA
23
22
21
20
SETENA
15
14
13
12
SETENA
7
6
5
4
SETENA
These registers enable interrupts and show which interrupts are enabled.
• SETENA: Interrupt Set-enable
Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
Notes:
232
1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates
the interrupt, regardless of its priority.
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12.8.3.2 Interrupt Clear-enable Registers
Name:
NVIC_ICERx [x=0..7]
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CLRENA
23
22
21
20
CLRENA
15
14
13
12
CLRENA
7
6
5
4
CLRENA
These registers disable interrupts, and show which interrupts are enabled.
• CLRENA: Interrupt Clear-enable
Write:
0: No effect.
1: Disables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
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12.8.3.3 Interrupt Set-pending Registers
Name:
NVIC_ISPRx [x=0..7]
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SETPEND
23
22
21
20
SETPEND
15
14
13
12
SETPEND
7
6
5
4
SETPEND
These registers force interrupts into the pending state, and show which interrupts are pending.
• SETPEND: Interrupt Set-pending
Write:
0: No effect.
1: Changes the interrupt state to pending.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Notes:
234
1. Writing a 1 to an ISPR bit corresponding to an interrupt that is pending has no effect.
2. Writing a 1 to an ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to pending.
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12.8.3.4 Interrupt Clear-pending Registers
Name:
NVIC_ICPRx [x=0..7]
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CLRPEND
23
22
21
20
CLRPEND
15
14
13
12
CLRPEND
7
6
5
4
CLRPEND
These registers remove the pending state from interrupts, and show which interrupts are pending.
• CLRPEND: Interrupt Clear-pending
Write:
0: No effect.
1: Removes the pending state from an interrupt.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Note: Writing a 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
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12.8.3.5 Interrupt Active Bit Registers
Name:
NVIC_IABRx [x=0..7]
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ACTIVE
23
22
21
20
ACTIVE
15
14
13
12
ACTIVE
7
6
5
4
ACTIVE
These registers indicate which interrupts are active.
• ACTIVE: Interrupt Active Flags
0: Interrupt is not active.
1: Interrupt is active.
Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
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12.8.3.6 Interrupt Priority Registers
Name:
NVIC_IPRx [x=0..10]
Access:
Read/Write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PRI3
23
22
21
20
PRI2
15
14
13
12
PRI1
7
6
5
4
PRI0
The NVIC_IPR0–NVIC_IPR10 registers provide a 8-bit priority field for each interrupt. These registers are byte-accessible.
Each register holds four priority fields that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[40].
• PRI3: Priority (4m+3)
Priority, Byte Offset 3, refers to register bits [31:24].
• PRI2: Priority (4m+2)
Priority, Byte Offset 2, refers to register bits [23:16].
• PRI1: Priority (4m+1)
Priority, Byte Offset 1, refers to register bits [15:8].
• PRI0: Priority (4m)
Priority, Byte Offset 0, refers to register bits [7:0].
Notes:
1. Each priority field holds a priority value, 0–15. The lower the value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:4] of each field; bits[3:0] read as zero and ignore writes.
2. For more information about the IP[0] to IP[40] interrupt priority array, that provides the software view of the interrupt
priorities, see Table 12-30 “CMSIS Functions for NVIC Control” .
3. The corresponding IPR number n is given by n = m DIV 4.
4. The byte offset of the required Priority field in this register is m MOD 4.
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12.8.3.7 Software Trigger Interrupt Register
Name:
NVIC_STIR
Access:
Write-only
Reset:
0x000000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
INTID
7
6
5
4
3
2
1
0
INTID
Write to this register to generate an interrupt from the software.
• INTID: Interrupt ID
Interrupt ID of the interrupt to trigger, in the range 0–239. For example, a value of 0x03 specifies interrupt IRQ3.
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12.9
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions.
Ensure that the software uses aligned accesses of the correct size to access the system control block registers:
Except for the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it must use aligned word accesses
For the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it can use byte or aligned halfword or word
accesses.
The processor does not support unaligned accesses to system control block registers.
In a fault handler, to determine the true faulting address:
1. Read and save the MMFAR or SCB_BFAR value.
2.
Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The
SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1.
The software must follow this sequence because another higher priority exception might change the SCB_MMFAR
or SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault
might change the SCB_MMFAR or SCB_BFAR value.
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12.9.1 System Control Block (SCB) User Interface
Table 12-33.
System Control Block (SCB) Register Mapping
Offset
Register
Name
Access
Reset
0xE000E008
Auxiliary Control Register
SCB_ACTLR
Read/Write
0x00000000
0xE000ED00
CPUID Base Register
SCB_CPUID
Read-only
0x410FC240
0xE000ED04
Interrupt Control and State Register
SCB_ICSR
Read/Write(1)
0x00000000
0xE000ED08
Vector Table Offset Register
SCB_VTOR
Read/Write
0x00000000
0xE000ED0C
Application Interrupt and Reset Control Register
SCB_AIRCR
Read/Write
0xFA050000
0xE000ED10
System Control Register
SCB_SCR
Read/Write
0x00000000
0xE000ED14
Configuration and Control Register
SCB_CCR
Read/Write
0x00000200
0xE000ED18
System Handler Priority Register 1
SCB_SHPR1
Read/Write
0x00000000
0xE000ED1C
System Handler Priority Register 2
SCB_SHPR2
Read/Write
0x00000000
0xE000ED20
System Handler Priority Register 3
SCB_SHPR3
Read/Write
0x00000000
0xE000ED24
System Handler Control and State Register
SCB_SHCSR
Read/Write
0x00000000
(2)
Read/Write
0x00000000
0xE000ED28
Configurable Fault Status Register
SCB_CFSR
0xE000ED2C
HardFault Status Register
SCB_HFSR
Read/Write
0x00000000
0xE000ED34
MemManage Fault Address Register
SCB_MMFAR
Read/Write
Unknown
0xE000ED38
BusFault Address Register
SCB_BFAR
Read/Write
Unknown
0xE000ED3C
Auxiliary Fault Status Register
SCB_AFSR
Read/Write
0x00000000
Notes:
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1. See the register description for more information.
2. This register contains the subregisters: “MMFSR: Memory Management Fault Status Subregister” (0xE000ED28 - 8 bits),
“BFSR: Bus Fault Status Subregister” (0xE000ED29 - 8 bits), “UFSR: Usage Fault Status Subregister” (0xE000ED2A - 16
bits).
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12.9.1.1 Auxiliary Control Register
Name:
SCB_ACTLR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
DISOOFP
8
DISFPCA
7
–
6
–
5
–
4
–
3
–
2
DISFOLD
1
DISDEFWBUF
0
DISMCYCINT
The SCB_ACTLR provides disable bits for the following processor functions:
• IT folding
• Write buffer use for accesses to the default memory map
• Interruption of multi-cycle instructions.
By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally
require modification.
• DISOOFP: Disable Out Of Order Floating Point
Disables floating point instructions that complete out of order with respect to integer instructions.
• DISFPCA: Disable FPCA
Disables an automatic update of CONTROL.FPCA.
• DISFOLD: Disable Folding
When set to 1, disables the IT folding.
Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction.
This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must
avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding.
• DISDEFWBUF: Disable Default Write Buffer
When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise
but decreases the performance, as any store to memory must complete before the processor can execute the next
instruction.
This bit only affects write buffers implemented in the Cortex-M4 processor.
• DISMCYCINT: Disable Multiple Cycle Interruption
When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the interrupt
latency of the processor, as any LDM or STM must complete before the processor can stack the current state and enter the
interrupt handler.
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12.9.1.2 CPUID Base Register
Name:
SCB_CPUID
Access:
Read/Write
31
30
29
28
27
26
19
18
25
24
17
16
9
8
1
0
Implementer
23
22
21
20
Variant
15
14
Constant
13
12
11
10
3
2
PartNo
7
6
5
4
PartNo
Revision
The SCB_CPUID register contains the processor part number, version, and implementation information.
• Implementer: Implementer Code
0x41: ARM.
• Variant: Variant Number
It is the r value in the rnpn product revision identifier:
0x0: Revision 0.
• Constant: Reads as 0xF
Reads as 0xF.
• PartNo: Part Number of the Processor
0xC24 = Cortex-M4.
• Revision: Revision Number
It is the p value in the rnpn product revision identifier:
0x0: Patch 0.
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12.9.1.3 Interrupt Control and State Register
Name:
SCB_ICSR
Access:
Read/Write
31
NMIPENDSET
30
29
28
PENDSVSET
23
–
22
ISRPENDING
21
20
15
14
13
VECTPENDING
12
7
6
4
–
5
27
PENDSVCLR
26
PENDSTSET
19
18
VECTPENDING
25
PENDSTCLR
24
–
17
16
11
RETTOBASE
10
–
9
–
8
VECTACTIVE
3
2
1
0
VECTACTIVE
The SCB_ICSR provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and clearpending bits for the PendSV and SysTick exceptions.
It indicates:
• The exception number of the exception being processed, and whether there are preempted active exceptions,
• The exception number of the highest priority pending exception, and whether any interrupts are pending.
• NMIPENDSET: NMI Set-pending
Write:
PendSV set-pending bit.
Write:
0: No effect.
1: Changes NMI exception state to pending.
Read:
0: NMI exception is not pending.
1: NMI exception is pending.
As NMI is the highest-priority exception, the processor normally enters the NMI exception handler as soon as it registers a
write of 1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if
the NMI signal is reasserted while the processor is executing that handler.
• PENDSVSET: PendSV Set-pending
Write:
0: No effect.
1: Changes PendSV exception state to pending.
Read:
0: PendSV exception is not pending.
1: PendSV exception is pending.
Writing a 1 to this bit is the only way to set the PendSV exception state to pending.
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• PENDSVCLR: PendSV Clear-pending
Write:
0: No effect.
1: Removes the pending state from the PendSV exception.
• PENDSTSET: SysTick Exception Set-pending
Write:
0: No effect.
1: Changes SysTick exception state to pending.
Read:
0: SysTick exception is not pending.
1: SysTick exception is pending.
• PENDSTCLR: SysTick Exception Clear-pending
Write:
0: No effect.
1: Removes the pending state from the SysTick exception.
This bit is Write-only. On a register read, its value is Unknown.
• ISRPENDING: Interrupt Pending Flag (Excluding NMI and Faults)
0: Interrupt not pending.
1: Interrupt pending.
• VECTPENDING: Exception Number of the Highest Priority Pending Enabled Exception
0: No pending exceptions.
Nonzero: The exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
• RETTOBASE: Preempted Active Exceptions Present or Not
0: There are preempted active exceptions to execute.
1: There are no active exceptions, or the currently-executing exception is the only active exception.
• VECTACTIVE: Active Exception Number Contained
0: Thread mode.
Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See “Interrupt
Program Status Register”.
Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, ClearPending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register”.
Note: When the user writes to the SCB_ICSR, the effect is unpredictable if:
- Writing a 1 to the PENDSVSET bit and writing a 1 to the PENDSVCLR bit
- Writing a 1 to the PENDSTSET bit and writing a 1 to the PENDSTCLR bit.
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12.9.1.4 Vector Table Offset Register
Name:
SCB_VTOR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
–
2
–
1
–
0
–
TBLOFF
23
22
21
20
TBLOFF
15
14
13
12
TBLOFF
7
TBLOFF
6
–
5
–
4
–
The SCB_VTOR indicates the offset of the vector table base address from memory address 0x00000000.
• TBLOFF: Vector Table Base Offset
It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
Bit [29] determines whether the vector table is in the code or SRAM memory region:
0: Code.
1: SRAM.
It is sometimes called the TBLBASE bit.
Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the next
statement to give the information required for your implementation; the statement reminds the user of how to determine the
alignment requirement. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the
alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the alignment must be on a 64-word
boundary because the required table size is 37 words, and the next power of two is 64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
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12.9.1.5 Application Interrupt and Reset Control Register
Name:
SCB_AIRCR
Access:
Read/Write
31
30
29
28
27
VECTKEYSTAT/VECTKEY
26
25
24
23
22
21
20
19
VECTKEYSTAT/VECTKEY
18
17
16
15
ENDIANNESS
14
–
13
–
12
–
11
–
10
9
PRIGROUP
8
7
–
6
–
5
–
4
–
3
–
2
1
0
SYSRESETREQ VECTCLRACTIVE
VECTRESET
The SCB_AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset
control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores the
write.
• VECTKEYSTAT: Register Key (Read)
Reads as 0xFA05.
• VECTKEY: Register Key (Write)
Writes 0x5FA to VECTKEY, otherwise the write is ignored.
• ENDIANNESS: Data Endianness
0: Little-endian.
1: Big-endian.
• PRIGROUP: Interrupt Priority Grouping
This field determines the split of group priority from subpriority. It shows the position of the binary point that splits the PRI_n
fields in the Interrupt Priority Registers into separate group priority and subpriority fields. The table below shows how the
PRIGROUP value controls this split.
Interrupt Priority Level Value, PRI_N[7:0]
Number of
PRIGROUP
Binary Point (1)
Group Priority Bits
Subpriority Bits
Group Priorities
Subpriorities
0b000
bxxxxxxx.y
[7:1]
None
128
2
0b001
bxxxxxx.yy
[7:2]
[4:0]
64
4
0b010
bxxxxx.yyy
[7:3]
[4:0]
32
8
0b011
bxxxx.yyyy
[7:4]
[4:0]
16
16
0b100
bxxx.yyyyy
[7:5]
[4:0]
8
32
0b101
bxx.yyyyyy
[7:6]
[5:0]
4
64
0b110
bx.yyyyyyy
[7]
[6:0]
2
128
0b111
b.yyyyyyy
None
[7:0]
1
256
Note:
1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.
Determining preemption of an exception uses only the group priority field.
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• SYSRESETREQ: System Reset Request
0: No system reset request.
1: Asserts a signal to the outer system that requests a reset.
This is intended to force a large system reset of all major components except for debug. This bit reads as 0.
• VECTCLRACTIVE: Reserved for Debug use
This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable.
• VECTRESET: Reserved for Debug use
This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable.
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12.9.1.6 System Control Register
Name:
SCB_SCR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
SEVONPEND
3
–
2
SLEEPDEEP
1
SLEEPONEXIT
0
–
• SEVONPEND: Send Event on Pending Bit
0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded.
1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
When an event or an interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
• SLEEPDEEP: Sleep or Deep Sleep
Controls whether the processor uses sleep or deep sleep as its low power mode:
0: Sleep.
1: Deep sleep.
• SLEEPONEXIT: Sleep-on-exit
Indicates sleep-on-exit when returning from the Handler mode to the Thread mode:
0: Do not sleep when returning to Thread mode.
1: Enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
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12.9.1.7 Configuration and Control Register
Name:
SCB_CCR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
STKALIGN
8
BFHFNMIGN
7
6
5
4
3
2
1
0
–
–
–
DIV_0_TRP
UNALIGN_TRP
–
NONBASETHRDE
USERSETMPEND
NA
The SCB_CCR controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated by
FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the access to
the NVIC_STIR by unprivileged software (see “Software Trigger Interrupt Register”).
• STKALIGN: Stack Alignment
Indicates the stack alignment on exception entry:
0: 4-byte aligned.
1: 8-byte aligned.
On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the
exception, it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN: Bus Faults Ignored
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the
hard fault and FAULTMASK escalated handlers:
0: Data bus faults caused by load and store instructions cause a lock-up.
1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.
• DIV_0_TRP: Division by Zero Trap
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: Do not trap divide by 0.
1: Trap divide by 0.
When this bit is set to 0, a divide by zero returns a quotient of 0.
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• UNALIGN_TRP: Unaligned Access Trap
Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses.
1: Trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND: Unprivileged Software Access
Enables unprivileged software access to the NVIC_STIR, see “Software Trigger Interrupt Register”:
0: Disable.
1: Enable.
• NONBASETHRDENA: Thread Mode Enable
Indicates how the processor enters Thread mode:
0: The processor can enter the Thread mode only when no exception is active.
1: The processor can enter the Thread mode from any level under the control of an EXC_RETURN value, see “Exception
Return”.
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12.9.1.8 System Handler Priority Registers
The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. They are byte-accessible.
The system fault handlers and the priority field and register for each handler are:
Table 12-34.
System Fault Handler Priority Fields
Handler
Field
Memory management fault (MemManage)
PRI_4
Bus fault (BusFault)
PRI_5
Usage fault (UsageFault)
PRI_6
SVCall
PRI_11
PendSV
PRI_14
SysTick
PRI_15
Register Description
System Handler Priority Register 1
System Handler Priority Register 2
System Handler Priority Register 3
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and
ignore writes.
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12.9.1.9 System Handler Priority Register 1
Name:
SCB_SHPR1
Access:
Read/Write
31
–
30
–
29
–
28
–
23
22
21
20
27
–
26
–
25
–
24
–
19
18
17
16
11
10
9
8
3
2
1
0
PRI_6
15
14
13
12
PRI_5
7
6
5
4
PRI_4
• PRI_6: Priority
Priority of system handler 6, UsageFault.
• PRI_5: Priority
Priority of system handler 5, BusFault.
• PRI_4: Priority
Priority of system handler 4, MemManage.
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12.9.1.10 System Handler Priority Register 2
Name:
SCB_SHPR2
Access:
Read/Write
31
30
29
28
27
26
25
24
PRI_11
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
• PRI_11: Priority
Priority of system handler 11, SVCall.
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12.9.1.11 System Handler Priority Register 3
Name:
SCB_SHPR3
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
PRI_15
23
22
21
20
PRI_14
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
• PRI_15: Priority
Priority of system handler 15, SysTick exception.
• PRI_14: Priority
Priority of system handler 14, PendSV.
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12.9.1.12 System Handler Control and State Register
Name:
SCB_SHCSR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
23
–
22
–
21
–
20
–
19
–
15
14
13
12
11
SVCALLPENDED
7
SVCALLACT
26
–
5
–
4
–
24
–
18
17
16
USGFAULTENA BUSFAULTENA MEMFAULTENA
BUSFAULTPEND MEMFAULTPEND USGFAULTPEND
SYSTICKACT
ED
ED
ED
6
–
25
–
3
USGFAULTACT
10
9
8
PENDSVACT
–
MONITORACT
2
–
1
0
BUSFAULTACT MEMFAULTACT
The SHCSR enables the system handlers, and indicates the pending status of the bus fault, memory management fault,
and SVC exceptions; it also indicates the active status of the system handlers.
• USGFAULTENA: Usage Fault Enable
0: Disables the exception.
1: Enables the exception.
• BUSFAULTENA: Bus Fault Enable
0: Disables the exception.
1: Enables the exception.
• MEMFAULTENA: Memory Management Fault Enable
0: Disables the exception.
1: Enables the exception.
• SVCALLPENDED: SVC Call Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• BUSFAULTPENDED: Bus Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
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• MEMFAULTPENDED: Memory Management Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• USGFAULTPENDED: Usage Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• SYSTICKACT: SysTick Exception Active
Read:
0: The exception is not active.
1: The exception is active.
Note: The user can write to these bits to change the active status of the exceptions.
- Caution: A software that changes the value of an active bit in this register without a correct adjustment to the stacked content
can cause the processor to generate a fault exception. Ensure that the software writing to this register retains and subsequently
restores the current active status.
- Caution: After enabling the system handlers, to change the value of a bit in this register, the user must use a read-modify-write
procedure to ensure that only the required bit is changed.
• PENDSVACT: PendSV Exception Active
0: The exception is not active.
1: The exception is active.
• MONITORACT: Debug Monitor Active
0: Debug monitor is not active.
1: Debug monitor is active.
• SVCALLACT: SVC Call Active
0: SVC call is not active.
1: SVC call is active.
• USGFAULTACT: Usage Fault Exception Active
0: Usage fault exception is not active.
1: Usage fault exception is active.
• BUSFAULTACT: Bus Fault Exception Active
0: Bus fault exception is not active.
1: Bus fault exception is active.
• MEMFAULTACT: Memory Management Fault Exception Active
0: Memory management fault exception is not active.
1: Memory management fault exception is active.
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If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault.
The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to
the active bits to perform a context switch that changes the current exception type.
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12.9.1.13 Configurable Fault Status Register
Name:
SCB_CFSR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
DIVBYZERO
24
UNALIGNED
23
–
22
–
21
–
20
–
19
NOCP
18
INVPC
17
INVSTATE
16
UNDEFINSTR
15
BFARVALID
14
–
13
LSPERR
12
STKERR
11
UNSTKERR
10
IMPRECISERR
9
PRECISERR
8
IBUSERR
7
MMARVALID
6
–
4
MSTKERR
3
MUNSTKERR
2
–
1
DACCVIOL
0
IACCVIOL
5
MLSPERR
• IACCVIOL: Instruction Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister”.
0: No instruction access violation fault.
1: The processor attempted an instruction fetch from a location that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not
written a fault address to the SCB_MMFAR.
• DACCVIOL: Data Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister”.
0: No data access violation fault.
1: The processor attempted a load or store at a location that does not permit the operation.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded
the SCB_MMFAR with the address of the attempted access.
• MUNSTKERR: Memory Manager Fault on Unstacking for a Return From Exception
This is part of “MMFSR: Memory Management Fault Status Subregister”.
0: No unstacking fault.
1: Unstack for an exception return has caused one or more access violations.
This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The processor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a
fault address to the SCB_MMFAR.
• MSTKERR: Memory Manager Fault on Stacking for Exception Entry
This is part of “MMFSR: Memory Management Fault Status Subregister”.
0: No stacking fault.
1: Stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor
has not written a fault address to SCB_MMFAR.
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• MLSPERR: MemManage During Lazy State Preservation
This is part of “MMFSR: Memory Management Fault Status Subregister”.
0: No MemManage fault occurred during the floating-point lazy state preservation.
1: A MemManage fault occurred during the floating-point lazy state preservation.
• MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag
This is part of “MMFSR: Memory Management Fault Status Subregister”.
0: The value in SCB_MMFAR is not a valid fault address.
1: SCB_MMFAR holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose SCB_MMFAR
value has been overwritten.
• IBUSERR: Instruction Bus Error
This is part of “BFSR: Bus Fault Status Subregister”.
0: No instruction bus error.
1: Instruction bus error.
The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it
attempts to issue the faulting instruction.
When the processor sets this bit to 1, it does not write a fault address to the BFAR.
• PRECISERR: Precise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister”.
0: No precise data bus error.
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused
the fault.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR.
• IMPRECISERR: Imprecise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister”.
0: No imprecise data bus error.
1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the
error.
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR.
This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault
priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects
that both this bit and one of the precise fault status bits are set to 1.
• UNSTKERR: Bus Fault on Unstacking for a Return From Exception
This is part of “BFSR: Bus Fault Status Subregister”.
0: No unstacking fault.
1: Unstack for an exception return has caused one or more bus faults.
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This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still
present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write
a fault address to the BFAR.
• STKERR: Bus Fault on Stacking for Exception Entry
This is part of “BFSR: Bus Fault Status Subregister”.
0: No stacking fault.
1: Stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the SCB_BFAR.
• LSPERR: Bus Error During Lazy Floating-point State Preservation
This is part of “BFSR: Bus Fault Status Subregister”.
0: No bus fault occurred during floating-point lazy state preservation
1: A bus fault occurred during floating-point lazy state preservation.
• BFARVALID: Bus Fault Address Register (BFAR) Valid flag
This is part of “BFSR: Bus Fault Status Subregister”.
0: The value in SCB_BFAR is not a valid fault address.
1: SCB_BFAR holds a valid fault address.
The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a
memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This
prevents problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten.
• UNDEFINSTR: Undefined Instruction Usage Fault
This is part of “UFSR: Usage Fault Status Subregister”.
0: No undefined instruction usage fault.
1: The processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
• INVSTATE: Invalid State Usage Fault
This is part of “UFSR: Usage Fault Status Subregister”.
0: No invalid state usage fault.
1: The processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal
use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
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• INVPC: Invalid PC Load Usage Fault
This is part of “UFSR: Usage Fault Status Subregister”. It is caused by an invalid PC load by EXC_RETURN:
0: No invalid PC load usage fault.
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC.
• NOCP: No Coprocessor Usage Fault
This is part of “UFSR: Usage Fault Status Subregister”. The processor does not support coprocessor instructions:
0: No usage fault caused by attempting to access a coprocessor.
1: The processor has attempted to access a coprocessor.
• UNALIGNED: Unaligned Access Usage Fault
This is part of “UFSR: Usage Fault Status Subregister”.
0: No unaligned access fault, or unaligned access trapping not enabled.
1: The processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR to 1. See “Configuration and
Control Register”. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
• DIVBYZERO: Divide by Zero Usage Fault
This is part of “UFSR: Usage Fault Status Subregister”.
0: No divide by zero fault, or divide by zero trapping not enabled.
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed
the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR to 1. See “Configuration and Control Register”.
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12.9.1.14 Configurable Fault Status Register (Byte Access)
Name:
SCB_CFSR (BYTE)
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
UFSR
23
22
21
20
UFSR
15
14
13
12
BFSR
7
6
5
4
MMFSR
• MMFSR: Memory Management Fault Status Subregister
The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section
12.9.1.13.
• BFSR: Bus Fault Status Subregister
The flags in the BFSR subregister indicate the cause of a bus access fault. See bitfield [14..8] description in Section
12.9.1.13.
• UFSR: Usage Fault Status Subregister
The flags in the UFSR subregister indicate the cause of a usage fault. See bitfield [31..15] description in Section 12.9.1.13.
Note: The UFSR bits are sticky. This means that as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing a 1 to that bit, or by a reset.
The SCB_CFSR indicates the cause of a memory management fault, bus fault, or usage fault. It is byte accessible. The
user can access the SCB_CFSR or its subregisters as follows:
• Access complete SCB_CFSR with a word access to 0xE000ED28
• Access MMFSR with a byte access to 0xE000ED28
• Access MMFSR and BFSR with a halfword access to 0xE000ED28
• Access BFSR with a byte access to 0xE000ED29
• Access UFSR with a halfword access to 0xE000ED2A.
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12.9.1.15 Hard Fault Status Register
Name:
SCB_HFSR
Access:
Read/Write
31
DEBUGEVT
30
FORCED
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
VECTTBL
0
–
The SCB_HFSR gives information about events that activate the hard fault handler. This register is read, write to clear.
This means that bits in the register read normally, but writing a 1 to any bit clears that bit to 0.
• DEBUGEVT: Reserved for Debug Use
When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable.
• FORCED: Forced Hard Fault
It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either
because of priority or because it is disabled:
0: No forced hard fault.
1: Forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL: Bus Fault on a Vector Table
It indicates a bus fault on a vector table read during an exception processing:
0: No bus fault on vector table read.
1: Bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
Note: The HFSR bits are sticky. This means that, as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing a 1 to that bit, or by a reset.
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12.9.1.16 MemManage Fault Address Register
Name:
SCB_MMFAR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDRESS
23
22
21
20
ADDRESS
15
14
13
12
ADDRESS
7
6
5
4
ADDRESS
The SCB_MMFAR contains the address of the location that generated a memory management fault.
• ADDRESS: Memory Management Fault Generation Location Address
When the MMARVALID bit of the MMFSR subregister is set to 1, this field holds the address of the location that generated
the memory management fault.
Notes:
264
1. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction
can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size.
2. Flags in the MMFSR subregister indicate the cause of the fault, and whether the value in the SCB_MMFAR is valid. See
“MMFSR: Memory Management Fault Status Subregister”.
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12.9.1.17 Bus Fault Address Register
Name:
SCB_BFAR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDRESS
23
22
21
20
ADDRESS
15
14
13
12
ADDRESS
7
6
5
4
ADDRESS
The SCB_BFAR contains the address of the location that generated a bus fault.
• ADDRESS: Bus Fault Generation Location Address
When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the
bus fault.
Notes:
1. When an unaligned access faults, the address in the SCB_BFAR is the one requested by the instruction, even if it is not the
address of the fault.
2. Flags in the BFSR indicate the cause of the fault, and whether the value in the SCB_BFAR is valid. See “BFSR: Bus Fault
Status Subregister”.
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12.10 System Timer (SysTick)
The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps
to) the value in the SYST_RVR on the next clock edge, then counts down on subsequent clocks.
When the processor is halted for debugging, the counter does not decrement.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick
counter stops.
Ensure that the software uses aligned word accesses to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the
SysTick counter is:
1. Program the reload value.
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2.
Clear the current value.
3.
Program the Control and Status register.
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12.10.1 System Timer (SysTick) User Interface
Table 12-35.
System Timer (SYST) Register Mapping
Offset
Register
Name
Access
Reset
0xE000E010
SysTick Control and Status Register
SYST_CSR
Read/Write
0x00000000
0xE000E014
SysTick Reload Value Register
SYST_RVR
Read/Write
Unknown
0xE000E018
SysTick Current Value Register
SYST_CVR
Read/Write
Unknown
0xE000E01C
SysTick Calibration Value Register
SYST_CALIB
Read-only
0x000030D4
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12.10.1.1 SysTick Control and Status Register
Name:
SYST_CSR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
COUNTFLAG
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
CLKSOURCE
1
TICKINT
0
ENABLE
The SysTick SYST_CSR enables the SysTick features.
• COUNTFLAG: Count Flag
Returns 1 if the timer counted to 0 since the last time this was read.
• CLKSOURCE: Clock Source
Indicates the clock source:
0: External Clock.
1: Processor Clock.
• TICKINT: SysTick Exception Request Enable
Enables a SysTick exception request:
0: Counting down to zero does not assert the SysTick exception request.
1: Counting down to zero asserts the SysTick exception request.
The software can use COUNTFLAG to determine if SysTick has ever counted to zero.
• ENABLE: Counter Enable
Enables the counter:
0: Counter disabled.
1: Counter enabled.
When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR and then counts down. On reaching
0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the
RELOAD value again, and begins counting.
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12.10.1.2 SysTick Reload Value Registers
Name:
SYST_RVR
Access:
Read/Write
31
–
30
–
29
–
28
–
23
22
21
20
27
–
26
–
25
–
24
–
19
18
17
16
11
10
9
8
3
2
1
0
RELOAD
15
14
13
12
RELOAD
7
6
5
4
RELOAD
The SYST_RVR specifies the start value to load into the SYST_CVR.
• RELOAD: SYST_CVR Load Value
Value to load into the SYST_CVR when the counter is enabled and when it reaches 0.
The RELOAD value can be any value in the range 0x00000001–0x00FFFFFF. A start value of 0 is possible, but has no
effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0.
The RELOAD value is calculated according to its use: For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD
to 99.
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12.10.1.3 SysTick Current Value Register
Name:
SYST_CVR
Access:
Read/Write
31
–
30
–
29
–
28
–
23
22
21
20
27
–
26
–
25
–
24
–
19
18
17
16
11
10
9
8
3
2
1
0
CURRENT
15
14
13
12
CURRENT
7
6
5
4
CURRENT
The SysTick SYST_CVR contains the current value of the SysTick counter.
• CURRENT: SysTick Counter Current Value
Reads return the current value of the SysTick counter.
A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
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12.10.1.4 SysTick Calibration Value Register
Name:
SYST_CALIB
Access:
Read/Write
31
NOREF
30
SKEW
29
–
28
–
23
22
21
20
27
–
26
–
25
–
24
–
19
18
17
16
11
10
9
8
3
2
1
0
TENMS
15
14
13
12
TENMS
7
6
5
4
TENMS
The SysTick SYST_CSR indicates the SysTick calibration properties.
• NOREF: No Reference Clock
It indicates whether the device provides a reference clock to the processor:
0: Reference clock provided.
1: No reference clock provided.
If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes.
• SKEW: TENMS Value Verification
It indicates whether the TENMS value is exact:
0: TENMS value is exact.
1: TENMS value is inexact, or not given.
An inexact TENMS value can affect the suitability of SysTick as a software real time clock.
• TENMS: Ten Milliseconds
The reload value for 10 ms (100 Hz) timing is subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
The TENMS field default value is 0x000030D4 (12500 decimal).
In order to achieve a 1 ms timebase on SystTick, the TENMS field must be programmed to a value corresponding to the
processor clock frequency (in kHz) divided by 8.
For example, for devices running the processor clock at 48 MHz, the TENMS field value must be 0x0001770
(48000 kHz/8).
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12.11 Memory Protection Unit (MPU)
The MPU divides the memory map into a number of regions, and defines the location, size, access permissions,
and memory attributes of each region. It supports:
Independent attribute settings for each region
Overlapping regions
Export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines:
Eight separate memory regions, 0–7
A background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the highest
number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps
region 7.
The background region has the same memory access attributes as the default memory map, but is accessible
from privileged software only.
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the
same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory
management fault. This causes a fault exception, and might cause the termination of the process in an OS
environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be
executed. Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes”).
Table 12-36 shows the possible MPU region attributes. These include Share ability and cache behavior attributes
that are not relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” for
guidelines for programming such an implementation.
Table 12-36.
Memory Attributes Summary
Memory Type
Shareability
Other Attributes
Description
Strongly-ordered
–
–
All accesses to Strongly-ordered memory occur in program order. All
Strongly-ordered regions are assumed to be shared.
Shared
–
Memory-mapped peripherals that several processors share.
Non-shared
–
Memory-mapped peripherals that only a single processor uses.
Shared
–
Normal memory that is shared between several processors.
Non-shared
–
Normal memory that only a single processor uses.
Device
Normal
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12.11.1 MPU Access Permission Attributes
This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and
XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of
memory without the required permissions, then the MPU generates a permission fault.
The table below shows the encodings for the TEX, C, B, and S access permission bits.
Table 12-37.
TEX
C
0
TEX, C, B, and S Encoding
B
S
(1)
0
x
1
x (1)
Memory Type
Shareability
Other Attributes
Strongly-ordered
Shareable
–
Device
Shareable
–
Normal
Not
shareable
0
0
b000
1
Shareable
0
Not
shareable
Outer and inner write-through. No
write allocate.
1
1
0
Normal
1
Shareable
0
Not
shareable
0
Normal
1
x (1)
Reserved encoding
–
0
x (1)
Implementation defined
attributes.
–
1
Not
shareable
0
1
Normal
1
Not
shareable
0
x (1)
Device
1
x (1)
Reserved encoding
–
(1)
Reserved encoding
–
x
(1)
x
0
b1BB
A
A
Normal
1
Note:
1.
Outer and inner write-back. Write and
read allocate.
Shareable
0
1
–
Shareable
1
b001
b010
Outer and inner write-back. No write
allocate.
Not
shareable
Nonshared Device.
–
Shareable
The MPU ignores the value of this bit.
Table 12-38 shows the cache policy for memory attribute encodings with a TEX value is in the range 4–7.
Table 12-38.
Cache Policy for Memory Attribute Encoding
Encoding, AA or BB
Corresponding Cache Policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate
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Table 12-39 shows the AP encodings that define the access permissions for privileged and unprivileged software.
Table 12-39.
AP Encoding
AP[2:0]
Privileged
Permissions
Unprivileged
Permissions
Description
000
No access
No access
All accesses generate a permission fault
001
RW
No access
Access from privileged software only
010
RW
RO
Writes by unprivileged software generate a permission
fault
011
RW
RW
Full access
100
Unpredictable
Unpredictable
Reserved
101
RO
No access
Reads by privileged software only
110
RO
RO
Read only, by privileged or unprivileged software
111
RO
RO
Read only, by privileged or unprivileged software
12.11.1.1 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management fault, see
“Exceptions and Interrupts”. The MMFSR indicates the cause of the fault. See “MMFSR: Memory Management
Fault Status Subregister” for more information.
12.11.1.2 Updating an MPU Region
To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASRs. Each register
can be programed separately, or a multiple-word write can be used to program all of these registers. MPU_RBAR
and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM instruction.
12.11.1.3 Updating an MPU Region Using Separate Words
Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
;
;
;
;
;
0xE000ED98, MPU region number register
Region Number
Region Base Address
Region Size and Enable
Region Attribute
Disable a region before writing new region settings to the MPU, if the region being changed was previously
enabled. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR
; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0]
; Region Number
BIC R2, R2, #1
; Disable
STRH R2, [R0, #0x8]
; Region Size and Enable
STR R4, [R0, #0x4]
; Region Base Address
STRH R3, [R0, #0xA]
; Region Attribute
ORR R2, #1
; Enable
STRH R2, [R0, #0x8]
; Region Size and Enable
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The software must use memory barrier instructions:
Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might
be affected by the change in MPU settings
After the MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering an exception
handler, or is followed by an exception return, because the exception entry and exception return mechanisms
cause memory barrier behavior.
The software does not need any memory barrier instructions during an MPU setup, because it accesses the MPU
through the PPB, which is a Strongly-Ordered memory region.
For example, if the user wants all of the memory access behavior to take effect immediately after the programming
sequence, a DSB instruction and an ISB instruction must be used. A DSB is required after changing MPU settings,
such as at the end of a context switch. An ISB is required if the code that programs the MPU region or regions is
entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking
an exception, then an ISB is not required.
12.11.1.4 Updating an MPU Region Using Multi-word Writes
The user can program directly using multi-word writes, depending on how the information is divided. Consider the
following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region Number, address, attribute, size and enable
This can be done in two words for pre-packed information. This means that the MPU_RBAR contains the required
region number and had the VALID bit set to 1. See “MPU Region Base Address Register”. Use this when the data
is statically packed, for example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPU_RBAR
; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and
; region number combined with VALID (bit 4) set to 1
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPU_RBAR
; 0xE000ED9C, MPU Region Base register
STM R0, {R1-R2}
; Region base address, region number and VALID bit,
; and Region Attribute, Size and Enable
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12.11.1.5 Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD
field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register”. The least
significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling
a subregion means another region overlapping the disabled range matches instead. If no other enabled region
overlaps the disabled subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be
set to 0x00, otherwise the MPU behavior is unpredictable.
12.11.1.6 Example of SRD Use
Two regions with the same base address overlap. Region 1 is 128 KB, and region 2 is 512 KB. To ensure the
attributes from region 1 apply to the first 128 KB region, set the SRD field for region 2 to b00000011 to disable the
first two subregions, as in Figure 12-13 below:
Figure 12-13. SRD Use
Region 2, with
subregions
Region 1
Base address of both regions
Offset from
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0
12.11.1.7 MPU Design Hints And Tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt
handlers might access.
Ensure the software uses aligned accesses of the correct size to access MPU registers:
Except for the MPU_RASR, it must use aligned word accesses
For the MPU_RASR, it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent
any previous region settings from affecting the new MPU setup.
MPU Configuration for a Microcontroller
Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU
as follows:
Table 12-40.
276
Memory Region Attributes for a Microcontroller
Memory Region
TEX
C
B
S
Memory Type and Attributes
Flash memory
b000
1
0
0
Normal memory, non-shareable, write-through
Internal SRAM
b000
1
0
1
Normal memory, shareable, write-through
External SRAM
b000
1
1
1
Normal memory, shareable, write-back, write-allocate
Peripherals
b000
0
1
1
Device memory, shareable
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In most microcontroller implementations, the shareability and cache policy attributes do not affect the system
behavior. However, using these settings for the MPU regions can make the application code more portable. The
values given are for typical situations. In special systems, such as multiprocessor designs or designs with a
separate DMA engine, the shareability attribute might be important. In these cases, refer to the recommendations
of the memory device manufacturer.
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12.11.2 Memory Protection Unit (MPU) User Interface
Table 12-41.
Memory Protection Unit (MPU) Register Mapping
Offset
Register
Name
Access
Reset
0xE000ED90
MPU Type Register
MPU_TYPE
Read-only
0x00000800
0xE000ED94
MPU Control Register
MPU_CTRL
Read/Write
0x00000000
0xE000ED98
MPU Region Number Register
MPU_RNR
Read/Write
0x00000000
0xE000ED9C
MPU Region Base Address Register
MPU_RBAR
Read/Write
0x00000000
0xE000EDA0
MPU Region Attribute and Size Register
MPU_RASR
Read/Write
0x00000000
0xE000EDA4
MPU Region Base Address Register Alias 1
MPU_RBAR_A1
Read/Write
0x00000000
0xE000EDA8
MPU Region Attribute and Size Register Alias 1
MPU_RASR_A1
Read/Write
0x00000000
0xE000EDAC
MPU Region Base Address Register Alias 2
MPU_RBAR_A2
Read/Write
0x00000000
0xE000EDB0
MPU Region Attribute and Size Register Alias 2
MPU_RASR_A2
Read/Write
0x00000000
0xE000EDB4
MPU Region Base Address Register Alias 3
MPU_RBAR_A3
Read/Write
0x00000000
0xE000EDB8
MPU Region Attribute and Size Register Alias 3
MPU_RASR_A3
Read/Write
0x00000000
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12.11.2.1 MPU Type Register
Name:
MPU_TYPE
Access:
Read/Write
31
–
30
–
29
–
28
–
23
22
21
20
27
–
26
–
25
–
24
–
19
18
17
16
11
10
9
8
3
–
2
–
1
–
0
SEPARATE
IREGION
15
14
13
12
DREGION
7
–
6
–
5
–
4
–
The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports.
• IREGION: Instruction Region
Indicates the number of supported MPU instruction regions.
Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.
• DREGION: Data Region
Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
• SEPARATE: Separate Instruction
Indicates support for unified or separate instruction and date memory maps:
0: Unified.
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12.11.2.2 MPU Control Register
Name:
MPU_CTRL
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
PRIVDEFENA
1
HFNMIENA
0
ENABLE
The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of
the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
• PRIVDEFENA: Privileged Default Memory Map Enable
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by
any enabled region causes a fault.
1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software
accesses.
When enabled, the background region acts as a region number -1. Any region that is defined and enabled has priority over
this default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA: Hard Fault and NMI Enable
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable.
• ENABLE: MPU Enable
Enables the MPU:
0: MPU disabled.
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the default memory map is as described in “Memory Model”. Any access by privileged
software that does not address an enabled memory region behaves as defined by the default memory map.
• Any access by unprivileged software that does not address an enabled memory region causes a memory management
fault.
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XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless
the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the
MPU is not implemented. The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are
accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with
priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is
enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
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12.11.2.3 MPU Region Number Register
Name:
MPU_RNR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
REGION
The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASRs.
• REGION: MPU Region Referenced by the MPU_RBAR and MPU_RASRs
Indicates the MPU region referenced by the MPU_RBAR and MPU_RASRs.
The MPU supports 8 memory regions, so the permitted values of this field are 0–7.
Normally, the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR. However, the region number can be changed by writing to the MPU_RBAR with the VALID bit set to 1; see “MPU Region Base
Address Register”. This write updates the value of the REGION field.
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12.11.2.4 MPU Region Base Address Register
Name:
MPU_RBAR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDR
23
22
21
20
ADDR
15
14
13
12
ADDR
7
6
ADDR
5
4
VALID
REGION
The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region (SIZE field in the
MPU_RASR).
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
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12.11.2.5 MPU Region Attribute and Size Register
Name:
MPU_RASR
Access:
Read/Write
31
–
30
–
29
–
28
XN
27
–
26
25
AP
24
23
–
22
–
21
20
TEX
19
18
S
17
C
16
B
15
14
13
12
11
10
9
8
3
SIZE
2
1
0
ENABLE
SRD
7
–
6
–
5
4
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-39.
• TEX, C, B: Memory Access Attributes
See Table 12-37.
• S: Shareable
See Table 12-37.
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subregion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD
field as 0x00.
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• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
SIZE Value
Region Size
Value of N (1)
Note
b00100 (4)
32 B
5
Minimum permitted size
b01001 (9)
1 KB
10
–
b10011 (19)
1 MB
20
–
b11101 (29)
1 GB
30
–
b11111 (31)
4 GB
b01100
Maximum possible size
Note:
1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes”.
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12.11.2.6 MPU Region Base Address Register Alias 1
Name:
MPU_RBAR_A1
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDR
23
22
21
20
ADDR
15
14
13
12
ADDR
7
6
ADDR
5
4
VALID
REGION
The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region.
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
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12.11.2.7 MPU Region Attribute and Size Register Alias 1
Name:
MPU_RASR_A1
Access:
Read/Write
31
–
23
30
–
29
–
28
XN
27
–
26
25
AP
24
22
21
20
TEX
19
18
S
17
C
16
B
14
13
12
11
10
9
8
3
SIZE
2
1
0
ENABLE
–
15
SRD
7
–
6
–
5
4
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-39.
• TEX, C, B: Memory Access Attributes
See Table 12-37.
• S: Shareable
See Table 12-37.
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subregion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD
field as 0x00.
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• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
SIZE Value
Region Size
Value of N (1)
Note
b00100 (4)
32 B
5
Minimum permitted size
b01001 (9)
1 KB
10
–
b10011 (19)
1 MB
20
–
b11101 (29)
1 GB
30
–
b11111 (31)
4 GB
b01100
Maximum possible size
Note:
1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes”.
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12.11.2.8 MPU Region Base Address Register Alias 2
Name:
MPU_RBAR_A2
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDR
23
22
21
20
ADDR
15
14
13
12
ADDR
7
6
ADDR
5
4
VALID
REGION
The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region.
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
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12.11.2.9 MPU Region Attribute and Size Register Alias 2
Name:
MPU_RASR_A2
Access:
Read/Write
31
–
30
–
29
–
28
XN
27
–
26
25
AP
24
23
–
22
–
21
20
TEX
19
18
S
17
C
16
B
15
14
13
12
11
10
9
8
3
SIZE
2
1
0
ENABLE
SRD
7
–
6
–
5
4
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-39.
• TEX, C, B: Memory Access Attributes
See Table 12-37.
• S: Shareable
See Table 12-37.
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subregion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD
field as 0x00.
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• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
SIZE Value
Region Size
Value of N (1)
Note
b00100 (4)
32 B
5
Minimum permitted size
b01001 (9)
1 KB
10
–
b10011 (19)
1 MB
20
–
b11101 (29)
1 GB
30
–
b11111 (31)
4 GB
b01100
Maximum possible size
Note:
1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes”.
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12.11.2.10 MPU Region Base Address Register Alias 3
Name:
MPU_RBAR_A3
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDR
23
22
21
20
ADDR
15
14
13
12
ADDR
7
6
ADDR
5
4
VALID
REGION
The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
Software must ensure that the value written to the ADDR field aligns with the size of the selected region.
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
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12.11.2.11 MPU Region Attribute and Size Register Alias 3
Name:
MPU_RASR_A3
Access:
Read/Write
31
–
30
–
29
–
28
XN
27
–
26
25
AP
24
23
–
22
–
21
20
TEX
19
18
S
17
C
16
B
15
14
13
12
11
10
9
8
3
SIZE
2
1
0
ENABLE
SRD
7
–
6
–
5
4
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-39.
• TEX, C, B: Memory Access Attributes
See Table 12-37.
• S: Shareable
See Table 12-37.
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding subregion is enabled.
1: Corresponding subregion is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD
field as 0x00.
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• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
SIZE Value
Region Size
Value of N (1)
Note
b00100 (4)
32 B
5
Minimum permitted size
b01001 (9)
1 KB
10
–
b10011 (19)
1 MB
20
–
b11101 (29)
1 GB
30
–
b11111 (31)
4 GB
b01100
Maximum possible size
Note:
1. In the MPU_RBAR; see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes”.
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12.12 Floating Point Unit (FPU)
The Cortex-M4F FPU implements the FPv4-SP floating-point extension.
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root
operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point
constant instructions.
The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008,
IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.
The FPU contains 32 single-precision extension registers, which can also be accessed as 16 doubleword registers
for load, store, and move operations.
12.12.1 Enabling the FPU
The FPU is disabled from reset. It must be enabled before any floating-point instructions can be used. Example 41 shows an example code sequence for enabling the FPU in both privileged and user modes. The processor must
be in privileged mode to read from and write to the CPACR.
Example of Enabling the FPU:
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF 1
Trace Data
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13.4
Cross Triggering Debug Events
Cross Triggering (CT) as shown in Figure 13-2 is an Atmel module that enables two cores to send and receive
debug events to and from each other. This module is used to debug two applications at the same time (one
application running on each core).
CT enables core 0 (or 1) to trigger a debug event (halt) to core 1 (or 0) to enter Debug mode. The debug event can
be sent when the core 0 (or 1) enters Debug mode (such as breakpoint) or at run-time.
Once core 0 (or 1) gets out of Debug mode, it releases core 1 (0) from Debug mode as well.
The Cross Triggering configuration is located in the Special Function Register in the Matrix User Interface.
13.5
Application Examples
13.5.1 Debug Environment
Figure 13-3 shows a complete debug environment example. The SWJ-DP interface is used for standard
debugging functions, such as downloading code and single-stepping through the program, as well as viewing core
and peripheral registers.
Figure 13-3.
Application Debug Environment Example
Host Debugger
PC
SWJ-DP
Emulator/Probe
SWJ-DP
Connector
SAM4
SAM4-based Application Board
13.5.2 Test Environment
Figure 13-4 shows an example of a test environment (JTAG Boundary scan). Test vectors are sent and interpreted
by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These
devices can be connected to form a single scan chain.
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Figure 13-4.
Application Test Environment Example
Test Adaptor
Tester
JTAG
Probe
JTAG
Connector
Chip n
SAM4
Chip 2
Chip 1
SAM4-based Application Board In Test
13.6
Debug and Test Pin Description
Table 13-1.
Debug and Test Signal List
Signal Name
Function
Type
Active Level
Input/Output
Low
Input
–
Reset/Test
NRST
Microcontroller Reset
TST
Test Select
SWD/JTAG
13.7
TCK/SWCLK
Test Clock/Serial Wire Clock
Input
–
TDI
Test Data In
Input
–
TDO/TRACESWO
Test Data Out/Trace Asynchronous Data Out
Output
–
TMS/SWDIO
Test Mode Select/Serial Wire Input/Output
Input
–
JTAGSEL
JTAG Selection
Input
High
Functional Description
13.7.1 Test Pin
One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during powerup, the device is in Normal operating mode. When at high level, the device is in Test mode or FFPI mode. The TST
pin integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal
operation. Note that when setting the TST pin to low or high level at power-up, the pin must remain in the same
state for the duration of the operation.
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13.7.2 Debug Architecture
Figure 13-5 illustrates the debug architecture. The Cortex-M4 embeds four functional units for debug:
SWJ-DP (Serial Wire/JTAG Debug Port)
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
TPIU (Trace Port Interface Unit)
The information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes and debugging tool
vendors for Cortex-M4 based microcontrollers. For further details on SWJ-DP, refer to the Cortex-M4 technical
reference manual.
Figure 13-5.
Debug Architecture
DWT
4 watchpoints
FPB
SWJ-DP
PC sampler
6 breakpoints
data address sampler
SWD/JTAG
ITM
data sampler
software trace
32 channels
interrupt trace
SWO trace
TPIU
time stamping
CPU statistics
13.7.3 Serial Wire/JTAG Debug Port (SWJ-DP)
The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight debug port. It combines the Serial
Wire Debug Port (SW-DP), from 2 to 3 pins, and the JTAG Debug Port (JTAG-DP), 5 pins.
By default, the JTAG-DP is active. If the host debugger needs to switch to the SW-DP, it must provide a dedicated
JTAG sequence on TMS/SWDIO and TCK/SWCLK. This disables JTAG-DP and enables SW-DP.
When SW-DP is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output
(TRACESWO) is multiplexed with TDO and thus the asynchronous trace can only be used with SW-DP.
Table 13-2.
SWJ-DP Pin List
Pin Name
JTAG Port
Serial Wire Debug Port
TMS/SWDIO
TMS
SWDIO
TCK/SWCLK
TCK
SWCLK
TDI
TDI
-
TDO/TRACESWO
TDO
TRACESWO (optional: trace)
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP
and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.
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13.7.3.1 SW-DP and JTAG-DP Selection
Debug port selection is done by sending a specific SWDIOTMS sequence. The JTAG-DP is selected by default
after reset.
Switch from JTAG-DP to SW-DP. The sequence is:
̶
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
̶
Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
̶
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Switch from SWD to JTAG. The sequence is:
̶
̶
̶
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
13.7.4 FPB (Flash Patch Breakpoint)
The FPB:
Implements hardware breakpoints
Patches code and data from code space to system space.
The FPB unit contains:
Two literal comparators for matching against literal loads from Code space, and remapping to a
corresponding area in System space.
Six instruction comparators for matching against instruction fetches from Code space, and remapping to a
corresponding area in System space.
Alternatively, comparators can also be configured to generate a Breakpoint instruction to the processor core
on a match.
13.7.5 DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to generate the following:
PC sampling packets at set intervals
PC or Data watchpoint packets
Watchpoint event to halt core
The DWT contains counters for the items that follow:
Clock cycle (CYCCNT)
Folded instructions
Load Store Unit (LSU) operations
Sleep Cycles
CPI (all instruction cycles except for the first cycle)
Interrupt overhead
13.7.6 ITM (Instrumentation Trace Macrocell)
The ITM is an application-driven trace source that supports ‘printf’ style debugging to trace operating system (OS)
and application events, and provides diagnostic system information. The ITM transmits the trace information as
packets which can be generated by three different sources with several priority levels:
Software trace—Software can write directly to ITM stimulus registers. This can be done using the ‘printf’
function. For more information, refer to Section 13.7.6.1 “How to Configure the ITM”.
Hardware trace—The ITM transmits packets generated by the DWT.
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Time stamping—Timestamps are transmitted relative to packets. The ITM contains a 21-bit counter to
generate the timestamp.
13.7.6.1 How to Configure the ITM
The following example describes how to output trace data in Asynchronous Trace mode.
1.
Configure the TPIU for Asynchronous Trace mode (refer to Section 13.7.6.3 “How to Configure the TPIU”)
2.
Enable the write accesses into the ITM registers by writing 0xC5ACCE55 into the Lock Access Register
(address: 0xE0000FB0)
3.
Write 0x00010015 into the Trace Control Register:
̶
Enable ITM
̶
Enable Synchronization packets
̶
Enable SWO behavior
̶
Set the ATB ID to 1
4.
Write 0x1 into the Trace Enable Register:
5.
Write 0x1 into the Trace Privilege Register:
̶
̶
Enable the Stimulus port 0
6.
Stimulus port 0 only accessed in Privileged mode (clearing a bit in this register results in the
corresponding stimulus port being accessible in User mode.)
Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
The TPIU acts as a bridge between the on-chip trace data and the ITM.
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
13.7.6.2 Asynchronous Mode
The TPIU is configured in Asynchronous mode, trace data are output using the single TRACESWO pin. The
TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, Asynchronous
Trace mode is only available when the Serial Wire Debug mode is selected since TDO signal is used in JTAG
Debug mode.
Two encoding formats are available for the single pin output:
Manchester encoded stream. This is the reset value.
NRZ_based UART byte structure
13.7.6.3 How to Configure the TPIU
This example is applicable with Asynchronous Trace mode only.
1.
Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of
trace and debug blocks.
2.
Write 0x2 into the Selected Pin Protocol Register
̶
Select the Serial Wire Output – NRZ
3.
Write 0x100 into the Formatter and Flush Control Register
4.
Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the
asynchronous output (this can be done automatically by the debugging tool).
13.7.7 IEEE 1149.1 JTAG Boundary Scan
With IEEE 1149.1 JTAG Boundary Scan, the pin-level access is independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied low, while JTAGSEL is high and PA7 is tied low
during the power-up, and must be kept in this state during the whole boundary scan operation. The SAMPLE,
EXTEST and BYPASS functions are implemented. In SWD/JTAG Debug mode, the ARM processor responds with
a non-JTAG chip ID that identifies the processor. This is not IEEE 1149.1 JTAG-compliant.
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It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset
must be performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided on www.atmel.com to set up the test.
13.7.7.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins and the associated
control signals.
Each SAM4 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be
forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects
the direction of the pad.
For more information, refer to BDSL files available for the SAM4 Series.
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13.7.8 ID Code Register
Access: Read-only
31
30
29
28
27
21
20
19
PART NUMBER
VERSION
23
22
15
14
13
PART NUMBER
7
6
5
12
11
4
3
MANUFACTURER IDENTITY
26
25
PART NUMBER
24
18
16
17
10
9
MANUFACTURER IDENTITY
2
1
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
Chip Name
Chip ID
SAM4CM
0x05B34
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1
Set to 0x1.
Chip Name
JTAG ID Code
SAM4CM
0x05B3_403F
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0
1
14.
Boot Program
14.1
Description
The SAM-BA Boot Program includes an array of programs used to download and/or upload data into the different
memories of the product.
14.2
Hardware and Software Constraints
SAM-BA Boot uses the first 4096 bytes of the SRAM for variables and stacks. The remaining available size
can be used for user code.
UART0 requirements: None
Table 14-1.
14.3
Pins Driven during Boot Program Execution
Peripheral
Pin
PIO Line
UART0
URXD0
PB4
UART0
UTXD0
PB5
Flow Diagram
The Boot Program implements the algorithm depicted in Figure 14-1.
Figure 14-1.
Boot Program Algorithm Flow Diagram
No
Device
Setup
Character # received
from UART0?
Yes
Run SAM-BA Monitor
The SAM-BA Boot program uses the internal 12-MHz RC oscillator as source clock for PLL. The MCK runs from
PLL divided by 2. The core runs at 48 MHz.
14.4
Device Initialization
Initialization follows the steps described below:
1.
Stack setup
2.
Setup the embedded Flash controller
3.
Switch on internal 12 MHz RC oscillator
4.
Configure PLLB to run at 48 MHz
5.
Configure UART0
6.
Disable Watchdog
7.
Wait for a character on UART0
8.
Jump to SAM-BA monitor (refer to Section 14.5 ”SAM-BA Monitor”)
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14.5
SAM-BA Monitor
The SAM-BA boot principle: once the communication interface is identified, running in an infinite loop waiting for
different commands as shown in Table 14-2.
Table 14-2.
Command
Action
Argument(s)
Example
N
Set Normal mode
No argument
N#
T
Set Terminal mode
No argument
T#
O
Write a byte
Address, Value#
O200001,CA#
o
Read a byte
Address,#
o200001,#
H
Write a half word
Address, Value#
H200002,CAFE#
h
Read a half word
Address,#
h200002,#
W
Write a word
Address, Value#
W200000,CAFEDECA#
w
Read a word
Address,#
w200000,#
S
Send a file
Address,#
S200000,#
R
Receive a file
Address, NbOfBytes#
R200000,1234#
G
Go
Address#
G200200#
V
Display version
No argument
V#
Mode commands:
̶
Normal mode configures SAM-BA Monitor to send/receive data in binary format
̶
Terminal mode configures SAM-BA Monitor to send/receive data in ASCII format
Write commands: Write a byte (O), a halfword (H) or a word (W) to the target
̶
̶
Note:
Address: Address in hexadecimal
Value: Byte, halfword or word to write in hexadecimal
Read commands: Read a byte (o), a halfword (h) or a word (w) from the target
̶
Address: Address in hexadecimal
̶
Output: The byte, halfword or word read in hexadecimal
Send a file (S): Send a file to a specified address
̶
Address: Address in hexadecimal
There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command
execution.
Receive a file (R): Receive data into a file from a specified address
̶
̶
Address: Address in hexadecimal
NbOfBytes: Number of bytes in hexadecimal to receive
Go (G): Jump to a specified address and execute the code
Get Version (V): Return the SAM-BA boot version
̶
Note:
318
Commands Available through the SAM-BA Boot
Address: Address to jump in hexadecimal
In Terminal mode, when the requested command is performed, SAM-BA Monitor adds the following prompt sequence
to its answer: ++'>'.
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14.5.1 UART0 Serial Port
Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send the application file to the target. The size of the binary file to send depends on the
SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size
because the Xmodem protocol requires some SRAM memory to work. Refer to Section 14.2 ”Hardware and
Software Constraints”.
14.5.2 Xmodem Protocol
The supported Xmodem protocol is the 128-byte length block. This protocol uses a two-character CRC-16 to
guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver report a successful transmission. Each
block of the transfer looks like:
where:
= 01 hex
= binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
= 1’s complement of the blk#.
= 2 bytes CRC16
Figure 14-2 shows a transmission using this protocol.
Figure 14-2.
Xmodem Transfer Example
Host
Device
C
SOH 01 FE Data[128] CRC CRC
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
14.5.3 In-Application Programming (IAP) Feature
The IAP feature is a function located in the ROM that can be called by any software application.
When called, IAP sends the required FLASH command to the EEFC and waits for the Flash to be ready (looping
while the FRDY bit is not set in the EEFC_FSR register).
Since this function is executed from ROM, Flash programming (such as sector write) can be performed by code
running in Flash.
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The IAP function entry point is retrieved by reading the NMI vector in the ROM (0x02000008).
This function takes one argument in parameter: the command to be sent to the EEFC.
This function returns the value of the EEFC_FSR register.
IAP software code example:
(unsigned int) (*IAP_Function)(unsigned long);
void main (void){
unsigned
unsigned
unsigned
unsigned
long
long
long
long
FlashSectorNum = 200; //
flash_cmd = 0;
flash_status = 0;
EFCIndex = 0; // 0:EEFC0, 1: EEFC1
/* Initialize the function pointer (retrieve function address from NMI vector)
*/
IAP_Function = ((unsigned long) (*)(unsigned long))
0x02000008;
/* Send your data to the sector here */
/* build the command to send to EEFC */
flash_cmd =
(0x5A Core 0 Cross Triggering
0: Core 1 is not able to trigger an event on core 0.
1: Core 1 is able to trigger an event on core 0.
• CROSS_TRG0: Core 0 --> Core 1 Cross Triggering
0: Core 0 is not able to trigger an event on core 1.
1: Core 0 is able to trigger an event on core 1.
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26.9.7 Write Protection Mode Register
Name:
MATRIX_WPMR
Address:
0x400E03E4 (0), 0x480101E4 (1)
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
WPEN
For more information on Write Protection registers, refer to Section 26.8 “Register Write Protection”.
• WPEN: Write Protect Enable
0: Disables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
See Section 26.8 “Register Write Protection” for the list of registers that can be protected.
• WPKEY: Write Protect Key
Value
Name
0x4D4154
PASSWD
Description
Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
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26.9.8 Write Protection Status Register
Name:
MATRIX_WPSR
Address:
0x400E03E8 (0), 0x480101E8 (1)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
11
10
9
8
WPVSRC
15
14
13
12
WPVSRC
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
WPVS
For more information on Write Protection registers, refer to Section 26.8 “Register Write Protection”.
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of the MATRIX_WPMR register.
1: A write protection violation has occurred since the last write of the MATRIX_WPMR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
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27.
Static Memory Controller (SMC)
27.1
Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external
devices and the ARM-based microcontroller. The Static Memory Controller (SMC) is part of the EBI.
This SMC can handle several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM,
EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
The SMC generates the signals that control the access to the external memory devices or peripheral devices. It
has 4 Chip Selects, a 24-bit address bus, and a configurable 8 or 16-bit data bus. Separate read and write control
signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully adjustable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with
an automatic Slow clock mode. In Slow clock mode, it switches from user-programmed waveforms to slow-rate
specific waveforms on read and write signals. The SMC supports asynchronous burst read in Page mode access
for page sizes up to 32 bytes.
The External Data Bus can be scrambled/unscrambled by means of user keys.
27.2
Embedded Characteristics
Four Chip Selects Available
16-Mbyte Address Space per Chip Select
8-bit or 16-bit Data Bus
Zero Wait State Scrambling/Unscrambling Function with User Key
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
Register Write Protection
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27.3
I/O Lines Description
Table 27-1.
I/O Line Description
Name
Description
Type
Active Level
NCS[3:0]
Static Memory Controller Chip Select Lines
Output
Low
NRD
Read Signal
Output
Low
NWR0/NWE
Write 0/Write Enable Signal
Output
Low
NWR1/NBS1
Write 1/Byte 1 Select Signal
Output
Low
A0/NBS0
Address Bit 0/Byte 0 Select Signal
Output
Low
A[23:1]
Address Bus
Output
–
D[15:0]
Data Bus
I/O
–
NWAIT
External Wait Signal
Input
Low
NANDCS
NAND Flash Chip Select Line
Output
Low
NANDOE
NAND Flash Output Enable
Output
Low
NANDWE
NAND Flash Write Enable
Output
Low
NANDALE
NAND Flash Address Latch Enable
Output
–
NANDCLE
NAND Flash Command Latch Enable
Output
–
27.4
Product Dependencies
27.4.1 I/O Lines
The pins used for interfacing the SMC are multiplexed with the PIO lines. The programmer must first program the
PIO controller to assign the SMC pins to their peripheral function. If I/O Lines of the SMC are not used by the
application, they can be used for other purposes by the PIO Controller.
27.4.2 Power Management
The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure
the PMC to enable the SMC clock.
27.5
Multiplexed Signals
Table 27-2.
Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals
Related Function
Byte-write or Byte-select access.
NWR0
NWE
A0
NBS0
8-bit or 16-bit data bus. See Section 27.7.1 ”Data Bus Width”
NWR1
NBS1
Byte-write or Byte-select access. See Section 27.7.2.1 ”Byte Write Access” and Section 27.7.2.2 ”Byte
Select Access”
A22
NANDCLE
NAND Flash Command Latch Enable
A21
NANDALE
NAND Flash Address Latch Enable
496
See Section 27.7.2.1 ”Byte Write Access” and Section 27.7.2.2 ”Byte Select Access”
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27.6
External Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and
appears to be repeated within this space. The SMC correctly handles any valid access to the memory device
within the page (see Figure 27-1).
Figure 27-1.
Memory Connections for Four External Devices
NCS[0] - NCS[3]
NRD
SMC
NWE
A[23:0]
D[15:0]
NCS3
NCS2
NCS1
NCS0
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
24
16 or 8
27.7
A[23:0]
D[15:0] or D[7:0]
Connection to External Devices
27.7.1 Data Bus Width
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the bit DBW in the
SMC MODE register (SMC_MODE) for the corresponding chip select.
Figure 27-2 shows how to connect a 512-Kbyte x 8-bit memory on NCS2. Figure 27-3 shows how to connect a
512-Kbyte x 16-bit memory on NCS2.
Figure 27-2.
Memory Connection for an 8-bit Data Bus
D[7:0]
A[18:2]
SMC
D[7:0]
A[18:2]
A1
A1
A0
A0
NWE
Write Enable
NRD
Output Enable
NCS[2]
Memory Enable
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Figure 27-3.
Memory Connection for a 16-bit Data Bus
D[15:0]
D[15:0]
A[19:2]
A[18:1]
A1
SMC
A[0]
NBS0
Low Byte Enable
NBS1
High Byte Enable
NWE
Write Enable
NRD
Output Enable
NCS[2]
Memory Enable
27.7.2 Byte Write or Byte Select Access
Each chip select with a 16-bit data bus can operate with one of two different types of write access: Byte Write or
Byte Select. This is controlled by the BAT bit of the SMC_MODE register for the corresponding chip select.
27.7.2.1 Byte Write Access
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory, and supports one write signal per byte
of the data bus and a single read signal.
Note that the SMC does not allow boot in Byte Write Access mode.
For 16-bit devices, the SMC provides NWR0 and NWR1 write signals for respectively Byte0 (lower byte) and Byte1
(upper byte) of a 16-bit bus. One single read signal (NRD) is provided.
27.7.2.2 Byte Select Access
Byte Select Access is used to connect one 16-bit device. In this mode, read/write operations can be
enabled/disabled at Byte level. One Byte-select line per byte of the data bus is provided. One NRD and one NWE
signal control read and write.
For 16-bit devices, the SMC provides NBS0 and NBS1 selection signals for respectively Byte0 (lower byte) and
Byte1 (upper byte) of a 16-bit bus.
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Figure 27-4.
Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option
D[7:0]
D[7:0]
D[15:8]
A[24:2]
A[23:1]
A[0]
A1
SMC
NWR0
Write Enable
NWR1
Read Enable
NRD
Memory Enable
NCS[3]
D[15:8]
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
27.7.2.3 Signal Multiplexing
Depending on the Byte Access Type (BAT), only the write signals or the byte select signals are used. To save IOs
at the external bus interface, control signals at the SMC interface are multiplexed. Table 27-3 shows signal
multiplexing depending on the data bus width and the Byte Access Type.
For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 is unused. When Byte
Write option is selected, NBS0 is unused.
Table 27-3.
SMC Multiplexed Signal Translation
Signal Name
16-bit Bus
Device Type
8-bit Bus
1 x 16-bit
2 x 8-bit
1 x 8-bit
Byte Select
Byte Write
–
NBS0_A0
NBS0
–
A0
NWE_NWR0
NWE
NWR0
NWE
NBS1_NWR1
NBS1
NWR1
–
A1
A1
A1
Byte Access Type (BAT)
A1
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27.7.3 NAND Flash Support
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the SMC. It depends on the programming of the SMC_NFCSx field in the
CCFG_SMCNFCS register on the Bus Matrix User Interface. For details on this register, refer to Section 26. ”Bus
Matrix (MATRIX)”. Access to an external NAND Flash device via the address space reserved to the chip select
programmed.
The user can connect up to four NAND Flash devices with separate chip selects.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer
address fails to lie in the NCSx programmed address space.
Figure 27-5.
NAND Flash Signal Multiplexing on SMC Pins
SMC
NAND Flash Logic
NCSx (activated if SMC_NFCSx=1) *
NRD
NANDOE
NANDWE
NANDOE
NANDWE
NWE
* in CCFG_SMCNFCS Matrix register
Note:
When the NAND Flash logic is activated, (SMC_NFCSx=1), the NWE pin cannot be used in PIO mode but only in
Peripheral mode (NWE function). If the NWE function is not used for other external memories (SRAM, LCD), it must
be configured in one of the following modes:
– PIO Input with pull-up enabled (default state after reset)
– PIO Output set at level 1
The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits
A22 and A21of the address bus. Any bit of the address bus can also be used for this purpose. The command,
address or data words on the data bus of the NAND Flash device use their own addresses within the NCSx
address space (configured by the register CCFG_SMCNFCS on the Bus Matrix User Interface). The chip enable
(CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains
asserted even when NCS3 is not selected, preventing the device from returning to Standby mode. The NANDCS
output signal should be used in accordance with the external NAND Flash device type.
Two types of CE behavior exist depending on the NAND Flash device:
Standard NAND Flash devices require that the CE pin remains asserted Low continuously during the read
busy period to prevent the device from returning to Standby mode. Since the SMC asserts the NCSx signal
High, it is necessary to connect the CE pin of the NAND Flash device to a GPIO line, in order to hold it low
during the busy period preceding data read out.
This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal can be directly
connected to the CE pin of the NAND Flash device.
Figure 27-6 illustrates both topologies: Standard and “CE don’t care” NAND Flash.
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Figure 27-6.
Standard and “CE don’t care” NAND Flash Application Examples
D[7:0]
D[7:0]
AD[7:0]
A[22:21]
AD[7:0]
A[22:21]
ALE
ALE
CLE
NCSx
CLE
NCSx
Not Connected
SMC
SMC
NAND Flash
“CE don’t care”
NAND Flash
NANDOE
NANDOE
NOE
NANDWE
27.8
CE
NOE
NANDWE
NWE
PIO
CE
PIO
R/B
PIO
NWE
R/B
Application Example
27.8.1 Implementation Examples
Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check
for memory device availability.
For hardware implementation examples, refer to the evaluation kit schematics for this microcontroller, which show
examples of a connection to an LCD module and NAND Flash.
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27.8.1.1 8-bit NAND Flash
Hardware Configuration
D[0..7]
U1
CLE
ALE
NANDOE
NANDWE
(ANY PIO)
(ANY PIO)
R1
3V3
R2
10K
16
17
8
18
9
CLE
ALE
RE
WE
CE
7
R/B
19
WP
1
2
3
4
5
6
10
11
14
15
20
21
22
23
24
25
26
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
10K
K9F2G08U0M
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
29
30
31
32
41
42
43
44
N.C
N.C
N.C
N.C
N.C
N.C
PRE
N.C
N.C
N.C
N.C
N.C
48
47
46
45
40
39
38
35
34
33
28
27
VCC
VCC
37
12
VSS
VSS
36
13
2 Gb
D0
D1
D2
D3
D4
D5
D6
D7
3V3
C2
100NF
C1
100NF
TSOP48 PACKAGE
Software Configuration
Perform the following configuration:
1. Assign the SMC_NFCSx (for example SMC_NFCS3) field in the CCFG_SMCNFCS register on the Bus
Matrix User Interface.
2.
Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled by setting the
address bits A21 and A22, respectively, during accesses.
3.
NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs must be
programmed in Peripheral mode in the PIO controller.
4.
Configure a PIO line as an input to manage the Ready/Busy signal.
5.
Configure SMC CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, the data bus width
and the system bus frequency.
In this example, the NAND Flash is not addressed as a “CE don’t care”. To address it as a “CE don’t care”, connect
NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE.
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27.8.1.2 NOR Flash
Hardware Configuration
D[0..7]
A[0..21]
U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D1
D2
D3
D4
D5
D6
D7
3V3
VCCQ
NRST
NWE
3V3
NCS0
NRD
RESET
WE
WP
VPP
CE
OE
C2
100NF
VCC
VSS
VSS
C1
100NF
Software Configuration
Configure the SMC CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency.
27.9
Standard Read and Write Protocols
In the following sections, the Byte Access Type is not considered. Byte select lines (NBS0 to NBS1) always have
the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of
the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR1 have the same timings and
protocol as NWE. If D[15:8] are used, they have the same timing as D[7:0]. In the same way, NCS represents one
of the NCS[0..3] chip select lines.
27.9.1 Read Waveforms
The read cycle is shown on Figure 27-7.
The read cycle starts with the address setting on the memory address bus.
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Figure 27-7.
Standard Read Cycle
MCK
A[23:0]
NRD
NCS
D[7:0]
NRD_SETUP
NCS_RD_SETUP
NRD_PULSE
NRD_HOLD
NCS_RD_PULSE
NCS_RD_HOLD
NRD_CYCLE
27.9.1.1 NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
NRD_SETUP—the NRD setup time is defined as the setup of address before the NRD falling edge;
NRD_PULSE—the NRD pulse length is the time between NRD falling edge and NRD rising edge;
NRD_HOLD—the NRD hold time is defined as the hold time of address after the NRD rising edge.
27.9.1.2 NCS Waveform
The NCS signal can be divided into a setup time, pulse length and hold time:
NCS_RD_SETUP—the NCS setup time is defined as the setup time of address before the NCS falling edge.
NCS_RD_PULSE— the NCS pulse length is the time between NCS falling edge and NCS rising edge;
NCS_RD_HOLD—the NCS hold time is defined as the hold time of address after the NCS rising edge.
27.9.1.3 Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on
the address bus to the point where address may change. The total read cycle time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles.
To ensure that the NRD and NCS timings are consistent, user must define the total read cycle instead of the hold
timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
27.9.1.4 Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously
in case of consecutive read cycles in the same memory (see Figure 27-8).
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Figure 27-8.
No Setup, No Hold on NRD and NCS Read Signals
MCK
A[23:0]
NRD
NCS
D[7:0]
NRD_PULSE
NRD_PULSE
NRD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_CYCLE
NRD_CYCLE
27.9.1.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
27.9.2 Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data
is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first.
The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
of NRD and NCS controls the read operation.
27.9.2.1 Read is Controlled by NRD (READ_MODE = 1)
Figure 27-9 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available
tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE
must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The
SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD,
whatever the programmed waveform of NCS may be.
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Figure 27-9.
READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
MCK
A[23:0]
NRD
NCS
tPACC
D[7:0]
Data Sampling
27.9.2.2 Read is Controlled by NCS (READ_MODE = 0)
Figure 27-10 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of
the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that
case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the
rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD
may be.
Figure 27-10. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
MCK
A[23:0]
NRD
NCS
tPACC
D[7:0]
Data Sampling
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27.9.3 Write Waveforms
The write protocol is similar to the read protocol. It is depicted in Figure 27-11. The write cycle starts with the
address setting on the memory address bus.
27.9.3.1 NWE Waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
NWE_SETUP—the NWE setup time is defined as the setup of address and data before the NWE falling
edge;
NWE_PULSE—the NWE pulse length is the time between NWE falling edge and NWE rising edge;
NWE_HOLD—the NWE hold time is defined as the hold time of address and data after the NWE rising edge.
27.9.3.2 NCS Waveforms
The NCS signal waveforms in write operation are not the same that those applied in read operations, but are
separately defined:
NCS_WR_SETUP—the NCS setup time is defined as the setup time of address before the NCS falling
edge.
NCS_WR_PULSE—the NCS pulse length is the time between NCS falling edge and NCS rising edge;
NCS_WR_HOLD—the NCS hold time is defined as the hold time of address after the NCS rising edge.
Figure 27-11. Write Cycle
MCK
A[23:0]
NWE
NCS
NWE_SETUP
NCS_WR_SETUP
NWE_PULSE
NCS_WR_PULSE
NWE_HOLD
NCS_WR_HOLD
NWE_CYCLE
27.9.3.3 Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set
on the address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE=NWE_SETUP + NWE_PULSE + NWE_HOLD=NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
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All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock
cycles. To ensure that the NWE and NCS timings are consistent, the user must define the total write cycle instead
of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
27.9.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in
case of consecutive write cycles in the same memory (see Figure 27-12). However, for devices that perform write
operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Figure 27-12. Null Setup and Hold Values of NCS and NWE in Write Cycle
MCK
A[23:0]
NWE
NCS
D[7:0]
NWE_PULSE
NWE_PULSE
NWE_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_CYCLE
NWE_CYCLE
27.9.3.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable
behavior.
27.9.4 Write Mode
The bit WRITE_MODE in the SMC_MODE register of the corresponding chip select indicates which signal controls
the write operation.
27.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1):
Figure 27-13 shows the waveforms of a write operation with WRITE_MODE set . The data is put on the bus during
the pulse and hold steps of the NWE signal. The internal data buffers are switched to Output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
508
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Figure 27-13. WRITE_MODE = 1. The write operation is controlled by NWE
MCK
A[23:0]
NWE
NCS
D[7:0]
27.9.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
Figure 27-14 shows the waveforms of a write operation with WRITE_MODE cleared. The data is put on the bus
during the pulse and hold steps of the NCS signal. The internal data buffers are switched to Output mode after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 27-14. WRITE_MODE = 0. The write operation is controlled by NCS
MCK
A[23:0]
NWE
NCS
D[7:0]
27.9.5 Register Write Protection
To prevent any single software error that may corrupt SMC behavior, the registers listed below can be writeprotected by setting the WPEN bit in the SMC Write Protection Mode register (SMC_WPMR).
If a write access in a write-protected register is detected, the WPVS flag in the SMC Write Protection Status
register (SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been
attempted.
The WPVS flag is automatically cleared after reading the SSMC_WPSR.
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The following registers can be write-protected:
“SMC Setup Register”
“SMC Pulse Register”
“SMC Cycle Register”
“SMC MODE Register”
27.9.6 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according
to their type.
The SMC_SETUP register groups the definition of all setup parameters:
NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
NRD_CYCLE, NWE_CYCLE
Table 27-4 shows how the timing parameters are coded and their permitted range.
Table 27-4.
Coding and Range of Timing Parameters
Permitted Range
Coded Value
Number of Bits
Effective Value
Coded Value
Effective Value
setup [5:0]
6
128 x setup[5] + setup[4:0]
0 ≤ ≤ 31
0 ≤ ≤ 128+31
pulse [6:0]
7
256 x pulse[6] + pulse[5:0]
0 ≤ ≤ 63
0 ≤ ≤ 256+63
0 ≤ ≤ 256+127
cycle [8:0]
9
256 x cycle[8:7] + cycle[6:0]
0 ≤ ≤ 127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
27.9.7 Reset Values of Timing Parameters
Table 27-5 gives the default value of timing parameters at reset.
Table 27-5.
Reset Values of Timing Parameters
Register
Reset Value
Definition
SMC_SETUP
0x01010101
All setup timings are set to 1.
SMC_PULSE
0x01010101
All pulse timings are set to 1.
SMC_CYCLE
0x00030003
The read and write operations last 3 Master Clock
cycles and provide one hold cycle.
WRITE_MODE
1
Write is controlled with NWE.
READ_MODE
1
Read is controlled with NRD.
27.9.8 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE
parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
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For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface
because of the propagation delay of theses signals through external logic and pads. If positive setup and hold
values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews
between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal
after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See Section 27.11.2 ”Early Read Wait
State”.
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable
behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For
external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and
NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the
address bus.
27.10 Scrambling/Unscrambling Function
The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories
from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling/unscrambling function can be enabled or disabled by configuring the CSxSE bits in the SMC
OCMS Mode Register (SMC_OCMS).
When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the
CSxSE bits in the SMC_OCMS register.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2. These key
registers are only accessible in Write mode.
The scrambling user key or the seed for key generation must be securely stored in a reliable non-volatile memory
in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the
key is lost.
27.11 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention
or operation conflict.
27.11.1 Chip Select Wait States
The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that
there is no bus contention between the de-activation of one device and the activation of the next one.
During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1.
Figure 27-15 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
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Figure 27-15. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
MCK
A[23:0]
NRD
NWE
NCS0
NCS2
NRD_CYCLE
NWE_CYCLE
D[7:0]
Read to Write
Wait State
Chip Select
Wait State
27.11.2 Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the
write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip
select wait state. The early read cycle thus only occurs between a write and read access to the same memory
device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
512
if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 2716).
in NCS Write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the
NCS_RD_SETUP parameter is set to 0, regardless of the Read mode (Figure 27-17). The write operation
must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete
properly.
in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback
of the write control signal is used to control address, data, and chip select lines. If the external write control
signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and
address, data and control signals are maintained one more cycle. See Figure 27-18.
SAM4CM Series [DATASHEET]
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Figure 27-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup
MCK
A[23:0]
NWE
NRD
no hold
no setup
D[7:0]
write cycle
Early Read
wait state
read cycle
Figure 27-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
MCK
A[23:0]
NCS
NRD
no hold
no setup
D[7:0]
write cycle
(WRITE_MODE = 0)
read cycle
Early Read
wait state (READ_MODE = 0 or READ_MODE = 1)
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Figure 27-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle
MCK
A[25:2]
internal write controlling signal
external write controlling signal
(NWE)
no hold
read setup = 1
NRD
D[7:0]
write cycle
Early Read
read cycle
(WRITE_MODE = 1) wait state (READ_MODE = 0 or READ_MODE = 1)
27.11.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state
before starting the next access. This “Reload User Configuration Wait State” is used by the SMC to load the new
set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before
and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip
Select Wait State is applied.
On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload
Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
27.11.3.1 User Procedure
To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the
user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in
the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on
the mode parameters.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification. Any change of the Chip Select parameters, while
fetching the code from a memory connected on this CS, may lead to unpredictable behavior. The instructions used
to modify the parameters of an SMC Chip Select can be executed from the internal RAM or from a memory
connected to another CS.
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27.11.3.2 Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock mode is entered or exited, after the end of
the current transfer (see Section 27.14 ”Slow Clock Mode”).
27.11.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be
inserted. See Figure 27-15.
27.12 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states
(data float wait states) after a read access:
before starting a read access to a different external memory
before starting a write access to the same device or to a different external one.
The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the
SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data
float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed
for the data output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with
long tDF will not slow down the execution of a program from internal memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the
SMC_MODE register for the corresponding chip select.
27.12.1 READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state
buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal
and lasts TDF_CYCLES MCK cycles.
When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of
MCK cycles during which the data bus remains busy after the rising edge of NCS.
Figure 27-19 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float
period of 2 cycles (TDF_CYCLES = 2). Figure 27-20 shows the read operation when controlled by NCS
(READ_MODE = 0) and the TDF_CYCLES parameter equals 3.
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Figure 27-19. TDF Period in NRD Controlled Read Access (TDF = 2)
MCK
A[23:0]
NRD
NCS
tpacc
D[7:0]
TDF = 2 clock cycles
NRD controlled read operation
Figure 27-20. TDF Period in NCS Controlled Read Operation (TDF = 3)
MCK
A[23:0]
NRD
NCS
tpacc
D[7:0]
TDF = 3 clock cycles
NCS controlled read operation
27.12.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
Figure 27-21 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip
Select 0. Chip Select 0 has been programmed with:
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NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
Figure 27-21. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
MCK
NRD
NRD_HOLD= 4
NWE
NWE_SETUP= 3
NCS0
TDF_CYCLES = 6
D[7:0]
Read to Write
Wait State
read access on NCS0 (NRD controlled)
write access on NCS0 (NWE controlled)
27.12.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float
period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data
float period, no additional tdf wait states will be inserted.
Figure 27-22, Figure 27-23 and Figure 27-24 illustrate the cases:
read access followed by a read access on another chip select,
read access followed by a write access on another chip select,
read access followed by a write access on the same chip select,
with no TDF optimization.
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Figure 27-22. TDF Optimization Disabled (TDF Mode = 0): TDF wait states between 2 read accesses on different chip selects
MCK
A[23:0]
read1 controlling signal
(NRD)
read1 hold = 1
read2 controlling signal
(NRD)
read2 setup = 1
TDF_CYCLES = 6
D[7:0]
5 TDF WAIT STATES
read 2 cycle
TDF_MODE = 0
(optimization disabled)
read1 cycle
TDF_CYCLES = 6
Chip Select
Wait State
Figure 27-23.
TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
MCK
A[23:0]
read1 controlling signal
(NRD)
read1 hold = 1
write2 controlling signal
(NWE)
write2 setup = 1
TDF_CYCLES = 4
D[7:0]
2 TDF WAIT STATES
read1 cycle
TDF_CYCLES = 4
Read to Write Chip Select
Wait State Wait State
518
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write2 cycle
TDF_MODE = 0
(optimization disabled)
Figure 27-24. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
MCK
A[23:0]
read1 controlling signal
(NRD)
write2 setup = 1
read1 hold = 1
write2 controlling signal
(NWE)
TDF_CYCLES = 5
D[7:0]
4 TDF WAIT STATES
read1 cycle
TDF_CYCLES = 5
Read to Write
Wait State
write2 cycle
TDF_MODE = 0
(optimization disabled)
27.13 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE
field of the SMC_MODE register on the corresponding chip select must be set either to “10” (Frozen mode) or “11”
(Ready mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the
corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write
controlling signal, depending on the Read and Write modes of the corresponding chip select.
27.13.1 Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the
read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page mode (Section
27.15 ”Asynchronous Page Mode”), or in Slow clock mode (Section 27.14 ”Slow Clock Mode”).
The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then
NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the
NWAIT signal outside the expected period has no impact on SMC behavior.
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27.13.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal,
the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When
the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the
point where it was stopped. See Figure 27-25. This mode must be selected when the external device uses the
NWAIT signal to delay the access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 27-26.
Figure 27-25. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[23:0]
FROZEN STATE
4
3
2
1
1
1
1
0
3
2
2
2
2
1
NWE
6
5
4
NCS
D[7:0]
NWAIT
internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
520
SAM4CM Series [DATASHEET]
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0
Figure 27-26. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[23:0]
FROZEN STATE
NCS
NRD
4
1
3
2
2
2
1
0
2
1
0
2
1
0
0
5
5
5
4
3
NWAIT
internally synchronized
NWAIT signal
Read cycle
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE =5, NCS_RD_HOLD =3
Assertion is ignored
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27.13.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by
down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse
phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 27-27 and Figure 27-28. After deassertion, the
access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability
to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the
controlling read/write signal, it has no impact on the access length as shown in Figure 27-28.
Figure 27-27. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
MCK
A[23:0]
Wait STATE
4
3
2
1
0
0
0
3
2
1
1
1
NWE
6
5
4
NCS
D[7:0]
NWAIT
internally synchronized
NWAIT signal
Write cycle
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
522
SAM4CM Series [DATASHEET]
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0
Figure 27-28. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)
MCK
A[23:0]
Wait STATE
6
5
4
3
2
1
0
0
6
5
4
3
2
1
1
NCS
NRD
0
NWAIT
internally synchronized
NWAIT signal
Read cycle
Assertion is ignored
EXNW_MODE = 11(Ready mode)
READ_MODE = 0 (NCS_controlled)
Assertion is ignored
NRD_PULSE = 7
NCS_RD_PULSE =7
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27.13.4 NWAIT Latency and Read/Write Timings
There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT
signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to
this latency plus the 2 cycles of resynchronization + one cycle. Otherwise, the SMC may enter the hold state of the
access without detecting the NWAIT signal assertion. This is true in Frozen mode as well as in Ready mode. This
is illustrated on Figure 27-29.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write
controlling signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + one cycle
Figure 27-29. NWAIT Latency
MCK
A[23:0]
WAIT STATE
4
3
2
1
0
NRD
minimal pulse length
NWAIT
intenally synchronized
NWAIT signal
NWAIT latency
2 cycle resynchronization
Read cycle
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
524
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0
0
27.14 Slow Clock Mode
The SMC is able to automatically apply a set of “Slow clock mode” read/write waveforms when an internal signal
driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate
(typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the Slow clock mode
waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate
waveforms at very slow clock rate. When activated, the Slow mode is active on all chip selects.
27.14.1 Slow Clock Mode Waveforms
Figure 27-30 illustrates the read and write operations in Slow clock mode. They are valid on all chip selects. Table
27-6 indicates the value of read and write parameters in Slow clock mode.
Figure 27-30.
Read/Write Cycles in Slow Clock Mode
MCK
MCK
A[23:0]
A[23:0]
NWE
1
NRD
1
1
1
1
NCS
NCS
NRD_CYCLE = 2
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Table 27-6.
SLOW CLOCK MODE READ
Read and Write Timing Parameters in Slow Clock Mode
Read Parameters
Duration (cycles)
Write Parameters
Duration (cycles)
NRD_SETUP
1
NWE_SETUP
1
NRD_PULSE
1
NWE_PULSE
1
NCS_RD_SETUP
0
NCS_WR_SETUP
0
NCS_RD_PULSE
2
NCS_WR_PULSE
3
NRD_CYCLE
2
NWE_CYCLE
3
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27.14.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from Slow clock mode to Normal mode, the current Slow clock mode transfer is completed at high
clock rate, with the set of Slow clock mode parameters.See Figure 27-31. The external device may not be fast
enough to support such timings.
Figure 27-32 illustrates the recommended procedure to properly switch from one mode to the other.
Figure 27-31. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Slow Clock Mode
internal signal from PMC
MCK
A[23:0]
NWE
1
1
1
1
1
1
3
2
2
NCS
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
NWE_CYCLE = 7
SLOW CLOCK MODE WRITE
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
NORMAL MODE WRITE
Slow clock mode
transition is detected:
Reload Configuration Wait State
Figure 27-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock
Mode
Slow Clock Mode
internal signal from PMC
MCK
A[23:0]
NWE
1
1
1
3
2
2
NCS
SLOW CLOCK MODE WRITE
IDLE STATE
NORMAL MODE WRITE
Reload Configuration
Wait State
526
SAM4CM Series [DATASHEET]
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27.15 Asynchronous Page Mode
The SMC supports asynchronous burst reads in Page mode, providing that the Page mode is enabled in the
SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4,
8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always
aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the
address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table
27-7.
With Page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to
the page (tsa) as shown in Figure 27-33. When in Page mode, the SMC enables the user to define different read
timings for the first access within one page, and next accesses within the page.
Table 27-7.
Page Address and Data Address within a Page
Page Size
Page Address(1)
Data Address in the Page
4 bytes
A[23:2]
A[1:0]
8 bytes
A[23:3]
A[2:0]
16 bytes
A[23:4]
A[3:0]
32 bytes
A[23:5]
A[4:0]
Note:
1.
“A” denotes the address bus of the memory device.
27.15.1 Protocol and Timings in Page Mode
Figure 27-33 shows the NRD and NCS timings in Page mode access.
Figure 27-33. Page Mode Read Protocol (Address MSB and LSB are defined in Table 27-7)
MCK
A[MSB]
A[LSB]
NRD
NCS
tpa
tsa
tsa
D[7:0]
NCS_RD_PULSE
NRD_PULSE
NRD_PULSE
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup
and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length
of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse
length of subsequent accesses within the page are defined using the NRD_PULSE parameter.
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527
In Page mode, the programming of the read timings is described in Table 27-8:
Table 27-8.
Programming of Read Timings in Page Mode
Parameter
Value
Definition
READ_MODE
‘x’
No impact
NCS_RD_SETUP
‘x’
No impact
NCS_RD_PULSE
tpa
Access time of first access to the page
NRD_SETUP
‘x’
No impact
NRD_PULSE
tsa
Access time of subsequent accesses in the page
NRD_CYCLE
‘x’
No impact
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page
access timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if the programmed value for tpa is
shorter than the programmed value for tsa.
27.15.2 Page Mode Restriction
The Page mode is not compatible with the use of the NWAIT signal. Using the Page mode and the NWAIT signal
may lead to unpredictable behavior.
27.15.3 Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 27-7 are identical, then the current access lies in
the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum
access time (tsa). Figure 27-34 illustrates access to an 8-bit memory device in Page mode, with 8-byte pages.
Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not
sequential accesses, only require a short access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip
select is different from the previous access, a page break occurs. If two sequential accesses are made to the Page
mode memory, but separated by an other internal or external peripheral access, a page break occurs on the
second access because the chip select of the device was deasserted between both accesses.
528
SAM4CM Series [DATASHEET]
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Figure 27-34.
Access to Non-Sequential Data within the Same Page
MCK
Page address
A[23:3]
A[2], A1, A0
A1
A3
A7
NRD
NCS
D[7:0]
D1
NCS_RD_PULSE
D3
NRD_PULSE
D7
NRD_PULSE
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27.16 Static Memory Controller (SMC) User Interface
The SMC is programmed using the registers listed in Table 27-9. For each chip select, a set of four registers is used to program the parameters of the external device connected on it. In Table 27-9, “CS_number” denotes the chip select number.
16 bytes (0x10) are required per chip select.
The user must complete writing the configuration by writing any one of the SMC_MODE registers.
Table 27-9.
Register Mapping
Offset
Register
Name
Access
Reset
0x10 x CS_number + 0x00
SMC Setup Register
SMC_SETUP
Read/Write
0x01010101
0x10 x CS_number + 0x04
SMC Pulse Register
SMC_PULSE
Read/write
0x01010101
0x10 x CS_number + 0x08
SMC Cycle Register
SMC_CYCLE
Read/Write
0x00030003
0x10 x CS_number + 0x0C
SMC MODE Register
SMC_MODE
Read/Write
0x10000003
0x80
SMC OCMS MODE Register
SMC_OCMS
Read/Write
0x00000000
0x84
SMC OCMS KEY1 Register
SMC_KEY1
Write Once
0x00000000
0x88
SMC OCMS KEY2 Register
SMC_KEY2
Write Once
0x00000000
0xE4
SMC Write Protection Mode Register
SMC_WPMR
Read/Write
0x00000000
0xE8
SMC Write Protection Status Register
SMC_WPSR
Read-only
0x00000000
0xEC-0xFC
Reserved
–
–
–
Notes:
530
1. All unlisted offset values are considered as ‘reserved’.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
27.16.1 SMC Setup Register
Name:
SMC_SETUP[0..3]
Address:
0x400E0000 (0)[0], 0x400E0010 (0)[1], 0x400E0020 (0)[2], 0x400E0030 (0)[3], 0x4801C000 (1)[0],
0x4801C010 (1)[1], 0x4801C020 (1)[2], 0x4801C030 (1)[3]
Access:
Read/Write
31
–
30
–
29
28
27
26
NCS_RD_SETUP
25
24
23
–
22
–
21
20
19
18
17
16
15
–
14
–
13
12
11
10
NCS_WR_SETUP
9
8
7
–
6
–
5
4
3
1
0
NRD_SETUP
2
NWE_SETUP
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• NWE_SETUP: NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
• NCS_WR_SETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
• NRD_SETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
• NCS_RD_SETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
SAM4CM Series [DATASHEET]
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531
27.16.2 SMC Pulse Register
Name:
SMC_PULSE[0..3]
Address:
0x400E0004 (0)[0], 0x400E0014 (0)[1], 0x400E0024 (0)[2], 0x400E0034 (0)[3], 0x4801C004 (1)[0],
0x4801C014 (1)[1], 0x4801C024 (1)[2], 0x4801C034 (1)[3]
Access:
Read/Write
31
–
30
29
28
27
NCS_RD_PULSE
26
25
24
23
–
22
21
20
19
NRD_PULSE
18
17
16
15
–
14
13
12
11
NCS_WR_PULSE
10
9
8
7
–
6
5
4
3
NWE_PULSE
2
1
0
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• NWE_PULSE: NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.
• NCS_WR_PULSE: NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
• NRD_PULSE: NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In Page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.
• NCS_RD_PULSE: NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
In Page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
532
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
27.16.3 SMC Cycle Register
Name:
SMC_CYCLE[0..3]
Address:
0x400E0008 (0)[0], 0x400E0018 (0)[1], 0x400E0028 (0)[2], 0x400E0038 (0)[3], 0x4801C008 (1)[0],
0x4801C018 (1)[1], 0x4801C028 (1)[2], 0x4801C038 (1)[3]
Access:
Read/Write
31
–
30
–
29
–
28
–
23
22
21
20
27
–
26
–
25
–
24
NRD_CYCLE
19
18
17
16
11
–
10
–
9
–
8
NWE_CYCLE
3
2
1
0
NRD_CYCLE
15
–
14
–
13
–
12
–
7
6
5
4
NWE_CYCLE
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• NWE_CYCLE: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse
and hold steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse
and hold steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
SAM4CM Series [DATASHEET]
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533
27.16.4 SMC MODE Register
Name:
SMC_MODE[0..3]
Address:
0x400E000C (0)[0], 0x400E001C (0)[1], 0x400E002C (0)[2], 0x400E003C (0)[3], 0x4801C00C (1)[0],
0x4801C01C (1)[1], 0x4801C02C (1)[2], 0x4801C03C (1)[3]
Access:
Read/Write
31
–
30
–
29
28
27
–
26
–
25
–
23
–
22
–
21
–
20
TDF_MODE
19
18
17
TDF_CYCLES
15
–
14
–
13
–
12
DBW
11
–
10
–
9
–
8
BAT
7
–
6
–
5
4
3
–
2
–
1
WRITE_MODE
0
READ_MODE
PS
EXNW_MODE
24
PMEN
16
This register can only be written if the WPEN bit is cleared in the “SMC Write Protection Mode Register” .
• READ_MODE: Read Mode
0: The read operation is controlled by the NCS signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
1: The read operation is controlled by the NRD signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
• WRITE_MODE: Write Mode
0: The write operation is controlled by the NCS signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
1: The write operation is controlled by the NWE signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.
Value
Name
Description
0
DISABLED
Disabled
1
–
Reserved
2
FROZEN
Frozen Mode
3
READY
Ready Mode
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
534
SAM4CM Series [DATASHEET]
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• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
•
BAT: Byte Access Type
This field is used only if DBW defines a 16-bit data bus.
Value
Name
Description
Byte select access type:
0
BYTE_SELECT
- Write operation is controlled using NCS, NWE, NBS0, NBS1.
- Read operation is controlled using NCS, NRD, NBS0, NBS1.
Byte write access type:
1
BYTE_WRITE
- Write operation is controlled using NCS, NWR0, NWR1.
- Read operation is controlled using NCS and NRD.
• DBW: Data Bus Width
Value
Name
Description
0
8_BIT
8-bit Data Bus
1
16_BIT
16-bit Data Bus
• TDF_CYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge
of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The
external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can
be set.
• TDF_MODE: TDF Optimization
0: TDF optimization is disabled.
– The number of TDF wait states is inserted before the next access begins.
1: TDF optimization is enabled.
– The number of TDF wait states is optimized using the setup period of the next read/write access.
•
PMEN: Page Mode Enabled
0: Standard read is applied.
1: Asynchronous burst read in Page mode is applied on the corresponding chip select.
• PS: Page Size
If Page mode is enabled, this field indicates the size of the page in bytes.
Value
Name
Description
0
4_BYTE
4-byte page
1
8_BYTE
8-byte page
2
16_BYTE
16-byte page
3
32_BYTE
32-byte page
SAM4CM Series [DATASHEET]
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535
27.16.5 SMC OCMS Mode Register
Name:
SMC_OCMS
Address:
0x400E0080 (0), 0x4801C080 (1)
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
CS3SE
18
CS2SE
17
CS1SE
16
CS0SE
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
SMSE
• CSxSE: Chip Select (x = 0 to 3) Scrambling Enable
0: Disable scrambling for CSx.
1: Enable scrambling for CSx.
• SMSE: Static Memory Controller Scrambling Enable
0: Disable scrambling for SMC access.
1: Enable scrambling for SMC access.
536
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
27.16.6 SMC OCMS Key1 Register
Name:
SMC_KEY1
Address:
0x400E0084 (0), 0x4801C084 (1)
Access:
Write Once
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
KEY1
23
22
21
20
KEY1
15
14
13
12
KEY1
7
6
5
4
KEY1
• KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1
When off-chip memory scrambling is enabled, setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the
data scrambling depends on KEY1 and KEY2 values.
SAM4CM Series [DATASHEET]
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537
27.16.7 SMC OCMS Key2 Register
Name:
SMC_KEY2
Address:
0x400E0088 (0), 0x4801C088 (1)
Access:
Write Once
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
KEY2
23
22
21
20
KEY2
15
14
13
12
KEY2
7
6
5
4
KEY2
• KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2
When off-chip memory scrambling is enabled, setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the
data scrambling depends on KEY2 and KEY1 values.
538
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
27.16.8 SMC Write Protection Mode Register
Name:
SMC_WPMR
Address:
0x400E00E4 (0), 0x4801C0E4 (1)
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
—
2
—
1
—
0
WPEN
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
—
6
—
5
—
4
—
• WPEN: Write Protect Enable
0: Disables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
See Section 27.9.5 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
Value
Name
0x534D43
PASSWD
Description
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads
as 0.
SAM4CM Series [DATASHEET]
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539
27.16.9 SMC Write Protection Status Register
Name:
SMC_WPSR
Address:
0x400E00E8 (0), 0x4801C0E8 (1)
Type:
Read-only
31
—
30
—
29
—
28
—
27
—
26
—
25
—
24
—
23
22
21
20
19
18
17
16
11
10
9
8
3
—
2
—
1
—
0
WPVS
WPVSRC
15
14
13
12
WPVSRC
7
—
6
—
5
—
4
—
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of the SMC_WPSR register.
1: A write protection violation has occurred since the last read of the SMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
540
SAM4CM Series [DATASHEET]
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28.
Peripheral DMA Controller (PDC)
28.1
Description
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the target memories.
The link between the PDC and a serial peripheral is operated by the AHB to APB bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user
interface of mono-directional channels (receive-only or transmit-only) contains two 32-bit memory pointers and two
16-bit counters, one set (pointer, counter) for the current transfer and one set (pointer, counter) for the next
transfer. The bidirectional channel user interface contains four 32-bit memory pointers and four 16-bit counters.
Each set (pointer, counter) is used by the current transmit, next transmit, current receive and next receive.
Using the PDC decreases processor overhead by reducing its intervention during the transfer. This lowers
significantly the number of clock cycles required for a data transfer, improving microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals.
When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
28.2
Embedded Characteristics
Performs Transfers to/from APB Communication Serial Peripherals
Supports Half-duplex and Full-duplex Peripherals
SAM4CM Series [DATASHEET]
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541
28.3
Block Diagram
Figure 28-1.
Block Diagram
FULL DUPLEX
PERIPHERAL
PDC
THR
PDC Channel A
RHR
PDC Channel B
Control
Status & Control
HALF DUPLEX
PERIPHERAL
Control
THR
PDC Channel C
RHR
Control
Status & Control
RECEIVE or TRANSMIT
PERIPHERAL
RHR or THR
Control
542
PDC Channel D
Status & Control
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
28.4
Functional Description
28.4.1 Configuration
The PDC channel user interface enables the user to configure and control data transfers for each channel. The
user interface of each PDC channel is integrated into the associated peripheral user interface.
The user interface of a serial peripheral, whether it is full- or half-duplex, contains four 32-bit pointers (RPR,
RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and
receive parts of each type are programmed differently: the transmit and receive parts of a full-duplex peripheral
can be programmed at the same time, whereas only one part (transmit or receive) of a half-duplex peripheral can
be programmed at a time.
32-bit pointers define the access location in memory for the current and next transfer, whether it is for read
(transmit) or write (receive). 16-bit counters define the size of the current and next transfers. It is possible, at any
moment, to read the number of transfers remaining for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The
status for each channel is located in the associated peripheral status register. Transfers can be enabled and/or
disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in
the peripheral Status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 28.4.3 and to the
associated peripheral user interface.
The peripheral where a PDC transfer is configured must have its peripheral clock enabled. The peripheral clock
must be also enabled to access the PDC register set associated to this peripheral.
28.4.2 Memory Pointers
Each full-duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels
have 32-bit memory pointers that point to a receive area and to a transmit area, respectively, in the target memory.
Each half-duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit
memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or
receive data depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1,
2 or 4 bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the
new address.
28.4.3 Transfer Counters
Each channel has two 16-bit counters, one for the current transfer and the one for the next transfer. These
counters define the size of data to be transferred by the channel. The current transfer counter is decremented first
as the data addressed by the current memory pointer starts to be transferred. When the current transfer counter
reaches zero, the channel checks its next transfer counter. If the value of the next counter is zero, the channel
stops transferring data and sets the appropriate flag. If the next counter value is greater than zero, the values of
the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the
transfer, whereas next pointer/next counter get zero/zero as values.At the end of this transfer, the PDC channel
sets the appropriate flags in the Peripheral Status register.
The following list gives an overview of how status register flags behave depending on the counters’ values:
ENDRX flag is set when the PDC Receive Counter Register (PERIPH_RCR) reaches zero.
RXBUFF flag is set when both PERIPH_RCR and the PDC Receive Next Counter Register
(PERIPH_RNCR) reach zero.
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543
ENDTX flag is set when the PDC Transmit Counter Register (PERIPH_TCR) reaches zero.
TXBUFE flag is set when both PERIPH_TCR and the PDC Transmit Next Counter Register
(PERIPH_TNCR) reach zero.
These status flags are described in the Transfer Status Register (PERIPH_PTSR).
28.4.4 Data Transfers
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive
enable (RXEN) flags in the transfer control register integrated in the peripheral’s user interface.
When the peripheral receives external data, it sends a Receive Ready signal to its PDC receive channel which
then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the
peripheral Receive Holding register (RHR). The read data are stored in an internal buffer and then written to
memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then
requests access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and
transfers the data to the Transmit Holding register (THR) of its associated peripheral. The same peripheral sends
data depending on its mechanism.
28.4.5 PDC Flags and Peripheral Status Register
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC returns flags
to the peripheral. All these flags are only visible in the peripheral’s Status register.
Depending on whether the peripheral is half- or full-duplex, the flags belong to either one single channel or two
different channels.
28.4.5.1 Receive Transfer End
The receive transfer end flag is set when PERIPH_RCR reaches zero and the last data has been transferred to
memory.
This flag is reset by writing a non-zero value to PERIPH_RCR or PERIPH_RNCR.
28.4.5.2 Transmit Transfer End
The transmit transfer end flag is set when PERIPH_TCR reaches zero and the last data has been written to the
peripheral THR.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
28.4.5.3 Receive Buffer Full
The receive buffer full flag is set when PERIPH_RCR reaches zero, with PERIPH_RNCR also set to zero and the
last data transferred to memory.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
28.4.5.4 Transmit Buffer Empty
The transmit buffer empty flag is set when PERIPH_TCR reaches zero, with PERIPH_TNCR also set to zero and
the last data written to peripheral THR.
This flag is reset by writing a non-zero value to PERIPH_TCR or PERIPH_TNCR.
544
SAM4CM Series [DATASHEET]
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28.5
Peripheral DMA Controller (PDC) User Interface
Table 28-1.
Offset
Register Mapping
Register
Name
(1)
Access
Reset
0x00
Receive Pointer Register
PERIPH _RPR
Read/Write
0
0x04
Receive Counter Register
PERIPH_RCR
Read/Write
0
0x08
Transmit Pointer Register
PERIPH_TPR
Read/Write
0
0x0C
Transmit Counter Register
PERIPH_TCR
Read/Write
0
0x10
Receive Next Pointer Register
PERIPH_RNPR
Read/Write
0
0x14
Receive Next Counter Register
PERIPH_RNCR
Read/Write
0
0x18
Transmit Next Pointer Register
PERIPH_TNPR
Read/Write
0
0x1C
Transmit Next Counter Register
PERIPH_TNCR
Read/Write
0
0x20
Transfer Control Register
PERIPH_PTCR
Write-only
–
0x24
Transfer Status Register
PERIPH_PTSR
Read-only
0
Note:
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
depending on the function and the desired peripheral.
SAM4CM Series [DATASHEET]
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545
28.5.1 Receive Pointer Register
Name:
PERIPH_RPR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RXPTR
23
22
21
20
RXPTR
15
14
13
12
RXPTR
7
6
5
4
RXPTR
• RXPTR: Receive Pointer Register
RXPTR must be set to receive buffer address.
When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
546
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
28.5.2 Receive Counter Register
Name:
PERIPH_RCR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
RXCTR
7
6
5
4
RXCTR
• RXCTR: Receive Counter Register
RXCTR must be set to receive buffer size.
When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0: Stops peripheral data transfer to the receiver.
1–65535: Starts peripheral data transfer if the corresponding channel is active.
SAM4CM Series [DATASHEET]
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547
28.5.3 Transmit Pointer Register
Name:
PERIPH_TPR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
TXPTR
23
22
21
20
TXPTR
15
14
13
12
TXPTR
7
6
5
4
TXPTR
• TXPTR: Transmit Counter Register
TXPTR must be set to transmit buffer address.
When a half-duplex peripheral is connected to the PDC, RXPTR = TXPTR.
548
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
28.5.4 Transmit Counter Register
Name:
PERIPH_TCR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
TXCTR
7
6
5
4
TXCTR
• TXCTR: Transmit Counter Register
TXCTR must be set to transmit buffer size.
When a half-duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0: Stops peripheral data transfer to the transmitter.
1–65535: Starts peripheral data transfer if the corresponding channel is active.
SAM4CM Series [DATASHEET]
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549
28.5.5 Receive Next Pointer Register
Name:
PERIPH_RNPR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RXNPTR
23
22
21
20
RXNPTR
15
14
13
12
RXNPTR
7
6
5
4
RXNPTR
• RXNPTR: Receive Next Pointer
RXNPTR contains the next receive buffer address.
When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
550
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
28.5.6 Receive Next Counter Register
Name:
PERIPH_RNCR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
RXNCTR
7
6
5
4
RXNCTR
• RXNCTR: Receive Next Counter
RXNCTR contains the next receive buffer size.
When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
SAM4CM Series [DATASHEET]
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551
28.5.7 Transmit Next Pointer Register
Name:
PERIPH_TNPR
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
TXNPTR
23
22
21
20
TXNPTR
15
14
13
12
TXNPTR
7
6
5
4
TXNPTR
• TXNPTR: Transmit Next Pointer
TXNPTR contains the next transmit buffer address.
When a half-duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
552
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
28.5.8 Transmit Next Counter Register
Name:
PERIPH_TNCR
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
TXNCTR
7
6
5
4
TXNCTR
• TXNCTR: Transmit Counter Next
TXNCTR contains the next transmit buffer size.
When a half-duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
SAM4CM Series [DATASHEET]
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553
28.5.9 Transfer Control Register
Name:
PERIPH_PTCR
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
TXTDIS
8
TXTEN
7
–
6
–
5
–
4
–
3
–
2
–
1
RXTDIS
0
RXTEN
• RXTEN: Receiver Transfer Enable
0: No effect.
1: Enables PDC receiver channel requests if RXTDIS is not set.
When a half-duplex peripheral is connected to the PDC, enabling the receiver channel requests automatically disables the
transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half-duplex peripheral.
• RXTDIS: Receiver Transfer Disable
0: No effect.
1: Disables the PDC receiver channel requests.
When a half-duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the transmitter channel requests.
• TXTEN: Transmitter Transfer Enable
0: No effect.
1: Enables the PDC transmitter channel requests.
When a half-duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not
set. It is forbidden to set both TXTEN and RXTEN for a half-duplex peripheral.
• TXTDIS: Transmitter Transfer Disable
0: No effect.
1: Disables the PDC transmitter channel requests.
When a half-duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver
channel requests.
554
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
28.5.10 Transfer Status Register
Name:
PERIPH_PTSR
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
TXTEN
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
RXTEN
• RXTEN: Receiver Transfer Enable
0: PDC receiver channel requests are disabled.
1: PDC receiver channel requests are enabled.
• TXTEN: Transmitter Transfer Enable
0: PDC transmitter channel requests are disabled.
1: PDC transmitter channel requests are enabled.
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29.
Clock Generator
29.1
Description
The Clock Generator user interface is embedded within the Power Management Controller and is described in
Section 30.18 "Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are
named CKGR_.
29.2
Embedded Characteristics
The Clock Generator is made up of:
A low-power 32.768 kHz crystal oscillator with Bypass mode
A low-power embedded 32 kHz (typical) RC oscillator
A 3 to 20 MHz crystal or ceramic resonator-based oscillator, which can be bypassed.
A factory-trimmed embedded RC oscillator. Three output frequencies can be selected: 4/8/12 MHz. By
default 4 MHz is selected.
Two programmable PLLs, (PLLA input from 32 kHz, output clock range 8 MHz and PLLB input from 3 to 32
MHz, output clock range 80 to 240 MHz), capable of providing the clock MCK to the processor and to the
peripherals.
It provides the following clocks:
556
SLCK, the slow clock, which is the only permanent clock within the system.
MAINCK is the output of the main clock oscillator selection: either the crystal or ceramic resonator-based
oscillator or 4/8/12 MHz RC oscillator.
PLLACK is the output of the 8 MHz programmable PLL (PLLA).
PLLBCK is the output of the divider and 80 to 240 MHz programmable PLL (PLLB).
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29.3
Block Diagram
Figure 29-1.
Clock Generator Block Diagram
Clock Generator
XTALSEL
(Supply Controller)
Embedded
32 kHz
RC Oscillator
0
Slow Clock
SLCK
XIN32
XOUT32
32.768 kHz
Crystal
Oscillator
1
CKGR_MOR
MOSCSEL
Embedded
4/8/12 MHz
RC Oscillator
XIN
XOUT
0
Main Clock
MAINCK
3–20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
1
PLLA
PLLADIV2
PLLA Clock
PLLACK
PMC_MCKR
1
PLLB and
Divider /2
PLLB Clock
PLLBCK
0
Status
SRCB
PLLBDIV2
CKGR_PLLBR
PMC_MCKR
Control
Power
Management
Controller
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29.4
Slow Clock
The Supply Controller embeds a slow clock generator that is supplied with the VDDBU power supply. As soon as
VDDBU is supplied, both the 32.768 kHz crystal oscillator and the embedded 32 kHz (typical) RC oscillator are
powered up, but only the RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100
µs).
The slow clock is generated either by the 32.768 kHz crystal oscillator or by the embedded 32 kHz (typical) RC
oscillator.
The selection of the slow clock source is made via the XTALSEL bit in the Supply Controller Control Register
(SUPC_CR).
The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) and the OSCSEL bit of the PMC Status
Register (PMC_SR) report which oscillator is selected as the slow clock source. PMC_SR.OSCSEL informs when
the switch sequence initiated by a new value written in SUPC_CR.XTALSEL is done.
29.4.1 Embedded 32 kHz (typical) RC Oscillator
By default, the embedded 32 kHz (typical) RC oscillator is enabled and selected. The user has to take into account
the possible drifts of this oscillator. More details are given in the section “DC Characteristics”.
This oscillator is disabled by clearing the SUPC_CR.XTALSEL.
29.4.2 32.768 kHz Crystal Oscillator
The Clock Generator integrates a low-power 32.768 kHz crystal oscillator. To use this oscillator, the XIN32 and
XOUT32 pins must be connected to a 32.768 kHz crystal. Two external capacitors must be wired as shown in
Figure 29-2. More details are given in the section “DC Characteristics”.
Note that the user is not obliged to use the 32.768 kHz crystal oscillator and can use the 32 kHz (typical) RC
oscillator instead.
Figure 29-2.
Typical 32768 Crystal Oscillator Connection
XIN32
XOUT32
GND
32.768 kHz
Crystal
The 32.768 kHz crystal oscillator provides a more accurate frequency than the 32 kHz (typical) RC oscillator.
To select the 32.768 kHz crystal oscillator as the source of the slow clock, the bit SUPC_CR.XTALSEL must be
set. This results in a sequence which enables the 32.768 kHz crystal oscillator and then disables the 32 kHz
(typical) RC oscillator to save power. The switch of the slow clock source is glitch-free.
Reverting to the 32 kHz (typical) RC oscillator is only possible by shutting down the VDDBU power supply. If the
user does not need the 32.768 kHz crystal oscillator, the XIN32 and XOUT32 pins can be left unconnected.
The user can also set the 32.768 kHz crystal oscillator in Bypass mode instead of connecting a crystal. In this
case, the user must provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are
given in the section “Electrical Characteristics”. To enter Bypass mode, the OSCBYPASS bit of the Supply
Controller Mode Register (SUPC_MR) must be set prior to setting SUPC_CR.XTALSEL.
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29.5
Main Clock
Figure 29-3 shows the main clock block diagram.
Figure 29-3.
Main Clock Block Diagram
CKGR_MOR
MOSCRCEN
CKGR_MOR
MOSCRCF
PMC_SR
MOSCRCS
Fast RC
Oscillator
CKGR_MOR
PMC_SR
MOSCSEL
MOSCSELS
0
CKGR_MOR
MAINCK
Main Clock
MOSCXTEN
1
3–20 MHz
Crystal
or
Ceramic Resonator
Oscillator
XIN
XOUT
CKGR_MOR
MOSCXTST
PMC_SR
3–20 MHz
Oscillator
Counter
SLCK
Slow Clock
MOSCXTS
CKGR_MOR
MOSCRCEN
CKGR_MOR
CKGR_MCFR
MOSCXTEN
RCMEAS
CKGR_MOR
MOSCSEL
CKGR_MCFR
MAINCK
Main Clock
Ref.
MAINF
Main Clock
Frequency
Counter
CKGR_MCFR
MAINFRDY
The main clock has two sources:
A 4/8/12 MHz RC oscillator with a fast start-up time and that is selected by default to start the system
A 3 to 20 MHz crystal or ceramic resonator-based oscillator which can be bypassed
29.5.1 Embedded 4/8/12 MHz RC Oscillator
After reset, the 4/8/12 MHz RC oscillator is enabled with the 4 MHz frequency selected. This oscillator is selected
as the source of MAINCK. MAINCK is the default clock selected to start the system.
The 4/8/12 MHz RC oscillator frequencies are calibrated in production except for the lowest frequency which is not
calibrated.
Refer to “DC Characteristics” in Section 46. "Electrical Characteristics”.
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The software can disable or enable the 4/8/12 MHz RC oscillator with the MOSCRCEN bit in the Clock Generator
Main Oscillator Register (CKGR_MOR).
The output frequency of the RC oscillator can be selected among 4/8/12 MHz. The selection is done via the
CKGR_MOR.MOSCRCF field. When changing the frequency selection, the MOSCRCS bit in the Power
Management Controller Status Register (PMC_SR) is automatically cleared and MAINCK is stopped until the
oscillator is stabilized. Once the oscillator is stabilized, MAINCK restarts and PMC_SR.MOSCRCS is set.
When disabling the main clock by clearing the CKGR_MOR.MOSCRCEN bit, the PMC_SR.MOSCRCS bit is
automatically cleared, indicating the main clock is off.
Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger
an interrupt to the processor.
When main clock (MAINCK) is not used to drive the processor and frequency monitor (SLCK or PLLACK is used
instead), it is recommended to disable the 4/8/12 MHz RC oscillator and 3 to 20 MHz crystal oscillator.
The CAL4, CAL8 and CAL12 values in the PMC Oscillator Calibration Register (PMC_OCR) are the default values
set by Atmel during production. These values are stored in a specific Flash memory area different from the
memory plane for code. These values cannot be modified by the user and cannot be erased by a Flash erase
command or by the ERASE pin. Values written by the user application in PMC_OCR are reset after each power up
or peripheral reset.
29.5.2 4/8/12 MHz RC Oscillator Clock Frequency Adjustment
It is possible for the user to adjust the 4/8/12 MHz RC oscillator frequency through PMC_OCR. By default,
SEL4/8/12 bits are cleared, so the RC oscillator will be driven with Flash calibration bits which are programmed
during chip production.
The user can adjust the trimming of the 4/8/12 MHz RC oscillator through this register. This can be used to
compensate derating factors such as temperature and voltage, thus providing greater accuracy.
In order to calibrate the RC oscillator lower frequency, SEL4 bit must be set to 1 and a frequency value must be
configured in the field CAL4. Likewise, SEL8/12 bit must be set to 1 and a trim value must be configured in the field
CAL8/12 in order to adjust the other frequencies of the RC oscillator.
It is possible to adjust the RC oscillator frequency while operating from this clock. For example, when running on
lowest frequency it is possible to change the CAL4 value if PMC_OCR.SEL4 bit is set.
At any time, it is possible to restart a measurement of the frequency of the selected clock via the RCMEAS bit in
Main Clock Frequency Register (CKGR_MCFR). Thus, when CKGR_MCFR.MAINFRDY reads 1, another read
access on CKGR_MCFR provides an image of the frequency on CKGR_MCFR.MAINF field. The software can
calculate the error with an expected frequency and correct the CAL4 (or CAL8/CAL12) field accordingly. This may
be used to compensate frequency drift due to derating factors such as temperature and/or voltage.
29.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator
After reset, the 3 to 20 MHz crystal or ceramic resonator-based oscillator is disabled and is not selected as the
source of MAINCK.
As the source of MAINCK, the 3 to 20 MHz crystal or ceramic resonator-based oscillator provides a very precise
frequency. The software enables or disables this oscillator in order to reduce power consumption via
CKGR_MOR.MOSCXTEN.
When disabling this oscillator by clearing the CKGR_MOR.MOSCXTEN, PMC_SR.MOSCXTS is automatically
cleared, indicating the 3 to 20 MHz crystal oscillator is off.
When enabling this oscillator, the user must initiate the start-up time counter. The start-up time depends on the
characteristics of the external device connected to this oscillator.
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When CKGR_MOR.MOSCXTEN and CKGR_MOR.MOSCXTST are written to enable this oscillator, the XIN and
XOUT pins are automatically switched into Oscillator mode. PMC_SR.MOSCXTS is cleared and the counter starts
counting down on the slow clock divided by 8 from the CKGR_MOR.MOSCXTST value. Since the
CKGR_MOR.MOSCXTST value is coded with 8 bits, the maximum start-up time is about 62 ms.
When the start-up time counter reaches 0, PMC_SR.MOSCXTS is set, indicating that the 3 to 20 MHz crystal
oscillator is stabilized. Setting the MOSCXTS bit in the Interrupt Mask Register (PMC_IMR) can trigger an interrupt
to the processor.
29.5.4 Main Clock Source Selection
The user can select the source of the main clock from either the 4/8/12 MHz RC oscillator, the 3 to 20 MHz crystal
oscillator or the ceramic resonator-based oscillator.
The advantage of the 4/8/12 MHz RC oscillator is its fast start-up time. By default, this oscillator is selected to start
the system and when entering Wait mode.
The advantage of the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator is its precise frequency.
The selection of the oscillator is made by writing CKGR_MOR.MOSCSEL. The switch of the main clock source is
glitch-free, so there is no need to run out of SLCK, PLLACK or PLLBCK in order to change the selection.
PMC_SR.MOSCSELS indicates when the switch sequence is done.
Setting PMC_IMR.MOSCSELS triggers an interrupt to the processor.
Enabling the 4/8/12 MHz RC oscillator (MOSCRCEN = 1) and changing its frequency (MOSCCRF) at the same
time is not allowed.
This oscillator must be enabled first and its frequency changed in a second step.
29.5.5 Bypassing the 3 to 20 MHz Crystal Oscillator
Prior to bypassing the 3 to 20 MHz crystal oscillator, the external clock frequency provided on the XIN pin must be
stable and within the values specified in the XIN Clock characteristics in the section “Electrical Characteristics”.
The sequence is as follows:
1. Ensure that an external clock is connected on XIN.
2.
Enable the bypass by writing a 1 to CKGR_MOR.MOSCXTBY.
3.
Disable the 3 to 20 MHz crystal oscillator by writing a 0 to bit CKGR_MOR.MOSCXTEN.
29.5.6 Main Clock Frequency Counter
The frequency counter is managed by CKGR_MCFR.
During the measurement period, the frequency counter increments at the main clock speed.
A measurement is started in the following cases:
When the RCMEAS bit of CKGR_MCFR is written to 1.
When the 4/8/12 MHz RC oscillator is selected as the source of main clock and when this oscillator becomes
stable (i.e., when the MOSCRCS bit is set)
When the 3 to 20 MHz crystal or ceramic resonator-based oscillator is selected as the source of main clock
and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)
When the main clock source selection is modified
The measurement period ends at the 16th falling edge of slow clock, the MAINFRDY bit in CKGR_MCFR is set
and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of
clock cycles during 16 periods of slow clock, so that the frequency of the 4/8/12 MHz RC oscillator or 3 to 20 MHz
crystal or ceramic resonator-based oscillator can be determined.
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29.5.7 Switching Main Clock between the RC Oscillator and the Crystal Oscillator
When switching the source of the main clock between the RC oscillator and the crystal oscillator, both oscillators
must be enabled. After completion of the switch, the unused oscillator can be disabled.
If switching to the crystal oscillator, a check must be carried out to ensure that the oscillator is present and that its
frequency is valid. Follow the sequence below:
1. Select the slow clock as MCK by configuring bit CSS = 0 in the Master Clock Register (PMC_MCKR)).
2.
Wait for PMC_SR.MCKRDY flag in PMC_SR to rise.
3.
Enable the crystal oscillator by setting CKGR_MOR.MOSCXTEN. Configure the CKGR_MOR. MOSCXTST
field with the crystal oscillator start-up time as defined in the section “Electrical Characteristics”.
4.
Wait for PMC_SR.MOSCXTS flag to rise, indicating the end of a start-up period of the crystal oscillator.
5.
Select the crystal oscillator as the source of the main clock by setting CKGR_MOR.MOSCSEL.
6.
Read CKGR_MOR.MOSCSEL until its value equals 1.
7.
Check the status of PMC_SR.MOSCSELS flag:
̶
If MOSCSELS = 1: There is a crystal oscillator connected.
a. Initiate a new frequency measurement by setting CKGR_MCFR.RCMEAS.
b.
Read CKGR_MCFR.MAINFRDY until its value equals 1.
c.
Read CKGR_MCFR.MAINF and compute the value of the crystal frequency.
d. If the MAINF value is valid, the main clock can be switched to the crystal oscillator.
̶
If MOSCSELS = 0:
a. There is no crystal oscillator connected or the crystal oscillator is out of specification.
b.
29.6
Select the RC oscillator as the source of the main clock by clearing CKGR_MOR.MOSCSEL.
Divider and PLL Block
The device features one divider block and two PLL blocks that permit a wide range of frequencies to be selected
on either the master clock, the processor clock or the programmable clock outputs.
Figure 29-4 shows the block diagram of the divider and PLL blocks.
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Figure 29-4.
Dividers and PLL Block Diagram
CKGR_PLLBR
SRCB
MAINCK
CKGR_PLLBR
CKGR_PLLBR
DIVB
MULB
0
Divider B
PLL B
PLLBCK
1
PLLBDIV2
PMC_MCKR
CKGR_PLLAR
MULA
PMC_MCKR
SLCK
PLLADIV2
PLL A
PLLACK
CKGR_PLLBR
PLLBCOUNT
PLL B
Counter
PMC_SR
LOCKB
CKGR_PLLAR
PLLACOUNT
PLL A
Counter
SLCK
PMC_SR
LOCKA
29.6.1 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is cleared, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is cleared, thus
the corresponding PLL input clock is stuck at 0.
The PLLs (PLLA, PLLB) allow multiplication of the SLCK clock source for PLLA or divided MAINCK or PLLA output
clock for PLLB. The PLL clock signal has a frequency that depends on the respective source signal frequency and
on the parameters DIV (, DIVB) and MUL (MULA, MULB) and PLLEN (PLLAEN). The factor applied to the source
signal frequency is (MUL + 1)/DIV. When MUL is written to 0 or PLLEN = 0, the PLL is disabled and its power
consumption is saved. Note that there is a delay of two SLCK clock cycles between the disable command and the
real disable of the PLL. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field
and PLLA(B)EN higher than 0.
To change the frequency of the PLLA, the PLLA must be first disabled by writing 0 in the MULA field and 0 in
PLLACOUNT field. Then, wait for two SLCK clock cycles before configuring the PLLA to generate the new
frequency by programming a new multiplier in MULA and the PLLACOUNT field in the same register access. See
Section 46. "Electrical Characteristics” to get the PLLACOUNT values covering the PLL transient time.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA, LOCKB) bit in PMC_SR
is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT, PLLBCOUNT) in CKGR_PLLR
(CKGR_PLLAR, CKGR_PLLBR) are loaded in the PLL counter. The PLL counter then decrements at the speed of
the slow clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the
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processor. The user has to load the number of slow clock cycles required to cover the PLL transient time into the
PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC_MCKR.
The PLLADIV2 has no effect on PLLB clock input because the output of the PLLA is directly routed to PLLB input
selection.
It is prohibited to change the frequency of the 4/8/12 MHz RC oscillator or to change the source of the main clock
in CKGR_MOR while the master clock source is the PLL and the PLL reference clock is the 4/8/12 MHz RC
oscillator.
The user must:
1. Switch on the 4/8/12 MHz RC oscillator by writing a 1 to the CSS field of PMC_MCKR.
564
2.
Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
3.
Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR.
4.
Disable and then enable the PLL.
5.
Wait for the LOCK flag in PMC_SR.
6.
Switch back to the PLL by writing the appropriate value to the CSS field of PMC_MCKR.
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30.
Power Management Controller (PMC)
30.1
Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user
peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Cortex-M4
processor.
The Supply Controller selects either the embedded 32 kHz RC oscillator or the 32.768 kHz crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup, the chip runs out of the master clock using the 4/8/12 MHz RC oscillator running at 4 MHz.
The user can trim the 8 and 12 MHz RC oscillator frequencies by software.
30.2
Embedded Characteristics
The PMC provides the following clocks:
MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the
device. It is available to the modules running permanently, such as the Enhanced Embedded Flash
Controller.
Processor Clock (HCLK) and Coprocessor (second processor) Clock (CPHCLK), automatically switched off
when entering the processor in Sleep Mode
Free-running processor Clock (FCLK) and Free-running Coprocessor Clock (CPFCLK)
One SysTick external clock for each Cortex-M4 core
Peripheral Clocks, provided to the embedded peripherals (USART, SPI, TWI, TC, etc.) and independently
controllable.
Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCK
pins
The PMC also provides the following features on clocks:
A 3 to 20 MHz crystal oscillator clock failure detector
A 32.768 kHz crystal oscillator frequency monitor
A frequency counter on main clockAn on-the-fly adjustable 4/8/12 MHz RC oscillator frequency
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SLCK
Master Clock Controller
(PMC_MCKR)
SYSTICK
Prescaler
Embedded
32 kHz
RC Oscillator
PLLACK
0
FCLK
/1,/2,/3,/4,/8,
SLCK
CSS
XIN32
XOUT32
32.768 kHz
Crystal
Oscillator
Processor
Free Running Clock
/16,/32,/64
PLLBCK
Slow Clock
Processor
SysTick Clock
Divider / 8
MAINCK
MCK
PRES
Peripherals
Clock Controller
(PMC_PCERx /
PMC_PCR)
1
Processor
Bus Master Clock
ON/OFF
periph_clk[n] Where n is an index
for the processor
system peripherals
CKGR_MOR
MOSCSEL
ON/OFF
periph_clk[n+1]
Embedded
4/8/12 MHz
RC Oscillator
XIN
XOUT
0
Main
Clock
MAINCK
ON/OFF
periph_clk[n+2]
Core 0 (CM4-P0 Clock System)
3–20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
1
ON/OFF
periph_clk[m]
SLCK
MAINCK
Where m is an index
for the coprocessor
system peripherals
Master Clock Controller
(PMC_MCKR)
PLLACK
PLLA
PLLADIV2
PLLA Clock
PLLACK
PMC_SCER/SCDR
CPCK= ON/OFF
CPCSS
1
PLLB and
Divider /2
0
SRCB
PLLBDIV2
CKGR_PLLBR
PMC_MCKR
periph_clk[m+2]
Divide by 1 to 16
MCK
PMC_MCKR
ON/OFF
Prescaler
PLLBCK
Coprocessor
Clock
Controller
CPPRES
PLLB Clock
PLLBCK
Sleep Mode
PMC_SCER/SCDR
CPBMCK= ON/OFF
Divider / 8
CPHCLK
CPSYSTICK
CPFCLK
Status
Power
Control
Management
Controller
Coprocessor Clock
int
CPBMCK
Coprocessor
SysTick Clock
Coprocessor
Free Running Clock
Coprocessor
Bus Master Clock
Core 1 (CM4-P1 Clock System)
Block Diagram
Sleep Mode
(Supply Controller)
General Clock Block Diagram
SAM4CM Series [DATASHEET]
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Processor Clock
int
XTALSEL
30.3
Figure 30-1.
566
HCLK
Processor
Clock
Controller
Clock Generator
30.4
Master Clock Controller
The Master Clock Controller provides selection and division of the master clock (MCK) and coprocessor master
clock (CPMCK). MCK is the source clock of the peripheral clocks in the subsystem 0 and CPMCK is the source of
the peripheral clocks in the subsystem 1. The master clock is selected from one of the clocks provided by the
Clock Generator.
Selecting the slow clock provides a slow clock signal to the whole device. Selecting the main clock saves power
consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler.
The master clock selection is made by writing the CSS/CPCSS field (Clock Source Selection/Coprocessor Clock
Source Selection) in PMC_MCKR. The prescaler supports the division by a power of 2 of the selected clock
between 1 and 64, and the division by 3. The PRES/CPPRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new master clock, the MCKRDY bit is cleared in PMC_SR. It reads 0
until the master clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor.
This feature is useful when switching from a high-speed clock to a lower one to inform the software when the
change is actually done.
Figure 30-2.
Master Clock Controller
PMC_MCKR
CSS
PMC_MCKR
PRES
SLCK
MAINCK
PLLACK
Master Clock
Prescaler
To the MCK Divider
PLLBCK
To the Processor
Clock Controller (PCK)
30.5
Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) and a Coprocessor Clock Controller (CPHCLK) that
implements the processor Sleep mode. These processor clocks can be disabled by executing the WFI
(WaitForInterrupt) or the WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast
Startup Mode Register (PMC_FSMR).
The Processor Clock Controller HCLK is enabled after a reset and is automatically re-enabled by any enabled
interrupt. The Coprocessor Clock Controller CPHCLK is disabled after reset. It is up to the master application to
enable the CPHCLK. Similar to HCLK, CPHCLK is automatically re-enabled by any enabled instruction after
having executed a WFI instruction. The processor Sleep mode is entered by disabling the processor clock, which
is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product.
When processor Sleep mode is entered, the current instruction is finished before the clock is stopped, but this
does not prevent data transfers from other masters of the system bus.
30.6
SysTick Clock
The SysTick calibration value is fixed to 8000 which allows the generation of a time base of 1 ms with SysTick
clock to the maximum frequency on MCK divided by 8.
30.7
Peripheral Clock Controller
The PMC controls the clocks of each embedded peripheral by means of the Peripheral Clock Controller. The user
can individually enable and disable the clock on the peripherals.
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The user can also enable and disable these clocks by writing Peripheral Clock Enable 0 (PMC_PCER0),
Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1 (PMC_PCER1) and Peripheral Clock
Disable 1 (PMC_PCDR1) registers. The status of the peripheral clock activity can be read in the Peripheral Clock
Status Register (PMC_PCSR0) and Peripheral Clock Status Register (PMC_PCSR1).
If the peripherals located on the coprocessor system bus require data exchange with the co-processor or the main
processor, the CPBMCK clock must be enabled prior to enable any co-processor peripheral clock.
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically
disabled after a reset.
To stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last
programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the
system.
The bit number within the Peripheral Clock Control registers (PMC_PCER0–1, PMC_PCDR0–1, and
PMC_PCSR0–1) is the Peripheral Identifier defined at the product level. The bit number corresponds to the
interrupt source number assigned to the peripheral.
30.8
Free-Running Processor Clock
The free-running processor clock (FCLK) together with the free-running coprocessor master clock (CPFCLK) used
for sampling interrupts and clocking debug blocks ensures that interrupts can be sampled, and sleep events can
be traced, while the processor(s) is(are) sleeping. It is connected to master clock (MCK)/coprocessor master clock
(CPMCK).
30.9
Programmable Clock Output Controller
The PMC controls three signals to be output on external pins, PCKx. Each signal can be independently
programmed via the Programmable Clock Registers (PMC_PCKx).
PCKx can be independently selected between the slow clock (SLCK), the main clock (MAINCK), the PLLA clock
(PLLACK), the PLLB clock (PLLBCK),and the master clock (MCK) by writing the CSS field in PMC_PCKx. Each
output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in
PMC_PCKx.
Each output signal can be enabled and disabled by writing a 1 to the corresponding PCKx bit of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of
PMC_SCSR.
The PCKRDYx status flag in PMC_SR indicates that the programmable clock is actually what has been
programmed in the programmable clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the programmable clock before any configuration change and to re-enable it after the
change is actually performed.
30.10 Main Processor Fast Startup
At exit from Wait mode, the device allows the main processor to restart in less than 10 microseconds only if the Ccode function that manages the Wait mode entry and exit is linked to and executed from on-chip SRAM.
The fast startup time cannot be achieved if the first instruction after an exit is located in the embedded Flash.
If fast startup is not required, or if the first instruction after a Wait mode exit is located in embedded Flash, see
Section 30.11 "Main Processor Startup from Embedded Flash”.
Prior to instructing the device to enter Wait mode:
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1. Select the 4/8/12 MHz RC oscillator as the master clock source (the CSS field in PMC_MCKR must be
written to 1).
2.
Disable the PLL if enabled.
3.
Clear the internal wake-up sources.
The system enters Wait mode either by setting the WAITMODE bit in CKGR_MOR, or by executing the
WaitForEvent (WFE) instruction of the processor while the LPM bit is at 1 in PMC_FSMR. Immediately after setting
the WAITMODE bit or using the WFE instruction, wait for the MCKRDY bit to be set in PMC_SR.
In case of dual core activity, it is recommended to check the coprocessor state before instructing the main
processor to enter Wait mode.
A fast startup is enabled upon the detection of a programmed level on one of the 16 wake-up inputs (WKUP) or
upon an active alarm from the RTC and RTT. The polarity of the 16 wake-up inputs is programmable by writing the
PMC Fast Startup Polarity Register (PMC_FSPR).
The fast startup circuitry, as shown in Figure 30-3, is fully asynchronous and provides a fast startup signal to the
PMC. As soon as the fast startup signal is asserted, the embedded 4/8/12 MHz RC oscillator restarts
automatically.
When entering Wait mode, the embedded Flash can be placed in one of the Low-power modes (Deep-powerdown or Standby modes) depending on the configuration of the FLPM field in the PMC_FSMR. The FLPM field
can be programmed at anytime and its value will be applied to the next Wait mode period.
The power consumption reduction is optimal when configuring 1 (Deep-power-down mode) in field FLPM. If 0 is
programmed (Standby mode), the power consumption is slightly higher than in Deep-power-down mode.
When programming 2 in field FLPM, the Wait mode Flash power consumption is equivalent to that of the Active
mode when there is no read access on the Flash.
Figure 30-3.
Fast Startup Circuitry
FSTT0
WKUP0
FSTP0
FSTT1
WKUP1
FSTP1
FSTT15
WKUP15
fast_restart
FSTP15
RTTAL
RTT Alarm
RTCAL
RTC Alarm
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Each wake-up input pin and alarm can be enabled to generate a fast startup event by setting the corresponding bit
in PMC_FSMR.
The user interface does not provide any status for fast startup, but the user can easily recover this information by
reading the PIO Controller and the status registers of the RTC and RTT.
30.11 Main Processor Startup from Embedded Flash
The inherent start-up time of the embedded Flash cannot provide a fast startup of the system.
If system fast start-up time is not required, the first instruction after a Wait mode exit can be located in the
embedded Flash. Under these conditions, prior to entering Wait mode, the Flash controller must be programmed
to perform access in 0 wait-state. Refer to Section 22. "Enhanced Embedded Flash Controller (EEFC)”.
The procedure and conditions to enter Wait mode and the circuitry to exit Wait mode are strictly the same as fast
startup (refer to Section 30.10 "Main Processor Fast Startup”).
30.12 Coprocessor Sleep Mode
The coprocessor enters Sleep mode by executing the WaitForInterrupt (WFI) instruction of the coprocessor. Any
enabled interrupt can wake the processor up.
30.13 Main Clock Failure Detector
The clock failure detector monitors the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator to
identify a failure of this oscillator when selected as main clock.
The clock failure detector can be enabled or disabled by bit CFDEN in CKGR_MOR. After a VDDCORE reset, the
detector is disabled. However, if the oscillator is disabled (MOSCXTEN = 0), the detector is also disabled.
A failure is detected by means of a counter incrementing on the main clock and detection logic is triggered by the
32 kHz (typical) RC oscillator which is automatically enabled when CFDEN=1.
The counter is cleared when the 32 kHz (typical) RC oscillator clock signal is low and enabled when the signal is
high. Thus, the failure detection time is one RC oscillator period. If, during the high level period of the 32 kHz
(typical) RC oscillator clock signal, less than eight 3 to 20 MHz crystal oscillator clock periods have been counted,
then a failure is reported.
If a failure of the main clock is detected, bit CFDEV in PMC_SR indicates a failure event and generates an
interrupt if the corresponding interrupt source is enabled. The interrupt remains active until a read occurs in
PMC_SR. The user can know the status of the clock failure detection at any time by reading the CFDS bit in
PMC_SR.
Figure 30-4.
Clock Failure Detection (Example)
Main Crytal Clock
SLCK
CDFEV
CDFS
Note: ratio of clock periods is for illustration purposes only
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Read PMC_SR
If the 3 to 20 MHz crystal oscillator or ceramic resonator-based oscillator is selected as the source clock of
MAINCK (MOSCSEL in CKGR_MOR = 1), and if MCK source is PLLACK or PLLBCK (CSS = 2), a clock failure
detection automatically forces MAINCK to be the source clock for MCK. Then, regardless of the PMC
configuration, a clock failure detection automatically forces the 4/8/12 MHz RC oscillator to be the source clock for
MAINCK. If this oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the
clock failure detection mechanism.
It takes two 32 kHz (typical) RC oscillator clock cycles to detect and switch from the 3 to 20 MHz crystal oscillator,
to the 4/8/12 MHz RC oscillator if the source master clock (MCK) is main clock (MAINCK), or three 32 kHz (typical)
RC oscillator clock cycles if the source of MCK is PLLACK or PLLBCK.
The user can know the status of the clock failure detector at any time by reading the FOS bit in PMC_SR.
This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault
Output Clear Register (PMC_FOCR).
30.14 32.768 kHz Crystal Oscillator Frequency Monitor
The frequency of the 32.768 kHz crystal oscillator can be monitored by means of logic driven by the 4/8/12 MHz
RC oscillator known as a reliable clock source. This function is enabled by configuring the XT32KFME bit of
CKGR_MOR. The SEL4/SEL8/SEL12 bits of PMC_OCR must be cleared.
An error flag (XT32KERR in PMC_SR) is asserted when the 32.768 kHz crystal oscillator frequency is out of the
±10% nominal frequency value (i.e., 32.768 kHz). The error flag can be cleared only if the slow clock frequency
monitoring is disabled.
When the 4/8/12 MHz RC oscillator frequency is 4 MHz, the accuracy of the measurement is ±40% as this
frequency is not trimmed during production. Therefore, ±10% accuracy is obtained only if the RC oscillator
frequency is configured for 8 or 12 MHz.
The monitored clock frequency is declared invalid if at least four consecutive clock period measurement results are
over the nominal period ±10%.
Due to the possible frequency variation of the embedded 4/8/12 MHz RC oscillator acting as reference clock for
the monitor logic, any 32.768 kHz crystal oscillator frequency deviation over ±10% of the nominal frequency is
systematically reported as an error by the XT32KERR bit in PMC_SR. Between -1% and -10% and +1% and
+10%, the error is not systematically reported.
Thus only a crystal running at 32.768 kHz frequency ensures that the error flag will not be asserted. The permitted
drift of the crystal is 10000 ppm (1%), which allows any standard crystal to be used.
If the 4/8/12 MHz RC frequency needs to be changed while the slow clock frequency monitor is operating, the
monitoring must be stopped prior to changing the 4/8/12 MHz RC frequency. Then it can be re-enabled as soon as
MOSCRCS is set in PMC_SR.
The error flag can be defined as an interrupt source of the PMC by setting the XT32KERR bit of PMC_IER.
30.15 Programming Sequence
1. If the 3 to 20 MHz crystal oscillator is not required, the PLL and divider can be directly configured (Step 6.)
else this oscillator must be started (Step 2.).
2.
Enable the 3 to 20 MHz crystal oscillator by setting the MOSCXTEN field in CKGR_MOR:
The user can define a start-up time. This is done by writing a value in the MOSCXTST field in CKGR_MOR.
Once this register has been correctly configured, the user must wait for MOSCXTS field in PMC_SR to be
set. This is done either by polling MOSCXTS in PMC_SR, or by waiting for the interrupt line to be raised if
the associated interrupt source (MOSCXTS) has been enabled in PMC_IER.
3.
Switch the MAINCK to the 3 to 20 MHz crystal oscillator by setting MOSCSEL in CKGR_MOR.
4.
Wait for the MOSCSELS to be set in PMC_SR to ensure the switch is complete.
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5.
Check the main clock frequency:
This main clock frequency can be measured via CKGR_MCFR.
Read CKGR_MCFR until the MAINFRDY field is set, after which the user can read the MAINF field in
CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have
been counted during a period of 16 slow clock cycles.
If MAINF = 0, switch the MAINCK to the 4/8/12 MHz RC Oscillator by clearing MOSCSEL in CKGR_MOR. If
MAINF ≠ 0, proceed to Step 6.
6.
Set PLLx and Divider (if not required, proceed to Step 7.):
In the names PLLx, DIVx, MULx, LOCKx, PLLxCOUNT, and CKGR_PLLxR, ‘x’ represents A or B.
All parameters needed to configure PLLx and the divider are located in CKGR_PLLxR.
The DIVx field is used to control the divider itself. This parameter can be programmed between 0 and 127.
Divider output is divider input divided by DIVx parameter. By default, DIVx field is cleared which means that
the divider and PLLx are turned off.
The MULx field is the PLLx multiplier factor. This parameter can be programmed between 0 and 254. If
MULx is cleared, PLLx will be turned off, otherwise the PLLx output frequency is PLLx input frequency
multiplied by (MULx + 1).
The PLLxCOUNT field specifies the number of slow clock cycles before the LOCKx bit is set in the PMC_SR
after CKGR_PLLxR has been written.
Once CKGR_PLLxR has been written, the user must wait for the LOCKx bit to be set in the PMC_SR. This
can be done either by polling LOCKx in PMC_SR or by waiting for the interrupt line to be raised if the
associated interrupt source (LOCKx) has been enabled in PMC_IER. All fields in CKGR_PLLxR can be
programmed in a single write operation. If at some stage one of the following parameters, MULx or DIVx is
modified, the LOCKx bit goes low to indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set
again. The user must wait for the LOCKx bit to be set before using the PLLx output clock.
7.
Select the master clock and processor clock
The master clock and the processor clock are configurable via PMC_MCKR.
The CSS field is used to select the clock source of the master clock and processor clock dividers. By default,
the selected clock source is the main clock.
The PRES field is used to define the processor clock and master clock prescaler. The user can choose
between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency
divided by the PRES value.
Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR.
This can be done either by polling MCKRDY in PMC_SR or by waiting for the interrupt line to be raised if the
associated interrupt source (MCKRDY) has been enabled in PMC_IER. PMC_MCKR must not be
programmed in a single write operation. The programming sequence for PMC_MCKR is as follows:
572
If a new value for CSS field corresponds to PLL clock,
̶
Program the PRES field in PMC_MCKR.
̶
Wait for the MCKRDY bit to be set in PMC_SR.
̶
Program the CSS field in PMC_MCKR.
̶
Wait for the MCKRDY bit to be set in PMC_SR.
If a new value for CSS field corresponds to main clock or slow clock,
̶
Program the CSS field in PMC_MCKR.
̶
Wait for the MCKRDY bit to be set in the PMC_SR.
̶
Program the PRES field in PMC_MCKR.
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̶
Wait for the MCKRDY bit to be set in PMC_SR.
If at some stage, parameters CSS or PRES are modified, the MCKRDY bit goes low to indicate that the
master clock and the processor clock are not yet ready. The user must wait for MCKRDY bit to be set again
before using the master and processor clocks.
Note:
IF PLLx clock was selected as the master clock and the user decides to modify it by writing in CKGR_PLLxR, the
MCKRDY flag will go low while PLLx is unlocked. Once PLLx is locked again, LOCKx goes high and MCKRDY is set.
While PLLx is unlocked, the master clock selection is automatically changed to slow clock for PLLA and main clock for
PLLB. For further information, see Section 30.16.2 "Clock Switching Waveforms”.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The master clock is main clock divided by 2.
8.
Select the programmable clocks
Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. Three
programmable clocks can be used. PMC_SCSR indicates which programmable clock is enabled. By default
all programmable clocks are disabled.
PMC_PCKx registers are used to configure programmable clocks.
The CSS field is used to select the programmable clock divider source. Several clock options are available:
main clock, slow clock, master clock, PLLACK, PLLBCK. The slow clock is the default clock source.
The PRES field is used to control the programmable clock prescaler. It is possible to choose between
different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES
parameter. By default, the PRES value is cleared which means that PCKx is equal to slow clock.
Once PMC_PCKx register has been configured, the corresponding programmable clock must be enabled
and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by
polling PCKRDYx in PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt
source (PCKRDYx) has been enabled in PMC_IER. All parameters in PMC_PCKx can be programmed in a
single write operation.
If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be
disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the
programmable clock and wait for the PCKRDYx bit to be set.
9.
Enable the peripheral clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled
via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR.
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30.16 Clock Switching Details
30.16.1 Master Clock Switching Timings
Table 30-1 and Table 30-2 give the worst case timings required for the master clock to switch from one selected
clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an
additional time of 64 clock cycles of the newly selected clock has to be added.
Table 30-1.
Clock Switching Timings (Worst Case)
From
Main Clock
SLCK
PLL Clock
–
4 x SLCK +
2.5 x Main Clock
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLL Clock +
5 x SLCK
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
To
Main Clock
SLCK
PLL Clock
Notes:
1.
2.
Table 30-2.
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
PLL designates eitherthe PLLA or the PLLB Clock.
PLLCOUNT designates eitherPLLACOUNT or PLLBCOUNT.
Clock Switching Timings between Two PLLs (Worst Case)
From
PLLA Clock
PLLB Clock
PLLA Clock
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock
3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK+
PLLBCOUNT x SLCK
To
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30.16.2 Clock Switching Waveforms
Figure 30-5.
Switch Master Clock from Slow Clock to PLLx Clock
Slow Clock
PLLx Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
Figure 30-6.
Switch Master Clock from Main Clock to Slow Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
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Figure 30-7.
Change PLLx Programming
Slow Clock
PLLx Clock
LOCKx
MCKRDY
Master Clock
Slow Clock
Write CKGR_PLLxR
Figure 30-8.
Programmable Clock Output Programming
PLLx Clock
PCKRDY
PCKx Output
Write PMC_PCKx
PLL Clock is selected
Write PMC_SCER
Write PMC_SCDR
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PCKx is enabled
PCKx is disabled
30.17 Register Write Protection
To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the PMC Write Protection Status
Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the PMC_WPSR.
The following registers can be write-protected:
PMC System Clock Enable Register
PMC System Clock Disable Register
PMC Peripheral Clock Enable Register 0
PMC Peripheral Clock Disable Register 0
PMC Clock Generator Main Oscillator Register
PMC Clock Generator PLLA Register
PMC Clock Generator PLLB Register
PMC Master Clock Register
PMC Programmable Clock Register
PMC Fast Startup Mode Register
PMC Fast Startup Polarity Register
PMC Coprocessor Fast Startup Mode Register
PMC Peripheral Clock Enable Register 1
PMC Peripheral Clock Disable Register 1
PMC Oscillator Calibration Register
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30.18 Power Management Controller (PMC) User Interface
Table 30-3.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
System Clock Enable Register
PMC_SCER
Write-only
–
0x0004
System Clock Disable Register
PMC_SCDR
Write-only
–
0x0008
System Clock Status Register
PMC_SCSR
Read-only
0x0000_0001
0x000C
Reserved
–
–
0x0010
Peripheral Clock Enable Register 0
PMC_PCER0
Write-only
–
0x0014
Peripheral Clock Disable Register 0
PMC_PCDR0
Write-only
–
0x0018
Peripheral Clock Status Register 0
PMC_PCSR0
Read-only
0x0000_0000
0x0020
Main Oscillator Register
CKGR_MOR
Read/Write
0x0000_0008
0x0024
Main Clock Frequency Register
CKGR_MCFR
Read/Write
0x0000_0000
0x0028
PLLA Register
CKGR_PLLAR
Read/Write
0x0000_3F00
0x002C
PLLB Register
CKGR_PLLBR
Read/Write
0x0000_3F00
0x0030
Master Clock Register
PMC_MCKR
Read/Write
0x0000_0001
–
–
0x0034–0x003C
Reserved
–
0x0040
Programmable Clock 0 Register
PMC_PCK0
Read/Write
0x0000_0000
0x0044
Programmable Clock 1 Register
PMC_PCK1
Read/Write
0x0000_0000
0x0048
Programmable Clock 2 Register
PMC_PCK2
Read/Write
0x0000_0000
–
–
0x004C– 0x005C
Reserved
–
0x0060
Interrupt Enable Register
PMC_IER
Write-only
–
0x0064
Interrupt Disable Register
PMC_IDR
Write-only
–
0x0068
Status Register
PMC_SR
Read-only
0x0003_0008
0x006C
Interrupt Mask Register
PMC_IMR
Read-only
0x0000_0000
0x0070
Fast Startup Mode Register
PMC_FSMR
Read/Write
0x0000_0000
0x0074
Fast Startup Polarity Register
PMC_FSPR
Read/Write
0x0000_0000
0x0078
Fault Output Clear Register
PMC_FOCR
Write-only
–
0x007C
Coprocessor Fast Startup Mode Register
PMC_CPFSMR
Read/Write
0x0000_0000
–
–
0x0080–0x00E0
Reserved
–
0x00E4
Write Protection Mode Register
PMC_WPMR
Read/Write
0x0000_0000
0x00E8
Write Protection Status Register
PMC_WPSR
Read-only
0x0000_0000
–
–
0x00EC–0x00FC
578
–
Reserved
–
0x0100
Peripheral Clock Enable Register 1
PMC_PCER1
Write-only
–
0x0104
Peripheral Clock Disable Register 1
PMC_PCDR1
Write-only
–
0x0108
Peripheral Clock Status Register 1
PMC_PCSR1
Read-only
0x0000_0000
0x010C
Reserved
–
–
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–
Table 30-3.
Register Mapping (Continued)
Offset
Register
Name
0x0110
Oscillator Calibration Register
PMC_OCR
Reserved
–
0x114–0x120
0134–0x144
Reserved
–
Note: If an offset is not listed in the table it must be considered as “reserved”.
Access
Reset
Read/Write
0x0040_4040
–
–
–
–
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30.18.1 PMC System Clock Enable Register
Name:
PMC_SCER
Address:
0x400E0400
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
22
21
20
19
–
18
–
17
CPBMCK
16
CPCK
CPKEY
15
–
14
–
13
–
12
–
11
–
10
PCK2
9
PCK1
8
PCK0
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PCKx: Programmable Clock x Output Enable
0: No effect.
1: Enables the corresponding Programmable Clock output.
• CPCK: Coprocessor (Second Processor) Clocks Enable
0: No effect.
1: Enables the corresponding Coprocessor Clocks (CPHCLK, CPSYSTICK) if CPKEY = 0xA.
• CPBMCK: Coprocessor Bus Master Clocks Enable
0: No effect.
1: Enables the corresponding Coprocessor Bus Master Clock (CPBMCK,CPFCLK) if CPKEY = 0xA.
Note: Enabling CPBMCK must be performed prior or at the same time as CPCK is programmed to 1 in PMC_SCER or prior
communication with one the peripherals of the coprocessor system bus.
• CPKEY: Coprocessor Clocks Enable Key
Value
0xA
580
Name
Description
PASSWD
This field must be written to 0xA in order to validate CPCK field.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.2 PMC System Clock Disable Register
Name:
PMC_SCDR
Address:
0x400E0404
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
22
21
20
19
–
18
–
17
CPBMCK
16
CPCK
CPKEY
15
–
14
–
13
–
12
–
11
–
10
PCK2
9
PCK1
8
PCK0
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PCKx: Programmable Clock x Output Disable
0: No effect.
1: Disables the corresponding Programmable Clock output.
• CPCK: Coprocessor Clocks Disable
0: No effect.
1: Enables the corresponding Coprocessor Clocks (CPHCLK, CPFCLK, CPSYSTICK) if CPKEY = 0xA.
• CPBMCK: Coprocessor Bus Master Clocks Disable
0: No effect.
1: Disables the corresponding Coprocessor Bus Master Clock (CPBMCK, CPFCLK) if CPKEY = 0xA.
Note: Disabling CPBMCK must not be performed if CPCK is 1 in PMC_SCSR.
• CPKEY: Coprocessor Clocks Disable Key
Value
0xA
Name
Description
PASSWD
This field must be written to 0xA in order to validate CPCK field.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
581
30.18.3 PMC System Clock Status Register
Name:
PMC_SCSR
Address:
0x400E0408
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
CPBMCK
16
CPCK
15
–
14
–
13
–
12
–
11
–
10
PCK2
9
PCK1
8
PCK0
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
• PCKx: Programmable Clock x Output Status
0: The corresponding Programmable Clock output is disabled.
1: The corresponding Programmable Clock output is enabled.
• CPCK: Coprocessor (Second Processor) Clocks Status
0: Coprocessor Clocks (CPHCLK, CPSYSTICK) are disabled (value after reset).
1: Coprocessor Clocks (CPHCLK, CPSYSTICK) are enabled.
• CPBMCK: Coprocessor Bus Master Clock Status
0: Coprocessor Clocks (CPBMCK, CPFCLK) are disabled (value after reset).
1: Coprocessor Clocks (CPBMCK, CPFCLK) are enabled.
582
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.4 PMC Peripheral Clock Enable Register 0
Name:
PMC_PCER0
Address:
0x400E0410
Access:
Write-only
31
PID31
30
–
29
PID29
28
PID28
27
PID27
26
PID26
25
PID25
24
PID24
23
PID23
22
PID22
21
PID21
20
PID20
19
PID19
18
PID18
17
PID17
16
PID16
15
PID15
14
PID14
13
PID13
12
PID12
11
PID11
10
PID10
9
PID9
8
PID8
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Enable
0: No effect.
1: Enables the corresponding peripheral clock.
Notes:
1. PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be enabled in PMC_PCER1
(Section 30.18.23 "PMC Peripheral Clock Enable Register 1”).
2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
583
30.18.5 PMC Peripheral Clock Disable Register 0
Name:
PMC_PCDR0
Address:
0x400E0414
Access:
Write-only
31
PID31
30
–
29
PID29
28
PID28
27
PID27
26
PID26
25
PID25
24
PID24
23
PID23
22
PID22
21
PID21
20
PID20
19
PID19
18
PID18
17
PID17
16
PID16
15
PID15
14
PID14
13
PID13
12
PID12
11
PID11
10
PID10
9
PID9
8
PID8
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Disable
0: No effect.
1: Disables the corresponding peripheral clock.
Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals can be disabled in PMC_PCDR1
(Section 30.18.24 "PMC Peripheral Clock Disable Register 1”).
584
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.6 PMC Peripheral Clock Status Register 0
Name:
PMC_PCSR0
Address:
0x400E0418
Access:
Read-only
31
PID31
30
–
29
PID29
28
PID28
27
PID27
26
PID26
25
PID25
24
PID24
23
PID23
22
PID22
21
PID21
20
PID20
19
PID19
18
PID18
17
PID17
16
PID16
15
PID15
14
PID14
13
PID13
12
PID12
11
PID11
10
PID10
9
PID9
8
PID8
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
–
• PIDx: Peripheral Clock x Status
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
Note: PIDx refers to identifiers defined in the section “Peripheral Identifiers”. Other peripherals status can be read in PMC_PCSR1
(Section 30.18.25 "PMC Peripheral Clock Status Register 1”).
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
585
30.18.7 PMC Clock Generator Main Oscillator Register
Name:
CKGR_MOR
Address:
0x400E0420
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
XT32KFME
25
CFDEN
24
MOSCSEL
23
22
21
20
19
18
17
16
11
10
9
8
3
MOSCRCEN
2
WAITMODE
1
MOSCXTBY
0
MOSCXTEN
KEY
15
14
13
12
MOSCXTST
7
–
6
5
MOSCRCF
4
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• MOSCXTEN: 3 to 20 MHz Crystal Oscillator Enable
A crystal must be connected between XIN and XOUT.
0: The 3 to 20 MHz crystal oscillator is disabled.
1: The 3 to 20 MHz crystal oscillator is enabled. MOSCXTBY must be cleared.
When MOSCXTEN is set, the MOSCXTS flag is set once the crystal oscillator start-up time is achieved.
• MOSCXTBY: 3 to 20 MHz Crystal Oscillator Bypass
0: No effect.
1: The 3 to 20 MHz crystal oscillator is bypassed. MOSCXTEN must be cleared. An external clock must be connected on
XIN.
When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set.
Clearing MOSCXTEN and MOSCXTBY bits resets the MOSCXTS flag.
Note:
When the crystal oscillator bypass is disabled (MOSCXTBY = 0), the MOSCXTS flag must be read at 0 in PMC_SR before
enabling the crystal oscillator (MOSCXTEN = 1).
• WAITMODE: Wait Mode Command (Write-only)
0: No effect.
1: Puts the device in Wait mode.
• MOSCRCEN: 4/8/12 MHz RC Oscillator Enable
0: The 4/8/12 MHz RC oscillator is disabled.
1: The 4/8/12 MHz RC oscillator is enabled.
When MOSCRCEN is set, the MOSCRCS flag is set once the RC oscillator start-up time is achieved.
586
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• MOSCRCF: 4/8/12 MHz RC Oscillator Frequency Selection
At startup, the RC oscillator frequency is 4 MHz.
Value
Name
Description
0
4_MHz
The RC oscillator frequency is at 4 MHz (default)
1
8_MHz
The RC oscillator frequency is at 8 MHz
2
12_MHz
The RC oscillator frequency is at 12 MHz
Note: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR. Therefore MOSCRCF and MOSCRCEN cannot be
changed at the same time.
• MOSCXTST: 3 to 20 MHz Crystal Oscillator Start-up Time
Specifies the number of slow clock cycles multiplied by 8 for the crystal oscillator start-up time.
• KEY: Write Access Password
Value
Name
0x37
PASSWD
Description
Writing any other value in this field aborts the write operation.
Always reads as 0.
• MOSCSEL: Main Clock Oscillator Selection
0: The 4/8/12 MHz RC oscillator is selected.
1: The 3 to 20 MHz crystal oscillator is selected.
• CFDEN: Clock Failure Detector Enable
0: The clock failure detector is disabled.
1: The clock failure detector is enabled.
Note:
1. The 32 kHz (typical) RC oscillator is automatically enabled when CFDEN=1.
• XT32KFME: 32.768 kHz Crystal Oscillator Frequency Monitoring Enable
0: The 32.768 kHz crystal oscillator frequency monitoring is disabled.
1: The 32.768 kHz crystal oscillator frequency monitoring is enabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
587
30.18.8 PMC Clock Generator Main Clock Frequency Register
Name:
CKGR_MCFR
Address:
0x400E0424
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
RCMEAS
19
–
18
–
17
–
16
MAINFRDY
15
14
13
12
11
10
9
8
3
2
1
0
MAINF
7
6
5
4
MAINF
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• MAINF: Main Clock Frequency
Gives the number of main clock cycleswithin 16 slow clock periods. To calculate the frequency of the measured clock:
fMAINCK = (MAINF × fSLCK) / 16
where frequency is in MHz.
• MAINFRDY: Main Clock Frequency Measure Ready
0: MAINF value is not valid or the measured oscillator is disabled or a measure has just been started by means of
RCMEAS.
1: The measured oscillator has been enabled previously and MAINF value is available.
Note: To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at 1 then another read access must
be performed on the register to get a stable value on the MAINF field.
• RCMEAS: Restart Main Clock Source Frequency Measure (write-only)
0: No effect.
1: Restarts measuring of the frequency of the main clock source. MAINF will carry the new frequency as soon as a low to
high transition occurs on the MAINFRDY flag.
The measure is performed on the main frequency (i.e. not limited to RC oscillator only), but if the main clock frequency
source is the 3 to 20 MHz crystal oscillator, the restart of measuring is not needed because of the well known stability of
crystal oscillators.
588
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.9 PMC Clock Generator PLLA Register
Name:
CKGR_PLLAR
Address:
0x400E0428
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
25
MULA
24
23
22
21
20
19
18
17
16
10
9
8
2
1
0
MULA
15
–
14
–
13
7
6
5
12
11
PLLACOUNT
4
3
PLLAEN
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PLLAEN: PLLA Control
0: PLLA is disabled
1: PLLA is enabled
2–255: Forbidden
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0: The PLLA is deactivated (PLLA also disabled if DIVA = 0).
200 up to 254 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
Unlisted values are forbidden.
To change the PLLA frequency, please read Section 29.6.1 "Divider and Phase Lock Loop Programming”.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
589
30.18.10PMC Clock Generator PLLB Register
Name:
CKGR_PLLBR
Address:
0x400E042C
Access:
Read/Write
31
–
30
–
29
SRCB
28
–
27
–
26
25
MULB
24
23
22
21
20
19
18
17
16
10
9
8
2
1
0
MULB
15
–
14
–
13
7
6
5
12
11
PLLBCOUNT
4
3
DIVB
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• DIVB: PLLB Front-End Divider
0: Divider output is stuck at 0 and PLLB is disabled.
1: Divider is bypassed (divide by 1)
2–255: Clock is divided by DIVB
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0: The PLLB is deactivated (PLLB also disabled if DIVB = 0).
1 up to 62: The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
Unlisted values are forbidden.
• SRCB: Source for PLLB
Value
590
Name
Description
0
MAINCK_IN_PLLB
The PLLB input clock is Main Clock
1
PLLA_IN_PLLB
The PLLB input clock is PLLA output
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.11PMC Master Clock Register
Name:
PMC_MCKR
Address:
0x400E0430
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
22
21
20
19
–
18
17
CPCSS
16
8
–
CPPRES
15
–
14
–
13
PLLBDIV2
12
PLLADIV2
11
–
10
–
9
–
7
–
6
5
PRES
4
3
–
2
–
1
0
CSS
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• CSS: Master Clock Source Selection
Value
Name
Description
0
SLOW_CLK
Slow Clock is selected
1
MAIN_CLK
Main Clock is selected
2
PLLA_CLK
PLLA Clock is selected
3
PLLB_CLK
PLLBClock is selected
• PRES: Processor Clock Prescaler
Value
Name
Description
0
CLK_1
Selected clock
1
CLK_2
Selected clock divided by 2
2
CLK_4
Selected clock divided by 4
3
CLK_8
Selected clock divided by 8
4
CLK_16
Selected clock divided by 16
5
CLK_32
Selected clock divided by 32
6
CLK_64
Selected clock divided by 64
7
CLK_3
Selected clock divided by 3
• PLLADIV2: PLLA Divisor by 2
PLLADIV2
PLLA Clock Division
0
PLLA clock frequency is divided by 1.
1
PLLA clock frequency is divided by 2.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
591
• PLLBDIV2 PLLB Divisor by 2
PLLBDIV2
PLLB Clock Division
0
PLLB clock frequency is divided by 1.
1
PLLB clock frequency is divided by 2.
• CPCSS: Coprocessor Master Clock Source Selection
Value
Name
Description
0
SLOW_CLK
Slow Clock is selected
1
MAIN_CLK
Main Clock is selected
2
PLLA_CLK
PLLA Clock is selected
3
PLLB_CLK
PLLB Clock is selected
4
MCK
Master Clock is selected
• CPPRES: Coprocessor Programmable Clock Prescaler
0–15: The selected clock is divided by CPPRES + 1.
592
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.12PMC Programmable Clock Register
Name:
PMC_PCKx
Address:
0x400E0440
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
5
PRES
4
3
–
2
1
CSS
0
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• CSS: Master Clock Source Selection
Value
Name
Description
0
SLOW_CLK
Slow Clock is selected
1
MAIN_CLK
Main Clock is selected
2
PLLA_CLK
PLLA Clock is selected
3
PLLB_CLK
PLLB Clock is selected
4
MCK
Master Clock is selected
• PRES: Programmable Clock Prescaler
Value
Name
Description
0
CLK_1
Selected clock
1
CLK_2
Selected clock divided by 2
2
CLK_4
Selected clock divided by 4
3
CLK_8
Selected clock divided by 8
4
CLK_16
Selected clock divided by 16
5
CLK_32
Selected clock divided by 32
6
CLK_64
Selected clock divided by 64
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
593
30.18.13PMC Interrupt Enable Register
Name:
PMC_IER
Address:
0x400E0460
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
XT32KERR
20
–
19
–
18
CFDEV
17
MOSCRCS
16
MOSCSELS
15
–
14
–
13
–
12
–
11
–
10
PCKRDY2
9
PCKRDY1
8
PCKRDY0
7
–
6
–
5
–
4
–
3
MCKRDY
2
LOCKB
1
LOCKA
0
MOSCXTS
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Enable
• LOCKA: PLLA Lock Interrupt Enable
• LOCKB: PLLB Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
• MOSCSELS: Main Clock Source Oscillator Selection Status Interrupt Enable
• MOSCRCS: 4/8/12 MHz RC Oscillator Status Interrupt Enable
• CFDEV: Clock Failure Detector Event Interrupt Enable
• XT32KERR: 32.768 kHz Crystal Oscillator Error Interrupt Enable
594
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.14PMC Interrupt Disable Register
Name:
PMC_IDR
Address:
0x400E0464
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
XT32KERR
20
–
19
–
18
CFDEV
17
MOSCRCS
16
MOSCSELS
15
–
14
–
13
–
12
–
11
–
10
PCKRDY2
9
PCKRDY1
8
PCKRDY0
7
–
6
–
5
–
4
–
3
MCKRDY
2
LOCKB
1
LOCKA
0
MOSCXTS
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Disable
• LOCKA: PLLA Lock Interrupt Disable
• LOCKB: PLLB Lock Interrupt Disable
• MCKRDY: Master Clock Ready Interrupt Disable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
• MOSCSELS: Main Clock Source Oscillator Selection Status Interrupt Disable
• MOSCRCS: 4/8/12 MHz RC Oscillator Status Interrupt Disable
• CFDEV: Clock Failure Detector Event Interrupt Disable
• XT32KERR: 32.768 kHz Oscillator Error Interrupt Disable
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
595
30.18.15PMC Status Register
Name:
PMC_SR
Address:
0x400E0468
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
XT32KERR
20
FOS
19
CFDS
18
CFDEV
17
MOSCRCS
16
MOSCSELS
15
–
14
–
13
–
12
–
11
–
10
PCKRDY2
9
PCKRDY1
8
PCKRDY0
7
OSCSELS
6
–
5
–
4
–
3
MCKRDY
2
LOCKB
1
LOCKA
0
MOSCXTS
• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status
0: 3 to 20 MHz crystal oscillator is not stabilized.
1: 3 to 20 MHz crystal oscillator is stabilized.
• LOCKA: PLLA Lock Status
0: PLLA is not locked
1: PLLA is locked.
• LOCKB: PLLB Lock Status
0: PLLB is not locked
1: PLLB is locked.
• MCKRDY: Master Clock Status
0: Master Clock is not ready.
1: Master Clock is ready.
• OSCSELS: Slow Clock Oscillator Selection
0: Embedded 32 kHz RC oscillator is selected.
1: 32.768 kHz crystal oscillator is selected.
• PCKRDYx: Programmable Clock Ready Status
0: Programmable Clock x is not ready.
1: Programmable Clock x is ready.
• MOSCSELS: Main Clock Source Oscillator Selection Status
0: Selection is in progress.
1: Selection is done.
596
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• MOSCRCS: 4/8/12 MHz RC Oscillator Status
0: 4/8/12 MHz RC oscillator is not stabilized.
1: 4/8/12 MHz RC oscillator is stabilized.
• CFDEV: Clock Failure Detector Event
0: No clock failure detection of the 3 to 20 MHz crystal oscillator has occurred since the last read of PMC_SR.
1: At least one clock failure detection of the 3 to 20 MHz crystal oscillator has occurred since the last read of PMC_SR.
• CFDS: Clock Failure Detector Status
0: A clock failure of the 3 to 20 MHz crystal oscillator is not detected.
1: A clock failure of the 3 to 20 MHz crystal oscillator is detected.
• FOS: Clock Failure Detector Fault Output Status
0: The fault output of the clock failure detector is inactive.
1: The fault output of the clock failure detector is active.
• XT32KERR: 32.768 kHz Crystal Oscillator Error
0: The frequency of the 32.768 kHz crystal oscillator is correct (32.768 kHz +/- 1%) or the monitoring is disabled.
1: The frequency of the 32.768 kHz crystal oscillator is incorrect or has been incorrect for an elapsed period of time since
the monitoring has been enabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
597
30.18.16PMC Interrupt Mask Register
Name:
PMC_IMR
Address:
0x400E046C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
XT32KERR
20
–
19
–
18
CFDEV
17
MOSCRCS
16
MOSCSELS
15
–
14
–
13
–
12
–
11
–
10
PCKRDY2
9
PCKRDY1
8
PCKRDY0
7
–
6
–
5
–
4
–
3
MCKRDY
2
LOCKB
1
LOCKA
0
MOSCXTS
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• MOSCXTS: 3 to 20 MHz Crystal Oscillator Status Interrupt Mask
• LOCKA: PLLA Lock Interrupt Mask
• LOCKB: PLLB Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
• MOSCSELS: Main Clock Source Oscillator Selection Status Interrupt Mask
• MOSCRCS: 4/8/12 MHz RC Oscillator Status Interrupt Mask
• CFDEV: Clock Failure Detector Event Interrupt Mask
• XT32KERR: 32.768 kHz Oscillator Error Interrupt Mask
598
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.17PMC Fast Startup Mode Register
Name:
PMC_FSMR
Address:
0x400E0470
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
21
20
LPM
19
–
18
–
17
RTCAL
16
RTTAL
15
FSTT15
14
FSTT14
13
FSTT13
12
FSTT12
11
FSTT11
10
FSTT10
9
FSTT9
8
FSTT8
7
FSTT7
6
FSTT6
5
FSTT5
4
FSTT4
3
FSTT3
2
FSTT2
1
FSTT1
0
FSTT0
FLPM
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• FSTT0–FSTT15: Fast Startup Input Enable 0 to 15
0: The corresponding wake-up input has no effect on the PMC.
1: The corresponding wake-up input enables a fast restart signal to the PMC.
• RTTAL: RTT Alarm Enable
0: The RTT alarm has no effect on the PMC.
1: The RTT alarm enables a fast restart signal to the PMC.
• RTCAL: RTC Alarm Enable
0: The RTC alarm has no effect on the PMC.
1: The RTC alarm enables a fast restart signal to the PMC.
• LPM: Low-power Mode
0: The WaitForInterrupt (WFI) or the WaitForEvent (WFE) instruction of the processor makes the processor enter Sleep
mode.
1: The WaitForEvent (WFE) instruction of the processor makes the system to enter Wait mode.
• FLPM: Flash Low-power Mode
Value
Name
Description
0
FLASH_STANDBY
Flash is in Standby Mode when system enters Wait Mode
1
FLASH_DEEP_POWERDOWN
Flash is in Deep-power-down mode when system enters Wait Mode
2
FLASH_IDLE
Idle mode
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
599
30.18.18PMC Fast Startup Polarity Register
Name:
PMC_FSPR
Address:
0x400E0474
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
FSTP15
14
FSTP14
13
FSTP13
12
FSTP12
11
FSTP11
10
FSTP10
9
FSTP9
8
FSTP8
7
FSTP7
6
FSTP6
5
FSTP5
4
FSTP4
3
FSTP3
2
FSTP2
1
FSTP1
0
FSTP0
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• FSTPx: Fast Startup Input Polarityx
Defines the active polarity of the corresponding wake-up input. If the corresponding wake-up input is enabled and at the
FSTP level, it enables a fast restart signal.
600
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.19PMC Coprocessor Fast Startup Mode Register
Name:
PMC_CPFSMR
Address:
0x400E047C
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
RTCAL
16
RTTAL
15
FSTT15
14
FSTT14
13
FSTT13
12
FSTT12
11
FSTT11
10
FSTT10
9
FSTT9
8
FSTT8
7
FSTT7
6
FSTT6
5
FSTT5
4
FSTT4
3
FSTT3
2
FSTT2
1
FSTT1
0
FSTT0
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• FSTT0–FSTT15: Fast Startup Input Enable 0 to 15
0: The corresponding wake-up input has no effect on the PMC.
1: The corresponding wake-up input enables a fast restart signal to the PMC.
• RTTAL: RTT Alarm Enable
0: The RTT alarm has no effect on the PMC.
1: The RTT alarm enables a fast restart signal to the PMC.
• RTCAL: RTC Alarm Enable
0: The RTC alarm has no effect on the PMC.
1: The RTC alarm enables a fast restart signal to the PMC.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
601
30.18.20PMC Fault Output Clear Register
Name:
PMC_FOCR
Address:
0x400E0478
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
FOCLR
• FOCLR: Fault Output Clear
Clears the clock failure detector fault output.
602
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.21PMC Write Protection Mode Register
Name:
PMC_WPMR
Address:
0x400E04E4
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
–
2
–
1
–
0
WPEN
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
–
6
–
5
–
4
–
• WPEN: Write Protection Enable
0: Disables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
See Section 30.17 "Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
Value
0x504D43
Name
Description
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
603
30.18.22PMC Write Protection Status Register
Name:
PMC_WPSR
Address:
0x400E04E8
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
22
21
20
19
18
17
16
11
10
9
8
3
–
2
–
1
–
0
WPVS
WPVSRC
15
14
13
12
WPVSRC
7
–
6
–
5
–
4
–
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of the PMC_WPSR.
1: A write protection violation has occurred since the last read of the PMC_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
604
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.23PMC Peripheral Clock Enable Register 1
Name:
PMC_PCER1
Address:
0x400E0500
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PID43
PID42
PID41
PID40
7
6
5
4
3
2
1
0
PID39
PID38
PID37
PID36
PID35
PID34
PID33
PID32
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Enable
0: No effect.
1: Enables the corresponding peripheral clock.
Notes:
1. The values for PIDx are defined in the section “Peripheral Identifiers”.
2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
605
30.18.24PMC Peripheral Clock Disable Register 1
Name:
PMC_PCDR1
Address:
0x400E0504
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PID43
PID42
PID41
PID40
7
6
5
4
3
2
1
0
PID39
PID38
PID37
PID36
PID35
PID34
PID33
PID32
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• PIDx: Peripheral Clock x Disable
0: No effect.
1: Disables the corresponding peripheral clock.
Note: The values for PIDx are defined in the section “Peripheral Identifiers”.
606
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
30.18.25PMC Peripheral Clock Status Register 1
Name:
PMC_PCSR1
Address:
0x400E0508
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
PID43
PID42
PID41
PID40
7
6
5
4
3
2
1
0
PID39
PID38
PID37
PID36
PID35
PID34
PID33
PID32
• PIDx: Peripheral Clock x Status
0: The corresponding peripheral clock is disabled.
1: The corresponding peripheral clock is enabled.
Note: The values for PIDx are defined in the section “Peripheral Identifiers”.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
607
30.18.26PMC Oscillator Calibration Register
Name:
PMC_OCR
Address:
0x400E0510
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
SEL12
22
21
20
19
CAL12
18
17
16
15
SEL8
14
13
12
11
CAL8
10
9
8
7
SEL4
6
5
4
3
CAL4
2
1
0
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
• CAL4: RC Oscillator Calibration bits for 4 MHz
Calibration bits applied to the RC Oscillator when SEL4 is set.
• SEL4: Selection of RC Oscillator Calibration bits for 4 MHz
0: Default value stored in Flash memory.
1: Value written by user in CAL4 field of this register.
• CAL8: RC Oscillator Calibration bits for 8 MHz
Calibration bits applied to the RC Oscillator when SEL8 is set.
• SEL8: Selection of RC Oscillator Calibration bits for 8 MHz
0: Factory-determined value stored in Flash memory.
1: Value written by user in CAL8 field of this register.
• CAL12: RC Oscillator Calibration bits for 12 MHz
Calibration bits applied to the RC Oscillator when SEL12 is set.
• SEL12: Selection of RC Oscillator Calibration bits for 12 MHz
0: Factory-determined value stored in Flash memory.
1: Value written by user in CAL12 field of this register.
608
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
31.
Chip Identifier (CHIPID)
31.1
Description
Chip Identifier (CHIPID) registers are used to recognize the device and its revision. These registers provide the
sizes and types of the on-chip memories, as well as the set of embedded peripherals.
Two CHIPID registers are embedded: Chip ID Register (CHIPID_CIDR) and Chip ID Extension Register
(CHIPID_EXID). Both registers contain a hard-wired value that is read-only.
The CHIPID_CIDR register contains the following fields:
VERSION: Identifies the revision of the silicon
EPROC: Indicates the embedded ARM processor
NVPTYP and NVPSIZ: Identify the type of embedded non-volatile memory and the size
SRAMSIZ: Indicates the size of the embedded SRAM
ARCH: Identifies the set of embedded peripherals
EXT: Shows the use of the extension identifier register
The CHIPID_EXID register is device-dependent and reads 0 if CHIPID_CIDR.EXT = 0.
31.2
Embedded Characteristics
Chip ID Registers
̶
Table 31-1.
Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals,
Embedded Processor
SAM4CM Chip ID Registers
Chip Name
CHIPID_CIDR
CHIPID_EXID
SAM4CMP32C (Rev A)
0xA64D_0EE0
0x1
SAM4CMP16C (Rev A)
0xA64C_0CE0
0x1
SAM4CMP8C (Rev A)
0xA64C_0AE0
0x1
SAM4CMP32C (Rev B)
0xA64D_0EE1
0x1
SAM4CMP16C (Rev B)
0xA64C_0CE1
0x1
SAM4CMP8C (Rev B)
0xA64C_0AE1
0x1
SAM4CMP16C (Rev C)
0xA64C_0CE2
0x1
SAM4CMP8C (Rev C)
0xA64C_0AE2
0x1
SAM4CMS32C (Rev A)
0xA64D_0EE0
0x2
SAM4CMS16C (Rev A)
0xA64C_0CE0
0x2
SAM4CMS8C (Rev A)
0xA64C_0AE0
0x2
SAM4CMS32C (Rev B)
0xA64D_0EE1
0x2
SAM4CMS16C (Rev B)
0xA64C_0CE1
0x2
SAM4CMS8C (Rev B)
0xA64C_0AE1
0x2
SAM4CMS4C (Rev B)
0xA64C_0CE5
0x2
SAM4CMS16C (Rev C)
0xA64C_0CE2
0x2
SAM4CMS8C (Rev C)
0xA64C_0AE2
0x2
SAM4CMS4C (Rev C)
0xA64C_0CE6
0x2
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
609
31.3
Chip Identifier (CHIPID) User Interface
Table 31-2.
Offset
610
Register Mapping
Register
Name
Access
Reset
0x0
Chip ID Register
CHIPID_CIDR
Read-only
–
0x4
Chip ID Extension Register
CHIPID_EXID
Read-only
–
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
31.3.1 Chip ID Register
Name:
CHIPID_CIDR
Address:
0x400E0740
Access:
Read-only
31
EXT
30
23
22
29
NVPTYP
28
21
20
27
26
19
18
ARCH
15
14
13
6
EPROC
24
17
16
9
8
1
0
SRAMSIZ
12
11
10
NVPSIZ2
7
25
ARCH
NVPSIZ
5
4
–
3
2
–
256K
VERSION
• VERSION: Version of the Device
Current version of the device.
• 256K: 256-Kbyte Devices
When set, the NVPSIZ field is irrelevant. The actual Nonvolatile Program Memory Size is 256 Kbytes.
• EPROC: Embedded Processor
Value
Name
Description
0
SAM x7
Cortex-M7
1
ARM946ES
ARM946ES
2
ARM7TDMI
ARM7TDMI
3
CM3
Cortex-M3
4
ARM920T
ARM920T
5
ARM926EJS
ARM926EJS
6
CA5
Cortex-A5
7
CM4
Cortex-M4
• NVPSIZ: Nonvolatile Program Memory Size
Value
Name
Description
0
NONE
None
1
8K
8 Kbytes
2
16K
16 Kbytes
3
32K
32 Kbytes
4
–
Reserved
5
64K
64 Kbytes
6
–
Reserved
7
128K
128 Kbytes
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
611
Value
Name
Description
8
160K
160 Kbytes
9
256K
256 Kbytes
10
512K
512 Kbytes
11
–
Reserved
12
1024K
1024 Kbytes
13
–
Reserved
14
2048K
2048 Kbytes
15
–
Reserved
• NVPSIZ2: Second Nonvolatile Program Memory Size
Value
Name
Description
0
NONE
None
1
8K
8 Kbytes
2
16K
16 Kbytes
3
32K
32 Kbytes
4
–
Reserved
5
64K
64 Kbytes
6
–
Reserved
7
128K
128 Kbytes
8
–
Reserved
9
256K
256 Kbytes
10
512K
512 Kbytes
11
–
Reserved
12
1024K
1024 Kbytes
13
–
Reserved
14
2048K
2048 Kbytes
15
–
Reserved
• SRAMSIZ: Internal SRAM Size
Value
612
Name
Description
0
48K
48 Kbytes
1
192K
192 Kbytes
2
384K
384 Kbytes
3
6K
6 Kbytes
4
24K
24 Kbytes
5
4K
4 Kbytes
6
80K
80 Kbytes
7
160K
160 Kbytes
8
8K
8 Kbytes
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Value
Name
Description
9
16K
16 Kbytes
10
32K
32 Kbytes
11
64K
64 Kbytes
12
128K
128 Kbytes
13
256K
256 Kbytes
14
96K
96 Kbytes
15
512K
512 Kbytes
• ARCH: Architecture Identifier
Value
Name
Description
0x64
SAM4CxxC
SAM4CxC (100-pin version)
0x66
SAM4CxxE
SAM4CxE (144-pin version)
• NVPTYP: Nonvolatile Program Memory Type
Value
Name
Description
0
ROM
ROM
1
ROMLESS
ROMless or on-chip Flash
2
FLASH
Embedded Flash Memory
ROM and Embedded Flash Memory
3
ROM_FLASH
NVPSIZ is ROM size
NVPSIZ2 is Flash size
4
SRAM
SRAM emulating ROM
• EXT: Extension Flag
0: Chip ID has a single register definition without extension.
1: An extended Chip ID exists.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
613
31.3.2 Chip ID Extension Register
Name:
CHIPID_EXID
Address:
0x400E0744
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
EXID
23
22
21
20
EXID
15
14
13
12
EXID
7
6
5
4
EXID
• EXID: Chip ID Extension
This field is cleared if CHIPID_CIDR.EXT = 0.
Value
614
Name
Description
0x1
SAM4CMP
SAM4C + 3-phase EMAFE
0x2
SAM4CMS
SAM4C + 2-phase EMAFE
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.
Parallel Input/Output Controller (PIO)
32.1
Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line
may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This ensures
effective optimization of the pins of the product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface.
Each I/O line of the PIO Controller features:
An input change interrupt enabling level change detection on any I/O line.
Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O
line.
A glitch filter providing rejection of glitches lower than one-half of peripheral clock cycle.
A debouncing filter providing rejection of unwanted pulses from key or push button operations.
Multi-drive capability similar to an open drain I/O line.
Control of the pull-up and pull-down of the I/O line.
Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write
operation.
32.2
Embedded Characteristics
Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Four Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
̶
Input Change Interrupt
̶
Programmable Glitch Filter
̶
Programmable Debouncing Filter
̶
Multi-drive Option Enables Driving in Open Drain
̶
Programmable Pull-Up on Each I/O Line
̶
Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
̶
Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or HighLevel
Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write
Register Write Protection
Programmable Schmitt Trigger Inputs
Programmable I/O Drive
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32.3
Block Diagram
Figure 32-1.
Block Diagram
PIO Controller
PIO Interrupt
Interrupt Controller
PMC
Peripheral Clock
Data, Enable
Up to x
peripheral IOs
Embedded
Peripheral
PIN 0
Data, Enable
PIN 1
Embedded
Peripheral
Up to x
peripheral IOs
x is an integer representing the maximum number
of IOs managed by one PIO controller.
32.4
PIN x-1
APB
Product Dependencies
32.4.1 Pin Multiplexing
Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line
multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent,
the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required
by their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O,
programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO
Controller can control how the pin is driven by the product.
32.4.2 Power Management
The Power Management Controller controls the peripheral clock in order to save power. Writing any of the
registers of the user interface does not require the peripheral clock to be enabled. This means that the
configuration of the I/O lines does not require the peripheral clock to be enabled.
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However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch
filtering. Note that the input change interrupt, the interrupt modes on a programmable event and the read of the pin
level require the clock to be validated.
After a hardware reset, the peripheral clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line information.
32.4.3 Interrupt Sources
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller
interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in Table
11-1 “Peripheral Identifiers” to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO
Controller requires the Interrupt Controller to be programmed first.
The PIO Controller interrupt can be generated only if the peripheral clock is enabled.
Table 32-1.
Peripheral IDs
Instance
ID
PIOA
11
PIOB
12
PIOC
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32.5
Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O
is represented in Figure 32-2. In this description each signal shown represents one of up to 32 possible indexes.
Figure 32-2.
I/O Line Control Logic
PIO_OER[0]
VDD
PIO_OSR[0]
PIO_PUER[0]
PIO_ODR[0]
PIO_PUSR[0]
PIO_PUDR[0]
1
Peripheral A Output Enable
00
01
10
11
Peripheral B Output Enable
Peripheral C Output Enable
Peripheral D Output Enable
0
0
PIO_PER[0]
PIO_ABCDSR1[0]
PIO_PDR[0]
00
01
10
11
Peripheral B Output
Peripheral C Output
Peripheral D Output
1
PIO_PSR[0]
PIO_ABCDSR2[0]
Peripheral A Output
Integrated
Pull-Up
Resistor
PIO_MDER[0]
PIO_MDSR[0]
0
PIO_MDDR[0]
0
PIO_SODR[0]
1
PIO_ODSR[0]
Pad
PIO_CODR[0]
1
PIO_PPDER[0]
Integrated
Pull-Down
Resistor
PIO_PPDSR[0]
PIO_PPDDR[0]
GND
Peripheral A Input
Peripheral B Input
Peripheral C Input
Peripheral D Input
PIO_PDSR[0]
PIO_ISR[0]
0
D
Peripheral Clock
0
Slow Clock
PIO_SCDR
Clock
Divider
div_slck
1
Programmable
Glitch
or
Debouncing
Filter
Q
DFF
D
Q
DFF
EVENT
DETECTOR
(Up to 32 possible inputs)
PIO Interrupt
1
Peripheral Clock
Resynchronization
Stage
PIO_IER[0]
PIO_IMR[0]
PIO_IFER[0]
PIO_IDR[0]
PIO_IFSR[0]
PIO_IFSCER[0]
PIO_IFDR[0]
PIO_IFSCSR[0]
PIO_IFSCDR[0]
PIO_ISR[31]
PIO_IER[31]
PIO_IMR[31]
PIO_IDR[31]
32.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up
resistor can be enabled or disabled by writing to the Pull-up Enable Register (PIO_PUER) or Pull-up Disable
Register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in
the Pull-up Status Register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading
a zero means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing the Pull-down
Enable Register (PIO_PPDER) or the Pull-down Disable Register (PIO_PPDDR), respectively. Writing in these
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registers results in setting or clearing the corresponding bit in the Pull-down Status Register (PIO_PPDSR).
Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled.
Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down
resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, depending on the I/O, pull-up or pull-down can be set.
32.5.2 I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable Register
(PIO_PER) and the Disable Register (PIO_PDR). The Status Register (PIO_PSR) is the result of the set and clear
registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A
value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABCD
Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO
Controller.
If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR
have no effect and PIO_PSR returns a one for the corresponding bit.
After reset, the I/O lines are controlled by the PIO Controller, i.e., PIO_PSR resets at one. However, in some
events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that
must be driven inactive after reset, or for address lines that must be driven low for booting out of an external
memory). Thus, the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the
device.
32.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is
performed by writing PIO_ABCDSR1 and PIO_ABCDSR2.
For each pin:
The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in
PIO_ABCDSR2 means peripheral A is selected.
The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in
PIO_ABCDSR2 means peripheral B is selected.
The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in
PIO_ABCDSR2 means peripheral C is selected.
The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level one in
PIO_ABCDSR2 means peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are
always connected to the pin input (see Figure 32-2).
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the
pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2
in addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on
peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
If the software selects a peripheral A, B, C or D which does not exist for a pin, no alternate functions are enabled
for this pin and the selection is taken into account. The PIO Controller does not carry out checks to prevent
selection of a peripheral which does not exist.
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32.5.4 Output Control
When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of
the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1
and PIO_ABCDSR2 determines whether the pin is driven or not.
When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing
the Output Enable Register (PIO_OER) and Output Disable Register (PIO_ODR). The results of these write
operations are detected in the Output Status Register (PIO_OSR). When a bit in this register is at zero, the
corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the
PIO Controller.
The level driven on an I/O line can be determined by writing in the Set Output Data Register (PIO_SODR) and the
Clear Output Data Register (PIO_CODR). These write operations, respectively, set and clear the Output Data
Status Register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and
PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to
a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO
Controller.
Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level
driven on the I/O line.
32.5.5 Synchronous Data Output
Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by
using PIO_SODR and PIO_CODR. It requires two successive write operations into two different registers. To
overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only
bits unmasked by the Output Write Status Register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set
by writing to the Output Write Enable Register (PIO_OWER) and cleared by writing to the Output Write Disable
Register (PIO_OWDR).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
32.5.6 Multi-Drive Control (Open Drain)
Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits
several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor
(or enabling of the internal one) is generally required to guarantee a high level on the line.
The multi-drive feature is controlled by the Multi-driver Enable Register (PIO_MDER) and the Multi-driver Disable
Register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or
assigned to a peripheral function. The Multi-driver Status Register (PIO_MDSR) indicates the pins that are
configured to support external drivers.
After reset, the multi-drive feature is disabled on all pins, i.e., PIO_MDSR resets at value 0x0.
32.5.7 Output Line Timings
Figure 32-3 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing
PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 32-3 also shows when
the feedback in the Pin Data Status Register (PIO_PDSR) is available.
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Figure 32-3.
Output Line Timings
Peripheral clock
Write PIO_SODR
Write PIO_ODSR at 1
APB Access
Write PIO_CODR
Write PIO_ODSR at 0
APB Access
PIO_ODSR
2 cycles
2 cycles
PIO_PDSR
32.5.8 Inputs
The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines
regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a
peripheral.
Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the
levels present on the I/O line at the time the clock was disabled.
32.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 peripheral clock and the debouncing filter can filter
a pulse of less than 1/2 period of a programmable divided slow clock.
The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock
Disable Register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable Register (PIO_IFSCER). Writing
PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status Register
(PIO_IFSCSR).
The current selection status can be checked by reading the PIO_IFSCSR.
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable
divided slow clock period.
For the debouncing filter, the period of the divided slow clock is defined by writing in the DIV field of the Slow Clock
Divider Debouncing Register (PIO_SCDR):
tdiv_slck = ((DIV + 1) × 2) × tslck
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock
cycle (selected clock represents peripheral clock or divided slow clock depending on PIO_IFSCDR and
PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock
(peripheral clock or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock
cycle and one selected clock cycle, the pulse may or may not be taken into account, depending on the precise
timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch
to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle.
The filters also introduce some latencies, illustrated in Figure 32-4 and Figure 32-5.
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The glitch filters are controlled by the Input Filter Enable Register (PIO_IFER), the Input Filter Disable Register
(PIO_IFDR) and the Input Filter Status Register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets
and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the
peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and
debouncing filters require that the peripheral clock is enabled.
Figure 32-4.
Input Glitch Filter Timing
PIO_IFCSR = 0
Peripheral clcok
up to 1.5 cycles
Pin Level
1 cycle
1 cycle
1 cycle
1 cycle
PIO_PDSR
if PIO_IFSR = 0
2 cycles
up to 2.5 cycles
PIO_PDSR
if PIO_IFSR = 1
Figure 32-5.
1 cycle
up to 2 cycles
Input Debouncing Filter Timing
PIO_IFCSR = 1
Divided Slow Clock
(div_slck)
Pin Level
up to 2 cycles tperipheral clock
up to 2 cycles tperipheral clock
PIO_PDSR
if PIO_IFSR = 0
1 cycle tdiv_slck
PIO_PDSR
if PIO_IFSR = 1
1 cycle tdiv_slck
up to 1.5 cycles tdiv_slck
up to 1.5 cycles tdiv_slck
up to 2 cycles tperipheral clock
up to 2 cycles tperipheral clock
32.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line.
The Input Edge/Level interrupt is controlled by writing the Interrupt Enable Register (PIO_IER) and the Interrupt
Disable Register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and
clearing the corresponding bit in the Interrupt Mask Register (PIO_IMR). As input change detection is possible only
by comparing two successive samplings of the input of the I/O line, the peripheral clock must be enabled. The
Input Change interrupt is available regardless of the configuration of the I/O line, i.e., configured as an input only,
controlled by the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable
Register (PIO_AIMER) and Additional Interrupt Modes Disable Register (PIO_AIMDR). The current state of this
selection can be read through the Additional Interrupt Modes Mask Register (PIO_AIMMR).
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These additional modes are:
Rising edge detection
Falling edge detection
Low-level detection
High-level detection
In order to select an additional interrupt mode:
The type of event detection (edge or level) must be selected by writing in the Edge Select Register
(PIO_ESR) and Level Select Register (PIO_LSR) which select, respectively, the edge and level detection.
The current status of this selection is accessible through the Edge/Level Status Register (PIO_ELSR).
The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the
Falling Edge/Low-Level Select Register (PIO_FELLSR) and Rising Edge/High-Level Select Register
(PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or highor low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible
through the Fall/Rise - Low/High Status Register (PIO_FRLHSR).
When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status Register
(PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The
interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt
controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts
that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
Figure 32-6.
Event Detector on Input Lines (Figure Represents Line 0)
Event Detector
Rising Edge
Detector
1
Falling Edge
Detector
0
0
PIO_REHLSR[0]
1
PIO_FRLHSR[0]
PIO_FELLSR[0]
Resynchronized input on line 0
Event detection on line 0
1
0
High Level
Detector
1
Low Level
Detector
0
PIO_LSR[0]
PIO_ELSR[0]
PIO_ESR[0]
PIO_AIMER[0]
PIO_AIMMR[0]
PIO_AIMDR[0]
Edge
Detector
Example of interrupt generation on following lines:
Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Low-level on PIO line 3
High-level on PIO line 4
High-level on PIO line 5
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Falling edge on PIO line 6
Rising edge on PIO line 7
Any edge on the other lines
Table 32-2 provides the required configuration for this example.
Table 32-2.
Configuration for Example Interrupt Generation
Configuration
Description
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Interrupt Mode
Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in
PIO_AIMER.
Edge or Level Detection
The other lines are configured in edge detection by default, if they have not been previously
configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing
32’h0000_00C7 in PIO_ESR.
Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR.
Falling/Rising Edge or Low/High-Level
Detection
Figure 32-7.
Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing
32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in falling edge or low-level detection by default if they have
not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling
edge/low-level detection by writing 32’h0000_004A in PIO_FELLSR.
Input Change Interrupt Timings When No Additional Interrupt Modes
Peripheral clock
Pin Level
PIO_ISR
Read PIO_ISR
APB Access
APB Access
32.5.11 Programmable I/O Drive
It is possible to configure the I/O drive for pads PA0 to PA31. Refer to Section 46. “Electrical Characteristics”.
32.5.12 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the
Schmitt trigger is requested when using the QTouch® Library.
32.5.13 I/O Lines Programming Example
The programming example shown in Table 32-3 is used to obtain the following configuration:
624
4-bit output port on I/O lines 0 to 3 (should be written in a single write operation), open-drain, with pull-up
resistor
Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor,
no pull-down resistor
Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch
filters and input change interrupts
SAM4CM Series [DATASHEET]
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Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change
interrupt), no pull-up resistor, no glitch filter
I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor
I/O lines 24 to 27 assigned to peripheral C with input change interrupt, no pull-up resistor and no pull-down
resistor
I/O lines 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor
Table 32-3.
Programming Example
Register
Value to be Written
PIO_PER
0x0000_FFFF
PIO_PDR
0xFFFF_0000
PIO_OER
0x0000_00FF
PIO_ODR
0xFFFF_FF00
PIO_IFER
0x0000_0F00
PIO_IFDR
0xFFFF_F0FF
PIO_SODR
0x0000_0000
PIO_CODR
0x0FFF_FFFF
PIO_IER
0x0F00_0F00
PIO_IDR
0xF0FF_F0FF
PIO_MDER
0x0000_000F
PIO_MDDR
0xFFFF_FFF0
PIO_PUDR
0xFFF0_00F0
PIO_PUER
0x000F_FF0F
PIO_PPDDR
0xFF0F_FFFF
PIO_PPDER
0x00F0_0000
PIO_ABCDSR1
0xF0F0_0000
PIO_ABCDSR2
0xFF00_0000
PIO_OWER
0x0000_000F
PIO_OWDR
0x0FFF_FFF0
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32.5.14 Register Write Protection
To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the PIO Write Protection Mode Register (PIO_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the PIO Write Protection Status
Register (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the PIO_WPSR.
The following registers can be write-protected:
626
PIO Enable Register
PIO Disable Register
PIO Output Enable Register
PIO Output Disable Register
PIO Input Filter Enable Register
PIO Input Filter Disable Register
PIO Multi-driver Enable Register
PIO Multi-driver Disable Register
PIO Pull-Up Disable Register
PIO Pull-Up Enable Register
PIO Peripheral ABCD Select Register 1
PIO Peripheral ABCD Select Register 2
PIO Output Write Enable Register
PIO Output Write Disable Register
PIO Pad Pull-Down Disable Register
PIO Pad Pull-Down Enable Register
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32.6
Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface
registers. Each register is 32-bit wide. If a parallel I/O line is not defined, writing to the corresponding bits has no
effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the
PIO Controller and PIO_PSR returns one systematically.
Table 32-4.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
PIO Enable Register
PIO_PER
Write-only
–
0x0004
PIO Disable Register
PIO_PDR
Write-only
–
Read-only
(1)
–
–
0x0008
PIO Status Register
PIO_PSR
0x000C
Reserved
–
0x0010
Output Enable Register
PIO_OER
Write-only
–
0x0014
Output Disable Register
PIO_ODR
Write-only
–
0x0018
Output Status Register
PIO_OSR
Read-only
0x00000000
0x001C
Reserved
–
–
–
0x0020
Glitch Input Filter Enable Register
PIO_IFER
Write-only
–
0x0024
Glitch Input Filter Disable Register
PIO_IFDR
Write-only
–
0x0028
Glitch Input Filter Status Register
PIO_IFSR
Read-only
0x00000000
0x002C
Reserved
–
–
–
0x0030
Set Output Data Register
PIO_SODR
Write-only
–
0x0034
Clear Output Data Register
PIO_CODR
Write-only
0x0038
Output Data Status Register
PIO_ODSR
Read-only
or(2)
Read/Write
–
0x003C
Pin Data Status Register
PIO_PDSR
Read-only
(3)
0x0040
Interrupt Enable Register
PIO_IER
Write-only
–
0x0044
Interrupt Disable Register
PIO_IDR
Write-only
–
0x0048
Interrupt Mask Register
PIO_IMR
Read-only
0x00000000
(4)
0x004C
Interrupt Status Register
PIO_ISR
Read-only
0x00000000
0x0050
Multi-driver Enable Register
PIO_MDER
Write-only
–
0x0054
Multi-driver Disable Register
PIO_MDDR
Write-only
–
0x0058
Multi-driver Status Register
PIO_MDSR
Read-only
0x00000000
0x005C
Reserved
–
–
–
0x0060
Pull-up Disable Register
PIO_PUDR
Write-only
–
0x0064
Pull-up Enable Register
PIO_PUER
Write-only
–
0x0068
Pad Pull-up Status Register
PIO_PUSR
Read-only
(1)
0x006C
Reserved
–
–
–
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
627
Table 32-4.
Register Mapping (Continued)
Offset
Register
Name
Access
Reset
0x0070
Peripheral Select Register 1
PIO_ABCDSR1
Read/Write
0x00000000
0x0074
Peripheral Select Register 2
PIO_ABCDSR2
Read/Write
0x00000000
0x0078–0x007C
Reserved
–
–
–
0x0080
Input Filter Slow Clock Disable Register
PIO_IFSCDR
Write-only
–
0x0084
Input Filter Slow Clock Enable Register
PIO_IFSCER
Write-only
–
0x0088
Input Filter Slow Clock Status Register
PIO_IFSCSR
Read-only
0x00000000
0x008C
Slow Clock Divider Debouncing Register
PIO_SCDR
Read/Write
0x00000000
0x0090
Pad Pull-down Disable Register
PIO_PPDDR
Write-only
–
0x0094
Pad Pull-down Enable Register
PIO_PPDER
Write-only
–
Read-only
(1)
–
–
0x0098
Pad Pull-down Status Register
PIO_PPDSR
0x009C
Reserved
–
0x00A0
Output Write Enable
PIO_OWER
Write-only
–
0x00A4
Output Write Disable
PIO_OWDR
Write-only
–
0x00A8
Output Write Status Register
PIO_OWSR
Read-only
0x00000000
0x00AC
Reserved
–
–
–
0x00B0
Additional Interrupt Modes Enable Register
PIO_AIMER
Write-only
–
0x00B4
Additional Interrupt Modes Disable Register
PIO_AIMDR
Write-only
–
0x00B8
Additional Interrupt Modes Mask Register
PIO_AIMMR
Read-only
0x00000000
0x00BC
Reserved
–
–
–
0x00C0
Edge Select Register
PIO_ESR
Write-only
–
0x00C4
Level Select Register
PIO_LSR
Write-only
–
0x00C8
Edge/Level Status Register
PIO_ELSR
Read-only
0x00000000
0x00CC
Reserved
–
–
–
0x00D0
Falling Edge/Low-Level Select Register
PIO_FELLSR
Write-only
–
0x00D4
Rising Edge/High-Level Select Register
PIO_REHLSR
Write-only
–
0x00D8
Fall/Rise - Low/High Status Register
PIO_FRLHSR
Read-only
0x00000000
0x00DC
Reserved
–
–
–
0x00E0
Reserved
–
–
–
0x00E4
Write Protection Mode Register
PIO_WPMR
Read/Write
0x00000000
0x00E8
Write Protection Status Register
PIO_WPSR
Read-only
0x00000000
0x00EC–0x00FC
Reserved
–
–
–
0x0100
Schmitt Trigger Register
PIO_SCHMITT
Read/Write
0x00000000
0x0104–0x010C
Reserved
–
–
–
0x0110
Reserved
–
–
–
0x0114
Reserved
–
–
–
0x0118
I/O Drive Register
PIO_DRIVER
Read/Write
0x00000000
0x011C
Reserved
–
–
–
628
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 32-4.
Offset
Register Mapping (Continued)
Register
Name
Access
Reset
0x0120–0x014C
Reserved
–
–
–
Notes: 1. Reset value depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
5. If an offset is not listed in the table it must be considered as reserved.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
629
32.6.1 PIO Enable Register
Name:
PIO_PER
Address:
0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x4800C000 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: PIO Enable
0: No effect.
1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
630
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.2 PIO Disable Register
Name:
PIO_PDR
Address:
0x400E0E04 (PIOA), 0x400E1004 (PIOB), 0x4800C004 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: PIO Disable
0: No effect.
1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
631
32.6.3 PIO Status Register
Name:
PIO_PSR
Address:
0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x4800C008 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: PIO Status
0: PIO is inactive on the corresponding I/O line (peripheral is active).
1: PIO is active on the corresponding I/O line (peripheral is inactive).
632
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.4 PIO Output Enable Register
Name:
PIO_OER
Address:
0x400E0E10 (PIOA), 0x400E1010 (PIOB), 0x4800C010 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Enable
0: No effect.
1: Enables the output on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
633
32.6.5 PIO Output Disable Register
Name:
PIO_ODR
Address:
0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x4800C014 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Disable
0: No effect.
1: Disables the output on the I/O line.
634
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.6 PIO Output Status Register
Name:
PIO_OSR
Address:
0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x4800C018 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Output Status
0: The I/O line is a pure input.
1: The I/O line is enabled in output.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
635
32.6.7 PIO Input Filter Enable Register
Name:
PIO_IFER
Address:
0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x4800C020 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Input Filter Enable
0: No effect.
1: Enables the input glitch filter on the I/O line.
636
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.8 PIO Input Filter Disable Register
Name:
PIO_IFDR
Address:
0x400E0E24 (PIOA), 0x400E1024 (PIOB), 0x4800C024 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Input Filter Disable
0: No effect.
1: Disables the input glitch filter on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
637
32.6.9 PIO Input Filter Status Register
Name:
PIO_IFSR
Address:
0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x4800C028 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Input Filter Status
0: The input glitch filter is disabled on the I/O line.
1: The input glitch filter is enabled on the I/O line.
638
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.10 PIO Set Output Data Register
Name:
PIO_SODR
Address:
0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x4800C030 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Set Output Data
0: No effect.
1: Sets the data to be driven on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
639
32.6.11 PIO Clear Output Data Register
Name:
PIO_CODR
Address:
0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x4800C034 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Clear Output Data
0: No effect.
1: Clears the data to be driven on the I/O line.
640
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.12 PIO Output Data Status Register
Name:
PIO_ODSR
Address:
0x400E0E38 (PIOA), 0x400E1038 (PIOB), 0x4800C038 (PIOC)
Access:
Read-only or Read/Write
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Output Data Status
0: The data to be driven on the I/O line is 0.
1: The data to be driven on the I/O line is 1.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
641
32.6.13 PIO Pin Data Status Register
Name:
PIO_PDSR
Address:
0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x4800C03C (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Output Data Status
0: The I/O line is at level 0.
1: The I/O line is at level 1.
642
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.14 PIO Interrupt Enable Register
Name:
PIO_IER
Address:
0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x4800C040 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Input Change Interrupt Enable
0: No effect.
1: Enables the input change interrupt on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
643
32.6.15 PIO Interrupt Disable Register
Name:
PIO_IDR
Address:
0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x4800C044 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Input Change Interrupt Disable
0: No effect.
1: Disables the input change interrupt on the I/O line.
644
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.16 PIO Interrupt Mask Register
Name:
PIO_IMR
Address:
0x400E0E48 (PIOA), 0x400E1048 (PIOB), 0x4800C048 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Input Change Interrupt Mask
0: Input change interrupt is disabled on the I/O line.
1: Input change interrupt is enabled on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
645
32.6.17 PIO Interrupt Status Register
Name:
PIO_ISR
Address:
0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x4800C04C (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Input Change Interrupt Status
0: No input change has been detected on the I/O line since PIO_ISR was last read or since reset.
1: At least one input change has been detected on the I/O line since PIO_ISR was last read or since reset.
646
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.18 PIO Multi-driver Enable Register
Name:
PIO_MDER
Address:
0x400E0E50 (PIOA), 0x400E1050 (PIOB), 0x4800C050 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0-P31: Multi-drive Enable
0: No effect.
1: Enables multi-drive on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
647
32.6.19 PIO Multi-driver Disable Register
Name:
PIO_MDDR
Address:
0x400E0E54 (PIOA), 0x400E1054 (PIOB), 0x4800C054 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Multi-drive Disable
0: No effect.
1: Disables multi-drive on the I/O line.
648
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.20 PIO Multi-driver Status Register
Name:
PIO_MDSR
Address:
0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x4800C058 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Multi-drive Status
0: The multi-drive is disabled on the I/O line. The pin is driven at high- and low-level.
1: The multi-drive is enabled on the I/O line. The pin is driven at low-level only.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
649
32.6.21 PIO Pull-Up Disable Register
Name:
PIO_PUDR
Address:
0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x4800C060 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Up Disable
0: No effect.
1: Disables the pull-up resistor on the I/O line.
650
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.22 PIO Pull-Up Enable Register
Name:
PIO_PUER
Address:
0x400E0E64 (PIOA), 0x400E1064 (PIOB), 0x4800C064 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Up Enable
0: No effect.
1: Enables the pull-up resistor on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
651
32.6.23 PIO Pull-Up Status Register
Name:
PIO_PUSR
Address:
0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x4800C068 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Pull-Up Status
0: Pull-up resistor is enabled on the I/O line.
1: Pull-up resistor is disabled on the I/O line.
652
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.24 PIO Peripheral ABCD Select Register 1
Name:
PIO_ABCDSR1
Access:
Read/Write
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Peripheral Select
If the same bit is set to 0 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral B function.
If the same bit is set to 1 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral C function.
1: Assigns the I/O line to the Peripheral D function.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
653
32.6.25 PIO Peripheral ABCD Select Register 2
Name:
PIO_ABCDSR2
Address:
0x400E0E70 (PIOA), 0x400E1070 (PIOB), 0x4800C070 (PIOC)
Access:
Read/Write
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Peripheral Select
If the same bit is set to 0 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral C function.
If the same bit is set to 1 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral B function.
1: Assigns the I/O line to the Peripheral D function.
654
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.26 PIO Input Filter Slow Clock Disable Register
Name:
PIO_IFSCDR
Address:
0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x4800C080 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Peripheral Clock Glitch Filtering Select
0: No effect.
1: The glitch filter is able to filter glitches with a duration < tperipheral clock/2.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
655
32.6.27 PIO Input Filter Slow Clock Enable Register
Name:
PIO_IFSCER
Address:
0x400E0E84 (PIOA), 0x400E1084 (PIOB), 0x4800C084 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Slow Clock Debouncing Filtering Select
0: No effect.
1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2.
656
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.28 PIO Input Filter Slow Clock Status Register
Name:
PIO_IFSCSR
Address:
0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x4800C088 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Glitch or Debouncing Filter Selection Status
0: The glitch filter is able to filter glitches with a duration < tperipheral clock/2.
1: The debouncing filter is able to filter pulses with a duration < tdiv_slck/2.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
657
32.6.29 PIO Slow Clock Divider Debouncing Register
Name:
PIO_SCDR
Address:
0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x4800C08C (PIOC)
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
2
1
0
–
–
7
6
DIV
5
4
3
DIV
• DIV: Slow Clock Divider Selection for Debouncing
tdiv_slck = ((DIV + 1) × 2) × tslck
658
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.30 PIO Pad Pull-Down Disable Register
Name:
PIO_PPDDR
Address:
0x400E0E90 (PIOA), 0x400E1090 (PIOB), 0x4800C090 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Down Disable
0: No effect.
1: Disables the pull-down resistor on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
659
32.6.31 PIO Pad Pull-Down Enable Register
Name:
PIO_PPDER
Address:
0x400E0E94 (PIOA), 0x400E1094 (PIOB), 0x4800C094 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Pull-Down Enable
0: No effect.
1: Enables the pull-down resistor on the I/O line.
660
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.32 PIO Pad Pull-Down Status Register
Name:
PIO_PPDSR
Address:
0x400E0E98 (PIOA), 0x400E1098 (PIOB), 0x4800C098 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Pull-Down Status
0: Pull-down resistor is enabled on the I/O line.
1: Pull-down resistor is disabled on the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
661
32.6.33 PIO Output Write Enable Register
Name:
PIO_OWER
Address:
0x400E0EA0 (PIOA), 0x400E10A0 (PIOB), 0x4800C0A0 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Write Enable
0: No effect.
1: Enables writing PIO_ODSR for the I/O line.
662
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.34 PIO Output Write Disable Register
Name:
PIO_OWDR
Address:
0x400E0EA4 (PIOA), 0x400E10A4 (PIOB), 0x4800C0A4 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
This register can only be written if the WPEN bit is cleared in the PIO Write Protection Mode Register.
• P0–P31: Output Write Disable
0: No effect.
1: Disables writing PIO_ODSR for the I/O line.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
663
32.6.35 PIO Output Write Status Register
Name:
PIO_OWSR
Address:
0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x4800C0A8 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Output Write Status
0: Writing PIO_ODSR does not affect the I/O line.
1: Writing PIO_ODSR affects the I/O line.
664
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
32.6.36 PIO Additional Interrupt Modes Enable Register
Name:
PIO_AIMER
Address:
0x400E0EB0 (PIOA), 0x400E10B0 (PIOB), 0x4800C0B0 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Additional Interrupt Modes Enable
0: No effect.
1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR.
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665
32.6.37 PIO Additional Interrupt Modes Disable Register
Name:
PIO_AIMDR
Address:
0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x4800C0B4 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Additional Interrupt Modes Disable
0: No effect.
1: The interrupt mode is set to the default interrupt mode (both-edge detection).
666
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32.6.38 PIO Additional Interrupt Modes Mask Register
Name:
PIO_AIMMR
Address:
0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x4800C0B8 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: IO Line Index
Selects the IO event type triggering an interrupt.
0: The interrupt source is a both-edge detection event.
1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR.
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667
32.6.39 PIO Edge Select Register
Name:
PIO_ESR
Address:
0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x4800C0C0 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Edge Interrupt Selection
0: No effect.
1: The interrupt source is an edge-detection event.
668
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32.6.40 PIO Level Select Register
Name:
PIO_LSR
Address:
0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x4800C0C4 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Level Interrupt Selection
0: No effect.
1: The interrupt source is a level-detection event.
SAM4CM Series [DATASHEET]
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669
32.6.41 PIO Edge/Level Status Register
Name:
PIO_ELSR
Address:
0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x4800C0C8 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Edge/Level Interrupt Source Selection
0: The interrupt source is an edge-detection event.
1: The interrupt source is a level-detection event.
670
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32.6.42 PIO Falling Edge/Low-Level Select Register
Name:
PIO_FELLSR
Address:
0x400E0ED0 (PIOA), 0x400E10D0 (PIOB), 0x4800C0D0 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Falling Edge/Low-Level Interrupt Selection
0: No effect.
1: The interrupt source is set to a falling edge detection or low-level detection event, depending on PIO_ELSR.
SAM4CM Series [DATASHEET]
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671
32.6.43 PIO Rising Edge/High-Level Select Register
Name:
PIO_REHLSR
Address:
0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x4800C0D4 (PIOC)
Access:
Write-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Rising Edge/High-Level Interrupt Selection
0: No effect.
1: The interrupt source is set to a rising edge detection or high-level detection event, depending on PIO_ELSR.
672
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32.6.44 PIO Fall/Rise - Low/High Status Register
Name:
PIO_FRLHSR
Address:
0x400E0ED8 (PIOA), 0x400E10D8 (PIOB), 0x4800C0D8 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
P31
P30
P29
P28
P27
P26
P25
P24
23
22
21
20
19
18
17
16
P23
P22
P21
P20
P19
P18
P17
P16
15
14
13
12
11
10
9
8
P15
P14
P13
P12
P11
P10
P9
P8
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0–P31: Edge/Level Interrupt Source Selection
0: The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if PIO_ELSR = 1).
1: The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if PIO_ELSR = 1).
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673
32.6.45 PIO Write Protection Mode Register
Name:
PIO_WPMR
Address:
0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x4800C0E4 (PIOC)
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
WPEN
• WPEN: Write Protection Enable
0: Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
See Section 32.5.14 “Register Write Protection” for the list of registers that can be protected.
• WPKEY: Write Protection Key
Value
Name
0x50494F
PASSWD
674
Description
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as
0.
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32.6.46 PIO Write Protection Status Register
Name:
PIO_WPSR
Address:
0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x4800C0E8 (PIOC)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
11
10
9
8
WPVSRC
15
14
13
12
WPVSRC
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
WPVS
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of the PIO_WPSR.
1: A write protection violation has occurred since the last read of the PIO_WPSR. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
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675
32.6.47 PIO Schmitt Trigger Register
Name:
PIO_SCHMITT
Address:
0x400E0F00 (PIOA), 0x400E1100 (PIOB), 0x4800C100 (PIOC)
Access:
Read/Write
31
30
29
28
27
26
25
24
SCHMITT31
SCHMITT30
SCHMITT29
SCHMITT28
SCHMITT27
SCHMITT26
SCHMITT25
SCHMITT24
23
22
21
20
19
18
17
16
SCHMITT23
SCHMITT22
SCHMITT21
SCHMITT20
SCHMITT19
SCHMITT18
SCHMITT17
SCHMITT16
15
14
13
12
11
10
9
8
SCHMITT15
SCHMITT14
SCHMITT13
SCHMITT12
SCHMITT11
SCHMITT10
SCHMITT9
SCHMITT8
7
6
5
4
3
2
1
0
SCHMITT7
SCHMITT6
SCHMITT5
SCHMITT4
SCHMITT3
SCHMITT2
SCHMITT1
SCHMITT0
• SCHMITTx [x=0..31]: Schmitt Trigger Control
0: Schmitt trigger is enabled.
1: Schmitt trigger is disabled.
676
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32.6.48 PIO I/O Drive Register
Name:
PIO_DRIVER
Address:
0x400E0F18 (PIOA), 0x400E1118 (PIOB), 0x4800C118 (PIOC)
Access:
Read/Write
31
30
29
28
27
26
25
24
LINE31
LINE30
LINE29
LINE28
LINE27
LINE26
LINE25
LINE24
23
22
21
20
19
18
17
16
LINE23
LINE22
LINE21
LINE20
LINE19
LINE18
LINE17
LINE16
15
14
13
12
11
10
9
8
LINE15
LINE14
LINE13
LINE12
LINE11
LINE10
LINE9
LINE8
7
6
5
4
3
2
1
0
LINE7
LINE6
LINE5
LINE4
LINE3
LINE2
LINE1
LINE0
• LINEx [x=0..31]: Drive of PIO Line x
Value
Name
Description
0
LOW_DRIVE
Lowest drive
1
HIGH_DRIVE
Highest drive
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33.
Serial Peripheral Interface (SPI)
33.1
Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with
external devices in Master or Slave mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is essentially a Shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (multiple
master protocol, contrary to single master protocol where one CPU is always the master while all of the others are
always slaves). One master can simultaneously shift data into multiple slaves. However, only one slave can drive
its output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master
generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
33.2
Master Out Slave In (MOSI)—This data line supplies the output data from the master shifted into the input(s)
of the slave(s).
Master In Slave Out (MISO)—This data line supplies the output data from a slave to the input of the master.
There may be no more than one slave transmitting data during any particular transfer.
Serial Clock (SPCK)—This control line is driven by the master and regulates the flow of the data bits. The
master can transmit data at a variety of baud rates; there is one SPCK pulse for each bit that is transmitted.
Slave Select (NSS)—This control line allows slaves to be turned on and off by hardware.
Embedded Characteristics
Master or Slave Serial Peripheral Bus Interface
8-bit to 16-bit programmable data length per chip select
̶
Programmable phase and polarity per chip select
̶
Programmable transfer delay between consecutive transfers and delay before SPI clock per chip
select
̶
̶
̶
Programmable delay between chip selects
Master Mode can drive SPCK up to Peripheral Clock
Master Mode Bit Rate can be Independent of the Processor/Peripheral Clock
Slave mode operates on SPCK, asynchronously with core and bus clock
Four chip selects with external decoder support allow communication with up to 15 peripherals
Communication with Serial External Devices Supported
̶
678
Selectable mode fault detection
̶
Serial memories, such as DataFlash and 3-wire EEPROMs
̶
Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and sensors
External coprocessors
Connection to PDC Channel Capabilities, Optimizing Data Transfers
̶
One channel for the receiver
̶
One channel for the transmitter
Register Write Protection
SAM4CM Series [DATASHEET]
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33.3
Block Diagram
Figure 33-1.
Block Diagram
AHB Matrix
PDC
Peripheral bridge
Trigger
events
Bus clock
PMC
33.4
Peripheral
clock
SPI
Application Block Diagram
Figure 33-2.
Application Block Diagram: Single Master/Multiple Slave Implementation
SPI Master
SPCK
SPCK
MISO
MISO
MOSI
MOSI
NPCS0
NSS
Slave 0
SPCK
NPCS1
NPCS2
NPCS3
NC
MISO
Slave 1
MOSI
NSS
SPCK
MISO
Slave 2
MOSI
NSS
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679
33.5
Signal Description
Table 33-1.
Signal Description
Type
33.6
Pin Name
Pin Description
Master
Slave
MISO
Master In Slave Out
Input
Output
MOSI
Master Out Slave In
Output
Input
SPCK
Serial Clock
Output
Input
NPCS1–NPCS3
Peripheral Chip Selects
Output
Unused
NPCS0/NSS
Peripheral Chip Select/Slave Select
Output
Input
Product Dependencies
33.6.1 I/O Lines
The pins used for interfacing the compliant external devices can be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the SPI pins to their peripheral functions.
Table 33-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
SPI0
SPI0_MISO
PA6
A
SPI0
SPI0_MOSI
PA7
A
SPI0
SPI0_NPCS0
PA5
A
SPI0
SPI0_NPCS1
PA21
A
SPI0
SPI0_NPCS2
PA22
A
SPI0
SPI0_NPCS3
PA23
A
SPI0
SPI0_SPCK
PA8
A
33.6.2 Power Management
The SPI can be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SPI clock.
33.6.3 Interrupt
The SPI interface has an interrupt line connected to the interrupt controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
Table 33-3.
Peripheral IDs
Instance
ID
SPI0
21
33.6.4 Peripheral DMA Controller (PDC)
The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full
description of the PDC, refer to Section 28. “Peripheral DMA Controller (PDC)”.
680
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33.7
Functional Description
33.7.1 Modes of Operation
The SPI operates in Master mode or in Slave mode.
The SPI operates in Master mode by writing a 1 to the MSTR bit in the SPI Mode Register (SPI_MR):
̶
Pins NPCS0 to NPCS3 are all configured as outputs
̶
The SPCK pin is driven
̶
The MISO line is wired on the receiver input
̶
The MOSI line is driven as an output by the transmitter.
The SPI operates in Slave mode if the MSTR bit in the SPI_MR is written to 0:
̶
The MISO line is driven by the transmitter output
̶
The MOSI line is wired on the receiver input
̶
The SPCK pin is driven by the transmitter to synchronize the receiver.
̶
The NPCS0 pin becomes an input, and is used as a slave select signal (NSS)
̶
NPCS1 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is
activated only in Master mode.
33.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These
two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two
parameters has two possible states, resulting in four possible combinations that are incompatible with one another.
Consequently, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves
are connected and require different configurations, the master must reconfigure itself each time it needs to
communicate with a different slave.
Table 33-4 shows the four modes and corresponding parameter settings.
Table 33-4.
SPI Bus Protocol Mode
SPI Mode
CPOL
NCPHA
Shift SPCK Edge
Capture SPCK Edge
SPCK Inactive Level
0
0
1
Falling
Rising
Low
1
0
0
Rising
Falling
Low
2
1
1
Rising
Falling
High
3
1
0
Falling
Rising
High
Figure 33-3 and Figure 33-4 show examples of data transfers.
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681
Figure 33-3.
SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
1
SPCK cycle (for reference)
2
3
4
6
5
7
8
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MSB
MISO
(from slave)
MSB
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
*
NSS
(to slave)
* Not defined.
Figure 33-4.
SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
1
SPCK cycle (for reference)
2
3
4
5
8
7
6
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
*
MSB
6
5
4
3
2
1
MSB
6
5
4
3
2
1
NSS
(to slave)
* Not defined.
682
SAM4CM Series [DATASHEET]
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LSB
LSB
33.7.3 Master Mode Operations
When configured in Master mode, the SPI operates on the clock generated by the internal programmable baud
rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives
the chip select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register (SPI_TDR) and the Receive Data Register
(SPI_RDR), and a single shift register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer starts when the processor writes to the SPI_TDR. The written data is
immediately transferred in the Shift register and the transfer on the SPI bus starts. While the data in the Shift
register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift register. Data cannot be
loaded in the SPI_RDR without transmitting data. If there is no data to transmit, dummy data can be used
(SPI_TDR filled with ones). When the SPI_MR.WDRBT bit is set, new data cannot be transmitted if the SPI_RDR
has not been read. If Receiving mode is not required, for example when communicating with a slave receiver only
(such as an LCD), the receive status flags in the SPI Status register (SPI_SR) can be discarded.
Before writing the SPI_TDR, the PCS field in the SPI_MR must be set in order to select a slave.
If new data is written in the SPI_TDR during the transfer, it is kept in the SPI_TDR until the current transfer is
completed. Then, the received data is transferred from the Shift register to the SPI_RDR, the data in the SPI_TDR
is loaded in the Shift register and a new transfer starts.
As soon as the SPI_TDR is written, the Transmit Data Register Empty (TDRE) flag in the SPI_SR is cleared. When
the data written in the SPI_TDR is loaded into the Shift register, the TDRE flag in the SPI_SR is set. The TDRE bit
is used to trigger the Transmit PDC channel.
See Figure 33-5.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR. If a transfer delay (DLYBCT) is greater than
0 for the last transfer, TXEMPTY is set after the completion of this delay. The peripheral clock can be switched off
at this time.
Note:
Figure 33-5.
When the SPI is enabled, the TDRE and TXEMPTY flags are set.
TDRE and TXEMPTY flag behavior
Write SPI_CR.SPIEN =1
TDRE
Write SPI_TDR
Write SPI_TDR
automatic set
TDR loaded
in shifter
Write SPI_TDR
automatic set
TDR loaded
in shifter
automatic set
TDR loaded
in shifter
TXEMPTY
Transfer
Transfer
DLYBCT
Transfer
DLYBCT
DLYBCT
The transfer of received data from the Shift register to the SPI_RDR is indicated by the Receive Data Register Full
(RDRF) bit in the SPI_SR. When the received data is read, the RDRF bit is cleared.
If the SPI_RDR has not been read before new data is received, the Overrun Error (OVRES) bit in the SPI_SR is
set. As long as this flag is set, data is loaded in the SPI_RDR. The user has to read the SPI_SR to clear the
OVRES bit.
Figure 33-6 shows a block diagram of the SPI when operating in Master mode. Figure 33-7 shows a flow chart
describing how transfers are handled.
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33.7.3.1 Master Mode Block Diagram
Figure 33-6.
Master Mode Block Diagram
SPI_CSRx
SCBR
Baud Rate Generator
Peripheral clock
SPCK
SPI
Clock
SPI_CSRx
BITS
NCPHA
CPOL
LSB
MISO
SPI_RDR
RDRF
OVRES
RD
MSB
Shift Register
MOSI
SPI_TDR
TDRE
TD
SPI_CSRx
SPI_RDR
CSAAT
PCS
PS
NPCSx
PCSDEC
SPI_MR
PCS
0
Current
Peripheral
SPI_TDR
NPCS0
PCS
1
MSTR
MODF
NPCS0
MODFDIS
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33.7.3.2 Master Mode Flow Diagram
Figure 33-7.
Master Mode Flow Diagram
SPI Enable
TDRE/TXEMPTY are set
0
TDRE ?
(SW check)
1
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- ‘x 1
Divide
by 16
1
0
Baud Rate
Clock
0
Receiver
Sampling Clock
35.5.2 Receiver
35.5.2.1 Receiver Reset, Enable and Disable
After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be
enabled by writing the Control Register (UART_CR) with the bit RXEN at 1. At this command, the receiver starts
looking for a start bit.
The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for
a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the
data, it waits for the stop bit before actually stopping its operation.
The receiver can be put in reset state by writing UART_CR with the bit RSTRX at 1. In this case, the receiver
immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data
is being processed, this data is lost.
35.5.2.2 Start Detection and Data Sampling
The UART only supports asynchronous operations, and this affects only its receiver. The UART receiver detects
the start of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on
URXD is interpreted as a valid start bit if it is detected for more than seven cycles of the sampling clock, which is
16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A
space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It
is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles
(0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after
detecting the falling edge of the start bit.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 35-3.
Start Bit Detection
URXD
S
D0
D1 D2
D3
D4 D5 D6
D7
P
stop S
D0
D1 D2
D3 D4
D5
D6
D7
P stop
RXRDY
OVRE
RSTSTA
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Figure 35-4.
Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit
period
1 bit
period
URXD
Sampling
D0
D1
True Start Detection
D2
D3
D4
D5
D6
Stop Bit
D7
Parity Bit
35.5.2.3 Receiver Ready
When a complete character is received, it is transferred to the Receive Holding Register (UART_RHR) and the
RXRDY status bit in the Status Register (UART_SR) is set. The bit RXRDY is automatically cleared when
UART_RHR is read.
Figure 35-5.
Receiver Ready
S
URXD
D0
D1
D2
D3
D4
D5
D6
D7
S
P
D0
D1
D2
D3
D4
D5
D6
D7
P
RXRDY
Read UART_RHR
35.5.2.4 Receiver Overrun
The OVRE status bit in UART_SR is set if UART_RHR has not been read by the software (or the PDC) since the
last transfer, the RXRDY bit is still set and a new character is received. OVRE is cleared when the software writes
a 1 to the bit RSTSTA (Reset Status) in UART_CR.
Figure 35-6.
URXD
Receiver Overrun
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
OVRE
RSTSTA
35.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with
the field PAR in the Mode Register (UART_MR). It then compares the result with the received parity bit. If different,
the parity error bit PARE in UART_SR is set at the same time RXRDY is set. The parity bit is cleared when
UART_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status
command is written, the PARE bit remains at 1.
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Figure 35-7.
Parity Error
S
URXD
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
PARE
Wrong Parity Bit
RSTSTA
35.5.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same
time the RXRDY bit is set. The FRAME bit remains high until the Control Register (UART_CR) is written with the
bit RSTSTA at 1.
Figure 35-8.
Receiver Framing Error
URXD
S
D0
D1
D2
D3
D4
D5
D6
D7
P
stop
RXRDY
FRAME
Stop Bit
Detected at 0
RSTSTA
35.5.2.7 Receiver Digital Filter
The UART embeds a digital filter on the receive line. It is disabled by default and can be enabled by writing a
logical 1 in the FILTER bit of UART_MR. When enabled, the receive line is sampled using the 16x bit clock and a
three-sample filter (majority 2 over 3) determines the value of the line.
35.5.3 Transmitter
35.5.3.1 Transmitter Reset, Enable and Disable
After device reset, the UART transmitter is disabled and must be enabled before being used. The transmitter is
enabled by writing UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to
be written in the Transmit Holding Register (UART_THR) before actually starting the transmission.
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the internal shift register
and/or a character has been written in the UART_THR, the characters are completed before the transmitter is
actually stopped.
The programmer can also put the transmitter in its reset state by writing the UART_CR with the bit RSTTX at 1.
This immediately stops the transmitter, whether or not it is processing characters.
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35.5.3.2 Transmit Format
The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the
format defined in UART_MR and the data stored in the internal shift register. One start bit at level 0, then the 8
data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted
out as shown in the following figure. The field PARE in UART_MR defines whether or not a parity bit is shifted out.
When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
Figure 35-9.
Character Transmission
Example: Parity enabled
Baud Rate
Clock
UTXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
35.5.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in UART_SR. The transmission starts
when the programmer writes in the UART_THR, and after the written character is transferred from UART_THR to
the internal shift register. The TXRDY bit remains high until a second character is written in UART_THR. As soon
as the first character is completed, the last character written in UART_THR is transferred into the internal shift
register and TXRDY rises again, showing that the holding register is empty.
When both the internal shift register and UART_THR are empty, i.e., all the characters written in UART_THR have
been processed, the TXEMPTY bit rises after the last stop bit has been completed.
Figure 35-10. Transmitter Control
UART_THR
Data 0
Data 1
Shift Register
UTXD
Data 0
Data 0
S
Data 1
P
stop
S
Data 1
P
stop
TXRDY
TXEMPTY
Write Data 0
in UART_THR
Write Data 1
in UART_THR
35.5.4 Optical Interface
To use the optical interface circuitry, the PLLA clock must be ready and programmed to generate a frequency
within the range of 4096 up to 8192 kHz. This range allows a modulation by a clock with an adjustable frequency
from 30 up to 60 kHz.
The optical interface is enabled by writing a 1 to the bit OPT_EN in UART_MR (see Section 35.6.2 ”UART Mode
Register”).
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When OPT_EN = 1, the URXD pad is automatically configured in Analog mode and the analog comparator is
enabled (see Figure 35-11).
To match the characteristics of the off-chip optical receiver circuitry, the voltage reference threshold of the
embedded comparator can be adjusted from VDDIO/10 up to VDD/2 by programming the OPT_CMPTH field in
UART_MR.
The NRZ output of the UART transmitter sub-module is modulated with the 30 up to 60 kHz modulation clock prior
to driving the PIO controller.
A logical 0 on the UART transmitter sub-module output generates the said modulated signal (see Figure 35-12)
having a frequency programmable from 30 kHz up to 60 kHz (38 kHz is the default value assuming the PLLA clock
frequency is 8192 kHz). A logical 1 on the UART transmitter sub-module output generates a stuck-at 1 output
signal (no modulation). The idle polarity of the modulated signal is 1 (OPT_MDINV = 0 in UART_MR).
The idle polarity of the modulated signal can be inverted by writing a 1 to the OPT_MDINV bit in UART_MR.
The duty cycle of the modulated signal can be adjusted from 6.25% up to 50% (default value) by steps of 6.25% by
programming the OPT_DUTY field in UART_MR.
Figure 35-11. Optical Interface Block Diagram
uart_irq
pio_irq
Optical Receive Logic
UART
OPT_EN
Interrupt
Control
OPT_CMPTH
vth
OPT_RXINV
1
Receive
peripheral
clock
Power
Management
Controller
URXD
0
Baud Rate
Generator
0
1
Optical Clock
Divider
OPT_EN
OPT_CLKDIV
Optical Duty Cycle
Generator
/8
OPT_DUTY
Optical Modulation
762
UTXD
Transmit
PLLACK
on
Analog
Comparator
SAM4CM Series [DATASHEET]
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OPT_MDINV
OPT_EN
Parallel
Input/
Output
Figure 35-12. Optical Interface Waveforms
UART Transmitter Ouput
UTXD (OPT_EN = 0)
OPT_EN = 1
UTXD (OPT_MDINV = 0)
UTXD (OPT_MDINV = 1)
tperipheral clock * ( 8 * (OPT_CLKDIV + 8) )
OPT_MDINV = 0
OPT_DUTY = 0
OPT_DUTY = 3
OPT_DUTY = 7
The default configuration values of the optical link circuitries allow the 38 kHz modulation, a 50% duty cycle and an
idle polarity allowing a direct drive of an IR LED through a resistor (see Figure 35-13).
Refer to Section 46. ”Electrical Characteristics” for drive capability of the buffer associated with the UTXD output.
In case of direct drive of the IR LED as shown in Figure 35-13, the PIO must be programmed in Multi-driver mode
(open-drain). To do so, the adequate index and values must be programmed into the PIO Multi-driver Enable
Register (PIO_MDER) (status reported on the PIO Multi-driver Status Register (PIO_MDSR)). Refer to Section 32.
”Parallel Input/Output Controller (PIO)” for details.
If an off-chip current amplifier is used to drive the transmitting of the IR LED, the PIO may be programmed in
Default drive mode (non open-drain) for the line index driving the UTXD output, or in Open-drain mode depending
on the type of external circuitry.
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Figure 35-13. Optical Interface Connected to IR Components
VDDIO
VDDIO
UART
PIO
PIO_MDSR [UTXD]
txd
0
0
0
UTXD
Resistor
IR LED
1
0
1
URXD
rxd
PhotoTransistor
35.5.5 Peripheral DMA Controller (PDC)
Both the receiver and the transmitter of the UART are connected to a PDC.
The PDC channels are programmed via registers that are mapped within the UART user interface from the offset
0x100. The status bits are reported in UART_SR and generate an interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in
UART_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of
data in UART_THR.
35.5.6 Test Modes
The UART supports three test modes. These modes of operation are programmed by using the CHMODE field in
UART_MR.
The Automatic echo mode allows a bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to
the UTXD line. The transmitter operates normally, but has no effect on the UTXD line.
The Local loopback mode allows the transmitted characters to be received. UTXD and URXD pins are not used
and the output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no
effect and the UTXD line is held high, as in idle state.
The Remote loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver are
disabled and have no effect. This mode allows a bit-by-bit retransmission.
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Figure 35-14. Test Modes
Automatic Echo
RXD
Receiver
Transmitter
Disabled
TXD
Local Loopback
Disabled
Receiver
RXD
VDD
Disabled
Transmitter
Remote Loopback
TXD
VDD
Disabled
RXD
Receiver
Disabled
Transmitter
TXD
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35.6
Universal Asynchronous Receiver Transmitter (UART) User Interface
Table 35-4.
Register Mapping
Access
Reset
UART_CR
Write-only
–
Mode Register
UART_MR
Read/Write
0x0013_0000
0x0008
Interrupt Enable Register
UART_IER
Write-only
–
0x000C
Interrupt Disable Register
UART_IDR
Write-only
–
0x0010
Interrupt Mask Register
UART_IMR
Read-only
0x0
0x0014
Status Register
UART_SR
Read-only
–
0x0018
Receive Holding Register
UART_RHR
Read-only
0x0
0x001C
Transmit Holding Register
UART_THR
Write-only
–
0x0020
Baud Rate Generator Register
UART_BRGR
Read/Write
0x0
0x0024
Reserved
–
–
–
0x0028–0x003C
Reserved
–
–
–
0x0040–0x00E8
Reserved
–
–
–
0x00EC–0x00FC
Reserved
–
–
–
0x0100–0x0128
Reserved for PDC registers
–
–
–
766
Offset
Register
Name
0x0000
Control Register
0x0004
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35.6.1 UART Control Register
Name:
UART_CR
Address:
0x400E0600 (0), 0x48004000 (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
RSTSTA
7
6
5
4
3
2
1
0
TXDIS
TXEN
RXDIS
RXEN
RSTTX
RSTRX
–
–
• RSTRX: Reset Receiver
0: No effect.
1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0: No effect.
1: The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
• RXEN: Receiver Enable
0: No effect.
1: The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the
receiver is stopped.
• TXEN: Transmitter Enable
0: No effect.
1: The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and
RSTTX is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status
0: No effect.
1: Resets the status bits PARE, FRAME and OVRE in the UART_SR.
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35.6.2 UART Mode Register
Name:
UART_MR
Address:
0x400E0604 (0), 0x48004004 (1)
Access:
Read/Write
31
30
–
29
28
27
OPT_CMPTH
23
22
21
–
–
–
15
14
13
12
–
–
CHMODE
26
–
20
25
19
18
17
16
9
8
OPT_CLKDIV
11
10
–
PAR
7
6
5
4
3
2
1
0
–
–
–
FILTER
–
OPT_MDINV
OPT_RXINV
OPT_EN
• OPT_EN: UART Optical Interface Enable
Value
Name
Description
0
DISABLED
The UART transmitter data is not inverted before modulation.
1
ENABLED
The UART transmitter data is inverted before modulation.
• OPT_RXINV: UART Receive Data Inverted
Value
Name
Description
0
DISABLED
The comparator data output is not inverted before entering UART.
1
ENABLED
The comparator data output is inverted before entering UART.
• OPT_MDINV: UART Modulated Data Inverted
Value
Name
Description
0
DISABLED
The output of the modulator is not inverted.
1
ENABLED
The output of the modulator is inverted.
• FILTER: Receiver Digital Filter
0 (DISABLED): UART does not filter the receive line.
1 (ENABLED): UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
• PAR: Parity Type
Value
Name
Description
0
EVEN
Even Parity
1
ODD
Odd Parity
2
SPACE
Space: parity forced to 0
3
MARK
Mark: parity forced to 1
4
NO
No parity
768
24
OPT_DUTY
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• CHMODE: Channel Mode
Value
Name
Description
0
NORMAL
Normal mode
1
AUTOMATIC
Automatic echo
2
LOCAL_LOOPBACK
Local loopback
3
REMOTE_LOOPBACK
Remote loopback
• OPT_CLKDIV: Optical Link Clock Divider
0 to 31: The optical modulation clock frequency is defined by PLLACK / (8 * (OPT_CLKDIV + 8)).
• OPT_DUTY: Optical Link Modulation Clock Duty Cycle
Value
Name
Description
0
DUTY_50
Modulation clock duty cycle Is 50%.
1
DUTY_43P75
Modulation clock duty cycle Is 43.75%.
2
DUTY_37P5
Modulation clock duty cycle Is 37.5%.
3
DUTY_31P25
Modulation clock duty cycle Is 31.75%.
4
DUTY_25
Modulation clock duty cycle Is 25%.
5
DUTY_18P75
Modulation clock duty cycle Is 18.75%.
6
DUTY_12P5
Modulation clock duty cycle Is 12.5%.
7
DUTY_6P25
Modulation clock duty cycle Is 6.25%.
• OPT_CMPTH: Receive Path Comparator Threshold
Value
Name
Description
0
VDDIO_DIV2
Comparator threshold is VDDIO/2 volts.
1
VDDIO_DIV2P5
Comparator threshold is VDDIO/2.5 volts.
2
VDDIO_DIV3P3
Comparator threshold is VDDIO/3.3 volts.
3
VDDIO_DIV5
Comparator threshold is VDDIO/5 volts.
4
VDDIO_DIV10
Comparator threshold is VDDIO/10 volts.
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35.6.3 UART Interrupt Enable Register
Name:
UART_IER
Address:
0x400E0608 (0), 0x48004008 (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt
770
SAM4CM Series [DATASHEET]
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35.6.4 UART Interrupt Disable Register
Name:
UART_IDR
Address:
0x400E060C (0), 0x4800400C (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt
SAM4CM Series [DATASHEET]
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771
35.6.5 UART Interrupt Mask Register
Name:
UART_IMR
Address:
0x400E0610 (0), 0x48004010 (1)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt
772
SAM4CM Series [DATASHEET]
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35.6.6 UART Status Register
Name:
UART_SR
Address:
0x400E0614 (0), 0x48004014 (1)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
RXBUFF
TXBUFE
–
TXEMPTY
–
7
6
5
4
3
2
1
0
PARE
FRAME
OVRE
ENDTX
ENDRX
–
TXRDY
RXRDY
• RXRDY: Receiver Ready
0: No character has been received since the last read of the UART_RHR, or the receiver is disabled.
1: At least one complete character has been received, transferred to UART_RHR and not yet read.
• TXRDY: Transmitter Ready
0: A character has been written to UART_THR and not yet transferred to the internal shift register, or the transmitter is
disabled.
1: There is no character written to UART_THR not yet transferred to the internal shift register.
• ENDRX: End of Receiver Transfer
0: The end of transfer signal from the receiver PDC channel is inactive.
1: The end of transfer signal from the receiver PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The end of transfer signal from the transmitter PDC channel is inactive.
1: The end of transfer signal from the transmitter PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0: No framing error has occurred since the last RSTSTA.
1: At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error
0: No parity error has occurred since the last RSTSTA.
1: At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0: There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1: There are no characters in UART_THR and there are no characters being processed by the transmitter.
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773
• TXBUFE: Transmission Buffer Empty
0: The buffer empty signal from the transmitter PDC channel is inactive.
1: The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full
0: The buffer full signal from the receiver PDC channel is inactive.
1: The buffer full signal from the receiver PDC channel is active.
774
SAM4CM Series [DATASHEET]
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35.6.7 UART Receiver Holding Register
Name:
UART_RHR
Address:
0x400E0618 (0), 0x48004018 (1)
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
RXCHR
• RXCHR: Received Character
Last received character if RXRDY is set.
SAM4CM Series [DATASHEET]
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775
35.6.8 UART Transmit Holding Register
Name:
UART_THR
Address:
0x400E061C (0), 0x4800401C (1)
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
TXCHR
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
776
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
35.6.9 UART Baud Rate Generator Register
Name:
UART_BRGR
Address:
0x400E0620 (0), 0x48004020 (1)
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
3
2
1
0
CD
7
6
5
4
CD
• CD: Clock Divisor
0: Baud rate clock is disabled
1 to 65,535:
f peripheral clock
CD = ---------------------------------16 × Baud Rate
SAM4CM Series [DATASHEET]
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777
36.
Universal Synchronous Asynchronous Receiver Transceiver (USART)
36.1
Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of
stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun
error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard
facilitates communications with slow remote devices. Multidrop communications are also supported through
address bit handling in reception and transmission.
The USART features three test modes: Remote loopback, Local loopback and Automatic echo.
The USART supports specific operating modes providing interfaces on RS485, and SPI buses, with ISO7816 T =
0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band
flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the
transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the
processor.
36.2
Embedded Characteristics
Programmable Baud Rate Generator
5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
̶
1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
̶
Parity Generation and Error Detection
̶
Framing Error Detection, Overrun Error Detection
̶
Digital Filter on Receive Line
̶
MSB- or LSB-first
̶
Optional Break Generation and Detection
̶
By 8 or by 16 Over-sampling Receiver Frequency
̶
Optional Hardware Handshaking RTS-CTS
̶
Receiver Time-out and Transmitter Timeguard
̶
Optional Multidrop Mode with Address Generation and Detection
RS485 with Driver Control Signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
IrDA Modulation and Demodulation
̶
̶
NACK Handling, Error Counter with Repetition and Iteration Limit
Communication at up to 115.2 kbit/s
SPI Mode
̶
Master or Slave
̶
Serial Clock Programmable Phase and Polarity
̶
SPI Serial Clock (SCK) Frequency up to fperipheral clock/6
Test Modes
Supports Connection of:
̶
̶
Remote Loopback, Local Loopback, Automatic Echo
778
Two Peripheral DMA Controller Channels (PDC)
SAM4CM Series [DATASHEET]
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36.3
Offers Buffer Transfer without Processor Intervention
Register Write Protection
Block Diagram
Figure 36-1.
USART Block Diagram
Interrupt
Controller
USART Interrupt
PIO
Controller
USART
RXD
Receiver
Channel
RTS
(Peripheral)
DMA Controller
TXD
Channel
Transmitter
CTS
Bus clock
SCK
Baud Rate
Generator
Bridge
APB
User
Interface
Peripheral clock
PMC
36.4
Peripheral clock/DIV
I/O Lines Description
Table 36-1.
I/O Line Description
Name
Description
Type
Active Level
SCK
Serial Clock
I/O
—
I/O
—
Input
—
Input
Low
Output
Low
Transmit Serial Data
TXD
or Master Out Slave In (MOSI) in SPI master mode
or Master In Slave Out (MISO) in SPI slave mode
Receive Serial Data
RXD
or Master In Slave Out (MISO) in SPI master mode
or Master Out Slave In (MOSI) in SPI slave mode
CTS
RTS
Clear to Send
or Slave Select (NSS) in SPI slave mode
Request to Send
or Slave Select (NSS) in SPI master mode
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779
36.5
Product Dependencies
36.5.1 I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART
are not used by the application, they can be used for other purposes by the PIO Controller.
Table 36-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
USART0
CTS0
PA20
A
USART0
RTS0
PA19
A
USART0
RXD0
PB16
A
USART0
SCK0
PB18
A
USART0
TXD0
PB17
A
USART1
CTS1
PA18
A
USART1
RTS1
PA17
A
USART1
RXD1
PA11
A
USART1
SCK1
PA16
A
USART1
TXD1
PA12
A
USART2
CTS2
PA15
A
USART2
RTS2
PA14
A
USART2
RXD2
PA9
A
USART2
SCK2
PA13
A
USART2
TXD2
PA10
A
USART3
CTS3
PA1
A
USART3
RTS3
PA0
A
USART3
RXD3
PA3
A
USART3
SCK3
PA2
A
USART3
TXD3
PA4
A
USART4
CTS4
PA26
A
USART4
RTS4
PB22
A
USART4
RXD4
PB19
A
USART4
SCK4
PB21
A
USART4
TXD4
PB20
A
36.5.2 Power Management
The USART is not continuously clocked. The programmer must first enable the USART clock in the Power
Management Controller (PMC) before using the USART. However, if the application does not require USART
operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will
resume its operations where it left off.
780
SAM4CM Series [DATASHEET]
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36.5.3 Interrupt Sources
The USART interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the USART
interrupt requires the Interrupt Controller to be programmed first.
Table 36-3.
36.6
Peripheral IDs
Instance
ID
USART0
14
USART1
15
USART2
16
USART3
17
USART4
18
Functional Description
36.6.1 Baud Rate Generator
The baud rate generator provides the bit period clock, also named the baud rate clock, to both the receiver and the
transmitter.
The baud rate generator clock source is selected by configuring the USCLKS field in the USART Mode Register
(US_MR) to one of the following:
The peripheral clock
A division of the peripheral clock, where the divider is product-dependent, but generally set to 8
The external clock, available on the SCK pin
The baud rate generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator register (US_BRGR). If a 0 is written to CD, the baud rate generator does not generate any clock. If a 1
is written to CD, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin
must be longer than a peripheral clock period. The frequency of the signal provided on SCK must be at least 3
times lower than the frequency provided on the peripheral clock in USART mode (field USART_MODE differs from
0xE or 0xF), or 6 times lower in SPI mode (field USART_MODE equals 0xE or 0xF).
Figure 36-2.
Baud Rate Generator
USCLKS
Peripheral clock
Peripheral clock/DIV
Reserved
SCK
CD
SCK
(CLKO = 1)
CD
0
1
2
16-bit Counter
FIDI
>1
3
1
(CLKO = 0)
0
0
0
SYNC
OVER
Sampling
Divider
0
Baud Rate
Clock
1
1
SYNC
USCLKS = 3
Sampling
Clock
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781
36.6.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in Asynchronous mode, the selected clock is first divided by CD, which is
field programmed in the US_BRGR. The resulting clock is provided to the receiver as a sampling clock and then
divided by 16 or 8, depending on how the OVER bit in the US_MR is programmed.
If OVER is set, the receiver sampling is eight times higher than the baud rate clock. If OVER is cleared, the
sampling is performed at 16 times the baud rate clock.
The baud rate is calculated as per the following formula:
SelectedClock
Baudrate = -------------------------------------------( 8 ( 2 – Over )CD )
This gives a maximum baud rate of peripheral clock divided by 8, assuming that the peripheral clock is the highest
possible clock and that the OVER bit is set.
Baud Rate Calculation Example
Table 36-4 shows calculations of CD to obtain a baud rate at 38,400 bit/s for different source clock frequencies.
This table also shows the actual resulting baud rate and the error.
Table 36-4.
Baud Rate Example (OVER = 0)
Source Clock
(MHz)
Expected Baud Rate
(bit/s)
Calculation Result
CD
Actual Baud Rate
(bit/s)
Error
3,686,400
38,400
6.00
6
38,400.00
0.00%
4,915,200
38,400
8.00
8
38,400.00
0.00%
5,000,000
38,400
8.14
8
39,062.50
1.70%
7,372,800
38,400
12.00
12
38,400.00
0.00%
8,000,000
38,400
13.02
13
38,461.54
0.16%
12,000,000
38,400
19.53
20
37,500.00
2.40%
12,288,000
38,400
20.00
20
38,400.00
0.00%
14,318,180
38,400
23.30
23
38,908.10
1.31%
14,745,600
38,400
24.00
24
38,400.00
0.00%
18,432,000
38,400
30.00
30
38,400.00
0.00%
24,000,000
38,400
39.06
39
38,461.54
0.16%
24,576,000
38,400
40.00
40
38,400.00
0.00%
25,000,000
38,400
40.69
40
38,109.76
0.76%
32,000,000
38,400
52.08
52
38,461.54
0.16%
32,768,000
38,400
53.33
53
38,641.51
0.63%
33,000,000
38,400
53.71
54
38,194.44
0.54%
40,000,000
38,400
65.10
65
38,461.54
0.16%
50,000,000
38,400
81.38
81
38,580.25
0.47%
The baud rate is calculated with the following formula:
BaudRate = f peripheral clock ⁄ CD × 16
782
SAM4CM Series [DATASHEET]
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The baud rate error is calculated with the following formula. It is not recommended to work with an error higher
than 5%.
ExpectedBaudRate
Error = 1 – ---------------------------------------------------
ActualBaudRate
36.6.1.2 Fractional Baud Rate in Asynchronous Mode
The baud rate generator is subject to the following limitation: the output frequency changes only by integer
multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that
has a high resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the
reference source clock. This fractional part is programmed with the FP field in the US_BRGR. If FP is not 0, the
fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when
using USART normal mode. The fractional baud rate is calculated using the following formula:
SelectedClock
Baudrate = --------------------------------------------------------------- 8 ( 2 – Over ) CD + FP
-------
8
The modified architecture is presented in the following Figure 36-3.
Figure 36-3.
Fractional Baud Rate Generator
FP
USCLKS
CD
Modulus
Control
FP
MCK
MCK/DIV
Reserved
SCK
(CLKO = 1)
CD
0
1
2
16-bit Counter
Glitch-free
Logic
3
1
SCK
(CLKO = 0)
0
FIDI
>1
0
0
SYNC
OVER
Sampling
Divider
0
Baud Rate
Clock
1
1
SYNC
USCLKS = 3
Sampling
Clock
36.6.1.3 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in Synchronous mode, the selected clock is simply divided by the field CD
in the US_BRGR.
SelectedClock
BaudRate = -------------------------------------CD
In Synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on
the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock
frequency must be at least 3 times lower than the system clock. In Synchronous mode master (USCLKS = 0 or 1,
CLKO set to 1), the receive part limits the SCK maximum frequency to fperipheral clock/3 in USART mode, or fperipheral
clock/6 in SPI mode.
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783
When either the external clock SCK or the internal clock divided (peripheral clock/DIV) is selected, the value
programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. When the
peripheral clock is selected, the baud rate generator ensures a 50:50 duty cycle on the SCK pin, even if the value
programmed in CD is odd.
36.6.1.4 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
Di
B = ------ × f
Fi
where:
B is the bit rate
Di is the bit-rate adjustment factor
Fi is the clock frequency division factor
f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 36-5.
Table 36-5.
Binary and Decimal Values for Di
DI field
0001
0010
0011
0100
0101
0110
1000
1001
1
2
4
8
16
32
12
20
Di (decimal)
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 36-6.
Table 36-6.
Binary and Decimal Values for Fi
FI field
0000
0001
0010
0011
0100
0101
0110
1001
1010
1011
1100
1101
Fi (decimal)
372
372
558
744
1116
1488
1860
512
768
1024
1536
2048
Table 36-7 shows the resulting Fi/Di ratio, which is the ratio between the ISO7816 clock and the baud rate clock.
Table 36-7.
Possible Values for the Fi/Di Ratio
Fi/Di
372
558
744
1116
1488
1806
512
768
1024
1536
2048
1
372
558
744
1116
1488
1860
512
768
1024
1536
2048
2
186
279
372
558
744
930
256
384
512
768
1024
4
93
139.5
186
279
372
465
128
192
256
384
512
8
46.5
69.75
93
139.5
186
232.5
64
96
128
192
256
16
23.25
34.87
46.5
69.75
93
116.2
32
48
64
96
128
32
11.62
17.43
23.25
34.87
46.5
58.13
16
24
32
48
64
12
31
46.5
62
93
124
155
42.66
64
85.33
128
170.6
20
18.6
27.9
37.2
55.8
74.4
93
25.6
38.4
51.2
76.8
102.4
If the USART is configured in ISO7816 mode, the clock selected by the USCLKS field in US_MR is first divided by
the value programmed in the field CD in the US_BRGR. The resulting clock can be provided to the SCK pin to feed
the smart card clock inputs. This means that the CLKO bit can be set in US_MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register
(US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 mode.
The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a
value as close as possible to the expected value.
784
SAM4CM Series [DATASHEET]
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The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the
ISO7816 clock and the bit rate (Fi = 372, Di = 1).
Figure 36-4 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816
clock.
Figure 36-4.
Elementary Time Unit (ETU)
FI_DI_RATIO
ISO7816 Clock Cycles
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
1 ETU
36.6.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control
register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the US_CR. However,
the transmitter registers can be programmed before being enabled.
The receiver and the transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in the US_CR. The software resets clear the status flag and
reset internal state machines but the user interface configuration registers hold the value configured prior to
software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately
stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively
in the US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception
of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the
USART waits the end of transmission of both the current character and character being stored in the Transmit
Holding register (US_THR). If a timeguard is programmed, it is handled normally.
36.6.3 Synchronous and Asynchronous Modes
36.6.3.1 Transmitter Operations
The transmitter performs the same in both Synchronous and Asynchronous operating modes (SYNC = 0 or SYNC
= 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on
the TXD pin at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in US_MR. Nine bits are selected by
setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The
even, odd, space, marked or none parity bit can be configured. The MSBF field in the US_MR configures which
data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent
first. The number of stop bits is selected by the NBSTOP field in the US_MR. The 1.5 stop bit is supported in
Asynchronous mode only.
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Figure 36-5.
Character Transmit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
TXD
D0
Start
Bit
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
The characters are sent by writing in the Transmit Holding register (US_THR). The transmitter reports two status
bits in the Channel Status register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty
and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current
character processing is completed, the last character written in US_THR is transferred into the Shift register of the
transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
Figure 36-6.
Transmitter Status
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
36.6.3.2 Manchester Encoder
When the Manchester encoder is in use, characters transmitted through the USART are encoded based on
biphase Manchester II format. To enable this mode, set the MAN bit in the US_MR to 1. Depending on polarity
configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a
transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal
(2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell.
An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10,
assuming the default polarity of the encoder. Figure 36-7 illustrates this coding scheme.
Figure 36-7.
NRZ to Manchester Encoding
NRZ
encoded
data
1
0
1
1
Manchester
encoded Txd
data
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0
0
0
1
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start
frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a
predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the
preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following
sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register,
the field TX_PL is used to configure the preamble length. Figure 36-8 illustrates and defines the valid patterns. To
improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If
the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is
encoded with a one-to-zero transition. If the TX_MPOL field is set to 1, a logic one is encoded with a one-to-zero
transition and a logic zero is encoded with a zero-to-one transition.
Figure 36-8.
Preamble Patterns, Default Polarity Assumed
Manchester
encoded
data
Txd
SFD
DATA
SFD
DATA
SFD
DATA
SFD
DATA
8-bit width "ALL_ONE" Preamble
Manchester
encoded
data
Txd
8-bit width "ALL_ZERO" Preamble
Manchester
encoded
data
Txd
8-bit width "ZERO_ONE" Preamble
Manchester
encoded
data
Txd
8-bit width "ONE_ZERO" Preamble
A start frame delimiter is to be configured using the ONEBIT bit in the US_MR. It consists of a user-defined pattern
that indicates the beginning of a valid data. Figure 36-9 illustrates these patterns. If the start frame delimiter, also
known as the start bit, is one bit, (ONEBIT = 1), a logic zero is Manchester encoded and indicates that a new
character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to
as sync (ONE BIT to 0), a sequence of three bit times is sent serially on the line to indicate the start of a new
character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of
the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command
sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half
bit times. If the MODSYNC bit in the US_MR is set to 1, the next character is a command. If it is set to 0, the next
character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a
modified character located in memory. To enable this mode, VAR_SYNC bit in US_MR must be set to 1. In this
case, the MODSYNC bit in the US_MR is bypassed and the sync configuration is held in the TXSYNH in the
US_THR. The USART character format is modified and includes sync information.
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Figure 36-9.
Start Frame Delimiter
Preamble Length
is set to 0
SFD
Manchester
encoded
data
DATA
Txd
One bit start frame delimiter
SFD
Manchester
encoded
data
DATA
Txd
SFD
Manchester
encoded
data
Command Sync
start frame delimiter
DATA
Txd
Data Sync
start frame delimiter
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger
clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is
one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken.
If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened
by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current
period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are
automatically taken.
Figure 36-10. Bit Resynchronization
Oversampling
16x Clock
RXD
Sampling
point
Expected edge
Synchro.
Error
Synchro.
Jump
Tolerance
Sync
Jump
Synchro.
Error
36.6.3.3 Asynchronous Receiver
If the USART is programmed in Asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD
input line. The oversampling is either 16 or 8 times the baud rate clock, depending on the OVER bit in the US_MR.
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected
and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16 (OVER = 0), a start is detected at the eighth sample to 0. Data bits, parity bit and stop bit
are assumed to have a duration corresponding to 16 oversampling clock cycles. If the oversampling is 8 (OVER =
1), a start bit is detected at the fourth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration
corresponding to 8 oversampling clock cycles.
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The number of data bits, first bit sent and Parity mode are selected by the same fields and bits as the transmitter,
i.e., respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop
bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that
resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is
sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when
the transmitter is operating with one stop bit.
Figure 36-11 and Figure 36-12 illustrate start detection and character reception when USART operates in
Asynchronous mode.
Figure 36-11. Asynchronous Start Detection
Baud Rate
Clock
Sampling
Clock (x16)
RXD
Sampling
1
2
3
4
5
6
7
8
1
2
3
4
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
D0
Sampling
Start
Detection
RXD
Sampling
1
2
3
4
5
6
7
0 1
Start
Rejection
Figure 36-12. Asynchronous Character Reception
Example: 8-bit, Parity Enabled
Baud Rate
Clock
RXD
Start
Detection
16
16
16
16
16
16
16
16
16
16
samples samples samples samples samples samples samples samples samples samples
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
36.6.3.4 Manchester Decoder
When the MAN bit in the US_MR is set to 1, the Manchester decoder is enabled. The decoder performs both
preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter
side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no
preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with
RX_MPOL bit in US_MAN register. Depending on the desired application the preamble pattern matching is to be
defined via the RX_PP field in US_MAN. See Figure 36-8 for available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT
field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set
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to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on
incoming stream. If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 3613. The sample pulse rejection mechanism applies.
Figure 36-13. Asynchronous Start Bit Detection
Sampling
Clock
(16 x)
Manchester
encoded
data
Txd
Start
Detection
1
2
3
4
The receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and
then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding
with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the
receiver resynchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three
quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded
into NRZ data and passed to USART for processing. Figure 36-14 illustrates Manchester pattern mismatch. When
incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A
code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in the US_CSR is raised. It is
cleared by writing a 1 to the RSTSTA in the US_CR. See Figure 36-15 for an example of Manchester error
detection during data phase.
Figure 36-14. Preamble Pattern Mismatch
Preamble Mismatch
Manchester coding error
Manchester
encoded
data
Preamble Mismatch
invalid pattern
SFD
Txd
DATA
Preamble Length is set to 8
Figure 36-15. Manchester Error Flag
Preamble Length
is set to 4
Elementary character bit time
SFD
Manchester
encoded
data
Txd
Entering USART character area
sampling points
Preamble subpacket
and Start Frame Delimiter
were successfully
decoded
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Manchester
Coding Error
detected
When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are
supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR and the
RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the
received character is a data. This mechanism alleviates and simplifies the direct memory access as the character
contains its own sync field in the same register.
As the decoder is setup to be used in Unipolar mode, the first bit of the frame has to be a zero-to-one transition.
36.6.3.5 Radio Interface: Manchester Encoded USART Application
This section describes low data rate RF transmission systems and their integration with a Manchester encoded
USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation
schemes.
The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the
configuration in Figure 36-16.
Figure 36-16. Manchester Encoded Characters RF Transmission
Fup frequency Carrier
ASK/FSK
Upstream Receiver
Upstream
Emitter
LNA
VCO
RF filter
Demod
Serial
Configuration
Interface
control
Fdown frequency Carrier
bi-dir
line
Manchester
decoder
USART
Receiver
Manchester
encoder
USART
Emitter
ASK/FSK
downstream transmitter
Downstream
Receiver
PA
RF filter
Mod
VCO
control
The USART peripheral is configured as a Manchester encoder/decoder. Looking at the downstream
communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include
a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish
between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See
Figure 36-17 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the
power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic
zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used
to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if
the data sent is a 0. See Figure 36-18.
From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation
examining demodulated data stream. If a valid pattern is detected, the receiver switches to Receiving mode. The
demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred
to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be
defined in accordance with the RF IC configuration.
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Figure 36-17. ASK Modulator Output
1
0
0
1
0
0
1
NRZ stream
Manchester
encoded
data
default polarity
unipolar output
Txd
ASK Modulator
Output
Uptstream Frequency F0
Figure 36-18. FSK Modulator Output
1
NRZ stream
Manchester
encoded
data
default polarity
unipolar output
Txd
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
36.6.3.6 Synchronous Receiver
In Synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate
clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled
and the receiver waits for the next start bit. Synchronous mode operations provide a high-speed transfer capability.
Configuration fields and bits are the same as in Asynchronous mode.
Figure 36-19 illustrates a character reception in Synchronous mode.
Figure 36-19. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
RXD
Sampling
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop Bit
Parity Bit
36.6.3.7 Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the
RXRDY bit in US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is
set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by
writing a 1 to the RSTSTA (Reset Status) bit in the US_CR.
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Figure 36-20. Receiver Status
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop Start
D0
Bit Bit Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RSTSTA = 1
Write
US_CR
Read
US_RHR
RXRDY
OVRE
36.6.3.8 Parity
The USART supports five Parity modes that are selected by writing to the PAR field in the US_MR. The PAR field
also enables the Multidrop mode, see Section 36.6.3.9 ”Multidrop Mode”. Even and odd parity bit generation and
error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the
character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is
selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit
is even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity
generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error
if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit
to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is
disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 36-8 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the
configuration of the USART. Because there are two bits set to 1 in the character value, the parity bit is set to 1
when the parity is odd, or configured to 0 when the parity is even.
Table 36-8.
Parity Bit Examples
Character
Hexadecimal
Binary
Parity Bit
Parity Mode
A
0x41
0100 0001
1
Odd
A
0x41
0100 0001
0
Even
A
0x41
0100 0001
1
Mark
A
0x41
0100 0001
0
Space
A
0x41
0100 0001
None
None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the US_CSR. The PARE bit can be
cleared by writing a 1 to the RSTSTA bit the US_CR. Figure 36-21 illustrates the parity bit status setting and
clearing.
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Figure 36-21. Parity Error
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Bad Stop
Parity Bit
Bit
RSTSTA = 1
Write
US_CR
PARE
Parity Error
Detect
Time
Flags
Report
Time
RXRDY
36.6.3.9 Multidrop Mode
If the value 0x6 or 0x07 is written to the PAR field in the US_MR, the USART runs in Multidrop mode. This mode
differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and
addresses are transmitted with the parity bit at 1.
If the USART is configured in Multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high
and the transmitter is able to send a character with the parity bit high when a 1 is written to the SENTA bit in the
US_CR.
To handle parity error, the PARE bit is cleared when a 1 is written to the RSTSTA bit in the US_CR.
The transmitter sends an address byte (parity bit set) when SENDA is written to in the US_CR. In this case, the
next byte written to the US_THR is transmitted as an address. Any character written in the US_THR without having
written the command SENDA is transmitted normally with the parity at 0.
36.6.3.10 Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This
idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard register (US_TTGR).
When this field is written to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD
after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop
bits.
As illustrated in Figure 36-22, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of
a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0 during the
timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard
transmission is completed as the timeguard is part of the current character being transmitted.
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Figure 36-22. Timeguard Operations
TG = 4
TG = 4
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
Write
US_THR
TXRDY
TXEMPTY
Table 36-9 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the
function of the baud rate.
Table 36-9.
Maximum Timeguard Length Depending on Baud Rate
Baud Rate (bit/s)
Bit Time (µs)
Timeguard (ms)
1,200
833
212.50
9,600
104
26.56
14,400
69.4
17.71
19,200
52.1
13.28
28,800
34.7
8.85
38,400
26
6.63
56,000
17.9
4.55
57,600
17.4
4.43
115,200
8.7
2.21
36.6.3.11 Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition
on the RXD line. When a time-out is detected, the bit TIMEOUT in the US_CSR rises and can generate an
interrupt, thus indicating to the driver an end of frame.
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of
the Receiver Time-out register (US_RTOR). If the TO field is written to 0, the Receiver Time-out is disabled and no
time-out is detected. The TIMEOUT bit in the US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter
with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new
character is received. If the counter reaches 0, the TIMEOUT bit in US_CSR rises. Then, the user can either:
Stop the counter clock until a new character is received. This is performed by writing a 1 to the STTTO (Start
Time-out) bit in the US_CR. In this case, the idle state on RXD before a new character is received will not
provide a time-out. This prevents having to handle an interrupt before a character is received and allows
waiting for the next idle state on RXD after a frame is received.
Obtain an interrupt while no character is received. This is performed by writing a 1 to the RETTO (Reload
and Start Time-out) bit in the US_CR. If RETTO is performed, the counter starts counting down immediately
from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for
example when no key is pressed on a keyboard.
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If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before
the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a
wait of the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation
of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
Figure 36-23 shows the block diagram of the Receiver Time-out feature.
Figure 36-23. Receiver Time-out Block Diagram
TO
Baud Rate
Clock
1
D
Clock
Q
16-bit Time-out
Counter
16-bit
Value
=
STTTO
Character
Received
RETTO
Load
Clear
TIMEOUT
0
Table 36-10 gives the maximum time-out period for some standard baud rates.
Table 36-10.
Maximum Time-out Period
Baud Rate (bit/s)
Bit Time (µs)
Time-out (ms)
600
1,667
109,225
1,200
833
54,613
2,400
417
27,306
4,800
208
13,653
9,600
104
6,827
14,400
69
4,551
19,200
52
3,413
28,800
35
2,276
38,400
26
1,704
56,000
18
1,170
57,600
17
1,138
200,000
5
328
36.6.3.12 Framing Error
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received
character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
A framing error is reported on the FRAME bit of US_CSR. The FRAME bit is asserted in the middle of the stop bit
as soon as the framing error is detected. It is cleared by writing a 1 to the RSTSTA bit in the US_CR.
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Figure 36-24. Framing Error Status
Baud Rate
Clock
RXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RSTSTA = 1
Write
US_CR
FRAME
RXRDY
36.6.3.13 Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the
TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity
and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user
requests the break condition to be removed.
A break is transmitted by writing a 1 to the STTBRK bit in the US_CR. This can be performed at any time, either
while the transmitter is empty (no character in either the Shift register or in US_THR) or when a character is being
transmitted. If a break is requested while a character is being shifted out, the character is first completed before the
TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is
completed.
The break condition is removed by writing a 1 to the STPBRK bit in the US_CR. If the STPBRK is requested before
the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter
ensures that the break condition completes.
The transmitter considers the break as though it is a character, i.e., the STTBRK and STPBRK commands are
processed only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and
TXEMPTY bits as if a character is processed.
Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK
commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding
register while a break is pending, but not started, is ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the
transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character.
If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 36-25 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the
TXD line.
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Figure 36-25. Break Transmission
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
STTBRK = 1
Break Transmission
End of Break
STPBRK = 1
Write
US_CR
TXRDY
TXEMPTY
36.6.3.14 Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by
writing a 1 to the RSTSTA bit in the US_CR.
An end of receive break is detected by a high level for at least 2/16 of a bit period in Asynchronous operating mode
or one sample at high level in Synchronous operating mode. The end of break detection also asserts the RXBRK
bit.
36.6.3.15 Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to
connect with the remote device, as shown in Figure 36-26.
Figure 36-26. Connection with a Remote Device for Hardware Handshaking
USART
Remote
Device
TXD
RXD
RXD
TXD
CTS
RTS
RTS
CTS
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in
US_MR to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard
Synchronous or Asynchronous mode, except that the receiver drives the RTS pin as described below and the level
on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the
PDC channel for reception. The transmitter can handle hardware handshaking in any case.
Figure 36-27 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if
the receiver is disabled or if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high.
Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the
receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new
buffer in the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low.
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Figure 36-27. Receiver Behavior when Operating with Hardware Handshaking
RXD
RXEN = 1
RXDIS = 1
Write
US_CR
RTS
RXBUFF
Figure 36-28 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the
transmitter. If a character is being processed, the transmitter is disabled only after the completion of the current
character and transmission of the next character happens as soon as the pin CTS falls.
Figure 36-28. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
36.6.4 ISO7816 Mode
The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and
Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined
by the ISO7816 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in US_MR to the value 0x4
for protocol T = 0 and to the value 0x5 for protocol T = 1.
36.6.4.1 ISO7816 Mode Overview
The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a
division of the clock provided to the remote device (see Section 36-2 ”Baud Rate Generator”).
The USART connects to a smart card as shown in Figure 36-29. The TXD line becomes bidirectional and the baud
rate generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains
driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input
of the receiver. The USART is considered as the master of the communication as it generates the clock.
Figure 36-29. Connection of a Smart Card to the USART
USART
SCK
TXD
CLK
I/O
Smart
Card
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8
data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and
CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in
normal or inverse mode. Refer to Section 36.7.3 ”USART Mode Register” and “PAR: Parity Type”.
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The USART cannot operate concurrently in both Receiver and Transmitter modes as the communication is
unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the
receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816
mode may lead to unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted
on the I/O line at their negative value.
36.6.4.2 Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which
lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with
the transmission of the next character, as shown in Figure 36-30.
If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 3631. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as
the guard time length is the same and is added to the error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive
Holding register (US_RHR). It appropriately sets the PARE bit in the Status register (US_SR) so that the software
can handle the error.
Figure 36-30. T = 0 Protocol without Parity Error
Baud Rate
Clock
RXD
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Guard Guard Next
Bit Time 1 Time 2 Start
Bit
Figure 36-31. T = 0 Protocol with Parity Error
Baud Rate
Clock
Error
I/O
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Guard
Bit Time 1
Guard Start
Time 2 Bit
D0
D1
Repetition
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER)
register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the
NB_ERRORS field.
Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in US_MR. If
INACK is to 1, no error signal is driven on the I/O line even if a parity bit is detected.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding register, as if no error
occurred and the RXRDY bit does rise.
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Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before
moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the US_MR at a value
higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in
MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION and the last repeated character is not
acknowledged, the ITER bit is set in US_CSR. If the repetition of the character is acknowledged by the receiver,
the repetitions are stopped and the iteration counter is cleared.
The ITER bit in US_CSR can be cleared by writing a 1 to the RSTIT bit in the US_CR.
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed
by setting the bit DSNACK in the US_MR. The maximum number of NACKs transmitted is programmed in the
MAX_ITERATION field. As soon as MAX_ITERATION is reached, no error signal is driven on the I/O line and the
ITER bit in the US_CSR is set.
36.6.4.3 Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one
stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the
PARE bit in the US_CSR.
36.6.5 IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the
modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure
36-32. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data
transfer speeds ranging from 2.4 kbit/s to 115.2 kbit/s.
The IrDA mode is enabled by setting the USART_MODE field in US_MR to the value 0x8. The IrDA Filter register
(US_IF) is used to configure the demodulator filter. The USART transmitter and receiver operate in a normal
Asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are
activated.
Figure 36-32. Connection to IrDA Transceivers
USART
IrDA
Transceivers
Receiver
Demodulator
Transmitter
Modulator
RXD
RX
TX
TXD
The receiver and the transmitter must be enabled or disabled depending on the direction of the transmission to be
managed.
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To receive IrDA signals, the following needs to be done:
Disable TX and Enable RX
Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pullup (better for power consumption).
Receive data
36.6.5.1 IrDA Modulation
For baud rates up to and including 115.2 kbit/s, the RZI modulation scheme is used. “0” is represented by a light
pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 36-11.
Table 36-11.
IrDA Pulse Duration
Baud Rate
Pulse Duration (3/16)
2.4 kbit/s
78.13 µs
9.6 kbit/s
19.53 µs
19.2 kbit/s
9.77 µs
38.4 kbit/s
4.88 µs
57.6 kbit/s
3.26 µs
115.2 kbit/s
1.63 µs
Figure 36-33 shows an example of character transmission.
Figure 36-33. IrDA Modulation
Start
Bit
Transmitter
Output
0
Stop
Bit
Data Bits
0
1
1
0
0
1
1
0
1
TXD
Bit Period
3/16 Bit Period
36.6.5.2 IrDA Baud Rate
Table 36-12 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on
the maximum acceptable error of ±1.87% must be met.
Table 36-12.
IrDA Baud Rate Error
Peripheral Clock
802
Baud Rate (bit/s)
CD
Baud Rate Error
Pulse Time (µs)
3,686,400
115,200
2
0.00%
1.63
20,000,000
115,200
11
1.38%
1.63
32,768,000
115,200
18
1.25%
1.63
40,000,000
115,200
22
1.38%
1.63
3,686,400
57,600
4
0.00%
3.26
20,000,000
57,600
22
1.38%
3.26
32,768,000
57,600
36
1.25%
3.26
40,000,000
57,600
43
0.93%
3.26
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Table 36-12.
IrDA Baud Rate Error (Continued)
Peripheral Clock
Baud Rate (bit/s)
CD
Baud Rate Error
Pulse Time (µs)
3,686,400
38,400
6
0.00%
4.88
20,000,000
38,400
33
1.38%
4.88
32,768,000
38,400
53
0.63%
4.88
40,000,000
38,400
65
0.16%
4.88
3,686,400
19,200
12
0.00%
9.77
20,000,000
19,200
65
0.16%
9.77
32,768,000
19,200
107
0.31%
9.77
40,000,000
19,200
130
0.16%
9.77
3,686,400
9,600
24
0.00%
19.53
20,000,000
9,600
130
0.16%
19.53
32,768,000
9,600
213
0.16%
19.53
40,000,000
9,600
260
0.16%
19.53
3,686,400
2,400
96
0.00%
78.13
20,000,000
2,400
521
0.03%
78.13
32,768,000
2,400
853
0.04%
78.13
36.6.5.3 IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the
value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting
down at the peripheral clock speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded
with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during
one bit time.
Figure 36-34 illustrates the operations of the IrDA demodulator.
Figure 36-34. IrDA Demodulator Operations
MCK
RXD
Counter
Value
6
Receiver
Input
5
4 3
Pulse
Rejected
2
6
6
5
4
3
2
1
0
Pulse
Accepted
The programmed value in the US_IF register must always meet the following criteria:
tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to
a value higher than 0 in order to make sure IrDA communications operate correctly.
36.6.6 RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART
behaves as though in Asynchronous or Synchronous mode and configuration of all the parameters is possible.
The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is
controlled by the TXEMPTY bit. A typical connection of the USART to an RS485 bus is shown in Figure 36-35.
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Figure 36-35. Typical Connection to a RS485 Bus
USART
RXD
Differential
Bus
TXD
RTS
The USART is set in RS485 mode by writing the value 0x1 to the USART_MODE field in US_MR.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is
programmed so that the line can remain driven after the last character completion. Figure 36-36 gives an example
of the RTS waveform during a character transmission when the timeguard is enabled.
Figure 36-36. Example of RTS Drive with Timeguard
TG = 4
1
Baud Rate
Clock
TXD
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity Stop
Bit Bit
RTS
Write
US_THR
TXRDY
TXEMPTY
36.6.7 SPI Mode
The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with
external devices in Master or Slave mode. It also enables communication between processors if an external
processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one
master may simultaneously shift data into multiple slaves. (Multiple master protocol is the opposite of single
master protocol, where one CPU is always the master while all of the others are always slaves.) However, only
one slave may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can
address only one SPI slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
804
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of
the slave.
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
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Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The
master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is
transmitted.
Slave Select (NSS): This control line allows the master to select or deselect the slave.
36.6.7.1 Modes of Operation
The USART can operate in SPI Master mode or in SPI Slave mode.
Operation in SPI Master mode is programmed by writing 0xE to the USART_MODE field in US_MR. In this case
the SPI lines must be connected as described below:
The MOSI line is driven by the output pin TXD
The MISO line drives the input pin RXD
The SCK line is driven by the output pin SCK
The NSS line is driven by the output pin RTS
Operation in SPI Slave mode is programmed by writing to 0xF the USART_MODE field in US_MR. In this case the
SPI lines must be connected as described below:
The MOSI line drives the input pin RXD
The MISO line is driven by the output pin TXD
The SCK line drives the input pin SCK
The NSS line drives the input pin CTS
In order to avoid unpredictable behavior, any change of the SPI mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset). (See Section 36.6.7.4
”Receiver and Transmitter Control”).
36.6.7.2 Baud Rate
In SPI mode, the baud rate generator operates in the same way as in USART Synchronous mode. See Section
36.6.1.3 ”Baud Rate in Synchronous Mode or SPI Mode”. However, there are some restrictions:
In SPI Master mode:
The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to 1 in the
US_MR, in order to generate correctly the serial clock on the SCK pin.
To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior
or equal to 6.
If the divided peripheral clock is selected, the value programmed in CD must be even to ensure a 50:50
mark/space ratio on the SCK pin, this value can be odd if the peripheral clock is selected.
In SPI Slave mode:
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR.
Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal
on the USART SCK pin.
To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at
least 6 times lower than the system clock.
36.6.7.3 Data Transfer
Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL
and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the US_MR. The nine bits are
selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI mode
(Master or Slave).
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Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the US_MR. The clock phase is programmed with the CPHA bit. These two parameters determine the
edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible
states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair
must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
Table 36-13.
SPI Bus Protocol Mode
SPI Bus Protocol Mode
CPOL
CPHA
0
0
1
1
0
0
2
1
1
3
1
0
Figure 36-37. SPI Transfer Format (CPHA = 1, 8 bits per transfer)
SCK cycle (for reference)
1
2
3
4
6
5
7
8
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
MSB
MSB
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
NSS
SPI Master -> RTS
SPI Slave -> CTS
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Figure 36-38. SPI Transfer Format (CPHA = 0, 8 bits per transfer)
SCK cycle (for reference)
1
2
3
4
5
7
6
8
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MSB
6
5
4
3
2
1
LSB
MISO
SPI Master -> RXD
SPI Slave -> TXD
MSB
6
5
4
3
2
1
LSB
NSS
SPI Master -> RTS
SPI Slave -> CTS
36.6.7.4 Receiver and Transmitter Control
See Section 36.6.2 ”Receiver and Transmitter Control”.
36.6.7.5 Character Transmission
The characters are sent by writing in the Transmit Holding register (US_THR). An additional condition for
transmitting a character can be added when the USART is configured in SPI Master mode. In the USART Mode
Register (SPI_MODE) (USART_MR), the value configured on the bit WRDBT can prevent any character
transmission (even if US_THR has been written) while the receiver side is not ready (character not read). When
WRDBT equals 0, the character is transmitted whatever the receiver status. If WRDBT is set to 1, the transmitter
waits for the Receive Holding register (US_RHR) to be read before transmitting the character (RXRDY flag
cleared), thus preventing any overflow (character loss) on the receiver side.
The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is
empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the
current character processing is completed, the last character written in US_THR is transferred into the Shift
register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave mode and if a character must be sent while the US_THR is empty, the UNRE
(Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is
cleared by writing a 1 to the RSTSTA (Reset Status) bit in US_CR.
In SPI Master mode, the slave select line (NSS) is asserted at low level one tbit (tbit being the nominal time required
to transmit a bit) before the transmission of the MSB bit and released at high level one tbit after the transmission of
the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a
minimum delay of three tbit always inserted. However, in order to address slave devices supporting the CSAAT
mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing a 1 to the
RTSEN bit in the US_CR. The slave select line (NSS) can be released at high level only by writing a 1 to the
RTSDIS bit in the US_CR (for example, when all data have been transferred to the slave device).
SAM4CM Series [DATASHEET]
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807
In SPI Slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a
character transmission but only a low level. However, this low level must be present on the slave select line (NSS)
at least one tbit before the first serial clock cycle corresponding to the MSB bit.
36.6.7.6 Character Reception
When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the
RXRDY bit in the Status register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE
(Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The
OVRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in the US_CR.
To ensure correct behavior of the receiver in SPI Slave mode, the master device sending the frame must ensure a
minimum delay of one tbit between each character transmission. The receiver does not require a falling edge of the
slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be
present on the slave select line (NSS) at least one tbit before the first serial clock cycle corresponding to the MSB
bit.
36.6.7.7 Receiver Timeout
Because the receiver baud rate clock is active only during data transfers in SPI mode, a receiver timeout is
impossible in this mode, whatever the time-out value is (field TO) in the US_RTOR.
36.6.8 Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback capability allows
on-board diagnostics. In Loopback mode, the USART interface pins are disconnected or not and reconfigured for
loopback internally or externally.
36.6.8.1 Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
Figure 36-39. Normal Mode Configuration
RXD
Receiver
TXD
Transmitter
36.6.8.2 Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD
pin, as shown in Figure 36-40. Programming the transmitter has no effect on the TXD pin. The RXD pin is still
connected to the receiver input, thus the receiver remains active.
Figure 36-40. Automatic Echo Mode Configuration
RXD
Receiver
TXD
Transmitter
808
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.6.8.3 Local Loopback Mode
Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure
36-41. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is
continuously driven high, as in idle state.
Figure 36-41. Local Loopback Mode Configuration
RXD
Receiver
1
Transmitter
TXD
36.6.8.4 Remote Loopback Mode
Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 36-42. The transmitter
and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.
Figure 36-42. Remote Loopback Mode Configuration
1
Receiver
RXD
TXD
Transmitter
36.6.9 Register Write Protection
To prevent any single software error from corrupting USART behavior, certain registers in the address space can
be write-protected by setting the WPEN bit in the USART Write Protection Mode Register (US_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the USART Write Protection Status
Register (US_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the US_WPSR.
The following registers can be write-protected:
USART Mode Register
USART Baud Rate Generator Register
USART Receiver Time-out Register
USART Transmitter Timeguard Register
USART FI DI RATIO Register
USART IrDA Filter Register
USART Manchester Configuration Register
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
809
36.7
Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface
Table 36-14.
Register Mapping
Offset
Register
Name
Access
Reset
0x0000
Control Register
US_CR
Write-only
–
0x0004
Mode Register
US_MR
Read/Write
0x0
0x0008
Interrupt Enable Register
US_IER
Write-only
–
0x000C
Interrupt Disable Register
US_IDR
Write-only
–
0x0010
Interrupt Mask Register
US_IMR
Read-only
0x0
0x0014
Channel Status Register
US_CSR
Read-only
0x0
0x0018
Receive Holding Register
US_RHR
Read-only
0x0
0x001C
Transmit Holding Register
US_THR
Write-only
–
0x0020
Baud Rate Generator Register
US_BRGR
Read/Write
0x0
0x0024
Receiver Time-out Register
US_RTOR
Read/Write
0x0
0x0028
Transmitter Timeguard Register
US_TTGR
Read/Write
0x0
Reserved
–
–
–
0x0040
FI DI Ratio Register
US_FIDI
Read/Write
0x174
0x0044
Number of Errors Register
US_NER
Read-only
0x0
0x0048
Reserved
–
–
–
0x004C
IrDA Filter Register
US_IF
Read/Write
0x0
0x0050
Manchester Configuration Register
US_MAN
Read/Write
0x30011004
0x0054–0x005C
Reserved
–
–
–
0x0060–0x00E0
Reserved
–
–
–
0x00E4
Write Protection Mode Register
US_WPMR
Read/Write
0x0
0x00E8
Write Protection Status Register
US_WPSR
Read-only
0x0
0x00EC–0x00FC
Reserved
–
–
–
0x0100–0x0128
Reserved for PDC Registers
–
–
–
0x002C–0x003C
810
SAM4CM Series [DATASHEET]
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36.7.1 USART Control Register
Name:
US_CR
Address:
0x40024000 (0), 0x40028000 (1), 0x4002C000 (2), 0x40030000 (3), 0x40034000 (4)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
RTSDIS
18
RTSEN
17
–
16
–
15
RETTO
14
RSTNACK
13
RSTIT
12
SENDA
11
STTTO
10
STPBRK
9
STTBRK
8
RSTSTA
7
TXDIS
6
TXEN
5
RXDIS
4
RXEN
3
RSTTX
2
RSTRX
1
–
0
–
For SPI control, see Section 36.7.2 ”USART Control Register (SPI_MODE)”.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR.
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811
• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
No effect if no break is being transmitted.
• STTTO: Clear TIMEOUT Flag and Start Time-out After Next Character Received
0: No effect.
1: Starts waiting for a character before enabling the time-out counter. Immediately disables a time-out period in progress.
Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
0: No effect.
1: Resets ITER in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Start Time-out Immediately
0: No effect
1: Immediately restarts time-out period.
• RTSEN: Request to Send Pin Control
0: No effect.
1: Drives RTS pin to 0 if US_MR.USART_MODE field = 0.
• RTSDIS: Request to Send Pin Control
0: No effect.
1: Drives RTS pin to 1 if US_MR.USART_MODE field = 0.
812
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.2 USART Control Register (SPI_MODE)
Name:
US_CR (SPI_MODE)
Address:
0x40024000 (0), 0x40028000 (1), 0x4002C000 (2), 0x40030000 (3), 0x40034000 (4)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
RCS
18
FCS
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
RSTSTA
7
TXDIS
6
TXEN
5
RXDIS
4
RXEN
3
RSTTX
2
RSTRX
1
–
0
–
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits OVRE, UNRE in US_CSR.
SAM4CM Series [DATASHEET]
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813
• FCS: Force SPI Chip Select
Applicable if USART operates in SPI master mode (USART_MODE = 0xE):
0: No effect.
1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI slave
devices supporting the CSAAT mode (Chip Select Active After Transfer).
• RCS: Release SPI Chip Select
Applicable if USART operates in SPI master mode (USART_MODE = 0xE):
0: No effect.
1: Releases the Slave Select Line NSS (RTS pin).
814
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.3 USART Mode Register
Name:
US_MR
Address:
0x40024004 (0), 0x40028004 (1), 0x4002C004 (2), 0x40030004 (3), 0x40034004 (4)
Access:
Read/Write
31
ONEBIT
30
MODSYNC
29
MAN
28
FILTER
27
–
26
25
MAX_ITERATION
24
23
INVDATA
22
VAR_SYNC
21
DSNACK
20
INACK
19
OVER
18
CLKO
17
MODE9
16
MSBF
15
14
13
12
11
10
PAR
9
8
SYNC
4
3
2
1
0
CHMODE
7
NBSTOP
6
5
CHRL
USCLKS
USART_MODE
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
For SPI configuration, see Section 36.7.4 ”USART Mode Register (SPI_MODE)”.
• USART_MODE: USART Mode of Operation
Value
Name
Description
0x0
NORMAL
Normal mode
0x1
RS485
0x2
HW_HANDSHAKING
0x3
—
0x4
IS07816_T_0
IS07816 Protocol: T = 0
0x6
IS07816_T_1
IS07816 Protocol: T = 1
0x8
IRDA
0xE
SPI_MASTER
SPI master
0xF
SPI_SLAVE
SPI Slave
RS485
Hardware Handshaking
Reserved
IrDA
The PDC transfers are supported in all USART modes of operation.
• USCLKS: Clock Selection
Value
Name
Description
0
MCK
Peripheral clock is selected
1
DIV
Peripheral clock divided (DIV=8) is selected
2
—
3
SCK
Reserved
Serial clock (SCK) is selected
SAM4CM Series [DATASHEET]
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815
• CHRL: Character Length
Value
Name
Description
0
5_BIT
Character length is 5 bits
1
6_BIT
Character length is 6 bits
2
7_BIT
Character length is 7 bits
3
8_BIT
Character length is 8 bits
• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous mode.
1: USART operates in Synchronous mode.
• PAR: Parity Type
Value
Name
Description
0
EVEN
Even parity
1
ODD
Odd parity
2
SPACE
Parity forced to 0 (Space)
3
MARK
Parity forced to 1 (Mark)
4
NO
6
MULTIDROP
No parity
Multidrop mode
• NBSTOP: Number of Stop Bits
Value
Name
Description
0
1_BIT
1 stop bit
1
1_5_BIT
2
2_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
2 stop bits
• CHMODE: Channel Mode
Value
Name
Description
0
NORMAL
Normal mode
1
AUTOMATIC
2
LOCAL_LOOPBACK
3
REMOTE_LOOPBACK
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver Input.
Remote Loopback. RXD pin is internally connected to the TXD pin.
• MSBF: Bit Order
0: Least significant bit is sent/received first.
1: Most significant bit is sent/received first.
• MODE9: 9-bit Character Length
0: CHRL defines character length
1: 9-bit character length
816
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• OVER: Oversampling Mode
0: 16 × Oversampling
1: 8 × Oversampling
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITER is
asserted.
Note: MAX_ITERATION field must be set to 0 if DSNACK is cleared.
• INVDATA: Inverted Data
0: The data field transmitted on TXD line is the same as the one written in US_THR or the content read in US_RHR is the
same as RXD line. Normal mode of operation.
1: The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR or the
content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted mode of
operation, useful for contactless card application. To be used with configuration bit MSBF.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: User defined configuration of command or data sync field depending on MODSYNC value.
1: The sync field is updated when a character is written into US_THR.
• MAX_ITERATION: Maximum Number of Automatic Iteration
0–7: Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
• FILTER: Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
• MAN: Manchester Encoder/Decoder Enable
0: Manchester encoder/decoder are disabled.
1: Manchester encoder/decoder are enabled.
• MODSYNC: Manchester Synchronization Mode
0:The Manchester start bit is a 0 to 1 transition
1: The Manchester start bit is a 1 to 0 transition.
SAM4CM Series [DATASHEET]
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817
• ONEBIT: Start Frame Delimiter Selector
0: Start frame delimiter is COMMAND or DATA SYNC.
1: Start frame delimiter is one bit.
818
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.4 USART Mode Register (SPI_MODE)
Name:
US_MR (SPI_MODE)
Address:
0x40024004 (0), 0x40028004 (1), 0x4002C004 (2), 0x40030004 (3), 0x40034004 (4)
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
WRDBT
19
–
18
CLKO
17
–
16
CPOL
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
CPHA
6
5
4
3
2
1
0
7
CHRL
USCLKS
USART_MODE
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• USART_MODE: USART Mode of Operation
Value
Name
Description
0xE
SPI_MASTER
SPI master
0xF
SPI_SLAVE
SPI Slave
• USCLKS: Clock Selection
Value
Name
Description
0
MCK
Peripheral clock is selected
1
DIV
Peripheral clock divided (DIV=8) is selected
3
SCK
Serial Clock SLK is selected
• CHRL: Character Length
Value
Name
Description
3
8_BIT
Character length is 8 bits
• CPHA: SPI Clock Phase
– Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF):
0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
SAM4CM Series [DATASHEET]
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819
• CPOL: SPI Clock Polarity
Applicable if USART operates in SPI mode (slave or master, USART_MODE = 0xE or 0xF):
0: The inactive state value of SPCK is logic level zero.
1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
clock/data relationship between master and slave devices.
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• WRDBT: Wait Read Data Before Transfer
0: The character transmission starts as soon as a character is written into US_THR (assuming TXRDY was set).
1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receive Holding Register has been read).
820
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.5 USART Interrupt Enable Register
Name:
US_IER
Address:
0x40024008 (0), 0x40028008 (1), 0x4002C008 (2), 0x40030008 (3), 0x40034008 (4)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
MANE
23
–
22
–
21
–
20
-
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
For SPI specific configuration, see Section 36.7.6 ”USART Interrupt Enable Register (SPI_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• RXBRK: Receiver Break Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
• ENDTX: End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• ITER: Max number of Repetitions Reached Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
• RXBUFF: Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Enable
SAM4CM Series [DATASHEET]
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821
• CTSIC: Clear to Send Input Change Interrupt Enable
• MANE: Manchester Error Interrupt Enable
822
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.6 USART Interrupt Enable Register (SPI_MODE)
Name:
US_IER (SPI_MODE)
Address:
0x40024008 (0), 0x40028008 (1), 0x4002C008 (2), 0x40030008 (3), 0x40034008 (4)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
RXBUFF
11
TXBUFE
10
UNRE
9
TXEMPTY
8
–
7
–
6
–
5
OVRE
4
ENDTX
3
ENDRX
2
–
1
TXRDY
0
RXRDY
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• UNRE: SPI Underrun Error Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
SAM4CM Series [DATASHEET]
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823
36.7.7 USART Interrupt Disable Register
Name:
US_IDR
Address:
0x4002400C (0), 0x4002800C (1), 0x4002C00C (2), 0x4003000C (3), 0x4003400C (4)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
MANE
23
–
22
–
21
–
20
-
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
For SPI specific configuration, see Section 36.7.8 ”USART Interrupt Disable Register (SPI_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)
• ENDTX: End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITER: Max Number of Repetitions Reached Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
• RXBUFF: Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Disable
824
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• CTSIC: Clear to Send Input Change Interrupt Disable
• MANE: Manchester Error Interrupt Disable
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
825
36.7.8 USART Interrupt Disable Register (SPI_MODE)
Name:
US_IDR (SPI_MODE)
Address:
0x4002400C (0), 0x4002800C (1), 0x4002C00C (2), 0x4003000C (3), 0x4003400C (4)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
RXBUFF
11
TXBUFE
10
UNRE
9
TXEMPTY
8
–
7
–
6
–
5
OVRE
4
ENDTX
3
ENDRX
2
–
1
TXRDY
0
RXRDY
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Disables the corresponding interrupt.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• ENDRX: End of Receive Buffer Transfer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• UNRE: SPI Underrun Error Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
826
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.9
USART Interrupt Mask Register
Name:
US_IMR
Address:
0x40024010 (0), 0x40028010 (1), 0x4002C010 (2), 0x40030010 (3), 0x40034010 (4)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
MANE
23
–
22
–
21
–
20
-
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
For SPI specific configuration, see Section 36.7.10 ”USART Interrupt Mask Register (SPI_MODE)”.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
• ENDTX: End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• ITER: Max Number of Repetitions Reached Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
• RXBUFF: Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Mask
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
827
• CTSIC: Clear to Send Input Change Interrupt Mask
• MANE: Manchester Error Interrupt Mask
828
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.10 USART Interrupt Mask Register (SPI_MODE)
Name:
US_IMR (SPI_MODE)
Address:
0x40024010 (0), 0x40028010 (1), 0x4002C010 (2), 0x40030010 (3), 0x40034010 (4)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
RXBUFF
11
TXBUFE
10
UNRE
9
TXEMPTY
8
–
7
–
6
–
5
OVRE
4
ENDTX
3
ENDRX
2
–
1
TXRDY
0
RXRDY
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• UNRE: SPI Underrun Error Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
829
36.7.11 USART Channel Status Register
Name:
US_CSR
Address:
0x40024014 (0), 0x40028014 (1), 0x4002C014 (2), 0x40030014 (3), 0x40034014 (4)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
MANERR
23
CTS
22
–
21
–
20
–
19
CTSIC
18
–
17
–
16
–
15
–
14
–
13
NACK
12
RXBUFF
11
TXBUFE
10
ITER
9
TXEMPTY
8
TIMEOUT
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
2
RXBRK
1
TXRDY
0
RXRDY
For SPI specific configuration, see Section 36.7.12 ”USART Channel Status Register (SPI_MODE)”.
• RXRDY: Receiver Ready (cleared by reading US_RHR)
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready (cleared by writing US_THR)
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has
been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)
0: No break received or end of break detected since the last RSTSTA.
1: Break received or end of break detected since the last RSTSTA.
• ENDRX: End of RX Buffer (cleared by writing US_RCR or US_RNCR)
0: The Receive Counter Register has not reached 0 since the last write in US_RCR or US_RNCR(1).
1: The Receive Counter Register has reached 0 since the last write in US_RCR or US_RNCR(1).
• ENDTX: End of TX Buffer (cleared by writing US_TCR or US_TNCR)
0: The Transmit Counter Register has not reached 0 since the last write in US_TCR or US_TNCR(1).
1: The Transmit Counter Register has reached 0 since the last write in US_TCR or US_TNCR(1).
• OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
830
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• FRAME: Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
• PARE: Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out (cleared by writing a one to bit US_CR.STTTO)
0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty (cleared by writing US_THR)
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• ITER: Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)
0: Maximum number of repetitions has not been reached since the last RSTIT.
1: Maximum number of repetitions has been reached since the last RSTIT.
• TXBUFE: TX Buffer Empty (cleared by writing US_TCR or US_TNCR)
0: US_TCR or US_TNCR have a value other than 0(1).
1: Both US_TCR and US_TNCR have a value of 0(1).
• RXBUFF: RX Buffer Full (cleared by writing US_RCR or US_RNCR)
0: US_RCR or US_RNCR have a value other than 0(1).
1: Both US_RCR and US_RNCR have a value of 0(1).
Note:
1. US_RCR, US_RNCR, US_TCR and US_TNCR are PDC registers.
• NACK: Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)
0: Non acknowledge has not been detected since the last RSTNACK.
1: At least one non acknowledge has been detected since the last RSTNACK.
• CTSIC: Clear to Send Input Change Flag (cleared on read)
0: No input change has been detected on the CTS pin since the last read of US_CSR.
1: At least one input change has been detected on the CTS pin since the last read of US_CSR.
• CTS: Image of CTS Input
0: CTS input is driven low.
1: CTS input is driven high.
• MANERR: Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)
0: No Manchester error has been detected since the last RSTSTA.
1: At least one Manchester error has been detected since the last RSTSTA.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
831
36.7.12 USART Channel Status Register (SPI_MODE)
Name:
US_CSR (SPI_MODE)
Address:
0x40024014 (0), 0x40028014 (1), 0x4002C014 (2), 0x40030014 (3), 0x40034014 (4)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
RXBUFF
11
TXBUFE
10
UNRE
9
TXEMPTY
8
–
7
–
6
–
5
OVRE
4
ENDTX
3
ENDRX
2
–
1
TXRDY
0
RXRDY
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
• RXRDY: Receiver Ready (cleared by reading US_RHR)
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were
being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready (cleared by writing US_THR)
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As
soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• ENDRX: End of RX Buffer (cleared by writing US_RCR or US_RNCR)
0: The Receive Counter Register has not reached 0 since the last write in US_RCR or US_RNCR(1).
1: The Receive Counter Register has reached 0 since the last write in US_RCR or US_RNCR(1).
• ENDTX: End of TX Buffer (cleared by writing US_TCR or US_TNCR)
0: The Transmit Counter Register has not reached 0 since the last write in US_TCR or US_TNCR(1).
1: The Transmit Counter Register has reached 0 since the last write in US_TCR or US_TNCR(1).
• OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty (cleared by writing US_THR)
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
832
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• UNRE: Underrun Error (cleared by writing a one to bit US_CR.RSTSTA)
0: No SPI underrun error has occurred since the last RSTSTA.
1: At least one SPI underrun error has occurred since the last RSTSTA.
• TXBUFE: TX Buffer Empty (cleared by writing US_TCR or US_TNCR)
0: US_TCR or US_TNCR have a value other than 0(1).
1: Both US_TCR and US_TNCR have a value of 0(1).
• RXBUFF: RX Buffer Full (cleared by writing US_RCR or US_RNCR)
0: US_RCR or US_RNCR have a value other than 0(1).
1: Both US_RCR and US_RNCR have a value of 0(1).
Note:
1. US_RCR, US_RNCR, US_TCR and US_TNCR are PDC registers.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
833
36.7.13 USART Receive Holding Register
Name:
US_RHR
Address:
0x40024018 (0), 0x40028018 (1), 0x4002C018 (2), 0x40030018 (3), 0x40034018 (4)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
RXSYNH
14
–
13
–
12
–
11
–
10
–
9
–
8
RXCHR
7
6
5
4
3
2
1
0
RXCHR
• RXCHR: Received Character
Last character received if RXRDY is set.
• RXSYNH: Received Sync
0: Last character received is a data.
1: Last character received is a command.
834
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.14 USART Transmit Holding Register
Name:
US_THR
Address:
0x4002401C (0), 0x4002801C (1), 0x4002C01C (2), 0x4003001C (3), 0x4003401C (4)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
TXSYNH
14
–
13
–
12
–
11
–
10
–
9
–
8
TXCHR
7
6
5
4
3
2
1
0
TXCHR
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
• TXSYNH: Sync Field to be Transmitted
0: The next character sent is encoded as a data. Start frame delimiter is DATA SYNC.
1: The next character sent is encoded as a command. Start frame delimiter is COMMAND SYNC.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
835
36.7.15 USART Baud Rate Generator Register
Name:
US_BRGR
Address:
0x40024020 (0), 0x40028020 (1), 0x4002C020 (2), 0x40030020 (3), 0x40034020 (4)
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
17
FP
16
15
14
13
12
11
10
9
8
3
2
1
0
CD
7
6
5
4
CD
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• CD: Clock Divider
USART_MODE ≠ ISO7816
SYNC = 0
OVER = 0
CD
OVER = 1
0
USART_MODE = ISO7816
Baud Rate Clock Disabled
1 to 65535
CD = Selected Clock / (16 ×
Baud Rate)
CD = Selected Clock / (8 ×
Baud Rate)
• FP: Fractional Part
0: Fractional divider is disabled.
1–7: Baud rate resolution, defined by FP × 1/8.
836
SYNC = 1
or
USART_MODE = SPI
(Master or Slave)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
CD = Selected Clock / Baud
Rate
CD = Selected Clock /
(FI_DI_RATIO × Baud
Rate)
36.7.16 USART Receiver Time-out Register
Name:
US_RTOR
Address:
0x40024024 (0), 0x40028024 (1), 0x4002C024 (2), 0x40030024 (3), 0x40034024 (4)
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
3
2
1
0
TO
7
6
5
4
TO
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• TO: Time-out Value
0: The receiver time-out is disabled.
1–65535: The receiver time-out is enabled and TO is Time-out Delay / Bit Period.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
837
36.7.17 USART Transmitter Timeguard Register
Name:
US_TTGR
Address:
0x40024028 (0), 0x40028028 (1), 0x4002C028 (2), 0x40030028 (3), 0x40034028 (4)
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
TG
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• TG: Timeguard Value
0: The transmitter timeguard is disabled.
1–255: The transmitter timeguard is enabled and TG is Timeguard Delay / Bit Period.
838
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.18 USART FI DI RATIO Register
Name:
US_FIDI
Address:
0x40024040 (0), 0x40028040 (1), 0x4002C040 (2), 0x40030040 (3), 0x40034040 (4)
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
9
FI_DI_RATIO
8
7
6
5
4
3
2
1
0
FI_DI_RATIO
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the baud rate generator generates no signal.
1–2: Do not use.
3–2047: If ISO7816 mode is selected, the baud rate is the clock provided on SCK divided by FI_DI_RATIO.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
839
36.7.19 USART Number of Errors Register
Name:
US_NER
Address:
0x40024044 (0), 0x40028044 (1), 0x4002C044 (2), 0x40030044 (3), 0x40034044 (4)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
NB_ERRORS
This register is relevant only if USART_MODE = 0x4 or 0x6 in the USART Mode Register.
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
840
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.20 USART IrDA Filter Register
Name:
US_IF
Address:
0x4002404C (0), 0x4002804C (1), 0x4002C04C (2), 0x4003004C (3), 0x4003404C (4)
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
6
5
4
3
2
1
0
IRDA_FILTER
This register is relevant only if USART_MODE = 0x8 in the USART Mode Register.
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• IRDA_FILTER: IrDA Filter
The IRDA_FILTER value must be defined to meet the following criteria:
tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs
SAM4CM Series [DATASHEET]
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841
36.7.21 USART Manchester Configuration Register
Name:
US_MAN
Address:
0x40024050 (0), 0x40028050 (1), 0x4002C050 (2), 0x40030050 (3), 0x40034050 (4)
Access:
Read/Write
31
–
30
DRIFT
29
ONE
28
RX_MPOL
27
–
26
–
25
23
–
22
–
21
–
20
–
19
18
17
15
–
14
–
13
–
12
TX_MPOL
11
–
10
–
9
7
–
6
–
5
–
4
–
3
2
1
24
RX_PP
16
RX_PL
8
TX_PP
TX_PL
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
• TX_PL: Transmitter Preamble Length
0: The transmitter preamble pattern generation is disabled
1–15: The preamble length is TX_PL × Bit Period
• TX_PP: Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
Value
Name
Description
0
ALL_ONE
The preamble is composed of ‘1’s
1
ALL_ZERO
The preamble is composed of ‘0’s
2
ZERO_ONE
The preamble is composed of ‘01’s
3
ONE_ZERO
The preamble is composed of ‘10’s
• TX_MPOL: Transmitter Manchester Polarity
0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition.
1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1–15: The detected preamble length is RX_PL × Bit Period
• RX_PP: Receiver Preamble Pattern detected
The following values assume that RX_MPOL field is not set:
Value
842
Name
Description
00
ALL_ONE
The preamble is composed of ‘1’s
01
ALL_ZERO
The preamble is composed of ‘0’s
10
ZERO_ONE
The preamble is composed of ‘01’s
11
ONE_ZERO
The preamble is composed of ‘10’s
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
0
• RX_MPOL: Receiver Manchester Polarity
0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition.
1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the US_MAN register.
• DRIFT: Drift Compensation
0: The USART cannot recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
SAM4CM Series [DATASHEET]
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843
36.7.22 USART Write Protection Mode Register
Name:
US_WPMR
Address:
0x400240E4 (0), 0x400280E4 (1), 0x4002C0E4 (2), 0x400300E4 (3), 0x400340E4 (4)
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
–
2
–
1
–
0
WPEN
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
–
6
–
5
–
4
–
• WPEN: Write Protection Enable
0: Disables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII).
See Section 36.6.9 ”Register Write Protection” for the list of registers that can be write-protected.
• WPKEY: Write Protection Key
Value
Name
0x555341
PASSWD
844
Description
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as
0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
36.7.23 USART Write Protection Status Register
Name:
US_WPSR
Address:
0x400240E8 (0), 0x400280E8 (1), 0x4002C0E8 (2), 0x400300E8 (3), 0x400340E8 (4)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
22
21
20
19
18
17
16
11
10
9
8
3
–
2
–
1
–
0
WPVS
WPVSRC
15
14
13
12
WPVSRC
7
–
6
–
5
–
4
–
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of the US_WPSR.
1: A write protection violation has occurred since the last read of the US_WPSR. If this violation is an unauthorized attempt
to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
SAM4CM Series [DATASHEET]
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845
37.
Timer Counter (TC)
37.1
Description
A Timer Counter (TC) module includes three identical TC channels. The number of implemented TC modules is
device-specific.
Each TC channel can be independently programmed to perform a wide range of functions including frequency
measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals
which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to
generate processor interrupts.
The TC embeds a quadrature decoder (QDEC) connected in front of the timers and driven by TIOA0, TIOB0 and
TIOB1 inputs. When enabled, the QDEC performs the input lines filtering, decoding of quadrature signals and
connects to the timers/counters in order to read the position and speed of the motor through the user interface.
The TC block has two global registers which act upon all TC channels:
37.2
Block Control Register (TC_BCR)—allows channels to be started simultaneously with the same instruction
Block Mode Register (TC_BMR)—defines the external clock inputs for each channel, allowing them to be
chained
Embedded Characteristics
Total number of TC channels: three
TC channel size: 16-bit
Wide range of functions including:
846
̶
Frequency measurement
̶
Event counting
̶
Interval measurement
̶
Pulse generation
̶
Delay timing
̶
Pulse Width Modulation
̶
Up/down capabilities
̶
Quadrature decoder
̶
2-bit gray up/down count for stepper motor
Each channel is user-configurable and contains:
̶
Three external clock inputs
̶
Five Internal clock inputs
̶
Two multi-purpose input/output signals acting as trigger event
Internal interrupt signal
Register Write Protection
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.3
Block Diagram
Table 37-1.
Timer Counter Clock Assignment
Name
Definition
TIMER_CLOCK1
MCK/2
TIMER_CLOCK2
MCK/8
TIMER_CLOCK3
MCK/32
TIMER_CLOCK4
MCK/128
TIMER_CLOCK5
SLCK
Note:
Figure 37-1.
1.
When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Master Clock Register), SLCK input is equivalent
to Peripheral Clock.
Timer Counter Block Diagram
Parallel I/O
Controller
TIMER_CLOCK1
TCLK0
TIMER_CLOCK2
TIOA1
TIOA2
TIMER_CLOCK3
TCLK1
TIMER_CLOCK4
XC0
XC1
Timer/Counter
Channel 0
TIOA
TIOA0
TIOB0
TIOA0
TIOB
TCLK2
TIOB0
XC2
TIMER_CLOCK5
TC0XC0S
SYNC
TCLK0
TCLK1
TCLK2
INT0
TCLK0
TCLK1
XC0
TIOA0
XC1
Timer/Counter
Channel 1
TIOA
TIOA1
TIOB1
TIOA1
TIOB
TIOA2
TCLK2
TIOB1
XC2
TC1XC1S
TCLK0
XC0
TCLK1
XC1
TCLK2
XC2
SYNC
Timer/Counter
Channel 2
INT1
TIOA
TIOA2
TIOB2
TIOA2
TIOB
TIOA0
TIOA1
TC2XC2S
TIOB2
SYNC
INT2
Timer Counter
Interrupt
Controller
SAM4CM Series [DATASHEET]
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847
37.4
Pin List
Table 37-2.
Signal Description
Block/Channel
Signal Name
Description
XC0, XC1, XC2
Channel Signal
External Clock Inputs
TIOA
Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Output
TIOB
Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
INT
Interrupt Signal Output (internal signal)
SYNC
Table 37-3.
Synchronization Input Signal (from configuration register)
Pin List
Pin Name
Description
Type
TCLK0–TCLK2
External Clock Input
Input
TIOA0–TIOA2
I/O Line A
I/O
TIOB0–TIOB2
I/O Line B
I/O
37.5
Product Dependencies
37.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer
must first program the PIO controllers to assign the TC pins to their peripheral functions.
Table 37-4.
848
I/O Lines
Instance
Signal
I/O Line
Peripheral
TC0
TCLK0
PB4
B
TC0
TCLK1
PB9
A
TC0
TCLK2
PB12
A
TC0
TIOA0
PA13
B
TC0
TIOA1
PB7
A
TC0
TIOA2
PB10
A
TC0
TIOB0
PA14
B
TC0
TIOB1
PB8
A
TC0
TIOB2
PB11
A
TC1
TCLK3
PB26
A
TC1
TCLK4
PA17
B
TC1
TCLK5
PA19
B
TC1
TIOA3
PB24
A
TC1
TIOA4
PA15
B
TC1
TIOA5
PA18
B
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 37-4.
I/O Lines (Continued)
TC1
TIOB3
PB25
A
TC1
TIOB4
PA16
B
TC1
TIOB5
PA20
B
37.5.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the Timer Counter clock of each channel.
37.5.3 Interrupt Sources
The TC has an interrupt line per channel connected to the interrupt controller. Handling the TC interrupt requires
programming the interrupt controller before configuring the TC.
Table 37-5.
37.6
Peripheral IDs
Instance
ID
TC0
23
TC1
24
Functional Description
37.6.1 Description
All channels of the Timer Counter are independent and identical in operation except when the QDEC is enabled.
The registers for channel programming are listed in Table 37-6 “Register Mapping”.
37.6.2 16-bit Counter
Each 16-bit channel is organized around a 16-bit counter. The value of the counter is incremented at each positive
edge of the selected clock. When the counter has reached the value 216-1 and passes to zero, an overflow occurs
and the COVFS bit in the TC Status Register (TC_SR) is set.
The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The
counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the
selected clock.
37.6.3 Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or
TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC
Block Mode Register (TC_BMR). See Figure 37-2.
Each channel can independently select an internal or external clock source for its counter:
External clock signals(1): XC0, XC1 or XC2
Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, SLCK
This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR).
The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges
of the clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the
TC_CMR defines this signal (none, XC0, XC1, XC2). See Figure 37-3.
SAM4CM Series [DATASHEET]
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849
Note:
1.
Figure 37-2.
In all cases, if an external clock is used, the duration of each of its levels must be longer than the peripheral clock
period. The external clock frequency must be at least 2.5 times lower than the peripheral clock.
Clock Chaining Selection
TC0XC0S
Timer/Counter
Channel 0
TCLK0
TIOA1
XC0
TIOA2
TIOA0
XC1 = TCLK1
XC2 = TCLK2
TIOB0
SYNC
TC1XC1S
Timer/Counter
Channel 1
TCLK1
XC0 = TCLK0
TIOA0
TIOA1
XC1
TIOA2
XC2 = TCLK2
TIOB1
SYNC
Timer/Counter
Channel 2
TC2XC2S
XC0 = TCLK0
TCLK2
TIOA2
XC1 = TCLK1
TIOA0
XC2
TIOB2
TIOA1
SYNC
Figure 37-3.
Clock Selection
TCCLKS
CLKI
TIMER_CLOCK1
Synchronous
Edge Detection
TIMER_CLOCK2
TIMER_CLOCK3
Selected
Clock
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Peripheral Clock
BURST
1
850
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.6.4 Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped.
See Figure 37-4.
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC
Channel Control Register (TC_CCR). In Capture mode it can be disabled by an RB load event if LDBDIS is
set to 1 in the TC_CMR. In Waveform mode, it can be disabled by an RC Compare event if CPCDIS is set to
1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the
TC_CCR can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the TC_SR.
The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts
the clock. The clock can be stopped by an RB load event in Capture mode (LDBSTOP = 1 in TC_CMR) or
an RC compare event in Waveform mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands
are effective only if the clock is enabled.
Figure 37-4.
Clock Control
Selected
Clock
Trigger
CLKSTA
Q
Q
CLKEN
CLKDIS
S
R
S
R
Stop
Event
Counter
Clock
Disable
Event
37.6.5 Operating Modes
Each channel can operate independently in two different modes:
Capture mode provides measurement on signals.
Waveform mode provides wave generation.
The TC operating mode is programmed with the WAVE bit in the TC_CMR.
In Capture mode, TIOA and TIOB are configured as inputs.
In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the
external trigger.
37.6.6 Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a
fourth external trigger is available to each mode.
Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This
means that the counter value can be read differently from zero just after a trigger, especially when a low frequency
signal is selected as the clock.
SAM4CM Series [DATASHEET]
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851
The following triggers are common to both modes:
Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.
SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as
a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block
Control) with SYNC set.
Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value
matches the RC value if CPCTRG is set in the TC_CMR.
The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be
selected between TIOA and TIOB. In Waveform mode, an external event can be programmed on one of the
following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by
setting bit ENETRG in the TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the peripheral clock period in order to
be detected.
37.6.7 Capture Mode
Capture mode is entered by clearing the WAVE bit in the TC_CMR.
Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty
cycle and phase on TIOA and TIOB signals which are considered as inputs.
Figure 37-5 shows the configuration of the TC channel when programmed in Capture mode.
37.6.8 Capture Registers A and B
Registers A and B (RA and RB) are used as capture registers. They can be loaded with the counter value when a
programmable event occurs on the signal TIOA.
The LDRA field in the TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB field
defines the TIOA selected edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of
RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS bit) in the TC_SR.
In this case, the old value is overwritten.
37.6.9 Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
The ABETRG bit in the TC_CMR selects TIOA or TIOB input signal as an external trigger . The External Trigger
Edge Selection parameter (ETRGEDG field in TC_CMR) defines the edge (rising, falling, or both) detected to
generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
852
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
MTIOA
MTIOB
1
ABETRG
CLKI
If RA is not loaded
or RB is Loaded
Edge
Detector
ETRGEDG
SWTRG
Timer/Counter Channel
BURST
Peripheral Clock
Synchronous
Edge Detection
S
R
OVF
LDRB
Edge
Detector
Edge
Detector
Capture
Register A
LDBSTOP
R
S
CLKEN
LDRA
If RA is Loaded
CPCTRG
Counter
RESET
Trig
CLK
Q
Q
CLKSTA
LDBDIS
Capture
Register B
CLKDIS
TC1_SR
TIOA
TIOB
SYNC
XC2
XC1
XC0
TIMER_CLOCK5
TIMER_CLOCK4
TIMER_CLOCK3
TIMER_CLOCK2
TIMER_CLOCK1
TCCLKS
Compare RC =
Register C
COVFS
LDRBS
INT
Figure 37-5.
Capture Mode
LOVRS
CPCS
ETRGS
LDRAS
TC1_IMR
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
SAM4CM Series [DATASHEET]
853
37.6.10 Waveform Mode
Waveform mode is entered by setting the TC_CMRx.WAVE bit.
In Waveform mode, the TC channel generates one or two PWM signals with the same frequency and
independently programmable duty cycles, or generates different types of one-shot or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event
(EEVT parameter in TC_CMR).
Figure 37-6 shows the configuration of the TC channel when programmed in Waveform operating mode.
37.6.11 Waveform Selection
Depending on the WAVSEL parameter in TC_CMR, the behavior of TC_CV varies.
With any selection, TC_RA, TC_RB and TC_RC can all be used as compare registers.
RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly
configured) and RC Compare is used to control TIOA and/or TIOB outputs.
854
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1
EEVT
BURST
ENETRG
CLKI
Timer/Counter Channel
Edge
Detector
EEVTEDG
SWTRG
Peripheral Clock
Synchronous
Edge Detection
Trig
CLK
R
S
OVF
WAVSEL
RESET
Counter
WAVSEL
Q
Compare RA =
Register A
Q
CLKSTA
Compare RC =
Compare RB =
CPCSTOP
CPCDIS
Register C
CLKDIS
Register B
R
S
CLKEN
CPAS
INT
BSWTRG
BEEVT
BCPB
BCPC
ASWTRG
AEEVT
ACPA
ACPC
Output Controller
TIOB
SYNC
XC2
XC1
XC0
TIMER_CLOCK5
TIMER_CLOCK4
TIMER_CLOCK3
TIMER_CLOCK2
TIMER_CLOCK1
TCCLKS
TIOB
MTIOB
TIOA
MTIOA
Figure 37-6.
Waveform Mode
Output Controller
CPCS
CPBS
COVFS
TC1_SR
ETRGS
TC1_IMR
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
SAM4CM Series [DATASHEET]
855
37.6.11.1 WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 216-1. Once 216-1 has been reached, the value
of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 37-7.
An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger
may occur at any time. See Figure 37-8.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare
can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in
TC_CMR).
Figure 37-7.
WAVSEL = 00 without Trigger
Counter Value
Counter cleared by compare match with 0xFFFF
0xFFFF
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 37-8.
WAVSEL = 00 with Trigger
Counter Value
Counter cleared by compare match with 0xFFFF
0xFFFF
RC
Counter cleared by trigger
RB
RA
Waveform Examples
TIOB
TIOA
856
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Time
37.6.11.2 WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a
RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 37-9.
It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are
programmed correctly. See Figure 37-10.
In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock
(CPCDIS = 1 in TC_CMR).
Figure 37-9.
WAVSEL = 10 without Trigger
Counter Value
2n-1
(n = counter size)
Counter cleared by compare match with RC
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 37-10. WAVSEL = 10 with Trigger
Counter Value
2n-1
(n = counter size)
Counter cleared by compare match with RC
Counter cleared by trigger
RC
RB
RA
Waveform Examples
Time
TIOB
TIOA
SAM4CM Series [DATASHEET]
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857
37.6.11.3 WAVSEL = 01
When WAVSEL = 01, the value of TC_CV is incremented from 0 to 216-1 . Once 216-1 is reached, the value of
TC_CV is decremented to 0, then re-incremented to 216-1 and so on. See Figure 37-11.
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while
TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV
then increments. See Figure 37-12.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock
(CPCDIS = 1).
Figure 37-11. WAVSEL = 01 without Trigger
Counter Value
Counter decremented by compare match with 0xFFFF
0xFFFF
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 37-12. WAVSEL = 01 with Trigger
Counter Value
Counter decremented by compare match with 0xFFFF
0xFFFF
Counter decremented
by trigger
RC
RB
Counter incremented
by trigger
RA
Waveform Examples
TIOB
TIOA
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Time
37.6.11.4 WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV
is decremented to 0, then re-incremented to RC and so on. See Figure 37-13.
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while
TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV
then increments. See Figure 37-14.
RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
Figure 37-13. WAVSEL = 11 without Trigger
Counter Value
2n-1
(n = counter size)
Counter decremented by compare match with RC
RC
RB
RA
Time
Waveform Examples
TIOB
TIOA
Figure 37-14. WAVSEL = 11 with Trigger
Counter Value
2n-1
(n = counter size)
RC
RB
Counter decremented by compare match with RC
Counter decremented
by trigger
Counter incremented
by trigger
RA
Waveform Examples
Time
TIOB
TIOA
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859
37.6.12 External Event/Trigger Conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The
external event selected can then be used as a trigger.
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge
for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event
is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare
register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only
generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in the TC_CMR.
As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can
also be used as a trigger depending on the parameter WAVSEL.
37.6.13 Output Controller
The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used
only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare
controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the
output as defined in the corresponding parameter in TC_CMR.
37.6.14 Quadrature Decoder
37.6.14.1 Description
The quadrature decoder (QDEC) is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of
channel 0 and 1. Channel 2 can be used as a time base in case of speed measurement requirements (refer to
Figure 37-15).
When writing a 0 to bit QDEN of the TC_BMR, the QDEC is bypassed and the IO pins are directly routed to the
timer counter function.
TIOA0 and TIOB0 are to be driven by the two dedicated quadrature signals from a rotary sensor mounted on the
shaft of the off-chip motor.
A third signal from the rotary sensor can be processed through pin TIOB1 and is typically dedicated to be driven by
an index signal if it is provided by the sensor. This signal is not required to decode the quadrature signals PHA,
PHB.
Field TCCLKS of TC_CMRx must be configured to select XC0 input (i.e., 0x101). Field TC0XC0S has no effect as
soon as the QDEC is enabled.
Either speed or position/revolution can be measured. Position channel 0 accumulates the edges of PHA, PHB
input signals giving a high accuracy on motor position whereas channel 1 accumulates the index pulses of the
sensor, therefore the number of rotations. Concatenation of both values provides a high level of precision on
motion system position.
In Speed mode, position cannot be measured but revolution can be measured.
Inputs from the rotary sensor can be filtered prior to down-stream processing. Accommodation of input polarity,
phase definition and other factors are configurable.
Interruptions can be generated on different events.
A compare function (using TC_RC) is available on channel 0 (speed/position) or channel 1 (rotation) and can
generate an interrupt by means of the CPCS flag in the TC_SRx.
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Figure 37-15. Predefined Connection of the Quadrature Decoder with Timer Counters
Reset pulse
SPEEDEN
Quadrature
Decoder
1
1
(Filter + Edge
Detect + QD)
TIOA
Timer/Counter
Channel 0
TIOA0
QDEN
PHEdges
1
TIOB
1
XC0
TIOB0
TIOA0
PHA
TIOB0
PHB
TIOB1
IDX
XC0
Speed/Position
QDEN
Index
1
TIOB
TIOB1
1
XC0
Timer/Counter
Channel 1
XC0
Rotation
Direction
Timer/Counter
Channel 2
Speed Time Base
37.6.14.2 Input Pre-processing
Input pre-processing consists of capabilities to take into account rotary sensor factors such as polarities and phase
definition followed by configurable digital filtering.
Each input can be negated and swapping PHA, PHB is also configurable.
The MAXFILT field in the TC_BMR is used to configure a minimum duration for which the pulse is stated as valid.
When the filter is active, pulses with a duration lower than MAXFILT +1 × tperipheral clock ns are not passed to downstream logic.
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Figure 37-16. Input Stage
Input Pre-Processing
MAXFILT
SWAP
1
PHA
Filter
TIOA0
MAXFILT > 0
1
PHedge
Direction
and
Edge
Detection
INVA
1
PHB
Filter
TIOB0
1
DIR
1
IDX
INVB
1
1
IDX
Filter
TIOB1
IDXPHB
INVIDX
Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate
contamination on the optical or magnetic disk of the rotary sensor.
Spurious pulses can also occur in environments with high levels of electro-magnetic interference. Or, simply if
vibration occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the
beginning of one of the reflective or magnetic bars on the rotary sensor disk is aligned with the light or magnetic
(Hall) receiver cell of the rotary sensor. Any vibration can make the PHA, PHB signals toggle for a short duration.
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Figure 37-17. Filtering Examples
MAXFILT = 2
Peripheral Clock
particulate contamination
PHA,B
Filter Out
Optical/Magnetic disk strips
PHA
PHB
motor shaft stopped in such a position that
rotary sensor cell is aligned with an edge of the disk
rotation
stop
PHA
PHB Edge area due to system vibration
PHB
Resulting PHA, PHB electrical waveforms
PHA
stop
mechanical shock on system
PHB
vibration
PHA, PHB electrical waveforms after filtering
PHA
PHB
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863
37.6.14.3 Direction Status and Change Detection
After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the two quadrature
signals detected in order to be counted by timer/counter logic downstream.
The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status
depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
Any change in rotation direction is reported in the TC_QISR and can generate an interrupt.
The direction change condition is reported as soon as two consecutive edges on a phase signal have sampled the
same value on the other phase signal and there is an edge on the other signal. The two consecutive edges of one
phase signal sampling the same value on other phase signal is not sufficient to declare a direction change, for the
reason that particulate contamination may mask one or more reflective bars on the optical or magnetic disk of the
sensor. Refer to Figure 37-18 for waveforms.
Figure 37-18. Rotation Change Detection
Direction Change under normal conditions
PHA
change condition
Report Time
PHB
DIR
DIRCHG
No direction change due to particulate contamination masking a reflective bar
missing pulse
PHA
same phase
PHB
DIR
spurious change condition (if detected in a simple way)
DIRCHG
The direction change detection is disabled when QDTRANS is set in the TC_BMR. In this case, the DIR flag report
must not be used.
A quadrature error is also reported by the QDEC via the QERR flag in the TC_QISR. This error is reported if the
time difference between two edges on PHA, PHB is lower than a predefined value. This predefined value is
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configurable and corresponds to (MAXFILT + 1) × tperipheral clock ns. After being filtered there is no reason to have
two edges closer than (MAXFILT + 1) × tperipheral clock ns under normal mode of operation.
Figure 37-19. Quadrature Error Detection
MAXFILT = 2
Peripheral Clock
Abnormally formatted optical disk strips (theoretical view)
PHA
PHB
strip edge inaccurary due to disk etching/printing process
PHA
PHB
resulting PHA, PHB electrical waveforms
PHA
Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time.
PHB
duration < MAXFILT
QERR
MAXFILT must be tuned according to several factors such as the peripheral clock frequency, type of rotary sensor
and rotation speed to be achieved.
37.6.14.4 Position and Rotation Measurement
When the POSEN bit is set in the TC_BMR, the motor axis position is processed on channel 0 (by means of the
PHA, PHB edge detections) and the number of motor revolutions are recorded on channel 1 if the IDX signal is
provided on the TIOB1 input. The position measurement can be read in the TC_CV0 register and the rotation
measurement can be read in the TC_CV1 register.
Channel 0 and 1 must be configured in Capture mode (TC_CMR0.WAVE = 0). ‘Rising edge’ must be selected as
the External Trigger Edge (TC_CMR.ETRGEDG = 0x01) and ‘TIOA’ must be selected as the External Trigger
(TC_CMR.ABETRG = 0x1).
In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0
register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word.
The timer/counter channel 0 is cleared for each increment of IDX count value.
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865
Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter
channels 0 and 1. The direction status is reported on TC_QISR.
37.6.14.5
Speed Measurement
When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in
Waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter
by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOA output.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set.
Channel 0 must be configured in Capture mode (WAVE = 0 in TC_CMR0). The ABETRG bit of TC_CMR0 must be
configured at 1 to select TIOA as a trigger for this channel.
EDGTRG must be set to 0x01, to clear the counter on a rising edge of the TIOA signal and field LDRA must be set
accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a
consequence, at the end of each time base period the differentiation required for the speed calculation is
performed.
The process must be started by configuring bits CLKEN and SWTRG in the TC_CCR.
The speed can be read on field RA in TC_RA0.
Channel 1 can still be used to count the number of revolutions of the motor.
37.6.15 2-bit Gray Up/Down Counter for Stepper Motor
Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA,
TIOB outputs by means of the GCEN bit in TC_SMMRx.
Up or Down count can be defined by writing bit DOWN in TC_SMMRx.
It is mandatory to configure the channel in Waveform mode in the TC_CMR.
The period of the counters can be programmed in TC_RCx.
Figure 37-20. 2-bit Gray Up/Down Counter
WAVEx = GCENx =1
TIOAx
TC_RCx
TIOBx
DOWNx
866
SAM4CM Series [DATASHEET]
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37.6.16 Register Write Protection
To prevent any single software error from corrupting TC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the TC Write Protection Mode Register (TC_WPMR).
The Timer Counter clock of the first channel must be enabled to access TC_WPMR.
The following registers can be write-protected:
TC Block Mode Register
TC Channel Mode Register: Capture Mode
TC Channel Mode Register: Waveform Mode
TC Stepper Motor Mode Register
TC Register A
TC Register B
TC Register C
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37.7
Timer Counter (TC) User Interface
Table 37-6.
Register Mapping
Offset(1)
Register
Name
Access
Reset
0x00 + channel * 0x40 + 0x00
Channel Control Register
TC_CCR
Write-only
–
0x00 + channel * 0x40 + 0x04
Channel Mode Register
TC_CMR
Read/Write
0
0x00 + channel * 0x40 + 0x08
Stepper Motor Mode Register
TC_SMMR
Read/Write
0
0x00 + channel * 0x40 + 0x0C
Reserved
–
–
–
0x00 + channel * 0x40 + 0x10
Counter Value
TC_CV
0x00 + channel * 0x40 + 0x14
Register A
TC_RA
Read-only
Read/Write
0
(2)
0
(2)
0
0x00 + channel * 0x40 + 0x18
Register B
TC_RB
0x00 + channel * 0x40 + 0x1C
Register C
TC_RC
Read/Write
0
0x00 + channel * 0x40 + 0x20
Status Register
TC_SR
Read-only
0
0x00 + channel * 0x40 + 0x24
Interrupt Enable Register
TC_IER
Write-only
–
0x00 + channel * 0x40 + 0x28
Interrupt Disable Register
TC_IDR
Write-only
–
0x00 + channel * 0x40 + 0x2C
Interrupt Mask Register
TC_IMR
Read-only
0
0xC0
Block Control Register
TC_BCR
Write-only
–
0xC4
Block Mode Register
TC_BMR
Read/Write
0
0xC8
QDEC Interrupt Enable Register
TC_QIER
Write-only
–
0xCC
QDEC Interrupt Disable Register
TC_QIDR
Write-only
–
0xD0
QDEC Interrupt Mask Register
TC_QIMR
Read-only
0
0xD4
QDEC Interrupt Status Register
TC_QISR
Read-only
0
0xD8
Reserved
–
–
–
0xE4
Write Protection Mode Register
TC_WPMR
Read/Write
0
Reserved
–
–
–
0xE8–0xFC
Notes:
1. Channel index ranges from 0 to 2.
2. Read-only if TC_CMRx.WAVE = 0
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Read/Write
37.7.1 TC Channel Control Register
Name:
TC_CCRx [x=0..2]
Address:
0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1],
0x40014080 (1)[2]
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
SWTRG
1
CLKDIS
0
CLKEN
• CLKEN: Counter Clock Enable Command
0: No effect.
1: Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0: No effect.
1: Disables the clock.
• SWTRG: Software Trigger Command
0: No effect.
1: A software trigger is performed: the counter is reset and the clock is started.
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869
37.7.2 TC Channel Mode Register: Capture Mode
Name:
TC_CMRx [x=0..2] (CAPTURE_MODE)
Address:
0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1],
0x40014084 (1)[2]
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
18
17
24
–
23
–
22
–
21
–
20
–
19
15
WAVE
14
CPCTRG
13
–
12
–
11
–
10
ABETRG
9
7
LDBDIS
6
LDBSTOP
5
4
3
CLKI
2
1
TCCLKS
16
LDRB
BURST
LDRA
8
ETRGEDG
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TCCLKS: Clock Selection
Value
Name
Description
0
TIMER_CLOCK1
Clock selected: internal MCK/2 clock signal (from PMC)
1
TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2
TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3
TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4
TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5
XC0
Clock selected: XC0
6
XC1
Clock selected: XC1
7
XC2
Clock selected: XC2
• CLKI: Clock Invert
0: Counter is incremented on rising edge of the clock.
1: Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
Value
Name
Description
0
NONE
The clock is not gated by an external signal.
1
XC0
XC0 is ANDed with the selected clock.
2
XC1
XC1 is ANDed with the selected clock.
3
XC2
XC2 is ANDed with the selected clock.
• LDBSTOP: Counter Clock Stopped with RB Loading
0: Counter clock is not stopped when RB loading occurs.
1: Counter clock is stopped when RB loading occurs.
870
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0
• LDBDIS: Counter Clock Disable with RB Loading
0: Counter clock is not disabled when RB loading occurs.
1: Counter clock is disabled when RB loading occurs.
• ETRGEDG: External Trigger Edge Selection
Value
Name
Description
0
NONE
The clock is not gated by an external signal.
1
RISING
Rising edge
2
FALLING
Falling edge
3
EDGE
Each edge
• ABETRG: TIOA or TIOB External Trigger Selection
0: TIOB is used as an external trigger.
1: TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0: RC Compare has no effect on the counter and its clock.
1: RC Compare resets the counter and starts the counter clock.
• WAVE: Waveform Mode
0: Capture mode is enabled.
1: Capture mode is disabled (Waveform mode is enabled).
• LDRA: RA Loading Edge Selection
Value
Name
Description
0
NONE
None
1
RISING
Rising edge of TIOA
2
FALLING
Falling edge of TIOA
3
EDGE
Each edge of TIOA
• LDRB: RB Loading Edge Selection
Value
Name
Description
0
NONE
None
1
RISING
Rising edge of TIOA
2
FALLING
Falling edge of TIOA
3
EDGE
Each edge of TIOA
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871
37.7.3 TC Channel Mode Register: Waveform Mode
Name:
TC_CMRx [x=0..2] (WAVEFORM_MODE)
Address:
0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1],
0x40014084 (1)[2]
Access:
Read/Write
31
30
29
BSWTRG
23
28
27
BEEVT
22
21
ASWTRG
20
19
AEEVT
15
WAVE
14
13
7
CPCDIS
6
CPCSTOP
WAVSEL
26
25
BCPB
18
17
12
ENETRG
11
4
3
CLKI
5
BURST
ACPA
10
9
EEVT
2
1
TCCLKS
Name
Description
0
TIMER_CLOCK1
Clock selected: internal MCK/2 clock signal (from PMC)
1
TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2
TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3
TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4
TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5
XC0
Clock selected: XC0
6
XC1
Clock selected: XC1
7
XC2
Clock selected: XC2
• CLKI: Clock Invert
0: Counter is incremented on rising edge of the clock.
1: Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
Value
Name
Description
0
NONE
The clock is not gated by an external signal.
1
XC0
XC0 is ANDed with the selected clock.
2
XC1
XC1 is ANDed with the selected clock.
3
XC2
XC2 is ANDed with the selected clock.
• CPCSTOP: Counter Clock Stopped with RC Compare
0: Counter clock is not stopped when counter reaches RC.
1: Counter clock is stopped when counter reaches RC.
SAM4CM Series [DATASHEET]
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8
EEVTEDG
• TCCLKS: Clock Selection
872
16
ACPC
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
Value
24
BCPC
0
• CPCDIS: Counter Clock Disable with RC Compare
0: Counter clock is not disabled when counter reaches RC.
1: Counter clock is disabled when counter reaches RC.
• EEVTEDG: External Event Edge Selection
Value
Name
Description
0
NONE
None
1
RISING
Rising edge
2
FALLING
Falling edge
3
EDGE
Each edge
• EEVT: External Event Selection
Signal selected as external event.
Value
Note:
Name
Description
0
TIOB
(1)
TIOB Direction
TIOB
Input
1
XC0
XC0
Output
2
XC1
XC1
Output
3
XC2
XC2
Output
1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and
subsequently no IRQs.
• ENETRG: External Event Trigger Enable
0: The external event has no effect on the counter and its clock.
1: The external event resets the counter and starts the counter clock.
Note: Whatever the value programmed in ENETRG, the selected external event only controls the TIOA output and TIOB if not used as
input (trigger event input or other input used).
• WAVSEL: Waveform Selection
Value
Name
Description
0
UP
UP mode without automatic trigger on RC Compare
1
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
2
UP_RC
UP mode with automatic trigger on RC Compare
3
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
• WAVE: Waveform Mode
0: Waveform mode is disabled (Capture mode is enabled).
1: Waveform mode is enabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
873
• ACPA: RA Compare Effect on TIOA
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
• ACPC: RC Compare Effect on TIOA
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
• AEEVT: External Event Effect on TIOA
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
• ASWTRG: Software Trigger Effect on TIOA
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
• BCPB: RB Compare Effect on TIOB
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
• BCPC: RC Compare Effect on TIOB
874
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• BEEVT: External Event Effect on TIOB
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
• BSWTRG: Software Trigger Effect on TIOB
Value
Name
Description
0
NONE
None
1
SET
Set
2
CLEAR
Clear
3
TOGGLE
Toggle
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
875
37.7.4 TC Stepper Motor Mode Register
Name:
TC_SMMRx [x=0..2]
Address:
0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1],
0x40014088 (1)[2]
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
DOWN
0
GCEN
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• GCEN: Gray Count Enable
0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.
• DOWN: Down Count
0: Up counter.
1: Down counter.
876
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.5 TC Counter Value Register
Name:
TC_CVx [x=0..2]
Address:
0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1],
0x40014090 (1)[2]
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CV
23
22
21
20
CV
15
14
13
12
CV
7
6
5
4
CV
• CV: Counter Value
CV contains the counter value in real time.
IMPORTANT: For 16-bit channels, CV field size is limited to register bits 15:0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
877
37.7.6 TC Register A
Name:
TC_RAx [x=0..2]
Address:
0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1],
0x40014094 (1)[2]
Access:
Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RA
23
22
21
20
RA
15
14
13
12
RA
7
6
5
4
RA
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RA: Register A
RA contains the Register A value in real time.
IMPORTANT: For 16-bit channels, RA field size is limited to register bits 15:0.
878
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.7 TC Register B
Name:
TC_RBx [x=0..2]
Address:
0x40010018 (0)[0], 0x40010058 (0)[1], 0x40010098 (0)[2], 0x40014018 (1)[0], 0x40014058 (1)[1],
0x40014098 (1)[2]
Access:
Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RB
23
22
21
20
RB
15
14
13
12
RB
7
6
5
4
RB
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RB: Register B
RB contains the Register B value in real time.
IMPORTANT: For 16-bit channels, RB field size is limited to register bits 15:0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
879
37.7.8 TC Register C
Name:
TC_RCx [x=0..2]
Address:
0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[2], 0x4001401C (1)[0], 0x4001405C (1)[1],
0x4001409C (1)[2]
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
RC
23
22
21
20
RC
15
14
13
12
RC
7
6
5
4
RC
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• RC: Register C
RC contains the Register C value in real time.
IMPORTANT: For 16-bit channels, RC field size is limited to register bits 15:0.
880
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.9 TC Status Register
Name:
TC_SRx [x=0..2]
Address:
0x40010020 (0)[0], 0x40010060 (0)[1], 0x400100A0 (0)[2], 0x40014020 (1)[0], 0x40014060 (1)[1],
0x400140A0 (1)[2]
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
MTIOB
17
MTIOA
16
CLKSTA
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
ETRGS
6
LDRBS
5
LDRAS
4
CPCS
3
CPBS
2
CPAS
1
LOVRS
0
COVFS
• COVFS: Counter Overflow Status (cleared on read)
0: No counter overflow has occurred since the last read of the Status Register.
1: A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status (cleared on read)
0: Load overrun has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if TC_CMRx.WAVE = 0.
• CPAS: RA Compare Status (cleared on read)
0: RA Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1: RA Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
• CPBS: RB Compare Status (cleared on read)
0: RB Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1: RB Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
• CPCS: RC Compare Status (cleared on read)
0: RC Compare has not occurred since the last read of the Status Register.
1: RC Compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status (cleared on read)
0: RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.
• LDRBS: RB Loading Status (cleared on read)
0: RB Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1: RB Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
881
• ETRGS: External Trigger Status (cleared on read)
0: External trigger has not occurred since the last read of the Status Register.
1: External trigger has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status
0: Clock is disabled.
1: Clock is enabled.
• MTIOA: TIOA Mirror
0: TIOA is low. If TC_CMRx.WAVE = 0, this means that TIOA pin is low. If TC_CMRx.WAVE = 1, this means that TIOA is
driven low.
1: TIOA is high. If TC_CMRx.WAVE = 0, this means that TIOA pin is high. If TC_CMRx.WAVE = 1, this means that TIOA is
driven high.
• MTIOB: TIOB Mirror
0: TIOB is low. If TC_CMRx.WAVE = 0, this means that TIOB pin is low. If TC_CMRx.WAVE = 1, this means that TIOB is
driven low.
1: TIOB is high. If TC_CMRx.WAVE = 0, this means that TIOB pin is high. If TC_CMRx.WAVE = 1, this means that TIOB is
driven high.
882
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.10 TC Interrupt Enable Register
Name:
TC_IERx [x=0..2]
Address:
0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1],
0x400140A4 (1)[2]
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
ETRGS
6
LDRBS
5
LDRAS
4
CPCS
3
CPBS
2
CPAS
1
LOVRS
0
COVFS
• COVFS: Counter Overflow
0: No effect.
1: Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0: No effect.
1: Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0: No effect.
1: Enables the RA Compare Interrupt.
• CPBS: RB Compare
0: No effect.
1: Enables the RB Compare Interrupt.
• CPCS: RC Compare
0: No effect.
1: Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0: No effect.
1: Enables the RA Load Interrupt.
• LDRBS: RB Loading
0: No effect.
1: Enables the RB Load Interrupt.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
883
• ETRGS: External Trigger
0: No effect.
1: Enables the External Trigger Interrupt.
884
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.11 TC Interrupt Disable Register
Name:
TC_IDRx [x=0..2]
Address:
0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1],
0x400140A8 (1)[2]
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
ETRGS
6
LDRBS
5
LDRAS
4
CPCS
3
CPBS
2
CPAS
1
LOVRS
0
COVFS
• COVFS: Counter Overflow
0: No effect.
1: Disables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0: No effect.
1: Disables the Load Overrun Interrupt (if TC_CMRx.WAVE = 0).
• CPAS: RA Compare
0: No effect.
1: Disables the RA Compare Interrupt (if TC_CMRx.WAVE = 1).
• CPBS: RB Compare
0: No effect.
1: Disables the RB Compare Interrupt (if TC_CMRx.WAVE = 1).
• CPCS: RC Compare
0: No effect.
1: Disables the RC Compare Interrupt.
• LDRAS: RA Loading
0: No effect.
1: Disables the RA Load Interrupt (if TC_CMRx.WAVE = 0).
• LDRBS: RB Loading
0: No effect.
1: Disables the RB Load Interrupt (if TC_CMRx.WAVE = 0).
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
885
• ETRGS: External Trigger
0: No effect.
1: Disables the External Trigger Interrupt.
886
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.12 TC Interrupt Mask Register
Name:
TC_IMRx [x=0..2]
Address:
0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1],
0x400140AC (1)[2]
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
ETRGS
6
LDRBS
5
LDRAS
4
CPCS
3
CPBS
2
CPAS
1
LOVRS
0
COVFS
• COVFS: Counter Overflow
0: The Counter Overflow Interrupt is disabled.
1: The Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0: The Load Overrun Interrupt is disabled.
1: The Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0: The RA Compare Interrupt is disabled.
1: The RA Compare Interrupt is enabled.
• CPBS: RB Compare
0: The RB Compare Interrupt is disabled.
1: The RB Compare Interrupt is enabled.
• CPCS: RC Compare
0: The RC Compare Interrupt is disabled.
1: The RC Compare Interrupt is enabled.
• LDRAS: RA Loading
0: The Load RA Interrupt is disabled.
1: The Load RA Interrupt is enabled.
• LDRBS: RB Loading
0: The Load RB Interrupt is disabled.
1: The Load RB Interrupt is enabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
887
• ETRGS: External Trigger
0: The External Trigger Interrupt is disabled.
1: The External Trigger Interrupt is enabled.
888
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.13 TC Block Control Register
Name:
TC_BCR
Address:
0x400100C0 (0), 0x400140C0 (1)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
SYNC
• SYNC: Synchro Command
0: No effect.
1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
889
37.7.14 TC Block Mode Register
Name:
TC_BMR
Address:
0x400100C4 (0), 0x400140C4 (1)
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
23
22
21
20
19
–
18
–
17
IDXPHB
16
SWAP
12
EDGPHA
11
QDTRANS
10
SPEEDEN
9
POSEN
8
QDEN
4
3
2
1
0
MAXFILT
15
INVIDX
14
INVB
13
INVA
7
–
6
–
5
TC2XC2S
TC1XC1S
This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register.
• TC0XC0S: External Clock Signal 0 Selection
Value
Name
Description
0
TCLK0
Signal connected to XC0: TCLK0
1
–
Reserved
2
TIOA1
Signal connected to XC0: TIOA1
3
TIOA2
Signal connected to XC0: TIOA2
• TC1XC1S: External Clock Signal 1 Selection
Value
Name
Description
0
TCLK1
Signal connected to XC1: TCLK1
1
–
Reserved
2
TIOA0
Signal connected to XC1: TIOA0
3
TIOA2
Signal connected to XC1: TIOA2
• TC2XC2S: External Clock Signal 2 Selection
890
Value
Name
Description
0
TCLK2
Signal connected to XC2: TCLK2
1
–
Reserved
2
TIOA0
Signal connected to XC2: TIOA0
3
TIOA1
Signal connected to XC2: TIOA1
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
24
MAXFILT
TC0XC0S
• QDEN: Quadrature Decoder Enabled
0: Disabled.
1: Enables the QDEC (filter, edge detection and quadrature decoding).
Quadrature decoding (direction change) can be disabled using QDTRANS bit.
One of the POSEN or SPEEDEN bits must be also enabled.
• POSEN: Position Enabled
0: Disable position.
1: Enables the position measure on channel 0 and 1.
• SPEEDEN: Speed Enabled
0: Disabled.
1: Enables the speed measure on channel 0, the time base being provided by channel 2.
• QDTRANS: Quadrature Decoding Transparent
0: Full quadrature decoding logic is active (direction change detected).
1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
• EDGPHA: Edge on PHA Count Mode
0: Edges are detected on PHA only.
1: Edges are detected on both PHA and PHB.
• INVA: Inverted PHA
0: PHA (TIOA0) is directly driving the QDEC.
1: PHA is inverted before driving the QDEC.
• INVB: Inverted PHB
0: PHB (TIOB0) is directly driving the QDEC.
1: PHB is inverted before driving the QDEC.
• INVIDX: Inverted Index
0: IDX (TIOA1) is directly driving the QDEC.
1: IDX is inverted before driving the QDEC.
• SWAP: Swap PHA and PHB
0: No swap between PHA and PHB.
1: Swap PHA and PHB internally, prior to driving the QDEC.
• IDXPHB: Index Pin is PHB Pin
0: IDX pin of the rotary sensor must drive TIOA1.
1: IDX pin of the rotary sensor must drive TIOB0.
• MAXFILT: Maximum Filter
1–63: Defines the filtering capabilities.
Pulses with a period shorter than MAXFILT+1 peripheral clock cycles are discarded.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
891
37.7.15 TC QDEC Interrupt Enable Register
Name:
TC_QIER
Address:
0x400100C8 (0), 0x400140C8 (1)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
QERR
1
DIRCHG
0
IDX
• IDX: Index
0: No effect.
1: Enables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: Direction Change
0: No effect.
1: Enables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature Error
0: No effect.
1: Enables the interrupt when a quadrature error occurs on PHA, PHB.
892
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
37.7.16 TC QDEC Interrupt Disable Register
Name:
TC_QIDR
Address:
0x400100CC (0), 0x400140CC (1)
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
QERR
1
DIRCHG
0
IDX
• IDX: Index
0: No effect.
1: Disables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: Direction Change
0: No effect.
1: Disables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature Error
0: No effect.
1: Disables the interrupt when a quadrature error occurs on PHA, PHB.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
893
37.7.17 TC QDEC Interrupt Mask Register
Name:
TC_QIMR
Address:
0x400100D0 (0), 0x400140D0 (1)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
QERR
1
DIRCHG
0
IDX
• IDX: Index
0: The interrupt on IDX input is disabled.
1: The interrupt on IDX input is enabled.
• DIRCHG: Direction Change
0: The interrupt on rotation direction change is disabled.
1: The interrupt on rotation direction change is enabled.
• QERR: Quadrature Error
0: The interrupt on quadrature error is disabled.
1: The interrupt on quadrature error is enabled.
894
SAM4CM Series [DATASHEET]
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37.7.18 TC QDEC Interrupt Status Register
Name:
TC_QISR
Address:
0x400100D4 (0), 0x400140D4 (1)
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
DIR
7
–
6
–
5
–
4
–
3
–
2
QERR
1
DIRCHG
0
IDX
• IDX: Index
0: No Index input change since the last read of TC_QISR.
1: The IDX input has changed since the last read of TC_QISR.
• DIRCHG: Direction Change
0: No change on rotation direction since the last read of TC_QISR.
1: The rotation direction changed since the last read of TC_QISR.
• QERR: Quadrature Error
0: No quadrature error since the last read of TC_QISR.
1: A quadrature error occurred since the last read of TC_QISR.
• DIR: Direction
Returns an image of the actual rotation direction.
SAM4CM Series [DATASHEET]
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895
37.7.19 TC Write Protection Mode Register
Name:
TC_WPMR
Address:
0x400100E4 (0), 0x400140E4 (1)
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
–
2
–
1
–
0
WPEN
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
–
6
–
5
–
4
–
• WPEN: Write Protection Enable
0: Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
The Timer Counter clock of the first channel must be enabled to access this register.
See Section 37.6.16 “Register Write Protection” for a list of registers that can be write-protected and Timer Counter clock
conditions.
• WPKEY: Write Protection Key
Value
0x54494D
896
Name
PASSWD
Description
Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.
Pulse Width Modulation Controller (PWM)
38.1
Description
The PWM macrocell controls several channels independently. Each channel controls one square output
waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through
the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock
generator provides several clocks resulting from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering
system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
38.2
Embedded characteristics
4 Channels
One 16-bit Counter Per Channel
Common Clock Generator Providing Thirteen Different Clocks
̶
A Modulo n Counter Providing Eleven Clocks
̶
Two Independent Linear Dividers Working on Modulo n Counter Outputs
Independent Channels
̶
Independent Enable Disable Command for Each Channel
̶
Independent Clock Selection for Each Channel
̶
Independent Period and Duty Cycle for Each Channel
̶
Double Buffering of Period or Duty Cycle for Each Channel
̶
Programmable Selection of The Output Waveform Polarity for Each Channel
̶
Programmable Center or Left Aligned Output Waveform for Each Channel Block Diagram
SAM4CM Series [DATASHEET]
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897
38.3
Block Diagram
Figure 38-1.
Pulse Width Modulation Controller Block Diagram
PWM
Controller
PWMx
Period
Channel
PWMx
Update
Duty Cycle
Clock
Selector
Comparator
PWMx
Counter
PIO
PWM0
Channel
Period
PWM0
Update
Duty Cycle
Clock
Selector
PMC
MCK
Clock Generator
Comparator
PWM0
Counter
APB Interface
Interrupt Generator
Interrupt Controller
APB
38.4
I/O Lines Description
Each channel outputs one waveform on one external I/O line.
Table 38-1.
38.5
I/O Line Description
Name
Description
Type
PWMx
PWM Waveform Output for channel x
Output
Product Dependencies
38.5.1 I/O Lines
The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the
PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by
the application, they can be used for other purposes by the PIO controller.
898
SAM4CM Series [DATASHEET]
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All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four
PIO lines will be assigned to PWM outputs.
Table 38-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
PWM
PWM0
PC0
B
PWM
PWM0
PC6
A
PWM
PWM1
PC1
B
PWM
PWM1
PC7
A
PWM
PWM3
PC9
A
38.5.2 Power Management
The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power
Management Controller (PMC) before using the PWM. However, if the application does not require PWM
operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will
resume its operations where it left off.
All the PWM registers except PWM_CDTY and PWM_CPRD can be read without the PWM peripheral clock
enabled. All the registers can be written without the peripheral clock enabled.
38.5.3 Interrupt Sources
The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PWM
interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the PWM
interrupt line in edge sensitive mode.
Table 38-3.
38.6
Peripheral IDs
Instance
ID
PWM
41
Functional Description
The PWM macrocell is primarily composed of a clock generator module and 4 channels.
̶
Clocked by the system clock, MCK, the clock generator module provides 13 clocks.
̶
Each channel can independently choose one of the clock generator outputs.
̶
Each channel generates an output waveform with attributes that can be defined independently for
each channel through the user interface registers.
SAM4CM Series [DATASHEET]
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899
38.6.1 PWM Clock Generator
Figure 38-2.
Functional View of the Clock Generator Block Diagram
MCK
modulo n counter
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
Divider A
PREA
clkA
DIVA
PWM_MR
Divider B
PREB
clkB
DIVB
PWM_MR
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power
Management Controller (PMC).
The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks
available for all channels. Each channel can independently select one of the divided clocks.
The clock generator is divided in three blocks:
̶
̶
a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32,
FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024
two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clkA and clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock
to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting
clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This
implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true
when the PWM master clock is turned off through the Power Management Controller.
900
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.6.2 PWM Channel
38.6.2.1 Block Diagram
Figure 38-3.
Functional View of the Channel Block Diagram
inputs
from clock
generator
Channel
Clock
Selector
Internal
Counter
Comparator
PWMx
output waveform
inputs from
APB bus
Each of the four channels is composed of three blocks:
A clock selector which selects one of the clocks provided by the clock generator described in Section 38.6.1
”PWM Clock Generator”.
An internal counter clocked by the output of the clock selector. This internal counter is incremented or
decremented according to the channel configuration and comparators events. The size of the internal
counter is 16 bits.
A comparator used to generate events according to the internal counter value. It also computes the PWMx
output waveform according to the configuration.
38.6.2.2 Waveform Properties
The different properties of output waveforms are:
the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the
clock generator described in the previous section. This channel parameter is defined in the CPRE field of the
PWM_CMRx register. This field is reset at 0.
the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
(-----------------------------X × CPRD )MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(---------------------------------------------X*CPRD*DIVA -)
( X*CPRD*DIVB )
or ----------------------------------------------MCK
MCK
If the waveform is center aligned then the output waveform period depends on the counter source clock and
can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
(---------------------------------------2 × X × CPRD )
MCK
SAM4CM Series [DATASHEET]
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901
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(----------------------------------------------------2*X*CPRD*DIVA -)
( 2*X*CPRD*DIVB )
or -----------------------------------------------------MCK
MCK
the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx
register.
If the waveform is left aligned then:
( period – 1 ⁄ fchannel_x_clock × CDTY )
duty cycle = ---------------------------------------------------------------------------------------------------period
If the waveform is center aligned, then:
( ( period ⁄ 2 ) – 1 ⁄ fchannel_x_clock × CDTY ) )
duty cycle = ------------------------------------------------------------------------------------------------------------------( period ⁄ 2 )
the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is
defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can
be used to generate non overlapped waveforms. This property is defined in the CALG field of the
PWM_CMRx register. The default mode is left aligned.
Figure 38-4.
Non Overlapped Center Aligned Waveforms
No overlap
PWM0
PWM1
Period
Note:
1.
See Figure 38-5 for a detailed description of center aligned waveforms.
When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the
period.
When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned
channel.
Waveforms are fixed at 0 when:
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
CDTY = 0 and CPOL = 0
CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.
Changes on channel polarity are not taken into account while the channel is enabled.
902
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 38-5.
Waveform Properties
PWM_MCKx
CHIDx(PWM_SR)
CHIDx(PWM_ENA)
CHIDx(PWM_DIS)
Center Aligned
CALG(PWM_CMRx) = 1
PWM_CCNTx
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
Period
Output Waveform PWMx
CPOL(PWM_CMRx) = 0
Output Waveform PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
Left Aligned
CALG(PWM_CMRx) = 0
PWM_CCNTx
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
Period
Output Waveform PWMx
CPOL(PWM_CMRx) = 0
Output Waveform PWMx
CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
903
38.6.3 PWM Controller Operations
38.6.3.1 Initialization
Before enabling the output channel, this channel must have been configured by the software application:
Configuration of the clock generator if DIVA and DIVB are required
Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx
Register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CUPDx Register to update PWM_CPRDx as explained below.
Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in
PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user
must use PWM_CUPDx Register to update PWM_CDTYx as explained below.
Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
Enable Interrupts (Writing CHIDx in the PWM_IER register)
Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
It is possible to synchronize different channels by enabling them at the same time by means of writing
simultaneously several CHIDx bits in the PWM_ENA register.
In such a situation, all channels may have the same clock selector configuration and the same period
specified.
38.6.3.2 Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the value in the Period
Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event
number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than
1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in
PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
38.6.3.3 Changing the Duty Cycle or the Period
It is possible to modulate the output waveform duty cycle or period.
To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change
waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value
in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and
updates the value for the next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either
updates PWM_CPRDx or PWM_CDTYx. Note that even if the update register is used, the period must not be
smaller than the duty cycle.
904
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 38-6.
Synchronized Period or Duty Cycle Update
User's Writing
PWM_CUPDx Value
1
PWM_CPRDx
0
PWM_CMRx. CPD
PWM_CDTYx
End of Cycle
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his
software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM
Controller level.
The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the
enabled channel(s). See Figure 38-7.
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note:
Reading the PWM_ISR register automatically clears CHIDx flags.
Figure 38-7.
Polling Method
PWM_ISR Read
Acknowledgement and clear previous register state
Writing in CPD field
Update of the Period or Duty Cycle
CHIDx = 1
YES
Writing in PWM_CUPDx
The last write has been taken into account
Note:
Polarity and alignment can be modified only when the channel is disabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
905
38.6.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the
corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is
disabled by setting the corresponding bit in the PWM_IDR register.
906
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.7
Pulse Width Modulation Controller (PWM) User Interface
Table 38-4.
Register Mapping(1)
Offset
Register
Name
Access
Reset
0x00
PWM Mode Register
PWM_MR
Read-write
0
0x04
PWM Enable Register
PWM_ENA
Write-only
-
0x08
PWM Disable Register
PWM_DIS
Write-only
-
0x0C
PWM Status Register
PWM_SR
Read-only
0
0x10
PWM Interrupt Enable Register
PWM_IER
Write-only
-
0x14
PWM Interrupt Disable Register
PWM_IDR
Write-only
-
0x18
PWM Interrupt Mask Register
PWM_IMR
Read-only
0
0x1C
PWM Interrupt Status Register
PWM_ISR
Read-only
0
0x20 - 0xFC
Reserved
–
–
0x100 - 0x1FC
Reserved
0x200 + ch_num * 0x20 + 0x00
PWM Channel Mode Register
PWM_CMR
Read-write
0x0
0x200 + ch_num * 0x20 + 0x04
PWM Channel Duty Cycle Register
PWM_CDTY
Read-write
0x0
0x200 + ch_num * 0x20 + 0x08
PWM Channel Period Register
PWM_CPRD
Read-write
0x0
0x200 + ch_num * 0x20 + 0x0C
PWM Channel Counter Register
PWM_CCNT
Read-only
0x0
0x200 + ch_num * 0x20 + 0x10
PWM Channel Update Register
PWM_CUPD
Write-only
-
Notes:
–
1. Some registers are indexed with “ch_num” index ranging from 0 to 3.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
907
38.7.1 PWM Mode Register
Name:
PWM_MR
Address:
0x48008000
Access:
Read/Write
31
–
30
–
29
–
28
–
27
26
23
22
21
20
19
18
11
10
25
24
17
16
9
8
1
0
PREB
DIVB
15
–
14
–
13
–
12
–
7
6
5
4
PREA
3
2
DIVA
• DIVA, DIVB: CLKA, CLKB Divide Factor
Value
Name
Description
0
CLK_OFF
CLKA, CLKB clock is turned off
1
CLK_DIV1
CLKA, CLKB clock is clock selected by PREA, PREB
2-255
–
CLKA, CLKB clock is clock selected by PREA, PREB
divided by DIVA, DIVB factor.
• PREA, PREB
Value
Name
Description
0000
MCK
Master Clock
0001
MCKDIV2
Master Clock divided by 2
0010
MCKDIV4
Master Clock divided by 4
0011
MCKDIV8
Master Clock divided by 8
0100
MCKDIV16
Master Clock divided by 16
0101
MCKDIV32
Master Clock divided by 32
0110
MCKDIV64
Master Clock divided by 64
0111
MCKDIV128
Master Clock divided by 128
1000
MCKDIV256
Master Clock divided by 256
1001
MCKDIV512
Master Clock divided by 512
1010
MCKDIV1024
Master Clock divided by 1024
Values which are not listed in the table must be considered as “reserved”.
908
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.7.2 PWM Enable Register
Name:
PWM_ENA
Address:
0x48008004
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CHID3
2
CHID2
1
CHID1
0
CHID0
• CHIDx: Channel ID
0 = No effect.
1 = Enable PWM output for channel x.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
909
38.7.3 PWM Disable Register
Name:
PWM_DIS
Address:
0x48008008
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CHID3
2
CHID2
1
CHID1
0
CHID0
• CHIDx: Channel ID
0 = No effect.
1 = Disable PWM output for channel x.
910
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.7.4 PWM Status Register
Name:
PWM_SR
Address:
0x4800800C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CHID3
2
CHID2
1
CHID1
0
CHID0
• CHIDx: Channel ID
0 = PWM output for channel x is disabled.
1 = PWM output for channel x is enabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
911
38.7.5 PWM Interrupt Enable Register
Name:
PWM_IER
Address:
0x48008010
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CHID3
2
CHID2
1
CHID1
0
CHID0
• CHIDx: Channel ID.
0 = No effect.
1 = Enable interrupt for PWM channel x.
912
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.7.6 PWM Interrupt Disable Register
Name:
PWM_IDR
Address:
0x48008014
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CHID3
2
CHID2
1
CHID1
0
CHID0
• CHIDx: Channel ID.
0 = No effect.
1 = Disable interrupt for PWM channel x.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
913
38.7.7 PWM Interrupt Mask Register
Name:
PWM_IMR
Address:
0x48008018
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CHID3
2
CHID2
1
CHID1
0
CHID0
• CHIDx: Channel ID.
0 = Interrupt for PWM channel x is disabled.
1 = Interrupt for PWM channel x is enabled.
914
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.7.8 PWM Interrupt Status Register
Name:
PWM_ISR
Address:
0x4800801C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
CHID3
2
CHID2
1
CHID1
0
CHID0
• CHIDx: Channel ID
0 = No new channel period has been achieved since the last read of the PWM_ISR register.
1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
915
38.7.9 PWM Channel Mode Register
Name:
PWM_CMR[0..3]
Address:
0x48008200 [0], 0x48008220 [1], 0x48008240 [2], 0x48008260 [3]
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
CPD
9
CPOL
8
CALG
7
–
6
–
5
–
4
–
3
2
1
0
CPRE
• CPRE: Channel Pre-scaler
Value
Name
Description
0000
MCK
0001
MCKDIV2
Master Clock divided by 2
0010
MCKDIV4
Master Clock divided by 4
0011
MCKDIV8
Master Clock divided by 8
0100
MCKDIV16
Master Clock divided by 16
0101
MCKDIV32
Master Clock divided by 32
0110
MCKDIV64
Master Clock divided by 64
0111
MCKDIV128
Master Clock divided by 128
1000
MCKDIV256
Master Clock divided by 256
1001
MCKDIV512
Master Clock divided by 512
1010
MCKDIV1024
Master Clock divided by 1024
1011
CLKA
Clock A
1100
CLKB
Clock B
Master Clock
Values which are not listed in the table must be considered as “reserved”.
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
916
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
917
38.7.10 PWM Channel Duty Cycle Register
Name:
PWM_CDTY[0..3]
Address:
0x48008204 [0], 0x48008224 [1], 0x48008244 [2], 0x48008264 [3]
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CDTY
23
22
21
20
CDTY
15
14
13
12
CDTY
7
6
5
4
CDTY
Only the first 16 bits (internal channel counter size) are significant.
• CDTY: Channel Duty Cycle
Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
918
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.7.11 PWM Channel Period Register
Name:
PWM_CPRD[0..3]
Address:
0x48008208 [0], 0x48008228 [1], 0x48008248 [2], 0x48008268 [3]
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CPRD
23
22
21
20
CPRD
15
14
13
12
CPRD
7
6
5
4
CPRD
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
(-----------------------------X × CPRD )MCK
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(----------------------------------------CPRD × DIVA )( CPRD × DIVB )
or -----------------------------------------MCK
MCK
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula will be:
(---------------------------------------2 × X × CPRD )
MCK
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(--------------------------------------------------2 × CPRD × DIVA )
( 2 × CPRD × DIVB )
or --------------------------------------------------MCK
MCK
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
919
38.7.12 PWM Channel Counter Register
Name:
PWM_CCNT[0..3]
Address:
0x4800820C [0], 0x4800822C [1], 0x4800824C [2], 0x4800826C [3]
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CNT
23
22
21
20
CNT
15
14
13
12
CNT
7
6
5
4
CNT
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
920
the channel is enabled (writing CHIDx in the PWM_ENA register).
the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
38.7.13 PWM Channel Update Register
Name:
PWM_CUPD[0..3]
Address:
0x48008210 [0], 0x48008230 [1], 0x48008250 [2], 0x48008270 [3]
Access:
Write-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CUPD
23
22
21
20
CUPD
15
14
13
12
CUPD
7
6
5
4
CUPD
• CUPD: Channel Update Register
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle.
Only the first 16 bits (internal channel counter size) are significant.
When CPD field of PWM_CMRx register = 0, the duty-cycle (CDTY of PWM_CDTYx register) is updated with the CUPD
value at the beginning of the next period.
When CPD field of PWM_CMRx register = 1, the period (CPRD of PWM_CPRDx register) is updated with the CUPD value
at the beginning of the next period.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
921
39.
Segment Liquid Crystal Display Controller (SLCDC)
39.1
Description
The Segment Liquid Crystal Display Controller (SLCDC) can drive a monochrome passive liquid crystal display
(LCD) with up to 6 common terminals and up to 38 segment terminals.
An LCD consists of several segments (pixels or complete symbols) which can be visible or invisible. A segment
has two electrodes with liquid crystal between them. When a voltage above a threshold voltage is applied across
the liquid crystal, the segment becomes visible.
The voltage must alternate to avoid an electrophoresis effect in the liquid crystal, which degrades the display.
Hence the waveform across a segment must not have a DC component.
The SLCDC is programmable to support many different requirements such as:
Adjusting the driving time of the LCD pads in order to save power and increase the controllability of the DC
offset
Driving smaller LCD (down to 1 common by 1 segment)
Adjusting the SLCDC frequency in order to obtain the best compromise between frequency and
consumption and adapt it to the LCD driver
Assigning the segments in a user defined pattern to simplify the use of the digital functions multiplexed on
these pins
Table 39-1.
39.2
List of Terms
Term
Description
LCD
A passive display panel with terminals leading directly to a segment
Segment
The least viewing element (pixel) which can be on or off
Common(s)
Denotes how many segments are connected to a segment terminal
Duty
1/(Number of common terminals on a current LCD display)
Bias
1/(Number of voltage levels used driving an LCD display -1)
Frame Rate
Number of times the LCD segments are energized per second
Embedded Characteristics
The SLCDC provides the following capabilities:
922
Display Capacity: Up to 38 Segments and 6 Common Terminals
Support from Static to 1/6 Duty
Supports: Static and 1/2 and 1/3 Bias
Two LCD Supply Sources:
̶
Internal (On-chip LCD Power Supply)
̶
External
LCD Output Voltage Software Selectable from 2.4V to VDDIN in 16 Steps
(Control Embedded in the Supply Controller)
Flexible Selection of Frame Frequency
Two Interrupt Sources: End Of Frame and Disable
Versatile Display Modes
Equal Source and Sink Capability to Maximize LCD Life Time
Segment and Common Pins not Needed for Driving the Display Can be Used as Ordinary I/O Pins
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
39.3
Segments Layout can be Fully Defined by User to Optimize Usage of Multiplexed Digital Functions
Latching of Display Data Gives Full Freedom in Register Updates
Power Saving Modes for Extremely Low Power Consumption
Block Diagram
Figure 39-1.
SLCDC Block Diagram
SLCK
SLCK/ 8
SLCK/1024
Prescaler
Clock
Multiplexer
PRESC
SLCDC_FRR
SEG0
SEG1
SEG2
Com./Rate Uniformizer
SEG3
/2
/16
SEG4
SEG5
COMSEL
DIV
Divide by 1 to 8
clkslcdc
COMSEL, LPMODE, BIAS
BUFFTIME, LCDBLKFREQ
ENDFRAME
Timing Generation
Buffer_on
User Frame Buffer
A
P
B
B
U
S
Display Frame
Buffer
SLCDC_{L,M}MEMR1
Analog
Switch
Array
LCD COM
Waveform
Generator
SLCDC_{L,M}MEMR0
Output
Decoder
SEG x
(COM->1)
MUX
LCD SEG
Waveform
Generator
SEG45
SEG46
DISPMODE, SEGSEL,LCDn
BIAS
SEG47
SEG48
SLCDC_SMR
SLCDC_DR
LCDn
LCDBLKFREQ, DISPMODE
SLCDC_IER
SLCDC_IDR
SLCDC_IMR
IT
Generation
SLCDC_MR
Analog/Digital
Pad Control
LCDn
SEGSEL
ENA
Analog/Digital
Pad Control
SEG49
to SEGn
pad buffers
COM0
COM1
DISABLE
Analog
Buffers
ENDFRAME
Buffer_on
SLCDC_ISR
SLCDC_CR
COMSEL
ENA
to COMn
pad buffers
on
ENABLE, DISABLE, SWRST
1/3 VDDLCD
COM4
1/2 VDDLCD
COM5
2/3 VDDLCD
2/3 1/3
1/2
COMSEL, SEGSEL
BIAS,BUFFTIME, LPMODE
SLCDC_SR
ENA
VDDLCD
R
R
R
GND
On-chip resistor ladder for 1/3 bias
VDDLCD
R
R
GND
On-chip resistor ladder for 1/2 bias
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
923
39.4
I/O Lines Description
Table 39-2.
39.5
I/O Lines Description
Name
Description
Type
SEG [39:0]
Segments control signals
Output
COM [5:0]
Commons control signals
Output
Product Dependencies
39.5.1 I/O Lines
The pins used for interfacing the SLCD Controller may be multiplexed with PIO lines. Refer to “SAM4CM Series
Block Diagram”.
If I/O lines of the SLCD Controller are not used by the application, they can be used for other purposes by the PIO
Controller.
By default (SLCDC_SMR0/1 registers cleared), the assignment of the segment controls and commons are
automatically done depending on COMSEL and SEGSEL in SLCDC_MR. For example, if 10 segments are
programmed in the SEGSEL field, they are automatically assigned to SEG[9:0] whereas the remaining SEG pins
are automatically selected to be driven by the multiplexed digital functions.
In any case, the user can define a new layout pattern for the segment assignment by programming the
SLCDC_SMR0/1 registers in order to optimize the usage of multiplexed digital function. If at least 1 bit is set in
SLCDC_SMR0/1 registers, the corresponding I/O line is driven by an LCD segment, whereas any cleared bit of
this register selects the corresponding multiplexed digital function.
Table 39-3.
924
I/O Lines
Instance
Signal
I/O Line
Peripheral
SLCDC
COM0
PA0
X1
SLCDC
COM1
PA1
X1
SLCDC
COM2
PA2
X1
SLCDC
COM3
PA3
X1
SLCDC
COM4/AD1
PA4
X1
SLCDC
COM5/AD2
PA5
X1
SLCDC
SEG0
PA6
X1
SLCDC
SEG1
PA7
X1
SLCDC
SEG2
PA8
X1
SLCDC
SEG3
PA9
X1
SLCDC
SEG4
PA10
X1
SLCDC
SEG5
PA11
X1
SLCDC
SEG6/AD0
PA12
X1
SLCDC
SEG7
PA13
X1
SLCDC
SEG8
PA14
X1
SLCDC
SEG9
PA15
X1
SLCDC
SEG10
PA16
X1
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 39-3.
I/O Lines (Continued)
SLCDC
SEG11
PA17
X1
SLCDC
SEG12
PA18
X1
SLCDC
SEG13
PA19
X1
SLCDC
SEG14
PA20
X1
SLCDC
SEG15
PA21
X1
SLCDC
SEG16
PA22
X1
SLCDC
SEG17
PA23
X1
SLCDC
SEG18
PA24
X1
SLCDC
SEG19
PA25
X1
SLCDC
SEG20
PA26
X1
SLCDC
SEG21
PA27
X1
SLCDC
SEG22
PA28
X1
SLCDC
SEG24
PB6
X1
SLCDC
SEG25
PB7
X1
SLCDC
SEG26
PB8
X1
SLCDC
SEG27
PB9
X1
SLCDC
SEG28
PB10
X1
SLCDC
SEG29
PB11
X1
SLCDC
SEG30
PB12
X1
SLCDC
SEG31/AD3
PB13
X1
SLCDC
SEG32
PB14
X1
SLCDC
SEG33
PB15
X1
SLCDC
SEG34
PB16
X1
SLCDC
SEG35
PB17
X1
SLCDC
SEG36
PB18
X1
SLCDC
SEG37
PB19
X1
SLCDC
SEG39
PB21
X1
39.5.2 Power Management
The SLCD Controller is clocked by the slow clock (SLCK). All the timings are based upon a typical value of 32 kHz
for SLCK.
The LCD segment/common pad buffers are supplied by the VDDLCD domain.
39.5.3 Interrupt Sources
The SLCD Controller interrupt line is connected to one of the internal sources of the Interrupt Controller. Using the
SLCD Controller interrupt requires prior programming of the Interrupt Controller.
Table 39-4.
Peripheral IDs
Instance
ID
SLCDC
32
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
925
39.6
Functional Description
The use of the SLCDC comprises three phases of functionality: initialization sequence, display phase, and disable
sequence.
Initialization Sequence:
1. Select the LCD supply source in the shutdown controller
̶
Internal: the On-chip LCD Power Supply is selected,
̶
External: the external supply source has to be between 2.5 to 3.6V
2.
Select the clock division (SLCDC_FRR) to use a proper frame rate
3.
Enter the number of common and segments terminals (SLCDC_MR)
4.
Select the bias in compliance with the LCD manufacturer datasheet (SLCDC_MR)
5.
Enter buffer driving time (SLCDC_MR)
6.
Define the segments remapping pattern if required (SLCDC_SMR0/1)
During the Display Phase:
1. Data may be written at any time in the SLCDC memory, they are automatically latched and displayed at
the next LCD frame
2.
926
It is possible to:
̶
Adjust contrast
̶
Adjust the frame frequency
̶
Adjust buffer driving time
̶
Reduce the SLCDC consumption by entering in low-power waveform at any time
̶
Use the large set of display features such as blinking, inverted blink, etc.
Disable Sequence: See Section 39.6.7 ”Disabling the SLCDC”
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
39.6.1 Clock Generation
39.6.1.1 Block Diagram
Figure 39-2.
Clock Generation Block Diagram
Com./Rate Uniformizer
Prescaler SLCK/8
Clock
Mux
SLCK
/2
Divider (1 to 8)
clkSLCDC
SLCK/1024
/16
PRESC
SLCDC_FRR
clkSLCDC
SLCDC_MR
COMSEL
DIV
Timing Generation
ENDFRAME
LPMODE
COMSEL
COM + SEG Waveform Generator
SEGSEL
LCD COM
Waveform
Generator
LCD SEG
Waveform
Generator
Buffer driving time management
BUFFTIME
Buffer_on
Blinking generator
SLCDC_DR
LCDBLKFREQ
Blink period
39.6.2 Waveform Generation
39.6.2.1 Static Duty and Bias
This kind of display is driven with the waveform shown in Figure 39-3. SEG0 - COM0 is the voltage across a
segment that is on, and SEG1 - COM0 is the voltage across a segment that is off.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
927
Figure 39-3.
Driving an LCD with One Common Terminal
VDDLCD
VDDLCD
SEG0
SEG1
GND
GND
VDDLCD
VDDLCD
COM0
GND
COM0
GND
VDDLCD
SEG0 - COM0
GND
GND
SEG1 - COM0
-VDDLCD
Frame Frame
Frame Frame
39.6.2.2 1/2 Duty and 1/2 Bias
For an LCD with two common terminals (1/2 duty) a more complex waveform must be used to control segments
individually. Although 1/3 bias can be selected, 1/2 bias is most common for these displays. In the waveform
shown in Figure 39-4, SEG0 - COM0 is the voltage across a segment that is on, and SEG0 - COM1 is the voltage
across a segment that is off.
Figure 39-4.
Driving an LCD with Two Common Terminals
VDDLCD
VDDLCD
SEG0
SEG0
GND
GND
VDDLCD
1/ V
2 DDLCD
COM0
VDDLCD
1/ V
2 DDLCD
GND
GND
VDDLCD
1/ V
2 DDLCD
VDDLCD
1/ V
2 DDLCD
SEG0 - COM0
GND
COM1
SEG0 - COM1
GND
-1/ V
2 DDLCD
-1/ V
2 DDLCD
-VDDLCD
-VDDLCD
Frame Frame
Frame Frame
39.6.2.3 1/3 Duty and 1/3 Bias
1/3 bias is usually recommended for an LCD with three common terminals (1/3 duty). In the waveform shown in
Figure 39-5, SEG0 - COM0 is the voltage across a segment that is on and SEG0 - COM1 is the voltage across a
segment that is off.
928
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 39-5.
Driving an LCD with Three Common Terminals
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
SEG0
GND
GND
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
COM0
GND
GND
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
SEG0 - COM0
GND
-1/3VDDLCD
-2/3VDDLCD
-VDDLCD
Frame
COM1
SEG0 - COM1
GND
-1/3VDDLCD
-2/3VDDLCD
-VDDLCD
Frame
SEG0
Frame
Frame
39.6.2.4 1/4 Duty and 1/3 Bias
1/3 bias is optimal for LCD displays with four common terminals (1/4 duty). In the waveform shown in Figure 39-6,
SEG0 - COM0 is the voltage across a segment that is on and SEG0 - COM1 is the voltage across a segment that
is off.
Figure 39-6.
Driving an LCD with Four Common Terminals
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
SEG0
GND
GND
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
COM0
GND
GND
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
SEG0 - COM0
GND
-1/3VDDLCD
-2/3VDDLCD
-VDDLCD
SEG0
COM1
SEG0 - COM1
GND
-1/3VDDLCD
-2/3VDDLCD
Frame
Frame
-VDDLCD
Frame
Frame
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929
39.6.2.5 Low Power Waveform
To reduce toggle activity and hence power consumption, a low power waveform can be selected by writing
LPMODE to one. The default and low power waveform is shown in Figure 39-7 for 1/3 duty and 1/3 bias. For other
selections of duty and bias, the effect is similar.
Figure 39-7.
Default and Low Power Waveform
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
SEG0
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
GND
GND
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
COM0
GND
GND
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
VDDLCD
2/ V
3 DDLCD
1/ V
3 DDLCD
SEG0 - COM0
GND
-1/3VDDLCD
-2/3VDDLCD
SEG0
COM0
SEG0 - COM0
GND
-1/3VDDLCD
-2/3VDDLCD
-VDDLCD
-VDDLCD
Frame
Frame
Frame
Frame
Note: Refer to the LCD specification to verify that low power waveforms are supported.
39.6.2.6 Frame Rate
The Frame Rate register (SLCDC_FRR) enables the generation of the frequency used by the SLCDC. It is done
by a prescaler (division by 8, 16, 32, 64, 128, 256, 512 and 1024) followed by a finer divider (division by 1, 2, 3, 4,
5, 6, 7 or 8).
To calculate the needed frame frequency, the equation below must be used:
fSLCK
f frame = -------------------------------------------------------------( PRESC ⋅ DIV ⋅ NCOM )
where:
fSLCK = slow clock frequency
fframe = frame frequency
PRESC = prescaler value (8, 16, 32, 64, 128, 256, 512 or 1024)
DIV = divider value (1, 2, 3, 4, 5, 6, 7, or 8)
NCOM = depends of number of commons and is defined in Table 39-5.
NCOM is automatically provided by the SLCDC.
For example, if COMSEL is programmed to 0 (1 common terminal on display device), the SLCDC introduces a
divider by 16 so that NCOM = 16. If COMSEL is programmed to 3 (3 common terminals on display device), the
930
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
SLCDC introduces a divider by 5 so that the NCOM remains close to 16 (the frame rate is uniformized whatever
the number of driven commons).
Table 39-5.
NCOM
Number of Commons
NCOM
Uniformizer Divider
1
16
16
2
16
8
3
15
5
4
16
4
5
15
3
6
18
3
39.6.2.7 Buffer Driving Time
Intermediate voltage levels are generated from buffer drivers. The buffers are active for the amount of time
specified by BUFTIME[3:0] in SLCDC_MR, then they are bypassed.
Shortening the drive time reduces power consumption, but displays with high internal resistance or capacitance
may need a longer drive time to achieve sufficient contrast.
Example for bias = 1/3.
Figure 39-8.
Buffer Driving
SLCDC_MR
BUFFTIME
VDDLCD
R
2/3 VDDLCD
R
1/3 VDDLCD
R
39.6.3 Number of Commons, Segments and Bias
It is important to note that the selection of the number of commons, segments and the bias can be programmed
when the SLCDC is disabled.
SAM4CM Series [DATASHEET]
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931
39.6.4 SLCDC memory
Figure 39-9.
Memory Management
COM0 time slot
COM1 time slot
COM2 time slot
COM0
Display data previously
loaded from the user buffer
to the disp buffer
COM1
Load data from the
user buffer to the disp buffer
Display data previously
loaded from the user buffer
to the disp buffer
COM2
Load data from the
user buffer to the disp buffer
Display data previously
loaded from the user buffer
to the disp buffer
Load data from the
user buff to the disp buff
When a bit in the display memory (SLCDC_LMEMRx and SLCDC_MMEMRx registers) is written to one, the
corresponding segment is energized (on), and non-energized when a bit in the display memory is written to zero.
At the beginning of each common, the display buffer is updated. The value of the previous common is latched in
the display memory (its value is transferred from the user buffer to the frame buffer).
The advantages of this solution are:
Ability to access the user buffer at any time in the frame, in any display mode and even in low power
waveform
Ability to change only one pixel without reloading the picture
39.6.5 Display Features
In order to improve the flexibility of SLCDC the following set of display modes are embedded:
Force mode off: all pixels are turned off and the memory content is kept.
Force mode on: all pixels are turned on and the memory content is kept.
Inverted Mode: all pixels are set in the inverted state as defined in SLCDC memory and the memory content
is kept.
Two blinking modes:
̶
̶
932
Standard Blinking mode: all pixels are alternately turned off to the predefined state in SLCDC memory
at LCDBLKFREQ frequency.
Inverted Blinking mode: all pixels are alternately turned off to the predefined opposite state in SLCDC
memory at LCDBLKFREQ frequency.
Buffer Swap mode: all pixels are alternatively assigned to the state defined in the user buffer then to the
state defined in the display buffer.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
39.6.6 Buffer Swap Mode
This mode is used to assign all pixels to two states alternatively without reloading the user buffer at each change.
The means to alternatively display two states is as follows:
1. Initially, the SLCDC must be in Normal mode or in Standard Blinking mode.
2.
Data corresponding to the first pixel state is written in the user buffer (through the SLCDC_MEM registers).
3.
Wait two ENDFRAME events (to be sure that the user buffer is entirely transferred in the display buffer).
4.
SLCDC_DR must be programmed with DISPMODE = 6 (User Buffer Only Load mode). This mode blocks
the automatic transfer from the user buffer to the display buffer.
5.
Wait ENDFRAME event. (The display mode is internally updated at the beginning of each frame.)
6.
Data corresponding to the second pixel state is written in the user buffer (through the SLCDC_MEM
registers). So, now the first pixel state is in the display buffer and the second pixel state is in the user buffer.
7.
SLCDC_DR must be programmed with DISPMODE = 7 (Buffer Swap mode) and LCDBLKFREQ must be
programmed with the required blinking frequency (if not previously done).
Now, each state is alternatively displayed at LCDBLKFREQ frequency.
Except for the phase dealing with the storage of the two display states, the management of the Buffer Swap mode
is the same as the Standard Blinking mode.
39.6.7 Disabling the SLCDC
There are two ways to disable the SLCDC:
By using the SLCDC_CR[LCDDIS] bit (recommended method). In this case, SLCDC configuration and
memory content are maintained.
By using the SWRST (Software Reset) bit that acts like a hardware reset for SLCDC only.
Both methods are described in the following sections.
39.6.7.1 Disable Bit
The LCDDIS bit in the SLCDC_CR can be set at any time. When the LCD Disable Command is activated during a
frame, the SLCDC is not immediately stopped (see Figure 39-10).
The next frame is generated in “All Ground” mode (whereby all commons and segments are tied to ground). At the
end of this “All Ground” frame, the disable interrupt is asserted if the bit DIS is set in the SLCDC_IMR. The SLCDC
is then disabled.
SAM4CM Series [DATASHEET]
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933
Figure 39-10. Disabling Sequence
Disable Example for Three Commons
End of Frame Interrupt
Common
VDDLCD
Commons/segments tied to ground
1/3
GND
-1/3
-VDDLCD
Disable command is activated
Disable Command
Command processing begins
ENA bit
SLCDC Interrupt
SLCDC disabled
39.6.7.2 Software Reset
When the SLCDC software reset command is activated during a frame, it is immediately processed and all
commons and segments are tied to ground.
Note that in the case of a software reset, the disable interrupt is not asserted.
Figure 39-11. Software Reset
SW Reset Example for Three Commons
End Of Frame Interrupt
Common
VDDLCD
The common is immediatly tied to ground
1/3
GND
-1/3
-VDDLCD
SW Reset Command
934
The SW reset command is activated
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
39.6.8 Flowchart
Figure 39-12. SLCDC Flow Chart
START
INITIALIZATION
Supply source (internal or external)
Number of com (COMSEL in SLCDC_MR)
Number of seg (SEGSEL in SLCDC_MR)
Frame rate ((PRESC + DIV) in SLCDC_FRR)
Buff on time (BUFTIME in SLCDC_MR)
Bias (BIAS in SLCDC_MR)
ENABLES THE SLCDC
LCDEN in SLCDC_MR
ENA = 1?
ENA in SLCDC_SR
No
Update the displayed data?
Write the new data in the SLCDC_MEM
No
Update/Change
the display mode?
No
Change/Update the display mode (DISPMODE in SLCDC_DR)
No
Blink?
- Normal mode
- Force off
- Force on
- Inverted mode
Change/Update the blinking frequency (LCDBLKFREQ in SLCDC_DR)
Change/Update the display mode (DISPMODE in SLCDC_DR)
- Blinking mode
- Inverted Blinking mode
Change the power
comsumption ?
No
Enter/Exit from
low-power wave form?
No
No
Change the frame rate ?
LPMODE in SLCDC_MR
PRESC + DIV in SLCDC_FRR
Disable the SLCDC ?
BUFTIME in SLCDC_MR
No
SW reset ?
LCDDIS in SLCDC_CR
Disable interrupt?
DIS in SLCDC_ISR
No
ENA bit = 0?
ENA in SLCDC_SR
No
No
SWRST in SLCDC_CR
END
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935
39.6.9 User Buffer Organization
The pixels to be displayed are written into SLCDC_LMEMRx and SLCDC_MMEMRx registers. There are up to two
32-bit registers for each common terminal. Table 39-6 provides the address mapping of all commons/segments to
be displayed.
If the segment map registers (SLCDC_SMR0/1) are cleared and the number of segments to handle (SEGSEL field
in SLCDC_MR) is lower or equal to 32, the registers SLCDC_MMEMRx are not required to be programmed and
can be left cleared (default value).
In case segments are remapped, the SLCDC_MMEMRx registers are not required to be programmed if
SLCDC_SMR1 register is cleared (i.e., no segment remapped on SEG32 to SEG39 I/O pins). In this case
SLCDC_MMEMRx registers must be cleared.
In the same way if all segments are remapped on the upper part of the SEG terminals (SEG32 to SEG39) there is
no need to program SLCDC_LMEMRx registers (they must be cleared).
When segment remap is used (SLCDC_SMR0/1 registers differ from 0), the unmapped segments must be kept
cleared to limit internal signal switching.
Table 39-6.
Commons/Segments Address Mapping
Register
Common Terminal
SLCDC_MMEMR5
COM5
SLCDC_LMEMR5
COM5
SLCDC_MMEMR4
COM4
SLCDC_LMEMR4
COM4
SLCDC_MMEMR3
COM3
SLCDC_LMEMR3
COM3
SLCDC_MMEMR2
COM2
SLCDC_LMEMR2
COM2
SLCDC_MMEMR1
COM1
SLCDC_LMEMR1
COM1
SLCDC_MMEMR0
COM0
SLCDC_LMEMR0
COM0
SEG0
X
X
X
X
X
X
--
--
--
--
--
--
--
SEG31
SEG32
--
SEG39
Memory address
X
--
X
0x22C
0x228
X
--
X
0x224
0x220
X
--
X
0x21C
0x218
X
--
X
0x214
0x210
X
--
X
0x20C
0x208
X
--
X
0x204
0x200
X
X
X
X
X
X
39.6.10 Segments Mapping Function
By default the segments pins (SEG0:39) are automatically assigned according to the SEGSEL configuration in the
SLCDC_MR. The unused SEG I/O pins are forced to be driven by a digital peripheral or can be used as I/O
through the PIO controller.
The automatic assignment is performed if the segment mapping function is not used (SLCDC_SMR0/1 registers
are cleared). The following table provides such assignments.
Table 39-7.
936
Segment Pin Assignments
SEGSEL
I/O Port in Use as Segment Driver
I/O Port Pin if SLCDC_SMR0/1 = 0
0
SEG0
SEG1:39
1
SEG0:1
SEG2:39
...
...
...
37
SEG0:37
SEG39
39
SEG0:39
None
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Programming is straightforward in this mode but it prevents flexibility of use of the digital peripheral multiplexed on
SEG0:39 especially when the number of segments to drive is close to the maximum (38).
For example, if the SEGSEL is set to 37, only the digital peripheral associated to SEG39 can be used and none of
the other digital peripherals multiplexed on SEG0:37 I/O can be used.
To offer a flexible selection of digital peripherals multiplexed on SEG0:39 the user can manually configure the SEG
I/O pins to be driven by the SLCDC.
This is done by programming the SLCDC_SMR0/1 registers. As soon as their values differ from 0 the Segment
Remapping mode is used.
When configuring a logic 1 at index n (n = 0..39) in SLCDC_SMR0 or SLCDC_SMR0, the SLCDC forces the SEGn
I/O pin to be driven by a segment waveform. In this mode, the SEGSEL field configuration value in SLCDC_MR is
ignored.
In Remapping mode, the software dispatches the pixels into SLCDC_LMEMRx or SLCDC_MMEMRx according to
what is programmed in SLCDC_SMR0 or SLCDC_SMR0.
SAM4CM Series [DATASHEET]
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937
Figure 39-13. Segments Remapping Example
LCD Display Panel
DEFAULT SEGMENT
PINS ASSIGMENTS
com0
com1
seg0
COM0 COM1
Dig0
Dig1
COM5
seg1 seg2 seg3
Dig10
SEG0 SEG1 SEG2 SEG3 SEG4
Dig5
Dig6
Dig7
Dig8
Dig9
Dig10
Dig11 Dig12 Dig13
SEG28 SEG29 SEG30
Dig11 Dig12 Dig13
Unusable Digital Functions
COMSEL=1
LCD Panel Config.
SEGSEL=3
SLCDC_SMR0=0
Default Config.
SLCDC_SMR1=0
SLCDC_LMEMR0=0x5
Direct Image Buffer
SLCDC_LMEMR1=0xA
MICROCONTROLLER
LCD Display Panel
USER REMAPPED
SEGMENT PINS
ASSIGMENTS
com0
com1
seg0
seg1 seg2 seg3
Dig8 Dig9 Dig10
Dig6
COM0 COM1
Dig0
Dig1
COM5
Dig5
SEG0 SEG1 SEG2 SEG3 SEG4
Dig6
Dig7
Dig8
Dig9
Dig10
SEG28 SEG29 SEG30
Dig11 Dig12 Dig13
COMSEL=1
SEGSEL=3
SLCDC_SMR0=0x8000_0002
User Config.
SLCDC_SMR1=0x0000_0003
SLCDC_LMEMR0=0x2
SLCDC_MMEMR0=0x1
Pre-processed Image Buffer
SLCDC_LMEMR1=0x8000_0000
SLCDC_MMEMR1=0x0000_0002
MICROCONTROLLER
39.7
Waveform Specifications
39.7.1 DC Characteristics
Refer to “DC Characteristics” in Section 46. ”Electrical Characteristics”.
39.7.2 LCD Contrast
The peak value (VDDLCD) on the output waveform determines the LCD Contrast. VDDLCD is controlled by software in
16 steps from 2.4V to VDDIN.
This is a function of the supply controller.
938
SAM4CM Series [DATASHEET]
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39.8
Segment LCD Controller (SLCDC) User Interface
Table 39-8.
Register Mapping
Offset
Register
Name
Access
Reset
0x0
SLCDC Control Register
SLCDC_CR
Write-only
–
0x4
SLCDC Mode Register
SLCDC_MR
Read/Write
0x0
0x8
SLCDC Frame Rate Register
SLCDC_FRR
Read/Write
0x0
0xC
SLCDC Display Register
SLCDC_DR
Read/Write
0x0
0x10
SLCDC Status Register
SLCDC_SR
Read-only
0x0
0x20
SLCDC Interrupt Enable Register
SLCDC_IER
Write-only
–
0x24
SLCDC Interrupt Disable Register
SLCDC_IDR
Write-only
–
0x28
SLCDC Interrupt Mask Register
SLCDC_IMR
Read-only
–
0x2C
SLCDC Interrupt Status Register
SLCDC_ISR
Read-only
0x0
0x30
SLCDC Segment Map Register 0
SLCDC_SMR0
Read/Write
0x0
0x34
SLCDC Segment Map Register 1
SLCDC_SMR1
Read/Write
0x0
0x38–0xE4
Reserved
–
–
–
0xE4-0xE8
Reserved
–
–
–
0xEC–0xF8
Reserved
–
–
–
0xFC
Reserved
–
–
–
0x200 + com*0x8 + 0x0
SLCDC LSB Memory Register
SLCDC_LMEMR
Read/Write
0x0
0x200 + com*0x8 + 0x4
SLCDC MSB Memory Register
SLCDC_MMEMR
Read/Write
0x0
SAM4CM Series [DATASHEET]
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939
39.8.1 SLCDC Control Register
Name:
SLCDC_CR
Address:
0x4003C000
Access:
Write-only
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
SWRST
26
–
18
–
10
–
2
–
25
–
17
–
9
–
1
LCDDIS
24
–
16
–
8
–
0
LCDEN
• LCDEN: Enable the LCDC
0: No effect.
1: The SLCDC is enabled.
• LCDDIS: Disable LCDC
0: No effect.
1: The SLCDC is disabled.
Note: LCDDIS is processed at the beginning of the next frame.
• SWRST: Software Reset
0: No effect.
1: Equivalent to a power-up reset. When this command is performed, the SLCDC immediately ties all segments end commons lines to values corresponding to a “ground voltage”.
940
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
39.8.2 SLCDC Mode Register
Name:
SLCDC_MR
Address:
0x4003C004
Access:
Read/Write
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
28
–
20
27
–
19
26
–
18
25
–
17
24
LPMODE
16
10
9
8
2
1
COMSEL
0
BIAS
13
BUFTIME
12
11
SEGSEL
5
–
4
–
3
–
• COMSEL: Selection of the Number of Commons
(For safety reasons, can be configured when SLCDC is disabled)
Value
Name
Description
0x0
COM_0
COM0 is driven by SLCDC, COM1:5 are driven by digital function
0x1
COM_0TO1
COM0:1 are driven by SLCDC, COM2:5 are driven by digital function
0x2
COM_0TO2
COM0:2 are driven by SLCDC, COM3:5 are driven by digital function
0x3
COM_0TO3
COM0:3 are driven by SLCDC, COM4:5 are driven by digital function
0x4
COM_0TO4
COM0:4 are driven by SLCDC, COM5 is driven by digital function
0x5
COM_0TO5
COM0:5 are driven by SLCDC, No COM pin driven by digital function
• SEGSEL: Selection of the Number of Segments
(For safety reasons, can be configured when SLCDC is disabled)
SEGSEL must be programmed with the number of segments of the display panel minus 1.
If segment remapping function is not used (i.e., SLCDC_SMRx equal 0) the SEGn [n = 0..39] I/O pins where n is greater
than SEGSEL are forced to be driven by digital function. When segments remapping function is used, SEGn pins are
driven by SLCDC only if corresponding PIXELn configuration bit is set in SLCDC_SMR1/0 registers.
• BUFTIME: Buffer On-Time
(Processed at beginning of next frame)
Value
Name
Description
0x0
OFF
Nominal drive time is 0% of SLCK period
0x1
X2_SLCK_PERIOD
Nominal drive time is 2 periods of SLCK clock
0x2
X4_SLCK_PERIOD
Nominal drive time is 4 periods of SLCK clock
0x3
X8_SLCK_PERIOD
Nominal drive time is 8 periods of SLCK clock
0x4
X16_SLCK_PERIOD
Nominal drive time is 16 periods of SLCK clock
0x5
X32_SLCK_PERIOD
Nominal drive time is 32 periods of SLCK clock
0x6
X64_SLCK_PERIOD
Nominal drive time is 64 periods of SLCK clock
0x7
X128_SLCK_PERIOD
Nominal drive time is 128 periods of SLCK clock
0x8
PERCENT_50
Nominal drive time is 50% of SLCK period
0x9
PERCENT_100
Nominal drive time is 100% of SLCK period
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
941
• BIAS: LCD Display Configuration
(For safety reasons, can be configured when SLCDC is disabled)
Value
Name
Description
0x0
STATIC
Static
0x1
BIAS_1_2
Bias 1/2
0x2
BIAS_1_3
Bias 1/3
• LPMODE: Low Power Mode
(Processed at beginning of next frame)
0: Normal mode.
1: Low Power Waveform is enabled.
942
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
39.8.3 SLCDC Frame Rate Register
Name:
SLCDC_FRR
Address:
0x4003C008
Access:
Read/Write
31
–
23
–
15
–
7
–
30
–
22
–
14
–
6
–
29
–
21
–
13
–
5
–
28
–
20
–
12
–
4
–
27
–
19
–
11
–
3
–
26
–
18
–
10
2
25
–
17
–
9
DIV
1
PRESC
24
–
16
–
8
0
• PRESC: Clock Prescaler
(Processed at beginning of next frame)
Value
Name
Description
0x0
SLCK_DIV8
Slow clock is divided by 8
0x1
SLCK_DIV16
Slow clock is divided by 16
0x2
SLCK_DIV32
Slow clock is divided by 32
0x3
SLCK_DIV64
Slow clock is divided by 64
0x4
SLCK_DIV128
Slow clock is divided by 128
0x5
SLCK_DIV256
Slow clock is divided by 256
0x6
SLCK_DIV512
Slow clock is divided by 512
0x7
SLCK_DIV1024
Slow clock is divided by 1024
• DIV: Clock Division
(Processed at beginning of next frame)
Value
Name
Description
0x0
PRESC_CLK_DIV1
Clock output from prescaler is divided by 1
0x1
PRESC_CLK_DIV2
Clock output from prescaler is divided by 2
0x2
PRESC_CLK_DIV3
Clock output from prescaler is divided by 3
0x3
PRESC_CLK_DIV4
Clock output from prescaler is divided by 4
0x4
PRESC_CLK_DIV5
Clock output from prescaler is divided by 5
0x5
PRESC_CLK_DIV6
Clock output from prescaler is divided by 6
0x6
PRESC_CLK_DIV7
Clock output from prescaler is divided by 7
0x7
PRESC_CLK_DIV8
Clock output from prescaler is divided by 8
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943
39.8.4 SLCDC Display Register
Name:
SLCDC_DR
Address:
0x4003C00C
Access:
Read/Write
31
30
29
28
27
26
25
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
10
–
9
–
8
7
6
5
–
–
12
11
LCDBLKFREQ
4
3
2
0
–
–
–
–
1
DISPMODE
–
• DISPMODE: Display Mode Register
(Processed at beginning of next frame)
Value
Name
Description
0x0
NORMAL
Normal Mode—Latched data are displayed.
0x1
FORCE_OFF
Force Off Mode—All pixels are invisible. (The SLCDC memory is unchanged.)
0x2
FORCE_ON
Force On Mode—All pixels are visible. (The SLCDC memory is unchanged.)
0x3
BLINKING
Blinking Mode—All pixels are alternately turned off to the predefined state in SLCDC memory
at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
0x4
INVERTED
Inverted Mode—All pixels are set in the inverted state as defined in SLCDC memory. (The
SLCDC memory is unchanged.)
0x5
INVERTED_BLINK
Inverted Blinking Mode—All pixels are alternately turned off to the predefined opposite state
in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
0x6
USER_BUFFER_LOAD
User Buffer Only Load Mode—Blocks the automatic transfer from User Buffer to Display
Buffer.
0x7
BUFFERS_SWAP
Buffer Swap Mode—All pixels are alternatively assigned to the state defined in the User
Buffer, then to the state defined in the Display Buffer at LCDBLKFREQ frequency.
• LCDBLKFREQ: LCD Blinking Frequency Selection
(Processed at beginning of next frame)
Blinking frequency = Frame Frequency/LCDBLKFREQ[7:0].
Note: 0 written in LCDBLKFREQ stops blinking.
944
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
39.8.5 SLCDC Status Register
Name:
SLCDC_SR
Address:
0x4003C010
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
ENA
• ENA: Enable Status (Automatically Set/Reset)
0: The SLCDC is disabled.
1: The SLCDC is enabled.
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945
39.8.6 SLCDC Interrupt Enable Register
Name:
SLCDC_IER
Address:
0x4003C020
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
DIS
–
ENDFRAME
• ENDFRAME: End of Frame Interrupt Enable
0: No effect.
1: Enables the corresponding interrupt.
• DIS: SLCDC Disable Completion Interrupt Enable
0: No effect.
1: Enables the corresponding interrupt.
946
SAM4CM Series [DATASHEET]
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39.8.7 SLCDC Interrupt Disable Register
Name:
SLCDC_IDR
Address:
0x4003C024
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
DIS
–
ENDFRAME
• ENDFRAME: End of Frame Interrupt Disable
0: No effect.
1: Disables the corresponding interrupt.
• DIS: SLCDC Disable Completion Interrupt Disable
0: No effect.
1: Disables the corresponding interrupt.
SAM4CM Series [DATASHEET]
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947
39.8.8 SLCDC Interrupt Mask Register
Name:
SLCDC_IMR
Address:
0x4003C028
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
DIS
–
ENDFRAME
• ENDFRAME: End of Frame Interrupt Mask
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• DIS: SLCDC Disable Completion Interrupt Mask
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
948
SAM4CM Series [DATASHEET]
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39.8.9 SLCDC Interrupt Status Register
Name:
SLCDC_ISR
Address:
0x4003C02C
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
DIS
–
ENDFRAME
• ENDFRAME: End of Frame Interrupt Status
0: No End of Frame occurred since the last read.
1: End of Frame occurred since the last read.
• DIS: SLCDC Disable Completion Interrupt Status
0: The SLCDC is enabled.
1: The SLCDC is disabled.
SAM4CM Series [DATASHEET]
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949
39.8.10 SLCDC Segment Map Register 0
Name:
SLCDC_SMR0
Address:
0x4003C030
Access:
Read/Write
31
30
29
28
27
26
25
24
LCD31
LCD30
LCD29
LCD28
LCD27
LCD26
LCD25
LCD24
23
22
21
20
19
18
17
16
LCD23
LCD22
LCD21
LCD20
LCD19
LCD18
LCD17
LCD16
15
14
13
12
11
10
9
8
LCD15
LCD14
LCD13
LCD12
LCD11
LCD10
LCD9
LCD8
7
6
5
4
3
2
1
0
LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
• LCDx: LCD Segment Mapped on SEGx I/O Pin
(For safety reasons, can be configured when SLCDC is disabled)
0: The corresponding I/O pin is driven either by SLCDC or digital function, depending on the SEGSEL field configuration in
the SLCDC_MR.
1: An LCD segment is driven on the corresponding I/O pin.
950
SAM4CM Series [DATASHEET]
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39.8.11 SLCDC Segment Map Register 1
Name:
SLCDC_SMR1
Address:
0x4003C034
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
LCD49
LCD48
15
14
13
12
11
10
9
8
LCD47
LCD46
LCD45
LCD44
LCD43
LCD42
LCD41
LCD40
7
6
5
4
3
2
1
0
LCD39
LCD38
LCD37
LCD36
LCD35
LCD34
LCD33
LCD32
• LCDx: LCD Segment Mapped on SEGx I/O Pin
(For safety reasons, can be configured when SLCDC is disabled)
0: The corresponding I/O pin is driven either by SLCDC or digital function, depending on the SEGSEL field configuration in
the SLCDC_MR.
1: An LCD segment is driven on the corresponding I/O pin.
SAM4CM Series [DATASHEET]
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951
39.8.12 SLCDC LSB Memory Register
Name:
SLCDC_LMEMRx [x = 0..5]
Address:
0x4003C200 [0], 0x4003C208 [1], 0x4003C210 [2], 0x4003C218 [3], 0x4003C220 [4], 0x4003C228 [5]
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
LPIXEL
23
22
21
20
LPIXEL
15
14
13
12
LPIXEL
7
6
5
4
LPIXEL
• LPIXEL: LSB Pixels Pattern Associated to COMx Terminal
0: The pixel associated to COMx terminal is not visible (if Non-inverted Display mode is used).
1: The pixel associated to COMx terminal is visible (if Non-inverted Display mode is used).
Note: LPIXEL[n] (n = 0..31) drives SEGn terminal.
952
SAM4CM Series [DATASHEET]
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39.8.13 SLCDC MSB Memory Register
Name:
SLCDC_MMEMRx [x = 0..5]
Address:
0x4003C204 [0], 0x4003C20C [1], 0x4003C214 [2], 0x4003C21C [3], 0x4003C224 [4], 0x4003C22C [5]
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
MPIXEL
23
22
21
20
MPIXEL
15
14
13
12
MPIXEL
7
6
5
4
MPIXEL
• MPIXEL: MSB Pixels Pattern Associated to COMx Terminal
0: The pixel associated to COMx terminal is not visible (if Non-inverted Display mode is used).
1: The pixel associated to COMx terminal is visible (if Non-inverted Display mode is used).
Note: MPIXEL[n] (n = 32..39) drives SEGn terminal.
SAM4CM Series [DATASHEET]
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953
40.
Analog-to-Digital Converter (ADC)
40.1
Description
The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. It also integrates
a 6-to-1 analog multiplexer, making possible the analog-to-digital conversions of 6 analog lines. The conversions
extend from 0V to the voltage carried on pin ADVREF or the voltage provided by the internal reference voltage
which can be programmed in the Analog Control register (ADC_ACR). Selection of the reference voltage source is
defined by the ONREF and FORCEREF bits in the Analog Control register (ADC_ACR).
The ADC supports the 8-bit or 10-bit resolution mode. The 8-bit resolution mode prevents using the 16-bit
peripheral DMA transfer into memory when only 8-bit resolution is required by the application. Note that using this
low resolution mode does not increase the conversion rate.
Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
The 11-bit and 12-bit resolution modes are obtained by averaging multiple samples to decrease quantization
noise. For 11-bit mode, four samples are used, giving an effective sample rate of 1/4 of the actual sample
frequency. For 12-bit mode, 16 samples are used, giving an effective sample rate of 1/16th of the actual sample
frequency. This allows conversion speed to be traded for better accuracy.
The last channel is internally connected to a temperature sensor. The processing of this channel can be fully
configured for efficient downstream processing due to the slow frequency variation of the value carried on such a
sensor. The seventh channel is reserved for measurement of VDDBU voltage.
The software trigger or internal triggers from Timer Counter output(s) are configurable.
The main comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a
given range or outside the range. Thresholds and ranges are fully configurable.
The ADC also integrates a Sleep mode and a conversion sequencer, and connects with a PDC channel. These
features reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as startup time and tracking time.
40.2
954
Embedded Characteristics
10-bit Resolution with Enhanced Mode up to 12 Bits
500 K Hz Conversion Rate
Digital Averaging Function Provides Enhanced Resolution Mode up to 12 Bits
On-chip Temperature Sensor Management
Wide Range of Power Supply Operation
Selectable External Voltage Reference or Programmable Internal Reference
Integrated Multiplexer Offering Up to 6 Independent Analog Inputs
Individual Enable and Disable of Each Channel
Hardware or Software Trigger
̶
External Trigger Pin
̶
Timer Counter Outputs (Corresponding TIOA Trigger)
PDC Support
Possibility of ADC Timings Configuration
Two Sleep Modes and Conversion Sequencer
̶
Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels
̶
Possibility of Customized Channel Sequence
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Standby Mode for Fast Wakeup Time Response
̶
40.3
Power Down Capability
Automatic Window Comparison of Converted Values
Register Write Protection
Block Diagram
Figure 40-1.
Analog-to-Digital Converter Block Diagram
Timer
Counter
Channels
RTC
1Hz
ADC Controller
Trigger
Selection
ADC Interrupt
Control
Logic
Interrupt
Controller
ADC Cell
ONREF
ADVREF
FORCEREF
Internal
Voltage
Reference
ADC Clock
System Bus
PDC
VDDIN
Temp.
Sensor
VDDBU
AD-
Analog Inputs
Multiplexed
with I/O lines
AD-
7
6
Peripheral Bridge
User
Interface
Successive
Approximation
Register
Analog-to-Digital
Converter
Bus Clock
APB
PIO
CHx
PMC
AD-
Peripheral Clock
GND
40.4
Signal Description
Table 40-1.
ADC Pin Description
Pin Name
Description
ADVREF
External reference voltage
(1)(2)(3)
AD0 - AD7
Note:
Analog input channels
1. AD7 is not an actual pin; it is internally connected to a temperature sensor.
2. AD6 is not an actual pin; it is internally connected to VDDBU.
3. AD4 and AD5 channels are not wired to I/O lines and thus cannot be measured. In the Channel Enable register
(ADC_CHER), these channels must be kept OFF by ensuring that the bits 4 and 5 are always cleared.
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40.5
Product Dependencies
40.5.1 Power Management
The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller peripheral
clock in the Power Management Controller (PMC) before using the ADC Controller. However, if the application
does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when
necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled.
40.5.2 Interrupt Sources
The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADC
interrupt requires the interrupt controller to be programmed first.
Table 40-2.
Peripheral IDs
Instance
ID
ADC
29
40.5.3 Analog Inputs
The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is
automatically done as soon as the corresponding channel is enabled by writing the Channel Enable register
(ADC_CHER). By default, after reset, the PIO line is configured as a digital input with its pull-up enabled, and the
ADC input is connected to the GND.
40.5.4 Temperature Sensor
The temperature sensor is internally connected to channel index 7 of the ADC.
The temperature sensor provides an output voltage VT that is proportional to the absolute temperature (PTAT). To
activate the temperature sensor, the TEMPON bit in the Temperature Sensor Mode register (ADC_TEMPMR)
must be set. After setting the bit, the startup time of the temperature sensor must be achieved prior to initiating any
measurement.
40.5.5 I/O Lines
The digital input ADTRG is multiplexed with digital functions on the I/O line and the selection of ADTRG is made
using the PIO controller by configuring the I/O Input mode.
The analog inputs ADx are multiplexed with digital functions on the I/O lines. ADx inputs are selected as inputs of
the ADCC when writing a one in the corresponding CHx bit of ADC_CHER and the digital functions are not
selected.
Table 40-3.
I/O Lines
Instance
Signal
I/O Line
Peripheral
ADC
COM4/AD1
PA4
X1
ADC
COM5/AD2
PA5
X1
ADC
SEG6/AD0
PA12
X1
ADC
SEG31/AD3
PB13
X1
40.5.6 Timer Triggers
Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all
of the timer counters may be unconnected.
956
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40.5.7 Conversion Performances
For performance and electrical characteristics of the ADC, see Section 46. ”Electrical Characteristics”.
40.6
Functional Description
40.6.1 Analog-to-digital Conversion
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data
requires tracking clock cycles as defined in the field TRACKTIM of the “ADC Mode Register” (ADC_MR). The ADC
clock frequency is selected in the PRESCAL field of ADC_MR.
The ADC clock frequency is between fperipheral clock/2 if PRESCAL is 0, and fperipheral clock/512 if PRESCAL is set to
255 (0xFF).
PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in
the section “Electrical Characteristics”.
Figure 40-2.
Sequence of ADC Conversions
ADCClock
Trigger event
(Hard or Soft)
Analog cell IOs
ADC_ON
ADC_Start
ADC_eoc
ADC_SEL
CH0
LCDR
CH1
CH2
CH0
CH1
DRDY
Conversion of CH0
Start Up Time
(and tracking of CH0)
Tracking of CH1
Conversion of CH1
Tracking of CH2
40.6.2 Conversion Reference
The conversion is performed on a full range between 0V and the reference voltage. The reference voltage is
defined by the external pin ADVREF, or programmed using the internal reference voltage configured in ADC_ACR.
Analog inputs between these voltages convert to values based on a linear conversion.
40.6.3 Conversion Resolution
The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the LOWRES bit in
ADC_MR. By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully
used. By setting the LOWRES bit, the ADC switches to the lowest resolution and the conversion results can be
read in the lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding
Channel Data register (ADC_CDR) and of the LDATA field in the Last Converted Data register (ADC_LCDR) read
0.
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957
40.6.4 Conversion Results
When a conversion is completed, the resulting 10-bit digital value is stored in ADC_CDRx of the current channel
and in ADC_LCDR. By setting the TAG bit in the Extended Mode register (ADC_EMR), ADC_LCDR presents the
channel number associated with the last converted data in the CHNB field.
The EOCx and DRDY bits in the Interrupt Status register (ADC_ISR) are set. In the case of a connected PDC
channel, DRDY rising triggers a data request. In any case, both EOC and DRDY can trigger an interrupt.
Reading one ADC_CDRx clears the corresponding EOCx bit. Reading ADC_LCDR clears the DRDY bit.
Figure 40-3.
EOCx and DRDY Flag Behavior
Write the ADC_CR
with START = 1
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Read the ADC_LCDR
CHx
(ADC_CHSR)
EOCx
(ADC_ISR)
DRDY
(ADC_ISR)
If ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag
is set in the Overrun Status register (ADC_OVER).
New data converted when DRDY is high sets the GOVRE bit in ADC_ISR.
The OVREx flag is automatically cleared when ADC_OVER is read, and GOVRE flag is automatically cleared
when ADC_ISR is read.
958
SAM4CM Series [DATASHEET]
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Figure 40-4.
EOCx, GOVRE and OVREx Flag Behavior
Trigger event
CH0
(ADC_CHSR)
CH1
(ADC_CHSR)
ADC_LCDR
Undefined Data
ADC_CDR0
Undefined Data
ADC_CDR1
EOC0
(ADC_ISR)
Data B
Data A
Data A
Undefined Data
Data C
Data B
Conversion A
EOC1
(ADC_ISR)
Data C
Conversion C
Conversion B
Read ADC_CDR0
Read ADC_CDR1
GOVRE
(ADC_ISR)
Read ADC_ISR
DRDY
(ADC_ISR)
Read ADC_OVER
OVRE0
(ADC_OVER)
OVRE1
(ADC_OVER)
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, the associated data and the corresponding EOCx and GOVRE flags in ADC_ISR and OVREx flags in ADC_OVER
are unpredictable.
40.6.5 Conversion Triggers
Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is
provided by writing the Control register (ADC_CR) with the START bit at 1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels. The hardware trigger is
selected with the TRGSEL field in ADC_MR. The selected hardware trigger is enabled with the TRGEN bit in
ADC_MR.
The minimum time between two consecutive trigger events must be strictly greater than the duration time of the
longest conversion sequence as configured in ADC_MR, ADC_CHSR and ADC_SEQR1.
If a hardware trigger is selected, the start of a conversion is triggered after a delay which starts at each rising edge
of the selected signal. Due to asynchronous handling, the delay may vary in a range of two peripheral clock
periods to one ADC clock period.
Figure 40-5.
Hardware Trigger Delay
trigger
start
delay
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959
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in
Waveform mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware
logic automatically performs the conversions on the active channels, then waits for a new request. The Channel
Enable (ADC_CHER) and Channel Disable (ADC_CHDR) registers permit the analog channels to be enabled or
disabled independently.
If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the
resulting data buffers should be interpreted accordingly.
40.6.6 Sleep Mode and Conversion Sequencer
The ADC Sleep mode maximizes power saving by automatically deactivating the ADC when it is not being used for
conversions. Sleep mode is selected by setting the SLEEP bit in ADC_MR.
Sleep mode is managed by a conversion sequencer, which automatically processes the conversions of all
channels at lowest power consumption.
This mode can be used when the minimum period of time between two successive trigger events is greater than
the startup period of the ADC. See Section 46.5.17 ”10-bit ADC Characteristics”.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up
time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are
complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are ignored.
The conversion sequencer allows automatic processing with minimum processor intervention and optimized power
consumption. Conversion sequences can be performed periodically using a Timer/Counter output. By using the
PDC, the periodic acquisition of several samples can be processed automatically without processor intervention.
The sequence can be customized by programming ADC_SEQR1 and setting the USEQ bit of ADC_MR. The user
can choose a specific order of channels and can program up to 6 conversions by sequence. The user is free to
create a personal sequence by writing channel numbers in ADC_SEQR1. Not only can channel numbers be
written in any sequence, channel numbers can be repeated several times. When the bit USEQ in ADC_MR is set,
the fields USCHx in ADC_SEQR1 are used to define the sequence. Only enabled USCHx fields are part of the
sequence. Each USCHx field has a corresponding enable, CHx, in ADC_CHER (USCHx field with the lowest x
index is associated with bit CHx of the lowest index).
40.6.7 Comparison Window
The ADC Controller features automatic comparison functions. It compares converted values to a low threshold, a
high threshold or both, depending on the value of the CMPMODE field in the Extended Mode register (ADC_EMR).
The comparison can be done on all channels or only on the channel specified in the CMPSEL field of ADC_EMR.
To compare all channels, the CMPALL bit of ADC_EMR should be set.
Moreover, a filtering option can be set by writing the number of consecutive comparison events needed to raise the
flag. This number can be written and read in the CMPFILTER field of ADC_EMR.
The flag can be read on the COMPE bit of ADC_ISR and can trigger an interrupt.
The high threshold and the low threshold can be read/write in the Compare Window register (ADC_CWR).
If the comparison window is to be used with the LOWRES bit set in ADC_MR, the thresholds do not need to be
adjusted, as the adjustment is done internally. Whether or not the LOWRES bit is set, thresholds must always be
configured in accordance with the maximum ADC resolution.
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40.6.8 ADC Timings
Each ADC has its own minimal startup time that is programmed through the field STARTUP in ADC_MR
A minimal tracking time is necessary for the ADC to guarantee the best converted final value between two channel
selections. This time must be programmed in the TRACKTIM field in ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into
consideration to program a precise value in the TRACKTIM field. See Section 46.5.17 ”10-bit ADC
Characteristics”.
40.6.9 Temperature Sensor
The temperature sensor is internally connected to channel index 7. To enable temperature measurement, the
TEMPON bit must be set in ADC_TEMPMR.
The ADC Controller manages temperature measurement in several ways. The different methods of measurement
depend on the configuration bits TRGEN in ADC_MR and CH7 in ADC_CHSR.
Temperature measurement can be triggered like the other channels by enabling its associated conversion channel
index 7, writing 1 in CH7 of ADC_CHER.
A manual start can only be performed if the TRGEN bit in ADC_MR is cleared. When the START bit in ADC_CR is
set, the temperature sensor channel conversion is scheduled together with the other enabled channels (if any).
The result of the conversion is placed in the ADC_CDR7 register and the associated flag EOC7 is set in ADC_ISR.
If the TRGEN bit is set in ADC_MR, the channel of the temperature sensor is periodically converted together with
other enabled channels. The result is placed inthe registers ADC_LCDR and ADC_CDR7. Thus the temperature
conversion result is part of the Peripheral DMA Controller buffer. The temperature channel can be
enabled/disabled at any time, however this may not be optimal for downstream processing.
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961
Figure 40-6.
Non-optimized Temperature Conversion
ADC_CHSR[TEMP]= 1 and ADC_MR.TRGEN=1
Internal/External
Trigger event
(TRGSEL defined)
C T
ADC_SEL
ADC_CDR[0]
C0
ADC_CDR[TEMP]
ADC_LCDR
C T
T1
T0
T0
C2
C1
C0
T1
C T
C T
C1
T2
T3
C2
C5
C4
C3
T2
C T
T3
T5
T4
C3
T4
C4
T5
Notes: ADC_SEL: Command to the ADC cell
C: Classic ADC Conversion Sequence
T: Temperature Sensor Channel
Assuming ADC_CHSR[0] = 1 and ADC_CHSR[TEMP] = 1
where TEMP is the index of the temperature sensor channel
trig.event1
DMA Buffer
Structure
trig.event2
trig.event3
0
ADC_CDR[0]
DMA Transfer
Base Address (BA)
0
ADC_CDR[TEMP]
BA + 0x02
0
ADC_CDR[0]
BA + 0x04
0
ADC_CDR[TEMP]
BA + 0x06
0
ADC_CDR[0]
BA + 0x08
0
ADC_CDR[TEMP]
BA + 0x0A
The temperature factor has a slow variation rate and is potentially different from other conversion channels. As a
result, the ADC Controller triggers the measurement differently when TEMPON is set in ADC_TEMPMR but CH7
is not set in the ADC_CHSR.
Under these conditions, the measurement is triggered every second by means of an internal trigger generated by
the RTC, always enabled and totally independent of the internal/external triggers. The RTC event will be
processed on the next internal/external trigger event as described in Figure 40-7, "Optimized Temperature
Conversion Combined With Classical Conversions". The internal/external trigger is selected through the TRGSEL
field of ADC_MR.
In this mode of operation, the temperature sensor is only powered for a period of time covering the startup time
and conversion time (refer to Figure 40-8, "Temperature Conversion Only").
Every second, a conversion is scheduled for channel 7 but the result of the conversion is only uploaded in
ADC_CDR7 and not in ADC_LCDR. Therefore there is no change in the structure of the Peripheral DMA Controller
buffer due to the conversion of the temperature channel; only the enabled channels are kept in the buffer. The end
of conversion of the temperature channel is reported by means of EOC7 flag in ADC_ISR.
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Figure 40-7.
Optimized Temperature Conversion Combined With Classical Conversions
ADC_CHSR[TEMP]= 0 and ADC_MR.TRGEN=1
TEMPON=1
1s
Internal RTC
Trigger event
Internal/External
Trigger event
(TRGSEL defined)
C T
ADC_SEL
ADC_CDR[0] &
ADC_LCDR
C0
ADC_CDR[TEMP]
T0
C
C T
C
C2
C1
C
C4
C3
T1
C5
T2
Notes: ADC_SEL: Command to the ADC cell
C: Classic ADC Conversion Sequence
T: Temperature Sensor Channel
Assuming ADC_CHSR[0] = 1
trig.event1
DMA Buffer Structure
trig.event2
trig.event3
DMA Transfer
0
ADC_CDR[0]
Base Address (BA)
0
ADC_CDR[0]
BA + 0x02
0
ADC_CDR[0]
BA + 0x04
If TEMPON=1, TRGEN is disabled and none of the channels are enabled in ADC_CHSR (ADC_CHSR=0), then
only channel 7 is converted at a rate of one conversion per second (see Figure 40-8, "Temperature Conversion
Only").
This mode of operation, when combined with the Sleep mode operation of the ADC Controller, provides a lowpower mode for temperature measurement. This assumes there is no other ADC conversion to schedule at a high
sampling rate, or no other channel to convert.
SAM4CM Series [DATASHEET]
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963
Figure 40-8.
Temperature Conversion Only
ADC_CHSR= 0 and ADC_MR.TRGEN=0
TEMPON=1
1s
Internal RTC
Trigger event
30 us
on
Automatic “On”
Temp. sensor
off
T
ADC_SEL
ADC_CDR[TEMP]
T0
T
T1
T2
Notes: ADC_SEL: Command to the ADC cell
C: Classic ADC Conversion Sequence
T: Temperature Sensor Channel
It is possible to raise a flag only if there is a predefined change in the temperature. The user can define a range of
temperature or a threshold in the Temperature Compare Window register (ADC_TEMPCWR), and the mode of
comparison that can be programmed into the TEMPCMPMOD field into ADC_TEMPMR. These values define how
the TEMPCHG flag is raised in ADC_ISR.
The TEMPCHG flag can be used to generate a temperature-dependent interrupt instead of the end-of-conversion
interrupt. More specifically, the interrupt is generated only if the temperature sensor as measured by the ADC
reports a temperature value below, above, inside or outside programmable thresholds (see “ADC Temperature
Sensor Mode Register”).
In any case, if TEMPON is set, the temperature can be read at anytime in ADC_CDR7 without any specific
software intervention.
40.6.10 VDDBU Measurement
The seventh ADC channel (CH6) of the ADC Controller is reserved for measurement of the VDDBU power supply
pin. For this channel, setting up, starting conversion, and other tasks must be performed the same way as for all
other channels. VDDBU is measured without any attenuation. This means that for VDDBU greater than the voltage
reference applied to the ADC, the digital output clamps to the maximum value.
40.6.11 Enhanced Resolution Mode and Digital Averaging Function
The Enhanced Resolution mode is enabled if LOWRES is cleared in ADC_MR, and the OSR field is set to 1 or 2 in
ADC_EMR. The enhancement is based on a digital averaging function.
FREERUN in ADC_MR must be cleared when digital averaging is used (OSR not equal to 0 in ADC_EMR).
There is no averaging on the last index channel if the measure is triggered by an RTC event (see Section 40.6.9
”Temperature Sensor”).
In Enhanced Resolution mode, the ADC Controller trades conversion speed for quantization noise by averaging
multiple samples, thus providing a digital low-pass filter function.
If 1-bit enhancement resolution is selected (OSR = 1 in ADC_EMR), the ADC real sample rate is the maximum
ADC sample rate divided by 4. Thus, the oversampling ratio is 4.
When the 2-bit enhancement resolution is selected (OSR = 2 in ADC_EMR), the ADC real sample rate is the
maximum ADC sample rate divided by 16 (oversampling ratio is 16).
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The selected oversampling ratio applies to all enabled channels except for the temperature sensor channel when
triggered by an RTC event.
The average result is valid into the ADC_CDRx register (x corresponding to the index of the channel) only if EOCn
flag is set in ADC_ISR and OVREn flag is cleared in ADC_OVER. The average result for all channels is valid in
ADC_LCDR only if DRDY is set and GOVRE is cleared in ADC_ISR.
Note that registers ADC_CDRx are not buffered. Therefore, when an averaging sequence is ongoing, the value in
these registers changes after each averaging sample. However, overrun flags in ADC_OVER rise as soon as the
first sample of an averaging sequence is received. Thus the previous averaged value is not read even if the new
averaged value is not ready.
As a result, when an overrun flag rises in ADC_OVER, the previous unread data is lost. However, the data has not
been overwritten by the new averaged value, as the averaging sequence for this channel may still be on-going.
40.6.11.1 Averaging Function versus Trigger Events
The samples can be defined in different ways for the averaging function depending on the configuration of the
ASTE bit in ADC_EMR and the USEQ bit in ADC_MR.
When USEQ is cleared, there are two ways to generate the averaging through the trigger event. If ASTE is cleared
in ADC_EMR, every trigger event generates one sample for each enabled channel as described in Figure 40-9,
"Digital Averaging Function Waveforms over Multiple Trigger Events". Therefore, four trigger events are requested
to get the result of averaging if OSR = 1.
Figure 40-9.
Digital Averaging Function Waveforms over Multiple Trigger Events
ADC_EMR.OSR=1 ASTE=0, ADC_CHSR[1:0]= 0x3 and ADC_MR.USEQ=0
Internal/External
Trigger event
ADC_SEL
ADC_CDR[0]
0 1
CH0_0
0 1
0i1
0 1
0i2
0 1
0i3
0 1
CH0_1
0i1
Read ADC_CDR[0]
EOC[0]
OVR[0]
ADC_CDR[1]
CH1_0
1i1
1i2
1i3
CH1_1
1i1
Read ADC_CDR[1]
Read ADC_CDR[1]
EOC[1]
ADC_LCDR
CH1_0
CH0_1
CH1_1
DRDY
Read ADC_LCDR
Read ADC_LCDR
Notes: ADC_SEL: Command to the ADC cell
0i1,0i2,0i3, 1i1, 1i2, 1i3 are intermediate results and CH0/1_0/1 are final results of average function.
If ASTE = 1 in ADC_EMR and USEQ = 0 in ADC_MR, then the sequence to be converted, defined in ADC_CHSR,
is automatically repeated n times, where n corresponds to the oversampling ratio defined in the OSR field in
ADC_EMR. As a result, only one trigger is required to obtain the result of the averaging function as described in
Figure 40-9, "Digital Averaging Function Waveforms over Multiple Trigger Events".
SAM4CM Series [DATASHEET]
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965
Figure 40-10. Digital Averaging Function Waveforms on a Single Trigger Event
ADC_EMR.OSR=1, ASTE=1, ADC_CHSR[1:0]= 0x3 and ADC_MR.USEQ=0
Internal/External
Trigger event
ADC_SEL
ADC_CDR[0]
0
CH0_0
1 0 1 0 1
0i1
0i2
0
0 1
0i3
1 0 1
CH0_1
Read ADC_CDR[0]
EOC[0]
ADC_CDR[1]
CH1_0
1i1
1i2 1i3
CH1_1
Read ADC_CDR[1]
EOC[1]
ADC_LCDR
CH0_1
CH1_1
DRDY
Read ADC_LCDR
Notes: ADC_SEL: Command to the ADC cell
0i1,0i2,0i3, 1i1, 1i2, 1i3 are intermediate results and CH0/1_0/1 are final results of average function.
When USEQ is set, the user can define the channel sequence to be converted by configuring ADC_SEQRx and
ADC_CHER so that channels are not interleaved during the averaging period. Under these conditions, a sample is
defined for each end of conversion as shown in Figure 40-11, "Digital Averaging Function Waveforms on Single
Trigger Event, Non-interleaved".
Therefore, if the same channel is configured to be converted four times consecutively, and OSR = 1 in ADC_EMR,
the averaging result is placed in the corresponding channel data register ADC_CDRx and ADC_LCDR for each
trigger event.
In this case, the ADC real sample rate remains the maximum ADC sample rate divided by 4 or 16, depending on
OSR.
When USEQ = 1, ASTE = 1 and OSR is different from 0, it is important to note that the user sequence must follow
a specific pattern. The user sequence must be programmed so that it generates a stream of conversion, where a
given channel is successively converted with an integer multiple depending on the value of OSR. Up to four
channels can be converted in this specific mode.
When OSR = 1, each channel to convert must be repeated four times consecutively in the sequence, so the first
four single bits enabled in ADC_CHSR must have the associated channel index programmed to the same value in
ADC_SEQ1/2. Therefore, for OSR =1 , a maximum of four channels can be converted. The user sequence allows
a maximum of 16 conversions for each trigger event.
When OSR = 2, a channel to convert must be repeated 16 times consecutively in the sequence, so all fields must
be enabled in the ADC_CHSR register, and their associated channel index programmed to the same value in
ADC_SEQ1/2. Therefore, for OSR = 2, only one channel can be converted. The user sequence allows a maximum
of 16 conversions for each trigger event.
OSR = 3 and OSR = 4 are prohibited when USEQ = 1 and ASTE = 1.
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Figure 40-11. Digital Averaging Function Waveforms on Single Trigger Event, Non-interleaved
ADC_EMR.OSR=1, ASTE=1, ADC_CHSR[7:0]=0xFF and ADC_MR.USEQ=1
ADC_SEQ1R = 0x1111_0000
Internal/External
Trigger event
0
ADC_SEL
0 0 0 1
CH0_0 0i1 0i2 0i3
ADC_CDR[0]
0
1 1 1
0 0 0
CH0_1
Read ADC_CDR[0]
EOC[0]
ADC_CDR[1]
CH1_0 1i1 1i2 1i3
CH1_1
Read ADC_CDR[1]
EOC[1]
CH0_1
ADC_LCDR
CH1_1
DRDY
Read ADC_LCDR
Notes: ADC_SEL: Command to the ADC cell
0i1,0i2,0i3, 1i1, 1i2, 1i3 are intermediate results and CH0/1_0/1 are final results of average function.
40.6.11.2 Oversampling Digital Output Range
When an oversampling is performed, the maximum value that can be read on ADC_CDRx or ADC_LCDR is not
the full scale value, even if the maximum voltage is supplied on the analog input. This is due to the digital
averaging algorithm. For example, when OSR = 1, four samples are accumulated and the result is then rightshifted by 1 (divided by 2).
The maximum output value carried on ADC_CDRx or ADC_LCDR depends on the configuration of th field OSR in
ADC_EMR.
Table 40-4.
Oversampling Digital Output Range Values
Resolution
Samples
Shift
Full Scale Value
Maximum Value
8-bit
1
0
255
255
10-bit
1
0
1023
1023
11-bit
4
1
2047
2046
12-bit
16
2
4095
4092
40.6.12 Buffer Structure
The PDC read channel is triggered each time a new data is stored in ADC_LCDR. The same data structure is
repeatedly stored in ADC_LCDR each time a trigger event occurs. Depending on the user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1), the structure differs. Each data read to the PDC buffer, carried on a halfword (16-bit), consists of the last converted data right-aligned. When TAG is set in ADC_EMR, the four most
significant bits carry the channel number, thus simplifying post-processing in the PDC buffer or improved checking
of the PDC buffer integrity.
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967
Figure 40-12. Buffer Structure
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 1
trig.event1
DMA Buffer
Structure
trig.event2
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 0
5
ADC_CDR5
DMA Transfer
Base Address (BA)
6
ADC_CDR6
BA + 0x02
8
ADC_CDR8
BA + 0x04
5
ADC_CDR5
6
trig.event1
0
ADC_CDR5
0
ADC_CDR6
0
ADC_CDR8
BA + 0x06
0
ADC_CDR5
ADC_CDR6
BA + 0x08
0
ADC_CDR6
8
ADC_CDR8
BA + 0x0A
0
ADC_CDR8
5
ADC_CDR5
BA + [(N-1) * 6]
0
ADC_CDR5
6
ADC_CDR6
BA + [(N-1) * 6]+ 0x02
0
ADC_CDR6
8
ADC_CDR8
BA + [(N-1) * 6]+ 0x04
0
ADC_CDR8
DMA Buffer
Structure
trig.event2
trig.eventN
trig.eventN
40.6.13 Register Write Protection
To prevent any single software error from corrupting ADC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the “ADC Write Protection Mode Register” (ADC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the “ADC Write Protection Status
Register” (ADC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the ADC_WPSR.
The following registers can be write-protected:
968
“ADC Mode Register”
“ADC Channel Sequence 1 Register”
“ADC Channel Enable Register”
“ADC Channel Disable Register”
“ADC Temperature Sensor Mode Register”
“ADC Temperature Compare Window Register”
“ADC Extended Mode Register”
“ADC Compare Window Register”
“ADC Analog Control Register”
SAM4CM Series [DATASHEET]
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40.7
Analog-to-Digital Converter (ADC) User Interface
Table 40-5.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
ADC_CR
Write-only
–
0x04
Mode Register
ADC_MR
Read/Write
0x00000000
0x08
Channel Sequence 1 Register
ADC_SEQR1
Read/Write
0x00000000
0x0C
Reserved
–
–
–
0x10
Channel Enable Register
ADC_CHER
Write-only
–
0x14
Channel Disable Register
ADC_CHDR
Write-only
–
0x18
Channel Status Register
ADC_CHSR
Read-only
0x00000000
0x1C
Reserved
–
–
–
0x20
Last Converted Data Register
ADC_LCDR
Read-only
0x00000000
0x24
Interrupt Enable Register
ADC_IER
Write-only
–
0x28
Interrupt Disable Register
ADC_IDR
Write-only
–
0x2C
Interrupt Mask Register
ADC_IMR
Read-only
0x00000000
0x30
Interrupt Status Register
ADC_ISR
Read-only
0x00000000
0x34
Temperature Sensor Mode Register
ADC_TEMPMR
Read/Write
0x00000000
0x38
Temperature Compare Window Register
ADC_TEMPCWR
Read/Write
0x00000000
0x3C
Overrun Status Register
ADC_OVER
Read-only
0x00000000
0x40
Extended Mode Register
ADC_EMR
Read/Write
0x00000000
0x44
Compare Window Register
ADC_CWR
Read/Write
0x00000000
0x50
Channel Data Register 0
ADC_CDR0
Read-only
0x00000000
0x54
Channel Data Register 1
ADC_CDR1
Read-only
0x00000000
...
...
...
ADC_CDR7
Read-only
0x00000000
–
–
–
ADC_ACR
Read/Write
0x00000000
–
–
–
...
0x6C
0x70 - 0x90
0x94
0x98 - 0xE0
...
Channel Data Register 7
Reserved
Analog Control Register
Reserved
0xE4
Write Protection Mode Register
ADC_WPMR
Read/Write
0x00000000
0xE8
Write Protection Status Register
ADC_WPSR
Read-only
0x00000000
0xEC - 0xF8
Reserved
–
–
–
0xFC
Reserved
–
–
–
–
–
–
0x100 - 0x124
Reserved for PDC registers
Note: If an offset is not listed in the table it must be considered as “reserved”.
SAM4CM Series [DATASHEET]
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969
40.7.1 ADC Control Register
Name:
ADC_CR
Address:
0x40038000
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
START
0
SWRST
• SWRST: Software Reset
0: No effect.
1: Resets the ADC simulating a hardware reset.
• START: Start Conversion
0: No effect.
1: Begins analog-to-digital conversion.
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40.7.2 ADC Mode Register
Name:
ADC_MR
Address:
0x40038004
Access:
Read/Write
31
USEQ
30
–
29
–
28
–
27
23
–
22
–
21
–
20
–
19
15
14
13
12
26
25
24
17
16
TRACKTIM
18
STARTUP
11
10
9
8
3
2
TRGSEL
1
0
TRGEN
PRESCAL
7
FREERUN
6
–
5
SLEEP
4
LOWRES
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• TRGEN: Trigger Enable
Value
Name
Description
0
DIS
Hardware triggers are disabled. Starting a conversion is only possible by software.
1
EN
Hardware trigger selected by TRGSEL field is enabled.
• TRGSEL: Trigger Selection
Value
Name
Description
0
ADC_TRIG0
–
1
ADC_TRIG1
Timer Counter Channel 0 Output
2
ADC_TRIG2
Timer Counter Channel 1 Output
3
ADC_TRIG3
Timer Counter Channel 2 Output
4
ADC_TRIG4
Timer Counter Channel 3 Output
5
ADC_TRIG5
Timer Counter Channel 4 Output
6
ADC_TRIG6
Timer Counter Channel 5 Output
7
–
Reserved
• LOWRES: Resolution
Value
Name
Description
0
BITS_10
10-bit resolution. For higher resolution by averaging, refer to Section 40.7.15 ”ADC
Extended Mode Register”.
1
BITS_8
8-bit resolution
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• SLEEP: Sleep Mode
Value
Name
0
NORMAL
1
SLEEP
Description
Normal mode: The ADC core and reference voltage circuitry are kept ON between conversions
Sleep mode: The ADC core and reference voltage circuitry are OFF between conversions
• FREERUN: Free Run Mode
Value
Name
Description
0
OFF
Normal mode
1
ON
Free Run mode: Never wait for any trigger.
Note: FREERUN must be set to 0 when digital averaging is used (OSR differs from 0 in ADC_EMR register).
• PRESCAL: Prescaler Rate Selection
fADC Clock = fperipheral clock/ ((PRESCAL+1) × 2)
• STARTUP: Start Up Time
Value
Name
Description
0
SUT0
0 periods of ADC Clock
1
SUT8
8 periods of ADC Clock
2
SUT16
16 periods of ADC Clock
3
SUT24
24 periods of ADC Clock
4
SUT64
64 periods of ADC Clock
5
SUT80
80 periods of ADC Clock
6
SUT96
96 periods of ADC Clock
7
SUT112
112 periods of ADC Clock
8
SUT512
512 periods of ADC Clock
9
SUT576
576 periods of ADC Clock
10
SUT640
640 periods of ADC Clock
11
SUT704
704 periods of ADC Clock
12
SUT768
768 periods of ADC Clock
13
SUT832
832 periods of ADC Clock
14
SUT896
896 periods of ADC Clock
15
SUT960
960 periods of ADC Clock
• TRACKTIM: Tracking Time
Tracking Time = (TRACKTIM + 1) × ADC Clock periods
972
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• USEQ: User Sequence Enable
Value
Name
Description
0
NUM_ORDER
Normal mode: The controller converts channels in a simple numeric order depending only on the
channel index.
1
REG_ORDER
User Sequence mode: The sequence respects what is defined in ADC_SEQR1 and can be used to
convert the same channel several times.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
973
40.7.3 ADC Channel Sequence 1 Register
Name:
ADC_SEQR1
Address:
0x40038008
Access:
Read/Write
31
30
29
28
27
26
–
23
22
21
20
19
18
USCH6
15
14
13
6
24
17
16
9
8
1
0
USCH5
12
11
10
USCH4
7
25
–
USCH3
5
4
USCH2
3
2
USCH1
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the channel number CHy where y is the value written in this
field. The allowed range is 0 up to 7. So it is only possible to use the sequencer from CH0 to CH7.
This register activates only if ADC_MR(USEQ) field is set to 1.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical 1; else any value written in
USCHx does not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, depending on user needs.
974
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.4 ADC Channel Enable Register
Name:
ADC_CHER
Address:
0x40038010
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
CH7
6
CH6
5
–
4
–
3
CH3
2
CH2
1
CH1
0
CH0
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• CHx: Channel x Enable
0: No effect.
1: Enables the corresponding channel.
Note: If USEQ = 1 in ADC_MR, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
975
40.7.5 ADC Channel Disable Register
Name:
ADC_CHDR
Address:
0x40038014
Access:
Write-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
CH7
6
CH6
5
–
4
–
3
CH3
2
CH2
1
CH1
0
CH0
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• CHx: Channel x Disable
0: No effect.
1: Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, the associated data and corresponding EOCx and GOVRE flags in ADC_ISR and OVREx flags in ADC_OVER are
unpredictable.
976
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.6 ADC Channel Status Register
Name:
ADC_CHSR
Address:
0x40038018
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
CH7
6
CH6
5
–
4
–
3
CH3
2
CH2
1
CH1
0
CH0
• CHx: Channel x Status
0: The corresponding channel is disabled.
1: The corresponding channel is enabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
977
40.7.7 ADC Last Converted Data Register
Name:
ADC_LCDR
Address:
0x40038020
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
14
13
12
11
10
9
8
1
0
CHNB
7
6
LDATA
5
4
3
2
LDATA
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
• CHNB: Channel Number
Indicates the last converted channel when the TAG option is set to 1 in ADC_EMR. If the TAG option is not set, CHNB = 0.
978
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.8 ADC Interrupt Enable Register
Name:
ADC_IER
Address:
0x40038024
Access:
Write-only
31
–
30
–
29
–
28
RXBUFF
27
ENDRX
26
COMPE
25
GOVRE
24
DRDY
23
–
22
–
21
–
20
–
19
TEMPCHG
18
–
17
–
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
EOC7
6
EOC6
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• EOCx: End of Conversion Interrupt Enable x
• TEMPCHG: Temperature Change Interrupt Enable
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• COMPE: Comparison Event Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
979
40.7.9 ADC Interrupt Disable Register
Name:
ADC_IDR
Address:
0x40038028
Access:
Write-only
31
–
30
–
29
–
28
RXBUFF
27
ENDRX
26
COMPE
25
GOVRE
24
DRDY
23
–
22
–
21
–
20
–
19
TEMPCHG
18
–
17
–
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
EOC7
6
EOC6
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• EOCx: End of Conversion Interrupt Disable x
• TEMPCHG: Temperature Change Interrupt Disable
• DRDY: Data Ready Interrupt Disable
• GOVRE: General Overrun Error Interrupt Disable
• COMPE: Comparison Event Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
980
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.10 ADC Interrupt Mask Register
Name:
ADC_IMR
Address:
0x4003802C
Access:
Read-only
31
–
30
–
29
–
28
RXBUFF
27
ENDRX
26
COMPE
25
GOVRE
24
DRDY
23
–
22
–
21
–
20
–
19
TEMPCHG
18
–
17
–
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
EOC7
6
EOC6
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
• EOCx: End of Conversion Interrupt Mask x
• TEMPCHG: Temperature Change Interrupt Mask
• DRDY: Data Ready Interrupt Mask
• GOVRE: General Overrun Error Interrupt Mask
• COMPE: Comparison Event Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
981
40.7.11 ADC Interrupt Status Register
Name:
ADC_ISR
Address:
0x40038030
Access:
Read-only
31
–
30
–
29
–
28
RXBUFF
27
ENDRX
26
COMPE
25
GOVRE
24
DRDY
23
–
22
–
21
–
20
–
19
TEMPCHG
18
–
17
–
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
EOC7
6
EOC6
5
–
4
–
3
EOC3
2
EOC2
1
EOC1
0
EOC0
• EOCx: End of Conversion x (automatically set/cleared)
0: The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the
corresponding ADC_CDRx registers.
1: The corresponding analog channel is enabled and conversion is complete.
• TEMPCHG: Temperature Change (cleared on read)
0: There is no comparison match (defined in ADC_TEMPCWR) since the last read of ADC_ISR.
1: The temperature value reported on ADC_CDR7 has changed since the last read of ADC_ISR, according to what is
defined in ADC_TEMPMR and ADC_TEMPCWR.
• DRDY: Data Ready (automatically set/cleared)
0: No data has been converted since the last read of ADC_LCDR.
1: At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error (cleared on read)
0: No general overrun error occurred since the last read of ADC_ISR.
1: At least one general overrun error has occurred since the last read of ADC_ISR.
• COMPE: Comparison Event (cleared on read)
0: No comparison event since the last read of ADC_ISR.
1: At least one comparison event (defined in ADC_EMR and ADC_CWR) has occurred since the last read of ADC_ISR.
• ENDRX: End of Receive Transfer (automatically set/cleared)
0: The Receive Counter Register has not reached 0 since the last write in ADC_RCR(1) or ADC_RNCR(1).
1: The Receive Counter Register has reached 0 since the last write in ADC_RCR(1) or ADC_RNCR(1).
• RXBUFF: Receive Buffer Full (automatically set/cleared)
0: ADC_RCR(1) or ADC_RNCR(1) has a value other than 0.
1: Both ADC_RCR(1) and ADC_RNCR(1) have a value of 0.
Note:
982
1. ADC_RCR and ADC_RNCR are PDC registers.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.12 ADC Temperature Sensor Mode Register
Name:
ADC_TEMPMR
Address:
0x40038034
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
4
TEMPCMPMOD
3
–
2
–
1
–
0
TEMPON
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• TEMPON: Temperature Sensor ON
0: The temperature sensor is not enabled.
1: The temperature sensor is enabled and the measurements are triggered.
• TEMPCMPMOD: Temperature Comparison Mode
Value
Name
Description
0
LOW
Generates an event when the converted data is lower than the low threshold of the window.
1
HIGH
Generates an event when the converted data is higher than the high threshold of the window.
2
IN
3
OUT
Generates an event when the converted data is in the comparison window.
Generates an event when the converted data is out of the comparison window.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
983
40.7.13 ADC Temperature Compare Window Register
Name:
ADC_TEMPCWR
Address:
0x40038038
Access:
Read/Write
31
–
30
–
29
–
28
–
23
22
21
15
–
14
–
7
6
27
26
25
THIGHTHRES
24
20
19
THIGHTHRES
18
17
16
13
–
12
–
10
9
8
5
4
1
0
11
TLOWTHRES
3
2
TLOWTHRES
This register can only be written if the WPEN bit is cleared in the “ADC Write Protection Mode Register”.
• TLOWTHRES: Temperature Low Threshold
Low threshold associated to compare settings of ADC_TEMPMR.
• THIGHTHRES: Temperature High Threshold
High threshold associated to compare settings of ADC_TEMPMR.
984
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.14 ADC Overrun Status Register
Name:
ADC_OVER
Address:
0x4003803C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
OVRE7
6
OVRE6
5
–
4
–
3
OVRE3
2
OVRE2
1
OVRE1
0
OVRE0
• OVREx: Overrun Error x
0: No overrun error on the corresponding channel since the last read of ADC_OVER.
1: There has been an overrun error on the corresponding channel since the last read of ADC_OVER.
Note: An overrun error does not always mean that the unread data has been replaced by a new valid data. Refer to Section 40.6.11
”Enhanced Resolution Mode and Digital Averaging Function” for details.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
985
40.7.15 ADC Extended Mode Register
Name:
ADC_EMR
Address:
0x40038040
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
23
–
22
–
21
–
20
ASTE
19
–
18
–
17
15
–
14
–
13
12
11
–
10
–
9
CMPALL
8
–
7
6
4
3
–
2
–
1
0
CMPFILTER
5
CMPSEL
24
TAG
16
OSR
CMPMODE
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• CMPMODE: Comparison Mode
Value
Name
Description
0
LOW
Generates an event when the converted data is lower than the low threshold of the window.
1
HIGH
Generates an event when the converted data is higher than the high threshold of the window.
2
IN
3
OUT
Generates an event when the converted data is in the comparison window.
Generates an event when the converted data is out of the comparison window.
• CMPSEL: Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
• CMPALL: Compare All Channels
0: Only the channel indicated in CMPSEL field is compared.
1: All channels are compared.
• CMPFILTER: Compare Event Filtering
Number of consecutive compare events necessary to raise the flag = CMPFILTER+1.
When programmed to 0, the flag rises as soon as an event occurs.
• OSR: Over Sampling Rate
Value
Name
Description
0
NO_AVERAGE
1
OSR4
1-bit enhanced resolution by averaging. ADC sample rate divided by 4.
2
OSR16
2-bit enhanced resolution by averaging. ADC sample rate divided by 16.
No averaging. ADC sample rate is maximum.
This field is active if LOWRES is cleared in ADC_MR.
Note: FREERUN (see “ADC Mode Register”) must be set to 0 when digital averaging is used.
986
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• ASTE: Averaging on Single Trigger Event
Value
Name
Description
0
MULTI_TRIG_AVERAGE
The average requests several trigger events.
1
SINGLE_TRIG_AVERAGE
The average requests only one trigger event.
• TAG: TAG of the ADC_LDCR register
0: Sets CHNB to zero in ADC_LDCR.
1: Appends the channel number to the conversion result in ADC_LDCR.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
987
40.7.16 ADC Compare Window Register
Name:
ADC_CWR
Address:
0x40038044
Access:
Read/Write
31
–
30
–
29
–
28
–
23
22
21
20
27
26
25
24
17
16
9
8
1
0
HIGHTHRES
19
18
11
10
HIGHTHRES
15
–
14
–
13
–
12
–
7
6
5
4
LOWTHRES
3
2
LOWTHRES
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• LOWTHRES: Low Threshold
Low threshold associated to compare settings of ADC_EMR.
If LOWRES is set in ADC_MR, only the 10 LSB of LOWTHRES must be programmed. The 2 LSBs are automatically discarded to match the value carried on ADC_CDR (8-bit).
• HIGHTHRES: High Threshold
High threshold associated to compare settings of ADC_EMR.
If LOWRES is set in ADC_MR, only the 10 LSB of HIGHTHRES must be programmed. The 2 LSBs are automatically discarded to match the value carried on ADC_CDR (8-bit).
988
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.17 ADC Channel Data Register
Name:
ADC_CDRx [x=0..7]
Address:
0x40038050
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
10
9
8
7
6
5
4
1
0
DATA
3
2
DATA
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. ADC_CDRx is only loaded if the corresponding analog channel is enabled.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
989
40.7.18 ADC Analog Control Register
Name:
ADC_ACR
Address:
0x40038094
Access:
Read/Write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
ONREF
19
FORCEREF
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
5
4
3
2
IRVCE
1
–
0
–
IRVS
This register can only be written if the WPEN bit is cleared in “ADC Write Protection Mode Register”.
• IRVCE: Internal Reference Voltage Change Enable
0 (STUCK_AT_DEFAULT): The internal reference voltage is stuck at the default value (see Section 46. ”Electrical Characteristics” for further details).
1 (SELECTION): The internal reference voltage is defined by field IRVS.
• IRVS: Internal Reference Voltage Selection
See Table 46-44 “Programmable Voltage Reference Selection Values” for further details.
• FORCEREF: Force Internal Reference Voltage
0: The internal ADC voltage reference input is connected to the ADVREF line
1: The internal ADC voltage reference input is forced to VDDIO (ONREF must be cleared).
• ONREF: Internal Voltage Reference ON
0: The programmable voltage reference is OFF. The user can either force the internal ADC voltage reference input on the
ADVREF pin or set the FORCEREF bit to connect VDDIO to the internal ADC voltage reference input.
1: The programmable voltage reference is ON and its output is connected both to the ADC voltage reference input and to
the external ADVREF pin for decoupling (FORCEREF must be cleared).
990
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
40.7.19 ADC Write Protection Mode Register
Name:
ADC_WPMR
Address:
0x400380E4
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
WPKEY
23
22
21
20
WPKEY
15
14
13
12
WPKEY
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
WPEN
• WPEN: Write Protect Enable
0: Disables the write protection if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
1: Enables the write protection if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
See Section 40.6.13 ”Register Write Protection” for the list of registers that can be protected.
• WPKEY: Write Protect Key
Value
Name
0x414443
PASSWD
Description
Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
991
40.7.20 ADC Write Protection Status Register
Name:
ADC_WPSR
Address:
0x400380E8
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
11
10
9
8
WPVSRC
15
14
13
12
WPVSRC
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
WPVS
• WPVS: Write Protection Violation Status
0: No write protection violation has occurred since the last read of the ADC_WPSR register.
1: A write protection violation has occurred since the last read of the ADC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.
992
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
41.
Energy Metering Analog Front End (EMAFE)
41.1
Description
The Energy Metering Analog Front End peripheral (EMAFE) embeds four or seven high-resolution Sigma-Delta
Analog-to-Digital Converters followed by SINC decimation filters running at an output data rate of 16kS/s. The two
or four current measurement channels feature a low noise programmable gain amplifier to accommodate any type
of current sensor configured in any type of IEC/ANSI-C application. One of these channels is dedicated to neutral
current measurement to implement anti-tamper functions.
The EMAFE also embeds a high-performance voltage reference and a die temperature sensor. The temperature
characteristics of these functions are measured during manufacturing and stored in an internal read-only memory.
A low-cost and efficient voltage reference temperature correction can then be implemented at software level.
41.2
Embedded Characteristics
Single-phase, Two-phase or Three-phase Energy Metering Analog Front End
Works with the Atmel MCU Metrology Library
Compliant with Class 0.2 standards (ANSI C12.20-2002 and IEC 62053-22)
Acquisition Channels
̶
Four or Seven Sigma-Delta ADC Measurement Channels: Two or Three Voltages, Two or Four
Currents, 20-bit Resolution - 102 dB Dynamic Range
̶
Current Channels with Pre-Gain (x1, x2, x4, x8)
̶
Supports Shunt, Current Transformer and Rogowsky Coils
̶
Direct Connection of Sensors Without External Preamplifier
̶
Dedicated Current Channel for Anti-tamper Measurement
̶
Integrated SINC Decimation Filters. Output Data Rate: 16kSps
Precision Voltage Reference
̶
̶
Standard 1.2V Output Voltage With Possible External Bypass
Temperature Drift: 10 ppm Typical With Software Correction
Factory-measured Temperature Drift and On-board Temperature Sensor to Perform Software Correction
Integrated 2.8V LDO Regulator To Supply Analog Functions
3.0V to 3.6V Operation, Ultra-Low-Power at < 2.5mW per Channel @3.3V
Specified Over TJ: -40°C to +100°C
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
993
41.3
Block Diagram
Functional Block Diagram for Three-Phase EMAFE
VD
D
G A
N
D
VR A
EF
_A
FE
Figure 41-1.
VDDA
VP3
ΣΔ ADC
VN
VD
D
G A
N
D
VR A
EF
_A
FE
Decimator
VDDIN_AFE
Decimator
ΣΔ ADC
PGA
2.8V
LDO
ADCI3
IP3
Die
Temperature
sensor
VD
D
G A
N
D
VR A
EF
_A
FE
IN3
GNDA
ADCV3
Voltage VREF_AFE
Reference 1k
GNDREF
VTEMP
VP2
ΣΔ ADC
VN
VD
D
G A
N
D
VR A
EF
_A
FE
Decimator
Decimator
ΣΔ ADC
PGA
APB
ADCI2
IP2
EMAFE
Interface
Peripheral
Clock
Interrupt
VD
D
G A
N
D
VR A
EF
_A
FE
IN2
ADCV2
VP1
ΣΔ ADC
VN
ADCV1
VD
D
G A
N
D
VR A
EF
_A
FE
Decimator
ADCI1
IP1
Decimator
ΣΔ ADC
PGA
D
G A
N
D
VR A
EF
_A
FE
IN1
VD
IP0
ADCI0
IN0
DIFF
MUX
2:1
PGA
ΣΔ ADC
Decimator
VTEMP
EMAFE 7-Ch
994
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Functional Block Diagram for Two-Phase EMAFE
VDDIN_AFE
2.8V
LDO
VDDA
VD
D
G A
N
D
VR A
EF
_A
FE
Die
Temperature
sensor
Voltage
Reference
VTEMP
GNDA
1k
VREF_AFE
GNDREF
VP1
ΣΔ ADC
VN
VD
D
G A
N
D
VR A
EF
_A
FE
Decimator
ADCI1
IP1
PGA
IN1
ADCV1
Decimator
ΣΔ ADC
APB
VD
D
G A
N
D
VR A
EF
_A
FE
EMAFE
Interface
VP2
ΣΔ ADC
Decimator
ADCV2
Interrupt
FE
VN
Peripheral
Clock
VD
D
G A
N
D
VR A
EF
_A
Figure 41-2.
IP0
ADCI0
IN0
DIFF
MUX
2:1
PGA
ΣΔ ADC
Decimator
VTEMP
EMAFE 4-Ch
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
995
41.4
Signal Description
Table 41-1.
Pin Name
Signal Description
I/O
Type
Function
VP1
Input
Analog
Voltage channel 1, positive input
VP2
Input
Analog
Voltage channel 2, positive input
VP3(1)
Input
Analog
Voltage channel 3, positive input
VN
Input
Analog
Voltage channel 1, negative input
IP0
Input
Analog
Current channel 0 (Tamper), positive input
IN0
Input
Analog
Current channel 0 (Tamper), negative input
IP1
Input
Analog
Current channel 1, positive input
IN1
Input
Analog
Current channel 1, negative input
(1)
Input
Analog
Current channel 2, positive input
(1)
IN2
Input
Analog
Current channel 2, negative input
IP3(1)
Input
Analog
Current channel 3, positive input
(1)
Input
Analog
Current channel 3, negative input
Input/Output
Analog
Voltage reference output and reference buffer input
IP2
IN3
VREF_AFE
Ground
Ground
Voltage reference ground pin
VDDA
GNDREF
Input/Output
Analog
2.8V LDO output and analog circuits power supply input
GNDA
Ground
Ground
Ground pin for low noise analog circuits and low-noise negative ADC
reference
Input
Power
2.8V LDO power supply input pin
VDDIN_AFE
Note:
996
1. Only in 7-channel EMAFE.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Application Block Diagram
Typical Three-Phase Application Block Diagram
L1
L2
L3
N
VD
D
G A
N
D
VR A
EF
_A
FE
Figure 41-3.
165k (x10)
2.2k
C.T
2000:1
3.3nF
1μF
ΣΔ ADC
VN
Decimator
VD
D
G A
N
D
VR A
EF
_A
FE
1k
VDDA
VP3
3k
1.5
3.3nF
1.5
3.3nF
IP3
PGA
IN3
GNDA
ADCV3
2.8V
LDO
ADCI3
Die
Temperature
sensor
VD
D
G A
N
D
VR A
EF
_A
FE
2.2k
1k
ΣΔ ADC
Decimator
VD
D
G A
N
D
VR A
EF
_A
FE
3.3nF
1.5
3.3nF
1μF
GNDREF
VP2
3.3nF
3k
1.5
VREF_AFE
Voltage
Reference 1k
VTEMP
VN
C.T
2000:1
VDDIO
3.3V
Decimator
ΣΔ ADC
3k
165k (x10)
VDDIN_AFE
IP2
PGA
IN2
ADCV2
APB
ADCI2
EMAFE
Interface
Decimator
ΣΔ ADC
Peripheral
Clock
Interrupt
3k
VD
D
G A
N
D
VR A
EF
_A
FE
165k (x10)
2.2k
1k
C.T
2000:1
VP1
ΣΔ ADC
3.3nF VN
Decimator
VD
D
G A
N
D
VR A
EF
_A
FE
3k
IP1
1.5
3.3nF
1.5
3.3nF
PGA
IN1
ADCV1
ADCI1
Decimator
ΣΔ ADC
3k
3k
VD
D
G A
N
D
VR A
EF
_A
FE
41.5
IP0
3.3nF
Shunt
150μR
ADCI0
IN0
3.3nF
3k
DIFF
MUX
2:1
PGA
ΣΔ ADC
Decimator
VTEMP
EMAFE 7-Ch
Example Application Diagram for EMAFE in a
Typical 200A (Imax), 3-phase, 4-wire Smart Meter
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
997
Figure 41-4.
Typical Single-phase Application Block Diagram
VDD 3.3V
VDDIN_AFE
2.8V
LDO
N
1μF
Voltage
Reference
VD
D
G A
N
D
VR A
EF
_A
FE
L
VDDA
Die
Temperature
sensor
165k (x10)
1k
GNDA
1k VREF_AFE
VTEMP
3.3nF
GNDREF
1μF
VP1
VN
Decimator
ADCV1
C.T
2000:1
VD
D
G A
N
D
VR A
EF
_A
FE
2.2k
ΣΔ ADC
3.3k
ADCI1
IP1
1.5
3.3nF
1.5
3.3nF
ΣΔ ADC
PGA
IN1
Decimator
VD
D
G A
N
DA
VR
EF
_
AF
E
APB
3.3k
EMAFE
Interface
VP2
VN
ΣΔ ADC
Decimator
Interrupt
D
G A
N
D
VR A
EF
_A
FE
3.3k
VD
IP0
3.3nF
Shunt
150uR
ADCV2
Peripheral
Clock
ADCI0
IN0
3.3nF
3.3k
DIFF
MUX
2:1
PGA
ΣΔ ADC
Decimator
VTEMP
EMAFE 4-Ch
Example Application Diagram for EMAFE in a
Typical 100A (Imax), single-phase with anti-tamper Smart Meter
41.6
Functional Description
41.6.1 Conversion Channels
The EMAFE has three types of acquisition channels:
Voltage channels
Current channels
Tamper and temperature channel
All these channels are built around the same Sigma-Delta A/D converter. The voltage reference of this converter is
the VREF_AFE pin voltage referred to ground (GNDA pin). This reference voltage can be internally or externally
sourced. The converter’s sampling rate is EMAFE_CLK/4, typically 1.024 MHz. An external low-pass filter,
typically a passive R-C network, is required at each ADC input to reject frequency images around this sampling
frequency (anti-alias).
The EMAFE analog inputs are designed to sample 0V centered signals. As these inputs have internal ESD
protection devices connected to GNDA, the maximum input signal level defined in the electrical characteristics
must be respected to avoid leakages in these devices. This is typically ±0.25V. Refer to Figure 41-5.
998
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 41-5.
Analog Inputs: Recommended Input Range
VDDA
+0.25V
E.S.D
IPx
V(IPx,GND)
(0.5Vpp)
E.S.D
-0.25V
GNDA
+0.5V
V(IPx,VINx)
(1Vpp)
VDDA
+0.25V
-0.5V
“Current”
Acquisition
Channel
E.S.D
INx
V(INx,GND)
(0.5Vpp)
E.S.D
-0.25V
GNDA
VDDA
+0.25V
E.S.D
VPx
V(VPx,GND)
(0.5Vpp)
E.S.D
-0.25V
GNDA
+0.25V
V(VPx,VN)
(0.5Vpp)
VDDA
-0.25V
“Voltage”
Acquisition
Channel
E.S.D
VN
GND
E.S.D
GNDA
Voltage channels have single-ended inputs referred to the VN pin. This pin must be connected to a low noise
ground. The user must take care that no voltage drop on the ground net is sampled by the ADC by non-optimum
connection of the VN pin.
Current channels and the tamper channel have a programmable gain amplifier (PGA) to accommodate low input
signals. The PGA improves the dynamic range of the channel as the input referred noise is reduced when gain
increases. The PGA does not introduce any delay or bandwidth limitation on the current channels compared to the
voltage channels. The channels (voltage or current) are always sampled synchronously. The input impedance of
the PGA depends on the programmed gain.
The tamper channel features an input multiplexer to perform both the neutral current measurement and the die
temperature measurement. The tamper channel has a PGA to accommodate low output level current sensors.
Programmed gain can be changed when switching from the tamper to the die temperature sensor source.
41.6.2 Voltage Reference, Die Temperature Measurement and Calibration Registers
41.6.2.1 Voltage Reference
The EMAFE embeds an analog voltage reference with a typical output voltage of 1.144V. The temperature drift of
the voltage reference can be approximated by a linear fit. The temperature drift is measured during manufacturing
and stored in the calibration registers (ROM). Two measurements are made: one at a low temperature, TL, and
another at a high temperature, TH. At both temperatures TL and TH, VREF voltage and ADC_TEMP_OUT (ADC
I0 reading of the temperature sensor) parameters are saved. From the data obtained, the user can implement a
software compensation of the voltage reference.
41.6.2.2 Die Temperature Sensor
To measure the internal die temperature, the EMAFE embeds a dedicated analog die temperature sensor that is
multiplexed on the tamper channel (ADC I0). By measuring the die temperature periodically and by using the
calibration bits, channel gain drifts over temperature due to the voltage reference can be corrected.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
999
42.
Advanced Encryption Standard (AES)
42.1
Description
The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing
Standard) Publication 197 specification.
The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB,
CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-38A Recommendation, as well as
Galois/Counter Mode (GCM) as specified in the NIST Special Publication 800-38D Recommendation. It is
compatible with all these modes via Peripheral DMA Controller channels, minimizing processor intervention for
large buffer transfers.
The 128-bit/192-bit/256-bit key is stored in four/six/eight 32-bit write-only AES Key Word Registers
(AES_KEYWR0–3).
The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit write-only AES Input
Data Registers (AES_IDATAR0–3) and AES Initialization Vector Registers (AES_IVR0–3).
As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process
may be started. Then the encrypted/decrypted data are ready to be read out on the four 32-bit AES Output Data
Registers (AES_ODATAR0–3) or through the PDC channels.
42.2
42.3
Embedded Characteristics
Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
128-bit/192-bit/256-bit Cryptographic Key
12/14/16 Clock Cycles Encryption/Decryption Processing Time with a 128-bit/192-bit/256-bit Cryptographic
Key
Double Input Buffer Optimizes Runtime
Support of the Modes of Operation Specified in the NIST Special Publication 800-38A and NIST Special
Publication 800-38D:
̶
Electronic Code Book (ECB)
̶
Cipher Block Chaining (CBC) including CBC-MAC
̶
Cipher Feedback (CFB)
̶
Output Feedback (OFB)
̶
Counter (CTR)
̶
Galois/Counter Mode (GCM)
8, 16, 32, 64 and 128-bit Data Sizes Possible in CFB Mode
Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation
Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes
̶
One Channel for the Receiver, One Channel for the Transmitter
̶
Next Buffer Support
Product Dependencies
42.3.1 Power Management
The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to
configure the PMC to enable the AES clock.
1000
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.3.2 Interrupt
The AES interface has an interrupt line connected to the Interrupt Controller.
Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES.
Table 42-1.
42.4
Peripheral IDs
Instance
ID
AES
36
Functional Description
The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to
protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt
(decipher) information.
Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data
back into its original form, called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection
between the encryption and the decryption processes.
The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128
bits. This 128-bit/192-bit/256-bit key is defined in the AES_KEYWRx.
The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a
128-bit data block called the initialization vector (IV), which must be set in the AES_IVRx. The initialization vector
is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The
AES_IVRx are also used by the CTR mode to set the counter value.
42.4.1 AES Register Endianism
In ARM processor-based products, the system bus and processors manipulate data in little-endian form. The AES
interface requires little-endian format words. However, in accordance with the protocol of the FIPS 197
specification, data is collected, processed and stored by the AES algorithm in big-endian form.
The following example illustrates how to configure the AES:
If the first 64 bits of a message (according to FIPS 197, i.e., big-endian format) to be processed is
0xcafedeca_01234567, then the AES_IDATAR0 and AES_IDATAR1 registers must be written with the following
pattern:
AES_IDATAR0 = 0xcadefeca
AES_IDATAR1 = 0x67452301
42.4.2 Operation Modes
The AES supports the following modes of operation:
ECB: Electronic Code Book
CBC: Cipher Block Chaining
OFB: Output Feedback
CFB: Cipher Feedback
̶
CFB8 (CFB where the length of the data segment is 8 bits)
̶
CFB16 (CFB where the length of the data segment is 16 bits)
̶
CFB32 (CFB where the length of the data segment is 32 bits)
̶
CFB64 (CFB where the length of the data segment is 64 bits)
̶
CFB128 (CFB where the length of the data segment is 128 bits)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1001
CTR: Counter
GCM: Galois/Counter Mode
The data pre-processing, post-processing and data chaining for the concerned modes are automatically
performed. Refer to the NIST Special Publication 800-38A and NIST Special Publication 800-38D for more
complete information.
These modes are selected by setting the OPMOD field in the AES_MR.
In CFB mode, five data sizes are possible (8, 16, 32, 64 or 128 bits), configurable by means of the CFBS field in
the AES_MR (Section 42.5.2 “AES Mode Register”).
In CTR mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after
processing 1 megabyte of data. If the file to be processed is greater than 1 megabyte, this file must be split into
fragments of 1 megabyte or less for the first fragment if the initial value of the counter is greater than 0. Prior to
loading the first fragment into AES_IDATARx, AES_IVRx must be fully programmed with the initial counter value.
For any fragment, after the transfer is completed and prior to transferring the next fragment, AES_IVRx must be
programmed with the appropriate counter value.
If the initial value of the counter is greater than 0 and the data buffer size to be processed is greater than 1
megabyte, the size of the first fragment to be processed must be 1 megabyte minus 16x(initial value) to prevent a
rollover of the internal 1-bit counter.
To have a sequential increment, the counter value must be programmed with the value programmed for the
previous fragment + 216 (or less for the first fragment).
All AES_IVRx fields must be programmed to take into account the possible carry propagation.
42.4.3 Double Input Buffer
The AES_IDATARx can be double-buffered to reduce the runtime of large files.
This mode allows writing a new message block when the previous message block is being processed. This is only
possible when DMA accesses are performed (SMOD = 0x2).
The DUALBUFF bit in the AES_MR must be set to ‘1’ to access the double buffer.
42.4.4 Start Modes
The SMOD field in the AES_MR allows selection of the encryption (or decryption) Start mode.
42.4.4.1 Manual Mode
The sequence order is as follows:
1. Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD.
2.
Write the 128-bit/192-bit/256-bit key in the AES_KEYWRx.
3.
Write the initialization vector (or counter) in the AES_IVRx.
Note:
1002
The AES_IVRx concerns all modes except ECB.
4.
Set the bit DATRDY (Data Ready) in the AES Interrupt Enable Register (AES_IER), depending on whether
an interrupt is required or not at the end of processing.
5.
Write the data to be encrypted/decrypted in the authorized AES_IDATARx (see Table 42-2).
6.
Set the START bit in the AES Control Register (AES_CR) to begin the encryption or the decryption process.
7.
When processing completes, the DATRDY flag in the AES Interrupt Status Register (AES_ISR) is raised. If
an interrupt has been enabled by setting the DATRDY bit in the AES_IER, the interrupt line of the AES is
activated.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
8.
When software reads one of the AES_ODATARx, the DATRDY bit is automatically cleared.
Table 42-2.
Authorized Input Data Registers
Operation Mode
Input Data Registers to Write
ECB
All
CBC
All
OFB
All
128-bit CFB
All
64-bit CFB
AES_IDATAR0 and AES_IDATAR1
32-bit CFB
AES_IDATAR0
16-bit CFB
AES_IDATAR0
8-bit CFB
AES_IDATAR0
CTR
All
GCM
All
Notes:
1.
2.
In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in
processing.
In 32, 16, and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not allowed and
may lead to errors in processing.
42.4.4.2 Auto Mode
The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of
AES_IDATARx is written, processing is automatically started without any action in the AES_CR.
42.4.4.3 PDC Mode
T h e P e r ip h e r a l D M A C o n t r o l l e r ( P D C ) c a n b e u s e d i n a s s o c i a t i o n w i t h t h e A E S t o p e r f o r m a n
encryption/decryption of a buffer without any action by software during processing.
The field SMOD in the AES_MR must be configured to 0x2.
The sequence order is as follows:
1. Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD.
2.
Write the key in the AES_KEYWRx.
3.
Write the initialization vector (or counter) in the AES_IVRx.
Note:
4.
Note:
5.
Note:
The AES_IVRx concern all modes except ECB.
Set the Transmit Pointer Register (AES_TPR) to the address where the data buffer to encrypt/decrypt is
stored and the Receive Pointer Register (AES_RPR) where it must be encrypted/decrypted.
Transmit and receive buffers can be identical.
Set the Transmit and the Receive Counter Registers (AES_TCR and AES_RCR) to the same value. This
value must be a multiple of the data transfer type size (see Table 42-3).
The same requirements are necessary for the Next Pointer(s) and Counter(s) of the PDC (AES_TNPR, AES_RNPR,
AES_TNCR, AES_RNCR).
6.
If not already done, set the bit ENDRX (or RXBUFF if the next pointers and counters are used) in the
AES_IER, depending on whether an interrupt is required or not at the end of processing.
7.
Enable the PDC in transmission and reception to start the processing (AES_PTCR).
When the processing completes, the ENDRX (or RXBUFF) flag in the AES_ISR is raised. If an interrupt has been
enabled by setting the corresponding bit in the AES_IER, the interrupt line of the AES is activated.
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When PDC is used, the data size to transfer (byte, half-word or word) depends on the AES mode of operations.
This size is automatically configured by the AES.
Table 42-3.
Data Transfer Type for the Different Operation Modes
Operation Mode
Data Transfer Type
ECB
Word
CBC
Word
OFB
Word
CFB 128-bit
Word
CFB 64-bit
Word
CFB 32-bit
Word
CFB 16-bit
Half-word
CFB 8-bit
Byte
CTR
Word
GCM
Word
42.4.5 Last Output Data Mode
This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining
encryption algorithm (CBC-MAC algorithm for example).
After each end of encryption/decryption, the output data are available either on the AES_ODATARx for Manual
and Auto mode or at the address specified in the receive buffer pointer for PDC mode (see Table 42-4).
The Last Output Data (LOD) bit in the AES_MR allows retrieval of only the last data of several
encryption/decryption processes.
Therefore, there is no need to define a read buffer in PDC mode.
This data are only available on the AES_ODATARx.
42.4.5.1 Manual and Auto Modes
If AES_MR.LOD = 0
The DATRDY flag is cleared when at least one of the AES_ODATARx is read (see Figure 42-1).
Figure 42-1.
Manual and Auto Modes with AES_MR.LOD = 0
Write START bit in AES_CR (Manual mode)
or
Write AES_IDATARx register(s) (Auto mode)
Read the AES_ODATARx
DATRDY
Encryption or Decryption Process
If the user does not want to read the AES_ODATARx between each encryption/decryption, the DATRDY flag will
not be cleared. If the DATRDY flag is not cleared, the user cannot know the end of the following
encryptions/decryptions.
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If AES_MR.LOD = 1
This mode is optimized to process AES CPC-MAC operating mode.
The DATRDY flag is cleared when at least one AES_IDATAR is written (see Figure 42-2). No more AES_ODATAR
reads are necessary between consecutive encryptions/decryptions.
Figure 42-2.
Manual and Auto Modes with AES_MR.LOD = 1
Write START bit in AES_CR (Manual mode)
or
Write AES_IDATARx register(s) (Auto mode)
Write AES_IDATARx register(s)
DATRDY
Encryption or Decryption Process
42.4.5.2 PDC Mode
If AES_MR.LOD = 0
This mode may be used for all AES operating modes except CBC-MAC where AES_MR.LOD = 1 mode is
recommended.
The end of the encryption/decryption is indicated when the ENDRX (or RXBUFF) flag is raised (see Figure 42-3).
Figure 42-3.
PDC Transfer with AES_MR.LOD = 0
Enable PDC Channels (Receive and Transmit Channels)
Multiple Encryption or Decryption Processes
ENDTX (or TXBUFEL)
ENDRX (or RXBUFF)
Write accesses into AES_IDATARx
Read accesses into AES_ODATARx
Message fully processed
(cipher or decipher) last
block can be read
If AES_MR.LOD = 1
This mode is optimized to process AES CBC-MAC operating mode.
The user must first wait for the ENDTX (or TXBUFE) flag to be raised, then for DATRDY to ensure that the
encryption/decryption is completed (see Figure 42-4).
In this case, no receive buffers are required.
The output data are only available on the AES_ODATARx.
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Figure 42-4.
PDC Transfer with AES_MR.LOD = 1
Enable PDC Channels (Receive and Transmit Channels)
Multiple Encryption or Decryption Processes
ENDTX (or TXBUFE)
Write accesses into AES_IDATARx
Message fully processed
(cipher or decipher)
MAC result can be read
DATRDY
Message fully transferred
Table 42-4 summarizes the different cases.
Table 42-4.
Last Output Data Mode Behavior versus Start Modes
Manual and Auto Modes
Sequence
AES_MR.LOD = 0
DATRDY Flag
Clearing Condition(1)
At least one
AES_ODATAR must be
read
At least one
AES_IDATAR must be
written
Not used
Managed by the PDC
DATRDY
DATRDY
ENDRX (or RXBUFF)
ENDTX (or TXBUFE)
then DATRDY
End of
Encryption/Decryption
Notification
AES_MR.LOD = 1
PDC Mode
AES_MR.LOD = 0
AES_MR.LOD = 1
Encrypted/Decrypted
At the address specified
In the AES_ODATARx
In the AES_ODATARx
In the AES_ODATARx
Data Result Location
in the AES_RPR
Note:
1. Depending on the mode, there are other ways of clearing the DATRDY flag. See Section 42.5.6 “AES Interrupt Status
Register”.
Warning: In PDC mode, reading the AES_ODATARx before the last data transfer may lead to unpredictable results.
42.4.6 Galois/Counter Mode (GCM)
42.4.6.1 Description
GCM comprises the AES engine in CTR mode along with a universal hash function (GHASH engine) that is
defined over a binary Galois field to produce a message authentication tag (the AES CTR engine and the GHASH
engine are depicted in Figure 42-5).
The GHASH engine processes data packets after the AES operation. GCM provides assurance of the
confidentiality of data through the AES Counter mode of operation for encryption. Authenticity of the confidential
data is assured through the GHASH engine. GCM can also provide assurance of data that is not encrypted. Refer
to the NIST Special Publication 800-38D for more complete information.
GCM can be used with or without the PDC master. Messages may be processed as a single complete packet of data or they
may be broken into multiple packets of data over time.
GCM processing is computed on 128-bit input data fields. There is no support for unaligned data. The AES key
length can be whatever length is supported by the AES module.
The recommended programming procedure when using PDC is described in Section 42.4.6.3 “GCM Processing”.
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Figure 42-5.
GCM Block Diagram
AES CTR Engine
(AES_IVRx)
(AES_CTRR)
Counter 0
Incr32
Counter 1
(AES_CTRR)
Incr32
Counter N
(AES_KEYWRx)
Cipher(Key)
Cipher(Key)
(AES_IDATARx)
Cipher(Key)
(AES_IDATARx)
Plaintext N
Plaintext 1
Ciphertext 1
(AES_IDATARx)
AAD 1
Ciphertext N
(AES_IDATARx)
AAD N
(AES_GHASHRx)
(AES_GHASHRx)
(AES_GHASHRx)
GF128Mult(H)
GF128Mult(H)
(AES_GCMHRx)(1)
(AES_AADLENR, AES_CLENR)
GF128Mult(H)
len(AAD) || len(C)
GF128Mult(H)
GF128Mult(H)
(AES_TAGRx)
Auth Tag(T)
GHASH Engine
Notes: 1. Optional
42.4.6.2 Key Writing and Automatic Hash Subkey Calculation
Whenever a new key (AES_KEYWRx) is written to the hardware, two automatic actions are processed:
GCM Hash Subkey H generation—The GCM hash subkey (H) is automatically generated. The GCM hash
subkey generation must be complete before doing any other action. The DATRDY bit of the AES_ISR
indicates when the subkey generation is complete (with interrupt if configured). The GCM hash subkey
calculation is processed with the formula H = CIPHER(Key, . The generated GCM H value
is then available in the AES_GCMHRx. If the application software requires a specific hash subkey, the
automatically generated H value can be overwritten in the AES_GCMHRx.
The AES_GCMHRx can be written after the end of the hash subkey generation (see AES_ISR.DATRDY)
and prior to starting the input data feed.
AES_GHASHRx Clear—The AES_GHASHRx are automatically cleared. If a hash initial value is needed for
the GHASH, it must be written to the AES_GHASHRx
̶
after a write to AES_KEYWRx, if any
̶
before starting the input data feed
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42.4.6.3 GCM Processing
GCM processing comprises three phases:
1. Processing the Additional Authenticated Data (AAD), hash computation only.
2.
Processing the Ciphertext (C), hash computation + ciphering/deciphering.
3.
Generating the Tag using length of AAD, length of C and J0 (see NIST documentation for details).
The Tag generation can be done either automatically, after the end of AAD/C processing if TAG_EN bit is set in
the AES_MR or done manually, using the GHASH field in AES_GHASHRx (see below “Processing a Complete
Message with Tag Generation” and “Manual GCM Tag Generation” for details).
Processing a Complete Message with Tag Generation
Use this procedure only if J0 four LSB bytes ≠ 0xFFFFFFFF.
NOTE: In the case where J 0 four LSB bytes = 0xFFFFFFFF or if the value is unknown, use the procedure
described in “Processing a Complete Message without Tag Generation” followed by the procedure in “Manual
GCM Tag Generation”.
Figure 42-6.
Full Message Alignment
16-byte Boundaries
C (Text)
AAD
Padding
AADLEN
Padding
CLEN
To process a complete message with Tag generation, the sequence is as follows:
1. In AES_MR set OPMOD to GCM and GTAGEN to ‘1’ (configuration as usual for the rest).
2.
Set KEYW in AES_KEYWRx and wait until DATRDY bit of AES_ISR is set (GCM hash subkey generation
complete); use interrupt if needed. See Section 42.4.6.2 “Key Writing and Automatic Hash Subkey
Calculation” for details.
3.
Calculate the J0 value as described in NIST documentation J0 = IV || 031 || 1 when len(IV) = 96 and
J0 = GHASHH(IV || 0s+64 || [len(IV)]64) if len(IV) ≠ 96. See “Processing a Message with only AAD (GHASHH)”
for J0 generation.
4.
Set IV in AES_IVRx with inc32(J0) (J0 + 1 on 32 bits).
5.
Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR.
6.
Fill the IDATA field of AES_IDATARx with the message to process according to the SMOD configuration
used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when the data have been processed
(however, no output data are generated when processing AAD).
7.
Wait for TAGRDY to be set (use interrupt if needed), then read the TAG field of AES_TAGRx to obtain the
authentication tag of the message.
Processing a Complete Message without Tag Generation
Processing a message without generating the Tag can be used to customize the Tag generation, or to process a
fragmented message. To manually generate the GCM Tag, refer to “Manual GCM Tag Generation”.
To process a complete message without Tag generation, the sequence is as follows:
1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’ (configuration as usual for the rest).
2.
1008
Set KEYW in AES_KEYWRx and wait until DATRDY bit of AES_ISR is set (GCM hash subkey generation
complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash
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subkey can be read or overwritten with specific value in the AES_GCMHRx (see Section 42.4.6.2 “Key
Writing and Automatic Hash Subkey Calculation” for details).
3.
Calculate the J0 value as described in NIST documentation J0 = IV || 031 || 1 when len(IV) = 96 and
J0 = GHASHH(IV || 0s+64 || [len(IV)]64) if len(IV) ≠ 96. See “Processing a Message with only AAD (GHASHH)”
for J0 generation example when len(IV) ≠ 96.
4.
Set IV in AES_IVRx with inc32(J0) (J0 + 1 on 32 bits).
5.
Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR.
6.
Fill the IDATA field of AES_IDATARx with the message to process according to the SMOD configuration
used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when the data have been processed
(however, no output data are generated when processing AAD).
7.
Make sure the last output data have been read if CLEN ≠ 0 (or wait for DATRDY), then read the GHASH field
of AES_GHASHRx to obtain the hash value after the last processed data.
Processing a Fragmented Message without Tag Generation
If needed, a message can be processed by fragments, in such case automatic GCM Tag generation is not
supported.
To process a message by fragments, the sequence is as follows:
First fragment:
1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’ (configuration as usual for the rest).
2.
Set KEYW in AES_KEYWRx and wait for DATRDY bit of AES_ISR to be set (GCM hash subkey generation
complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash
subkey can be read or overwritten with specific value in the AES_GCMHRx (see Section 42.4.6.2 “Key
Writing and Automatic Hash Subkey Calculation” for details).
3.
Calculate the J0 value as described in NIST documentation J0 = IV || 031 || 1 when len(IV) = 96 and
J0 = GHASHH(IV || 0s+64 || [len(IV)]64) if len(IV) ≠ 96. See “Processing a Message with only AAD (GHASHH)”
for J0 generation example when len(IV) ≠ 96.
4.
Set IV in AES_IVRx with inc32(J0) (J0 + 1 on 32 bits).
5.
Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR according to the length of the first
fragment, or set the fields with the full message length, both configurations work.
6.
Fill the IDATA field of AES_IDATARx with the first fragment of the message to process (aligned on 16-byte
boundary) according to the SMOD configuration used. If Manual Mode or Auto Mode is used the DATRDY
bit indicates when the data have been processed (however, no output data are generated when processing
AAD).
7.
Make sure the last output data have been read if the fragment ends in C phase (or wait for DATRDY if the
fragment ends in AAD phase), then read the GHASH field of AES_GHASHRx to obtain the value of the hash
after the last processed data and finally read the CTR field of the AES_CTR to obtain the value of the CTR
encryption counter (not needed when the fragment ends in AAD phase).
Next fragment (or last fragment):
1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’ (configuration as usual for the rest).
2.
Set KEYW in AES_KEYWRx and wait until DATRDY bit of AES_ISR is set (GCM hash subkey generation
complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash
subkey can be read or overwritten with specific value in the AES_GCMHRx (see Section 42.4.6.2 “Key
Writing and Automatic Hash Subkey Calculation” for details).
3.
Set IV in AES_IVRx with:
̶
If the first block of the fragment is a block of Additional Authenticated data, set IV in AES_IVRx with
the J0 initial value
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̶
If the first block of the fragment is a block of Plaintext data, set IV in AES_IVRx with a value
constructed as follows: ‘LSB96(J0) || CTR’ value, (96 bit LSB of J0 concatenated with saved CTR
value from previous fragment).
4.
Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR according to the length of the current
fragment, or set the fields with the remaining message length, both configurations work.
5.
Fill the GHASH field of AES_GHASHRx with the value stored after the previous fragment.
6.
Fill the IDATA field of AES_IDATARx with the current fragment of the message to process (aligned on 16
byte boundary) according to the SMOD configuration used. If Manual Mode or Auto Mode is used, the
DATRDY bit indicates when the data have been processed (however, no output data are generated when
processing AAD).
7.
Make sure the last output data have been read if the fragment ends in C phase (or wait for DATRDY if the
fragment ends in AAD phase), then read the GHASH field of AES_GHASHRx to obtain the value of the hash
after the last processed data and finally read the CTR field of the AES_CTR to obtain the value of the CTR
encryption counter (not needed when the fragment ends in AAD phase).
Note:
Step 1 and 2 are required only if the value of the concerned registers has been modified.
Once the last fragment has been processed, the GHASH value will allow manual generation of the GCM tag (see
“Manual GCM Tag Generation” for details).
Manual GCM Tag Generation
This section describes the last steps of the GCM Tag generation.
The Manual GCM Tag Generation is used to complete the GCM Tag Generation when the message has been
processed without Tag Generation.
Note:
The Message Processing without Tag Generation must be finished before processing the Manual GCM Tag
Generation.
To generate a GCM Tag manually, the sequence is as follows:
Processing S = GHASHH (AAD || 0v || C || 0u || [len(AAD)]64 || [len(C)]64):
1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’ (configuration as usual for the rest).
2.
Set KEYW in AES_KEYWRx and wait for DATRDY bit of AES_ISR to be set (GCM hash subkey generation
complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash
subkey can be read or overwritten with specific value in the AES_GCMHRx (see Section 42.4.6.2 “Key
Writing and Automatic Hash Subkey Calculation” for details).
3.
Set AADLEN field to 0x10 (16 bytes) in AES_AADLENR and CLEN field to ‘0’ in AES_CLENR. This will
allow running a single GHASHH on a 16-byte input data (see Figure 42-7).
4.
Fill the GHASH field of AES_GHASHRx with the state of the GHASH field stored at the end of the message
processing.
5.
Fill the IDATA field of AES_IDATARx according to the SMOD configuration used with ‘len(AAD)64 || len(C)64’
value as described in the NIST documentation and wait for DATRDY to be set; use interrupt if needed.
6.
Read the GHASH field of AES_GHASHRx to obtain the current value of the hash.
Processing T = GCTRK(J0, S):
7.
In AES_MR set OPMOD to CTR (configuration as usual for the rest).
8.
Set the IV field in AES_IVRx with ‘J0’ value.
9.
Fill the IDATA field of AES_IDATARx with the GHASH value read at step 6 and wait for DATRDY to be set
(use interrupt if needed).
10. Read the ODATA field of AES_ODATARx to obtain the GCM Tag value.
Note:
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Step 4 is optional if the GHASH field is to be filled with value ‘0’ (0 length packet for instance).
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Processing a Message with only AAD (GHASHH)
Figure 42-7.
Single GHASHH Block Diagram (AADLEN ≤ 0x10 and CLEN = 0)
GHASH
IDATA
GF128Mult(H)
GHASH
It is possible to process a message with only AAD setting the CLEN field to ‘0’ in the AES_CLENR, this can be
used for J0 generation when len(IV) ≠ 96 for instance.
Example: Processing J0 when len(IV) ≠ 96
To process J0 = GHASHH(IV || 0s+64 || [len(IV)]64), the sequence is as follows:
1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’ (configuration as usual for the rest).
2.
Set KEYW in AES_KEYWRx and wait until DATRDY bit of AES_ISR is set (GCM hash subkey generation
complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash
subkey can be read or overwritten with specific value in the AES_GCMHRx (see Section 42.4.6.2 “Key
Writing and Automatic Hash Subkey Calculation” for details).
3.
Set AADLEN field with ‘len(IV || 0s+64 || [len(IV)]64)’ in AES_AADLENR and CLEN field to ‘0’ in AES_CLENR.
This will allow running a GHASHH only.
4.
Fill the IDATA field of AES_IDATARx with the message to process (IV || 0s+64 || [len(IV)]64) according to the
SMOD configuration used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when a
GHASHH step is over (use interrupt if needed).
5.
Read the GHASH field of AES_GHASHRx to obtain the J0 value.
Note:
The GHASH value can be overwritten at any time by writing the GHASH field value of AES_GHASHRx, used to
perform a GHASHH with an initial value for GHASH (write GHASH field between step 3 and step 4 in this case).
Processing a Single GF128 Multiplication
The AES can also be used to process a single multiplication in the Galois field on 128 bits (GF128) using a single
GHASHH with custom H value (see Figure 42-7).
To run a GF128 multiplication (A x B), the sequence is as follows:
1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’ (configuration as usual for the rest).
2.
Set AADLEN field with 0x10 (16 bytes) in AES_AADLENR and CLEN field to ‘0’ in AES_CLENR. This will
allow running a single GHASHH.
3.
Fill the H field of the AES_GCMHRx with B value.
4.
Fill the IDATA field of AES_IDATARx with the A value according to the SMOD configuration used. If Manual
Mode or Auto Mode is used, the DATRDY bit indicates when a GHASHH computation is over (use interrupt if
needed).
5.
Read the GHASH field of AES_GHASHRx to obtain the result.
Note:
The GHASH field of AES_GHASHRx can be initialized with a value C between step 3 and step 4 to run a ((A XOR C) x
B) GF128 multiplication.
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42.4.7
Security Features
42.4.7.1 Unspecified Register Access Detection
When an unspecified register access occurs, the URAD flag in the AES_ISR is raised. Its source is then reported
in the Unspecified Register Access Type (URAT) field. Only the last unspecified register access is available
through the URAT field.
Several kinds of unspecified register accesses can occur:
Input Data Register written during the data processing when SMOD = IDATAR0_START
Output Data Register read during data processing
Mode Register written during data processing
Output Data Register read during sub-keys generation
Mode Register written during sub-keys generation
Write-only register read access
The URAD bit and the URAT field can only be reset by the SWRST bit in the AES_CR.
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42.5
Advanced Encryption Standard (AES) User Interface
Table 42-5.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
AES_CR
Write-only
–
0x04
Mode Register
AES_MR
Read/Write
0x0
Reserved
–
–
–
0x10
Interrupt Enable Register
AES_IER
Write-only
–
0x14
Interrupt Disable Register
AES_IDR
Write-only
–
0x18
Interrupt Mask Register
AES_IMR
Read-only
0x0
0x1C
Interrupt Status Register
AES_ISR
Read-only
0x0000001E
0x20
Key Word Register 0
AES_KEYWR0
Write-only
–
0x24
Key Word Register 1
AES_KEYWR1
Write-only
–
0x28
Key Word Register 2
AES_KEYWR2
Write-only
–
0x2C
Key Word Register 3
AES_KEYWR3
Write-only
–
0x30
Key Word Register 4
AES_KEYWR4
Write-only
–
0x34
Key Word Register 5
AES_KEYWR5
Write-only
–
0x38
Key Word Register 6
AES_KEYWR6
Write-only
–
0x3C
Key Word Register 7
AES_KEYWR7
Write-only
–
0x40
Input Data Register 0
AES_IDATAR0
Write-only
–
0x44
Input Data Register 1
AES_IDATAR1
Write-only
–
0x48
Input Data Register 2
AES_IDATAR2
Write-only
–
0x4C
Input Data Register 3
AES_IDATAR3
Write-only
–
0x50
Output Data Register 0
AES_ODATAR0
Read-only
0x0
0x54
Output Data Register 1
AES_ODATAR1
Read-only
0x0
0x58
Output Data Register 2
AES_ODATAR2
Read-only
0x0
0x5C
Output Data Register 3
AES_ODATAR3
Read-only
0x0
0x60
Initialization Vector Register 0
AES_IVR0
Write-only
–
0x64
Initialization Vector Register 1
AES_IVR1
Write-only
–
0x68
Initialization Vector Register 2
AES_IVR2
Write-only
–
0x6C
Initialization Vector Register 3
AES_IVR3
Write-only
–
0x70
Additional Authenticated Data Length Register
AES_AADLENR
Read/Write
–
0x74
Plaintext/Ciphertext Length Register
AES_CLENR
Read/Write
–
0x78
GCM Intermediate Hash Word Register 0
AES_GHASHR0
Read/Write
–
0x7C
GCM Intermediate Hash Word Register 1
AES_GHASHR1
Read/Write
–
0x80
GCM Intermediate Hash Word Register 2
AES_GHASHR2
Read/Write
–
0x84
GCM Intermediate Hash Word Register 3
AES_GHASHR3
Read/Write
–
0x88
GCM Authentication Tag Word Register 0
AES_TAGR0
Read-only
–
0x8C
GCM Authentication Tag Word Register 1
AES_TAGR1
Read-only
–
0x08–0x0C
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Table 42-5.
Register Mapping (Continued)
Offset
Register
Name
Access
Reset
0x90
GCM Authentication Tag Word Register 2
AES_TAGR2
Read-only
–
0x94
GCM Authentication Tag Word Register 3
AES_TAGR3
Read-only
–
0x98
GCM Encryption Counter Value Register
AES_CTRR
Read-only
–
0x9C
GCM H Word Register 0
AES_GCMHR0
Read/Write
–
0xA0
GCM H Word Register 1
AES_GCMHR1
Read/Write
–
0xA4
GCM H Word Register 2
AES_GCMHR2
Read/Write
–
0xA8
GCM H Word Register 3
AES_GCMHR3
Read/Write
–
0xAC
Reserved
–
–
–
0xB0–0xFC
Reserved
–
–
–
Reserved for the PDC
–
–
–
0x100–0x124
1014
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.1 AES Control Register
Name:
AES_CR
Address:
0x40000000
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
SWRST
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
START
• START: Start Processing
0: No effect.
1: Starts manual encryption/decryption process.
• SWRST: Software Reset
0: No effect.
1: Resets the AES. A software-triggered hardware reset of the AES interface is performed.
SAM4CM Series [DATASHEET]
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1015
42.5.2 AES Mode Register
Name:
AES_MR
Address:
0x40000004
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
CKEY
15
–
14
13
LOD
12
11
OPMOD
7
6
5
CFBS
10
9
KEYSIZE
4
PROCDLY
8
SMOD
3
2
1
0
DUALBUFF
–
GTAGEN
CIPHER
• CIPHER: Processing Mode
0: Decrypts data.
1: Encrypts data.
• GTAGEN: GCM Automatic Tag Generation Enable
0: Automatic GCM Tag generation disabled.
1: Automatic GCM Tag generation enabled.
• DUALBUFF: Dual Input Buffer
Value
Name
Description
0
INACTIVE
AES_IDATARx cannot be written during processing of previous block.
1
ACTIVE
AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds
up the overall runtime of large files.
• PROCDLY: Processing Delay
Processing Time = N × (PROCDLY + 1)
where
N = 10 when KEYSIZE = 0
N = 12 when KEYSIZE = 1
N = 14 when KEYSIZE = 2
The processing time represents the number of clock cycles that the AES needs in order to perform one
encryption/decryption.
Note: The best performance is achieved with PROCDLY equal to 0.
• SMOD: Start Mode
Value
1016
Name
Description
0
MANUAL_STAR
T
Manual Mode
1
AUTO_START
Auto Mode
2
IDATAR0_START
AES_IDATAR0 access only Auto Mode (PDC)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Values which are not listed in the table must be considered as “reserved”.
If a PDC transfer is used, configure SMOD to 0x2. Refer to Section 42.4.4.3 “PDC Mode” for more details.
• KEYSIZE: Key Size
Value
Name
Description
0
AES128
AES Key Size is 128 bits
1
AES192
AES Key Size is 192 bits
2
AES256
AES Key Size is 256 bits
Values which are not listed in the table must be considered as “reserved”.
• OPMOD: Operation Mode
Value
Name
Description
0
ECB
ECB: Electronic Code Book mode
1
CBC
CBC: Cipher Block Chaining mode
2
OFB
OFB: Output Feedback mode
3
CFB
CFB: Cipher Feedback mode
4
CTR
CTR: Counter mode (16-bit internal counter)
5
GCM
GCM: Galois/Counter mode
Values which are not listed in the table must be considered as “reserved”.
For CBC-MAC operating mode, set OPMOD to CBC and LOD to 1.
• LOD: Last Output Data Mode
0: No effect.
After each end of encryption/decryption, the output data are available either on the output data registers (Manual and Auto
modes) or at the address specified in the Receive Pointer Register (AES_RPR) for PDC mode.
In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read.
1: The DATRDY flag is cleared when at least one of the Input Data Registers is written.
No more Output Data Register reads is necessary between consecutive encryptions/decryptions (see Section 42.4.5 “Last
Output Data Mode”).
Warning: In PDC mode, reading to the Output Data registers before the last data encryption/decryption process may lead to
unpredictable results.
• CFBS: Cipher Feedback Data Size
Value
Name
Description
0
SIZE_128BIT
128-bit
1
SIZE_64BIT
64-bit
2
SIZE_32BIT
32-bit
3
SIZE_16BIT
16-bit
4
SIZE_8BIT
8-bit
Values which are not listed in table must be considered as “reserved”.
SAM4CM Series [DATASHEET]
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1017
• CKEY: Key
Value
0xE
Name
Description
PASSWD
This field must be written with 0xE the first time the AES_MR is programmed. For subsequent
programming of the AES_MR, any value can be written, including that of 0xE.
Always reads as 0.
1018
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.3 AES Interrupt Enable Register
Name:
AES_IER
Address:
0x40000010
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
TAGRDY
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
URAD
7
6
5
4
3
2
1
0
–
–
–
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
• DATRDY: Data Ready Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• URAD: Unspecified Register Access Detection Interrupt Enable
• TAGRDY: GCM Tag Ready Interrupt Enable
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1019
42.5.4 AES Interrupt Disable Register
Name:
AES_IDR
Address:
0x40000014
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
TAGRDY
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
URAD
7
6
5
4
3
2
1
0
–
–
–
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
• DATRDY: Data Ready Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• URAD: Unspecified Register Access Detection Interrupt Disable
• TAGRDY: GCM Tag Ready Interrupt Disable
1020
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.5 AES Interrupt Mask Register
Name:
AES_IMR
Address:
0x40000018
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
TAGRDY
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
URAD
7
6
5
4
3
2
1
0
–
–
–
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
• DATRDY: Data Ready Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• URAD: Unspecified Register Access Detection Interrupt Mask
• TAGRDY: GCM Tag Ready Interrupt Mask
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1021
42.5.6 AES Interrupt Status Register
Name:
AES_ISR
Address:
0x4000001C
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
TAGRDY
15
14
13
12
11
10
9
8
–
–
–
URAD
URAT
7
6
5
4
3
2
1
0
–
–
–
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
• DATRDY: Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)
0: Output data not valid.
1: Encryption or decryption process is completed.
Note: If AES_MR.LOD = 1: In Manual and Auto mode, the DATRDY flag can also be cleared by writing at least one AES_IDATARx.
• ENDRX: End of RX Buffer (cleared by writing AES_RCR or AES_RNCR)
0: The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR.
1: The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.
Note: This flag must be used only in PDC mode with AES_MR.LOD bit cleared.
• ENDTX: End of TX Buffer (cleared by writing AES_TCR or AES_TNCR)
0: The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR.
1: The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.
Note: This flag must be used only in PDC mode with AES_MR.LOD bit set.
• RXBUFF: RX Buffer Full (cleared by writing AES_RCR or AES_RNCR)
0: AES_RCR or AES_RNCR has a value other than 0.
1: Both AES_RCR and AES_RNCR have a value of 0.
Note: This flag must be used only in PDC mode with AES_MR.LOD bit cleared.
• TXBUFE: TX Buffer Empty (cleared by writing AES_TCR or AES_TNCR)
0: AES_TCR or AES_TNCR has a value other than 0.
1: Both AES_TCR and AES_TNCR have a value of 0.
Note: This flag must be used only in PDC mode with AES_MR.LOD bit set.
• URAD: Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)
0: No unspecified register access has been detected since the last SWRST.
1: At least one unspecified register access has been detected since the last SWRST.
1022
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
• URAT: Unspecified Register Access (cleared by writing SWRST in AES_CR)
Value
Name
Description
0
IDR_WR_PROCESSING
Input Data Register written during the data processing when SMOD = 0x2 mode.
1
ODR_RD_PROCESSING
Output Data Register read during the data processing.
2
MR_WR_PROCESSING
Mode Register written during the data processing.
3
ODR_RD_SUBKGEN
Output Data Register read during the sub-keys generation.
4
MR_WR_SUBKGEN
Mode Register written during the sub-keys generation.
5
WOR_RD_ACCESS
Write-only register read access.
Only the last Unspecified Register Access Type is available through the URAT field.
• TAGRDY: GCM Tag Ready
0: GCM Tag is not valid.
1: GCM Tag generation is complete (cleared by reading GCM Tag, starting another processing or when writing a new key).
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1023
42.5.7 AES Key Word Register x
Name:
AES_KEYWRx [x=0..7]
Address:
0x40000020
Access:
Write-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
KEYW
23
22
21
20
KEYW
15
14
13
12
KEYW
7
6
5
4
KEYW
• KEYW: Key Word
The four/six/eight 32-bit Key Word Registers set the 128-bit/192-bit/256-bit cryptographic key used for AES
encryption/decryption.
AES_KEYWR0 corresponds to the first word of the key and respectively AES_KEYWR3/AES_KEYWR5/AES_KEYWR7 to
the last one.
Whenever a new key (AES_KEYWRx) is written to the hardware, two automatic actions are processed:
• GCM hash subkey generation
• AES_GHASHRx Clear
See Section 42.4.6.2 “Key Writing and Automatic Hash Subkey Calculation” for details.
These registers are write-only to prevent the key from being read by another application.
1024
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.8 AES Input Data Register x
Name:
AES_IDATARx [x=0..3]
Address:
0x40000040
Access:
Write-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IDATA
23
22
21
20
IDATA
15
14
13
12
IDATA
7
6
5
4
IDATA
• IDATA: Input Data Word
The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption.
AES_IDATAR0 corresponds to the first word of the data to be encrypted/decrypted, and AES_IDATAR3 to the last one.
These registers are write-only to prevent the input data from being read by another application.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1025
42.5.9 AES Output Data Register x
Name:
AES_ODATARx [x=0..3]
Address:
0x40000050
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ODATA
23
22
21
20
ODATA
15
14
13
12
ODATA
7
6
5
4
ODATA
• ODATA: Output Data
The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted.
AES_ODATAR0 corresponds to the first word, AES_ODATAR3 to the last one.
1026
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.10 AES Initialization Vector Register x
Name:
AES_IVRx [x=0..3]
Address:
0x40000060
Access:
Write-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
IV
23
22
21
20
IV
15
14
13
12
IV
7
6
5
4
IV
• IV: Initialization Vector
The four 32-bit Initialization Vector Registers set the 128-bit Initialization Vector data block that is used by some modes of
operation as an additional initial input.
AES_IVR0 corresponds to the first word of the Initialization Vector, AES_IVR3 to the last one.
These registers are write-only to prevent the Initialization Vector from being read by another application.
For CBC, OFB and CFB modes, the IV input value corresponds to the initialization vector.
For CTR mode, the IV input value corresponds to the initial counter value.
Note: These registers are not used in ECB mode and must not be written.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1027
42.5.11 AES Additional Authenticated Data Length Register
Name:
AES_AADLENR
Address:
0x40000070
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
AADLEN
23
22
21
20
AADLEN
15
14
13
12
AADLEN
7
6
5
4
AADLEN
• AADLEN: Additional Authenticated Data Length
Length in bytes of the Additional Authenticated Data (AAD) that is to be processed.
Note: The maximum byte length of the AAD portion of a message is limited to the 32-bit counter length.
1028
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.12 AES Plaintext/Ciphertext Length Register
Name:
AES_CLENR
Address:
0x40000074
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CLEN
23
22
21
20
CLEN
15
14
13
12
CLEN
7
6
5
4
CLEN
• CLEN: Plaintext/Ciphertext Length
Length in bytes of the plaintext/ciphertext (C) data that is to be processed.
Note: The maximum byte length of the C portion of a message is limited to the 32-bit counter length.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1029
42.5.13 AES GCM Intermediate Hash Word Register x
Name:
AES_GHASHRx [x=0..3]
Address:
0x40000078
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
GHASH
23
22
21
20
GHASH
15
14
13
12
GHASH
7
6
5
4
GHASH
• GHASH: Intermediate GCM Hash Word x
The four 32-bit Intermediate Hash Word registers expose the intermediate GHASH value. May be read to save the current
GHASH value so processing can later be resumed, presumably on a later message fragment. Whenever a new key
(AES_KEYWRx) is written to the hardware two automatic actions are processed:
• GCM hash subkey generation
• AES_GHASHRx Clear
See Section 42.4.6.2 “Key Writing and Automatic Hash Subkey Calculation” for details.
If an application software specific hash initial value is needed for the GHASH it must be written to the AES_GHASHRx:
• after a write to AES_KEYWRx, if any
• before starting the input data feed
1030
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.14 AES GCM Authentication Tag Word Register x
Name:
AES_TAGRx [x=0..3]
Address:
0x40000088
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
TAG
23
22
21
20
TAG
15
14
13
12
TAG
7
6
5
4
TAG
• TAG: GCM Authentication Tag x
The four 32-bit Tag registers contain the final 128-bit GCM Authentication tag (T) when GCM processing is complete.
TAG0 corresponds to the first word, TAG3 to the last word.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1031
42.5.15 AES GCM Encryption Counter Value Register
Name:
AES_CTRR
Address:
0x40000098
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CTR
23
22
21
20
CTR
15
14
13
12
CTR
7
6
5
4
CTR
• CTR: GCM Encryption Counter
Reports the current value of the 32-bit GCM counter.
1032
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
42.5.16 AES GCM H Word Register x
Name:
AES_GCMHRx [x=0..3]
Address:
0x4000009C
Access:
Read/Write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
H
23
22
21
20
H
15
14
13
12
H
7
6
5
4
H
• H: GCM H Word x
The four 32-bit H Word registers contain the 128-bit GCM hash subkey H value.
Whenever a new key (AES_KEYWRx) is written to the hardware two automatic actions are processed:
• GCM hash subkey H generation
• AES_GHASHRx Clear
If the application software requires a specific hash subkey, the automatically generated H value can be overwritten in the
AES_GCMHRx (see Section 42.4.6.2 “Key Writing and Automatic Hash Subkey Calculation” for details).
The choice of a GCM hash subkey H by a write in the AES_GCMHRx permits
• selection of the GCM hash subkey H for GHASH operations
• selection of one operand to process a single GF128 multiply
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1033
43.
Integrity Check Monitor (ICM)
43.1
Description
The Integrity Check Monitor (ICM) is a DMA controller that performs hash calculation over multiple memory
regions through the use of transfer descriptors located in memory (ICM Descriptor Area). The Hash function is
based on the Secure Hash Algorithm (SHA). The ICM controller integrates two modes of operation. The first one is
used to hash a list of memory regions and save the digests to memory (ICM Hash Area). The second operation
mode is an active monitoring of the memory. In that mode, the hash function is evaluated and compared to the
digest located at a predefined memory address (ICM Hash Area). If a mismatch occurs, an interrupt is raised. See
Figure 43-1 for an example of four-region monitoring. Hash and Descriptor areas are located in Memory instance
i2, and the four regions are split in memory instances i0 and i1.
Figure 43-1.
Four-region Monitoring Example
Processor
Interrupt
Controller
ICM
System Interconnect
Memory i0
Memory
Region 0
Memory
Region 1
Memory i1
Memory i2
Memory
Region 2
ICM
Hash
Area
Memory
Region 3
ICM
Descriptor
Area
The ICM SHA engine is compliant with the American FIPS (Federal Information Processing Standard) Publication
180-2 specification.
The following terms are concise definitions of the ICM concepts used throughout this document:
1034
Region—a partition of instruction or data memory space
Region Descriptor—a data structure stored in memory, defining region attributes
Region Attributes—region start address, region size, region SHA engine processing mode, Write Back or
Compare function mode
Context Registers—a set of ICM non-memory-mapped, internal registers which are automatically loaded,
containing the attributes of the region being processed
Main List—a list of region descriptors. Each element associates the start address of a region with a set of
attributes.
Secondary List—a linked list defined on a per region basis that describes the memory layout of the region
(when the region is non-contiguous)
Hash Area—predefined memory space where the region hash results (digest) are stored
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
43.2
Embedded Characteristics
DMA AHB master interface
Supports monitoring of up to 4 Non-Contiguous Memory Regions
Supports block gathering through the use of linked list
Supports Secure Hash Algorithm (SHA1, SHA224, SHA256)
Compliant with FIPS Publication 180-2
Configurable Processing Period:
43.3
̶
When SHA1 algorithm is processed, the runtime period is either 85 or 209 clock cycles.
̶
When SHA256 or SHA224 algorithm is processed, the runtime period is either 72 or 194 clock cycles.
Programmable Bus burden
Block Diagram
Figure 43-2.
Integrity Check Monitor Block Diagram
APB
Host
Interface
Configuration
Registers
SHA
Hash
Engine
Context
Registers
Monitoring
FSM
Integrity
Scheduler
Master
DMA Interface
Bus Layer
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1035
43.4
Product Dependencies
43.4.1 Power Management
The peripheral clock is not continuously provided to the ICM. The programmer must first enable the ICM clock in
the Power Management Controller (PMC) before using the ICM.
43.4.2 Interrupt Sources
The ICM interface has an interrupt line connected to the Interrupt Controller.
Handling the ICM interrupt requires programming the interrupt controller before configuring the ICM.
Table 43-1.
43.5
Peripheral IDs
Instance
ID
ICM
34
Functional Description
43.5.1 Overview
The Integrity Check Monitor (ICM) is a DMA controller that performs SHA-based memory hashing over memory
regions. As shown in Figure 43-2, it integrates a DMA interface, a Monitoring Finite State Machine (FSM), an
integrity scheduler, a set of context registers, a SHA engine, an interface for configuration and status registers.
The ICM integrates a Secure Hash Algorithm Engine (SHA). This engine requires a message padded according to
FIPS180-2 specification when used as a SHA calculation unit only. Otherwise, if the ICM is used as integrated
check for memory content, the padding is not mandatory. The SHA module produces an N-bit message digest
each time a block is read and a processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256.
When the ICM module is enabled, it sequentially retrieves a circular list of region descriptors from the memory
(Main List described in Figure 43-3). Up to four regions may be monitored. Each region descriptor is composed of
four words indicating the layout of the memory region (see Figure 43-4). It also contains the hashing engine
configuration on a per region basis. As soon as the descriptor is loaded from the memory and context registers are
updated with the data structure, the hashing operation starts. A programmable number of blocks (see TRSIZE field
of the ICM_RCTRL structure member) is transferred from the memory to the SHA engine. When the desired
number of blocks have been transferred, the digest is whether moved to memory (Write Back function) or
compared with a digest reference located in the system memory (Compare function). If a digest mismatch occurs,
an interrupt is triggered if unmasked. The ICM module passes through the region descriptor list until the end of the
list marked by an End of List bit set to one. To continuously monitor the list of regions, the WRAP bit must be set to
one in the last data structure.
1036
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 43-3.
ICM Region Descriptor and Hash Areas
Main List
infinite loop
when wrap bit is set
End of Region N
WRAP=1
Region N
Descriptor
ICM Descriptor
Area - Contiguous
Read-only Memory
Secondary List
End of Region 1 List
WRAP=0
Region 1
Descriptor
End of Region 0
WRAP=0
Region 0
Descriptor
Region N Hash
ICM Hash Area Contiguous
Read-write once
Memory
Region 1 Hash
Region 0 Hash
Each region descriptor supports gathering of data through the use of the Secondary List. Unlike the Main List, the
Secondary List cannot modify the configuration attributes of the region. When the end of the Secondary List has
been encountered, the ICM returns to the Main List. Memory integrity monitoring can be considered as a
background service and the mandatory bandwidth shall be very limited. In order to limit the ICM memory
bandwidth, use the BBC field of the ICM_CFG register to control ICM memory load.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1037
Figure 43-4.
Region Descriptor
Main List
Region 3 Descriptor
Region 2 Descriptor
Optional Region 0 Secondary List
Region 1 Descriptor
ICMDSCR
Region 0 Descriptor
End of Region 0
1038
0x00C
Region NEXT
0x00C
Region NEXT
0x008
Region CTRL
0x008
Region CTRL
0x004
Region CFG
0x004
Unused
0x000
Region ADDR
0x000
Region ADDR
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 43-5 shows an example of the mandatory ICM settings to monitor three memory data blocks of the system
memory (defined as two regions) with one region being not contiguous (two separate areas) and one contiguous
memory area. For each said region, the SHA algorithm may be independently selected (different for each region).
The wrap allows continuous monitoring.
Figure 43-5.
Example: Monitoring of 3 Memory Data Blocks (Defined as 2 Regions)
Size of
region1
block (S1)
R
Si e g i
Bl ng o n
oc le 1
k Da
ta
System Memory, data areas
System Memory, region descriptor structure
wrap=1 effect
NEXT=0
R
D egi
at o n
a
Bl 0
oc
k
1
Size of
region0
block 1
(S0B1)
2
1
@r0db1
NEXT=@sd @md+12
@md+8
S0B0
wrap=0, etc @md+4
@r0db0
@md
Region 1
Single
Descriptor
Region 0
Main
Descriptor
1
2
R
D egi
at o n
a
Bl 0
oc
k
0
3
Size of
region0
block 0
(S0B0)
@md+24
S1
wrap=1, etc @md+20
@md+16
@r1d
@r1d
3
@md+28
S0B1
@sd+12
@sd+8
don’t care
@sd+4
NEXT=0
@r0db1
Region 0
Second
Descriptor
@sd
@r0db0
43.5.2 ICM Region Descriptor Structure
The ICM Region Descriptor Area is a contiguous area of system memory that the controller and the processor can
access. When the ICM controller is activated, the controller performs a descriptor fetch operation at *(ICM_DSCR)
address. If the Main List contains more than one descriptor (i.e., more than one region is to be monitored), the
fetch address is *(ICM_DSCR) + (RID 2.0V, TJ = 100°C
–
–
120
VDDIN ≤ 2.0V, TJ = 100°C
–
–
40
-5
–
5
%
ILOAD = 0. Refer to Note(3)
–
–
400
mA
Normal mode; ILoad = 0 mA
–
5
–
Normal mode; ILoad = 120 mA
–
500
–
Standby mode
–
0.02
1
–
1
–
–
µF
Capacitance
0.7
2.2
10
µF
ESR
0.01
–
10
Ω
V
mA
ILOAD = 0.8 mA to 120 mA
ACC
Output voltage total accuracy
VDDIN = 2.0V to 3.6V
TJ = [-40°C to 100°C]
IINRUSH
Inrush current
IDDIN
Current consumption (VDDIN)
Input decoupling capacitor
CIN
(1)
µA
(2)
Output capacitor
COUT
tON
Turn-on time
COUT= 2.2µF, VDDOUT reaches 1.2V
(± 3%)
–
500
–
µs
tOFF
Turn-off Time
COUT= 2.2µF
–
–
40
ms
Notes:
1. A ceramic capacitor must be connected between VDDIN and the closest GND pin of the device.
This decoupling capacitor is mandatory to reduce inrush current and to improve transient response and noise rejection.
2. To ensure stability, an external output capacitor, COUT must be connected between the VDDOUT and the closest GND pin of
the device. The ESR (Equivalent Series Resistance) of the capacitor must be in the range of 0.01 to 10Ω.
Solid tantalum, and multilayer ceramic capacitors are all suitable as output capacitors. An additional 100-nF bypass
capacitor between VDDOUT and the closest GND pin of the device helps decrease output noise and improves the load
transient response.
3. Current needed to charge the external bypass/decoupling capacitor network.
46.5.2 Automatic Power Switch
Table 46-17.
Automatic Power Switch Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+
Positive-going input threshold voltage (VDDIO)
–
1.9
–
2.2
V
VIT-
Negative-going input threshold voltage (VDDIO)
–
1.8
–
2.1
V
VIT_HYST
Threshold hysteresis
–
–
100
–
mV
1092
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
46.5.3 LCD Voltage Regulator and LCD Output Buffers
The LCD Voltage Regulator is a complete solution to drive an LCD display. It integrates a low-power LDO
regulator with programmable output voltage and buffers to drive the LCD lines. A 1 µF capacitor is required at the
LDO regulator output (VDDLCD). This regulator can be set in Active (Normal) mode, in Bypass mode (HiZ mode),
or in OFF mode.
In Normal mode, the VDDLCD LDO regulator output can be selected from 2.4V to 3.5V using LCDVROUT
bits in the Supply Controller Mode Register (SUPC_MR), with the conditions:
VDDLCD ≤ VDDIO, and
̶
̶
VDDLCD ≤ VDDIN - 150 mV.
In Bypass mode (HiZ mode), the VDDLCD is set in high impedance (through the LCDMODE bits in
SUPC_MR register), and can be forced externally. This mode can be used to save the LDO operating
current (4 µA).
In OFF mode, the VDDLCD output is pulled down.
IMPORTANT: When using an external or the internal voltage regulator, VDDIO and VDDIN must be still supplied
with the conditions: 2.4V≤ VDDLCD ≤ VDDIO/VDDIN and VDDIO/VDDIN ≥ 2.5V.
Table 46-18.
LCD Voltage Regulator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDIN
Supply voltage range (VDDIN)
–
2.5
–
3.6
V
2.4
–
3.5
V
-10
–
+10
%
Programmable output range
VDDLCD
Refer to Table 46-19.
Output voltage accuracy
IDDIN
Current consumption (VDDIN)
LDO enabled
–
–
4
µA
dVOUT/
dVDDIN
VDDLCD variation with VDDIN
–
–
-50
-70
mV/V
ILOAD
Output current
DC or transient load averaged by
the external decoupling capacitor
–
–
2
mA
COUT
Output capacitor on VDDLCD
–
1
–
10
µF
tON
Start-up time
COUT= 1µF
–
–
1
ms
Table 46-19.
VDDLCD Voltage Selection at VDDIN = 3.6V
LCD
VROUT
VDDLCD
(V)
LCD
VROUT
VDDLCD
(V)
LCD
VROUT
VDDLCD
(V)
LCD
VROUT
VDDLCD
(V)
0
2.86
4
2.57
8
3.45
12
3.16
1
2.79
5
2.50
9
3.38
13
3.09
2
2.72
6
2.43
10
3.31
14
3.02
3
2.64
7
2.36
11
3.23
15
2.95
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1093
Table 46-20.
LCD Buffers Characteristics
Symbol
Parameter
Conditions
IDDIN
Current consumption (VDDIN)
LDO enabled
ZOUT
Buffer output impedance
CLOAD
Capacitive output load
tr / tf
Min
Typ
Max
Unit
–
25
35
µA
GPIO in LCD mode (SEG or COM)
200
500
1500
Ω
–
10p
–
50n
F
–
–
Rising or falling time
CLOAD = 10 pF
95% convergence
CLOAD = 50 nF
3
225
µs
46.5.4 VDDCORE Brownout Detector
Table 46-21.
Core Power Supply Brownout Detector Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT-
Negative-going input threshold voltage
(VDDCORE) (1)
–
0.98
1.0
1.04
V
VIT+
Positive-going input threshold voltage
(VDDCORE)
–
0.80
1.0
1.08
V
VHYST
Hysteresis voltage
VIT+ - VIT-
–
25
50
mV
td-
VIT- detection propagation time
VDDCORE = VIT+ to (VIT- - 100mV)
–
200
300
ns
tSTART
Start-up time
From disabled state to enabled state
–
–
300
µs
IDDCORE
Current consumption (VDDCORE)
Brownout detector enabled
–
–
15
µA
IDDIO
Current consumption (VDDIO)
Brownout detector enabled
–
–
18
µA
Note:
1. The product is guaranteed to be functional at VIT-.
Figure 46-13. Core Brownout Output Waveform
VDDCORE
VIT+
VITt
BODCORE_out
td-
td+
t
Figure 46-14. Core Brownout Transfer Characteristics
BODCORE_out
Vhyst
Increasing Supply
Decreasing Supply
VDDCORE
Vth-
1094
Vth+
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
46.5.5 VDDCORE Power-On-Reset
Table 46-22.
Core Power Supply Power-On-Reset Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT-
Negative-going input threshold voltage
(VDDCORE)
–
0.71
0.9
1.02
V
VIT+
Positive-going input threshold voltage
(VDDCORE)
–
0.80
1.0
1.08
V
VHYS
Hysteresis voltage
VIT+ - VIT-
–
60
110
mV
td-
VIT- detection propagation time
VDDCORE = VIT+ to (VIT- - 100mV)
–
–
15
µs
tSTART
Start-up time
VDDCORE rising from 0 to final value.
Time to release reset signal.
–
–
300
µs
IDDCORE
Current consumption (VDDCORE)
–
–
–
6
µA
IDDIO
Current consumption (VDDIO)
–
–
–
9
µA
46.5.6 VDDIO Supply Monitor
Table 46-23.
VDDIO Supply Monitor
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VTH-
Programmable range of negativegoing input threshold voltage (VDDIO)
16 selectable steps
1.6
–
3.4
V
ACC
VTH- accuracy
With respect to programmed value
-2.5
–
+2.5
%
–
–
30
40
mV
VHYST
Hysteresis
(2)
(1)
IDDON
Current consumption (VDDIO)
On with a 100% duty cycle.
–
20
40
µA
tON
Start-up time
From OFF to ON
–
–
300
µs
Notes:
1. The average current consumption can be reduced by using the supply monitor in Sampling mode. Refer to Section 20.
“Supply Controller (SUPC)”.
2. VHYST = VTH+ - VTH-. VTH+ is the positive-going input threshold voltage (VDDIO).
Table 46-24.
VDDIO Supply Monitor VTH- Threshold Selection
Digital Code
Threshold
Typ (V)
Digital Code
Threshold
Typ (V)
Digital Code
Threshold
Typ (V)
Digital Code
Threshold
Typ (V)
0000
1.60
0100
2.08
1000
2.56
1100
3.04
0001
1.72
0101
2.20
1001
2.68
1101
3.16
0010
1.84
0110
2.32
1010
2.80
1110
3.28
0011
1.96
0111
2.44
1011
2.92
1111
3.40
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1095
46.5.7 VDDBU Power-On-Reset
Table 46-25.
Zero-Power-On POR (Backup POR) Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VTH+
Positive-going input threshold voltage (VDDBU)
At startup
1.45
1.53
1.59
V
VTH-
Negative-going input threshold voltage (VDDBU)
–
1.35
1.45
1.55
V
IDDBU
Current consumption
Enabled
–
300
700
nA
tres
Reset time-out period
–
100
240
500
µs
Figure 46-15. Zero-Power-On Reset Characteristics
VDDBU
VIT+
VIT-
PORBUSW_out
46.5.8 VDDIO Power-On-Reset
Table 46-26.
Zero-Power-On POR (VDDIO POR) Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VTH+
Positive-going input threshold voltage (VDDIO)
At startup
1.45
1.53
1.59
V
VTH-
Negative-going input threshold voltage (VDDIO)
–
1.35
1.45
1.55
V
IDDIO
Current consumption
–
–
300
700
nA
tres
Reset time-out period
–
100
240
500
µs
1096
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
46.5.9 32-kHz RC Oscillator
Table 46-27.
32-kHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDBU
Supply voltage range (VDDBU)
–
1.62
3.3
3.6
V
f0
Frequency initial accuracy
26
32
39
kHz
df/dV
Frequency drift with VDDBU
0.5
1.5
2.5
%/V
dF/dT
Frequency drift with temperature
TA = [-40°C to +27°C]
–
+8
+17
TA = [27°C to 85°C]
–
+6
+13
Duty
Duty cycle
–
48
50
52
%
tON
Start-up time
–
–
–
100
µs
IDDON
Current consumption (VDDBU)
–
–
150
300
nA
Conditions
Min
Typ
Max
Unit
–
1.08
1.2
1.32
V
–
4
–
12
MHz
-40°C < TA < +85°C
–
–
±30
%
–
–
VDDBU = 3.3V,
TA = 27°C
VDDBU from 1.6V to 3.6V
%
46.5.10 4/8/12 MHz RC Oscillator
Table 46-28.
4/8/12-MHz RC Oscillators Characteristics
Symbol
Parameter
VDDCORE
Supply voltage range (VDDCORE)
fRANGE
ACC4
(1)
Output frequency range
4 MHz range;
total accuracy
VDDCORE from 1.08V to 1.32V
ACC8
8 MHz range;
TA= 25°C
total accuracy
0°C < TA < +70°C
-40°C < TA < +85°C
±1.0
±3.0
%
±5
VDDCORE from 1.08V to 1.32V
ACC12
12 MHz range;
TA= 25°C
total accuracy
0°C < TA < +70°C
–
–
-40°C < TA < +85°C
8 MHz
Frequency trimming step size
Duty
Duty cycle
–
45
tON
Startup time, MOSCRCEN from 0 to 1
–
tSTAB
Stabilization time on RC frequency
change (MOSCRCF)
–
IDDON
Active current consumption
(VDDCORE)
–
12 MHz
Note:
%
47
–
kHz
50
55
%
–
–
10
µs
–
–
5
µs
50
68
65
86
82
102
4 MHz
8 MHz
±3.0
±5
fSTEP
12 MHz
±1.0
–
64
µA
1. The frequency range can be configured in the PMC Clock Generator.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1097
46.5.11 32.768-kHz Crystal Oscillator
Table 46-29.
32.768-kHz Crystal Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDBU
Supply voltage range (VDDBU)
–
1.62
3.3
3.6
V
fREQ
Operating frequency
Normal mode with crystal
–
–
32.768
kHz
Duty
Duty Cycle
–
40
50
60
%
CCRYSTAL = 12.5 pF
RS(1) < 50 kΩ
tON
CCRYSTAL = 6 pF
Start-up time
(1)
RS
Current consumption (VDDBU)
300
–
RS(1) < 100 kΩ
IDDON
900
< 65 kΩ
–
ms
CCRYSTAL = 12.5 pF
1200
CCRYSTAL = 6 pF
500
CCRYSTAL = 12.5 pF
450
950
CCRYSTAL = 6 pF
280
850
350
1050
RS(1) < 100 kΩ
CCRYSTAL = 6 pF
RS(1) < 20 kΩ
CCRYSTAL = 6 pF
–
nA
220
PON
Drive level
–
–
–
0.1
µW
RF
Internal resistor
Between XIN32 and XOUT32
–
10
–
MΩ
CCRYSTAL
Allowed crystal capacitive load
From crystal specification.
6
–
12.5
pF
CLEXT32K
External capacitor
on XIN32 and XOUT32
–
–
–
24
pF
CPARA32K
Internal parasitic capacitance
Between XIN32 and XOUT32
0.6
0.7
0.8
pF
Note:
1. RS is the series resistor.
Figure 46-16. 32.768-kHz Crystal Oscillator Schematic
SAM4
CPARA32K
XIN32
CPCB
CLEXT32K
XOUT32
CPCB
CLEXT32K
CLEXT32K = 2 × (CCRYSTAL – CPARA32K – CPCB / 2)
where CPCB is the ground referenced parasitic capacitance of the printed circuit board (PCB) on XIN32 and
XOUT32 tracks. As an example, if the crystal is specified for a 12.5 pF load, with CPCB = 1 pF (on XIN32 and on
XOUT32), CLEXT32K = 2 x (12.5 - 0.7 - 0.5) = 22.6 pF.
1098
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 46-30 summarizes recommendations for 32.768 kHz crystal selection.
Table 46-30.
Recommended Crystal Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ESR
Equivalent Series Resistor (RS)
Crystal @ 32.768 kHz
–
50
100
kΩ
CM
Motional capacitance
Crystal @ 32.768 kHz
0.6
–
3
fF
CSHUNT
Shunt capacitance
Crystal @ 32.768 kHz
0.6
–
2
pF
46.5.12 3- to 20-MHz Crystal Oscillator
Table 46-31.
3- to 20-MHz Crystal Oscillator Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDIO
Supply voltage range (VDDIO)
–
1.62
3.3
3.6
V
VDDPLL
Supply voltage range (VDDPLL)
–
1.08
1.2
1.32
V
fOSC
Operating frequency range
Normal mode with crystal
3
16
20
MHz
Duty
Duty cycle
–
40
50
60
%
Start-up time
tON
3 MHz, CSHUNT = 3pF
14.5
8 MHz, CSHUNT = 7pF
4
16 MHz, CSHUNT = 7pF with CM = 8 fF
–
–
1.4
16 MHz, CSHUNT = 7pF with CM = 1.6 fF
2.5
20 MHz, CSHUNT = 7pF
Current consumption
On VDDIO
1
3 MHz(1)
230
350
8 MHz(2)
300
400
16 MHz
(3)
390
470
20 MHz
(4)
450
560
–
IDD_ON
On VDDPLL
3 MHz(1)
8 MHz
(2)
µA
6
7
12
14
(3)
20
23
20 MHz(4)
24
30
16 MHz
3 MHz
Drive level
PON
8 MHz
ms
15
–
–
30
16 MHz, 20 MHz
µW
50
Rf
Internal resistor
Between XIN and XOUT
–
0.5
–
MΩ
CCRYSTAL
Allowed crystal capacitive load
From crystal specification
12
–
18
pF
CLEXT
External capacitor on XIN and XOUT
–
–
–
18
pF
CLINT
Integrated load capacitance
Between XIN and XOUT
7.5
9.5
10.5
pF
Notes:
1.
2.
3.
4.
RS = 100-200 Ohms; CS = 2.0 - 2.5 pF; CM = 2 – 1.5 fF(typ, worst case) using 1 kΩ serial resistor on XOUT.
RS = 50-100 Ohms; CS = 2.0 - 2.5 pF; CM = 4 - 3 fF(typ, worst case).
RS = 25-50 Ohms; CS = 2.5 - 3.0 pF; CM = 7 - 5 fF (typ, worst case).
RS = 20-50 Ohms; CS = 3.2 - 4.0 pF; CM = 10 - 8 fF(typ, worst case).
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1099
Figure 46-17. 3- to 20-MHz Crystal Oscillator Schematic
SAM4
CLINT
XOUT
XIN
R = 1K if Crystal Frequency
is lower than 8 MHz
CPCB
CPCB
CLEXT
CLEXT
CLEXT = 2 x (CCRYSTAL – CLINT – CPCB / 2).
where CPCB is the ground referenced parasitic capacitance of the printed circuit board (PCB) on XIN and XOUT
tracks. As an example, if the crystal is specified for an 18-pF load, with C PCB = 1 pF (on XIN and on XOUT),
CLEXT = 2 x (18 - 9.5 - 0.5) = 16 pF.
Table 46-32 summarizes recommendations to be followed when choosing a crystal.
Table 46-32.
Symbol
Recommended Crystal Characteristics
Parameter
Conditions
Min
Typ
Fundamental @ 3 MHz
Equivalent Series Resistor (RS)
Fundamental @ 12 MHz
Unit
200
Fundamental @ 8 MHz
ESR
Max
100
–
–
80
Fundamental @ 16 MHz
80
Fundamental @ 20 MHz
50
Ω
CM
Motional capacitance
–
–
–
8
fF
CSHUNT
Shunt capacitance
–
–
–
7
pF
46.5.13 Crystal Oscillator Design Considerations
When choosing a crystal for the 32768-Hz slow clock oscillator or for the 3- to 20-MHz oscillator, several
parameters must be taken into account. Important parameters are as follows:
1100
Crystal Load Capacitance.
The total capacitance loading the crystal, including the oscillator’s internal parasitics and the PCB parasitics,
must match the load capacitance for which the crystal’s frequency is specified. Any mismatch in the load
capacitance with respect to the crystal’s specification will lead to inaccurate oscillation frequency.
Crystal Drive Level.
Use only crystals with the specified drive levels greater than the specified MCU oscillator drive level.
Applications that do not respect this criterion may damage the crystal.
Crystal Equivalent Series Resistor (ESR).
Use only crystals with the specified ESR lower than the specified MCU oscillator ESR. In applications where
this criterion is not respected, the crystal oscillator may not start.
Crystal Shunt Capacitance.
Use only crystal with the specified shunt capacitance lower than the specified MCU oscillator shunt
capacitance. In applications where this criterion is not respected, the crystal oscillator may not start.
PCB Layout Considerations.
To minimize inductive and capacitive parasitics associated with XIN, XOUT, XIN32, XOUT32 nets, it is
recommended to route them as short as possible. It is also of prime importance to keep those nets away
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
from noisy switching signals (clock, data, PWM, etc.). A good practice is to shield them with a quiet ground
net to avoid coupling to neighboring signals.
46.5.14 PLLA, PLLB Characteristics
Table 46-33.
PLLA Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDPLL
Supply voltage range (VDDPLL)
–
1.08
1.2
1.32
V
fIN
Input frequency range
–
30
32.768
34
kHz
fOUT
Output frequency range
–
7.5
8.192
8.5
MHz
NRATIO
Frequency multiplying ratio (MULA +1)
–
–
250
–
–
JP
Period jitter
Peak value
–
4
–
ns
tON
Start-up time
From OFF to output oscillations
(Output frequency within 10% of target
frequency)
–
–
250
µs
tLOCK
Lock time
From OFF to PLL locked
–
–
2.5
ms
IPLLON
Active mode current consumption
(VDDPLL)
fOUT = 8.192 MHz
–
50
–
µA
IPLLOFF
OFF mode current consumption
(VDDPLL)
0.05
0.30
0.05
5
Table 46-34.
@25°C
–
Over the temperature range
µA
PLLB Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VVDDPLL
Supply voltage range (VDDPLL)
–
1.08
1.2
1.32
V
fIN
Input frequency range
–
3
–
32
MHz
fOUT
Output frequency range
–
80
–
240
MHz
NRATIO
Frequency multiplying ratio (MULB +1)
–
3
–
62
–
–
2
–
24
–
–
–
60
150
µs
0.94
1.2
1.2
1.5
2.1
2.5
3.34
4
QRATIO
tON
Frequency dividing ratio
(DIVB)
Start-up time
Active mode @ 80 MHz @1.2V
IDDPLL
Current consumption on VDDPLL
Active mode @ 96 MHz @1.2V
Active mode @ 160 MHz @1.2V
Active mode @ 240 MHz @1.2V
–
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
mA
1101
46.5.15 Temperature Sensor Characteristics
The temperature sensor provides an output voltage (VT) that is proportional to absolute temperature (PTAT). This
voltage can be measured through the channel number 7 of the 10-bit ADC. Improvement of the raw performance
of the temperature sensor acquisition can be achieved by performing a single temperature point calibration to
remove the initial inaccuracies (VT and ADC offsets).
Table 46-35.
Temperature Sensor Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDIN
Supply voltage range (VDDIN)
–
2.4
–
3.6
V
VT
Output voltage
TJ = 27° C
1.34
1.44
1.54
V
dVT/dT
Output voltage sensitivity to
temperature
–
4.2
4.7
5.2
mV/°C
dVT/dV
VT variation with VDDIN
VDDIN from 2.4V to 3.6V
–
–
1
mV/V
tS
VT settling time
When VT is sampled by the 10-bit ADC,
the required track time to ensure 1°C
accurate settling
–
–
1
µs
After offset calibration
Over TJ range [-40°C to +85°C]
–
±5
±7
°C
After offset calibration
Over TJ range [0°C to +80°C]
–
±4
±6
°C
–
–
5
10
µs
50
70
80
µA
Temperature accuracy(1)
TACC
tON
Start-up time
Current consumption
–
IVDDIN
Note:
1. Does not include errors due to A/D conversion process.
46.5.16 Optical UART RX Transceiver Characteristics
Table 46-36 gives the description of the optical link transceiver for electrically isolated serial communication with
hand-held equipment, such as calibrators compliant with standards ANSI-C12.18 or IEC62056-21 (only available
on UART1).
Table 46-36.
Transceiver Characteristics
Symbol
Parameter
Conditions
VDDIO
Supply voltage range (VDDIO)
–
IDD
Current consumption
VTH
Comparator threshold
OPT_CMPTH field in Section 35.6.2 “UART
Mode Register” (UART1)
-20
–
+20
mV
VHYST
Hysteresis
–
10
20
40
mV
tPROP
Propagation time
With 100 mVpp square wave input around threshold
–
–
5
µs
tON
Start-up time
–
–
–
100
µs
ON
OFF
Min
Typ
Max
Unit
3
3.3
3.6
V
25
35
–
0.1
µA
According to the programmed threshold. See the
1102
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
46.5.17 10-bit ADC Characteristics
Table 46-37.
ADC Power Supply Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDIN
Supply voltage range (VDDIN)
–
2.4
3.3
3.6
V
ADC ON , Internal Voltage Reference
ON generating ADVREF = 3.0V
–
450
700
ADC ON(1), Internal Voltage Reference
OFF, ADVREF externally supplied
–
(1)
Current consumption on VDDIN
IVDDIN
Note:
µA
Symbol
ADC Voltage Reference Input Characteristics (ADVREF pin)
Parameter
(1)
Conditions
Min
Typ
Max
Unit
2.4
–
VDDIN
V
9
14
19
kΩ
+35%
µA
VADVREF
ADVREF input voltage range
Internal Voltage Reference OFF
RADVREF
ADVREF input resistance
ADC ON, Internal Voltage Reference
OFF
ADVREF = 2.4V
Current consumption on ADVREF
IADVREF
170
ADVREF = 3.3V
-35%
ADVREF = 3.6V
CADVREF
Decoupling capacitor on ADVREF
235
260
–
100
–
–
nF
Min
Typ
Max
Unit
–
–
1. ADVREF input range limited to VDDIO if VDDIO < VDDIN.
Table 46-39.
ADC Timing Characteristics
Symbol
Parameter
fCK_ADC
ADC clock frequency
Conditions
3.0V ≤ VDDIN ≤ 3.6
16
2.4V ≤ VDDIN ≤ 3.0
tCONV
ADC conversion time
(1)
fCK_ADC = 16 MHz, tTRACK = 500 ns
Sampling rate
(2)
1.95
–
Start-up time
–
tTRACK
Track and hold time(3)
Notes:
ADC only
–
µs
510
kS/s
–
380
VDDIN > 2.4V, fCK_ADC = 14 MHz
tON
MHz
14
VDDIN > 3V, fCK_ADC = 16 MHz
FS
350
1. Average current consumption performing conversion in Free Run mode @ 16 MHz ADC Clock. FS = 510 kS/s.
Table 46-38.
Note:
220
–
2.4V ≤ VDDIN ≤ 3.0
1000
3.0V < VDDIN < 3.6V
500
–
40
µs
–
–
ns
1. tCONV = (TRACKTIM + 24) / fCK_ADC.
2. FS = 1 / tCONV.
3. Refer to Section 46.5.17.1 “Track and Hold Time versus Source Output Impedance, Effective Sampling Rate”.
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1103
Table 46-40.
Symbol
Parameter
Notes:
Conditions
(1)
FSR
CIN
ADC Analog Input Characteristics
Analog input full scale range
–
Accounts for I/O input capacitance +
ADC sampling capacitor
1. If VVDDIO < VADVREF, full scale range is limited to VDDIO.
2. Refer to Figure 46-18 “Simplified Acquisition Path”.
Input capacitance(2)
Table 46-41.
Typ
Max
Unit
0
–
VADVREF
V
–
–
10
pF
Static Performance Characteristics(1)
Symbol
Parameter
Conditions
RADC
Native ADC resolution
RADC_AV
Resolution with digital averaging
INL
Integral non linearity
DNL
Differential non linearity
OE
Offset error
GE
Gain error
Note:
Min
Min
Typ
Max
Unit
–
–
10
–
Bits
Refer to Section 40. “Analog-to-Digital
Converter (ADC)”
10
–
12
Bits
-2
–
+2
LSB
-1
–
+1
LSB
-5
–
5
LSB
-3
–
+3
LSB
Min
Typ
Max
Unit
fCK_ADC = 16 MHz
Errors with respect to the best fit line
method
1. In this table, values expressed in LSB refer to the Native ADC resolution (i.e., a 10-bit LSB).
Table 46-42.
Dynamic Performance Characteristics
Symbol
Parameter
Conditions
SNR
Signal to noise ratio
fCK_ADC = 16 MHz,
57
60
–
dB
THD
Total harmonic distortion
VADVREF = VDDIN,
–
-68
-55
dB
SINAD
Signal to noise and distortion
fIN = 50 kHz,
52
59
–
dB
Effective number of bits
VINPP = 0.95 x VADVREF
8.3
9.6
–
Bits
ENOB
1104
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
46.5.17.1 Track and Hold Time versus Source Output Impedance, Effective Sampling Rate
The following figure gives a simplified view of the acquisition path.
Figure 46-18. Simplified Acquisition Path
VDDIO
Mux.
ADC
Input
Zsource
Track & Hold
10-bit
ADC
Core
Ron
Csample
SAM4
During its tracking phase, the 10-bit ADC charges its sampling capacitor through various serial resistors: source
output resistor, multiplexer series resistor and the sampling switch series resistor. In case of high output source
resistance (low power resistive divider, for example), the track time must be increased to ensure full settling of the
sampling capacitor voltage. The following formulas give the minimum track time that guarantees a 10-bit accurate
settling:
VDDIN > 3.0V: tTRACK (ns) = 0.12 x RSOURCE(Ω) + 500
VDDIN ≤ 3.0V: tTRACK (ns) = 0.12 x RSOURCE(Ω) + 1000
According to the calculated track time ( t TRACK ), the actual track time of the ADC must be adjusted through
the TRACKTIM field in the ADC_MR register. TRACKTIM is obtained by the following formula:
TRACKTIM = floor
(
TTRACK
TCK_ADC
)
with tCK_ADC = 1 / fCK_ADC and floor(x) the mathematical function that rounds x to the greatest previous integer.
The actual conversion time of the converter is obtained by the following formula:
TCONV = (TRACKTIM + 24) x TCK_ADC
When converting in Free Run mode, the actual sampling rate of the converter is (1 / TCONV) or as defined by the
following formula:
FS =
FCK_ADC
(TRACKTIM + 24)
The maximum source resistance with the actual TRACKTIM setting is:
RSOURCE_MAX(Ω) = ((TRACKTIM + 1) x tCK_ADC(ns) - 500) / 0.12 for VDDIN > 3.0V; or
RSOURCE_MAX(Ω) = ((TRACKTIM + 1) x tCK_ADC(ns) - 1000) / 0.12 for VDDIN ≤ 3.0V
SAM4CM Series [DATASHEET]
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1105
Example:
Calculated track time is lower than actual ADC clock period
Assuming: fCK_ADC = 1 MHz (tCK_ADC = 1 µs), RSOURCE = 100Ω and VDDIN = 3.3V
The minimum required track time is: tTRACK = 0.12 x 100 + 500 = 512 ns
tTRACK being less than tCK_ADC, TRACKTIM is set to 0. Actual track time is tCK_ADC = 1 µs
The calculated sampling rate is: fS = 1 MHz / 24 = 41.7 kHz
The maximum allowable source resistance is: RSOURCE_MAX = (1000 - 500) / 0.12 = 4.1 kΩ
Example:
Calculated track time is greater than actual ADC clock period
Assuming: fCK_ADC = 16 MHz (tCK_ADC = 62.5 ns), RSOURCE = 600Ω and VDDIN = 2.8V
The minimum required track time is: tTRACK = 0.12 x 600 + 1000 = 1072 ns
TRACKTIM = floor (1072 / 62.5) = 17. Actual track time is: (17 + 1) x tCK_ADC = 1.125 µs
The calculated sampling rate is: fS = 16 MHz / (24 + 17) = 390.2 kHz
The maximum allowable source resistance is: RSOURCE_MAX = (1125 - 1000) / 0.12 = 1.04 kΩ
46.5.18 Programmable Voltage Reference Characteristics
SAM4CM embeds a programmable voltage reference designed to drive the 10-bit ADC ADVREF input. Table 4643 shows the electrical characteristics of this internal voltage reference. If necessary, this voltage reference can be
bypassed with some level of configurability: the user can either choose to feed the ADVREF input with an external
voltage source or with the VDDIO internal power rail. Refer to programming details in Section 40.7.18 “ADC
Analog Control Register”.
Table 46-43.
Programmable Voltage Reference Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDIN
Voltage reference supply range
–
2
–
3.6
V
VADVREF
Programmable output range
1.6
–
3.4
V
ACC
Reference voltage accuracy
With respect to the programmed value.
VDDIN = 3.3V; TJ = 25°C
-3
–
3
%
TC
Temperature coefficient
Box method(1)
–
–
250
ppm/°C
Refer to Table 46-44.
VDDIN > VADVREF + 100mV
100
VDDIN = 2.4V
tON
Start-up time
VDDIN = 3V
–
–
VDDIN = 3.6V
ZLOAD
Load impedance
Resistive
Capacitive
IVDDIN
Current consumption on VDDIN(2)
ADC is OFF
Notes: 1. TC = ( max(VADVREF) - min(VADVREF) ) / ( (TMAX - TMIN) * VADVREF(25°C) ).
2. Does not include the current consumed by the ADC ADVREF input if ADC is ON
1106
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
70
µs
40
4
–
–
kΩ
0.1
–
1
µF
–
20
30
µA
Table 46-44.
Programmable Voltage Reference Selection Values
Selection Value(1)
ADVREF
Notes
0
2.40
Default value
1
2.28
–
2
2.16
–
3
2.04
–
4
1.92
–
5
1.80
–
6
1.68
–
7
1.55
Min value
8
3.38
Max value
9
3.25
–
A
3.13
–
B
3.01
–
C
2.89
–
D
2.77
–
E
2.65
–
F
2.53
–
Note:
1.
Voltage reference values are configurable in ADC_ACR.IRVS.
46.5.19 EMAFE Characteristics
Unless otherwise specified, external components characteristics according to the typical application diagram in
the EMAFE section are as follows:
CVREF=1 μF and CVDDA=1 μF
EMAFE clock = 4.096 MHz
VDDIN_AFE = VDDIO = 3.3V
Noise bandwidth = [30 Hz, 2 kHz] for measurement channels characteristics
TJ = [-40°C; +100°C]
Table 46-45.
EMAFE Power Supply Characteristics
Symbol
Parameter
Comments
Min
Typ
Max
Unit
VVDDIN_AFE
Supply voltage range (VDDIN_AFE)
–
3.0
3.3
3.6
V
VVDDIO
Supply voltage range (VDDIO)
–
3.0
3.3
3.6
VVDDA
Supply voltage range (VDDA)
–
2.7
2.8
2.9
V
–
1.4 + k
× 0.75
–
mA
EMAFE clock @ 4.096 MHz
IDDON
Current consumption on (VDDIN_AFE
+ VDDIO)
VVDDIO = VVDDIN_AFE = 3.3V
k Channels ON (k≥1),
Voltage reference ON,
VDDA LDO regulator ON.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1107
Table 46-46.
EMAFE VDDIO Power-On-Reset Thresholds(1)
Symbol
Parameter
Comments
Min
Typ
Max
Unit
VT_RISE
VDDIO rising threshold
DC level
2.5
2.6
2.8
V
VT_FALL
VDDIO falling threshold
DC level
2.35
2.5
2.65
V
VT_HYST
VT_RISE - VT_FALL
–
90
120
180
mV
Note:
1. In case of power fail conditions on VDDIO, this POR only resets EMAFE-related settings.
Table 46-47.
Current or Voltage Measurement Channel Electrical Characteristics
Symbol
Parameter
VVDDA
Operating supply voltage
(1)
IDDON
Channel supply current
VDDIO and VDDA
in
FEMAFE_CLK
Master clock input frequency
VIND_FS
A/D converter input referred full
scale voltage(2)
Comments
Min
Typ
Max
Unit
–
2.7
2.8
2.9
V
OFF
–
–
0.2
µA
ON
–
0.75
1
mA
3.9
4.096
4.3
MHz
–
1.2 / G
–
VPP
-20
–
20
mV
400 / G
480 / G
560 / G
kΩ
–
84
–
–
78
–
Gain = 2, VIND = 0.500 VPP
–
84
–
Gain = 4, VIND = 0.250 VPP
–
82
–
Gain = 8, VIND = 0.125 VPP
–
81
–
Gain = 1
–
21
–
Gain = 2
–
10
–
Gain = 4
–
6
–
Gain = 8
–
3.3
–
Gain = 1
–
470
–
Gain = 2
–
220
–
Gain = 4
–
130
–
Gain = 8
–
73
–
TJ0 = 23°C; VREF = 1.2V
-3
–
3
%
–
-5
–
ppm /°C
-5 / G
–
5/G
mV
-2
–
+2
µV/°C
–
VREF = 1.2V
VIND = VVPx or VIND = VIPx - VINx
G: Channel Gain = {1, 2, 4 or 8}
VCM_IN
Common mode input voltage
range
ZIN0
Common mode input impedance
at TJ0 = 23°C
(VIPx + VINx) / 2
G: Channel Gain = {1, 2, 4 or 8}
On VPx, IPx , INx pins.
FEMAFE_CLK = 4.096 MHz
Gain = 1, VIND = 1.000 VPP
Peak signal to noise and distortion
ratio.
SINADPEAK
fIN = 45 Hz to 66 Hz
BW = [30Hz, 2 kHz]
EN
SN
Input referred noise voltage
integrated over [30 Hz, 2 kHz]
Input referred noise voltage
density at fundamental frequency.
(Between 45 Hz and 66 Hz).
EG0
Gain error
TCG
Channel gain drift with
temperature(4)
Gain = 1, VIND = 0.500
VPP(3)
dB
µVRMS
nV/√Hz
-40°C < TJ < 100°C,
VREF = 1.2V
RSOURCE = 3kΩ
VOS0
Input referred offset
TJ0 = 23°C
TCVOS
VOS drift with temperature
-40°C < TJ < 100°C
1108
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Notes:
1. Current consumption per measurement channel.
2. VIND may be limited by the recommended input voltage on analog input pins (+/-0.25V, refer to Table 46-5 “Recommended
Operating Conditions on Input Pins”).
3. Corresponds to the maximum signal on the voltage channel(s).
4. Includes the input impedance drift with temperature.
Table 46-48.
EMAFE Precision Voltage Reference and Die Temperature Sensor Characteristics
Symbol
Parameter
Comments
Min
Typ
Max
Unit
VVDDA
Operating supply voltage
–
2.7
2.8
2.9
V
OFF
–
–
0.1
IVDDA
Supply current
ON
–
70
100
VREF_AFE0
Output voltage initial accuracy
1.142
1.144
1.146
Uncompensated (SAM4CMS4 devices)
–
50
–
Using factory-programmed calibration
registers
–
10
30
µA
TCVREF_U
TCVREF_C
VREF drift with temperature
(1)
At TJ0 = 23°C
V
ppm /°C
ROUT
VREF_AFE output resistance
–
200
500
800
kΩ
DTEMP_Lin
Die temperature sensor,
digital reading linearity
–
–
±2
–
°C
IVREF_OFF
Current in VREF pin when
internal voltage reference is
OFF
–
-100
–
100
nA
Note:
1. TC is defined using the box method: TC = ( VREF_AFE_MAX - VREF_AFE_MIN ) / ( VREF_AFE0 x ( TMAX - TMIN ) ).
Table 46-49.
EMAFE VDDA LDO Regulator
Symbol
Parameter
Comments
Min
Typ
Max
Unit
VVDDIN
Operating supply voltage
–
3.0
3.3
3.6
V
OFF
–
–
0.1
IVDDIN
Supply current
ON
–
–
250
IO
Output current
–
–
–
15
mA
VO
DC output voltage
IO= 0 mA.
2.75
2.8V
2.85
V
ΔVO / ΔIO
Static load regulation
IO: 0 to IOMAX
-5
–
–
mV/mA
ΔVO/
ΔVDDIN
Static line regulation
VDDIN: 3.0 to 3.6V
-5
–
5
mV/V
f = DC to 2000 Hz
–
40
–
PSRR
Power supply rejection ratio
f = 1 MHz
–
40
–
VO from 0 to 95% of final value.
IO= 0 mA.
–
–
1
ms
0.5
1
4.7
µF
5
10
300
mΩ
tON
Start-up time
CO
Stable output capacitor range
µA
dB
Capacitive
Resistive
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1109
46.6
Embedded Flash Characteristics
46.6.1 Embedded Flash DC Characteristics
Table 46-50.
Symbol
DC Flash Characteristics
Parameter
Conditions
Typ
Max
Unit
Maximum Read Frequency onto VDDCORE = 1.2V @ 25°C
16
25
mA
Maximum Read Frequency onto VDDIO = 3.3V @ 25°C
3
5
Maximum Read Frequency onto VDDCORE = 1.2V @ 25°C
10
18
Maximum Read Frequency onto VDDIO = 3.3V @ 25°C
3
5
- Onto VDDCORE = 1.2V @ 25°C
3
5
- Onto VDDIO = 3.3V @ 25°C
10
15
- Onto VDDCORE = 1.2V @ 25°C
3
5
- Onto VDDIO = 3.3V @ 25°C
10
15
Random 128-bit Read:
Random 64-bit Read:
ICC
Active current
mA
Program:
mA
Erase:
mA
46.6.2 Embedded Flash AC Characteristics
Table 46-51.
AC Flash Characteristics
Parameter
Min
Typ
Max
Unit
Write page (512 bytes)
Conditions
–
1.5
3
ms
Erase page
–
10
50
ms
Erase block (4 Kbytes)
–
50
200
ms
Program/ Erase Operation
Erase sector
–
400
950
ms
Cycle Time
Full chip erase
- 1 Mbyte
- 512 Kbytes
–
9
5.5
18
11
s
Lock/Unlock time per region
–
1.5
3
ms
Data Retention
Not powered or powered
–
20
–
Years
Endurance
Write/Erase cycles per page, block or sector @ 85°C
10K
–
–
Cycles
1110
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
46.6.2.1 SAM4CM4/8/16 Flash Wait States and Operating Frequency
The maximum operating frequency given in Table 46-52 below is limited by the Embedded Flash access time when the
processor is fetching code out of it. The table gives the device maximum operating frequency depending on the FWS field
of the EFC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory.
Table 46-52.
SAM4CM4/8/16 Flash Wait State Versus Operating Frequency
FWS
(Flash Wait State)
Maximum Operating Frequency (MHz) @ TA = 85°C
VDDCORE = 1.08V
VDDIO = 1.62V to 3.6V
VDDCORE = 1.2V
VDDIO = 1.62V to 3.6V
VDDCORE = 1.08V
VDDIO = 2.7V to 3.6V
VDDCORE = 1.2V
VDDIO = 2.7V to 3.6V
0
16
17
20
21
1
33
35
40
42
2
51
52
61
63
3
67
70
81
85
4
85
87
98
106
5
100
105
–
120
6
–
121
–
–
46.6.2.2 SAM4CM32 Flash Wait States and Operating Frequency
The maximum operating frequency given in Table 46-53 below is limited by the Embedded Flash access time when the
processor is fetching code out of it. The table gives the device maximum operating frequency depending on the FWS field
of the EFC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory.
Table 46-53.
SAM4CM32 Flash Wait State Versus Operating Frequency
FWS
(Flash Wait State)
Maximum Operating Frequency (MHz) @ TA = 85°C
VDDCORE = 1.08V
VDDIO = 1.62V to 3.6V
VDDCORE = 1.2V
VDDIO = 1.62V to 3.6V
VDDCORE = 1.08V
VDDIO = 2.7V to 3.6V
VDDCORE = 1.2V
VDDIO = 2.7V to 3.6V
0
16
17
20
21
1
33
34
40
42
2
50
52
60
63
3
67
69
80
83
4
84
86
91
104
5
91
104
–
118
6
–
114
–
–
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1111
46.7
Power Supply Current Consumption
This section provides information about the current consumption on different power supply rails of the device.
It gives current consumption in low-power modes (Backup mode, Wait mode, Sleep mode) and in Active mode
(the application running from memory, by peripheral).
46.7.1 Backup Mode Current Consumption
Backup mode configurations and measurements are defined as follows:
Configuration A is used to achieve the lowest possible current consumption,
Configurations B, C and D are typical use cases with crystal oscillator, LCD and anti-tamper pins enabled.
Reminder: In Backup mode, the core voltage regulator is off and thus all the digital functions powered by
VDDCORE are off.
46.7.1.1 Backup Mode Configuration A: Embedded Slow Clock RC Oscillator Enabled
POR backup on VDDBU is disabled
RTC running
RTT enabled on 1 Hz mode
Force wake-up (FWUP) enabled
Current measurement as per Figure 46-19
46.7.1.2 Backup Mode Configuration B: 32.768 kHz Crystal Oscillator Enabled
POR backup on VDDBU is disabled
RTC running
RTT enabled on 1 Hz mode
Force wake-up (FWUP) enabled
Anti-tamper input TMP0 enabled
Current measurement as per Figure 46-19
Figure 46-19. Measurement Setup for Configurations A and B
AMP1
1.6V to 3.6V
SAM4
VDDBU
VDDIO
VDDIN
VDDLCD
VDDOUT
VDDCORE
VDDPLL
1112
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 46-54.
SAM4CM4/8/16 Typical Current Consumption Values for Backup Mode Configurations A and B
Conditions
Configuration A
Configuration B
VDDBU = 3.6V @25°C
580
760
VDDBU = 3.3V @25°C
520
700
VDDBU = 3.0V @25°C
480
680
VDDBU = 2.5V @25°C
440
640
VDDBU = 1.6V @25°C
400
600
VDDBU = 3.6V @85°C
1.57
1.80
VDDBU = 3.3V @85°C
1.50
1.70
VDDBU = 3.0V @85°C
1.44
1.65
VDDBU = 2.5V @85°C
1.30
1.56
VDDBU = 1.6V @85°C
1.16
1.43
Table 46-55.
Unit
nA
µA
SAM4CM32 Typical Current Consumption Values for Backup Mode Configurations A and B
Conditions
Configuration A
Configuration B
VDDBU = 3.6V @25°C
980
1100
VDDBU = 3.3V @25°C
900
1000
VDDBU = 3.0V @25°C
870
960
VDDBU = 2.5V @25°C
740
870
VDDBU = 1.6V @25°C
610
720
VDDBU = 3.6V @85°C
1.87
2.20
VDDBU = 3.3V @85°C
1.76
2.10
VDDBU = 3.0V @85°C
1.67
2.00
VDDBU = 2.5V @85°C
1.54
1.90
VDDBU = 1.6V @85°C
1.36
1.74
Unit
nA
µA
Figure 46-20. Typical Current Consumption in Backup Mode for Configurations A and B
SAM4Cx4/8/16
Config. A (25°C)
Config. A (85°C)
SAM4Cx32
Config. B (25°C)
Config. B (85°C)
Config. A (25°C)
2.2
2.2
2.0
2.0
1.6
B
1.4
1.2
A
1.0
0.8
B
1.4
A
1.2
25°C
1.0
0.6
B
0.6
0.4
A
0.4
0.2
Config. B (85°C)
1.6
0.8
25°C
Config. B (25°C)
85°C
1.8
85°C
IDDBU (uA)
IDDBU (uA)
1.8
Config. A (85°C)
B
A
0.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
VDDBU (V)
3.0
3.2
3.4
3.6
3.8
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDDBU (V)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1113
46.7.1.3 Backup Mode Configuration C: 32.768 kHz Crystal Oscillator Enabled
POR backup on VDDBU is disabled
RTC running
RTT enabled on 1 Hz mode
Force wake-up (FWUP) enabled
Anti-tamper input TMP0, TMP1 and RTCOUT0 enabled
Main crystal oscillator disabled
System IO lines PA30, PA31, PB[0...3] in GPIO Input Pull-up mode
All other GPIO lines in default state (refer to Section 11.4 “Peripheral Signal Multiplexing on I/O Lines”)
Current measurement as per Figure 46-21
46.7.1.4 Backup Mode Configuration D: 32.768 kHz Crystal Oscillator and LCD Enabled
POR backup on VDDBU is disabled
RTC running
RTT enabled on 1 Hz mode
LCD controller in Low-power mode, static bias and x64 slow clock buffer on-time drive time
LCD voltage regulator used
Force wake-up (FWUP) enabled
Anti-tamper input TMP0, TMP1 and RTCOUT0 enabled
Main crystal oscillator disabled
System IO lines PA30, PA31, PB[0..3] in GPIO Input Pull-up mode
All other GPIO lines in default state (refer to Section 11.4 “Peripheral Signal Multiplexing on I/O Lines”)
Current measurement as per Figure 46-21
Figure 46-21. Measurement Setup for Configuration C and D
AMP1
VDDBU
3V
AMP2
2.5V to 3.6V
SAM4
VDDIO
VDDIN
VDDLCD
VDDOUT
VDDCORE
VDDPLL
RTCOUT
TMPx
COMx
Note:
1114
SEGx
No current is drawn on VDDIN power input in Backup mode. The pin VDDIN can be left unpowered in Backup mode.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 46-56.
SAM4CM4/8/16 Typical Current Consumption Values for Backup Mode Configurations C and D
Configuration C
Conditions
IDD_BU - AMP1
Configuration D
IDD_IN/IO - AMP2
VDDIO = 3.6V @25°C
IDD_BU - AMP1
IDD_IN/IO - AMP2
3.6
VDDIO = 3.3V @25°C
10.5
3.3
0.05
VDDIO = 3.0V @25°C
Unit
9.9
0.05
2.9
9.3
VDDIO = 2.5V @25°C
2.4
8.3
VDDIO = 3.6V @85°C
7.8
15.9
µA
VDDIO = 3.3V @85°C
7.2
0.09
VDDIO = 3.0V @85°C
6.7
VDDIO = 2.5V @85°C
Table 46-57.
15.0
0.10
14.4
5.7
13.2
SAM4CM32 Typical Current Consumption Values for Backup Mode Configurations C and D
Configuration C
Conditions
IDD_BU - AMP1
Configuration D
IDD_IN/IO - AMP2
VDDIO = 3.6V @25°C
4.5
VDDIO = 3.3V @25°C
4.0
0.05
VDDIO = 3.0V @25°C
IDD_BU - AMP1
Unit
IDD_IN/IO - AMP2
10.7
9.9
0.05
3.6
9.1
VDDIO = 2.5V @25°C
3.1
8.3
VDDIO = 3.6V @85°C
10.7
18.2
µA
VDDIO = 3.3V @85°C
9.8
0.09
VDDIO = 3.0V @85°C
9.0
VDDIO = 2.5V @85°C
16.9
0.10
15.9
7.9
14.3
Figure 46-22. Typical Current Consumption in Backup Mode for Configurations C and D
SAM4CM4/8/16
Config. C (25°C)
Config. C (85°C)
SAM4CM32
Config. D (25°C)
Config. D (85°C)
Config. C (25°C)
20
20
18
18
14
D
85°C
12
10
8
6
25°C
C
85°C
4
2
Config. D (25°C)
Config. D (85°C)
16
IDDIO/IN (uA)
IDDIO/IN (uA)
16
Config. C (85°C)
14
12
10
8
25°C
85°C
C
6
4
25°C
D
85°C
25°C
2
0
0
2.4
2.6
2.8
3.0
3.2
VDDIO/IN (V)
3.4
3.6
3.8
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDDIO/IN (V)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1115
46.7.2 Wait Mode Current Consumption
Wait mode configuration and measurements are defined in Section 46.7.2.1 “Wait Mode Configuration”.
Reminder: In Wait mode, the core voltage regulator is on, but the device is not clocked. Flash Power mode can be
either in Standby mode or Deep Power-down mode. Wait mode provides a much faster wake-up compared to
Backup mode.
46.7.2.1 Wait Mode Configuration
32.768 kHz crystal oscillator running
4-MHz RC oscillator running
Main crystal and PLLs stopped
RTC running
RTT enabled on 1 Hz mode.
One wake-up pin (WKUPx) used in Fast Wake-up mode
Anti-tamper inputs TMP0, TMP1 and RTCOUT0 enabled
System IO lines PA30, PA31, PB[0...3] in GPIO Input Pull-up mode
All other GPIO lines in default state
Current measurement as per Figure 46-23
Figure 46-23. Measurement Setup for Wait Mode Configuration
AMP1
SAM4
VDDBU
3V
VDDIO
AMP2
3.3V
VDDIN
VDDLCD
VDDOUT
AMP3
VDDCORE
VDDPLL
Table 46-58.
SAM4CM4/8/16 Typical Current Consumption in Wait Mode
IDD_BU - AMP1
IDD_IN/IO - AMP2
IDD_CORE - AMP3
Conditions
@25°C
@85°C
@25°C
@85°C
@25°C
@85°C
Flash in Read-Idle mode
0.003
0.09
68
500
45
470
Flash in Standby mode
0.003
0.09
66
500
45
470
Flash in Deep Power-down mode
0.003
0.09
62
500
45
470
1116
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Unit
µA
Table 46-59.
SAM4CM32 Typical Current Consumption in Wait Mode
IDD_BU - AMP1
IDD_IN/IO - AMP2
IDD_CORE - AMP3
Conditions
@25°C
@85°C
@25°C
@85°C
@25°C
@85°C
Flash in Read-Idle mode
0.003
0.09
100
760
62
700
Flash in Standby mode
0.003
0.09
100
760
62
700
Flash in Deep Power-down mode
0.003
0.09
90
740
62
700
Unit
µA
46.7.3 Sleep Mode Current Consumption
Sleep mode configuration and measurements are defined in this section.
Reminder: The purpose of Sleep mode is to optimize power consumption of the device versus response time. In
this mode, only the core clocks of CM4P0 and/or CM4P1 are stopped.
Figure 46-24. Measurement Setup for Sleep Mode
SAM4
VDDBU
AMP2
3.3V
VDDIO
AMP1
VDDIN
VDDLCD
VDDOUT
AMP3
VDDCORE
VDDPLL
VDDIO = VDDIN = 3.3V
VDDCORE = 1.2V (Internal Voltage regulator used)
TA = 25°C
Core 0 clock (HCLK) and Core 1 (CPHCLK) clock stopped
Sub-system 0 Master Clock (MCK), Sub-system 1 Master Clock (CPBMCK) running at various frequencies
(PLLB used for frequencies above 12 MHz, fast RC oscillator at 12 MHz for the 12 MHz point, and fast RC
oscillator at 8 MHz divided by 1/2/4/8/16/32 for lower frequencies)
All peripheral clocks deactivated
No activity on I/O lines
VDDPLL not taken into account. Refer to Section 46.5.14 “PLLA, PLLB Characteristics” for further details
Current measurement as per Figure 46-24
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1117
Table 46-60.
SAM4CM4/8/16 Typical Sleep Mode Current Consumption Versus Frequency
Master Clock (MHz)
IDD_IN - AMP1
IDD_IO - AMP2
IDD_CORE - AMP3
120
14.26
0.22
10.83
100
11.96
0.22
9.09
84
10.1
0.22
7.68
64
7.78
0.22
5.92
48
5.93
0.22
4.48
32
5.02
0.22
3.16
24
3.85
0.22
2.4
12
1.26
0.03
1.21
8
0.88
0.03
0.83
4
0.50
0.03
0.45
2
0.32
0.03
0.27
1
0.26
0.03
0.22
0.5
0.22
0.03
0.20
0.25
0.19
0.03
0.18
Unit
mA
Table 46-61.
SAM4CM32 Typical Sleep Mode Current Consumption Versus Frequency
Master Clock (MHz)
IDD_IN - AMP1
IDD_IO - AMP2
IDD_CORE - AMP3
120
16.6
0.22
13.0
100
14.0
0.22
11.0
84
11.9
0.22
9.4
64
9.2
0.22
7.2
48
7.0
0.22
5.5
32
5.8
0.22
3.9
24
4.5
0.22
3.0
12
1.6
0.03
1.5
8
1.1
0.03
1.0
4
0.69
0.03
0.58
2
0.47
0.03
0.36
1
0.36
0.03
0.25
0.5
0.31
0.03
0.19
0.25
0.23
0.03
0.12
Unit
mA
1118
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 46-25. Typical Current Consumption in Sleep Mode
SAM4Cx4/8/16
IDDIN (AMP1)
IDDIO ( AMP2)
IDDCORE (AMP3)
18
18
16
16
14
14
12
12
IDD (mA)
IDD (mA)
IDDIO ( AMP2)
SAM4Cx32
10
8
IDDCORE (AMP3)
10
8
6
6
4
4
2
2
0
IDDIN (AMP1)
0
0
10
20
30
40
50
60
70
80
90
100
110
120
0
10
Master Clock Frequency (MHz)
20
30
40
50
60
70
80
90
100
110
120
Master Clock Frequency (MHz)
46.7.4 Active Mode Power Consumption
The current consumption configuration for Active mode, i.e., Core executing codes, is as follows:
VDDIO = VDDIN = 3.3V
VDDCORE = 1.2V (internal voltage regulator used)
TA = 25°C
Sub-system 0 Master Clock (MCK), Sub-system 1 Master Clock (CPBMCK) running at various frequencies
(PLLB used for frequencies above 12 MHz, fast RC oscillator at 12 MHz for the 12 MHz point, and fast RC
oscillator at 8 MHz divided by 1/2/4/8/16/32 for lower frequencies)
All peripheral clocks deactivated
No activity on IO lines
Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency
Current measurement as per Figure 46-26
Figure 46-26. Measurement Setup for Active Mode
SAM4
VDDBU
AMP2
3.3V
VDDIO
AMP1
VDDIN
VDDLCD
VDDOUT
AMP3
VDDCORE
VDDPLL
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1119
46.7.4.1 Test Setup 1: CoreMark™
CoreMark on Core 0 (CM4P0) running out of flash in 128-bit or 64-bit Access mode with and without Cache
Enabled. Cache is enabled above 0 WS.
Sub-system 1 Master Clock (CPBMCK) and Core Clock (CPHCLK) stopped and in reset state
Table 46-62.
SAM4CM4/8/16 Test Setup 1 Current Consumption
128-bit Flash Access
Cache Enabled
64-bit Flash Access
Cache Disabled
Cache Enabled
Cache Disabled
Clock IDD_IN IDD_I0 IDD_CORE IDD_IN IDD_I0 IDD_CORE IDD_IN IDD_I0 IDD_CORE IDD_IN IDD_I0 IDD_CORE
(MHz) (AMP1) (AMP2)
Unit
(AMP3)
(AMP1) (AMP2)
(AMP3)
(AMP1) (AMP2)
(AMP3)
(AMP1) (AMP2)
(AMP3)
120
21.8
0.27
18.5
24.4
2.0
21.1
21.5
0.27
18.3
21.2
1.9
17.9
100
18.1
0.27
15.4
21.6
1.8
18.9
18.1
0.27
15.4
19.0
1.8
16.3
84
15.3
0.27
13.0
18.8
1.7
16.6
15.3
0.27
13.0
16.8
1.7
14.5
64
11.8
0.27
10.1
15.2
1.5
13.5
11.8
0.27
10.1
14.1
1.4
12.5
48
9.2
0.27
7.9
11.7
1.4
10.5
9.2
0.27
7.9
11.3
1.3
10.0
32
7.2
0.27
5.6
9.5
1.2
7.9
7.2
0.27
5.6
9.3
1.2
7.7
24
5.6
0.27
4.3
7.5
1.1
6.2
5.6
0.27
4.3
7.2
1.2
5.9
12
2.4
0.09
2.4
3.1
0.9
3.1
2.4
0.09
2.4
3.1
1.0
3.1
8
1.6
0.09
1.6
2.1
0.7
2.1
1.6
0.09
1.6
2.1
0.9
2.1
4
1.0
0.09
1.0
1.4
0.5
1.4
1.0
0.09
1.0
1.4
0.8
1.4
2
0.70
0.09
0.69
0.90
0.40
0.90
0.70
0.09
0.69
0.70
0.70
0.70
1
0.54
0.09
0.53
0.65
0.30
0.65
0.55
0.09
0.54
0.65
0.40
0.65
0.5
0.47
0.09
0.46
0.50
0.20
0.50
0.47
0.09
0.46
0.60
0.20
0.60
0.25
0.25
0.09
0.24
0.26
0.10
0.25
0.25
0.09
0.24
0.36
0.10
0.25
1120
SAM4CM Series [DATASHEET]
mA
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 46-63.
SAM4CM32 Test Setup 1 Current Consumption
128-bit Flash Access
Cache Enabled
64-bit Flash Access
Cache Disabled
Cache Enabled
Cache Disabled
Clock
(MHz)
IDD_IN
IDD_I0
(AMP1)
(AMP2)
(AMP3)
(AMP1)
(AMP2)
(AMP3)
120
25.2
0.23
22.3
29.5
1.9
26.2
25.6
0.23
22.3
25.0
1.7
21.7
100
21.5
0.23
18.8
26.5
1.8
23.8
21.5
0.23
18.8
22.4
1.7
19.7
84
18.1
0.23
15.9
23.3
1.6
20.9
18.2
0.23
16.0
19.9
1.6
17.7
64
13.9
0.23
12.3
18.5
1.5
16.8
14.5
0.23
12.8
16.6
1.5
15.0
48
10.6
0.23
9.3
14.6
1.4
13.4
10.6
0.23
9.4
13.8
1.5
12.5
32
8.1
0.22
6.4
11.3
1.1
9.7
8.6
0.23
6.9
11.3
1.3
9.6
24
6.1
0.22
4.9
8.2
1.0
7.0
6.6
0.23
5.4
8.7
1.2
7.5
12
2.5
0.02
2.5
4.1
0.8
4.1
2.4
0.02
2.5
3.7
1.1
3.6
8
2.0
0.02
2.0
2.5
0.7
2.4
2.0
0.02
2.0
2.5
1.0
2.5
4
1.3
0.02
1.3
1.7
0.5
1.6
1.3
0.02
1.3
1.7
0.9
1.7
2
0.89
0.02
0.88
1.12
0.33
1.11
0.89
0.02
0.88
1.09
0.64
1.09
1
0.69
0.02
0.68
0.83
0.23
0.81
0.69
0.02
0.68
0.67
0.34
0.66
0.5
0.61
0.02
0.59
0.66
0.13
0.65
0.61
0.02
0.59
0.66
0.17
0.65
0.25
0.31
0.02
0.30
0.32
0.04
0.31
0.31
0.02
0.30
0.32
0.06
0.31
IDD_CORE IDD_IN
IDD_I0
IDD_CORE IDD_IN
IDD_I0
(AMP1) (AMP2)
IDD_CORE
IDD_IN
(AMP3)
IDD_I0 IDD_CORE
(AMP1) (AMP2)
Unit
(AMP3)
mA
Figure 46-27. Typical Current Consumption in Active Mode (Test Setup 1)
SAM4Cx4/8/16
SAM4Cx32
35
35
128-bit (Cache Enabled)
128-bit (Cache Disabled)
64-bit (Cache Enabled)
64-bit (Cache Disabled)
25
128-bit (Cache Enabled)
128-bit (Cache Disabled)
64-bit (Cache Enabled)
64-bit (Cache Disabled)
30
IDDIO + IDDIN (mA)
IDDIO + IDDIN (mA)
30
20
15
10
5
25
20
15
10
5
0
0
0
10
20
30
40
50
60
70
80
90
Master Clock Frequency (MHz)
100
110
120
0
10
20
30
40
50
60
70
80
90
100
110
120
Master Clock Frequency (MHz)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1121
46.7.4.2 Test Setup 2: CoreMark
CoreMark on Core 1 (CM4P1) running out of SRAM1 (Code) / SRAM2 (Data)
Core 0 (CM4P0) in Sleep mode.
Table 46-64.
SAM4CM4/8/16 Test Setup 2 Current Consumption
SRAM1, SRAM2
Clock
(MHz)
IDD_IN
(AMP1)
IDD_I0
(AMP2)
IDD_CORE
(AMP3)
120
22.3
0.22
19.0
100
18.7
0.22
16.0
84
15.8
0.22
13.6
64
12.1
0.22
10.5
48
9.2
0.22
7.9
32
7.1
0.22
5.5
24
5.4
0.22
4.2
12
2.1
0.01
2.1
8
1.4
0.01
1.4
4
0.78
0.01
0.77
2
0.46
0.01
0.45
1
0.29
0.01
0.28
0.5
0.21
0.01
0.2
0.25
0.13
0.01
0.12
Unit
mA
Table 46-65.
SAM4CM32 Test Setup 2 Current Consumption
SRAM1, SRAM2
Clock
(MHz)
IDD_IN
(AMP1)
IDD_I0
(AMP2)
IDD_CORE
(AMP3)
120
23.8
0.3
20.6
100
20.0
0.3
17.3
84
16.9
0.3
14.7
64
13.0
0.3
11.3
48
9.8
0.3
8.6
32
7.6
0.3
5.9
24
5.7
0.3
4.5
12
2.3
0.09
2.3
8
1.6
0.09
1.5
4
0.86
0.09
0.84
2
0.5
0.09
0.49
1
0.32
0.09
0.31
0.5
0.24
0.09
0.23
0.25
0.15
0.09
0.14
Unit
mA
1122
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Figure 46-28. Typical Current Consumption in Active Mode (Test Setup 2)
SAM4Cx4/8/16
SAM4Cx32
25
25
IDDIN (AMP1)
IDDIN (AMP1)
IDDIO (AMP2)
20
IDDIO (AMP2)
20
IDDCORE (AMP3)
IDD (mA)
IDD (mA)
IDDCORE (AMP3)
15
10
5
15
10
5
0
0
0
10
20
30
40
50
60
70
80
90
100
110
120
0
10
20
Master Clock Frequency (MHz)
30
40
50
60
70
80
90
100
110
120
Master Clock Frequency (MHz)
46.7.4.3 Test Setup 3: CoreMark
CoreMark on Core 0 (CM4P0) running out of Flash in 128-bit or 64-bit Access mode with and without Cache
Enabled. Cache is enabled above 0 WS.
CoreMark on Core 1 (CM4P1) running out of SRAM1 (Code) / SRAM2 (Data)
Table 46-66.
SAM4CM4/8/16 Test Setup 3 Current Consumption
128-bit Flash Access
Cache Enabled
64-bit Flash Access
Cache Disabled
Cache Enabled
Cache Disabled
Clock
(MHz)
IDD_IN
IDD_I0
(AMP1)
(AMP2)
(AMP3)
(AMP1)
(AMP2)
(AMP3)
120
31.3
0.28
28.0
34.2
1.9
30.9
31.3
0.28
28.0
30.7
1.8
27.4
100
26.4
0.28
23.6
29.8
1.8
27.1
26.4
0.28
23.6
27.0
1.8
24.3
84
22.4
0.28
20.1
26.3
1.7
24.0
22.4
0.28
20.1
24.1
1.7
21.8
64
17.2
0.28
15.6
21.0
1.5
19.3
17.2
0.28
15.6
19.6
1.6
18.0
48
13.1
0.28
11.8
16.6
1.4
15.3
13.1
0.28
11.8
16.0
1.6
14.7
32
9.8
0.28
8.1
12.6
1.2
10.9
9.8
0.28
8.1
12.3
1.4
10.6
24
7.4
0.28
6.2
9.5
1.1
8.3
7.4
0.28
6.2
9.4
1.3
8.1
12
3.1
0.11
3.1
4.2
0.88
4.2
3.1
0.11
3.1
4.2
1.2
4.2
8
2.1
0.11
2.1
2.8
0.78
2.8
2.1
0.11
2.1
2.8
1.0
2.8
4
1.1
0.11
1.1
1.5
0.58
1.5
1.1
0.11
1.1
1.5
0.9
1.5
2
0.63
0.11
0.61
0.82
0.40
0.81
0.63
0.11
0.61
0.82
0.66
0.81
1
0.38
0.11
0.37
0.47
0.26
0.46
0.38
0.11
0.37
0.47
0.38
0.46
0.5
0.25
0.11
0.24
0.30
0.18
0.29
0.25
0.11
0.24
0.30
0.23
0.29
0.25
0.14
0.11
0.13
0.16
0.12
0.15
0.14
0.11
0.13
0.16
0.14
0.15
IDD_CORE IDD_IN
IDD_I0
IDD_CORE IDD_IN
IDD_I0
(AMP1) (AMP2)
IDD_CORE
(AMP3)
IDD_IN
IDD_I0 IDD_CORE
(AMP1) (AMP2)
(AMP3)
Unit
mA
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1123
Table 46-67.
SAM4CM32 Test Setup 3 Current Consumption
128-bit Flash Access
Cache Enabled
64-bit Flash Access
Cache Disabled
Cache Enabled
Cache Disabled
Clock
(MHz)
IDD_IN
IDD_I0
(AMP1)
(AMP2)
(AMP3)
(AMP1)
(AMP2)
(AMP3)
120
35.0
0.23
31.7
38.4
2.1
35.1
34.9
0.23
31.6
33.8
1.8
30.5
100
29.5
0.23
26.8
33.8
2.0
31.0
29.4
0.23
26.7
29.5
1.7
27.0
84
25.1
0.23
22.8
29.4
1.8
27.1
24.9
0.23
22.7
26.6
1.7
24.3
64
19.3
0.23
17.7
23.2
1.5
21.5
19.2
0.23
17.6
21.8
1.5
20.1
48
14.7
0.23
13.4
18.0
1.3
16.8
14.6
0.23
13.4
17.7
1.5
16.5
32
10.9
0.23
9.2
13.3
1.1
11.7
10.8
0.23
9.2
13.5
1.3
11.8
24
8.2
0.23
7.0
10.5
1.0
9.3
8.2
0.22
7.0
10.3
1.2
9.0
12
3.5
0.02
3.5
4.8
0.86
4.7
3.5
0.02
3.5
4.7
1.1
4.6
8
2.4
0.02
2.4
3.2
0.74
3.2
2.4
0.02
2.4
3.1
1.0
3.1
4
1.3
0.02
1.3
1.7
0.42
1.7
1.3
0.02
1.3
1.7
0.87
1.7
2
0.72
0.02
0.71
0.92
0.40
0.89
0.71
0.02
0.81
0.94
0.56
0.94
1
0.43
0.02
0.42
0.52
0.18
0.52
0.43
0.02
0.42
0.55
0.36
0.54
0.5
0.29
0.02
0.28
0.36
0.09
0.36
0.29
0.02
0.28
0.35
0.18
0.34
0.25
0.16
0.02
0.15
0.18
0.02
0.16
0.16
0.02
0.15
0.17
0.06
0.16
IDD_CORE IDD_IN
IDD_I0
IDD_CORE IDD_IN
IDD_I0
(AMP1) (AMP2)
IDD_CORE
IDD_IN
(AMP3)
IDD_I0 IDD_CORE
(AMP1) (AMP2)
Unit
(AMP3)
mA
Figure 46-29. Typical Current Consumption in Active Mode (Test Setup 3)
SAM4Cx4/8/16
SAM4Cx32
50
128-bit (Cache Enabled)
128-bit (Cache Disabled)
64-bit (Cache Enabled)
64-bit (Cache Disabled)
40
IDDIO + IDDIN (mA)
IDDIO + IDDIN (mA)
50
30
20
128-bit (Cache Enabled)
128-bit (Cache Disabled)
64-bit (Cache Enabled)
64-bit (Cache Disabled)
40
30
20
10
10
0
0
0
10
20
30
40
50
60
70
80
90
100
110
120
Master Clock Frequency (MHz)
1124
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
0
10
20
30
40
50
60
70
80
90
Master Clock Frequency (MHz)
100
110
120
46.7.4.4 Test Setup 4: DSP Application (Five Cascaded 4th Order Biquad Filters) from ARM CMSIS DSP Library
Application running on Core 1 (CM4P1) out of SRAM1 (Code) / SRAM2 (Data)
Core 0 (CM4P0) in Sleep mode.
Table 46-68.
SAM4CM4/8/16 Test Setup 4 Current Consumption
DSP Application
Clock
(MHz)
IDD_IN
(AMP1)
IDD_I0
(AMP2)
IDD_CORE
(AMP3)
120
21.6
0.22
18.3
100
18.1
0.22
15.4
84
15.3
0.22
13.1
64
11.7
0.22
10.1
48
8.9
0.22
7.6
32
7.9
0.22
6.3
24
6.0
0.22
4.8
12
2.2
0.08
2.1
8
1.5
0.08
1.5
4
0.80
0.08
0.76
2
0.47
0.08
0.46
1
0.30
0.08
0.29
0.5
0.22
0.08
0.20
Table 46-69.
Unit
mA
SAM4CM32 Test Setup 4 Current Consumption
DSP Application
Clock
(MHz)
IDD_IN
(AMP1)
IDD_I0
(AMP2)
IDD_CORE
(AMP3)
120
23.2
0.22
20.0
100
19.5
0.22
16.8
84
16.4
0.22
14.2
64
12.6
0.22
11.0
48
9.5
0.22
8.3
32
8.4
0.22
6.7
24
6.3
0.22
5.1
12
1.1
0.02
1.1
8
0.75
0.02
0.74
4
0.45
0.02
0.44
2
0.29
0.02
0.28
1
0.22
0.02
0.21
0.5
0.18
0.02
0.17
Unit
mA
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1125
Figure 46-30. Typical Current Consumption in Active Mode (Test Setup 4)
SAM4Cx4/8/16
SAM4Cx32
25
25
IDDIN (AMP1)
IDDIN (AMP1)
IDDIO (AMP2)
20
IDDIO (AMP2)
20
IDDCORE (AMP3)
IDD (mA)
IDD (mA)
IDDCORE (AMP3)
15
10
15
10
5
5
0
0
0
10
20
30
40
50
60
70
80
90
100
110
0
120
10
20
Master Clock Frequency (MHz)
30
40
50
60
70
80
90
100
110
120
Master Clock Frequency (MHz)
46.7.4.5 Test Setup 5: DSP Application (Five Cascaded 4th Order Biquad Filters) from ARM CMSIS DSP Library
Application running on Core 0 (CM4P0) out of Flash in 128-bit Access mode with and without cache
enabled. Cache is enabled above 0 WS.
Sub-system 1 Master Clock (CPBMCK) and Core Clock (CPHCLK) stopped and in reset.
VDDIO = VDDIN = 3V
Table 46-70.
SAM4CM4/8/16 Test Setup 5 Current Consumption
128-bit Flash Access
Cache Enabled
64-bit Flash Access
Cache Disabled
Cache Enabled
Cache Disabled
Clock
(MHz)
IDD_IN
IDD_I0
(AMP1)
(AMP2)
(AMP3)
(AMP1)
(AMP2)
(AMP3)
120
23.2
0.31
19.9
26.3
2.1
23.1
23.2
0.31
19.9
21.2
1.7
18.0
100
19.3
0.31
16.6
23.7
2.0
21.0
19.3
0.31
16.6
18.9
1.7
16.2
84
16.3
0.31
14.1
21.2
1.9
19.0
16.3
0.31
14.1
17.5
1.7
15.3
64
12.9
0.31
11.2
17.2
1.8
15.5
12.9
0.31
11.2
14.8
1.6
13.1
48
9.9
0.31
8.6
13.9
1.6
12.7
9.9
0.31
8.6
12.3
1.6
11.1
32
7.5
0.31
5.8
10.6
1.4
9.0
7.5
0.31
5.8
9.9
1.4
8.2
24
5.7
0.31
4.4
8.7
1.2
7.5
5.7
0.31
4.4
8.1
1.3
6.9
12
2.6
0.08
2.6
4.0
0.82
3.9
2.6
0.08
2.6
3.5
0.8
3.4
8
1.7
0.08
1.7
2.7
0.70
2.7
1.7
0.08
1.7
2.4
0.8
2.4
4
0.89
0.08
0.88
1.6
0.51
1.6
0.89
0.08
0.88
1.3
0.7
1.3
2
0.56
0.08
0.55
0.96
0.39
0.95
0.56
0.08
0.55
0.78
0.54
0.76
1
0.55
0.08
0.54
0.67
0.20
0.66
0.55
0.08
0.54
0.68
0.37
0.67
IDD_CORE IDD_IN
IDD_I0
IDD_CORE IDD_IN
IDD_I0
(AMP1) (AMP2)
IDD_CORE
(AMP3)
IDD_IN
IDD_I0 IDD_CORE
(AMP1) (AMP2)
(AMP3)
Unit
mA
1126
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Table 46-71.
SAM4CM32Test Setup 5 Current Consumption
128-bit Flash Access
Cache Enabled
64-bit Flash Access
Cache Disabled
Cache Enabled
Cache Disabled
Clock
(MHz)
IDD_IN
IDD_I0
(AMP1)
(AMP2)
(AMP3)
(AMP1)
(AMP2)
(AMP3)
120
26.6
0.40
23.3
29.9
2.1
26.6
26.3
0.42
23.1
24.4
1.6
21.2
100
22.4
0.39
19.7
27.8
2.0
24.5
22.7
0.40
20.0
22.0
1.7
19.4
84
18.9
0.38
16.7
24.1
1.9
21.9
19.4
0.39
17.1
19.9
1.7
17.7
64
14.7
0.36
13.0
19.7
1.8
18.0
14.6
0.36
13.0
16.7
1.6
15.1
48
11.6
0.34
10.4
15.3
1.6
14.0
11.6
0.34
10.4
14.4
1.5
13.2
32
9.0
0.33
7.3
11.8
1.4
10.2
8.9
0.32
7.3
11.0
1.4
9.4
24
6.5
0.32
5.3
10.0
1.4
8.7
6.5
0.31
5.2
8.2
1.3
7.5
12
2.7
0.08
2.7
4.8
1.23
4.8
2.7
0.08
2.7
3.9
1.1
3.9
8
1.9
0.06
1.8
2.9
0.99
2.9
2.2
0.06
2.2
3.0
1.1
2.9
4
1.03
0.04
1.01
1.9
0.64
1.9
1.36
0.05
1.35
1.8
0.9
1.8
2
0.95
0.03
0.94
1.23
0.45
1.24
0.95
0.04
0.94
0.86
0.71
0.86
1
0.75
0.02
0.73
0.56
0.23
0.54
0.75
0.03
0.74
0.85
0.32
0.84
IDD_CORE IDD_IN
IDD_I0
IDD_CORE IDD_IN
IDD_I0
(AMP1) (AMP2)
IDD_CORE
IDD_IN
(AMP3)
IDD_I0 IDD_CORE
(AMP1) (AMP2)
Unit
(AMP3)
mA
Figure 46-31. Typical Current Consumption in Active Mode (Test Setup 5)
SAM4Cx4/8/16
SAM4Cx32
35
35
128-bit (Cache Enabled)
128-bit (Cache Disabled)
64-bit (Cache Enabled)
64-bit (Cache Disabled)
25
128-bit (Cache Enabled)
128-bit (Cache Disabled)
64-bit (Cache Enabled)
64-bit (Cache Disabled)
30
IDDIO + IDDIN (mA)
IDDIO + IDDIN (mA)
30
20
15
10
25
20
15
10
5
5
0
0
0
10
20
30
40
50
60
70
80
90
Master Clock Frequency (MHz)
100
110
120
0
10
20
30
40
50
60
70
80
90
100
110
120
Master Clock Frequency (MHz)
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1127
46.7.5 Peripheral Power Consumption in Active Mode
Power Consumption on VDDCORE(1)
Table 46-72.
Peripheral
Consumption
(Typical)
PIO Controller
4.0
UART0
5.4
UART1
5.4
USART[0-4]
7.7
PWM
3.9
TWI
5.3
SPI
5.0
Timer Counter (TCx)
2.7
ADC
3.9
SMC
4.6
SLCD
0.16
AES: Performing AES256 Encryption
164
TRNG
6.2
ICM
5.2
Unit
µA/MHz
Note:
1128
1.
VDDIO = 3.3V, VDDCORE = 1.2V, TA = 25°C.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
47.
Mechanical Characteristics
47.1
100-lead LQFP Package
Figure 47-1.
100-lead LQFP Package Drawing
Table 47-1.
Device and LQFP Package Maximum Weight
SAM4CM
Table 47-2.
800
mg
LQFP Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
e3
Table 47-3.
LQFP Package Characteristics
Moisture Sensitivity Level
3
This package respects the recommendations of the NEMI User Group.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1129
47.2
Soldering Profile
Table 47-4 gives the recommended soldering profile from J-STD-020C.
Table 47-4.
Soldering Profile
Profile Feature
Green Package
Average Ramp-up Rate (217°C to Peak)
3°C/sec. max.
Preheat Temperature 175°C ± 25°C
180 sec. max.
Temperature Maintained Above 217°C
60 sec. to 150 sec.
Time within 5°C of Actual Peak Temperature
20 sec. to 40 sec.
Peak Temperature Range
260°C
Ramp-down Rate
6°C/sec. max.
Time 25°C to Peak Temperature
8 min. max.
Note:
The package is certified to be backward compatible with Pb/Sn soldering profile.
A maximum of three reflow passes is allowed per component.
47.3
Packaging Resources
This section provides land pattern definition.
Refer to the following IPC standards:
1130
IPC-7351A and IPC-782 (Generic Requirements for Surface Mount Design and Land Pattern Standards)
http://landpatterns.ipc.org/default.asp
Atmel Green and RoHS Policy and Package Material Declaration Data Sheet
http://www.atmel.com/about/quality/package.aspx
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
48.
Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking is as follows:
YYWW
V
XXXXXXXXX
ARM
where
“YY”: Manufactory year
“WW”: Manufactory week
“V”: Revision
“XXXXXXXXX”: Lot number
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1131
49.
Ordering Information
Table 49-1.
Ordering Codes for SAM4CM Devices
Ordering Code
MRL
Flash
(Kbytes)
Package
ATSAM4CMP32CB-AU
Conditioning
Temperature
Operating Range
Tray
B
ATSAM4CMP32CB-AUR
Reel
2 x 1024
ATSAM4CMP32CA-AU
Tray
A
ATSAM4CMP32CA-AUR
Reel
ATSAM4CMP16CC-AU
Tray
C
ATSAM4CMP16CC-AUR
Reel
ATSAM4CMP16CB-AU
Tray
B
1024
ATSAM4CMP16CB-AUR
Reel
ATSAM4CMP16CA-AU
Tray
A
ATSAM4CMP16CA-AUR
Reel
ATSAM4CMP8CC-AU
Tray
C
ATSAM4CMP8CC-AUR
Reel
ATSAM4CMP8CB-AU
Tray
B
512
ATSAM4CMP8CB-AUR
Reel
ATSAM4CMP8CA-AU
Tray
A
ATSAM4CMP8CA-AUR
Reel
LQFP100
ATSAM4CMS32CB-AU
Tray
B
ATSAM4CMS32CB-AUR
Reel
2 x 1024
ATSAM4CMS32CA-AU
Tray
A
ATSAM4CMS32CA-AUR
Reel
ATSAM4CMS16CC-AU
Tray
C
ATSAM4CMS16CC-AUR
Reel
ATSAM4CMS16CB-AU
Tray
B
1024
ATSAM4CMS16CB-AUR
Reel
ATSAM4CMS16CA-AU
Tray
A
ATSAM4CMS16CA-AUR
Reel
ATSAM4CMS8CC-AU
Tray
C
ATSAM4CMS8CC-AUR
Reel
ATSAM4CMS8CB-AU
Tray
B
512
ATSAM4CMS8CB-AUR
Reel
ATSAM4CMS8CA-AU
Tray
A
ATSAM4CMS8CA-AUR
1132
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Reel
Industrial
(-40°C to +85°C)
Table 49-1.
Ordering Codes for SAM4CM Devices (Continued)
Ordering Code
MRL
Flash
(Kbytes)
Package
ATSAM4CMS4CC-AU
Conditioning
Temperature
Operating Range
Tray
C
ATSAM4CMS4CC-AUR
Reel
256
ATSAM4CMS4CB-AU
LQFP100
Tray
Industrial
(-40°C to +85°C
B
ATSAM4CMS4CB-AUR
Reel
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1133
50.
SAM4CM16/8 Errata Revision A (MRL A) Parts
50.1
Device Identification
The following errata apply to the devices listed in Table 50-1.
Table 50-1.
Device List
Device Marking
50.2
Chip ID
ATSAM4CMP16CA-AU
0xA64C_0CE0
ATSAM4CMP16CA-AUR
0xA64C_0CE0
ATSAM4CMP8CA-AU
0xA64C_0AE0
ATSAM4CMP8CA-AUR
0xA64C_0AE0
ATSAM4CMS16CA-AU
0xA64C_0CE0
ATSAM4CMS16CA-AUR
0xA64C_0CE0
ATSAM4CMS8CA-AU
0xA64C_0AE0
ATSAM4CMS8CA-AUR
0xA64C_0AE0
Flash Memory
50.2.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State
Flash read issues leading to wrong instruction fetch or data read may occur under the following operating
condition:
̶
VDDIO < 2.4V and Flash wait state(1) ≥ 1
If the core clock frequency does not require the use of the Flash wait state(2) (FWS = 0 in EEFC_FMR), there are
no constraints on VDDIO voltage. The usable voltage range for VDDIO is defined in Table 46-2 “Recommended
DC Operating Conditions on Power Supply Inputs”.
Notes:
1.
2.
FWS field in EEFC_FMR register.
Refer to Table 46-52 “SAM4CM4/8/16 Flash Wait State Versus Operating Frequency” and Table 46-53
“SAM4CM32 Flash Wait State Versus Operating Frequency” for maximum core clock frequency at zero (0) wait
states.
Problem Fix/Workaround
None.
The issue is corrected in the device revision Marketing Revision Level B (MRL B). Please contact your local Sales
Representative for further details.
50.3
Supply Controller (SUPC)
50.3.1 SUPC: Supply Monitor (SM) on VDDIO
The Supply Monitor (SM) Sampling mode reducing the average current consumption on VDDIO is not functional.
Problem Fix/Workaround
Use the Supply Monitor in Continuous mode only.
1134
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
50.3.2 SUPC: Core Voltage Regulator Standby Mode Control
The Core Voltage Regulator Standby mode controlled by the ONREG bit in SUPC_MR is not functional. This does
not prevent to power VDDCORE and VDDPL by using an external voltage regulator.
Problem Fix/Workaround
None. Do not use the ONREG bit.
50.3.3 SUPC: Core Brownout Detector. Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO
is Powered
In Active mode or in Wait mode, if the Brownout Detector (BOD) is disabled (SUPC_MR: BODDIS=1) and power is
lost on VDDCORE while VDDIO is powered, the device can be reset incorrectly and its behavior becomes then
unpredictable.
Problem Fix/Workaround
When the Brownout Detector is disabled in Active or in Wait mode, VDDCORE must be always powered.
50.4
Parallel Input Output (PIO) Controller
50.4.1 PIO: Schmitt Trigger
Schmitt triggers on all PIO controllers are not enabled by default (after reset) as stated in the product
datasheet.
Enable and disable values in the PIO Schmitt Trigger Register (for all PIO controllers) are inverted. The
definition of PIO_SCHMITT fields must be as follows:
̶
0: Schmitt Trigger is disabled.
̶
1: Schmitt Trigger is enabled.
Problem Fix/Workaround
None. It is up to the application to enable Schmitt Trigger mode and to take into account the inverted values of
the PIO_SCHMITT fields.
50.5
Watchdog (WDT) / Reinforced Safety Watchdog (RSWDT)
50.5.1 WDT / RSWDT not stopped in WAIT mode
When the Watchdog (WDT) or the Reinforced Safety Watchdog (RSWDT) is enabled and the WAITMODE bit set
to 1 is used to enter Low-power Wait mode, the WDT/RSWDT is not halted. If the time spent in Wait mode is
longer than the Watchdog (Reinforced Safety Watchdog) time-out, the device is reset provided that the
WDT/RSWDT reset is enabled.
Problem Fix/Workaround
When entering Wait mode, the Wait-For-Event (WFE) instruction of the Cortex-M4 processor must be used while
the SLEEPDEEP bit of the Cortex-M System Control Register (SCB_SCR) is set to 0.
50.5.2 RSWDT Windowing Mode
When the RSWDT is configured in Windowing mode (WDD set lower than WDV in RSWDT_MR), an unexpected
watchdog reset order may be sent to the Reset Controller (RSTC).
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1135
Problem Fix/Workaround
Do not use the Windowing mode of the RSWDT and set WDD to 4095 in RSWDT_MR.
50.6
Enhanced Embedded Flash Controller (EEFC)
50.6.1 EEFC: Erase Sector (ES) Command Cannot be Performed if a Subsector is Locked (ONLY in Flash
sector 0)
If one of the subsectors
small sector 0
small sector 1
larger sector
is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked
subsectors. Refer to Section 8.1.4.1 “Flash Overview”.
Problem Fix/Workaround
All the lock bits of the sector 0 must be cleared prior to issuing the ES command. After the ES command has been
issued, the lock bits must be reverted to the state before clearing them.
50.7
Wait For Interrupt (WFI)
50.7.1 Unpredictable Software Behavior When Entering Sleep Mode
When entering Sleep mode, if an interrupt occurs during WFI or WFE instruction (with PMC_FSMR.LPM=0), the
ARM core may read a wrong data, thus leading to unpredictable behavior of the software. This issue is not present
in Wait mode.
Problem Fix/Workaround
The slave interface for the Flash must be set to no default master in the Bus Matrix Controller.
This is done by setting the field DEFMSTR_TYPE in the register MATRIX_SCFG to NO_DEFAULT.
MATRIX_SCFG[2] = MATRIX_SCFG.SLOT_CYCLE(0x1FF) | MATRIX_SCFG.DEFMSTR_TYPE(0x0);
This operation must be done once in the software or the instruction before WFI or WFE.
50.8
Power Supply and Power Control / Clock System
50.8.1 CORE 1 Systick Counter Erratic Behavior
If the CORE 0 processor clock (HCLK) frequency is higher than four times the frequency of the CORE 1 processor
clock (CPHCLK), the systick counter behavior is erratic.
Problem Fix/Workaround
Always ensure that fHCLK < 4 x fCPHCLK.
1136
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
50.9
Power Management Controller (PMC)
50.9.1 SRCB Bit in CKGR_PLLB Register
The SRCB bit is programmed in bit 29 of the CKGR_PLLB register but must be read in bit 27 of this register.
Problem Fix/Workaround
For SRCB, read bit 27 of the CKGR_PLLB register.
50.10 EMAFE
50.10.1 EMAFE Accuracy
Atmel ATSAM4CM EMAFE accuracy can be degraded under certain device conditions such as embedded Flash
registers set up and Read/Write accesses.
Problem Fix/Workaround
None.
The issue is corrected in the device Marketing Revision Level C (MRL C). MRL-C devices are
pin-to-pin compatible, form-compatible and firmware-compatible with previous version.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1137
51.
SAM4CM16/8/4 Errata Revision B (MRL B) Parts
51.1
Device Identification
The following errata apply to the devices listed in Table 51-1.
Table 51-1.
Device List
Device Marking
51.2
Chip ID
ATSAM4CMP16CB-AU
0xA64C_0CE1
ATSAM4CMP16CB-AUR
0xA64C_0CE1
ATSAM4CMP8CB-AU
0xA64C_0AE1
ATSAM4CMP8CB-AUR
0xA64C_0AE1
ATSAM4CMS16CB-AU
0xA64C_0CE1
ATSAM4CMS16CB-AUR
0xA64C_0CE1
ATSAM4CMS8CB-AU
0xA64C_0AE1
ATSAM4CMS8CB-AUR
0xA64C_0AE1
ATSAM4CMS4CB-AU
0xA64C_0CE5
ATSAM4CMS4CB-AUR
0xA64C_0CE5
Supply Controller (SUPC)
51.2.1 SUPC: Supply Monitor (SM) on VDDIO
The Supply Monitor (SM) Sampling mode reducing the average current consumption on VDDIO is not functional.
Problem Fix/Workaround
Use the Supply Monitor in Continuous mode only.
51.2.2 SUPC: Core Voltage Regulator Standby Mode Control
The Core Voltage Regulator Standby mode controlled by the ONREG bit in SUPC_MR is not functional. This does
not prevent to power VDDCORE and VDDPL by using an external voltage regulator.
Problem Fix/Workaround
None. Do not use the ONREG Bit.
51.2.3 SUPC: Core Brownout Detector. Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO
is Powered
In Active mode or in Wait mode, if the Brownout Detector (BOD) is disabled (SUPC_MR: BODDIS=1) and power is
lost on VDDCORE while VDDIO is powered, the device can be reset incorrectly and its behavior becomes then
unpredictable.
Problem Fix/Workaround
When the Brownout Detector is disabled in Active or in Wait mode, VDDCORE must be always powered.
1138
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
51.3
Parallel Input Output (PIO) Controller
51.3.1 PIO: Schmitt Trigger
Schmitt triggers on all PIO controllers are not enabled by default (after reset) as stated in the product
datasheet
Enable and disable values in the PIO Schmitt Trigger Register (for all PIO controllers) are inverted. The
definition of PIO_SCHMITT fields must be as follows:
̶
0: Schmitt Trigger is disabled.
̶
1: Schmitt Trigger is enabled.
Problem Fix/Workaround
None. It is up to the application to enable Schmitt Trigger mode and to take into account the inverted values of
the PIO_SCHMITT fields.
51.4
Watchdog (WDT) / Reinforced Safety Watchdog (RSWDT)
51.4.1 WDT / RSWDT not stopped in WAIT mode
When the Watchdog (WDT) or the Reinforced Safety Watchdog (RSWDT) is enabled and the WAITMODE bit set
to 1 is used to enter Low-power Wait mode, the WDT/RSWDT is not halted. If the time spent in Wait mode is
longer than the Watchdog (Reinforced Safety Watchdog) time-out, the device is reset provided that the
WDT/RSWDT reset is enabled.
Problem Fix/Workaround
When entering Wait mode, the WaitForEvent (WFE) instruction of the Cortex-M4 processor must be used while
the SLEEPDEEP bit of the Cortex-M System Control Register (SCB_SCR) is set to 0.
51.4.2 RSWDT Windowing Mode
When the RSWDT is configured in Windowing mode (WDD set lower than WDV in RSWDT_MR), an unexpected
watchdog reset order may be sent to the Reset Controller (RSTC).
Problem Fix/Workaround
Do not use the Windowing mode of the RSWDT and set WDD to 4095 in RSWDT_MR.
51.5
Enhanced Embedded Flash Controller (EEFC)
51.5.1 EEFC: Erase Sector (ES) Command Cannot be Performed if a Subsector is Locked (ONLY in Flash
sector 0)
If one of the subsectors
small sector 0
small sector 1
larger sector
is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked
subsectors. Refer to Section 8.1.4.1 “Flash Overview”.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1139
Problem Fix/Workaround
All the lock bits of the sector 0 must be cleared prior to issuing the ES command. After the ES command has been
issued, the lock bits must be reverted to the state before clearing them.
51.6
Wait For Interrupt (WFI)
51.6.1 Unpredictable Software Behavior When Entering Sleep Mode
When entering Sleep mode, if an interrupt occurs during WFI or WFE instruction (with PMC_FSMR.LPM=0), the
ARM core may read a wrong data, thus leading to unpredictable behavior of the software. This issue is not present
in Wait mode.
Problem Fix/Workaround
The slave interface for the Flash must be set to no default master in the Bus Matrix Controller.
This is done by setting the field DEFMSTR_TYPE in the register MATRIX_SCFG to NO_DEFAULT.
MATRIX_SCFG[2] = MATRIX_SCFG.SLOT_CYCLE(0x1FF) | MATRIX_SCFG.DEFMSTR_TYPE(0x0);
This operation must be done once in the software or the instruction before WFI or WFE.
51.7
Power Supply and Power Control / Clock System
51.7.1 CORE 1 Systick Counter Erratic Behavior
If the CORE 0 processor clock (HCLK) frequency is higher than four times the frequency of the CORE 1 processor
clock (CPHCLK), the systick counter behavior is erratic.
Problem Fix/Workaround
Always ensure that fHCLK < 4 x fCPHCLK.
51.8
Power Management Controller (PMC)
51.8.1 SRCB Bit in CKGR_PLLB Register
The SRCB bit is programmed in bit 29 of the CKGR_PLLB register but must be read in bit 27 of this register.
Problem Fix/Workaround
For SRCB, read bit 27 of the CKGR_PLLB register.
51.9
EMAFE
51.9.1 EMAFE Accuracy
Atmel ATSAM4CM EMAFE accuracy can be degraded under certain device conditions such as embedded Flash
registers set up and Read/Write accesses.
Problem Fix/Workaround
1140
None.
The issue is corrected in the device Marketing Revision Level C (MRL C). MRL-C devices are
pin-to-pin compatible, form-compatible and firmware-compatible with previous version.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
52.
SAM4CM16/8/4 Errata Revision C (MRL C) Parts
52.1
Device Identification
The following errata apply to the devices listed in Table 51-1.
Table 52-1.
Device List
Device Marking
52.2
Chip ID
ATSAM4CMP16CC-AU
0xA64C_0CE2
ATSAM4CMP16CC-AUR
0xA64C_0CE2
ATSAM4CMP8CC-AU
0xA64C_0AE2
ATSAM4CMP8CC-AUR
0xA64C_0AE2
ATSAM4CMS16CC-AU
0xA64C_0CE2
ATSAM4CMS16CC-AUR
0xA64C_0CE2
ATSAM4CMS8CC-AU
0xA64C_0AE2
ATSAM4CMS8CC-AUR
0xA64C_0AE2
ATSAM4CMS4CC-AU
0xA64C_0CE6
ATSAM4CMS4CC-AUR
0xA64C_0CE6
Supply Controller (SUPC)
52.2.1 SUPC: Supply Monitor (SM) on VDDIO
The Supply Monitor (SM) Sampling mode reducing the average current consumption on VDDIO is not functional.
Problem Fix/Workaround
Use the Supply Monitor in Continuous mode only.
52.2.2 SUPC: Core Voltage Regulator Standby Mode Control
The Core Voltage Regulator Standby mode controlled by the ONREG bit in SUPC_MR is not functional. This does
not prevent to power VDDCORE and VDDPL by using an external voltage regulator.
Problem Fix/Workaround
None. Do not use the ONREG Bit.
52.2.3 SUPC: Core Brownout Detector. Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO
is Powered
In Active mode or in Wait mode, if the Brownout Detector (BOD) is disabled (SUPC_MR: BODDIS=1) and power is
lost on VDDCORE while VDDIO is powered, the device can be reset incorrectly and its behavior becomes then
unpredictable.
Problem Fix/Workaround
When the Brownout Detector is disabled in Active or in Wait mode, VDDCORE must be always powered.
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1141
52.3
Parallel Input Output (PIO) Controller
52.3.1 PIO: Schmitt Trigger
Schmitt triggers on all PIO controllers are not enabled by default (after reset) as stated in the product
datasheet
Enable and disable values in the PIO Schmitt Trigger Register (for all PIO controllers) are inverted. The
definition of PIO_SCHMITT fields must be as follows:
̶
0: Schmitt Trigger is disabled.
̶
1: Schmitt Trigger is enabled.
Problem Fix/Workaround
None. It is up to the application to enable Schmitt Trigger mode and to take into account the inverted values of
the PIO_SCHMITT fields.
52.4
Watchdog (WDT) / Reinforced Safety Watchdog (RSWDT)
52.4.1 WDT / RSWDT not stopped in WAIT mode
When the Watchdog (WDT) or the Reinforced Safety Watchdog (RSWDT) is enabled and the WAITMODE bit set
to 1 is used to enter Low-power Wait mode, the WDT/RSWDT is not halted. If the time spent in Wait mode is
longer than the Watchdog (Reinforced Safety Watchdog) time-out, the device is reset provided that the
WDT/RSWDT reset is enabled.
Problem Fix/Workaround
When entering Wait mode, the WaitForEvent (WFE) instruction of the Cortex-M4 processor must be used while
the SLEEPDEEP bit of the Cortex-M System Control Register (SCB_SCR) is set to 0.
52.4.2 RSWDT Windowing Mode
When the RSWDT is configured in Windowing mode (WDD set lower than WDV in RSWDT_MR), an unexpected
watchdog reset order may be sent to the Reset Controller (RSTC).
Problem Fix/Workaround
Do not use the Windowing mode of the RSWDT and set WDD to 4095 in RSWDT_MR.
52.5
Enhanced Embedded Flash Controller (EEFC)
52.5.1 EEFC: Erase Sector (ES) Command Cannot be Performed if a Subsector is Locked (ONLY in Flash
sector 0)
If one of the subsectors
small sector 0
small sector 1
larger sector
is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked
subsectors. Refer to Section 8.1.4.1 “Flash Overview”.
1142
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
Problem Fix/Workaround
All the lock bits of the sector 0 must be cleared prior to issuing the ES command. After the ES command has been
issued, the lock bits must be reverted to the state before clearing them.
52.6
Wait For Interrupt (WFI)
52.6.1 Unpredictable Software Behavior When Entering Sleep Mode
When entering Sleep mode, if an interrupt occurs during WFI or WFE instruction (with PMC_FSMR.LPM=0), the
ARM core may read a wrong data, thus leading to unpredictable behavior of the software. This issue is not present
in Wait mode.
Problem Fix/Workaround
The slave interface for the Flash must be set to no default master in the Bus Matrix Controller.
This is done by setting the field DEFMSTR_TYPE in the register MATRIX_SCFG to NO_DEFAULT.
MATRIX_SCFG[2] = MATRIX_SCFG.SLOT_CYCLE(0x1FF) | MATRIX_SCFG.DEFMSTR_TYPE(0x0);
This operation must be done once in the software or the instruction before WFI or WFE.
52.7
Power Supply and Power Control / Clock System
52.7.1 CORE 1 Systick Counter Erratic Behavior
If the CORE 0 processor clock (HCLK) frequency is higher than four times the frequency of the CORE 1 processor
clock (CPHCLK), the systick counter behavior is erratic.
Problem Fix/Workaround
Always ensure that fHCLK < 4 x fCPHCLK.
52.8
Power Management Controller (PMC)
52.8.1 SRCB Bit in CKGR_PLLB Register
The SRCB bit is programmed in bit 29 of the CKGR_PLLB register but must be read in bit 27 of this register.
Problem Fix/Workaround
For SRCB, read bit 27 of the CKGR_PLLB register.
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53.
SAM4CM32 Errata Revision A (MRL A) Parts
53.1
Device Identification
The following errata apply to the devices listed in Table 53-1.
Table 53-1.
Device List
Device Marking
53.2
Chip ID
ATSAM4CMP32CA-AU
0xA64D_0EE0
ATSAM4CMP32CA-AUR
0xA64D_0EE0
Supply Controller (SUPC)
53.2.1 SUPC: Supply Monitor (SM) on VDDIO
The Supply Monitor (SM) Sampling mode reducing the average current consumption on VDDIO is not functional.
Problem Fix/Workaround
Use the Supply Monitor in Continuous mode only.
53.2.2 SUPC: Core Voltage Regulator Standby Mode Control
The Core Voltage Regulator Standby mode controlled by the ONREG bit in SUPC_MR is not functional. This does
not prevent to power VDDCORE and VDDPL by using an external voltage regulator.
Problem Fix/Workaround
None. Do not use the ONREG Bit.
53.2.3 SUPC: Core Brownout Detector. Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO
is Powered
In Active mode or in Wait mode, if the Brownout Detector (BOD) is disabled (SUPC_MR: BODDIS=1) and power is
lost on VDDCORE while VDDIO is powered, the device can be reset incorrectly and its behavior becomes then
unpredictable.
Problem Fix/Workaround
When the Brownout Detector is disabled in Active or in Wait mode, VDDCORE must be always powered.
53.3
Parallel Input Output (PIO) Controller
53.3.1 PIO: Schmitt Trigger
1144
Schmitt triggers on all PIO controllers are not enabled by default (after reset) as stated in the product
datasheet
SAM4CM Series [DATASHEET]
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Enable and disable values in the PIO Schmitt Trigger Register (for all PIO controllers) are inverted. The
definition of PIO_SCHMITT fields must be as follows:
̶
0: Schmitt Trigger is disabled.
̶
1: Schmitt Trigger is enabled.
Problem Fix/Workaround
None. It is up to the application to enable Schmitt Trigger mode and to take into account the inverted values of
the PIO_SCHMITT fields.
53.4
Reinforced Safety Watchdog (RSWDT)
53.4.1 RSWDT Windowing Mode
When the RSWDT is configured in Windowing mode (WDD set lower than WDV in RSWDT_MR), an unexpected
watchdog reset order may be sent to the Reset Controller (RSTC).
Problem Fix/Workaround
Do not use the Windowing mode of the RSWDT and set WDD to 4095 in RSWDT_MR.
53.5
Enhanced Embedded Flash Controller (EEFC)
53.5.1 EEFC: Erase Sector (ES) Command Cannot be Performed if a Subsector is Locked (ONLY in Flash
sector 0)
If one of the subsectors
small sector 0
small sector 1
larger sector
is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked
subsectors. Refer to Section 8.1.4.1 “Flash Overview”.
Problem Fix/Workaround
All the lock bits of the sector 0 must be cleared prior to issuing the ES command. After the ES command has been
issued, the lock bits must be reverted to the state before clearing them.
53.6
Wait For Interrupt (WFI)
53.6.1 Unpredictable Software Behavior When Entering Sleep Mode
When entering Sleep mode, if an interrupt occurs during WFI or WFE instruction (with PMC_FSMR.LPM=0), the
ARM core may read a wrong data, thus leading to unpredictable behavior of the software. This issue is not present
in Wait mode.
Problem Fix/Workaround
The slave interface for the Flash must be set to no default master in the Bus Matrix Controller.
This is done by setting the field DEFMSTR_TYPE in the register MATRIX_SCFG to NO_DEFAULT.
MATRIX_SCFG[2] = MATRIX_SCFG.SLOT_CYCLE(0x1FF) | MATRIX_SCFG.DEFMSTR_TYPE(0x0);
This operation must be done once in the software or the instruction before WFI or WFE.
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53.7
Power Management Controller (PMC)
53.7.1 SRCB Bit in CKGR_PLLB Register
The SRCB bit is programmed in bit 29 of the CKGR_PLLB register but must be read in bit 27 of this register.
Problem Fix/Workaround
For SRCB, read bit 27 of the CKGR_PLLB register.
53.8
EMAFE
53.8.1 EMAFE Accuracy
Atmel ATSAM4CM EMAFE accuracy can be degraded under certain device conditions such as embedded Flash
registers set up and Read/Write accesses.
Problem Fix/Workaround
1146
None.
The issue is corrected in the device Marketing Revision Level B (MRL B). MRL-B devices are
pin-to-pin compatible, form-compatible and firmware-compatible with previous version.
SAM4CM Series [DATASHEET]
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54.
SAM4CM32 Errata Revision B (MRL B) Parts
54.1
Device Identification
The following errata apply to the devices listed in Table 53-1.
Table 54-1.
Device List
Device Marking
54.2
Chip ID
ATSAM4CMP32CB-AU
0xA64D_0EE1
ATSAM4CMP32CB-AUR
0xA64D_0EE1
Supply Controller (SUPC)
54.2.1 SUPC: Supply Monitor (SM) on VDDIO
The Supply Monitor (SM) Sampling mode reducing the average current consumption on VDDIO is not functional.
Problem Fix/Workaround
Use the Supply Monitor in Continuous mode only.
54.2.2 SUPC: Core Voltage Regulator Standby Mode Control
The Core Voltage Regulator Standby mode controlled by the ONREG bit in SUPC_MR is not functional. This does
not prevent to power VDDCORE and VDDPL by using an external voltage regulator.
Problem Fix/Workaround
None. Do not use the ONREG Bit.
54.2.3 SUPC: Core Brownout Detector. Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO
is Powered
In Active mode or in Wait mode, if the Brownout Detector (BOD) is disabled (SUPC_MR: BODDIS=1) and power is
lost on VDDCORE while VDDIO is powered, the device can be reset incorrectly and its behavior becomes then
unpredictable.
Problem Fix/Workaround
When the Brownout Detector is disabled in Active or in Wait mode, VDDCORE must be always powered.
54.3
Parallel Input Output (PIO) Controller
54.3.1 PIO: Schmitt Trigger
Schmitt triggers on all PIO controllers are not enabled by default (after reset) as stated in the product
datasheet
Enable and disable values in the PIO Schmitt Trigger Register (for all PIO controllers) are inverted. The
definition of PIO_SCHMITT fields must be as follows:
̶
0: Schmitt Trigger is disabled.
̶
1: Schmitt Trigger is enabled.
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Problem Fix/Workaround
None. It is up to the application to enable Schmitt Trigger mode and to take into account the inverted values of
the PIO_SCHMITT fields.
54.4
Reinforced Safety Watchdog (RSWDT)
54.4.1 RSWDT Windowing Mode
When the RSWDT is configured in Windowing mode (WDD set lower than WDV in RSWDT_MR), an unexpected
watchdog reset order may be sent to the Reset Controller (RSTC).
Problem Fix/Workaround
Do not use the Windowing mode of the RSWDT and set WDD to 4095 in RSWDT_MR.
54.5
Enhanced Embedded Flash Controller (EEFC)
54.5.1 EEFC: Erase Sector (ES) Command Cannot be Performed if a Subsector is Locked (ONLY in Flash
sector 0)
If one of the subsectors
small sector 0
small sector 1
larger sector
is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked
subsectors. Refer to Section 8.1.4.1 “Flash Overview”.
Problem Fix/Workaround
All the lock bits of the sector 0 must be cleared prior to issuing the ES command. After the ES command has been
issued, the lock bits must be reverted to the state before clearing them.
54.6
Wait For Interrupt (WFI)
54.6.1 Unpredictable Software Behavior When Entering Sleep Mode
When entering Sleep mode, if an interrupt occurs during WFI or WFE instruction (with PMC_FSMR.LPM=0), the
ARM core may read a wrong data, thus leading to unpredictable behavior of the software. This issue is not present
in Wait mode.
Problem Fix/Workaround
The slave interface for the Flash must be set to no default master in the Bus Matrix Controller.
This is done by setting the field DEFMSTR_TYPE in the register MATRIX_SCFG to NO_DEFAULT.
MATRIX_SCFG[2] = MATRIX_SCFG.SLOT_CYCLE(0x1FF) | MATRIX_SCFG.DEFMSTR_TYPE(0x0);
This operation must be done once in the software or the instruction before WFI or WFE.
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54.7
Power Management Controller (PMC)
54.7.1 SRCB Bit in CKGR_PLLB Register
The SRCB bit is programmed in bit 29 of the CKGR_PLLB register but must be read in bit 27 of this register.
Problem Fix/Workaround
For SRCB, read bit 27 of the CKGR_PLLB register.
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55.
Revision History
In the tables that follow, the most recent version of the document appears first.
Table 55-1.
Doc. Rev.
11203E
SAM4CM Datasheet Rev. 11203E Revision History
Changes
Added:
MRL-B for SAM4CMP32C and SAM4CMS32C
MRL-C for SAM4CMP16C, SAM4CMP8C, SAM4CMS16C, SAM4CMS8C and SAM4CMS4C
“Features”
Updated Shared System Controller Clock features
Section 2. “Block Diagram”
Updated Figure 2-1 “SAM4CM Series Block Diagram”
Section 3. “Signal Description”
Table 3-1 “Signal Description List”: updated “Clocks, Oscillators and PLLs” and “Supply Controllers”
Section 4. “Package and Pinout”
Replaced “TMP0” with “WKUP0/TMP0” in pinout tables
Section 5. “Power Supply and Power Control”
Updated Figure 5-1 “Power Domains”
Table 5-1 “Power Supply Voltage Ranges(1)”: added notes (1) and (2)
Updated Section 5.2 “Clock System Overview”
Section 5.5.1.1 “Entering and Exiting Backup Mode”: added note in step (7)
24-Oct-16 Section 5.5.2 “Wait Mode”: updated first paragraph
Section 5.5.2.1 “Entering and Exiting Wait Mode”: updated step (2)
Updated Figure 5-3 “Single Supply Operation with Backup Battery” and Figure 5-4 “Single Power Supply using Battery and
LCD Controller in Backup Mode”
Table 5-2 “Low-power Mode Configuration Summary”: removed column “Mode Entry”
Section 10. “System Controller”
Updated Section 10.2.3 “Power-on Reset on VDDIO”
Section 11. “Peripherals”
Table 11-1 “Peripheral Identifiers”:
- Replaced "Watchdog Timer/Reinforced Watchdog Timer" with "Watchdog Timer"
- Modified EFC1 row
Section 15. “Reset Controller (RSTC)”
Throughout: replaced “is set” with “is written to 1” and “is reset” with “is written to 0”.
Section 15.2 “Embedded Characteristics”: updated "Reset Source Status" characteristic
Reworked Section 15.1 “Description” and Section 15.2 “Embedded Characteristics”
Updated Figure 15-1 “Reset Controller Block Diagram”, Section 15.4.3.3 “Watchdog Reset” and Section 15.4.2.1 “NRST
Signal or Interrupt”
Added Section 15.4.5 “Managing Reset at Application Level”
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Table 55-1.
Doc. Rev.
11203E
SAM4CM Datasheet Rev. 11203E Revision History
Changes
Section 17. “Real-time Clock (RTC)”
Updated Section 17.2 “Embedded Characteristics”
Reworked Section 17.5.6 “Updating Time/Calendar”
Table 17-2 "Register Mapping": added offset 0xCC as reserved
Section 17.6.1 “RTC Control Register”: updated UPDTIM, UPDCAL and CALEVSEL bit description
Deleted “All non-significant bits read zero.” from Section 17.6.3 “RTC Time Register”, Section 17.6.4 “RTC Calendar
Register”, Section 17.6.13 “RTC TimeStamp Time Register 0”, Section 17.6.14 “RTC TimeStamp Time Register 1”,
Section 17.6.15 “RTC TimeStamp Date Register” and Section 17.6.16 “RTC TimeStamp Source Register”
Added sentence on register report of timestamp to Section 17.6.13 “RTC TimeStamp Time Register 0”, Section 17.6.14
“RTC TimeStamp Time Register 1” and Section 17.6.15 “RTC TimeStamp Date Register”
Section 19. “Reinforced Safety Watchdog Timer (RSWDT)”
Removed all references to interrupt by modifying:
- Figure 19-1 “Reinforced Safety Watchdog Timer Block Diagram”
- Section 19.2 “Embedded Characteristics”
- Section 19.4 “Functional Description”
- Section 19.5.2 “Reinforced Safety Watchdog Timer Mode Register” (bit WDFIEN now reserved)
Section 20. “Supply Controller (SUPC)”
Corrected all occurrences of “SCLK” to “SLCK”
Section 20.2 “Embedded Characteristics”: bullet “A Supply Monitor Detection on VDDBU_SW Triggers a System Reset”
changed to “A Zero-power Power-on-reset on VDDBU_SW Triggers a System Reset”
Section 20.4.8.1 “Supply Monitor Reset”: updated second paragraph
24-Oct-16 Section 20.4.9.1 “Force Wakeup”: replaced “the FWUP pin must be low during at least one slow clock period to wake up
(cont’d) the system” with “the FWUP pin must transition from high to low and remain low during at least one slow clock period to
wake up the core power supply”
Section 20.5 “Register Write Protection”: removed “Supply Controller Wake-up Inputs Register” from list of protectable
registers
Added sentence about write protection in Section 20.6.3 “Supply Controller Control Register”, Section 20.6.4 “Supply
Controller Supply Monitor Mode Register”, Section 20.6.5 “Supply Controller Mode Register” and Section 20.6.6 “Supply
Controller Wakeup Mode Register”
Section 20.6.9 “System Controller Write Protection Mode Register”: updated WPEN bit description
Figure 20-2 “Supply Monitor Status Bit and Associated Interrupt”: added SMOS waveform
Changed “Low Level Detect” to “Negative Edge Detector” in Figure 20-4 “SAM4CM16/8/4 Wakeup Sources” and Figure
20-5 “SAM4CM32 Wakeup Sources”
Section 21. “General Purpose Backup Registers (GPBR)”
Section 21.1 “Description”: reworded parts related to tamper pins
Section 21.2 “Embedded Characteristics”: added "Immediate Clear on Tamper Event" characteristic
Section 23. “Fast Flash Programming Interface (FFPI)”
Table 23-1 “Signal Description List”: updated XIN information
Section 23.3.3 “Entering Parallel Programming Mode”: deleted note on device clocking.
Figure 23-1 “16-bit Parallel Programming Interface”: changed input source for XIN
Section 31. “Chip Identifier (CHIPID)”
Updated Table 31-1 "SAM4CM Chip ID Registers" with:
MRL-B for SAM4CMP32C and SAM4CMS32C
MRL-C for SAM4CMP16C, SAM4CMP8C, SAM4CMS16C, SAM4CMS8C and SAM4CMS4C
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Table 55-1.
Doc. Rev.
11203E
SAM4CM Datasheet Rev. 11203E Revision History
Changes
Section 39. “Segment Liquid Crystal Display Controller (SLCDC)”
Removed all information related to Register Write Protection, including SLCDC Write Protection Mode Register
(SLCDC_WPMR) and SLCDC Write Protection Status Register (SLCDC_WPSR)
Added Table 39-1 “List of Terms”
Section 40. “Analog-to-Digital Converter (ADC)”
Updated Figure 40-1 “Analog-to-Digital Converter Block Diagram”
Reworked Section 40.5.5 “I/O Lines”
Section 40.7.18 “ADC Analog Control Register”: updated FORCEREF and ONREF bit descriptions
Section 46. “Electrical Characteristics”
Reorganized Section 46.2 “Recommended Operating Conditions” and added Section 46.2.1 “Recommended Operating
Conditions on Power Supply Inputs” and Section 46.2.2 “Recommended Power Supply Conditions at Powerup”
Table 46-2 “Recommended DC Operating Conditions on Power Supply Inputs”: added notes (1) and (4)
Section 46.4.3 “SPI Characteristics”: added introduction and Figure 46-3 “MISO Capture in Master Mode”
Section 46.4.3.1 “Maximum SPI Frequency”: updated paragraph “Master Read Mode” (removed Atmel SPI DataFlash
information)
Table 46-7 “I/O DC Characteristics”: changed VOL from 0.4V to 0.45V and from 0.6V to 0.65V
24-Oct-16 Updated Table 46-35 “Temperature Sensor Characteristics”
(cont’d) Table 46-47 “Current or Voltage Measurement Channel Electrical Characteristics”: in row ZIN0, Common mode input
impedance, replaced “On VPx, VIPx, VINx pins” with “On VPx, IPx, INx pins”
Table 46-48 “EMAFE Precision Voltage Reference and Die Temperature Sensor Characteristics”: added TCVREF_C max
value
Section 49. “Ordering Information”
Table 49-1 “Ordering Codes for SAM4CM Devices”:
- Added new ordering codes
- Reorganized table rows
- Removed column “Package Type” (Green is the only available package type now)
Section 50. “SAM4CM16/8 Errata Revision A (MRL A) Parts”
Added Section 50.10.1 “EMAFE Accuracy”
Section 51. “SAM4CM16/8/4 Errata Revision B (MRL B) Parts”
Added Section 51.9.1 “EMAFE Accuracy”
Added Section 52. “SAM4CM16/8/4 Errata Revision C (MRL C) Parts”
Section 53. “SAM4CM32 Errata Revision A (MRL A) Parts”
Added Section 53.8.1 “EMAFE Accuracy”
Added Section 54. “SAM4CM32 Errata Revision B (MRL B) Parts”
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Table 55-2.
Doc. Rev.
11203D
SAM4CM Datasheet Rev. 11203D Revision History
Changes
Added device SAM4CMS4C. Modifications made accordingly throughout the datasheet.
Section 1. “Configuration Summary”
Updated Table 1-1 “Configuration Summary”
Section 2. “Block Diagram”
Consolidated block diagrams into a single figure: Figure 2-1 “SAM4CM Series Block Diagram”
Section 5. “Power Supply and Power Control”
Updated Section 5.1.5.2 “Single Supply Operation with Backup Battery”
Modified Figure 5-1 “Power Domains”, Figure 5-2 “Single Supply Operation”, Figure 5-3 “Single Supply Operation with
Backup Battery”, Figure 5-4 “Single Power Supply using Battery and LCD Controller in Backup Mode”
Section 6. “Input/Output Lines”
Updated Section 6.9 “ERASE Pin”
Section 15. “Reset Controller (RSTC)”
Table 15-1 “Register Mapping”: added note (1) to reset value of register RSTC_SR
Section 16. “Real-time Timer (RTT)”
Section 16.5.4 “Real-time Timer Status Register”: updated bit descriptions
Section 17. “Real-time Clock (RTC)”
27-Mar-15
Modified Figure 17-1 “RTC Block Diagram”
Updated Section 17.5.7 “RTC Accurate Clock Calibration”
Section 18. “Watchdog Timer (WDT)”
Section 18.5.3 “Watchdog Timer Status Register”: updated bit descriptions WDUNF and WDERR
Section 19. “Reinforced Safety Watchdog Timer (RSWDT)”
Updated Section 19.1 “Description”
Section 19.2 “Embedded Characteristics”: removed characteristic “System safety level reinforced by means of an
independent second watchdog timer”
Section 20. “Supply Controller (SUPC)”
Modified Figure 20-4 “SAM4CM16/8/4 Wake-up Sources” and Figure 20-5 “SAM4CM32 Wake-up Sources”
Updated Section 20.4.9.2 “Wake-up Inputs” and added Figure 20-6 “Entering and Exiting Backup Mode with a WKUP pin”
Section 21. “General Purpose Backup Registers (GPBR)”
Updated Section 21.3.1 “General Purpose Backup Register x”
Section 22. “Enhanced Embedded Flash Controller (EEFC)”
Added Figure 22-1 “Flash Memory Areas”
Modified Figure 22-3 “Code Read Optimization for FWS = 0” and Figure 22-4 “Code Read Optimization for FWS = 3”
Updated Section 22.2 “Embedded Characteristics”, Section 22.4.3.2 “Write Commands” and Section 22.4.3.9 “User
Signature Area”
Section 22.5.2 “EEFC Flash Command Register”: corrected FARG description for EPA command
Section 22.5.3 “EEFC Flash Status Register”: updated bit descriptions
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Table 55-2.
Doc. Rev.
11203D
SAM4CM Datasheet Rev. 11203D Revision History
Changes
Section 24. “Cortex-M Cache Controller (CMCC)”
Section 24.5.2 “Cache Controller Control Register”, Section 24.5.3 “Cache Controller Status Register”, Section 24.5.4
“Cache Controller Maintenance Register 0”, Section 24.5.7 “Cache Controller Monitor Enable Register”, Section 24.5.8
“Cache Controller Monitor Control Register”: updated bit descriptions
Section 24.5.6 “Cache Controller Monitor Configuration Register” and Section 24.5.7 “Cache Controller Monitor Enable
Register”: changed access from Write-only to Read/Write
Section 26. “Bus Matrix (MATRIX)”
Updated Section 26.8 “Register Write Protection”
Section 26.9.8 “Write Protection Status Register”: modified WPVS bit description
Section 27. “Static Memory Controller (SMC)”
Updated Section 27.9.5 “Register Write Protection” and added information on write protection to Section 27.16.1 “SMC
Setup Register”, Section 27.16.2 “SMC Pulse Register”, Section 27.16.3 “SMC Cycle Register” and Section 27.16.4 “SMC
MODE Register”
Updated Section 27.10 “Scrambling/Unscrambling Function”, Section 27.16.8 “SMC Write Protection Mode Register” and
Section 27.16.9 “SMC Write Protection Status Register”
Section 29. “Clock Generator”
Updated Section 29.5.6 “Main Clock Frequency Counter” and Section 29.5.7 “Switching Main Clock between the RC
Oscillator and the Crystal Oscillator”
Section 30. “Power Management Controller (PMC)”
Updated Section 30.13 “Main Clock Failure Detector”
Section 30.18.8 “PMC Clock Generator Main Clock Frequency Register”: updated MAINF bit description
Section 31. “Chip Identifier (CHIPID)”
27-Mar-15
Section 31.3.1 “Chip ID Register”: added field 256K and modified size of field VERSION
(cont’d)
Section 32. “Parallel Input/Output Controller (PIO)”
Modified Figure 32-1 “Block Diagram”
Updated Section 32.5.3 “Peripheral A or B or C or D Selection” and Section 32.6.32 “PIO Pad Pull-Down Status Register”
Section 33. “Serial Peripheral Interface (SPI)”
Modified Figure 33-7 “Master Mode Flow Diagram”
Updated Section 33.7.3.5 “Peripheral Selection”, Section 33.7.3.6 “SPI Peripheral DMA Controller (PDC)”, and Section
33.7.3.8 “Peripheral Deselection without PDC”
Section 33.7.3 “Master Mode Operations”: modified description of flags TDRE and TXEMPTY, and added Figure 33-5
“TDRE and TXEMPTY flag behavior”
Section 33.8.1 “SPI Control Register”, Section 33.8.5 “SPI Status Register” and Section 33.8.9 “SPI Chip Select Register”:
updated bit descriptions
Section 34. “Two-wire Interface (TWI)”
Updated Section 34.1 “Description”
Modified Figure 34.4 “Block Diagram”, Figure 34-24 “Slave Mode Typical Application Block Diagram”, Figure 34-25 “Read
Access Ordered by a Master”, Figure 34-26 “Write Access Ordered by a Master”, Figure 34-27 “Master Performs a General
Call”, Figure 34-29 “Clock Synchronization in Write Mode”, Figure 34-32 “Read Write Flowchart in Slave Mode”
Replaced Section 34.5 “Application Block Diagram” with updated Section 34.5 “I/O Lines Description”
Section 34.8.5 “TWI Clock Waveform Generator Register” and Section 34.8.6 “TWI Status Register”: updated bit
descriptions
In procedures, replaced “(Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.”
with “(Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR.”
Section 34.7.3.4 “Master Transmitter Mode”: modified description of NACK
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Table 55-2.
Doc. Rev.
11203D
SAM4CM Datasheet Rev. 11203D Revision History
Changes
Section 35. “Universal Asynchronous Receiver Transmitter (UART)”
Modified Figure 35-2 “Baud Rate Generator”
Section 35.6.9 “UART Baud Rate Generator Register”: updated CD bit description
Section 36. “Universal Synchronous Asynchronous Receiver Transceiver (USART)”
Removed all references to bit RXIDLEV
Updated Section 36.5.1 “I/O Lines”, Section 36.6.1 “Baud Rate Generator”, Section 36.6.3.15 “Hardware Handshaking”,
Section 36.6.9 “Register Write Protection”
Section 36.7.1 “USART Control Register”, Section 36.7.3 “USART Mode Register”, Section 36.7.6 “USART Interrupt
Enable Register (SPI_MODE)”, Section 36.7.8 “USART Interrupt Disable Register (SPI_MODE)”, Section 36.7.10 “USART
Interrupt Mask Register (SPI_MODE)”, Section 36.7.11 “USART Channel Status Register”, Section 36.7.12 “USART
Channel Status Register (SPI_MODE)”, Section 36.7.15 “USART Baud Rate Generator Register”, Section 36.7.16
“USART Receiver Time-out Register”, Section 36.7.17 “USART Transmitter Timeguard Register”: updated bit descriptions
Updated Table 36-14 “Register Mapping”
Section 37. “Timer Counter (TC)”
Updated Section 37.1 “Description”, Section 37.5.2 “Power Management”, Section 37.5.3 “Interrupt Sources”, Section
37.6.14.4 “Position and Rotation Measurement”, Section 37.6.14.5 “Speed Measurement” and Section 37.6.16 “Register
Write Protection”
Section 37.6.14 “Quadrature Decoder”: removed subsection “Missing Pulse Detection and Auto-correction”
Section 37.7.2 “TC Channel Mode Register: Capture Mode”: in ‘Name’ line, replaced “(WAVE = 0)” with
“(CAPTURE_MODE)”
27-Mar-15 Section 37.7.3 “TC Channel Mode Register: Waveform Mode”: in ‘Name’ line, replaced “(WAVE = 1)” with
(cont’d) “(WAVEFORM_MODE)”
Section 37.7.5 “TC Counter Value Register”, Section 37.7.6 “TC Register A”, Section 37.7.7 “TC Register B”, Section
37.7.8 “TC Register C”: added ‘IMPORTANT’ note
Section 37.7.9 “TC Status Register”, Section 37.7.19 “TC Write Protection Mode Register”: updated bit descriptions
Section 37.7.14 “TC Block Mode Register”: removed AUTOC bit and MAXCMP field
Section 37.7.18 “TC QDEC Interrupt Status Register”: removed MPE bit
Section 42. “Advanced Encryption Standard (AES)”
Added Section 42.4.1 “AES Register Endianism”
Section 42.5.6 “AES Interrupt Status Register”: updated bit descriptions
Section 43. “Integrity Check Monitor (ICM)”
Updated Section 43.5.1 “Overview”, Section 43.5.4 “Using ICM as SHA Engine”
Section 43.5.2.2 “ICM Region Configuration Structure Member”, Section 43.6.1 “ICM Configuration Register”, Section
43.6.3 “ICM Status Register”: updated bit descriptions
Section 45. “True Random Number Generator (TRNG)”
Updated Section 45.5 “Functional Description” and Table 45-2 “Register Mapping”
Section 46. “Electrical Characteristics”
Updated Table 46-1 “Absolute Maximum Ratings*” and Table 46-3 “Recommended Operating Conditions on Input Pins”
Updated Figure 46-19 “Typical Current Consumption in Backup Mode for Configurations C and D”
Added footnotes (4) and (5) in Table 46-5 “I/O DC Characteristics”
Updated VDDIN min. value in Table 46-41 “Programmable Voltage Reference Characteristics”
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Changes
Added SAM4CMP32C and SAM4CMS32C devices. Modifications throughout datasheet for these devices.
“Features”
In section “Safety”, modified information on anti-tamper detection I/Os.
Section 1. “Configuration Summary”
Added SAM4CMP32C and SAM4CMS32C devices.
Section 2. “Block Diagram”
Figure 2-1 “SAM4CM Series 100-pin Block Diagram”: Added TRACESWO to TDO pin.Added WKUP[0:13]. Moved Dual
Watchdog block out of backup zone. Added power supply for Segment LCD Controller.
Section 3. “Signal Description”
Table 3-1 “Signal Description List”: Added section with Supply Controller signals, including WKUP0 and WKUP[1:13].
Removed ADTRG signal. Removed PGMCK signal.
Section 5. “Power Supply and Power Control”
Updated Table 5-1 “Power Supply Voltage Ranges”.
Modified Section 5.1.2 “LCD Voltage Regulator”.
Modified Section 5.1.3 “Automatic Power Switch”.
06-Oct-14
Modified Section 5.1.5 “Typical Powering Schematics”..
Removed Note (2) on EMAFE following Figure 5-2 “Single Supply Operation”.
Modified Section 5.1.5.3 “Single Power Supply using One Main Battery and LCD Controller in Backup Mode”.
Updated Section 5.3.2 “Device Configuration after a Power Cycle when Booting from Flash Memory” and Section 5.3.3
“Device Configuration after a Reset”.
Modified Note in Section 5.5 “Low-power Modes”.
Added step 8 to Section 5.5.1.1 “Entering and Exiting Backup Mode”.
Table 5-2 “Low-power Mode Configuration Summary”: Removed column Current Consumption and updated Notes
below.
Section 6. “Input/Output Lines”
Changed Section 6.3 title from “Test Pin” to “TST Pin”.
Section 6.7 “Shutdown (SHDN) Pin”: removed sentence on SHDN pin controlling an external voltage regulator and/or
power switch.
Updated Section 6.9 “ERASE Pin”.
Section 7. “Product Mapping and Peripheral Access”
Added Figure 7-3 “SAM4CM32 Memory Mapping of CODE and SRAM Area” and Figure 7-5 “SAM4CM32 Memory
Mapping of the Peripherals Area”.
Updated Figure 7-6 “SAM4CM32/16/8 Memory Mapping of External SRAM and External Devices Area”.
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Changes
Section 8. “Memories”
Updated Section 8.1.1 “Internal SRAM”.
Added dual-plane feature in Section 8.1.4 “Embedded Flash”, changed Figure 8-1 “Dual Bank and Dual Boot Firmware
Upgrade”. Added Table 8-1 “SAM4CM Flash Size”.
Updated Section 8.1.4.5 “Security Bit”.
Updated Table 8-2 “Lock Bit Number”. Updated Section 8.1.4.10 “GPNVM Bits” and Table 8-3 “General-purpose
Nonvolatile Memory Bits”.
Added Section 8.1.5.4 “Sub-system 1 Start-up Time”. .
Removed Section 8.2.1 “Static Memory Controller” from Section 8.2 “External Memories”
Section 10. “System Controller”
Updated Section 10.2.4 “Supply Monitor on VDDIO”.
Updated Section 10.3 “Reset Controller”.
Section 11. “Peripherals”
Table 11-1 “Peripheral Identifiers”: Modified WDT (ID 4).
Table 11-4 “I/O Line Features Abbreviations”: removed Medium Drive. Added Maximum Drive.
Table 11-5 “Multiplexing on PIO Controller A (PIOA)”, Table 11-6 “Multiplexing on PIO Controller B (PIOB)”, Table 11-7
“Multiplexing on PIO Controller C (PIOC)”: modified Features column in all tables for all I/O lines.
Section 12. “ARM Cortex-M4 Processor”
Corrected instruction in Section 12.5.3 “Power Management Programming Hints”.
Updated Table 12-5 “Memory Region Shareability Policies”.
06-Oct-14
Updated Table 12-11 “Faults”.
Updated Table 12-41 “Memory Protection Unit (MPU) Register Mapping” with new register names for MPU_RASR_Ax
and MPU_RBSR_Ax.
Updated Table 12-31 “Mapping of Interrupts to the Interrupt Variables”.
Section 12.9.1.13 “Configurable Fault Status Register”: added LSPERR bit.
Section 14. “Boot Program”
Section 14.5.3 “In Application Programming (IAP) Feature”: Corrected MC_FSR to EEFC_FSR.
Section 15. “Reset Controller (RSTC)”
Section 15.4.1 “Reset Controller Overview”: changed events that that trigger assertion of reset signals by the RSTC.
Changed VDD_REG_BU to VDDBU.
Removed section “Brownout Manager”.
Section 15.4.3.2 “Backup Reset”: replaced “core_backup_reset” with “vddcore_nreset”.
Section 15.5.1 “Reset Controller Control Register”: modified EXTRST description.
Section 15.5.2 “Reset Controller Status Register”: modified bit descriptions.
Section 15.5.3 “Reset Controller Mode Register”: modified ERSTL bit description.
Section 16. “Real-time Timer (RTT)”
Modified Section 16.4 “Functional Description”.
Section 16.5.1 “Real-time Timer Mode Register”: modified RTPRES description.
Section 16.5.2 “Real-time Timer Alarm Register”: modified ALMV description.
Section 16.5.3 “Real-time Timer Value Register”: added notes.
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Changes
Section 17. “Real-time Clock (RTC)”
Section 17.5.7 “RTC Accurate Clock Calibration”; modified paragraph on calibration circuitry. Added paragraph on clock
calibration correction.
Section 17.6.2 “RTC Mode Register”: modified descriptions of NEGPPM, HIGHPPM and THIGH bits.
Added Section 17.6.17 “RTC Write Protection Mode Register”.
Section 18. “Watchdog Timer (WDT)”
Modified Figure 18-2 “Watchdog Behavior”.
Section 19. “Reinforced Safety Watchdog Timer (RSWDT)”
Added Windowed Watchdog in Section 19.2 “Embedded Characteristics” and Section 19.4 “Functional Description”.
Modified Figure 19-2 “Watchdog Behavior”.
Section 19.5.2 “Reinforced Safety Watchdog Timer Mode Register”: added notes.
Section 20. “Supply Controller (SUPC)”
Section 20.4.2 “Slow Clock Generator”: updated information on entering Bypass mode using OSCBYPASS and
XTSALSEL bits.
Section 20.4.4 “Segmented LCD Voltage Regulator Control”: changed the section name and aligned references to
SLCD and SLCD Controller in the text. Updated content.
Section 20.4.6 “Supply Monitor”: Supply Monitor sampling mode, power reduction factor: replaced incorrect values of
32, 256 or 2048 by the correct values of 2, 16 and 128.
Figure 20-4 “SAM4CM16/8 Wake-up Sources”: modified to show that wake-up input detectors are based on edges.
06-Oct-14
Added Figure 20-5 “SAM4CM32 Wake-up Sources”.
Section 20.4.9.1 “Force Wake-up”: corrected bit name from FWUP to FWUPS in 2nd paragraph.
Section 20.4.9.2 “Wake-up Inputs”: corrected polarity bit name from WKUPPL to WKUPT.
Section 20.4.9.3 “Low-power Debouncer Inputs (Tamper Detection Pins)”: added information on SAM4CM32 devices.
Corrected register names for WKUPTx bits and LPDBCCLR bit.
Section 20.6.5 “Supply Controller Mode Register”: changed OSCBYPASS bit description.
Section 20.6.8 “Supply Controller Status Register”: updated to bit descriptions as ‘cleared on read’ where applicable.
Updated the bit description for WKUPIS = 1
Section 22. “Enhanced Embedded Flash Controller (EEFC)”
Number of GPNVM bits changed to 3 for SAM4C32.
Added informaton on dual-plane configuration available for SAM4C32.
Section 27. “Static Memory Controller (SMC)”
Section 27.2 “Embedded Characteristics”: added bullet for Byte Write or Byte Select Lines
Table 27-1 “I/O Line Description”: updated with latch enables
Table 27-2 “Static Memory Controller (SMC) Multiplexed Signals”: completed table with relevant information.
Added text and figures for 16-bit memory connections in Section 27.6 “External Memory Mapping”, Section 27.7.1 “Data
Bus Width”, Section 27.7.2 “Byte Write or Byte Select Access”, Section 27.9 “Standard Read and Write Protocols” and
Section 27.10 “Scrambling/Unscrambling Function”.
Table 27-5 “Reset Values of Timing Parameters”: Modified reset values.
Section 27.16.4 “SMC MODE Register”: added BAT bit.
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Changes
Section 29. “Clock Generator”
Section 29.2 “Embedded Characteristics”: removed “Write Protected Regsiters”.
Figure 29-1 “Clock Generator Block Diagram” and Figure 29-4 “Dividers and PLL Block Diagram” Updated for clarity.
Added Section 29.5.5 “Bypassing the Main Crystal Oscillator”.
Added Section 29.5.6 “Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator”.
Section 29.6.1 “Divider and Phase Lock Loop Programming”: introduced the notion that the user must wait for a delay of
two SLCK clock cycles between the disable command and the actual disable of the PLL. Removed ‘LOCK’ from step 4.
Section 30. “Power Management Controller (PMC)”
Updated Section 30.2 “Embedded Characteristics”.
Figure 30-1 “General Clock Block Diagram”: Updated for clarity, relocate on/off switch for usb and pck..
Section 30.10 “Main Processor Fast Startup”: Updated for clarity.
Added Section 30.11 “Main Processor Startup from Embedded Flash”.
Section 30.13 “Main Clock Failure Detector”: Updated for clarity.
Section 30.14 “Slow Crystal Clock Frequency Monitor”: added “The SEL4/SEL8/SEL12 bits of PMC_OCR must be
cleared”.
Section 30.15 “Programming Sequence”: Updated for clarity.
Section 30.18 “Power Management Controller (PMC) User Interface”: corrected PMC_SR reset value.
Section 30.18.7 “PMC Clock Generator Main Oscillator Register”: added note to MOSCXTBY bit description.
Section 30.18.8 “PMC Clock Generator Main Clock Frequency Register”: Updated MAINF and MAINFRDY bit
descriptions.
06-Oct-14
Section 30.18.9 “PMC Clock Generator PLLA Register”: updated MULA bit description.
Section 30.18.10 “PMC Clock Generator PLLB Register”: changed SRCB bit description. Changed MULB bit
description.
Section 31. “Chip Identifier (CHIPID)”
Table 31-1 “SAM4CM Chip ID Registers”: Updated with new devices.
Section 31.3.1 “Chip ID Register”: “NVPSIZ: Nonvolatile Program Memory Size”: Changed information in row for Value
8.
Changed “ARCH: Architecture Identifier” bit information.
Section 32. “Parallel Input/Output (PIO3) Controller”
‘PIO clock” and “PIO controller clock’ replaced by ‘peripheral clock’ throughout.
‘MCK’ and ‘mck’ replaced by ‘peripheral clock’ throughout.
Removed section “External Interrupt Lines”.
Updated Figure 32-2 “I/O Line Control Logic”.
Section 32.5.1 “Pull-up and Pull-down Resistor Control”: Added information on setting pull-up and pull-down.
Section 32.5.3 “Peripheral A or B or C or D Selection”: Added information on products that do not have A, B, C and D
peripherals.
Section 32.5.11 “Programmable I/O Drive”: Corrected list of configurable pads.
Section 32.6.38 “PIO Additional Interrupt Modes Mask Register”: Updated bit description.
Modified Section 32.6.48 “PIO I/O Drive Register” (was PIO I/O Drive Register 1).
Removed section “PIO I/O Drive Register 2”.
Updated Table 32-3 “Register Mapping” for Drive Registers changes.
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Changes
Section 33. “Serial Peripheral Interface (SPI)”
‘MCK’ replaced by ‘peripheral clock’ throughout.
Section 33.2 “Embedded Characteristics”: Reworked list.
Reworked Figure 33-1 “Block Diagram”, Figure 33-3 “SPI Transfer Format (NCPHA = 1, 8 bits per transfer)” and Figure
33-4 “SPI Transfer Format (NCPHA = 0, 8 bits per transfer)”.
Modified Section 33.7.3 “Master Mode Operations”.
Section 33.7.3.6 “SPI Peripheral DMA Controller (PDC)”, section “Transfer Size”: under “Fixed mode” replaced “8-bit to
16-bit data” with “9-bit to 16-bit data”.
Section 33.8.2 “SPI Mode Register”: Modified DLYBCS bit description.
Section 33.8.9 “SPI Chip Select Register”: Added register addresses. Updated CSNAAT bit description. Updated
descriptions of bits SCBR, DLYBS, and DLYBCT.
Section 34. “Two-wire Interface (TWI2)”
‘MCK’ replaced by ‘peripheral clock’ throughout.
06-Oct-14
Table 34-1 “Atmel TWI Compatibility with I2C Standard”: Clock synchronization added as supported feature.
Section 34.7.3.3 “Programming Master Mode”: Added Note after section. Removed references to TWIHS.
Section 34.7.3.7 “Using the Peripheral DMA Controller (PDC)”: Modified “Data Transmit with the PDC” and “Data
Receive with the PDC”.
“Clock Synchronization in Write Mode”: At end of last sentence, changed “in Read mode” to “in Write mode”.
Section 34.7.3.5 “Master Receiver Mode”: Removed reference to clock stretching in the “Warning”. (clock stretching is a
slave-only mechanism)
Figure 34-11 “Master Read Wait State with Multiple Data Bytes”: Changed title and figure to remove references to clock
stretching reference (slave-only mechanism)
Section 34.7.5.4 “Receiving Data”: Removed reference to TWI_THR.
“Clock Stretching Sequence”: Added section which refers only to TWI_THR.
“Clock Synchronization/Stretching” Changed the section name and updated.
Section 35. “Universal Asynchronous Receiver Transmitter (UART)”
‘MCK’ replaced by ‘peripheral clock’ throughout.
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SAM4CM Datasheet Rev. 11203C Revision History (Continued)
Changes
Section 36. “Universal Synchronous Asynchronous Receiver Transmitter (USART)”
‘MCK’ replaced by ‘peripheral clock’ throughout.
Section 36.2 “Embedded Characteristics”: Added ‘Digital Filter on Receive LIne’ bullet
Updated Figure 36-1 “USART Block Diagram”.
Removed table “SPI Operating Mode”.
Section 36.6.1 “Baud Rate Generator”: updated 4th paragraph and figure.
Updated information on RXIDLEV bit in Section 36.6.3.2 “Manchester Encoder” and Section 36.7.21 “USART
Manchester Configuration Register”.
Updated Figure 36-36 “Example of RTS Drive with Timeguard”.
Table 36-7 “Possible Values for the Fi/Di Ratio”: in top row, replaced “774” with “744”.
Section “Transmit Character Repetition”: updated 3rd paragraph.
Section “Disable Successive Receive NACK”: updated last sentence.
Section 36.6.7.5 “Character Transmission”: INACK replaced by WRDBT.
Table 36-14 “Register Mapping”: US_MAN reset value corrected to 0x30011004.
Section 36.7.3 “USART Mode Register”: Updated USART_MODE, USCLKS and PAR field descriptions. Added note on
MAX_ITERATION field to DSNACK bit description.
Section 36.7.4 “USART Mode Register (SPI_MODE)”: Deleted CHMODE filed description and added CLKO bit.
06-Oct-14
Updated ENDRX, ENDTX, TXBUFE, and RXBUFF bit descriptions in Section 36.7.5 “USART Interrupt Enable
Register”, Section 36.7.6 “USART Interrupt Enable Register (SPI_MODE)”, Section 36.7.7 “USART Interrupt Disable
Register”, Section 36.7.9 “USART Interrupt Mask Register” and Section 36.7.11 “USART Channel Status Register”.
Updated RXRDY, TXRDY, TXEMPTY, ITER and CTSIC bit descriptions in Section 36.7.11 “USART Channel Status
Register”.
Updated RXRDY, TXRDY, and TXEMPTY bit descriptions in Section 36.7.12 “USART Channel Status Register
(SPI_MODE)”
Section 36.7.18 “USART FI DI RATIO Register”: FI_DI_RATIO field now 11 bits wide and updated description.
Section 37. “Timer Counter (TC)”
‘MCK’ replaced by ‘peripheral clock’ throughout.
Added Section 37.6.14.6 “Missing Pulse Detection and Auto-correction”.
Section 37.7.14 “TC Block Mode Register”: Removed FILTER bit (register bit 19 now reserved). Added AUTOC bit and
MAXCMP field.
Section 37.7.18 “TC QDEC Interrupt Status Register”: Added MPE bit.
Section 39. “Segment Liquid Crystal Display Controller (SLCDC)”
‘SCLK’ replaced by ‘SLCK’ throughout.
Updated Section 39.5.2 “Power Management”.
In Section 39.5 “Product Dependencies”, removed section “Number of Segments and Commons”.
Revised Section 39.6.7 “Disabling the SLCDC” (was “Disable Sequence”).
Section 39.8.8 “SLCDC Interrupt Mask Register”: Modified access to Read-only.
Updated DIS bit descriptions.
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Changes
Section 40. “Analog-to-Digital Converter (ADC)”
Replaced references to ‘MCK’ with ‘peripheral clock’ in text and figures.
Section 40.1 “Description””: corrected name of register for ONREF and FORCEREF bits from ADC_SR to ADC_ISR.
Figure 40-1 “Analog-to-Digital Converter Block Diagram”: added bus clock. Added ADC Clock output from Control Logic
block.
Added Table 40-2 “Peripheral IDs” and Table 40-3 “I/O Lines”.
Renamed Figure 40-4 from GOVRE and OVREx Flag Behavior to “EOCx, GOVRE and OVREx Flag Behavior”.
Corrected ADC_SR to ADC_ISR in Figure 40-3 “EOCx and DRDY Flag Behavior” and Figure 40-4 “EOCx, GOVRE and
OVREx Flag Behavior”.
Modified warning below Figure 40-4 “EOCx, GOVRE and OVREx Flag Behavior”.
Section 40.6.6 “Sleep Mode and Conversion Sequencer”: removed description of ADC channel use on an application
board (3 paragraphs).
In Figure 40-6 “Non-optimized Temperature Conversion” to Figure 40-11 “Digital Averaging Function Waveforms on
Single Trigger Event, Non-interleaved”: added note on ADC_SEL.
Section 40.7.5 “ADC Channel Disable Register”: modified warning below bit description.
06-Oct-14
Section 40.7.11 “ADC Interrupt Status Register”: updated all bit descriptions with information on status. Corrected
COMPE bit name and description; changed ‘error’ to ‘event’. Modified ENDRX and RXBUFF bit descriptions.
Added addresses for all registers.
Section 42. “Advanced Encryption Standard (AES)”
Updated Section 42.4.4.3 “If AES_MR.LOD = 1”
Updated Figure 42-4 “PDC transfer with AES_MR.LOD = 1”.
Updated Section 42.4.5 “Galois/Counter Mode (GCM)”.
Section 42.5.2 “AES Mode Register”: Updated PROCDLY bit description.
Section 42.5.3 “AES Interrupt Enable Register”, Section 42.5.4 “AES Interrupt Disable Register”, Section 42.5.5 “AES
Interrupt Mask Register”, Section 42.5.6 “AES Interrupt Status Register”: added TAGRDY bit.
Section 43. “Integrity Check Monitor (ICM)”
Updated Section 43.1 “Description”.
Renamed Figure 43-1 “Four-region Monitoring Example” (was “Integrity Check Monitor Integrated in the System”).
Inserted Table 43-1 “Peripheral IDs”.
Section 43.5.1.2 “ICM Region Configuration Structure Member”: Corrected configuration value descriptions for bits
RHIEN, DMIEN, BEIEN, WCIEN, ECIEN and SUIEN.
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SAM4CM Datasheet Rev. 11203C Revision History (Continued)
Changes
Section 46. “Electrical Characteristics”
Table 46-2 “Recommended Operating Conditions on Power Supply Inputs”: changed min value of VDDLCD. modified
column “Conditions” for all parameters. Added notes at end of table.
Updated RJA and PD in Table 46-4 “Recommended Thermal Operating Conditions”.
Table 46-7 “Input Characteristics”: added mention of voltage reference to VDDIO in paragraph preceding table.
Updated Table 46-8 “SPI Timings”.
Updated Table 46-9 “SMC Read Signals - NRD Controlled (READ_MODE = 1)”, Table 46-10 “SMC Read Signals - NCS
Controlled (READ_MODE= 0)”, Table 46-11 “SMC Write Signals - NWE Controlled (WRITE_MODE = 1)” and Table 4612 “SMC Write NCS Controlled (WRITE_MODE = 0)”.
Updated Table 46-13 “USART SPI Timings”.
In Table 46-18 “LCD Buffers Characteristics”, changed max value for ZOUT ‘Buffer output impedance’. Changed
convergence value and max value for tr / tf ‘Rising or falling time’.
Table 46-21 “VDDIO Supply Monitor”: added Note (2). Removed figure “VDDIO Supply Monitor”.
Improved definition of parameters and modified equations and figures in Section 46.5.11 “32.768 kHz Crystal Oscillator”
and Section 46.5.12 “3 to 20 MHz Crystal Oscillator”.
Table 46-27 “32.768 kHz Crystal Oscillator Characteristics”: modified min/typ/max values for CLEXT.
Table 46-33 “Temperature Sensor Characteristics”: modified condition of parameter VT settling time.
Table 46-35 “ADC Power Supply Characteristics”: modified typ for supply voltage range (VDDIN).
Table 46-36 “ADC Voltage Reference Input Characteristics (ADVREF pin)”: modified min value of VADVREF
Table 46-41 “Programmable Voltage Reference Characteristics”: modified condition for VADVREF
Table 46-45 “Current or Voltage Measurement Channel Electrical Characteristics”: modified max value IDDON when OFF
Added Section 46.6.2.2 “SAM4CM32 Flash Wait States and Operating Frequency”.
06-Oct-14
Added Table 46-53 “SAM4CM32 Typical Current Consumption Values for Backup Mode Configurations A and B” and
Figure 46-17 “Typical Current Consumption in Backup Mode for Configurations A and B”.
Modified Table 46-54 “SAM4CM8/16 Typical Current Consumption Values for Backup Mode Configurations C and D”.
Added Table 46-55 “SAM4CM32 Typical Current Consumption Values for Backup Mode Configurations C and D” and
Figure 46-19 “Typical Current Consumption in Backup Mode for Configurations C and D”.
Updated Section 46.7.2.1 “Wait Mode Configuration”.
Updated Table 46-56 “SAM4CM8/16 Typical Current Consumption in Wait Mode”.
Added Table 46-57 “SAM4CM32 Typical Current Consumption in Wait Mode”.
Section 46.7.3 “Sleep Mode Current Consumption”: modified information on sub-system frequencies in bullets.
Updated Table 46-58 “SAM4CM8/16 Typical Sleep Mode Current Consumption Versus Frequency”.
Added Table 46-59 “SAM4CM32 Typical Sleep Mode Current Consumption Versus Frequency”. Added Figure 46-22
“Typical Current Consumption in Sleep Mode”.
Section 46.7.4 “Active Mode Power Consumption”: modified information on sub-system frequencies in bullets.
Updated Table 46-60 “SAM4CM8/16 Test Setup 1 Current Consumption”. Added Table 46-61 “SAM4CM32 Test Setup
1 Current Consumption” and Figure 46-24 “Typical Current Consumption in Active Mode (Test Setup 1)”.
Updated Table 46-62 “SAM4CM8/16 Test Setup 2 Current Consumption”. Added Table 46-63 “SAM4CM32 Test Setup
2 Current Consumption” and Figure 46-25 “Typical Current Consumption in Active Mode (Test Setup 2)”.
Updated Table 46-64 “SAM4CM8/16 Test Setup 3 Current Consumption”. Added Table 46-65 “SAM4CM32 Test Setup
3 Current Consumption” and Figure 46-26 “Typical Current Consumption in Active Mode (Test Setup 3)”.
Updated Table 46-66 “SAM4CM8/16 Test Setup 4 Current Consumption”. Added Table 46-67 “SAM4CM32 Test Setup
4 Current Consumption” and Figure 46-27 “Typical Current Consumption in Active Mode (Test Setup 4)”.
Updated Table 46-68 “SAM4CM8/16 Test Setup 5 Current Consumption”. Added Table 46-69 “SAM4CM32Test Setup 5
Current Consumption” and Figure 46-28 “Typical Current Consumption in Active Mode (Test Setup 5)”.
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Changes
Section 49. “Ordering Information”
Updated Table 49-1 “Ordering Codes for SAM4CM Devices”.
Section 50. “SAM4CM16/8 Errata Revision A (MRL A) Parts”
Removed erratum on SUPC: LCD End of Frame Disable Does Not Work.
06-Oct-14
Added Section 50.5.2 “RSWDT Windowing Mode”, Section 50.7.1 “Unpredictable Software Behavior When Entering
Sleep Mode”, Section 50.8.1 “CORE 1 Systick Counter Erratic Behavior” and Section 50.9.1 “SRCB Bit in CKGR_PLLB
Register”.
Added Section 51. “SAM4CM16/8 Errata Revision B (MRL B) Parts”.
Added Section 52. “SAM4CM32 Errata Revision A (MRL A) Parts”.
Table 55-4.
SAM4CM Datasheet Rev. 11203B Revision History
Doc. Rev.
11203B
Changes
Removed preliminary status.
In Section “Features”, removed “...or using internal voltage regulator.” from Note (1).
In Figure 2-1 “SAM4CM Series 100-pin Block Diagram”, removed 100MHz from Cortex-M4 blocks.
Table 5-2 “Low-power Mode Configuration Summary”: Updated notes (4) and (5).
In Figure 8-6 “Execution View”, in Core 1 block, changed the incoming SRAM bus to ICode/DCode Bus .
Section 27. “Static Memory Controller (SMC)”
Section 27.1 “Description”: Removed reference to configurable 16-bit data bus in 3rd paragraph.
14-Apr-14
Table 27-1 “I/O Line Description”: Table contents modified.
Removed section ‘Multiplexed Signals’.
Section 27.2 “Embedded Characteristics”: Removed reference to 16-bit datas bus in 3rd bullet.
Section 27.15.4 “SMC MODE Register”: Removed bit 12 ‘DBW’.
Section 41. “Energy Metering Analog Front End (EMAFE)”
Figure 41-1 “Functional Block Diagram for Three-Phase EMAFE”, Figure 41-2 “Functional Block Diagram for Two-Phase
EMAFE”, Figure 41-3 “Typical Three-Phase Application Block Diagram” and Figure 41-4 “Typical Single-phase Application
Block Diagram”: modified all instances of VREF to VREF_AFE.
Continued on next page
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SAM4CM Datasheet Rev. 11203B Revision History (Continued)
Doc. Rev.
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Changes
Section 47. “SAM4CM Electrical Characteristics”
Table 47-1 “Absolute Maximum Ratings*”: removed junction temperature.
In Table 47-16 “LCD Voltage Regulator Characteristics”, Changed min and max values for VVDDLCD ‘Output voltage
accuracy’ parameter. Added new characteristic dVOUT/dVDDIN ‘VDDLCD variation with VDDIN’ with typ and max values.
In Table 47-17 “VDDLCD Voltage Selection at VDDIN = 3.6V”, all VDDLCD values updated.
In Table 47-18 “LCD Buffers Characteristics”, changed min, typ and max values for ZOUT ‘Buffer output impedance’.
Changed convergence value and max value for tr / tf ‘Rising or falling time’.
Table 47-21 “VDDIO Supply Monitor”: modified min and max values for parameter ACC
Table 47-26 “4/8/12 MHz RC Oscillators Characteristics”: Modified conditions for ACC4, ACC8 and ACC12. Modified max
values for ACC8 and ACC12.
In Table 47-31 “PLLA Characteristics”, modified tON ‘Startup time’. Added new tLOCK ‘Lock time’.
Table 47-41 “Programmable Voltage Reference Characteristics”: Modified ACC ‘reference voltage accuracy’ min and max
values and added conditions. Modified max value of TC ‘Temperature coefficient’.
Table 47-42 “Programmable Voltage Reference Selection Values”: all ADVREF values modified.
In Table 47-45 “Current or Voltage Measurement Channel Electrical Characteristics”, added condition ‘Gain = 1, VIND =
0.500 VPP’ with typ value for parameter SINADPEAK
14-Apr-14 Table 47-46 “EMAFE Precision Voltage Reference and Die Temperature Sensor Characteristics”: changed min/typ/max
values of parameter VREF_AFE0.
Table 47-47 “EMAFE VDDA LDO Regulator”: Updated min, typ and max values and modified units for parameters Static
Load Regulation and Static Line Regulation. Changed typ value for parameter Power Supply Rejection Ration for condition f
= 1 MHz.
Figure 45-18 “Measurement Setup for Configuration C and D”: added note below figure.
Table 47-52 “Typical Current Consumption Values for Backup Mode Configurations C and D”: modified ‘Conditions’ column
to VDDIO.
Removed section 46.5.17.2 ‘10-bit ADC with Averager’.
Table 47-57 “Test Setup 3 Current Consumption”: modified values for 128-bit Flash Access, Cache Enabled columns.
Table 46-61 “Wake-up Time versus Low-power Mode”: all consumption values modified except AES.
Removed section 46.7.6 ‘Low-power Mode Wake-up Time’.
Section 51. “Errata”
Added erratum on Flash Memory: “Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait
State”
Added erratum on EFC: “Erase Sector (ES) Command Cannot be Performed if a Subsector is Locked (ONLY in Flash sector
0)”
Table 55-5.
SAM4CM Datasheet Rev. 11203A 15-Oct-13 Revision History
Doc. Rev.
11203A
Changes
15-Oct-13 First issue
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1165
Table of Contents
1.
Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.
Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
5.
Power Supply and Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.
100-lead LQFP Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
100-lead LQFP Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System State at Power-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
19
21
21
22
26
26
Input/Output Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
General-Purpose I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMPx Pins: Anti-tamper Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTCOUT0 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shutdown (SHDN) Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Force Wake-up (FWUP) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ERASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
27
27
28
28
28
28
28
28
7.
Product Mapping and Peripheral Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1
8.2
9.
Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
External Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Real-time Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1
9.2
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Real-time Event Mapping List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10. System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.1
10.2
10.3
10.4
System Controller and Peripheral Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
46
47
47
11. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11.1
11.2
11.3
11.4
i
Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB/AHB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Signal Multiplexing on I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
48
50
51
51
12. ARM Cortex-M4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.12
12.13
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Cortex-M4 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Cortex-M4 Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
System Control Block (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
System Timer (SysTick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
13. Debug and Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Associated Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cross Triggering Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
308
308
308
310
310
311
311
14. Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
14.1
14.2
14.3
14.4
14.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware and Software Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
317
317
317
317
318
15. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
15.1
15.2
15.3
15.4
15.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
321
321
321
322
329
16. Real-time Timer (RTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
16.1
16.2
16.3
16.4
16.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
334
334
334
335
337
17. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
17.1
17.2
17.3
17.4
17.5
17.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
342
342
342
343
343
352
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
ii
18. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
18.1
18.2
18.3
18.4
18.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
374
374
375
376
378
19. Reinforced Safety Watchdog Timer (RSWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
19.1
19.2
19.3
19.4
19.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reinforced Safety Watchdog Timer (RSWDT) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .
383
383
384
384
386
20. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
20.1
20.2
20.3
20.4
20.5
20.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
391
391
392
393
403
405
21. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
21.1
21.2
21.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
General Purpose Backup Registers (GPBR) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
22. Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
22.1
22.2
22.3
22.4
22.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Enhanced Embedded Flash Controller (EEFC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
23. Fast Flash Programming Interface (FFPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
23.1
23.2
23.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Parallel Fast Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
24. Cortex-M Cache Controller (CMCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
24.1
24.2
24.3
24.4
24.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cortex-M Cache Controller (CMCC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
453
453
453
454
455
25. Interprocessor Communication (IPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
25.1
25.2
25.3
25.4
25.5
iii
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inter-processor Communication (IPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
466
466
467
467
469
26. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Bus Granting Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
No Default Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Last Access Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fixed Default Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Bus Matrix (MATRIX) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
477
477
481
481
481
481
482
484
485
27. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
27.1
27.2
27.3
27.4
27.5
27.6
27.7
27.8
27.9
27.10
27.11
27.12
27.13
27.14
27.15
27.16
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connection to External Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Read and Write Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scrambling/Unscrambling Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slow Clock Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
495
495
496
496
496
497
497
501
503
511
511
515
519
525
527
530
28. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
28.1
28.2
28.3
28.4
28.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral DMA Controller (PDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
541
541
542
543
545
29. Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
29.1
29.2
29.3
29.4
29.5
29.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Slow Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Main Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Divider and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
30. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
30.1
30.2
30.3
30.4
30.5
30.6
30.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SysTick Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
565
565
566
567
567
567
567
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
iv
30.8
30.9
30.10
30.11
30.12
30.13
30.14
30.15
30.16
30.17
30.18
Free-Running Processor Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Programmable Clock Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Main Processor Fast Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Main Processor Startup from Embedded Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Coprocessor Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Main Clock Failure Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
32.768 kHz Crystal Oscillator Frequency Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Clock Switching Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
Power Management Controller (PMC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
31. Chip Identifier (CHIPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
31.1
31.2
31.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
32. Parallel Input/Output Controller (PIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
32.1
32.2
32.3
32.4
32.5
32.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
33. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
33.1
33.2
33.3
33.4
33.5
33.6
33.7
33.8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
678
678
679
679
680
680
681
694
34. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
34.1
34.2
34.3
34.4
34.5
34.6
34.7
34.8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-wire Interface (TWI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
710
710
711
711
711
712
712
739
35. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . 756
35.1
35.2
35.3
35.4
35.5
35.6
v
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . . . . . . . . . . . . . . . . . .
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
756
756
756
757
757
766
36. Universal Synchronous Asynchronous Receiver Transceiver (USART) . . . . . . . . . 778
36.1
36.2
36.3
36.4
36.5
36.6
36.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface . . . . . . . . .
778
778
779
779
780
781
810
37. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
37.1
37.2
37.3
37.4
37.5
37.6
37.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Counter (TC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
846
846
847
848
848
849
868
38. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
38.1
38.2
38.3
38.4
38.5
38.6
38.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Width Modulation Controller (PWM) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
897
897
898
898
898
899
907
39. Segment Liquid Crystal Display Controller (SLCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
39.1
39.2
39.3
39.4
39.5
39.6
39.7
39.8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Waveform Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Segment LCD Controller (SLCDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
40. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
40.1
40.2
40.3
40.4
40.5
40.6
40.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
954
954
955
955
956
957
969
41. Energy Metering Analog Front End (EMAFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
41.1
41.2
41.3
41.4
41.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
993
993
994
996
997
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
vi
41.6
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
42. Advanced Encryption Standard (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
42.1
42.2
42.3
42.4
42.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Encryption Standard (AES) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1000
1000
1000
1001
1013
43. Integrity Check Monitor (ICM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034
43.1
43.2
43.3
43.4
43.5
43.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrity Check Monitor (ICM) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1034
1035
1035
1036
1036
1049
44. Classical Public Key Cryptography Controller (CPKCC) . . . . . . . . . . . . . . . . . . . . . . . 1063
44.1
44.2
44.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
45. True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
45.1
45.2
45.3
45.4
45.5
45.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
True Random Number Generator (TRNG) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1065
1065
1065
1065
1066
1067
46. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
46.1
46.2
46.3
46.4
46.5
46.6
46.7
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Parameters Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Analog Peripherals Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1074
1075
1077
1079
1092
1110
1112
47. Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
47.1
47.2
47.3
100-lead LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Packaging Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
48. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
49. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
50. SAM4CM16/8 Errata Revision A (MRL A) Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
50.1
50.2
50.3
50.4
vii
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Input Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
1134
1134
1134
1135
50.5
50.6
50.7
50.8
50.9
50.10
Watchdog (WDT) / Reinforced Safety Watchdog (RSWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
Wait For Interrupt (WFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
Power Supply and Power Control / Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
EMAFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
51. SAM4CM16/8/4 Errata Revision B (MRL B) Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
51.1
51.2
51.3
51.4
51.5
51.6
51.7
51.8
51.9
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
Parallel Input Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
Watchdog (WDT) / Reinforced Safety Watchdog (RSWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139
Wait For Interrupt (WFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
Power Supply and Power Control / Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
EMAFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1140
52. SAM4CM16/8/4 Errata Revision C (MRL C) Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
52.1
52.2
52.3
52.4
52.5
52.6
52.7
52.8
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
Parallel Input Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Watchdog (WDT) / Reinforced Safety Watchdog (RSWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Wait For Interrupt (WFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
Power Supply and Power Control / Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143
53. SAM4CM32 Errata Revision A (MRL A) Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
53.1
53.2
53.3
53.4
53.5
53.6
53.7
53.8
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
Parallel Input Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
Reinforced Safety Watchdog (RSWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Wait For Interrupt (WFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145
Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
EMAFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146
54. SAM4CM32 Errata Revision B (MRL B) Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
54.1
54.2
54.3
54.4
54.5
54.6
54.7
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Parallel Input Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
Reinforced Safety Watchdog (RSWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Wait For Interrupt (WFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
55. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150
SAM4CM Series [DATASHEET]
Atmel-11203E-ATARM-SAM4CM32-SAM4CM16-SAM4CM8-SAM4CM4-Datasheet_24-Oct-16
viii
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