ATSAM4LS2AA-AU

Summary Atmel's SAM4L series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M4 RISC processor running at frequencies up to 48MHz. The SAM4L series embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active current consumption down to 90μA/MHz. The device allows a wide range of options between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. The WAIT and RETENTION modes provide full logic and RAM retention, associated with fast wake-up capability (0) 1. Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY indicates the state of THR. Software or the Peripheral DMA Controller must write the data byte to THR. 2. Transmit this data byte 3. Decrement NBYTES 4. If (NBYTES==0) and STOP=1, transmit STOP condition Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, SADR+W, STOP. TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER). TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. The end of a command is marked when the TWIM sets the SR.CCOMP bit. See Figure 27-6 and Figure 27-7. Figure 27-6. Master Write with One Data Byte TWD S DADR W A DATA A P SR.IDLE TXRDY Write THR (DATA) NBYTES set to 1 STOP sent automatically (ACK received and NBYTES=0) 713 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 27-7. Master Write with Multiple Data Bytes TWD S DADR W A DATAn A DATAn+5 A DATAn+m A P SR.IDLE TXRDY Write THR (DATAn) NBYTES set to n 27.8.4 Write THR (DATAn+1) Write THR (DATAn+m) Last data sent STOP sent automatically (ACK received and NBYTES=0) Master Receiver Mode A START condition is transmitted and master receiver mode is initiated when the bus is free and CMDR has been written with START=1 and READ=1. START and SADR+R will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in the Status Register if no slave acknowledges the address. After the address phase, the following is repeated: while (NBYTES>0) 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or the Peripheral DMA Controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition. Writing CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, DADR+R, STOP The TWI transfers require the master to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. All data bytes except the last are acknowledged by the master. Not acknowledging the last byte informs the slave that the transfer is finished. RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel. 714 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 27-8. Master Read with One Data Byte TWD S DADR R A DATA N P SR.IDLE RXRDY Write START & STOP bit NBYTES set to 1 Read RHR Figure 27-9. Master Read with Multiple Data Bytes TWD S DADR R A DATAn A DATAn+1 DATAn+m-1 A DATAn+m N P SR.IDLE RXRDY Write START + STOP bit NBYTES set to m Read RHR DATAn Read RHR DATAn+m-2 Read RHR DATAn+m-1 Read RHR DATAn+m Send STOP When NBYTES=0 27.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 27.8.5.1 Data Transmit with the Peripheral DMA Controller 1. 2. 3. 4. 5. 27.8.5.2 Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). Configure the TWIM (ADR, NBYTES, etc.). Start the transfer by enabling the Peripheral DMA Controller to transmit. Wait for the Peripheral DMA Controller end-of-transmit flag. Disable the Peripheral DMA Controller. Data Receive with the Peripheral DMA Controller 1. 2. 3. 4. 5. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.). Configure the TWIM (ADR, NBYTES, etc.). Start the transfer by enabling the Peripheral DMA Controller to receive. Wait for the Peripheral DMA Controller end-of-receive flag. Disable the Peripheral DMA Controller. 715 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.8.6 Multi-master Mode More than one master may access the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master who lost arbitration may reinitiate the data transfer. Arbitration is illustrated in Figure 27-11. If the user starts a transfer and if the bus is busy, the TWIM automatically waits for a STOP condition on the bus before initiating the transfer (see Figure 27-10). Note: The state of the bus (busy or free) is not indicated in the user interface. Figure 27-10. User Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master TWD DATA sent by a master DATA sent by the TWI Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is kept Bus is considered as free Transfer is initiated 716 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 27-11. Arbitration Cases TWCK TWD TWCK Data from a Master S 1 0 0 1 1 Data from TWI S 1 0 TWD S 1 0 0 1 P Arbitration is lost TWI stops sending data Data from the master 1 1 P Arbitration is lost S 1 0 S 1 0 0 1 1 S 1 0 1 1 The master stops sending data 0 1 Data from the TWI ARBLST Bus is busy Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) 27.8.7 Bus is free Transfer is stopped Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Combined Transfers CMDR and NCMDR may be used to generate longer sequences of connected transfers, since generation of START and/or STOP conditions is programmable on a per-command basis. Writing NCMDR with START=1 when the previous transfer was written with STOP=0 will cause a REPEATED START on the bus. The ability to generate such connected transfers allows arbitrary transfer lengths, since it is legal to write CMDR with both START=0 and STOP=0. If this is done in master receiver mode, the CMDR.ACKLAST bit must also be controlled. As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see Section 27.8.5 27.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1. 2. 3. 4. 5. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. Wait until SR.TXRDY==1, then write third data byte to transfer to THR. 717 42023H–SAM–11/2016 ATSAM4L8/L4/L2 6. Wait until SR.TXRDY==1, then write fourth data byte to transfer to THR. 27.8.7.2 Read Followed by Read Consider the following transfer: START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.RXRDY==1, then read second data byte received from RHR. 5. Wait until SR.RXRDY==1, then read third data byte received from RHR. 6. Wait until SR.RXRDY==1, then read fourth data byte received from RHR. If combining several transfers, without any STOP or REPEATED START between them, remember to write a one to the ACKLAST bit in CMDR to keep from ending each of the partial transfers with a NACK. 27.8.7.3 Write Followed by Read Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. Figure 27-12. Combining a Write and Read Transfer THR DATA0 DATA1 RHR TWD DATA2 S DADR W A DATA0 A DATA1 NA Sr DADR R A DATA2 A DATA3 DATA3 A P SR.IDLE 1 TXRDY RXRDY To generate this transfer: 1. 2. 3. 4. 5. 6. 27.8.7.4 Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. Wait until SR.RXRDY==1, then read first data byte received from RHR. Wait until SR.RXRDY==1, then read second data byte received from RHR. Read Followed by Write Consider the following transfer: START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+W, DATA+A, DATA+A, STOP. 718 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 27-13. Combining a Read and Write Transfer THR DATA2 RHR TWD DATA0 DATA3 DATA3 1 S SADR R A A DATA0 DATA1 A Sr DADR W A DATA2 A DATA3 NA SR.IDLE P 2 TXRDY Read TWI_RHR RXRDY To generate this transfer: 1. 2. 3. 4. 5. 6. 27.8.8 Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. Wait until SR.RXRDY==1, then read first data byte received from RHR. Wait until SR.RXRDY==1, then read second data byte received from RHR. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. Ten Bit Addressing Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of CMDR.SADR must be written appropriately. In Figure 27-14 and Figure 27-15, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 27.8.8.1 Master Transmitter To perform a master transmitter transfer: 1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the desired address and NBYTES value. Figure 27-14. A Write Transfer with 10-bit Addressing 1 S 27.8.8.2 1 1 1 0 X SLAVE ADDRESS 1st 7 bits X 0 RW A1 SLAVE ADDRESS 2nd byte A2 DATA A DATA AA P Master Receiver When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be controlled. CMDR.REPSAME must be written to one when the address phase of the transfer should consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard specifies that such addressing is required when addressing a slave for reads using 10-bit addressing. To perform a master receiver transfer: 719 42023H–SAM–11/2016 ATSAM4L8/L4/L2 1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0, NBYTES=0 and the desired address. 2. Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the desired address and NBYTES value. Figure 27-15. A Read Transfer with 10-bit Addressing 1 S 27.8.9 1 1 1 0 X X SLAVE ADDRESS 1st 7 bits 0 RW A1 1 SLAVE ADDRESS 2nd byte A2 Sr 1 1 1 0 X SLAVE ADDRESS 1st 7 bits X 1 RW A3 DATA A DATA A P SMBus Mode SMBus mode is enabled and disabled by writing to the SMEN and SMDIS bits in CR. SMBus mode operation is similar to I²C operation with the following exceptions: • Only 7-bit addressing can be used. • The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be written into SMBTR. • Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). • A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. 27.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct. In master transmitter mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NACK value. The DNAK bit in SR reflects the state of the last received ACK/NACK value. Some slaves may not be able to check the received PEC in time to return a NACK if an error occurred. In this case, the slave should always return an ACK after the PEC byte, and some other mechanism must be implemented to verify that the transmission was received correctly. In master receiver mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and SR.PECERR is set. In master receiver mode, the PEC byte is always followed by a NACK transmitted by the master, since it is the last byte in the transfer. The PEC byte is automatically inserted in a master transmitter transmission if PEC is enabled when NBYTES reaches zero. The PEC byte is identified in a master receiver transmission if PEC is enabled when NBYTES reaches zero. NBYTES must therefore be written with the total number of data bytes in the transmission, including the PEC byte. 720 42023H–SAM–11/2016 ATSAM4L8/L4/L2 In combined transfers, the PECEN bit should only be written to one in the last of the combined transfers. Consider the following transfer: S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P This transfer is generated by writing two commands to the command registers. The first command is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and PECEN=1. Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current byte. No PEC byte will be sent in this case. 27.8.9.2 Timeouts The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is set. 27.8.10 Identifying Bus Events This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 27-5. Bus Events Event Effect Master transmitter has sent a data byte SR.THR is cleared. Master receiver has received a data byte SR.RHR is set. Start+Sadr sent, no ack received from slave SR.ANAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Data byte sent to slave, no ack received from slave SR.DNAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Arbitration lost SR.ARBLST is set. SR.CCOMP not set. CMDR.VALID remains set. TWCK and TWD immediately released to a pulled-up state. SMBus timeout received SR.SMBTOUT is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. 721 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 27-5. Bus Events Event Effect Master transmitter receives SMBus PEC Error SR.DNAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. Master receiver discovers SMBus PEC Error SR.PECERR is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. CR.STOP is written by user SR.STOP is set. SR.CCOMP set. CMDR.VALID remains set. STOP transmitted on bus after current byte transfer has finished. 722 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9 User Interface Table 27-6. Note: TWIM Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Write-only 0x00000000 0x04 Clock Waveform Generator Register CWGR Read/Write 0x00000000 0x08 SMBus Timing Register SMBTR Read/Write 0x00000000 0x0C Command Register CMDR Read/Write 0x00000000 0x10 Next Command Register NCMDR Read/Write 0x00000000 0x14 Receive Holding Register RHR Read-only 0x00000000 0x18 Transmit Holding Register THR Write-only 0x00000000 0x1C Status Register SR Read-only 0x00000002 0x20 Interrupt Enable Register IER Write-only 0x00000000 0x24 Interrupt Disable Register IDR Write-only 0x00000000 0x28 Interrupt Mask Register IMR Read-only 0x00000000 0x2C Status Clear Register SCR Write-only 0x00000000 0x30 Parameter Register PR Read-only -(1) 0x34 Version Register VR Read-only -(1) 0x38 HS-mode Clock Waveform Generator HSCWGR Read/Write 0x00000000 0x3C Slew Rate Register SRR Read/Write 0x00000000 0x40 HS-mode Slew Rate Register HSSRR Read/Write 0x00000000 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter. 723 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - STOP 7 6 5 4 3 2 1 0 SWRST - SMDIS SMEN - - MDIS MEN • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully sent. Writing a zero to this bit has no effect. • SWRST: Software Reset If the TWIM master interface is enabled, writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly violating the bus semantics. If the TWIM master interface is not enabled, it must first be enabled before writing a one to this bit. Writing a zero to this bit has no effect. • SMDIS: SMBus Disable Writing a one to this bit disables SMBus mode. Writing a zero to this bit has no effect. • SMEN: SMBus Enable Writing a one to this bit enables SMBus mode. Writing a zero to this bit has no effect. • MDIS: Master Disable Writing a one to this bit disables the master interface. Writing a zero to this bit has no effect. • MEN: Master Enable Writing a one to this bit enables the master interface. Writing a zero to this bit has no effect. 724 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.2 Name: Clock Waveform Generator Register CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 - 23 29 28 27 26 EXP 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock. Counters are prescaled according to the following formula f CLK_TWIM f PRESCALER = ------------------------( EXP + 1 ) 2 • DATA: Data Setup and Hold Cycles Clock cycles for data setup and hold count. Prescaled by CWGR.EXP. Used to time THD_DAT, TSU_DAT. • STASTO: START and STOP Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THD_STA, TSU_STA, TSU_STO • HIGH: Clock High Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THIGH. • LOW: Clock Low Cycles Clock cycles in clock low count. Prescaled by CWGR.EXP. Used to time TLOW, TBUF. 725 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.3 Name: SMBus Timing Register SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 THMAX 15 14 13 12 TLOWM 7 6 5 4 TLOWS • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR. Counters are prescaled according to the following formula f CLKTWIM f prescaled, SMBus = -----------------------( EXP + 1 ) 2 • THMAX: Clock High Maximum Cycles Clock cycles in clock high maximum count. Prescaled by SMBTR.EXP. Used for bus free detection. Used to time THIGH:MAX. NOTE: Uses the prescaler specified by CWGR, NOT the prescaler specified by SMBTR. • TLOWM: Master Clock Stretch Maximum Cycles Clock cycles in master maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:MEXT • TLOWS: Slave Clock Stretch Maximum Cycles Clock cycles in slave maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:SEXT. 726 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.4 Name: Command Register CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 - 23 29 28 HSMCODE 22 21 20 27 26 25 24 - HS ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ • HSMCODE: HS-mode Master Code 3-bit code to be prefixed with 0b00001 to form a unique 8-bit HS-mode master code (0000 1XXX). • HS: HS-mode 0: Causes the TWIM not to initiate HS-mode transfer. 1: Causes the TWIM to initiate HS-mode transfer. • ACKLAST: ACK Last Master RX Byte 0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of ending a master receiver transfer. 1: Causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for performing linked transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is needed when more than 255 bytes are to be received in one single transmission. • PECEN: Packet Error Checking Enable 0: Causes the transfer not to use PEC byte verification. The PEC LFSR is still updated for every bit transmitted or received. Must be used if SMBus mode is disabled. 1: Causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if master receiver) will be performed. • NBYTES: Number of Data Bytes in Transfer The number of data bytes in the transfer. After the specified number of bytes have been transferred, a STOP condition is transmitted if CMDR.STOP is one. In SMBus mode, if PEC is used, NBYTES includes the PEC byte, i.e. there are NBYTES-1 data bytes and a PEC byte. • VALID: CMDR Valid 0: Indicates that CMDR does not contain a valid command. 1: Indicates that CMDR contains a valid command. This bit is cleared when the command is finished. • STOP: Send STOP Condition 0: Do not transmit a STOP condition after the data bytes have been transmitted. 1: Transmit a STOP condition after the data bytes have been transmitted. • START: Send START Condition 0: The transfer in CMDR should not commence with a START or REPEATED START condition. 727 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • • • • 1: The transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free when the command is executed, a START condition is used. If the bus is busy, a REPEATED START is used. REPSAME: Transfer is to Same Address as Previous Address Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode. Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. TENBIT: Ten Bit Addressing Mode 0: Use 7-bit addressing mode. 1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode. SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used. READ: Transfer Direction 0: Allow the master to transmit data. 1: Allow the master to receive data. 728 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.5 Name: Next Command Register NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 - 29 28 HSMCODE 23 22 21 20 27 26 25 24 - HS ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR. If the VALID bit in CMDR is cleared when NCMDR is written, the content is copied immediately. 729 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.6 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus. 730 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.7 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here. 731 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK MENB 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY • HSMCACK: ACK in HS-mode Master Code Phase Received This bit is one when an ACK is erroneously received during a HS-mode master code phase. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled. • STOP: Stop Request Accepted This bit is one when a STOP request caused by writing a one to CR.STOP has been accepted, and transfer has stopped. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • PECERR: PEC Error This bit is one when a SMBus PEC error occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • TOUT: Timeout This bit is one when a SMBus timeout occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • ARBLST: Arbitration Lost This bit is one when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority transmission in progress by a different master. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • DNAK: NAK in Data Phase Received This bit is one when no ACK was received form slave during data transmission. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • ANAK: NAK in Address Phase Received This bit is one when no ACK was received from slave during address phase This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • BUSFREE: Two-wire Bus is Free This bit is one when activity has completed on the two-wire bus. Otherwise, this bit is cleared. 732 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • IDLE: Master Interface is Idle This bit is one when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • CRDY: Ready for More Commands This bit is one when CMDR and/or NCMDR is ready to receive one or more commands. This bit is cleared when this is no longer true. • TXRDY: THR Data Ready This bit is one when THR is ready for one or more data bytes. This bit is cleared when this is no longer true (i.e. THR is full or transmission has stopped). • RXRDY: RHR Data Ready This bit is one when RX data are ready to be read from RHR. This bit is cleared when this is no longer true. 733 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR 734 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR 735 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 736 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.12 Name: Status Clear Register SCR Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - HSMCACK - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT - ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - - - CCOMP - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 737 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.13 Name: Parameter Register PR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - HS • HS: HS-mode 0: High-speed-mode is not supported. 1: High-speed-mode is supported. 738 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.14 Name: Version Register VR Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 739 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.15 Name: HS-mode Clock Waveform Generator Register HSCWGR Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 - 29 28 27 26 EXP 23 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW This register is identical to CWGR. It is used to generate the TWCK signal during HS-mode transfer. 740 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.16 Name: Slew Rate Register SRR Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 - - 23 22 21 - - 15 28 27 26 - - 20 19 18 - - - 14 13 12 11 10 - - - - - - 7 6 5 4 3 2 - - - - - FILTER 25 24 CLSLEW 17 16 CLDRIVEL 9 8 DASLEW 1 0 DADRIVEL • FILTER: Input Spike Filter Control FILTER Value Function 0 Reserved 1 Reserved 2 Standard- or Fast-mode 3 Fast-mode plus • CLSLEW: Clock Slew Limit Selects the slew limit of the TWCK output buffer in F/S-mode. • CLDRIVEL: Clock Drive Strength LOW Selects the pull-down drive strength of the TWCK output buffer in F/S-mode. • DASLEW: Data Slew Limit Selects the slew limit of the TWD output buffer in F/S-mode. • DADRIVEL: Data Drive Strength LOW Selects the pull-down drive strength of the TWD output buffer in F/S-mode. Refer to Section 42. ”Electrical Characteristics” on page 1121 for appropriates values of these register fields. 741 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.9.17 Name: HS-mode Slew Rate Register HSSRR Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 - - 23 22 - - 15 14 13 12 11 10 - - - - - - 7 6 5 4 3 2 FILTER 21 20 CLDRIVEH - 27 26 - - 19 18 - 25 24 CLSLEW 17 16 CLDRIVEL 9 8 DASLEW 1 0 DADRIVEL • FILTER: Input Spike Filter Control 0: Reserved 1: HS-mode 2: Reserved 3: Reserved • CLSLEW: Clock Slew Limit Selects the slew limit of the TWCK output buffer in HS-mode. • CLDRIVEH: Clock Drive Strength HIGH Selects the pull-up drive strength of the TWCK output buffer In HS-mode. • CLDRIVEL: Clock Drive Strength LOW Selects the pull-down drive strength of the TWCK output buffer in HS-mode. • DASLEW: Data Slew Limit Selects the slew limit of the TWD output buffer in HS-mode. • DADRIVEL: Data Drive Strength LOW Selects the pull-down drive strength of the TWD output buffer in HS-mode. Refer to Section 42. ”Electrical Characteristics” on page 1121 for appropriates values of these register fields. 742 42023H–SAM–11/2016 ATSAM4L8/L4/L2 27.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 109 for details. Table 27-7. Module Clock Name Module Name Clock Name Description TWIM0 CLK_TWIM0 Clock for the TWIM0 bus interface TWIM1 CLK_TWIM1 Clock for the TWIM1 bus interface TWIM2 CLK_TWIM2 Clock for the TWIM2 bus interface TWIM3 CLK_TWIM3 Clock for the TWIM3 bus interface Note : TWI2 and TWI3 are master only. TWI0 and TWI1 are master and slave Table 27-8. Register Reset Values Register Reset Value VERSION 0x00000120 PARAMETER 0x00000001 743 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28. Two-wire Slave Interface (TWIS) Rev: 1.4.0.1 28.1 Features • Compatible with I²C standard • • • • • • 28.2 – Transfer speeds up to 3.4 Mbit/s – 7 and 10-bit and General Call addressing Compatible with SMBus standard – Hardware Packet Error Checking (CRC) generation and verification with ACK response – 25 ms clock low timeout delay – 25 ms slave cumulative clock low extend time Compatible with PMBus DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer 32-bit Peripheral Bus interface for configuration of the interface Overview The Atmel Two-wire Slave Interface (TWIS) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 3.4 Mbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus, I²C, or SMBus-compatible master. The TWIS is always a bus slave and can transfer sequential or single bytes. Below, Table 28-1 lists the compatibility level of the Atmel Two-wire Slave Interface and a full I²C compatible device. Table 28-1. Atmel TWIS Compatibility with I²C Standard I²C Standard Atmel TWIS Standard-mode (100 kbit/s) Supported Fast-mode (400 kbit/s) Supported High-speed-mode (3.4 Mbit/s) Supported 7 or 10 bits Slave Addressing Supported START BYTE(1) Not Supported Repeated Start (Sr) Condition Supported ACK and NAK Management Supported Slope control and input filtering (Fast mode) Supported Clock stretching Supported Note: 1. START + b000000001 + Ack + Sr 744 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Below, Table 28-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 28-2. 28.3 SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Packet Error Checking Supported List of Abbreviations Table 28-3. 28.4 Atmel TWIS Compatibility with SMBus Standard Abbreviations Abbreviation Description TWI Two-wire Interface A Acknowledge NA Non Acknowledge P Stop S Start Sr Repeated Start SADR Slave Address ADR Any address except SADR R Read W Write Block Diagram Figure 28-1. Block Diagram Peripheral Bus Bridge TWCK I/O Controller TWD Two-wire Interface Power Manager Interrupt Controller CLK_TWIS TWI Interrupt 745 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.5 Application Block Diagram Figure 28-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI serial EEPROM Slave 1 I²C RTC I²C LCD controller I²C temp. sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 28.6 I/O Lines Description Table 28-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output 28.7 Type Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 28.7.1 I/O Lines TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 28-5 on page 748). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with I/O Controller lines. To enable the TWIS, the user must perform the following steps: • Program the I/O Controller to: – Dedicate TWD, TWCKas peripheral lines. – Define TWD, TWCKas open-drain. 28.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop functioning and resume operation after the system wakes up from sleep mode. The TWIS is able to wake the system from sleep mode upon address match, see Section 28.8.9 on page 755. 746 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. It is recommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state. 28.7.4 DMA The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting up the TWIS. 28.7.5 Interrupts The TWIS interrupt request lines are connected to the NVIC. Using the TWIS interrupts requires the NVIC to be programmed first. 28.7.6 28.8 28.8.1 Debug Operation When an external debugger forces the CPU into debug mode, the TWIS continues normal operation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 28-4 on page 747). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 28-3). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 28-3. START and STOP Conditions TWD TWCK Start Stop Figure 28-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 747 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.8.2 Operation The TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 28-5. Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 28.8.3 High-speed-mode After reset and initialization, the TWIS is either in Standard-mode, Fast-mode, or Fast-mode Plus (collectively referred to as the F/S-mode). The TWIS automatically enters High-speedmode (HS-mode) after it detects the following conditions (all of which are in F/S-mode) on the bus: 1. START condition (S) 2. 8-bit master code (0000 1XXX) 3. Not-acknowledge bit (NA) After the TWIS has detected the above conditions and before the commencement of HS-mode transfer, it does the following: 1. Adapts the TWD and TWCK input filters to the spike suppression requirement in HSmode. 2. Adapts the TWD output stage to the slope control requirement in HS-mode. The TWIS automatically returns to F/S-mode after it detects a STOP condition on the bus. With regard to the slope control of the TWD output, the user can control the fall times of the TWD output in F/S- and HS-mode by writing to the Data Drive Strength LOW (DADRIVEL) and Data Slew Limit (DASLEW) fields in the Slew Rate Register (SRR) and HS-mode Slew Rate Register (HSSRR), respectively. Refer to Section 42. ”Electrical Characteristics” on page 1121 for appropriate values of these register fields. Note that the fall times of the TWD output are also controlled by the corresponding register fields in the Two-wire Master Interface (TWIM) module. In order to correctly control the slew rate of the TWD output, the user must either 748 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • Write to the relevant register fields in the TWIS with appropriate values and leave those in TWIM as zeros, or vice versa; or • Write to the relevant register fields in both the TWIM and the TWIS with the same values. 28.8.3.1 Bus Timing The Timing Register (TR) is used to control the timing of bus signals driven by the TWIS. TR describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling can be selected through TR.EXP. f CLK_TWIS f PRESCALED = -----------------------( EXP + 1 ) 2 TR has the following fields: TLOWS: Prescaled clock cycles used to time SMBUS timeout TLOW:SEXT. TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT. SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT. EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. When the TWIS is in HS-mode, the data hold count is set by writing to the HDDAT field in the HS-mode Timing Register (HSTR). Figure 28-6. Bus Timing Diagram t HIGH t LOW S t t LOW t HD:STA SU:DAT t HD:DAT t t SU:DAT t SU:STA SU:STO P Sr 749 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.8.3.2 Setting Up and Performing a Transfer Operation of the TWIS is mainly controlled by the Control Register (CR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by writing to the Timing Register (TR) and, if HS-mode transfer is supported, the HS-mode Timing Register (HSTR). 2. If the Peripheral DMA Controller is to be used for the transfers, it must be set up. 3. The Control Register (CR) must be configured with information such as the slave address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and which addresses to match. The interrupt system can be set up to generate interrupt request on specific events or error conditions, for example when a byte has been received. The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to zero. NBYTES is updated by hardware, so in order to avoid hazards, software updates of NBYTES can only be done through writes to the NBYTES register. 28.8.3.3 Address Matching The TWIS can be set up to match several different addresses. More than one address match may be enabled simultaneously, allowing the TWIS to be assigned to several addresses. The address matching phase is initiated after a START or REPEATED START condition. When the TWIS receives an address that generates an address match, an ACK is automatically returned to the master. In I²C mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The General Call address is checked for address match if CR.GCMATCH is one. In SMBus mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The Alert Response Address is checked for address match if CR.SMAL is one. • The Default Address is checked for address match if CR.SMDA is one. • The Host Header Address is checked for address match if CR.SMHH is one. 28.8.3.4 Clock Stretching Any slave or bus master taking part in a transfer may extend the TWCK low period at any time. The TWIS may extend the TWCK low period after each byte transfer if CR.STREN is one and: • Module is in slave transmitter mode, data should be transmitted, but THR is empty, or • Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but the Receive Holding Register (RHR) is full, or • Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains stretched until all address match bits in the Status Register (SR) have been cleared. If CR.STREN is zero and: • Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit the value present in THR (the last transmitted byte or reset value), and set SR.URUN. 750 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but RHR is full: Discard the received byte and set SR.ORUN. 28.8.3.5 Bus Errors If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and the TWIS waits for a new START condition. 28.8.4 Slave Transmitter Mode If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it will enter slave transmitter mode and set the SR.TRA bit (note that SR.TRA is set one CLK_TWIS cycle after the relevant address match bit in the same register is set). After the address phase, the following actions are performed: 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to transmit. This is necessary in order to know when to transmit the PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Byte to transmit depends on I²C/SMBus mode and CR.PEC: – If in I²C mode or CR.PEC is zero or NBYTES is non-zero: The TWIS waits until THR contains a valid data byte, possibly stretching the low period of TWCK. After THR contains a valid data byte, the data byte is transferred to a shifter, and then SR.TXRDY is changed to one because the THR is empty again. – SMBus mode and CR.PEC is one: If NBYTES is zero, the generated PEC byte is automatically transmitted instead of a data byte from THR. TWCK will not be stretched by the TWIS. 3. The data byte in the shifter is transmitted. 4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transmitted, the master transmits an ACK (Acknowledge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be HIGH (see Figure 28-9). The NAK indicates that the transfer is finished, and the TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, the SR.NAK bit remains LOW. The ACK indicates that more data should be transmitted, jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer Finished (SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be LOW (see Figure 28-9). Also note that in the event that SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to ensure correct TWIS behavior. 6. If STOP is received, SR.TCOMP and SR.STO will be set. 7. If REPEATED START is received, SR.REP will be set. The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. The slave polls the data line during this clock pulse and sets the NAK bit in SR if the master does not acknowledge the data byte. A NAK means that the master does not wish to receive additional data bytes. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER). SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. 751 42023H–SAM–11/2016 ATSAM4L8/L4/L2 The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one. See Figure 28-7 and Figure 28-8. Figure 28-7. Slave Transmitter with One Data Byte S TWD DADR R A DATA N P TCOMP TXRDY STOP sent by master Write THR (DATA) NBYTES set to 1 Figure 28-8. Slave Transmitter with Multiple Data Bytes TWD S DADR R A DATA n A DATA n+5 A DATA n+m N P TCOMP TXRDY STOP sent by master Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent Figure 28-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF TWD DATA (LSB) N P TWCK SR.NAK SR.BTF t1 t1 t1: (CLK_TWIS period) x 2 28.8.5 Slave Receiver Mode If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one CLK_TWIS cycle after the relevant address match bit in the same register is set). After the address phase, the following is repeated: 752 42023H–SAM–11/2016 ATSAM4L8/L4/L2 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to receive. This is necessary in order to know which of the received bytes is the PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Receive a byte. Set SR.BTF when done. 3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is used. 4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordinary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC is enabled and the last byte received was a PEC byte (indicated by NBYTES equal to zero), The TWIS will automatically return an ACK if the PEC value was correct, otherwise a NAK will be returned. 5. If STOP is received, SR.TCOMP will be set. 6. If REPEATED START is received, SR.REP will be set. The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 28-10. Slave Receiver with One Data Byte TWD S DADR W A DATA A P TCOMP RXRDY Read RHR Figure 28-11. Slave Receiver with Multiple Data Bytes TWD S DADR W A DATA n A DATA (n+1) A DAT A (n+m)-1 A DATA (n+m) A P TCOMP RXRDY Read RHR DATA n 28.8.6 Read RHR DATA (n+1) Read RHR DAT A (n+m)-1 Read RHR DATA (n+m) Interactive ACKing Received Data Bytes When implementing a register interface over TWI, it may sometimes be necessary or just useful to report reads and writes to invalid register addresses by sending a NAK to the host. To be able to do this, one must first receive the register address from the TWI bus, and then tell the TWIS 753 42023H–SAM–11/2016 ATSAM4L8/L4/L2 whether to ACK or NAK it. In normal operation of the TWIS, this is not possible because the controller will automatically ACK the byte at about the same time as the RXRDY bit changes from zero to one. Writing a one to the Stretch on Data Byte Received bit (CR.SODR) will stretch the clock allowing the user to update CR.ACK bit before returning the desired value. After the last bit in the data byte is received, the TWI bus clock is stretched, the received data byte is transferred to the RHR register, and SR.BTF is set. At this time, the user can examine the received byte and write the desired ACK or NACK value to CR.ACK. When the user clears SR.BTF, the desired ACK value is transferred on the TWI bus. This makes it possible to look at the byte received, determine if it is valid, and then decide to ACK or NAK it. 28.8.7 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. By initializing NBYTES to zero before a transfer, and writing a one to CR.CUP, NBYTES is incremented by one each time a data has been transmitted or received. This allows the user to detect how much data was actually transferred by the DMA system. To assure correct behavior, respect the following programming sequences: 28.8.7.1 Data Transmit with the Peripheral DMA Controller 1. 2. 3. 4. 5. 28.8.7.2 Data Receive with the Peripheral DMA Controller 1. 2. 3. 4. 5. 28.8.8 Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). Configure the TWIS (ADR, NBYTES, etc.). Start the transfer by enabling the Peripheral DMA Controller to transmit. Wait for the Peripheral DMA Controller end-of-transmit flag. Disable the Peripheral DMA Controller. Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.). Configure the TWIS (ADR, NBYTES, etc.). Start the transfer by enabling the Peripheral DMA Controller to receive. Wait for the Peripheral DMA Controller end-of-receive flag. Disable the Peripheral DMA Controller. SMBus Mode SMBus mode is enabled by writing a one to the SMBus Mode Enable (SMEN) bit in CR. SMBus mode operation is similar to I²C operation with the following exceptions: • Only 7-bit addressing can be used. • The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be written to TR. • Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). • A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. Address matching on these addresses can be enabled by configuring CR appropriately. 28.8.8.1 Packet Error Checking (PEC) Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to the Packet Error Checking Enable (PECEN) bit in CR enables automatic PEC handling in the 754 42023H–SAM–11/2016 ATSAM4L8/L4/L2 current transfer. The PEC generator is always updated on every bit transmitted or received, so that PEC handling on following linked transfers will be correct. In slave receiver mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NAK value. The SR.SMBPECERR bit is set automatically if a PEC error occurred. In slave transmitter mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the master must take appropriate action. The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled when NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if PEC enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. 28.8.8.2 Timeouts The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave will leave the bus. The SR.SMBTOUT bit is also set. 28.8.9 Wakeup from Sleep Modes by TWI Address Match The TWIS is able to wake the device up from a sleep mode upon an address match, including sleep modes where CLK_TWIS is stopped. After detecting the START condition on the bus, The TWIS will stretch TWCK until CLK_TWIS has started. The time required for starting CLK_TWIS depends on which sleep mode the device is in. After CLK_TWIS has started, the TWIS releases its TWCK stretching and receives one byte of data on the bus. At this time, only a limited part of the device, including the TWIS, receives a clock, thus saving power. If the received byte is a master code, the TWIS enters HS-mode. The TWIS goes on to receive the slave address. If the address phase causes a TWIS address match, the entire device is wakened and normal TWIS address matching actions are performed. Normal TWI transfer then follows. If the TWIS is not addressed, CLK_TWIS is automatically stopped and the device immediately returns to its original sleep mode. If the TWIS is in HS-mode, it remains so until it detects a STOP condition on the bus, after which it switches back to F/S-mode. 755 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.8.10 Identifying Bus Events This chapter lists the different bus events, and how these affects the bits in the TWIS registers. This is intended to help writing drivers for the TWIS. Table 28-5. Bus Events Event Effect Slave transmitter has sent a data byte SR.THR is cleared. SR.BTF is set. The value of the ACK bit sent immediately after the data byte is given by CR.ACK. Slave receiver has received a data byte SR.RHR is set. SR.BTF is set. SR.NAK updated according to value of ACK bit received from master. Start+Sadr on bus, but address is to another slave None. Start+Sadr on bus, current slave is addressed, but address match enable bit in CR is not set None. Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set Correct address match bit in SR is set. SR.TRA updated according to transfer direction (updating is done one CLK_TWIS cycle after address match bit is set) Slave enters appropriate transfer direction mode and data transfer can commence. Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set, SR.STREN and SR.SOAM are set. Correct address match bit in SR is set. SR.TRA updated according to transfer direction (updating is done one CLK_TWIS cycle after address match bit is set). Slave stretches TWCK immediately after transmitting the address ACK bit. TWCK remains stretched until all address match bits in SR have been cleared. Slave enters appropriate transfer direction mode and data transfer can commence. Repeated Start received after being addressed SR.REP set. SR.TCOMP unchanged. Stop received after being addressed SR.STO set. SR.TCOMP set. Start, Repeated Start, or Stop received in illegal position on bus SR.BUSERR set. SR.STO and SR.TCOMP may or may not be set depending on the exact position of an illegal stop. Data is to be received in slave receiver mode, SR.STREN is set, and RHR is full TWCK is stretched until RHR has been read. Data is to be transmitted in slave receiver mode, SR.STREN is set, and THR is empty TWCK is stretched until THR has been written. 756 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 28-5. Bus Events Event Effect Data is to be received in slave receiver mode, SR.STREN is cleared, and RHR is full TWCK is not stretched, read data is discarded. SR.ORUN is set. Data is to be transmitted in slave receiver mode, SR.STREN is cleared, and THR is empty TWCK is not stretched, previous contents of THR is written to bus. SR.URUN is set. SMBus timeout received SR.SMBTOUT is set. TWCK and TWD are immediately released. Slave transmitter in SMBus PEC mode has transmitted a PEC byte, that was not identical to the PEC calculated by the master receiver. Slave receiver discovers SMBus PEC Error Master receiver will transmit a NAK as usual after the last byte of a master receiver transfer. Master receiver will retry the transfer at a later time. SR.SMBPECERR is set. NAK returned after the data byte. 757 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9 User Interface Table 28-6. TWIS Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Read/Write 0x00000000 0x04 NBYTES Register NBYTES Read/Write 0x00000000 0x08 Timing Register TR Read/Write 0x00000000 0x0C Receive Holding Register RHR Read-only 0x00000000 0x10 Transmit Holding Register THR Write-only 0x00000000 0x14 Packet Error Check Register PECR Read-only 0x00000000 0x18 Status Register SR Read-only 0x00000002 0x1C Interrupt Enable Register IER Write-only 0x00000000 0x20 Interrupt Disable Register IDR Write-only 0x00000000 0x24 Interrupt Mask Register IMR Read-only 0x00000000 0x28 Status Clear Register SCR Write-only 0x00000000 0x2C Parameter Register PR Read-only -(1) 0x30 Version Register VR Read-only -(1) 0x34 HS-mode Timing Register HSTR Read/Write 0x00000000 0x38 Slew Rate Register SRR Read/Write 0x00000000 0x3C HS-mode Slew Rate Register HSSRR Read/Write 0x00000000 Note: 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter. 758 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - TENBIT 23 22 21 20 19 18 17 16 ADR[9:8] ADR[7:0] 15 14 13 12 11 10 9 8 SODR SOAM CUP ACK PECEN SMHH SMDA - 7 6 5 4 3 2 1 0 SWRST - - STREN GCMATCH SMATCH SMEN SEN • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match. • ADR: Slave Address Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise. • SODR: Stretch Clock on Data Byte Reception 0: Does not stretch bus clock immediately before ACKing a received data byte. 1: Stretches bus clock immediately before ACKing a received data byte. • SOAM: Stretch Clock on Address Match 0: Does not stretch bus clock after address match. 1: Stretches bus clock after address match. • CUP: NBYTES Count Up 0: Causes NBYTES to count down (decrement) per byte transferred. 1: Causes NBYTES to count up (increment) per byte transferred. • ACK: Slave Receiver Data Phase ACK Value 0: Causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode. 1: Causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode. • PECEN: Packet Error Checking Enable 0: Disables SMBus PEC (CRC) generation and check. 1: Enables SMBus PEC (CRC) generation and check. • SMHH: SMBus Host Header 0: Causes the TWIS not to acknowledge the SMBus Host Header. 1: Causes the TWIS to acknowledge the SMBus Host Header. • SMDA: SMBus Default Address 0: Causes the TWIS not to acknowledge the SMBus Default Address. 1: Causes the TWIS to acknowledge the SMBus Default Address. • SWRST: Software Reset This bit will always read as 0. Writing a zero to this bit has no effect. 759 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address. 1: Causes the TWIS to acknowledge the General Call Address. • SMATCH: Slave Address Match 0: Causes the TWIS not to acknowledge the Slave Address. 1: Causes the TWIS to acknowledge the Slave Address. • SMEN: SMBus Mode Enable 0: Disables SMBus mode. 1: Enables SMBus mode. • SEN: Slave Enable 0: Disables the slave interface. 1: Enables the slave interface. 760 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.2 Name: NBYTES Register NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 NBYTES • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer. NBYTES can be incremented or decremented automatically by hardware. 761 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.3 Name: Timing Register TR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 SUDAT 15 14 13 12 TTOUT 7 6 5 4 TLOWS • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter. The counter is prescaled according to the following formula: f CLK_TWIS f PRESCALED = -----------------------( EXP + 1 ) 2 • SUDAT: Data Setup Cycles Non-prescaled clock cycles for data setup count. Used to time TSU_DAT. Data is driven SUDAT cycles after TWCK low detected. This timing is used for timing the ACK/NAK bits, and any data bits driven in slave transmitter mode. • TTOUT: SMBus TTIMEOUT Cycles Prescaled clock cycles used to time SMBus TTIMEOUT. • TLOWS: SMBus TLOW:SEXT Cycles Prescaled clock cycles used to time SMBus TLOW:SEXT. 762 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.4 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus. 763 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.5 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here. 764 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.6 Name: Packet Error Check Register PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PEC • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition. Provided if the user manually wishes to control when the PEC byte is transmitted, or wishes to access the PEC value for other reasons. In ordinary operation, the PEC handling is done automatically by hardware. 765 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.7 Name: Status Register SR Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN TRA - TCOMP SEN TXRDY RXRDY • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when byte transfer has completed. • REP: Repeated Start Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a REPEATED START condition is received. • STO: Stop Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the STOP condition is received. • SMBDAM: SMBus Default Address Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the SMBus Default Address. • SMBHHM: SMBus Host Header Address Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the SMBus Host Header Address. • GCM: General Call Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the General Call Address. • SAM: Slave Address Match This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the received address matched the Slave Address. • BUSERR: Bus Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a misplaced START or STOP condition has occurred. • SMBPECERR: SMBus PEC Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus PEC error has occurred. 766 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred. • NAK: NAK Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a NAK was received from the master during slave transmitter operation. • ORUN: Overrun This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an overrun has occurred in slave receiver mode. Can only occur if CR.STREN is zero. • URUN: Underrun This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an underrun has occurred in slave transmitter mode. Can only occur if CR.STREN is zero. • TRA: Transmitter Mode 0: The slave is in slave receiver mode. 1: The slave is in slave transmitter mode. • TCOMP: Transmission Complete This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when transmission is complete. Set after receiving a STOP after being addressed. • SEN: Slave Enabled 0: The slave interface is disabled. 1: The slave interface is enabled. • TXRDY: TX Buffer Ready 0: The TX buffer is full and should not be written to. 1: The TX buffer is empty, and can accept new data. • RXRDY: RX Buffer Ready 0: No RX data ready in RHR. 1: RX data is ready to be read from RHR. 767 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will write a one to the corresponding bit in IMR. 768 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 769 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 770 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.11 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM - GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 771 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.12 Name: Parameter Register PR Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - HS • HS: HS-mode 0: High-speed-mode is not supported. 1: High-speed-mode is supported. 772 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.13 Name: Version Register VR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 773 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.14 Name: HS-mode Timing Register HSTR Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 HDDAT 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - • HDDAT: Data Hold Cycles Non-prescaled clock cycles for data hold count when the TWIS is in HS-mode. Used to time THD_DAT. Data is driven HDDAT cycles after a LOW on TWCK is detected. This timing is used for timing the ACK/NAK bits, and any data bits driven in slave transmitter mode. 774 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.15 Name: Slew Rate Register SRR Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 - - 23 22 21 - - 15 28 27 26 25 24 - - - - 20 19 18 17 16 - - - - - - 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - - - - - FILTER DASLEW 1 0 DADRIVEL • FILTER: Input Spike Filter Control FILTER Value Function 0 Reserved 1 Reserved 2 Standard- or Fast-mode 3 Fast-mode Plus • DASLEW: Data Slew Limit Selects the slew limit of the TWD output buffer in F/S-mode. • DADRIVEL: Data Drive Strength LOW Selects the pull-down drive strength of the TWD output buffer in F/S-mode. Refer to Section 42. ”Electrical Characteristics” on page 1121 for appropriates values of these register fields. 775 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.9.16 Name: HS-mode Slew Rate Register HSSRR Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 - - 23 22 21 - - 15 28 27 26 25 24 - - - - 20 19 18 17 16 - - - - - - 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - - - - - FILTER DASLEWL 1 0 DADRIVEL • FILTER: Input Spike Filter Control FILTER Value Function 0 Reserved 1 HS-mode 2 Reserved 3 Reserved • DASLEW: Data Slew Limit Selects the slew limit of the TWD output buffer in HS-mode. • DADRIVEL: Data Drive Strength LOW Selects the pull-down drive strength of the TWD output buffer in HS-mode. Refer to Section 42. ”Electrical Characteristics” on page 1121 for appropriates values of these register fields. 776 42023H–SAM–11/2016 ATSAM4L8/L4/L2 28.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 109 for details. Table 28-7. Module Clock Name Module Name Clock Name Description TWIS0 CLK_TWIS0 Clock for the TWIS0 bus interface TWIS1 CLK_TWIS1 Clock for the TWIS1 bus interface Note : TWI2 and TWI3 are master only. TWI0 and TWI1 are master and slave Table 28-8. Register Reset Values Register Reset Value VERSION 0x00000140 PARAMETER 0x00000001 777 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29. Inter-IC Sound Controller (IISC) Rev: 1.0.0.0 29.1 Features • Compliant with Inter-IC Sound (I2S) bus specification • Master, slave, and controller modes: • • • • • 29.2 – Slave: data received/transmitted – Master: data received/transmitted and clocks generated – Controller: clocks generated Individual enable and disable of receiver, transmitter, and clocks Configurable clock generator common to receiver and transmitter: – Suitable for a wide range of sample frequencies (fs), including 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, and 192kHz – 16fs to 1024fs Master Clock generated for external oversampling ADCs Several data formats supported: – 32-, 24-, 20-, 18-, 16-, and 8-bit mono or stereo format – 16- and 8-bit compact stereo format, with left and right samples packed in the same word to reduce data transfers DMA interfaces for receiver and transmitter to reduce processor overhead: – Either one DMA channel for both audio channels, or – One DMA channel per audio channel Smart holding registers management to avoid audio channels mix after overrun or underrun Overview The Inter-IC Sound Controller (IISC) provides a 5-wire, bidirectional, synchronous, digital audio link with external audio devices: ISDI, ISDO, IWS, ISCK, and IMCK pins. This controller is compliant with the Inter-IC Sound (I2S) bus specification. The IISC consists of a Receiver, a Transmitter, and a common Clock Generator, that can be enabled separately, to provide Master, Slave, or Controller modes with Receiver, Transmitter, or both active. Peripheral DMA channels, separate for the Receiver and for the Transmitter, allow a continuous high bitrate data transfer without processor intervention to the following: • Audio CODECs in Master, Slave, or Controller mode • Stereo DAC or ADC through dedicated I2S serial interface The IISC can use either a single DMA channel for both audio channels or one DMA channel per audio channel. The 8- and 16-bit compact stereo format allows reducing the required DMA bandwidth by transferring the left and right samples within the same data word. In Master Mode, the IISC allows outputting a 16 fs to 1024fs Master Clock, in order to provide an oversampling clock to an external audio codec or digital signal processor (DSP). 778 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.3 Block Diagram Figure 29-1. IISC Block Diagram IISC Peripheral DMA Controller Interrupt Controller 29.4 Clocks PB clock PB Rx Tx IRQ Transmitter IWS ISDI ISDO I/O Lines Description Table 29-1. I/O Lines Description Pin Name 29.5 Receiver ISCK I/O Controller Peripheral Bus Bridge IMCK Generic clock Peripheral Bus interface SCIF Power Manager Pin Description Type IMCK Master Clock Output ISCK Serial Clock Input/Output 2 IWS I S Word Select Input/Output ISDI Serial Data Input Input ISDO Serial Data Output Output Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 29.5.1 I/O lines The IISC pins may be multiplexed with I/O Controller lines. The user must first program the I/O Controller to assign the desired IISC pins to their peripheral function. If the IISC I/O lines are not used by the application, they can be used for other purposes by the I/O Controller. It is required to enable only the IISC inputs and outputs actually in use. 29.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the IISC, the IISC will stop functioning and resume operation after the system wakes up from sleep mode. 779 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.5.3 Clocks The clock for the IISC bus interface (CLK_IISC) is generated by the Power Manager. It is recommended to disable the IISC before disabling the clock, to avoid freezing the IISC in an undefined state. One of the generic clocks is connected to the IISC. The generic clock (GCLK_IISC) can be set to a wide range of frequencies and clock sources. The GCLK_IISC must be enabled and configured before use. Refer to the module configuration section for details on the GCLK_IISC used for the IISC. The frequency for this clock has to be set as described in Table. 29.5.4 DMA The IISC DMA handshake interfaces are connected to the Peripheral DMA Controller. Using the IISC DMA functionality requires the Peripheral DMA Controller to be programmed first. 29.5.5 Interrupts The IISC interrupt line is connected to the Interrupt Controller. Using the IISC interrupt requires the Interrupt Controller to be programmed first. 29.5.6 29.6 29.6.1 Debug Operation When an external debugger forces the CPU into debug mode, the IISC continues normal operation. If this module is configured in a way that requires it to be periodically serviced by the CPU through interrupt requests or similar, improper operation or data loss may result during debugging. Functional Description Initialization The IISC features a Receiver, a Transmitter, and, for Master and Controller modes, a Clock Generator. Receiver and Transmitter share the same Serial Clock and Word Select. Before enabling the IISC, the chosen configuration must be written to the Mode Register (MR). The IMCKMODE, MODE, and DATALENGTH fields in the MR register must be written. If the IMCKMODE field is written as one, then the IMCKFS field should be written with the chosen ratio, as described in Section 29.6.5 “Serial Clock and Word Select Generation” on page 782. Once the Mode Register has been written, the IISC Clock Generator, Receiver, and Transmitter can be enabled by writing a one to the CKEN, RXEN, and TXEN bits in the Control Register (CR). The Clock Generator can be enabled alone, in Controller Mode, to output clocks to the IMCK, ISCK, and IWS pins. The Clock Generator must also be enabled if the Receiver or the Transmitter is enabled. The Clock Generator, Receiver, and Transmitter can be disabled independently by writing a one to CR.CXDIS, CR.RXDIS and/or CR.TXDIS respectively. Once requested to stop, they will only stop when the transmission of the pending frame transmission will be completed. 29.6.2 Basic Operation The Receiver can be operated by reading the Receiver Holding Register (RHR), whenever the Receive Ready (RXRDY) bit in the Status Register (SR) is set. Successive values read from RHR will correspond to the samples from the left and right audio channels for the successive frames. 780 42023H–SAM–11/2016 ATSAM4L8/L4/L2 The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), whenever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values written to THR should correspond to the samples from the left and right audio channels for the successive frames. The Receive Ready and Transmit Ready bits can be polled by reading the Status Register. The IISC processor load can be reduced by enabling interrupt-driven operation. The RXRDY and/or TXRDY interrupt requests can be enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER). The interrupt service routine associated to the IISC interrupt request will then be executed whenever the Receive Ready or the Transmit Ready status bit is set. 29.6.3 Master, Controller, and Slave Modes In Master and Controller modes, the IISC provides the Master Clock, the Serial Clock and the Word Select. IMCK, ISCK, and IWS pins are outputs. In Controller mode, the IISC Receiver and Transmitter are disabled. Only the clocks are enabled and used by an external receiver and/or transmitter. In Slave mode, the IISC receives the Serial Clock and the Word Select from an external master. ISCK and IWS pins are inputs. The mode is selected by writing the MODE field of the Mode Register (MR). Since the MODE field changes the direction of the IWS and ISCK pins, the Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS and ISCK pins. 29.6.4 I2S Reception and Transmission Sequence As specified in the I2S protocol, data bits are left-adjusted in the Word Select time slot, with the MSB transmitted first, starting one clock period after the transition on the Word Select line. Figure 29-2. I2S Reception and Transmission Sequence Serial Clock ISCK Word Select IWS Data ISDI/ISDO MSB LSB Left Channel MSB Right Channel Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The Word Select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel. The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the MR.DATALENGTH field. If the time slot allows for more data bits than written in the MR.DATALENGTH field, zeroes are appended to the transmitted data word or extra received bits are discarded. If the time slot allows for less data bits than written, the extra bits to be transmitted are not sent or the missing bits are set to zero in the received data word. 781 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.6.5 Serial Clock and Word Select Generation The generation of clocks in the IISC is described in Figure 29-3 on page 783. In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK and IWS pins are inputs and no generic clock is required by the IISC. In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock through the Mode Register (MR). IMCK, ISCK, and IWS pins are outputs and a generic clock is used to derive the IISC clocks. Audio codecs connected to the IISC pins may require a Master Clock signal with a frequency multiple of the audio sample frequency (fs), such as 256fs. When the IISC is in Master mode, writing a one to MR.IMCKMODE will output GCLK_IISC as Master Clock to the IMCK pin, and will divide GCLK_IISC to create the internal bit clock, output on the ISCK pin. The clock division factor is defined by writing to MR.IMCKFS and MR.DATALENGTH, as described “IMCKFS: Master Clock to fs Ratio” on page 789. The Master Clock (IMCK) frequency is 16*(IMCKFS+1) times the sample frequency (fs), i.e. IWS frequency. The Serial Clock (ISCK) frequency is 2*Slot Length times the sample frequency (fs), where Slot Length is defined in Table 29-2 on page 782. Table 29-2. Slot Length MR.DATALENGT H Word Length Slot Length 0 32 bits 32 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo 6 8 bits 7 8 bits compact stereo 32 if MR.IWS24 is zero 24 if MR.IWS24 is one 16 8 Warning: MR.IMCKMODE should only be written as one if the Master Clock frequency is strictly higher than the Serial Clock. If a Master Clock output is not required, the GCLK_IISC generic clock is used as ISCK, by writing a zero to MR.IMCKMODE. Alternatively, if the frequency of the generic clock used is a multiple of the required ISCK frequency, the IMCK to ISCK divider can be used with the ratio defined by writing the MR.IMCKFS field. The IWS pin is used as Word Select as described in Section 29.6.4 “I2S Reception and Transmission Sequence” on page 781. 782 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 29-3. IISC Clocks Generation CR.CKEN/CKDIS MR.IMCKMODE Clock enable GCLK_IISC IMCK pin output Clock divider MR.IMCKMODE 0 MR.IMCKFS MR.DATALENGTH 1 ISCK pin output CR.CKEN/CKDIS 0 ISCK pin input 1 Internal bit clock Clock enable Clock divider MR.MODE = SLAVE MR.DATALENGTH IWS pin output 0 IWS pin input 29.6.6 1 Internal word clock Mono When the Transmit Mono (TXMONO) in the Mode Register is set, data written to the left channel is duplicated to the right output channel. When the Receive Mono (RXMONO) in the Mode Register is set, data received from the left channel is duplicated to the right channel. 29.6.7 Holding Registers The IISC user interface includes a Receive Holding Register (RHR) and a Transmit Holding Register (THR). RHR and THR are used to access audio samples for both audio channels. When a new data word is available in the RHR register, the Receive Ready bit (RXRDY) in the Status Register (SR) is set. Reading the RHR register will clear this bit. A receive overrun condition occurs if a new data word becomes available before the previous data word has been read from the RHR register. Then, the Receive Overrun bit in the Status Register will be set and bit i of the RXORCH field in the Status Register is set, where i is the current receive channel number. When the THR register is empty, the Transmit Ready bit (TXRDY) in the Status Register (SR) is set. Writing into the THR register will clear this bit. A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to the THR register. Then, the Transmit Underrun bit in the Status Register will be set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is transmitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current transmit channel number is transmitted. 783 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Data words are right-justified in the RHR and THR registers. For 16-bit compact stereo, the left sample uses bits 15 through 0 and the right sample uses bits 31 through 16 of the same data word. For 8-bit compact stereo, the left sample uses bits 7 through 0 and the right sample uses bits 15 through 8 of the same data word. 29.6.8 DMA Operation The Receiver and the Transmitter can each be connected either to one single Peripheral DMA channel or to one Peripheral DMA channel per data channel. This is selected by writing to the MR.RXDMA and MR.TXDMA bits. If a single Peripheral DMA channel is selected, all data samples use IISC Receiver or Transmitter DMA channel 0. The Peripheral DMA reads from the RHR register and writes to the RHR register for both audio channels, successively. The Peripheral DMA transfers may use 32-bit word, 16-bit halfword, or 8-bit byte according to the value of the MR.DATALENGTH field. 29.6.9 Loop-back Mode For debugging purposes, the IISC can be configured to loop back the Transmitter to the Receiver. Writing a one to the MR.LOOP bit will internally connect ISDO to ISDI, so that the transmitted data is also received. Writing a zero to MR.LOOP will restore the normal behavior with independent Receiver and Transmitter. As for other changes to the Receiver or Transmitter configuration, the IISC Receiver and Transmitter must be disabled before writing to the MR register to update MR.LOOP. 29.6.10 Interrupts An IISC interrupt request can be triggered whenever one or several of the following bits are set in the Status Register (SR): Receive Ready (RXRDY), Receive Overrun (RXOR), Transmit Ready (TXRDY), or Transmit Underrun (TXOR). The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one the corresponding bit in the Status Clear Register (SCR). For debugging purposes, interrupt requests can be simulated by writing a one to the corresponding bit in the Status Set Register (SSR). 784 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 29-4. Interrupt Block Diagram IER Set IMR Clear IDR Transmitter TXRDY TXUR Interrupt Control IISC Interrupt Request Receiver RXRDY RXOR 29.7 IISC Application Examples The IISC can support several serial communication modes used in audio or high-speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the IISC are not listed here. Figure 29-5. Audio Application Block Diagram Serial Clock ISCK Word Select IWS IISC Serial Data Out EXTERNAL I2S RECEIVER ISDO ISDI Serial Clock Word Select Serial Data Out MSB LSB MSB 785 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 29-6. Codec Application Block Diagram IMCK ISCK IISC Master Clock Serial Clock EXTERNAL AUDIO CODEC Word Select IWS ISDO ISDI Serial Data Out Serial Data In Serial Clock Word Select Right Time Slot Left Time Slot Dstart Dend Serial Data Out Serial Data In Figure 29-7. Time Slot Application Block Diagram IMCK ISCK IISC IWS ISDO ISDI Master Clock Serial Clock EXTERNAL AUDIO CODEC for Left Time Slot Word Select Serial Data Out Serial Data In EXTERNAL AUDIO CODEC for Right Time Slot Serial Clock Word Select Left Time Slot Dstart Right Time Slot Dend Serial Data Out Serial Data In 786 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8 User Interface Table 29-3. Note: IISC Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CR Write-only 0x00000000 0x04 Mode Register MR Read/Write 0x00000000 0x08 Status Register SR Read-only 0x00000000 0x0C Status Clear Register SCR Write-only 0x00000000 0x10 Status Set Register SSR Write-only 0x00000000 0x14 Interrupt Enable Register IER Write-only 0x00000000 0x18 Interrupt Disable Register IDR Write-only 0x00000000 0x1C Interrupt Mask Register IMR Read-only 0x00000000 0x20 Receiver Holding Register RHR Read-only 0x00000000 0x24 Transmitter Holding Register THR Write-only 0x00000000 0x28 Version Register VERSION Read-only -(1) 0x2C Parameter Register PARAMETER Read-only -(1) 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter. 787 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 SWRST - TXDIS TXEN CKDIS CKEN RXDIS RXEN The Control Register should only be written to enable the IISC after the chosen configuration has been written to the Mode Register, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to disable the IISC before writing a new value into MR. • SWRST: Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets all the registers in the module. The module will be disabled after the reset. This bit always reads as zero. • TXDIS: Transmitter Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the IISC Transmitter. SR.TXEN will be cleared when the Transmitter is effectively stopped. • TXEN: Transmitter Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the IISC Transmitter, if TXDIS is not one. SR.TXEN will be set when the Transmitter is effectively started. • CKDIS: Clocks Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the IISC clocks generation. • CKEN: Clocks Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the IISC clocks generation, if CKDIS is not one. • RXDIS: Receiver Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the IISC Receiver. SR.TXEN will be cleared when the Transmitter is effectively stopped. • RXEN: Receiver Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the IISC Receiver, if RXDIS is not one. SR.RXEN will be set when the Receiver is effectively started. 788 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 IWS24 IMCKMODE 23 22 21 20 - - - 15 14 - 27 26 25 24 19 18 17 16 - - - - - 13 12 11 10 9 8 TXSAME TXDMA TXMONO RXLOOP RXDMA RXMONO 7 6 5 4 2 1 0 - - - - MODE IMCKFS 3 DATALENGTH The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs. The proper sequence is to write the MR register, then write the CR register to enable the IISC, or to disable the IISC before writing a new value into MR. • IWS24: IWS TDM Slot Width 0: IWS slot is 32-bit wide for DATALENGTH=18/20/24-bit. 1: IWS slot is 24-bit wide for DATALENGTH=18/20/24-bit. Refer to Table 29-2, “Slot Length,” on page 782. • IMCKMODE: Master Clock Mode 0: No Master Clock generated (generic clock is used as ISCK output). 1: Master Clock generated (generic clock is used as IMCK output). Warning: if IMCK frequency is the same as ISCK, IMCKMODE should not be written as one. Refer to Section 29.6.5 “Serial Clock and Word Select Generation” on page 782 and Table 29-2, “Slot Length,” on page 782. • IMCKFS: Master Clock to fs Ratio Master Clock frequency is 16*(IMCKFS+1) times the sample rate, i.e. IWS frequency: Table 29-4. fs Ratio Master Clock to Sample Frequency (fs) Ratio IMCKFS 16 fs 0 32 fs 1 48fs 2 64 fs 3 96fs 5 128 fs 7 192fs 11 256 fs 15 789 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 29-4. fs Ratio Master Clock to Sample Frequency (fs) Ratio IMCKFS 384 fs 23 512 fs 31 768 fs 47 1024 fs 63 • TXSAME: Transmit Data when Underrun 0: Zero sample transmitted when underrun. 1: Previous sample transmitted when underrun • TXDMA: Single or multiple DMA Channels for Transmitter 0: Transmitter uses a single DMA channel for both audio channels. 1: Transmitter uses one DMA channel per audio channel. • TXMONO: Transmit Mono 0: Stereo. 1: Mono, with left audio samples duplicated to right audio channel by the IISC. • RXLOOP: Loop-back Test Mode 0: Normal mode. 1: ISDO output of IISC is internally connected to ISDI input. • RXMONO: Receive Mono 0: Stereo. 1: Mono, with left audio samples duplicated to right audio channel by the IISC. • RXDMA: Single or multiple DMA Channels for Receiver 0: Receiver uses a single DMA channel for both audio channels. 1: Receiver uses one DMA channel per audio channel. • DATALENGTH: Data Word Length Table 29-5. Data Word Length DATALENGTH Word Length 0 32 bits 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo 6 8 bits 7 8 bits compact stereo Comments Left sample in bits 15 through 0 and right sample in bits 31 through 16 of the same word Left sample in bits 7 through 0 and right sample in bits 15 through 8 of the same word • MODE: Mode Table 29-6. Mode MODE Comments 0 SLAVE ISCK and IWS pin inputs used as Bit Clock and Word Select/Frame Sync. 1 MASTER Bit Clock and Word Select/Frame Sync generated by IISC from GCLK_IISC and output to ISCK and IWS pins. GCLK_IISC is output as Master Clock on IMCK if MR.IMCKMODE is one. 790 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY TXEN - RXOR RXRDY RXEN TXURCH RXORCH • TXURCH: Transmit Underrun Channel This field is cleared when SCR.TXUR is written to one. Bit i of this field is set when a transmit underrun error occurred in channel i (i=0 for first channel of the frame). • RXORCH: Receive Overrun Channel This field is cleared when SCR.RXOR is written to one. Bit i of this field is set when a receive overrun error occurred in channel i (i=0 for first channel of the frame). • TXUR: Transmit Underrun This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an underrun error occurs on the THR register or when the corresponding bit in SSR is written to one. • TXRDY: Transmit Ready This bit is cleared when data is written to THR. This bit is set when the THR register is empty and can be written with new data to be transmitted. • TXEN: Transmitter Enabled This bit is cleared when the Transmitter is effectively disabled, following a CR.TXDIS or CR.SWRST request. This bit is set when the Transmitter is effectively enabled, following a CR.TXEN request. • RXOR: Receive Overrun This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an overrun error occurs on the RHR register or when the corresponding bit in SSR is written to one. • RXRDY: Receive Ready This bit is cleared when the RHR register is read. This bit is set when received data is present in the RHR register. • RXEN: Receiver Enabled This bit is cleared when the Receiver is effectively disabled, following a CR.RXDIS or CR.SWRST request. This bit is set when the Receiver is effectively enabled, following a CR.RXEN request. 791 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 792 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.5 Name: Status Set Register SSR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in SR. 793 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 794 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 795 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 796 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.9 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RHR[31:24] 23 22 21 20 RHR[23:16] 15 14 13 12 RHR[15:8] 7 6 5 4 RHR[7:0] • RHR: Received Word This field is set by hardware to the last received data word. If MR.DATALENGTH specifies less than 32 bits, data shall be rightjustified into the RHR field. 797 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.10 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 THR[31:24] 23 22 21 20 THR[23:16] 15 14 13 12 THR[15:8] 7 6 5 4 THR[7:0] • THR: Data Word to Be Transmitted Next data word to be transmitted after the current word if TXRDY is not set. If MR.DATALENGTH specifies less than 32 bits, data shall be right-justified into the THR field. 798 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.11 Name: Module Version VERSION Access Type: Read-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 799 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.8.12 Name: Module Parameters PARAMETER Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Reserved. No functionality associated. 800 42023H–SAM–11/2016 ATSAM4L8/L4/L2 29.9 Module Configuration The specific configuration for each IISC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. “Power Manager (PM)” on page 109 for details. Table 29-7. IISC Clocks Clock Name Description CLK_IISC Clock for the IISC bus interface GCLK The generic clock used for the IISC is GCLK6 Table 29-8. Register Reset Values Register Reset Value VERSION 0x00000100 801 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30. Timer/Counter (TC) Rev: 4.0.2.0 30.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: • • • • • 30.2 – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse width modulation – Up/down capabilities – 2-bit gray up/down count for stepper motor Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals Internal interrupt signal Two global registers that act on all three TC channels Configuration registers can be write protected Peripheral event input on all A/B lines in capture mode Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The TC block has two global registers which act upon all three TC channels. The Block Control Register (BCR) allows the three channels to be started simultaneously with the same instruction. The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing them to be chained. 802 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.3 Block Diagram I/O Contr oller TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIOA1 TIOA2 TIMER_CLOCK3 TIMER_CLOCK4 XC0 XC1 TCLK1 Timer/Counter Channel 0 TIOA A0 TIOA0 B0 TIOB XC2 TCLK2 TIMER_CLOCK5 TC0XC0S CLK0 CLK1 CLK2 TIOB0 SYNC INT0 TCLK0 XC0 TCLK1 TIOA0 XC1 TIOA2 XC2 TCLK2 TC1XC1S TCLK0 XC0 TCLK1 XC1 Timer/Counter Channel 1 TIOA TIOB A1 TIOA1 B1 TIOB1 SYNC Timer/Counter Channel 2 INT1 TIOA A2 TIOA2 B2 TIOB XC2 TCLK2 TIOA0 TIOA1 TC2XC2S TIOB2 SYNC INT2 Timer Count er Interrupt Controller 30.4 I/O Lines Description Table 30-1. 30.5 I/O Lines Description Pin Name Description Type CLK0-CLK2 External Clock Input Input A0-A2 I/O Line A Input/Output B0-B2 I/O Line B Input/Output Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 30.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first program the I/O Controller to assign the TC pins to their peripheral functions. 803 42023H–SAM–11/2016 ATSAM4L8/L4/L2 When using the TIOA/TIOB lines as inputs the user must make sure that no peripheral events are generated on the line. Refer to Section 31. “Peripheral Event Controller (PEVC)” on page 845 for details. 30.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 30.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is disabled at reset, and can be enabled in the Power Manager. It is recommended to disable the TC before disabling the clock, to avoid freezing the TC in an undefined state. 30.5.4 Interrupts The TC interrupt request line is connected to the NVIC. Using the TC interrupt requires the NVIC to be programmed first. 30.5.5 Peripheral Events The TC peripheral events are connected via the Peripheral Event System. Refer to Section 31. “Peripheral Event Controller (PEVC)” on page 845 for details. 30.5.6 Debug Operation The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps peripherals running in debug operation. 30.6 Functional Description 30.6.1 30.6.1.1 TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Figure 30-3 on page 819. Channel I/O Signals As described in Figure 30.3 on page 803, each Channel has the following I/O signals. Table 30-2. Channel I/O Signals Description Block/Channel Signal Name XC0, XC1, XC2 Channel Signal External Clock Inputs TIOA Capture mode: Timer Counter Input Waveform mode: Timer Counter Output TIOB Capture mode: Timer Counter Input Waveform mode: Timer Counter Input/Output INT SYNC 30.6.1.2 Description Interrupt Signal Output Synchronization Input Signal 16-bit counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and 804 42023H–SAM–11/2016 ATSAM4L8/L4/L2 passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Status Register (SRn.COVFS) is set. The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 30.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 30-1 on page 806. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about the connection of these clock sources. • External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details about the connection of these clock sources. This selection is made by the Clock Selection field in the Channel n Mode Register (CMRn.TCCLKS). The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The Burst Signal Selection field in the CMRn register (CMRn.BURST) defines this signal. Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC. 805 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 30-1. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 CLKI TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Selected Clock XC0 XC1 XC2 BURST 1 30.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 30-2 on page 807. • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions have no effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA). • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. In Capture mode the clock can be stopped by an RB load event if the Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop commands have effect only if the clock is enabled. 806 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 30-2. Clock Control Selected Clock Trigger CLKSTA Q Q S CLKEN CLKDIS S R R Counter Clock 30.6.1.5 Stop Event Disable Event TC operating modes Each channel can independently operate in two different modes: • Capture mode provides measurement on signals. • Waveform mode provides wave generation. The TC operating mode selection is done by writing to the Wave bit in the CCRn register (CCRn.WAVE). In Capture mode, TIOA and TIOB are configured as inputs. In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 30.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.SWTRG). • SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing a one to the Synchro Command bit in the BCR register (BCR.SYNC). • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn (CMRn.CPCTRG) is written to one. 807 42023H–SAM–11/2016 ATSAM4L8/L4/L2 The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external event can then be programmed to perform a trigger by writing a one to the External Event Trigger Enable bit in CMRn (CMRn.ENETRG). If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 30.6.1.7 30.6.2 Peripheral events on TIOA/TIOB inputs The TIOA/TIOB input lines are ored internally with peripheral events from the Peripheral Event System. To capture using events the user must ensure that the corresponding pin functions for the TIOA/TIOB line are disabled. When capturing on the external TIOA/TIOB pin the user must ensure that no peripheral events are generated on this pin. Capture Operating Mode This mode is entered by writing a zero to the CMRn.WAVE bit. Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 30-3 on page 809 shows the configuration of the TC channel when programmed in Capture mode. 30.6.2.1 Capture registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in SRn (SRn.LOVRS). In this case, the old value is overwritten. 30.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled. 808 42023H–SAM–11/2016 42023H–SAM–11/2016 TIOA TIOB SYNC MTIOA MTIOB TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 TIMER_CLOCK1 1 Edge Detector ETRGEDG SWTRG CLKI Edge Detector LDRA CLK Trig S R OVF If RA is Loaded CPCTRG 16-bit Counter RESET Q LDBSTOP R S CLKEN Edge Detector LDRB Capture Register A Q CLKSTA LDBDIS Capture Register B CLKDIS SR Timer/Counter Channel If RA is not Loaded or RB is Loaded ABETRG BURST TCCLKS Compare RC = Register C COVFS INT ATSAM4L8/L4/L2 Figure 30-3. Capture Mode LOVRS CPCS LDRBS ETRGS LDRAS IMR 809 ATSAM4L8/L4/L2 30.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event. Figure 30-4 on page 811 shows the configuration of the TC channel when programmed in Waveform operating mode. 30.6.3.1 Waveform selection Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 810 42023H–SAM–11/2016 42023H–SAM–11/2016 TIOB SYNC XC2 XC1 TIMER_CLOCK5 XC0 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 Edge Detector EEVTEDG SWTRG Timer/Counter Channel EEVT BURST CLKI ENETRG Trig CLK R S WAVSEL RESET 16-bit Counter WAVSEL Q OVF Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC O utput Contr oller O utput Cont r oller TCCLKS TIOB MTIOB TIOA MTIOA ATSAM4L8/L4/L2 Figure 30-4. Waveform Mode CPCS CPBS COVFS ETRGS SR IMR 811 ATSAM4L8/L4/L2 30.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 30-5 on page 812. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 30-6 on page 813. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 30-5. WAVSEL= 0 Without Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC RB RA Waveform Examples Time TIOB TIOA 812 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 30-6. WAVSEL= 0 With Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA 30.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 30-7 on page 814. It is important to note that CVn can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 30-8 on page 814. In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the counter clock (CMRn.CPCDIS = 1). 813 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 30-7. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 30-8. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 30.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of CVn is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 30-9 on page 815. 814 42023H–SAM–11/2016 ATSAM4L8/L4/L2 A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 30-10 on page 815. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 30-9. WAVSEL = 1 Without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 30-10. WAVSEL = 1 With Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Waveform Examples Time TIOB TIOA 815 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 30-11 on page 816. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 30-12 on page 817. RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 30-11. WAVSEL = 3 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA 816 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 30-12. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 30.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger. The External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to zero, no external event is defined. If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by writing a one to the CMRn.ENETRG bit. As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the CMRn.WAVSEL field. 30.6.3.7 Output controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: • software trigger • external event • RC compare RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the following fields in CMRn: • RC Compare Effect on TIOB (CMRn.BCPC) 817 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.ACPA) 30.7 2-bit Gray Up/Down Counter for Stepper Motor Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA, TIOB outputs by means of GCEN bit in SMMRx registers. Up or Down count can be defined by writing bit DOWN in SMMRx registers. It is mandatory to configure the channel in WAVE mode in CMR register. The period of the counters can be programmed on RCx registers. Figure 30-13. 2-bit Gray Up/Down Counter. 30.8 Write Protection System In order to bring security to the Timer Counter, a write protection system has been implemented. The write protection mode prevent the write of BMR, FMR, CMRx, SMMRx, RAx, RBx, RCx registers. When this mode is enabled and one of the protected registers write, the register write request canceled. Due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a security code. Thus when enabling or disabling the write protection mode the WPKEY field of the WPMR register must be filled with the “TIM” ASCII code (corresponding to 0x54494D) otherwise the register write will be canceled. 818 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9 User Interface Table 30-3. TC Register Memory Map Offset Register Register Name Access Reset 0x00 Channel 0 Control Register CCR0 Write-only 0x00000000 0x04 Channel 0 Mode Register CMR0 Read/Write 0x00000000 0x08 Ch 0 Stepper Motor Mode Register SMMR0 Read/Write 0x00000000 0x10 Channel 0 Counter Value CV0 Read-only 0x00000000 0x14 Channel 0 Register A RA0 Read/Write (1) 0x00000000 Read/Write (1) 0x00000000 0x18 Channel 0 Register B RB0 0x1C Channel 0 Register C RC0 Read/Write 0x00000000 0x20 Channel 0 Status Register SR0 Read-only 0x00000000 0x24 Interrupt Enable Register IER0 Write-only 0x00000000 0x28 Channel 0 Interrupt Disable Register IDR0 Write-only 0x00000000 0x2C Channel 0 Interrupt Mask Register IMR0 Read-only 0x00000000 0x40 Channel 1 Control Register CCR1 Write-only 0x00000000 0x44 Channel 1 Mode Register CMR1 Read/Write 0x00000000 0x48 Ch 1 Stepper Motor Mode Register SMMR1 Read/Write 0x00000000 0x50 Channel 1 Counter Value CV1 Read-only 0x00000000 0x54 Channel 1 Register A RA1 Read/Write(1) 0x00000000 (1) 0x00000000 0x58 Channel 1 Register B RB1 Read/Write 0x5C Channel 1 Register C RC1 Read/Write 0x00000000 0x60 Channel 1 Status Register SR1 Read-only 0x00000000 0x64 Channel 1 Interrupt Enable Register IER1 Write-only 0x00000000 0x68 Channel 1 Interrupt Disable Register IDR1 Write-only 0x00000000 0x6C Channel 1 Interrupt Mask Register IMR1 Read-only 0x00000000 0x80 Channel 2 Control Register CCR2 Write-only 0x00000000 0x84 Channel 2 Mode Register CMR2 Read/Write 0x00000000 0x88 Ch 2 Stepper Motor Mode Register SMMR2 Read/Write 0x00000000 0x90 Channel 2 Counter Value CV2 Read-only 0x00000000 0x94 Channel 2 Register A RA2 Read/Write(1) 0x00000000 (1) 0x00000000 0x98 Channel 2 Register B RB2 Read/Write 0x9C Channel 2 Register C RC2 Read/Write 0x00000000 0xA0 Channel 2 Status Register SR2 Read-only 0x00000000 0xA4 Channel 2 Interrupt Enable Register IER2 Write-only 0x00000000 0xA8 Channel 2 Interrupt Disable Register IDR2 Write-only 0x00000000 0xAC Channel 2 Interrupt Mask Register IMR2 Read-only 0x00000000 0xC0 Block Control Register BCR Write-only 0x00000000 0xC4 Block Mode Register BMR Read/Write 0x00000000 819 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 30-3. TC Register Memory Map Offset Register Register Name Access Reset 0xE4 Write Protect Mode Register WPMR Read/Write 0x00000000 0xF8 Features Register FEATURES Read-only -(2) 0xFC Version Register VERSION Read-only -(2) Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Refer to the Module Configuration section at the end of this chapter. 820 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.1 Name: Channel Control Register CCR Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - SWTRG CLKDIS CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started. 0: Writing a zero to this bit has no effect. • CLKDIS: Counter Clock Disable Command 1: Writing a one to this bit will disable the clock. 0: Writing a zero to this bit has no effect. • CLKEN: Counter Clock Enable Command 1: Writing a one to this bit will enable the clock if CLKDIS is not one. 0: Writing a zero to this bit has no effect. 821 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.2 Name: Channel Mode Register: Capture Mode CMR Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 11 10 WAVE CPCTRG - - - ABETRG 7 6 5 4 3 2 LDBDIS LDBSTOP BURST LDRB LDRA CLKI 9 8 ETRGEDG 1 0 TCCLKS This register can only be written if write protect is disabled (WPMR.WPEN is zero). • LDRB: RB Loading Selection LDRB Edge 0 none 1 rising edge of TIOA 2 falling edge of TIOA 3 each edge of TIOA • LDRA: RA Loading Selection LDRA Edge 0 none 1 rising edge of TIOA 2 falling edge of TIOA 3 each edge of TIOA • WAVE 1: Capture mode is disabled (Waveform mode is enabled). 0: Capture mode is enabled. • CPCTRG: RC Compare Trigger Enable 1: RC Compare resets the counter and starts the counter clock. 0: RC Compare has no effect on the counter and its clock. 822 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • ABETRG: TIOA or TIOB External Trigger Selection 1: TIOA is used as an external trigger. 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs. • BURST: Burst Signal Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal 1 XC0 is ANDed with the selected clock 2 XC1 is ANDed with the selected clock 3 XC2 is ANDed with the selected clock • CLKI: Clock Invert 1: The counter is incremented on falling edge of the clock. 0: The counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection TCCLKS Clock Selected 0 TIMER_CLOCK1 1 TIMER_CLOCK2 2 TIMER_CLOCK3 3 TIMER_CLOCK4 4 TIMER_CLOCK5 5 XC0 6 XC1 7 XC2 823 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.3 Name: Channel Mode Register: Waveform Mode CMR Access Type: Read/Write Offset: 0x04 + n * 0x40 Reset Value: 0x00000000 31 30 29 BSWTRG 23 27 BEEVT 22 21 ASWTRG 15 28 20 WAVE 13 7 6 19 CPCDIS CPCSTOP 4 BURST BCPB 18 11 ENETRG 5 24 17 16 ACPC 12 WAVSEL 25 BCPC AEEVT 14 26 ACPA 10 9 EEVT 3 8 EEVTEDG 2 CLKI 1 0 TCCLKS This register can only be written if write protect is disabled (WPMR.WPEN is zero). • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 none 1 set 2 clear 3 toggle • BEEVT: External Event Effect on TIOB BEEVT Effect 0 none 1 set 2 clear 3 toggle 824 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • BCPC: RC Compare Effect on TIOB BCPC Effect 0 none 1 set 2 clear 3 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 none 1 set 2 clear 3 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 none 1 set 2 clear 3 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 none 1 set 2 clear 3 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 none 1 set 2 clear 3 toggle 825 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • ACPA: RA Compare Effect on TIOA ACPA Effect 0 none 1 set 2 clear 3 toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled). • WAVSEL: Waveform Selection WAVSEL Effect 0 UP mode without automatic trigger on RC Compare 1 UPDOWN mode without automatic trigger on RC Compare 2 UP mode with automatic trigger on RC Compare 3 UPDOWN mode with automatic trigger on RC Compare • ENETRG: External Event Trigger Enable 1: The external event resets the counter and starts the counter clock. 0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. • EEVT: External Event Selection Signal selected as external event TIOB Direction 0 TIOB input(1) 1 XC0 output 2 XC1 output 3 XC2 output EEVT Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge • CPCDIS: Counter Clock Disable with RC Compare 1: Counter clock is disabled when counter reaches RC. 0: Counter clock is not disabled when counter reaches RC. 826 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal. 1 XC0 is ANDed with the selected clock. 2 XC1 is ANDed with the selected clock. 3 XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock. 0: Counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection TCCLKS Clock Selected 0 TIMER_CLOCK1 1 TIMER_CLOCK2 2 TIMER_CLOCK3 3 TIMER_CLOCK4 4 TIMER_CLOCK5 5 XC0 6 XC1 7 XC2 827 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.4 Name: Stepper Motor Mode Register SMCR Access Type: Read/Write Offset: 0x08 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - DOWN GCEN This register can only be written if write protect is disabled (WPMR.WPEN is zero). • DOWN: Down Count 0: Up counter. 1: Down counter. • GCEN: Gray Count Enable 0: TIOAx and TIOBx are driven by internal counter of channel x. 1: TIOAx and TIOBx are driven by a 2-bit gray counter. 828 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.5 Name: Channel Counter Value Register CV Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 CV[15:8] 7 6 5 4 CV[7:0] • CV: Counter Value CV contains the counter value in real time. 829 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.6 Name: Channel Register A RA Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RA[15:8] 7 6 5 4 RA[7:0] This register can only be written if write protect is disabled (WPMR.WPEN is zero). • RA: Register A RA contains the Register A value in real time. 830 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.7 Name: Channel Register B RB Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RB[15:8] 7 6 5 4 RB[7:0] This register can only be written if write protect is disabled (WPMR.WPEN is zero). • RB: Register B RB contains the Register B value in real time. 831 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.8 Name: Channel Register C RC Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RC[15:8] 7 6 5 4 RC[7:0] This register can only be written if write protect is disabled (WPMR.WPEN is zero). • RC: Register C RC contains the Register C value in real time. 832 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.9 Name: Channel Status Register SR Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts. • MTIOB: TIOB Mirror 1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven high. 0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven low. • MTIOA: TIOA Mirror 1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven high. 0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven low. • CLKSTA: Clock Enabling Status 1: This bit is set when the clock is enabled. 0: This bit is cleared when the clock is disabled. • ETRGS: External Trigger Status 1: This bit is set when an external trigger has occurred. 0: This bit is cleared when the SR register is read. • LDRBS: RB Loading Status 1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • LDRAS: RA Loading Status 1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • CPCS: RC Compare Status 1: This bit is set when an RC Compare has occurred. 0: This bit is cleared when the SR register is read. 833 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • COVFS: Counter Overflow Status 1: This bit is set when a counter overflow has occurred. 0: This bit is cleared when the SR register is read. 834 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.10 Name: Channel Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 835 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.11 Name: Channel Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 836 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.12 Name: Channel Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 837 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.13 Name: Block Control Register BCR Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0: Writing a zero to this bit has no effect. 838 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.14 Name: Block Mode Register BMR Access Type: Read/Write Offset: 0xC4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - TC2XC2S TC1XC1S TC0XC0S This register can only be written if write protect is disabled (WPMR.WPEN is zero). 839 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S Signal Connected to XC2 0 TCLK2 1 none 2 TIOA0 3 TIOA1 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S Signal Connected to XC1 0 TCLK1 1 none 2 TIOA0 3 TIOA2 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2 840 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.15 Name: Write Protect Mode Register WPMR Access Type: Read/write Offset: 0xE4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 - - - - - - - WPEN • WPKEY: Write Protect Key Valid key is “TIM” in ASCII (0x54494D in hexadecimal). • WPEN: Write Protect Enable 1: Writing a one to this bit will enable write protection (WPKEY must be set). 0: Writing a zero to this bit will disable write protection (WPKEY must be set). Protected registers: Channel Mode Register: Capture Mode Channel Mode Register: Waveform Mode Stepper Motor Mode Register Register A Register B Register C Block Mode Register 841 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.16 Name: Features Register FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - BRPBHSB UPDNIMPL 7 6 5 4 3 2 1 0 CTRSIZE • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented. 0: Up/down counter capability is not implemented. • CTRSIZE: Counter size This field indicates the size of the counter in bits. 842 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.9.17 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 843 42023H–SAM–11/2016 ATSAM4L8/L4/L2 30.10 Module Configuration The specific configuration for each Timer/Counter instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 109 for details. Table 30-4. TC Bus Interface Clocks Module name Clock Name Description TC0 CLK_TC0 Clock for the TC0 bus interface TC1 CLK_TC1 Clock for the TC1 bus interface Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 30-5. Timer/Counter Clock Connections Module Source Name Connection TC0 Internal TIMER_CLOCK1 Generic Clock number 5 TIMER_CLOCK2 PBA Clock / 2 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 32 TIMER_CLOCK5 PBA Clock / 128 XC0 PA14, PB13 XC1 PA15, PB14 XC2 PA16, PB15 TIMER_CLOCK1 Generic Clock number 8 TIMER_CLOCK2 PBA Clock / 2 TIMER_CLOCK3 PBA Clock / 8 TIMER_CLOCK4 PBA Clock / 32 TIMER_CLOCK5 PBA Clock / 128 XC0 PC06, PC21 XC1 PC07, PC22 XC2 PC08, PC23 External TC1 Internal External Table 30-6. Register Reset Values Register Reset Value VERSION 0x00000402 844 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31. Peripheral Event Controller (PEVC) Rev: 2.0.0.0 31.1 Features • • • • 31.2 Direct peripheral to peripheral communication system Allows peripherals to receive, react to, and send peripheral events without CPU intervention Cycle deterministic event communication SleepWalking™ and asynchronous interrupts for peripheral operation in Power Save Modes Overview Several peripheral modules can be configured to emit or respond to signals known as peripheral events. The exact condition to trigger a peripheral event, or the action taken upon receiving a peripheral event, is specific to each module. Peripherals that respond to events are called users and peripherals that emit events are called generators. A module may be both a generator and user. The peripheral event generators and users are interconnected by a network known as the Peripheral Event System. The Peripheral Event Controller (PEVC) controls the interconnection parameters, such as generator-to-user multiplexing and peripheral event enable/disable. The Peripheral Event System allows low latency peripheral-to-peripheral signalling without CPU intervention, and without consuming system resources such as bus or RAM bandwidth. This offloads the CPU and system resources compared to a traditional interrupt-based software driven system. Figure 31-1. Peripheral Event System Overview Generator Generator User Peripheral Event System Generator/ User 845 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.3 Block Diagram The main building blocks of the PEVC are: • Channels: One channel per user, to propagate events and follow-up the user status • Event Shapers (EVS): Instantiated for some generators, in case synchronisation and/or edge detection is needed prior to peripheral event propagation • Input Glitch Filters (IGF): Present specifically for I/O inputs, to filter the incoming signal prior to going through EVS and Channel To help distinguish the different signalling stages, following naming conventions are used: • Generators generate events • PEVC multiplexes these incoming events • PEVC outputs triggers to users Figure 31-2. PEVC Block Diagram PEVC TRIG 0 EVS 0 Generator 0 PAD_EVT 0 IGF Channel 0 RDY 0 CLK 0 User 0 EVS … Generator ... TRIG... EVT... Channel ... Generator ... RDY... CLK... User ... EVT... TRIG i Channel i Generator j EVT j EVS IGF SEV RCSYS RDY i CLK i User i CHMX CLK_PEVC The maximum number of generators and Event Shapers supported by the PEVC is 64. The maximum number of channels and users supported by the PEVC is 32. EVS and IGF implementation are device-specific. Refer to the Module Configuration section at the end of this chapter for the device-specific configuration. 846 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.4 I/O Lines Description Table 31-1. 31.5 I/O Lines Description Pin Name Pin Description Type PAD_EVT[n] External Event Inputs Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 31.5.1 I/O Lines Multiplexed I/O lines can be used as event generators. To generate a peripheral event from an external source the source pin must be configured as an input pin by the I/O Controller. It is also possible to trigger a peripheral event by driving these pins from registers in the I/O Controller, or another peripheral output connected to the same pin. 31.5.2 Power Management and Low Power Operation As the peripheral events do not require CPU intervention, they are available in Idle mode. They are also available in deeper Power Save Modes if both the generator and user remain clocked in that mode. In deeper Power Save Modes, certain events can be issued even when the system clock is stopped, and revive unclocked user peripherals. The clock will be restarted for this module only, without waking the system from Power Save Mode. The clock remains active only as long as required by the triggered function, before being switched off again, and the system remains in the original sleep mode. The CPU and system will only be woken up if the user peripheral generates an interrupt as a result of the operation. This concept is known as SleepWalking™ and is described in further detail in Section 10. ”Power Manager (PM)” on page 109. Note that asynchronous peripheral events may be associated with a delay due to the need to restart the system clock source if this has been stopped in the sleep mode. Refer to the Module Configuration section at the end of this chapter for the device-specific configuration, especially on which peripheral event generators and users can rely on SleepWalking™. The table and diagram below represent the timed behavior of SleepWalking™ operations: Table 31-2. SleepWalking™ on Peripheral Events Phase Operation 1 while in a Power Save Mode where peripheral clocks are asleep, asynchronous Generator j sends Peripheral Event to PEVC 2 incoming Event is detected by EVS j , and CLK_PEVC requested to PM 3 upon reception of clock request, PM wakes clock sources if required 4 CLK_PEVC wakes up 847 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 31-2. SleepWalking™ on Peripheral Events Phase Operation incoming Event j propagates to Channel i: • CLK_USER i request to PM 5 • TRIG i forwarded to User i 6 CLK_USER i wakes up 7 User i handles the incoming Peripheral Event and signals it to PEVC 8 depending on the Peripheral’s operation, a CPU wake request occurs in case of Interrupt processing 9 alternatively, the Peripheral may simply go back to sleep, in which case PM will silently shut off CLK_USER i and CLK_PEVC Figure 31-3. SleepWalking™ on Peripheral Events Power Manager Wake Clock Sources Wake CPU 8 IRQ USER i 3 CLK_PEVC CLK_USER i 6 2 5 PEVC 4 TRIG i 1 Generator j 31.5.3 EVT j EVS j Channel i 7 5 RDY i CLK_USER i User i Clocks The PEVC has two clocks connected: one Peripheral Bus clock (CLK_PEVC) and the system RC oscillator clock (CLK_RCSYS). These clocks are generated by the Power Manager. CLK_PEVC is required for event propagation and Peripheral Bus operations. CLK_RCSYS is used for glitch filtering in Event Shapers. It is required for event propagation in case glitch filtering is turned on for a given generator. 848 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.5.4 Interrupts PEVC can generate an interrupt request in case of trigger generation or trigger overrun. The PEVC interrupt request lines are connected to the NVIC. Using the PEVC interrupts requires the NVIC to be programmed first. 31.5.5 Debug Operation PEVC is not frozen during debug operation when the Core is halted, unless the bit corresponding to the PEVC is set in the Peripheral Debug Register (PDBG). Refer to the On-Chip Debug chapter for details. 849 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.6 Functional Description 31.6.1 31.6.1.1 PEVC Channel Operation PEVC routes incoming events to users by means of one channel per user. Channels operate in parallel, allowing multiple users to listen to the same generator. Channel Setup The Channel Multiplexer Register (CHMXi) is written to allocate a generator to a given channel. The Event Multiplexer field (EVMX) selects between the different generators, while the Software Event Multiplexer bit (SMX) selects Software Events. The channel is then enabled by writing a one to the appropriate bit in the Channel Enable Register (CHER). It is disabled by writing a one to the appropriate bit in the Channel Disable Register (CHDR). To safely configure a channel, user software must: • disable the channel by writing a one to CHDR • configure CHMXi • enable the channel by writing a one to CHER 31.6.1.2 Channel Operation When the channel is enabled, the user signals its busy/ready state to the channel, to determine how an incoming event will be handled: • If the user is ready, an incoming event is forwarded. The corresponding Trigger Status Register (TRISR) bit is set to one allowing an interrupt to be generated for tracking PEVC operations. • If the user is busy (because of a previous event, or for some other cause), the new event is not forwarded. The corresponding Overrun Status Register (OVSR) flag is set allowing an interrupt to be generated. The Busy Register (BUSY) is used to determine the current activity of a channel/user. A busy status has one of two causes: • A peripheral event is being relayed by the channel and handled by the user, • No event relayed, but user is not ready (e.g. not initialized, or handling some other request). 31.6.1.3 Software Event A Software Event can be initiated by writing to the Software Event Register (SEV). This is intended for application debugging. The channel must first be configured by writing a one to the Software Event Multiplexer bit (SMX) of CHMXi. Writing a one to the appropriate bit of SEV will then trigger a Software Event on the channel. 850 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.6.2 Event Shaper (EVS) Operation PEVC contains Event Shapers (EVS) for certain types of generators: • External inputs • General-purpose waveforms like timer outputs or Generic Clocks Refer to the Module Configuration section at the end of this chapter for the device-specific configuration of Event Shapers and Input Glitch Filters. Each Event Shaper is responsible of shaping one input, prior to going through a PEVC channel: • Optionally apply input-glich-filtering • Synchronize incoming events • Request CLK_PEVC when in deeper sleep modes Write a one to the EN field of the corresponding Event Shaper Register (EVS) to enable operation. 31.6.2.1 Input Glitch Filter (IGF) Input Glitch Filtering can be turned on or off by writing to the Input Glitch Filter fields (IGFR and IGFF) of the corresponding Event Shaper Register (EVS). When IGF is on, the incoming event is sampled periodically. The sampling clock is divided from CLK_RCSYS by the value of the Input Glitch Filter Divider Register (IGFDR). IGF will filter out spikes and propagate only incoming events that respect one of the following two conditions: • rise event: 2 samples low, followed by 0+ changes, followed by 2 samples high • fall event: 2 samples high, followed by 0+ changes, followed by 2 samples low CLK_RCSYS must be enabled to use Input Glitch Filtering. 31.6.3 Event Propagation Latency Once a channel is setup, incoming peripheral events are relayed by hardware. Event progation latency is therefore cycle deterministic. However, its value depends on the exact settings that apply to a given channel. When the channel multiplexer CHMXi.EVMX selects a generator without Event Shaper, event propagation latency is 0 cycle. Software event is a particular case of 0 cycle propagation. When the channel multiplexer CHMXi.EVMX selects a generator with Event Shaper, event propagation latency depends on Input Glitch Filter setting EVSj.IGF and SleepWalking™: • IGF off: event propagation latency is less or equal to 2 CLK_PEVC cycles • IGF on: event propagation latency is less or equal to 3 * 2IGFDR * CLK_RCSYS cycles • in case of SleepWalking™ operation, an additional delay incurs if the PM needs to revive the clocks sources. In that particular case of Low-Power operation, propagation latency is longer and cannot be predicted. 851 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 31-3. Event Propagation Latency Generator CHMXi.EVMX Input Glitch Filter EVSj.IGF Latency Clock Software event - 0 - Generator without Event Shaper - 0 - Generator with Event Shaper Off 2 Generator with Event Shaper Asynchronous Generator in SleepWalking™ operation CLK_PEVC IGFDR On 3*2 On or Off unpredicted CLK_RCSYS - Refer to the Module Configuration section at the end of this chapter for the list of generators implementing Event Shapers. 31.7 Application Example This application example shows how the Peripheral Event System can be used to program the ADC Interface to perform ADC conversions at selected intervals. One of the possible ADC conversion trigger is a peripheral event trigger, allowing the Peripheral Event System to synchronize conversion with some configured peripheral event source. One particular peripheral event source can be an AST peripheral event, among other types of peripheral events. The Peripheral Event System can then be used to set up the ADC Interface to sample an analog signal at regular intervals generated by the AST. The user must enable peripheral events in the AST and in the ADC Interface. Refer to the corresponding chapters for how this is accomplished. Next, the AST will generate peripheral events periodically, and the Peripheral Event System will route the peripheral events to the ADC Interface, which will perform ADC conversions at the selected intervals. Figure 31-4. Application Example Trigger Periodic peripheral conversion Peripheral event AST Event System ADC Interface Since the AST peripheral event is an asynchronous event, the description above will also work in Power Save Modes where the ADC clock is stopped. In this case, the ADC clock (and clock source, if needed) will be restarted during the ADC conversion. After the conversion, the ADC clock and clock source will return to the sleep state, unless the ADC generates an interrupt, which in turn will wake up the system. Using asynchronous events thus allows ADC operation in much lower power states than would otherwise be possible. 852 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8 User Interface Table 31-4. Notes: PEVC Register Memory Map Offset Register Register Name Access Reset 0x000 Channel Status Register CHSR Read-only 0x00000000 0x004 Channel Enable Register CHER Write-only - 0x008 Channel Disable Register CHDR Write-only - 0x010 Software Event SEV Write-only (1) 0x014 Channel / User Busy BUSY Read-only - 0x020 Trigger Interrupt Mask Enable Register TRIER Write-only - 0x024 Trigger Interrupt Mask Disable Register TRIDR Write-only - 0x028 Trigger Interrupt Mask Register TRIMR Read-only 0x00000000 0x030 Trigger Status Register TRSR Read-only 0x00000000 0x034 Trigger Status Clear Register TRSCR Write-only - 0x040 Overrun Interrupt Mask Enable Register OVIER Write-only - 0x044 Overrun Interrupt Mask Disable Register OVIDR Write-only - 0x048 Overrun Interrupt Mask Register OVIMR Read-only 0x00000000 0x050 Overrun Status Register OVSR Read-only 0x00000000 0x054 Overrun Status Clear Register OVSCR Write-only - 0x100 Channel Multiplexer 0 CHMX0 Read/Write 0x00000000 0x100 + i*4 Channel Multiplexer i CHMXi Read/Write 0x00000000 0x17C Channel Multiplexer 31 CHMX31 Read/Write 0x00000000 0x200 Event Shaper 0 EVS0 Read/Write 0x00000000 0x200 + j*4 Event Shaper j EVSj Read/Write 0x00000000 0x2FC Event Shaper 63 EVS63 Read/Write 0x00000000 0x300 Input Glitch Filter Divider Register IGFDR Read/Write 0x00000000 0x3F8 Parameter PARAMETER Read-only -(1) 0x3FC Version VERSION Read-only -(1) 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter. 853 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.1 Name: Channel Status Register CHSR Access Type: Read-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHS 23 22 21 20 CHS 15 14 13 12 CHS 7 6 5 4 CHS • CHS: Channel Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. This bit is cleared when the corresponding bit in CHDR is written to one. This bit is set when the corresponding bit in CHER is written to one. 854 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.2 Name: Channel Enable Register CHER Access Type: Write-only Offset: 0x004 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHE 23 22 21 20 CHE 15 14 13 12 CHE 7 6 5 4 CHE • CHE: Channel Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in CHSR. 855 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.3 Name: Channel Disable Register CHDR Access Type: Write-only Offset: 0x008 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHD 23 22 21 20 CHD 15 14 13 12 CHD 7 6 5 4 CHD • CHD: Channel Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in CHSR. 856 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.4 Name: Software Event Register SEV Access Type: Write-only Offset: 0x010 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEV 23 22 21 20 SEV 15 14 13 12 SEV 7 6 5 4 SEV • SEV: Software Event Writing a zero to this bit has no effect. Writing a one to this bit will trigger a Software Event for the corresponding channel. 857 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.5 Name: Channel / User Busy BUSY Access Type: Read-only Offset: 0x014 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUSY 23 22 21 20 BUSY 15 14 13 12 BUSY 7 6 5 4 BUSY • BUSY: Channel Status 0: The corresponding channel and user are idle. 1: The corresponding channel and user are busy. 858 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.6 Name: Trigger Interrupt Enable Register TRIER Access Type: Write-only Offset: 0x020 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIE 23 22 21 20 TRIE 15 14 13 12 TRIE 7 6 5 4 TRIE • TRIE: Trigger Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in TRIMR. 859 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.7 Name: Trigger Interrupt Disable Register TRIDR Access Type: Write-only Offset: 0x024 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRID 23 22 21 20 TRID 15 14 13 12 TRID 7 6 5 4 TRID • TRID: Trigger Interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. 860 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.8 Name: Trigger Interrupt Mask Register TRIMR Access Type: Read-only Offset: 0x028 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIM 23 22 21 20 TRIM 15 14 13 12 TRIM 7 6 5 4 TRIM • TRIM: Trigger Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in TRIDR is written to one. This bit is set when the corresponding bit in TRIER is written to one. 861 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.9 Name: Trigger Status Register TRSR Access Type: Read-only Offset: 0x030 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRS 23 22 21 20 TRS 15 14 13 12 TRS 7 6 5 4 TRS • TRS: Trigger Interrupt Status 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in TRSCR. 862 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.10 Name: Trigger Status Clear Register TRSCR Access Type: Write-only Offset: 0x034 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRSC 23 22 21 20 TRSC 15 14 13 12 TRSC 7 6 5 4 TRSC • TRSC: Trigger Interrupt Status Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in TRSR. 863 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.11 Name: Overrun Interrupt Enable Register OVIER Access Type: Write-only Offset: 0x040 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVIE 23 22 21 20 OVIE 15 14 13 12 OVIE 7 6 5 4 OVIE • OVIE: Overrun Interrupt Enable Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in OVIMR. 864 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.12 Name: Overrun Interrupt Disable Register OVIDR Access Type: Write-only Offset: 0x044 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVID 23 22 21 20 OVID 15 14 13 12 OVID 7 6 5 4 OVID • OVID: Overrun Interrupt Disable Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. 865 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.13 Name: Overrun Interrupt Mask Register OVIMR Access Type: Read-only Offset: 0x048 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVIM 23 22 21 20 OVIM 15 14 13 12 OVIM 7 6 5 4 OVIM • OVIM: Overrun Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in OVIDR is written to one. This bit is set when the corresponding bit in OVIER is written to one. 866 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.14 Name: Overrun Status Register OVSR Access Type: Read-only Offset: 0x050 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVS 23 22 21 20 OVS 15 14 13 12 OVS 7 6 5 4 OVS • OVS: Overrun Interrupt Status 0: An interrupt event has not occurred 1: An interrupt event has occurred This bit is cleared by writing a one to the corresponding bit in OVSCR. 867 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.15 Name: Overrun Status Clear Register OVSCR Access Type: Write-only Offset: 0x054 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 OVSC 23 22 21 20 OVSC 15 14 13 12 OVSC 7 6 5 4 OVSC • OVSC: Overrun Interrupt Status Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in OVSR. 868 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.16 Name: Channel Multiplexer Register CHMXi Access Type: Read/Write Offset: 0x100 + i*0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - SMX 7 6 5 4 3 2 1 0 - - EVMX • SMX: Software Event Multiplexer 0: The Software Event is not selected. Event / generator is selected by EVMX. 1: The Software Event is selected. EVMX is not considered. • EVMX: Event Multiplexer Select input event / generator. SMX EVMX Channel Input 1 Any Software Event 0 0x00 EVT0 0 0x01 EVT1 0 0xj EVTj 0 > TRIGOUT None 869 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.17 Name: Event Shaper Register EVSj Access Type: Read/Write Offset: 0x200 + j*0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - IGFON IGFF IGFR 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - EN • IGFON: Input Glitch Filter Status 0: Input Glitch Filter is off. 1: Input Glitch Filter is on. Only present when IGF is used. Refer to the Module Configuration section at the end of this chapter. To enable Input Glitch Filtering, EN bit must be set to 1, as well as one of IGFF or IGFR. This bit is Read-only, and can be used to detect that configuration is effective. It incurs some delay compared to the writing of IGFF, IGFR, or EN. • IGFF: Input Glitch Filter Fall 0: No event detection on falling edge. 1: Event detection through Input Glitch Fiilter on falling edge. Only present when IGF is used. Refer to the Module Configuration section at the end of this chapter. To enable Input Glitch Filtering, EN bit must also be set to 1. Both IGFF and IGFR can be combined. • IGFR: Input Glitch Filter Rise 0: No event detection on rising edge. 1: Event detection through Input Glitch Fiilter on rising edge. Only present when IGF is used. Refer to the Module Configuration section at the end of this chapter. To enable Input Glitch Filtering, EN bit must also be set to 1. Both IGFF and IGFR can be combined. • EN: Event Shaper Enable 0: Event Shaper is off. 1: Event Shaper is on. To enable Input Glitch Filtering, IGFR and/or IGFF must also be set to 1. 870 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.18 Name: Input Glitch Filter Divider Register IGFDR Access Type: Read/Write Offset: 0x300 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - IGFDR • IGFDR: Input Glitch Filter Divider Selects prescaler division ratio for the system RC clock used for glitch filtering. IGFDR Division Ratio 0x0 1 0x1 2 0x2 4 0xn 2n 0xF 32768 871 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.19 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x3F8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TRIGOUT 23 22 21 20 EVIN 15 14 13 12 EVS_COUNT 7 6 5 4 IGF_COUNT • TRIGOUT: Number of Trigger Outputs / Channels / Users Number of trigger outputs / channels implemented. No functionality associated. • EVIN: Number of Event Inputs / Generators Number of event inputs. No functionality associated. • EVS_COUNT: Number of Event Shapers Number of Event Shapers implemented. No functionality associated. • IGF_COUNT: Number of Input Glitch Filters Number of Input Glitch Filters implemented. No functionality associated. 872 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.8.20 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Variant number of the module. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 873 42023H–SAM–11/2016 ATSAM4L8/L4/L2 31.9 Module Configuration The specific configuration for each PEVC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. “Power Manager (PM)” on page 109 for details. Table 31-5. Module Clock Name Module name Clock name PEVC CLK_PEVC The module Register Reset Values are listed below. Table 31-6. Register Reset Values Register Reset Value VERSION 0x00000200 PARAMETER 0x131F1204 BUSY 0x0002401F The following table defines generators and input events connected to the Peripheral Event System. It also specifies whether Event Shaper and Input Glitch Filter are implemented for this generator, and if SleepWalking is available. Table 31-7. Generators CHMXn.EVMX Generator - input event IGF EVS SleepWalking 0 PAD_EVT 0 - change on input pin Yes Yes Yes 1 PAD_EVT 1 - change on input pin Yes Yes Yes 2 PAD_EVT 2 - change on input pin Yes Yes Yes 3 PAD_EVT 3 - change on input pin Yes Yes Yes 4 GCLK 8 - rising edge Yes 5 GCLK 9 - rising edge Yes 6 AST - alarm event 0 Yes Yes 7 Reserved 8 AST - periodic event 0 Yes Yes 9 Reserved 10 AST - overflow event Yes Yes 11 ACIFC - AC0 VINP>VINN 12 ACIFC - AC1 VINP>VINN 13 ACIFC - AC2 VINP>VINN 14 ACIFC - AC3 VINP>VINN 15 ACIFC - AC0 VINP VACAPx • ACWOUT = 0 if the window mode output is not available (SR.ACRDYx=0 or SR.ACRDYx+1=0) The Windowx Mode Current Status bit in SR (SR.WFCSx) gives the comparison status of the window pair. 37.6.5.2 Window Mode Interrupts When operating in window mode, each AC can generate the same interrupt as in normal mode, see Section 37.6.4.2. Additionally, when ACs operate in window mode, a third type of interrupt based on ACWOUT can be generated (bit ISR.WFINTx). Writing to Window Mode Interrupt Settings in Windowx Mode Configuration Register (CONFWx.WIS) selects an interrupt source: • As soon as the common input voltage is inside the window. • As soon as the common input voltage is outside the window. 976 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • On toggle of the window compare output (ACWOUT). • When the comparison in both ACs in the window mode is ready. • When the common input voltage enters the window (i.e., rising-edge of ACWOUT). • When the common input voltage leaves the window (i.e., falling-edge of ACWOUT). 37.6.5.3 Window Mode Peripheral Events When operating in window mode, each AC can generate the same peripheral events as in normal mode, see Section 37.6.4.3. Additionally, user enables generation of window peripheral events by writing a one to the Window Peripheral Event Enable bit (CONFWx.WFEN). Writing to Window Mode Peripheral Event Selection Source (CONFWx.WEVSRC) selects the peripheral events source: • As soon as the common input voltage is inside the window. • As soon as the common input voltage is outside the window. • On toggle of the window compare output (ACWOUT) • Whenever a comparison is ready and the common input voltage is inside the window. • Whenever a comparison is ready and the common input voltage is outside the window. • When the comparison of both ACs in the window mode is ready. 37.6.6 Analog Hysteresis Control The user can select the hysteresis voltage used by each AC to reduce noise in its output. As shown in Figure 37-3, the output of the AC switches from zero to one when the differential voltage VD (= VINP - VINN) is greater than (hysteresis voltage / 2) and switches from one to zero when VD is less than (hysteresis voltage / 2). The hysteresis voltage for each AC is selected by writing to the Hysteresis Voltage field in the CONFx register (CONFx.HYS), as shown in Table 37-3. Figure 37-3. Hysteresis Voltage ACOUT VDD Hysteresis Voltage VD = VINP – VINN Table 37-3. Hysteresis Voltage Selection CONFx.HYS Hysteresis Voltage (mV) 0 0 1 25 2 50 3 75 977 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.6.7 Power Dissipation and Speed Trade-off ACIFC is able to control whether an AC operates in fast or low-power mode, allowing a trade-off between its active power dissipation and speed. The desired mode is selected by writing to the FAST bit in the CONFx register (CONFx.FAST). When CONFx.FAST is zero (default), the corresponding AC operates in low-power mode. When CONFx.FAST is one, it operates in fast mode. In low-power mode, the AC dissipates significantly less active power than when it is in fast mode, but has a longer start-up time and propagation delay. Refer to Section 42. “Electrical Characteristics” on page 1121 for details. 37.6.8 Wake Up from Sleep Modes by Interrupt An AC is able to wake up the system from a sleep mode by its interrupt, including sleep modes where CLK_ACIFC is stopped. For an AC to wake up the system, the user must follow this procedure before the system enters a sleep mode: • Set AC in the Continuous Measurement mode (CONFx.MODE). • Set the AC’s interrupt setting (CONFx.IS =2) so that it generates an interrupt on the toggling of the corresponding AC output. • Wait for AC to be ready (SR.ACRDYx = 1). Once ACIFC detects a transition on the relevant AC output, it sends a request to Power Manager for CLK_ACIFC to restart (the corresponding bit in the Power Manager Peripheral Power Control Register (PPCR) must be set) and sets the corresponding interrupt status bit in ISR after CLK_ACIFC has restarted. Note that in order for the interrupt from ACIFC to wake up the system, the ACIFC bit in the Power Manager Asynchronous Wake Up Enable Register (AWEN) must be set. 37.7 Peripheral Event Triggers Peripheral events from other modules can trigger comparisons in the ACIFC. All ACs that are configured in peripheral event triggered single measurement mode will be started simultaneously when a peripheral event is received. ACs operating in continuous measurement mode or user triggered single measurement mode are unaffected by the received peripheral event. Software can still operate these ACs independently of ACs in peripheral event triggered single measurement mode. A peripheral event will trigger one or more comparisons, in normal or window mode. 37.8 AC Test mode By writing a one to the Analog Comparator Test Mode bit (CR.ACTEST), the outputs from the ACs are overridden by the value in the Test Register (TR), see Figure 37-1. This can be useful for software tests. 978 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9 User Interface Table 37-4. ACIFC Register Memory Map Offset Register Register Name Access Reset 0x00 Control Register CTRL Read/Write 0x00000000 0x04 Status Register SR Read-only 0x00000000 0x10 Interrupt Enable Register IER Write-only 0x00000000 0x14 Interrupt Disable Register IDR Write-only 0x00000000 0x18 Interrupt Mask Register IMR Read-only 0x00000000 0x1C Interrupt Status Register ISR Read-only 0x00000000 0x20 Interrupt Status Clear Register ICR Write-only 0x00000000 0x24 Test Register TR Read/Write 0x00000000 0x30 Parameter Register PARAMETER Read-only -(1) 0x34 Version Register VERSION Read-only -(1) 0x80 Window0 Configuration Register(2) CONFW0 Read/Write 0x00000000 0x84 Window1 Configuration Register(2) CONFW1 Read/Write 0x00000000 0x88 Window2 Configuration Register (2) CONFW2 Read/Write 0x00000000 0x8C Window3 Configuration Register (2) CONFW3 Read/Write 0x00000000 0xD0 AC0 Configuration Register(2) CONF0 Read/Write 0x00000000 0xD4 AC1 Configuration Register(2) CONF1 Read/Write 0x00000000 0xD8 AC2 Configuration Register (2) CONF2 Read/Write 0x00000000 0xDC AC3 Configuration Register (2) CONF3 Read/Write 0x00000000 0xE0 AC4 Configuration Register(2) CONF4 Read/Write 0x00000000 0xE4 AC5 Configuration Register(2) CONF5 Read/Write 0x00000000 0xE8 AC6 Configuration Register (2) CONF6 Read/Write 0x00000000 AC7 Configuration Register (2) CONF7 Read/Write 0x00000000 0xEC Note: 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter. 2. Number of AC and AC pair is device specific therefore associated register may not exist. 979 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACTEST - ESTART USTART - - EVENTEN EN • ACTEST: Analog Comparator Test Mode 0: The Analog Comparator outputs are connected to the logic in ACIFC. 1: The Analog Comparator outputs are bypassed with the AC Test Register. • ESTART: Peripheral Event Start Single Comparison Writing a zero to this bit has no effect. Writing a one to this bit starts a comparison and can be used for test purposes. This bit is cleared when comparison is done. This bit is set when an enabled peripheral event is received. • USTART: User Start Single Comparison Writing a zero to this bit has no effect. Writing a one to this bit starts a single comparison. This bit is cleared when comparison is done. • EVENTEN: Peripheral Event Trigger Enable 0: A peripheral event will not trigger a comparison. 1: Enable comparison triggered by a peripheral event. • EN: ACIFC Enable 0: The ACIFC is disabled. 1: The ACIFC is enabled. 980 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.2 Name: Status Register SR Access Type: Read-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFCS3 WFCS2 WFCS1 WFCS0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 ACRDY7 ACCS7 ACRDY6 ACCS6 ACRDY5 ACCS5 ACRDY4 ACCS4 7 6 5 4 3 2 1 0 ACRDY3 ACCS3 ACRDY2 ACCS2 ACRDY1 ACCS1 ACRDY0 ACCS0 • WFCSx: Windowx Mode Current Status This bit is cleared when the common input voltage is outside the window. This bit is set when the common input voltage is inside the window. • ACRDYx: ACx Ready This bit is cleared when the AC output (ACOUT) is not ready. This bit is set when the AC output (ACOUT) is ready, AC is enabled and its startup time is over. • ACCSx: ACx Current Comparison Status This bit is cleared when VINP is currently lower than VINN This bit is set when VINP is currently greater than VINN. 981 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 982 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 983 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 984 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.6 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 • WFINTx: Windowx Mode Interrupt Status 0: No Window mode interrupt is pending. 1: Window mode interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding ACs pair operating in window mode generates an interrupt (see CONFWx to select the source). • SUTINTx: ACx Startup Time Interrupt Status 0: No Startup Time Interrupt is pending. 1: Startup Time Interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the startup time of the corresponding AC is over. • ACINTx: ACx Interrupt Status 0: No normal mode interrupt is pending. 1: Normal mode interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding AC generates an interrupt (see CONFx to select the source). 985 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.7 Name: Interrupt Status Clear Register ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 986 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.8 Name: Test Register TR Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACTEST7 ACTEST6 ACTEST5 ACTEST4 ACTEST3 ACTEST2 ACTEST1 ACTEST0 • ACTESTx: ACx Output Override Value 0: Normal operating mode. 1: If CTRL.ACTEST is one, ACx output is the bit value ACTESTx. 987 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.9 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - WIMPL3 WIMPL2 WIMPL1 WIMPL0 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACIMPL7 ACIMPL6 ACIMPL5 ACIMPL4 ACIMPL3 ACIMPL2 ACIMPL1 ACIMPL0 • WIMPLx: Window x Mode Implemented 0: Window x mode is not implemented. 1: Window x mode is implemented. • ACIMPLx: Analog Comparator x Implemented 0: Analog Comparator x is not implemented. 1: Analog Comparator x is implemented. 988 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 989 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.11 Name: Windowx Configuration Register CONFWx Access Type: Read/Write Offset: 0x80,0x84,0x88,0x8C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - WFEN 15 14 13 12 11 10 9 8 - - - - WEVEN 7 6 5 4 3 - - - - - WEVSRC 2 1 0 WIS • WFEN: Window Mode Enable 0: Window mode is disabled. 1: Window mode is enabled. • WEVEN: Window Peripheral Event Enable 0: Peripheral event from ACWOUT is disabled. 1: Peripheral event from ACWOUT is enabled. 990 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • WEVSRC: Peripheral Event Source Selection for Window Mode WEVSRC Peripheral Source Selection 0 0 0 ACWOUT rising edge 0 0 1 ACWOUT falling edge 0 1 0 ACWOUT rising or falling edge 0 1 1 Inside window 1 0 0 Outside window 1 0 1 Measure done 1 1 0 Reserved 1 1 1 Reserved • WIS: Window Mode Interrupt Settings WIS Interrupt Settings 0 0 0 Window interrupt as soon as the common input voltage is inside the window 0 0 1 Window interrupt as soon as the common input voltage is outside the window 0 1 0 Window interrupt on toggle of ACWOUT 0 1 1 Window interrupt when evaluation of common input voltage is done 1 0 0 Window interrupt when the common input voltage enters the window (i.e., rising-edge of ACWOUT) 1 0 1 Window interrupt when the common input voltage leaves the window (i.e., falling-edge of ACWOUT) 1 1 0 Reserved 1 1 1 Reserved 991 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.9.12 Name: ACx Configuration Register CONFx Access Type: Read/Write Offset: 0xD0,0xD4,0xD8,0xDC,0xE0,0xE4,0xE8,0xEC Reset Value: 0x00000000 24 31 30 29 28 27 26 - - - - ALWAYSON FAST 23 22 21 20 19 18 17 16 - - - - - - EVENP EVENN 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - - - - MODE 25 HYS INSELN 0 1 IS • ALWAYSON: Always On 0: AC is disabled between measurements 1: AC is always enabled • FAST: Fast Mode Enable This bit controls whether the AC operates in fast or low-power mode, thus allowing a trade-off between its active power dissipation and speed (i.e., startup time and propagation delay): 0: Low-power mode 1: Fast mode Refer to Section 42. “Electrical Characteristics” on page 1121 for details on the current consumption, start-up time, and propagation delay of the AC when it is in either of these modes. • HYS: Hysteresis Voltage Value. HYS Hysteresis value 0 0 Hysteresis voltage = 0 mV 0 1 Hysteresis voltage = 25 mV 1 0 Hysteresis voltage = 50 mV 1 1 Hysteresis voltage = 75 mV • EVENN: Peripheral Event Enable Negative 0: Do not output peripheral event when ACOUT is zero. 1: Output peripheral event when ACOUT is zero. • EVENP: Peripheral Event Enable Positive 0: Do not output peripheral event when ACOUT is one. 1: Output peripheral event when ACOUT is one. • INSELN: Negative Input Select See CONFx.INSELN: Negative Input Select table in Module Configuration section. 992 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • MODE: Analog Comparator Mode MODE Mode selected 0 0 Off 0 1 Continuous measurement mode 1 0 User triggered single measurement mode 1 1 Peripheral event triggered single measurement mode • IS: Interrupt Settings IS Interrpt setting 0 0 When VINP > VINN 0 1 When VINP < VINN 1 0 On toggle of ACOUT 1 1 When comparison of VINP and VINN is done 993 42023H–SAM–11/2016 ATSAM4L8/L4/L2 37.10 Module configuration The specific configuration for each ACIFC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 37-5. ACIFC Configuration Feature ACIFC AC_NO 8 ACW_NO 4 Table 37-6. ACIFC Clocks Clock Name Description CLK_ACIFC Clock for the ACIFC bus interface Table 37-7. INSELN CONFx.INSELN: Negative Input Select Input selected 0 0 ACANx (ACBNx) pin selected 0 1 Reserved 1 0 Reserved 1 1 Reserved Table 37-8. Register Reset Values Register Reset Value VERSION 0x00000100 PARAMETER 0x0003000F 994 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38. ADC Interface (ADCIFE) Rev. 1.0.0.0 38.1 Features • • • • • • • • • • 38.2 Multi-channel Analog-to-Digital Converter with 12-bit resolution Selectable single ended or differential input voltage Programmable gain per conversion selectable ADC voltage input reference per conversion Numerous trigger sources – Software – Embedded 16-bit timer for periodic trigger – Continuous trigger – Peripheral Event trigger – External trigger, rising, falling or any-edge trigger Multiple sequencer modes: – Run multiple sequences using DMA transfer – Run a single conversion on a start-of-conversion Start of conversion or sequence without CPU intervention ADC Power Reduction Mode for low power ADC applications Window monitor, with selectable channel per conversion Programmable Sample & Hold time per conversion Overview The ADC interface (ADCIFE) converts analog input voltages to digital values. The ADCIFE is based on a 12-bit Cyclic Pipeline topology to achieve sampling rates up to 300 KSPS (In differential mode without gain). The ADC conversion results are reported in a common register for all channels. Conversions can be started for all enabled channels, either by a software trigger, by detection of a level change on the external trigger pin or event system, or by an integrated programmable 16-bit timer. This ADC has selectable single-ended or fully differential inputs and takes benefits from a programmable gain from x0.5 to x64 included. The conversions extend from -Vref to +Vref. 16 external channels on both positive and negative inputs can be managed. The ADCIFE also integrates an Power Reduction mode, a Window Monitor mode, and connects with two Peripheral DMA Controller channels (One Rx for configuration and one Tx for transfering results). These features reduce both power consumption and processor intervention. 995 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.3 Block diagram Figure 38-1. ADCIFE Block Diagram A D C IF E T im e r T rig g e r/P E V C S o u rc e s T rig g e r S e le c tio n Sequencer C L K _ A D C IF E ADVREFP G CLK GNDREF R e fe re n c e B u ffe r Bandgap D M A re q u e s t AD2 GPIO Controller AD1 ADn 38.4 Neg Analog mux AD0 Pos Analog mux E x te rn a l R e f. U ser In te rfa c e A d c ife _ p e v c _ e o c 1 2 -b it C y c lic P ip e lin e ADC CORE A d c ife _ p e v c _ w m C L K _ A D C IF E I/O Lines decription table Name AD0-AD14 Description Type Analog input channels Analog 2 External Voltage References Analog A33VDD Analog power supply Power A33GND Analog ground Power ADTRG External trigger Digital External Ref. 38.5.1 P e rip h e ra l B u s I/O Lines Description Table 38-1. 38.5 In te rru p t R e q u e s t C lo c k G e n e ra to r Product dependencies I/O Lines The pins used for interfacing the ADCIFE may be multiplexed with I/O Controller lines. The programmer must first program the I/O controller to assign the desired ADCIFE pins to their 996 42023H–SAM–11/2016 ATSAM4L8/L4/L2 peripheral function. If I/O lines of the ADCIFE are not used by the application, they can be used for other purposes by the I/O controller. 38.5.2 Power Management If the CPU enters a power reduction mode that disables clocks used by the ADCIFE, the ADCIFE will stop functioning and resume operation after the system wakes up from power reduction mode. Before entering a power reduction mode where the clock to the ADCIFE is stopped, make sure the Analog-to-Digital Converter cell is put in an inactive state. If an event is sent to the ADCIFE and the clocks used by the ADCIFE are stopped, the ADCIFE clock will automatically be requested so that the conversion can be processed. 38.5.3 Clocks The clock for the ADCIFE bus interface (CLK_ADCIFE) is generated by the Power Manager. This clock is disabled at reset, and can be enabled/disabled in the Power Manager. It is recommended to disable the ADCIFE before disabling the clock, to avoid freezing the ADCIFE in an undefined state. Additionally, the ADCIFE depends on a dedicated Generic Clock (GCLK). The GCLK can be set to a wide range of frequencies and clock sources, and must be enabled by the System Control Interface (SCIF) before the ADCIFE can be used. This GCLK can also be muxed with the CLK_ADCIFE clock by writting the Clock Selection bit in the Configuration Register (CFG.CLKSEL). It is used during the sleep walking mode. 38.5.4 Interrupt Controller The ADCIFE interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADCIFE requires the Interrupt Controller to be programmed first. 38.5.5 Event System The event controller provides the ADCIFE a trigger source. The ADCIFE also behaves as an event source: • Event on an end of conversion (Figure 38-1 adcife_pevc_eoc signal) • Event on a window monitor trigger (Figure 38-1 adcife_pevc_wm signal) To operate correctly, the event source period should not exceed the ADC conversion time plus the startup time if needed. Refer to the Peripheral Event System chapter for details. 38.6 38.6.1 Section 42. ”Electrical Characteristics” on page 1121Functional Description Initializing the ADCIFE To initialize the module the user first needs to configure the ADCIFE clocks (refer to Section 38.5.3). Then he needs to wait for the STARTUP time (Refer to Section 38.6.7) (If necessary). Then he can write a one to the Enable (EN) bit in the Control Register (CR). The user must check that ADCIFE has started correctly, firstly by checking that the Enable bit (EN) located in the Status Register (SR) is set. The Bandgap Buffer Request bit in the Control register (CR.BGREQEN) and the Reference Buffer Enable in the Control register (CR.REFBUFEN) must be set. If the reference buffer of the ADC cell is enabled and ready for use, SR.EN can tell if the ADCIFE is ready for operation since startup-time will be performed only when a sequencer trigger event occurs if necessary. 997 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Note that all ADCIFE controls will be ignored until SR.EN goes to ‘1’. Before the ADCIFE can be used, the Internal Reference Voltage signal must be selected by writing the CFG.REFSEL field and the I/O Controller must be configured correctly. Refer to I/O Controller section for details. The user must also configure the frequency range by writting the CFG.SPEED field. Note that once configured, ADCIFE configuration registers should not be written during operation since they are permanently used by the ADCIFE. The user must ensure that ADCIFE is stopped during configuration unless he knows what he is doing. 38.6.2 Basic Operation To convert analog values to digital values the user must first initialize the ADCIFE as described in Section 38.6.1. When the ADCIFE is initialized, the sequencer must be configured by writing into the Sequencer Configuration Register (SEQCFG) all the necessary bits or fields for the next conversion. This configuration can also be performed by Peripheral DMA Rx channel access. Configuring channel N for a given conversion instructs the ADCIFE to convert the analog voltage applied to AD pin N. To start converting data the user can either manually start a conversion sequence by write a one to the sequencer trigger event (STRIG) bit in the Control Register (CR) or configure an automatic trigger to initiate the conversions. The automatic trigger can be configured to trig on many different conditions. Refer to Section 38.6.13 for details. The result of the conversions are stored in the Last Converted Value register (LCV) as they become available, overwriting the result from the previous conversion. To avoid data loss, the user must read the conversion results as they become available either by using an interrupt handler or by using a Peripheral DMA channel to copy the results to memory. Failing to do so will result in an Overrun Error condition, indicated by the LOVR bit in the Status Register (SR). To use an interrupt handler the user must enable the End Of Conversion (EOC) interrupt request by writing a one to the corresponding bit in the Interrupt Enable Register (IER). To clear the interrupt after the conversion result is read, the user must write a one to the corresponding bit in the Status Clear Register (SCR). To use a Peripheral DMA Controller Tx channel, the user must configure the Peripheral DMA Controller appropriately. The DMA Controller will, when configured, automatically read converted data as they become available. There is no need to manually clear any bits in the Interrupt Status Register as this is performed by the hardware. If an Overrun Error condition happens during DMA operation, the LOVR bit in the SR will be set. 38.6.3 ADC Resolution This ADC is a cyclic pipeline 12-bit or 8-bit resolution. Resolution can be changed by writing the resolution field (RES) in the Sequencer Configuration Register (SEQCFG). By default, after a reset, the resolution is set to 12-bit. 38.6.4 Differential and Single-Ended Conversion Modes The ADC has two conversion modes; differential and single-ended. If measuring signals where the positive input is always at a higher voltage than the negative input, the single-ended conversion mode should be used in order to have full 12-bit resolution in the conversion mode, which has only positive values. If however the positive input may go below the negative input creating some negative results, the differential mode should be used in order to get correct results. The configuration of the conversion mode is set in the field bipolar in SEQCFG (SEQCFG.BIPOLAR). 998 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Note that the ADC works differentially in single-ended mode as well, as long as the positive input has a higher voltage than the negative. 38.6.5 ADC Clock Configuration The ADCIFE generates an internal clock named CLK_ADC that is used by the Analog-to-Digital Converter cell to perform conversions. The CLK_ADC is selected by writing to the CLKSEL bit in the Configuration Register (CFG). The CLK_ADC frequency is the frequency of the clock s e l e c t e d b y t h e C L K S E L b i t di v i d e d b y th e pr e s c al e r f i e l d i n t h e C o n f i g u r at i o n Register(CFG.PRESCAL). The value of th frequency must be defined in order to provide an ADC clock frequency according to the maximum sampling rate parameter given in the Electrical Characteristics section. Failing to do so may result in incorrect Analog-to-Digital Converter operation. The ADC cell converts an input voltage in 6 CLK_ADC periods and takes at least SHTIM+1 GCLK periods to sample for a 12-bit resolution. Thus, the maximum achievable ADC sampling frequency is: F ( CLKADC ) ---------------------------------6 If a 8-bit result is generated, the maximum ADC sampling frequency is 38.6.6 F ( CLKADC ) ---------------------------------4 Power Reduction Mode The Power Reduction Mode maximizes power saving by automatically deactivating the Analogto-Digital Converter cell when it is not being used for conversions. The Power Reduction Mode is enabled by writing a one to the Disable ADC(DIS) bit in the Control register (CR.DIS). Before entering power reduction mode the user must make sure the ADCIFE is idle and that the Analog-to-Digital Converter cell is inactive. To make sure the ADCIFE is idle, write a zero to the Trigger Selection (TRGSEL) field in the Sequencer Configuration Register (SEQCFG) and wait for the sequencer busy (SBUSY) bit in the Status Register (SR) to be cleared. Note that by deactivating the Analog-to-Digital Converter cell, a startup time penalty as defined in the STARTUP field in the timing register (TIM) will apply on the next conversion. The ADCIFE has the possibility to adjust the power consumption of the ADC cell according to the frequency range used. The SPEED field in the CFG register must be written to the right value. 38.6.7 Power-up and Startup Time The Analog-to-Digital Converter cell has a startup time when the cell is activated for the first time. This startup time is at least 12 ADC_CLK. This timing should be manage by the user by setting the startup time field in the Timing Configuration register (TIM.STARTUP). The enable startup bit in the Timing Configuration register (TIM.ENSTUP) allows to enable or not the startup time. For power-up and startup time values of the ADC cell, refer to the ADC cell chapter. 38.6.8 Operation Start/Stop To reset ADCIFE to its initial state, user can enable the ADCIFE after it was previously disabled thanks to the Enable bit in the Control register (CR.EN) and the Disable bit in the Control register 999 42023H–SAM–11/2016 ATSAM4L8/L4/L2 (CR.DIS). Another way to reset ADCIFE is to write a one in the SWRST field of the Control Register (CR.SWRST). In both cases configuration registers won’t be affected. 38.6.9 Analog Reference Refer to Section 42. ”Electrical Characteristics” on page 1121. The ADC allows the possibility to select several voltage reference (Vref). • An internal 1.0V voltage reference derived from the internal 1.1V • 0.625*Vcc (to get 1.0V when Vcc=1.6V) • Vcc/2 • 2 external reference inputs 38.6.10 GAIN The ADC cell allows to affect different gain for each conversion by configuring approprietely the Gain Factor field GAIN in the SEQCFG register. The programmable input amplification is from 1x to 64x. Moreover, this amplification can be divided by 2 by setting all bits in the field GAIN in the SEQCFG register to seven. 38.6.11 Conversion Results If the Half Word Left Adjust (HWLA) bit in the SEQCFG register is set, then the result will be left adjusted on the 16 lower bits of the LCV register. Otherwise, results will be right-adjusted. Positive and negative channels used in the last conversion are available both by reading the Sequencer Last Converted Value register (LCV). 38.6.12 Operating Modes Overview Table 38-2. Operating modes description Operating mode Differential mode without gain Input range Output code range Conversion time Output decimal code 6 clock_cycles 2047 + (Vin/Vref)*2047 -Vref to + Vref 0 to 4095 (11 bits signed number) 0 to 4095 (11 bits signed number) 7 clock_cycles for n=1 (gain=2) 2047 + (2n*Vin/Vref)*2047 Differential mode with gain=2n -Vref/2n to +Vref/2n Differential mode with division by 2 -2*Vref to +2*Vref Differential mode with zoom and gain =2n (n>0) -Vref/2n+Vshift, Vref/2n+Vshift Vshift=Vsup(1/4* zoomrange[1]+1/8*zo omrange[0]) 9 clock_cycles for n=6 (gain=64) 0 to 4095 (11 bits signed number) 7 clock_cycles 2047 + (Vin/(2*Vref))*2047 0 to 4095 (11 bits signed number) 7 clock_cycles for n=1 (gain=2) 2047+(2n*(VinVshift)/Vref*2047 10 clock_cycles for n=6 (gain=64) 1000 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Operating mode Unipolar mode without gain and without hysteresis Unipolar mode without gain and with hysteresis (zoomrange[2]=1) Unipolar mode without hysteresis and gain =2n Unipolar mode without hysteresis and with division by 2 Input range 0 to Vref -0.05*vref to 0.95*vref 0 to Vref/2n Conversion time Output decimal code 0 to 4095 (12 bits unsigned number) 7 clock_cycles 4095*Vin/Vref 0 to 4095 (12 bits unsigned number) 7 clock_cycles 4095*(Vin+0.05*vref)/Vref 0 to 4095 (12 bits unsigned number) 7 clock_cycles for n=1 (gain=2) 4095*(2n*Vin)/Vref 10 clock_cycles for n=6 (gain=64) 0 to 2*Vref Unipolar mode with hysteresis and gain =2n (-0.05*Vref to 0.95*Vref) /2n Unipolar mode with hysteresis and with division by 2 -0.1*Vref to 1.9*Vref 38.6.13 Output code range 0 to 4095 (12 bits unsigned number) 7 clock_cycles 4095*(Vin/2)/Vref) 0 to 4095 (12 bits unsigned number) 7 clock_cycles for n=1 (gain=2) 4095*(2n*Vin+0.05*Vref)/Vre f 10 clock_cycles for n=6 (gain=64) 0 to 4095 (12 bits unsigned number) 7 clock_cycles 4095*(0.5*Vin+0.05*Vref)/Vr ef Sequencer Trigger Event (STRIG) The sources must be configured through the TRGSEL field of the SEQCFG register (SEQCFG.TRGSEL). Selecting the event controller source allows any event controller source to generate a sequencer trigger event (STRIG). By configuring the continuous mode, STRIG will be generated continuously. The ADC can serve a maximum of one STRIG every 6+1 CLK_ADC periods. Extra STRIG will be ignored. User will be informed thanks to the Sequencer Missed Trigger Event (SMTRG) field of the SR register (SR.SMTRG). If the STRIG frequency provided by the event controller exceeds the ADC capability, the event controller will generate an underrun status. 38.6.14 Internal Timer The ADCIFE embeds an internal 16-bit timer used as a trigger source which can be configured by setting the ITMC field of the ITIMER register (ITIMER.ITMC). Internal Timer Trigger Period= (ITMC+1)*T(CLK_ADC) Once set as a STRIG source, the internal timer has to be started by writing a '1' in the TSTART bit of the CR register (CR.TSTART). It can be stopped in the same way by writing a '1' in the TSTOP bit of the CR register (CR.TSTOP). The current status of the internal timer can be read 1001 42023H–SAM–11/2016 ATSAM4L8/L4/L2 from the Timer Busy field of the SR register (SR.TBUSY): 0 means stopped, 1 means running. In addition when the internal timer is running, if ITIMER.ITMC is written to change the internal timer timeout frequency, the internal counter is cleared to avoid rollover phenomena. Note: It is possible to generate an internal timer event each GCLK period by writing 0 in ITIMER.ITMC and by selecting the internal timer as a STRIG source 38.6.15 Peripheral DMA Controller (PDCA) Capability There are two PDCA channels. One Rx for transferring data result to memory, and one Tx for storing the updated configuration of the next conversion from memory. The LCV register contains the last converted value of the sequencer according to the conversion result format. The LCV register is updated each time the sequencer ends a conversion. If the last converted value has not been read, there’s an overrun, the LOVR bit in the SR register indicates that at least one overrun error occurred. The LOVR bit of the SR register is cleared by writing a ‘1’ in the LOVR field of the SCR register. Tx transfer: If the configuration is performed by the PDCA, so the CDMA register contains configuration for the next conversion. If Window Mode is not used, only one word is usefull with the MSB bit to zero. If Window Mode is used, the first word has the MSB bit to one and the second word is dedicated for Window Mode with MSB bit set to zero. Note: Rx PDCA transfers are 16 bits wide. Note: In Tx, the first word received has always the same structure. The second word, if necessary, has always the same structure too. Figure 38-2. One DMA Tx transfer: No Window Mode Configuration DMA Tx Ready MSB : 0 Start Of Conversion APB Data Bus DMA Word Data CDMA Register 31 0 23 DMA Word Data with MSB to "0" 30 22 15 14 INTERNAL 7 6 GCOMP 29 28 ZOOMRANGE 21 20 MUXNEG 13 12 TSS RES 5 4 GAIN 27 26 25 24 19 18 17 MUXPOS 10 9 16 11 3 STRIG 2 BIPOLAR 1 8 ENSTUP 0 HWLA 1002 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 38-3. Two DMA Tx transfers: With Window Mode Configuration DMA Tx Ready MSB : 0 MSB : 1 Start Of Conversion 1st DMA Word Data APB Data Bus 2nd DMA Word Data CDMA Register 31 1 23 30 29 ZOOMRANGE 22 21 MUXNEG 15 14 13 INTERNAL TSS 7 6 5 GAIN GCOMP 28 27 26 25 24 20 19 16 12 RES 4 11 18 17 MUXPOS 10 9 3 STRIG 2 BIPOLAR 1 8 ENSTUP 0 HWLA CDMA Register 31 0 23 29 28 22 21 20 27 24 19 26 25 HT[11:8] 18 17 11 10 9 8 1 0 16 HT[7:0] 15 7 First DMA Word Data with MSB to "1" 30 14 6 13 WM 5 12 LT[11:8] 4 3 2 LT[7:0] Second DMA Word Data with MSB to "0" 38.6.16 Zoom Mode The Zoom mode allows to choose a part of a range of the reference voltage (SEQCFG.ZOOMRANGE) and spread it from 0 to 4095 decimal. This particular mode of the ADC uses GAIN in which the input range is shifted with a programmable voltage. The input voltage range is acording to a programmable voltage of Vdd and a range around this voltage (SEQCFG.GAIN). 38.6.17 Window Monitor The window monitor monitors ADC results and make the ADCIFE behave as an analog comparator. Configuration is done by writing appropriately the Window Configuration Register (WCFG) and the Window Thresholds Register (WTH). When writing a one in the Monitor Filter Mode bit in the WCFG register (WCFG.MFM) , conversions are filtered using its index in the sequence. Otherwise, no filtering is applied, monitoring is performed on every conversion. Index is given by writing the field Source in the WCFG register (WCFG.SRC). Supported modes are selected by writing the Window Mode field in the WCFG register, refer to the Table 38-3 below. Thresholds are given by writing the Low Threshold (LT) and High Threshold (HT) in WTH. Note that the significant WTH.LT and WT.HT bits are given by the precision selected in the SEQCFG.RES field. That means that if you are in 8-bit mode, only the 8 lower bits will be considered. 1003 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 38-3. Window Monitor Modes WM field in WCFGy Modes 0 0 0 No window mode (default) 0 0 1 Mode 1: active when result > LT 0 1 0 Mode 2: active when result < HT 0 1 1 Mode 3: active when LT < result < HT 1 0 0 Mode 4: active when (!(LT < result < HT)) 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved Note: Comparisons are performed regardless with the SEQCFG.HWLA setting (half word left adjust). 38.6.18 Interrupts Interrupt requests are enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). Enabled interrupts can be read from the Interrupt Mask Register (IMR). Active interrupt requests, but potentially masked, are visible in the Status Register (SR). To clear an active interrupt request, write a one to the corresponding bit in the Clear Register (CR). The Status Register (SR) fields in common with IER/IDR/IMR show the status since the last write to the Interrupt Clear Register. Other SR fields show the status at the time being read. Table 38-4. Line ADCIFE Interrupt Group Line Description Related Status Sequencer end of conversion (SEOC) Sequencer Sequencer missed trigger event (SMTRG) 0 38.6.19 Sequencer (last converted value) overrun (LOVR) Timing Timer time-out Window Window monitor Conversion Performances For performance and electrical characteristics of the ADCIFE, refer to Section 42. ”Electrical Characteristics” on page 1121. 1004 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7 User Interface Table 38-5. ADCIFE Register Memory Map Offset Register Register Name Access Reset 0x0000 Control Register CR Write-Only 0x00000000 0x0004 Configuration Register CFG Read/Write 0x00000000 0x0008 Status Register SR Read-Only 0x00000000 0x000C Status Clear Register SCR Write-Only 0x00000000 0x0014 Sequencer Configuration Register SEQCFG Read/Write 0x00000000 0x0018 Configuration Direct Memory Access Register CDMA Write-Only 0x00000000 0x001C Timing Configuration Register TIM Read/Write 0x00000000 0x0020 Internal Timer Register ITIMER Read/Write 0x00000000 0x0024 Window Monitor Configuration Register WCFG Read/Write 0x00000000 0x0028 Window Monitor Threshold Configuration Register WTH Read/Write 0x00000000 0x002C Sequencer Last Converted Value Register LCV Read-Only 0x00000000 0x0030 Interrupt Enable Register IER Write-Only 0x00000000 0x0034 Interrupt Disable Register IDR Write-Only 0x00000000 0x0038 Interrupt Mask Register IMR Read-Only 0x00000000 0x003C Calibration Register CALIB Read/Write 0x00000000 0x0040 Version Register VERSION Read-Only -(1) 0x0044 Parameter Register PARAMETER Read-Only -(1) Note: 1. The reset value for this register is device specific. Refer to the Module Configuration section at the end of this chapter. 1005 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.1 Name: Control Register CR Access Type: Write-Only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - BGREQDIS BGREQEN DIS EN 7 6 5 4 3 2 1 0 - - REFBUFDIS REFBUFEN STRIG TSTART TSTOP SWRST Writing a zero to any of those bits in this register has no effect. • BGREQDIS:Bandgap buffer request disable Writing a one to this bit disables the bandgap buffer request Reading this bit always returns 0 • BGREQEN:Bandgap buffer request enable Writing a one to this bit enables the bandgap buffer request Reading this bit always returns 0 • DIS:ADCIFE disable Writing a one to this bit disables the ADCIFE Reading this bit always returns 0 Note: Changes do not apply immediately, ADCIFE status can be checked by reading the EN field of the SR register • EN:ADCIFE enable Writing a one to this bit enables the ADCIFE Reading this bit always returns 0 Note: Changes do not apply immediately, ADCIFE status can be checked by reading the EN field of the SR register • REFBUFDIS: Reference buffer disable Writing a one to this bit disables the Reference Buffer Reading this bit always returns 0 • REFBUFEN: Reference buffer enable Writing a one to this bit enables the Reference Buffer Reading this bit always returns 0 • STRIG:Sequencer trigger Writing a one to this bit generates a sequencer trigger event Reading this bit always returns 0 1006 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • TSTART:Internal timer start bit Writing a one to this bit starts the internal timer Reading this bit always returns 0 Note: The internal timer status can be read in the RUNT field of the SR register • TSTOP:Internal timer stop bit Writing a one to this bit stops the internal timer Reading this bit always returns 0 Note: The internal timer status can be read in the RUNT field of the SR register • SWRST: Software reset Writing a zero to this bit has no effect. Writing a one to this bit resets the ADCIFE, simulating a hardware reset. Using that control ensures that ADCIFE internal features will return to their initial states. Configuration registers won’t be affected. 1007 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.2 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 - CLKSEL SPEED PRESCAL 2 REFSEL 1 0 - • PRESCAL: Prescaler Rate Slection PRESCAL Group Configuration System clock division factor 000 DIV4 4 001 DIV8 8 010 DIV16 16 011 DIV32 32 100 DIV64 64 101 DIV128 128 110 DIV256 256 111 DIV512 512 • CLKSEL: Clock Selection for sequencer/ADC cell 1: The APB clock is used 0: The Generic clock is used 1008 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • SPEED: ADC current reduction SPEED Max speed 00 300 ksps 01 225 ksps 10 150 ksps 11 75 ksps • REFSEL: ADC Reference selection REFSEL Description 000 Internal 1.0V (10/11*bandgap) 001 0.625*VCC 010 External reference 1 011 External reference 2 (DAC_VOUT) 1XX VCC/2 1009 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.3 Name: Status Register SR Access Type: Read-Only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - BGREQ - REFBUF CBUSY SBUSY TBUSY EN 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - TTO - SMTRG WM LOVR SEOC • BGREQ: Bandgap buffer request Status • • • • • • 1: Bandgap buffer request is enabled 0: Bandgap buffer request is disabled BGREQREFBUF: Reference Buffer Status 1: Reference Buffer is enabled 0: Reference Buffer is disabled CBUSY: Conversion busy 1: ADCIFE is converting 0: ADCIFE is not converting SBUSY: Sequencer busy 1: ADCIFE sequencer is running 0: ADCIFE sequencer is ready TBUSY: Timer busy 1: ADCIFE internal timer is running 0: ADCIFE internal timer is stopped EN: Enable Status 1: ADCIFE is ready for operation 0: ADCIFE is not ready TTO: Timer time-out This bit is set when the internal timer times out This bit is cleared when the corresponding bit in SCR is written to one 1010 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • SMTRG:Sequencer missed trigger event This bit is set when a sequencer trigger event is missed This bit is cleared when the corresponding bit in SCR is written to one • WM:Window monitor This bit is set when the watched result value goes to the defined window This bit is cleared when the corresponding bit in SCR is written to one • LOVR:Sequencer last converted value overrun This bit is set when an overrun error occurs on the LCV register This bit is cleared when the corresponding bit in SCR is written to one • SEOC:Sequencer end of conversion This bit is set when an end of conversion occurs This bit is cleared when the corresponding bit in SCR is written to one 1011 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.4 Name: Status Clear Register SCR Access Type: Write-Only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - TTO - SMTRG WM LOVR SEOC Writing a zero to a bit in this register has no effect. Writing a one to a bit clears the corresponding SR bit 1012 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.5 Name: Sequencer Configuration Register SEQCFG Access Type: Read/Write Offset: 0x14 Reset Value: 0x00000000 4 31 30 - 29 28 ZOOMRANGE 23 22 - 21 20 27 26 25 24 - - - - 19 18 17 16 9 8 MUXNEG 15 14 INTERNAL 7 GCOMP 6 MUXPOS 13 12 11 - RES - 5 4 3 2 1 0 - BIPOLAR - HWLA GAIN 10 TRGSEL 1013 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • ZOOMRANGE: Zoom shift/unipolar reference source selection ZOOMRANGE Mode Comment 000 Select Vref for shift cycle All modes except zoom and unipolar with hysteresis 001 Select Vdd/4 for shift cycle Zoom mode 010 Select Vdd/2 for shift cycle Zoom mode 011 Select 3*Vdd/4 for shift cycle Zoom mode 1XX Select 0.9*Vref for shift cycle Unipolar mode with hysteresis • MUXNEG: MUX selection on Negative ADC input channel BIPOLAR INTERNAL MUXNEG Negative input to ADC 0 0X XXX primary_anahot_XXX tied to ground 0 1X 001 or 111 Pad Ground 1 0X 000 primary_anahot_0 1 0X 001 primary_anahot_1 1 0X 010 primary_anahot_2 1 0X 011 primary_anahot_3 1 0X 100 primary_anahot_4 1 0X 101 primary_anahot_5 1 0X 110 primary_anahot_6 1 0X 111 primary_anahot_7 1 1X 000 Vsingle = 0.9*Vref 1 1X 001 Pad Ground 1 1X 010 Vcalib3 = Vref/10 1 1X 011 Reference Ground 1 1v 100 Not used 1 1X 101 Vcalib3 = Vref/10 1 1X 110 Not used 1 1X 111 Pad Ground • MUXPOS: MUX selection on Positive ADC input channel BIPOLAR INTERNAL MUXPOS Positive input to ADC X X0 0000 AD0 X X0 0001 AD1 X X0 0010 AD2 X X0 0011 AD3 1014 42023H–SAM–11/2016 ATSAM4L8/L4/L2 BIPOLAR INTERNAL MUXPOS Positive input to ADC X X0 0100 AD4 X X0 0101 AD5 X X0 0110 AD6 X X0 0111 AD7 X X0 1000 AD8 X X0 1001 AD9 X X0 1010 AD10 X X0 1011 AD11 X X0 1100 AD12 X X0 1101 AD13 X X0 1110 AD14 X X0 1111 Bandgap X X1 X000 Not used X X1 X001 Bandgap X X1 X010 Scaled Vcc, Vcc/10 X X1 X011 DAC internal X X1 X100 Not used X X1 X101 Not used X X1 X110 Vsingle = 0.9*Vref X X1 X111 Reference Ground 1015 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • INTERNAL: Internal Voltage Sources Selection INTERNAL Positive Internal Selection Negative Internal Selection 00 Enables the primary/secondary voltage sources Enables the primary voltage sources 01 Enables the internal voltage sources Enables the primary voltage sources 10 Enables the primary/secondary voltage sources Enables the internal voltage sources 11 Enables the internal voltage sources Enables the internal voltage sources • RES: Resolution RES Resolution 0 12-bits 1 8-bits • TRGSEL: Trigger selection TRGSEL Trigger 000 Software 001 internal ADC timer 010 internal trigger source (refer to module configuration section) 011 Continuous mode 100 External trigger pin rising edge 101 External trigger pin falling edge 110 External trigger pin both edges 111 Reserved • GCOMP: Gain Compensation 1: Enables the ADC gain error reduction 0: Disables the ADC gain error reduction 1016 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • GAIN: Gain factor GAIN Gain factor 000 1x 001 2x 010 4x 011 8x 100 16 x 101 32 x 110 64 x 111 0,5 x • BIPOLAR: Bipolar Mode 1: Enables the differential mode 0: Enables the single-ended mode • HWLA: Half Word Left Adjust 1: Enables the HWLA mode 0: Disables the HWLA mode 1017 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.6 Name: Configuration Direct Memory Access CDMA Access Type: Write-Only Offset: 0x18 Reset Value: 0x00000000 First DMA Word 31 30 DW 29 28 ZOOMRANGE 23 22 - 21 20 27 26 25 24 - - - - 19 18 17 16 MUXNEG 15 14 INTERNAL 7 13 12 11 10 9 8 TSS RES - - - ENSTUP 5 4 3 2 1 0 STRIG BIPOLAR - HWLA 25 24 6 GCOMP MUXPOS GAIN • DW: Double Word transmitting Number of DMA transfer remainning to end the configuration of the next conversion • TSS: Internal timer start or stop bit Writing a one to this bit starts the internal timer Writing a zero to this bit stops the internal timer Second DMA Word (Optional Window Mode) 31 30 29 28 DW - - - 23 22 21 20 27 26 HT[11:8] 19 18 17 16 11 10 9 8 1 0 HT[7:0] 15 14 - 13 12 WM 7 6 5 LT[11:8] 4 3 2 LT[7:0] • DW: Double Word transmitting This bit must be set to zero (configuration completed) 1018 42023H–SAM–11/2016 ATSAM4L8/L4/L2 This register is used for DMA transfers to the ADCIFE module. The first word transmitted is the general configuration. If the MSB bit is set to one, a second word will be transfered to complete the configuration so that use the Window Mode. If the MSB bit is set to zero, the configuration is completed. The second word is only used when the window mode is needed. In this case, its MSB bit is always set to zero (configuration completed). 1019 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.7 Name: Timing Configuration Register TIM Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ENSTUP 7 6 5 4 3 2 1 0 - - - STARTUP • ENSTUP: Enable Startup 1: Enables the Startup time 0: Disables the Startup time • STARTUP: Startup time Number of CLK_ADC clock cycles to wait for starting conversion: (STARTUP+1) 1020 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.8 Name: Internal Timer Register ITIMER Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 ITMC[15:8] 7 6 5 4 ITMC[7:0] • ITMC:Internal Timer Max Counter f(itimer_timeout)=f(GCLK)/(ITMC+1) 1021 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.9 Name: Window Monitor Configuration WCFG Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - WM 7 6 5 4 3 2 1 0 - - - - - - - - • WM: Window Monitor Mode WM Window monitor mode 000 OFF 001 Mode 1: RES(SRC) > LT 010 Mode 2: RES(SRC) < HT 011 Mode 3: LT=HT) 101 Reserved 110 Reserved 111 Reserved 1022 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.10 Name: Window Monitor Threshold Configuration WTH Access Type: Read/Write Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 26 25 24 HT[11:8] 19 18 17 16 11 10 9 8 1 0 HT[7:0] 15 14 13 12 - - - - 7 6 5 4 LT[11:8] 3 2 LT[7:0] • HT:High Threshold HighThreshold value • LT:Low Threshold Low Threshold value 1023 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.11 Name: Sequencer Last Converted Value LCV Access Type: Read-Only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 15 LCNC 14 13 LCPC 12 11 10 9 8 3 2 1 0 LCV[15:0] 7 6 5 4 LCV[7:0] • LCNC: Last converted negative channel This field is set by hardware to the last negative channel converted, i.e. what negative channel the LCV represents. • LCPC: Last converted positive channel This field is set by hardware to the last positive channel converted, i.e. what positive channel the LCV represents. • LCV: Last converted value This field is set by hardware to the last sequencer converted value depending on precision and on the choosen left adjustment mode (SEQCFG.HWLA). 1024 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.12 Name: Interrupt Enable Register IER Access Type: Write-Only Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 - - TTO - SMTRG WM LOVR SEOC Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 1025 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.13 Name: Interrupt Disable Register IDR Access Type: Write-Only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 - - TTO - SMTRG WM LOVR SEOC Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 1026 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.14 Name: Interrupt Mask Register IMR Access Type: Read-Only Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 - - - 23 22 21 20 - - - - 15 14 13 12 - - - 7 6 5 4 - - TTO - 27 26 25 24 - - - 18 17 16 - - - 10 9 8 - - - 3 2 1 0 SMTRG WM LOVR SEOC 19 11 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 1027 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.15 Name: Calibration Register CALIB Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - BIASSEL 3 2 1 0 BIASCAL 7 6 5 4 CALIB • FCD: Flash Calibration Done Set to one when CALIB and BIASCAL have been updated by the flash fuses after a reset. 1: The flash calibration will be redone after any reset 0: The flash calibration will only be redone after a power-on reset • BIASCAL: Bias calibration BIASCAL Ptat current Bgap current Total current 0000 3.0 1.1 4.1 0001 3.0+0.75 1.1 4.85 3.0+1.5 1.1 5.6 0011 3.0+1.5+0.75 1.1 6.35 0100 3.0 1.1+1.1 5.2 0101 3.0+0.75 1.1+1.1 5.95 0110 3.0+1.5 1.1+1.1 6.7 0111 3.0+1.5+0.7 1.1+1.1 7.45 0 5.5 5.5 0 5.5+1.1 6.6 0010 Default setting 10XX Pure bandgap bias 11XX • BIASSEL: Select bias mode 1: Select bandgap bias 0: Select mixed bias 1028 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • CALIB: Calibration value CALIB Value Description 7 S1 MSB 4 S1 LSB 3 S2 MSB 0 S2 LSB 1029 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.16 Name: Module Version VERSION Access Type: Read-Only Offset: 0x40 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 1030 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.7.17 Name: Parameter Register PARAMETER Access Type: Read-Only Offset: 0x44 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 N • N: Number of channels 1031 42023H–SAM–11/2016 ATSAM4L8/L4/L2 38.8 Module Configuration The specific configuration for each ADCIFE instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 109 for details. Table 38-6. ADCIFE Configuration Feature ADCIFE External Ref 2 connection DACC OUT output Table 38-7. ADCIFE Clock Name Clock Name Description CLK_ADCIFE Clock for the ADCIFE bus interface GCLK_ADCIFE The generic clock used for the ADCIFE is GCLK10 Register Reset Value VERSION 0x00000100 1032 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39. LCD Controller (LCDCA) Rev: 1.0.0.0 39.1 Features • • • • • • • • • • • • • • • • • • 39.2 Display capacity up to 40 segment and up to 4 common terminals Supports from static up to 1/4 duty Supports static and 1/3 bias Shadow display memory gives full freedom in segment update ASCII character mapping Automated characters string scrolling Automated characters string display Automated segments display Autonomous animation up to 8 segments LCD driver active in power save mode for low power operation Low power waveform Flexible selection of frame frequency Configurable blink mode and frequency Uses only 32 kHz clock On-chip LCD power supply Software contrast adjustment control Equal source and sink capability to increase LCD life time Interrupt mode for display update or wake-up from sleep mode Overview A LCD display is made of several segments (or complete symbols) which can be visible or invisible. A segment has two electrodes with liquid crystal between them. These electrodes are the common terminal (COM) and the segment terminal (SEG). When a voltage above a threshold voltage is applied across the liquid crystal, the segment becomes visible. The voltage must alternate to avoid an electrophoresis effect in the liquid crystal, this effect degrades the display. Hence the voltage waveform across a segment must not have a DC-component. Figure 39-1. LCD Segment/Common Terminals SEG0 SEG1 SEG2 se gm en t2 se gm en t1 se gm en t0 COM0 ... 2 en t4 se gm en t4 1 se gm se gm en t4 0 COM1 ... The LCD controller (LCDCA) is intended for monochrome passive liquid crystal display (LCD) with up to 4 common terminals and up to 40 segment terminals. Unused segment/common terminals (pins) are configured as general purpose I/O pins.The LCD controller uses a 32kHz clock (CLK_LCD) and can therefore be running in deep sleep modes. 1033 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Dedicated Low Power Waveform, Contrast Control, Extended Interrupt Mode, ASCII Character Mapping, automated modes... are defined to offload the CPU, reduce interrupts and reduce power consumption. To reduce hardware design complexity, the module includes integrated LCD buffers, an integrated power supply voltage. 39.3 Block Diagram Figure 39-2. LCDCA Block Diagram LCDCA BPM CLK32 APB Interface IRQ Automated Modes Display Memory Timing Shadow Display Memory Analog Switch Array SEGx COMy VLCD LCD Power Supply BIASH BIASL CAPH 39.4 I/O Lines Description Table 39-1. I/O Lines Description Pin Name 39.5 CAPL Pin Description Type SEGx Segment terminal x Analog COMy Common terminal y Analog VLCD Bias voltage Analog BIAS1 Bias voltage (= 1/3 VLCD) Analog BIAS2 Bias voltage (= 2/3 VLCD) Analog CAPL High voltage end of flying capacitor Analog CAPH Low voltage end of flying capacitor Analog Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 1034 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.5.1 I/O Lines The LCDCA pins (SEGx and COMy) are multiplexed with other peripherals. The user must first configure the I/O Controller to give control of the pins to the LCDCA. VLCD, BIAS1, BIAS2, CAPL, CAPH are not multiplexed. 39.5.2 Power Management This module can control the LCD display while CLK_LCDCA is disabled but stops functioning when CLK_LCD (32KHz) is disabled. The power consumption of LCDCA itself can be minimized by: • using the lowest acceptable frame rate (refer to the LCD glass technical characteristics), • using the low power waveform (default mode), • using automated modes, • configuring the lowest possible contrast value. 39.5.3 Clocks The clock for this module (CLK_LCDCA) is generated by the Power Manager. It can be enabled or disabled either manually through the user interface of the Power Manager or automatically when the system enters a sleep mode that disables the clocks to the peripheral bus modules. The 32KHz clock (CLK_LCD) must be enabled before use. When system enters a sleep mode, 32KHz clock can be disabled, see Power Manager chapter for details. 39.5.4 Interrupts The LCDCA interrupt request line is connected to the interrupt controller. Using the interrupt requires the interrupt controller to be configured first. 39.5.5 Wake Up Wake up signal is connected to Power Manager (PM). Using wake up mechanism requires the PM to enable the corresponding asynchronous wake up source first. Also LCDCA interrupt must be enabled first. 39.5.6 39.6 39.6.1 Debug Operation When an external debugger forces the CPU into debug mode, the LCDCA continues normal operation. Functional Description LCD Display The display memory stores the values of all segments to display. Accessible through APB, it should be filled before next frame starts. A start of a new frame triggers the update of the shadow display memory. The content of display memory is copied into the shadow display memory. A display memory refresh is possible without affecting data that is sent to the panel. Note that display memory is not initialized at power-up. When a bit in the display memory is written to one, the corresponding segment will be energized (ON / opaque), and de-energized (OFF / transparent) when this bit is written to zero. 1035 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Addressing COM0 starts a frame by driving an opposite phase with large amplitude on COM0 as against non addressed COM terminals. Non-energized segments are in phase with the addressed COM0, and energized segments have opposite phase and large amplitude (refer to ”Operating modes” on page 1036). Shadow display memory bits are multiplexed into the decoder. The decoder is configured by the LCD timing and controls the analog switches to produce an output waveform onto each selected COM terminals (duty value). Figure 39-3. Display Memory Mapping offset 19 DATA[39:0] COM3 DATA[39:0] COM2 DATA[39:0] COM1 DATA[39:0] COM0 15 10 9 8 7 6 5 4 3 2 1 0 7 39.6.2 6 5 4 3 2 1 0 Operating modes To energize a segment, an absolute voltage above the LCD threshold must be applied. This is done by setting the SEG terminal to opposite phase when the corresponding COM terminal is active. For a display with more than one common terminal, two additional voltage levels (1/3 bias) must be applied. Otherwise, non-energized segments on COM0 would be energized for all non-selected common lines. Duty bits (DUTY) in the Configuration register (CFG) defines the duty cycle. Unused common terminals are driven to ground. Table 39-2. 39.6.2.1 Duty Selection DUTY[1:0] Duty Bias COM pins Used 00 1/4 1/3 COM[0:3] 01 Static Static COM0 10 1/2 1/3 COM[0:1] 11 1/3 1/3 COM[0:2] Static Duty and Static Bias If all segments on a LCD have one common electrode then each segment have a unique segment terminal. SEG0-COM0 is the voltage across a segment that is ON and SEG1-COM0 is the voltage across a segment that is OFF. 1036 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 39-4. Driving a LCD With One Common Line 39.6.2.2 1/2 Duty and 1/3 Bias For a LCD with two common terminals (1/2 duty) a more complex waveform must be used to individually control segments. SEG0-COM0 is the voltage across a segment that is ON and SEG0-COM1 is the voltage across a segment that is OFF. Figure 39-5. Driving an LCD With Two Common Lines 39.6.2.3 1/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). SEG0-COM0 is the voltage across a segment that is ON and SEG0-COM1 is the voltage across a segment that is OFF. 1037 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 39-6. Driving a LCD With Three Common Lines 39.6.2.4 1/4 Duty and 1/3 Bias 1/3 bias is optimal for LCD with four common terminals (1/4 duty). SEG0-COM0 is the voltage across a segment that is ON and SEG0-COM1 is the voltage across a segment that is OFF. Figure 39-7. Driving a LCD With Four Common Lines VLCD VLCD 2/3 VLCD 2/3 VLCD SEG0 1/3 VLCD GND GND VLCD VLCD 2/3 VLCD 2/3 VLCD COM0 1/3 VLCD GND COM1 1/3 VLCD GND VLCD VLCD 2/3 VLCD 2/3 VLCD 1/3 VLCD 1/3 VLCD SEG0-COM0 GND GND -1/3 VLCD -1/3 VLCD -2/3 VLCD -2/3 VLCD - VLCD SEG0-COM1 - VLCD Frame 39.6.3 SEG0 1/3 VLCD Frame Frame Frame Enabling/Disabling LCDCA Write bit Enable (EN) to one in Control Register (CR) to enable the module. Write bit Disable (DIS) to one to disable it. LCD controller will be disabled after the completion of current frame. Bit Enable in Status Register (SR.EN) is set to one when LCD controller is ready to operate and set to zero when LCD power supply is off. 1038 42023H–SAM–11/2016 ATSAM4L8/L4/L2 When LCD controller is disabled all segment and common terminals are driven to GND, discharging the LCD in order to avoid DC voltage across the segments and a slowly fading image. Data in the display memory is preserved. In order to restart correctly, it is preferrable to disable all functions (blinking, FCx,...) before disabling LCD controller. 39.6.4 Waveform Modes To reduce toggle activity and hence power consumption, write a zero to the Waveform Mode (CFG.WMOD) to enable the low power waveform mode (the LCD glass must support this mode). The low power waveform period is then twice the standard waveform period, in both modes DC voltage is null. To select the standard waveform, write a one to the CFG.WMOD bit. This bit shall not be modified when LCDCA is enabled. Figure 39-8. Waveform Modes (Three Common Lines) Standard waveform Low power waveform VLCD VLCD 2/3 VLCD 2/3 VLCD SEG0 1/3 VLCD GND VLCD VLCD COM0 2/3 VLCD 1/3 VLCD GND GND VLCD VLCD 2/3 VLCD 2/3 VLCD VThreshold 1/3 VLCD VThreshold 1/3 VLCD SEG0-COM0 GND -1/3 VLCD SEG0-COM0 GND -1/3 VLCD -VThreshold -2/3 VLCD -VLCD -VThreshold -2/3 VLCD -VLCD Frame 1 Frame 2 Frame 1 T = 20ms 39.6.5.1 COM0 2/3 VLCD 1/3 VLCD 39.6.5 SEG0 1/3 VLCD GND T = 40ms Timing Generation Frame Rate The Prescaler field (PRESC) in Timing register (TIM) selects a tap point from a ripple counter. The ripple counter output can be further divided by setting the Clock Divider (CLKDIV[2:0]). Table 39-3. LCD Prescaler Selection PRESC Output From Prescaler 0 CLK_LCD / 8 1 CLK_LCD / 16 1039 42023H–SAM–11/2016 ATSAM4L8/L4/L2 The Clock Division field (CLKDIV) in TIM register defines the division ratio in the clock divider. This gives extra flexibility in frame rate setting. F ( CLK_LCD ) FrameRate = ---------------------------------------------------------------------------------------------------( 1 – WMOD ) ( K × N × ( 1 + CLKDIV ) × 2 ) Where: N = prescaler divider (8 or 16). K = 8 for 1/4, 1/2 and static duty. K = 6 for 1/3 duty. WMOD = 0 in low power waveform mode, = 1 in standard waveform mode. Table 39-4. LCD Clock Divider (1/4 Duty, WMOD=1) Frame rate (1/4 Duty) CLKDIV[2:0] Divided by 000 F(CLK_LCD) = 32 kHz F(CLK_LCD) = 32768 Hz N=8 N=16 N=8 N=16 1 500 Hz 250 Hz 512 Hz 256 Hz 001 2 250 Hz 125 Hz 256 Hz 128 Hz 010 3 166.667 Hz 83.333 Hz 170.667 Hz 85.333 Hz 011 4 125 Hz 62.5 Hz 128 Hz 64 Hz 100 5 100 Hz 50 Hz 102.4 Hz 51.2 Hz 101 6 83.333 Hz 41.667 Hz 85.333 Hz 42.667 Hz 110 7 71.429 Hz 35.714 Hz 73.143 Hz 36.671 Hz 111 8 62.5 Hz 31.25 Hz 64 Hz 32 Hz Note that when using 1/3 duty, the frame rate is increased by 33% compared to the values listed above and in low power waveform mode, the frame rate is divided by two. Table 39-5. 39.6.5.2 Frame Rate Examples (WMOD=1) CLK_LCD Duty K PRESC N CLKDIV[2:0] Frame rate 32.768 kHz Static 8 1 16 4 32768 / (8*16*(1+4)) = 51.2 Hz 32.768 kHz 1/2 8 1 16 4 32768 / (8*16*(1+4)) = 51.2 Hz 32.768 kHz 1/3 6 1 16 4 32768 / (6*16*(1+4)) = 68.267 Hz 32.768 kHz 1/4 8 1 16 4 32768 / (8*16*(1+4)) = 51.2 Hz Frame Counters For several functions (blinking, automated modes,...) a frame counter is used to create a time base. There are three independent frame counters (FC0, FC1 and FC2) which can be associated to any function (refer to corresponding section). FrameRate f FCx = ----------------------------------------------( TIM.FCx × 8 ) + 1 For FC0 only, the prescaler of 8 can be bypassed by writting a one to TIM.FC0PB. Note that frame counter frequency depends on frame duration therefore of waveform mode. 1040 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Each frame counter is enabled by writing a one to Frame Counter x Enable (CR.FCxEN) and disabled by writing a one to Frame Counter x Disable (CR.FCxDIS).Frame counter must be disabled (SR.FCxS=0) before the update of its associated TIM.FCx value. 39.6.6 39.6.6.1 CPU Display Memory Access Direct Access CPU can access display memory in direct access by writing to Data Register Low x (DRLx) and Data Register High x (DRHx). Read-modify-write operation is then required to update few bits. To modify a segment defined by SEGx / COMy, select register R and bit B: R = ( y > 5 B = x & 0x1F Where R is the register index in the list {DRL0, DRH0, DRL1, DRH1, DRL2, DRH2, DRL3, DRH3} and B is the bit position in this register. 39.6.6.2 Indirect Access CPU can also update up to 8 bits in display memory in indirect access by writing to Indirect Access Data Register (IADR). It allows to modify 1 up to 8 bits in a single operation without modifying masked bits in display memory (no read-modify-write operation). This register requires: • DATA[7:0], each bit represents the state of a segment, • DMASK[7:0], each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to display memory, • OFF[4:0], byte offset in display memory (see Figure 39-3 on page 1036). To modify a segment defined by SEGx / COMy, write byte at offset OFF, bit B: OFF = ( 5(y > 3 B = x & 0x7 39.6.7 Locking Shadow Display Memory Writing a one to LOCK bit, in Configuration register (CFG), freezes the shadow display memory update. Then if the display memory is modified, the display remains unchanged. When this bit is cleared, the shadow display memory is updated when a new frame starts. 39.6.8 Blinking Modes 39.6.8.1 Software Blinking Writing bit BLANK in CFG register to one turns OFF all LCD segments at the next frame. If BLANK=0 the content of the display memory is output on the LCD. The blink frequency is then software dependant. To avoid unexpected intermediate display, blank command should be written after the end of the frame (SR.FC0R=1). LCD controller must be running (frames are generated) to blink segments. 39.6.8.2 Hardware Blinking To blink all segments on LCD panel, write a zero to Blink Mode (MODE) in Blink Configuration Register (BCFG). Write a one to MODE to blink selected segments. 1041 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Up to eight segments can be selected individually to blink. Each bit in Blink Segment Selection x field (BCFG.BSSx) selects a segment for blinking. If BSS0[y]=1, segment connected to SEG0/COMy is selected to blink. If BSS1[y]=1, segment connected to SEG1/COMy is selected to blink. A segment will blink if its corresponding bit is one in the display memory, otherwise it remains OFF. The blink frequency is defined by the number of frames (FCx in TIM register) between each state ON/OFF. So after FCx+1 frames, the segment will change state. Note that blinking frequency is also related to waveform mode, see ”Waveform Modes” on page 1039. The frame counter is selected by writing its number in BCFG.FCS field. BCFG.BSSx and BCFG.MODE should be modified after a frame has ended (SR.FC0R=1), BCFG.FCS shall not be modified when blinking is running. The blinking is started by writing a one to CR.BSTART and stopped by writing a one to CR.BSTOP. The status of blinking can be read in SR.BLKS. Table 39-6. Blinking Modes BLANK EN BSS1[3:0] BSS0[3:0] 1 x xxxx xxxx All segments are OFF 0 0 xxxx xxxx All segments are driven by the display memory 0000 0000 All segments are blinking at the blink frequency 0 1 Not equal to zero 39.6.9 Comment Selected segment(s) are blinking at the blink frequency Autonomous Segment Animation Up to eight pixels can be animated by an internal circular shift register. Up to eight states are then defined to make a running wheel for example. The number of segments used for animation must be written in SIZE field in Circular Shift Register Configuration (CSRCFG). If SIZE=N, circular shift register uses bits 0 to N-1. The circular shift register bits are mapped on SEG2 and SEG3 of all common terminals. Table 39-7. Circular Shift Register Bit Mapping Shift Register Bit COM SEG 0 0 2 1 0 3 2 1 2 3 1 3 4 2 2 5 2 3 6 3 2 7 3 3 1042 42023H–SAM–11/2016 ATSAM4L8/L4/L2 The shifting period is defined by the number of frame in TIM.FCx. The frame counter is selected by writing its number in CSRCFG.FCS field. If frame rate is 50Hz (20ms) in standard waveform mode, shifting period is 160ms up to 5.1s. Initial value of circular shift register must be written in CSRCFG.DATA, the direction is defined by CSRCFG.DIR bit (0 for left, 1 for right) and circular shift register operation is started by writing a one to CR.CSTART. Once enabled, data is shifted every TIM.FCx+1 frames, circular shift register is autonomous and system can enter any sleep mode (only 32KHz must be running). Figure 39-9. Wheel Animation Example (8 Segments) circular shift register b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 0 0 0 0 LCD wheel 39.6.10 ASCII Character Mapping LCDCA handles up to four ASCII characters tables, configured in Character Mapping Configuration register (CMCFG). Instead of handling each segments in display memory for a selected digit, user writes ASCII code in Character Mapping Control Register (CMCR) to display the corresponding character. User can then drive several digits with few operations: 1. select the Type of Digit (CMCFG.TDG), see Figure 39-10 on page 1044, 2. write the Start Segment value (CMCFG.STSEG) of the first digit, 3. select Digit Reverse Mode (CMCFG.DREV) if required. If DREV is one, segment index is decremented, 4. then write ASCII code in CMCR register. If digit uses contiguous segments, repeat step 4 to update remaining digits. Segment index is updated automatically according to the number of segment used in the digit and DREV value. 1043 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 39-10. Type of Digit Supported 7-Segment - 3 COM term. - 3 SEG term. 7-Segment - 4 COM term. - 2 SEG term. 14-Segment - 4 COM term. - 4 SEG term. 16-Segment - 3 COM term. - 6 SEG term. Character mapping saves CPU execution time and allows a fast return to sleep mode after display update. 1044 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 39-8. 7-segments character table 1045 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 39-9. 14-segments character table 1046 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 39-10. 16-segments character table 1047 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.6.11 Automated Character Mapping Displaying predefined character strings can be automated using the Peripheral DMA Controller (PDCA). Two modes are available, defined by MODE bit in Automated Character Mapping Configuration register (ACMCFG): • MODE=0, the sequential character string display mode is selected • MODE=1, the scrolling of character string display mode is selected 39.6.11.1 Sequential Characters String Display This mode displays characters of a string periodically (frame basis). The configuration is: • specify the number of digits to display (ACMCFG.DIGN), • specify the type of digit (ACMCFG.TDG), see ”ASCII Character Mapping” on page 1043, • specify the start segment (ACMCFG.STSEG) of the first character of the string, • select the digit reverse mode (ACMCFG.DREV) if required. This mode is useful if digits have been inverted on the glass (first digit on the right), • set the display period by writing the number of frame between each display in Frame Counter x in TIM register (TIM.FCx), • select a frame counter by writing its number in ACMCFG.FCS, • enable this mode by writing a one to the ACMCFG.EN bit, • configure PDCA to transfer an ASCII character string of any size (should a multiple of the number of digit). To repeat the character string display, repeat the PDCA transfer. TIM.FCx defines the number of frames between each PDCA transfer (display update). Nframes = 8 × ( FCx + 1 ) If frame rate is 50Hz (20ms) in standard waveform mode, characters are displayed with a period from 160ms up to 5.1s. 1048 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 39-11. Sequential Character String Example (DIGN = 5, frame rate = 50Hz, TIM.ACMFC = 31) String = ’HELLOWORLDTHIS IS AUTOMATED ’ H E L L O W O R L D 10.2 T H I S 15.3 I S 20.4 A U T O 25.5 A T E D 0 5.1 M t (s) 39.6.11.2 Scrolling of Characters String This mode displays the same characters string periodically shifted by one character in left direction. The configuration is: • specify the number of digit (ACMCFG.DIGN), • specify the number of scrolling steps ACMCFG.STEPS = string length - DIGN + 1, • specify the type of digit (ACMCFG.TDG), see ”ASCII Character Mapping” on page 1043, • specify the start segment (ACMCFG.STSEG) of the first character to display • select the digit reverse mode (ACMCFG.DREV). If enabled ACMCFG.STSEG must be initialized with the start segment corresponding to the last character on the LCD glass. • set the display period by writing the number of frame in Frame Counter x (TIM.FCx), • select a frame counter by writing its number in ACMCFG.FCS, • enable this mode by writing a one to the ACMCFG.EN bit, • configure PDCA to transfer the ASCII characters string to the Automated Character Mapping Data Register (ACMDR). PDCA must be configured to repeat transfer in order to scroll 1049 42023H–SAM–11/2016 ATSAM4L8/L4/L2 character string. Number of transfer must be a multiple of STEPS to get a complete scrolling of the string. Blank characters can be added to string to create a complete scrolling. The frame counter selected (TIM.FCx) defines the number of frames between each PDCA transfer, refer to ”Sequential Characters String Display” on page 1048 Figure 39-12. Characters String Scrolling Examples (DIGN = 3) String=’HELLO’ (string length=5, STEPS=3) H E L E L L L L H String=’HELLO ‘ (string length=8, STEPS=6) 1 H E L 2 2 E L L O 3 3 L L O E L 1 4 L O E L L 2 5 O L L O 3 6 H E L 1 1 1 H E L step 39.6.12 Automated Bit Mapping Any segment can be modified using the Peripheral DMA Controller, making predefined animations possible. Data can be located in FLASH or RAM and are transferred periodically to the display memory. When PDCA writes to the Automated Bit Mapping Data Register (ABMDR), up to 8 segments can be modified. PDCA must be configured to transfer a word made of: • DATA[7:0], each bit represents the state of a segment, 1050 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • DMASK[7:0], each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to display memory, • OFF[4:0], byte offset in display memory (see Figure 39-3 on page 1036). To update more than 8 segments, PDCA must transfer multiple words before shadow memory is updated. This number of words must also be written in SIZE field in Automated Bit Mapping Configuration register (ABMCFG), it indicates the number of writes in display memory to form a frame. To make an automated animation of N states with M segments, PDCA must be configured to transfer N x SIZE (= M/8 or more) words. Note that if segments are at any position in display memory, DMASK is used then PDCA size can be up to N x M. The display period (animation update) is defined by writing the number of frame in TIM.FCx. The frame counter is selected by writing its number in ABMCFG.FCS. Animation can be repeated if PDCA is configured to repeat the whole transfer. 39.6.13 Contrast Adjustment Contrast is defined by the maximum value of VLCD. The higher value the higher contrast. Fine Contrast value (FCST) in CFG register is a signed value (two’s complement) which defines the maximum voltage VLCD on segment and common terminals. New value takes effect at the beginning of next frame. V LCD = 3 V + ( FCST × 0, 016 V ) 39.6.14 Interrupts LCDCA can generate an interrupt at the beginning of a frame. When Frame Counter 0 Rollover bit (SR.FC0R) is set to one and interrupt is not masked, LCDCA interrupt is pending. Moreover Frame Counter 0 (TIM.FC0) can be used to select the interrupt period generation. This mode can provide a useful time base to update LCD. If TIM.FC0PB=0: Interrupt Period = ( ( TIM.FC0 × 8 ) + 1 ) × Frame Period If TIM.FC0PB=1: Interrupt Period = ( TIM.FC0 + 1 ) × Frame Period Note that in low power waveform mode, frame period is twice the frame period in standard waveform mode. An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one to the corresponding bit in Status Clear Register (SCR). 39.6.15 LCD Wake Up LCD controller can wake up CPU with the interrupt request line. But in sleep modes where APB clocks are off, LCD wake up mechanism must be enabled to wake up CPU. 1051 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Wake up mechanism is enabled by writing a one to the Wake up Enable (WEN) bit in configuration register. It is disabled by writing a one to the Wake up Disable bit (WDIS). Moreover LCDCA interrupt request must not be masked (see previous section) and LCDCA bit in Asynchronous Wake Up Enable register (AWEN.LCDCA) must be set to one (see Power Manager chapter). Wake up signal is generated when frame counter 0 rolls over. When wake up is detected in Power Manager, system clocks are running therefore SR.FC0R is set to one and LCDCA irq is generated. CPU is then woken up. Wake up signal is cleared by disabling wake up mechanism. 39.6.16 LCD Power Supply To operate correctly, LCD controller requires a reference level. The External BIAS bit (XBIAS) in CFG register selects the source of V LCD. If XBIAS is zero, V LCD sources voltages from the internal bandgap reference. Otherwise, V LCD must be powered externally. Note that when using external V LCD, the fine contrast controlled by CFG.FCST is inoperative. Table 39-11. LCD Power Supply Pins SR.EN CFG.XBIAS VLCD BIAS2 BIAS1 CAPH / CAPL 0 x H.Z. H.Z. H.Z. H.Z. 0 VLCD 1/3 VLCD Capacitor Pump Charge 1 Input for VLCD 2/3 VLCD 1 (also in static mode) (also in static mode) - Input for BIAS2 - H.Z. if static bias - Input for BIAS1 - H.Z. if static bias H.Z. Figure 39-13. LCD Power Supply Block Diagram CAPH CAPL x3 BANDGAP Reference Pump Contrast x2 VLCD BIAS2 x1 BIAS1 XBIAS COMy SEGx 1052 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 39-14. Internal and External Bias Generation Internal Generation (static or 1/3 Bias) Device External Generation (static) Device VCC VCC CAPH External Generation (example) (1/3 Bias) Device VCC VCC VCC VCC CAPH CAPH (1) 100 nF CAPL CAPL CAPL Ext. VLCD Ext. VLCD VLCD VLCD (2) VLCD BIASH BIASH 100 nF (1) BIASL BIASL 100 nF BIASH BIASL Decoupling capacitors (1) Decoupling capacitor 100 nF (1) GND GND GND (1) Values are given for design guidance only. (2) Bias generation can be provided by other voltage source than a divison resistor 1053 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7 User Interface Table 39-12. LCDCA Register Memory Map Offset Note: Register Register Name Access Reset CR Write-Only - 0x00 Control Register 0x04 Configuration Register CFG Read/Write 0x00000000 0x08 Timing Register TIM Read/Write 0x00000000 0x0C Status Register SR Read-Only 0x00000000 0x10 Status Clear Register SCR Write-Only - 0x14 Data Register Low 0 DRL0 Read/Write - 0x18 Data Register High 0 DRH0 Read/Write - 0x1C Data Register Low 1 DRL1 Read/Write - 0x20 Data Register High 1 DRH1 Read/Write - 0x24 Data Register Low 2 DRL2 Read/Write - 0x28 Data Register High 2 DRH2 Read/Write - 0x2C Data Register Low 3 DRL3 Read/Write - 0x30 Data Register High 3 DRH3 Read/Write - 0x34 Indirect Access Data Register IADR Write-Only - 0x38 Blink Configuration Register BCFG Read/Write 0x00000000 0x3C Circular Shift Register Configuration CSRCFG Read/Write 0x00000000 0x40 Character Mapping Configuration Register CMCFG Read/Write 0x00000000 0x44 Character Mapping Data Register CMDR Write-Only - 0x48 Automated Character Mapping Configuration Register ACMCFG Read/Write 0x00000000 0x4C Automated Character Mapping Data Register ACMDR Write-Only - 0x50 Automated Bit Mapping Configuration Register ABMCFG Read/Write 0x00000000 0x54 Automated Bit Mapping Data Register ABMDR Write-Only - 0x58 Interrupt Enable Register IER Write-Only - 0x5C Interrupt Disable Register IDR Write-Only - 0x60 Interrupt Mask Register IMR Read-Only 0x00000000 0x64 Version Register VERSION Read-Only -(1) 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of this chapter. 1054 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.1 Name: Control Register CR Access Type: Write-Only Offset: 0x00 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CSTOP CSTART BSTOP BSTART WEN WDIS CDM 7 6 5 4 3 2 1 0 FC2EN FC2DIS FC1EN FC1DIS FC0EN FC0DIS EN DIS Writing a zero to a bit in this register has no effect. • CSTOP: Circular Shift Stop Writing a one to this bit stops circular shift register. • CSTART: Circular Shift Start Writing a one to this bit starts circular shift register. • BSTOP: Blinking Stop Writing a one to this bit stops blinking. • BSTART: Blinking Start Writing a one to this bit starts blinking. • WEN: Wake up Enable Writing a one to this bit enables wake up mechanism. • WDIS: Wake up Disable Writing a one to this bit disables wake up mechanism. • CDM: Clear Display Memory Writing a one to this bit clears immediately the display memory. • FC2EN: Frame Counter 2 Enable Writing a one to this bit enables the frame counter 2. • FC2DIS: Frame Counter 2 Disable Writing a one to this bit disables the frame counter 2. • FC1EN: Frame Counter 1 Enable Writing a one to this bit enables the frame counter 1. • FC1DIS: Frame Counter 1 Disable Writing a one to this bit disables the frame counter 1. • FC0EN: Frame Counter 0 Enable Writing a one to this bit enables the frame counter 0. • FC0DIS: Frame Counter 0 Disable Writing a one to this bit disables the frame counter 0. • EN: Enable Writing a one to this bit enables the LCD controller. 1055 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • DIS: Disable Writing a one to this bit disables the LCD controller. 1056 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.2 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 - - 23 22 - - 15 14 13 12 - - - 7 6 - - 27 26 25 24 18 17 16 11 10 9 8 - - - 5 4 3 2 1 0 - - LOCK BLANK WMOD XBIAS NSU 21 20 19 FCST DUTY NSU, DUTY, WMOD and XBIAS shall not be modified when LCDCA is enabled (SR.EN=1). • NSU: Number of Segment Terminals in Use This field indicates the number of segment terminals in use. It prevents any activity on muxes driving the unused segment terminals. • FCST: Fine Contrast Defines the maximum voltage VLCD on segment and common terminals. FCST is a signed number (two's complement). New value takes effect at the beginning of next frame. VLCD = 3.0 V + (FCST[5:0] * 0.016 V) • DUTY: Duty Select This field defines the duty cycle. Table 39-13. Duty Selection DUTY[1:0] Duty Bias COM pins Used 00 1/4 1/3 COM[0:3] 01 Static Static COM0 10 1/2 1/3 COM[0:1] 11 1/3 1/3 COM[0:2] • LOCK: Lock 0: Shadow display memory is unlocked. 1: Shadow display memory is locked and can’t be updated. • BLANK: Blank LCD 0: LCD segments value is defined in shadow display memory. 1: Turns OFF all LCD segments. • WMOD: Waveform Mode 0: low power waveform mode. 1: standard waveform mode. 1057 42023H–SAM–11/2016 ATSAM4L8/L4/L2 If this bit is modified during display operation the waveform mode is applied at the beginning of next frame. • XBIAS: External Bias Generation 0:Internal bias is used. 1:External bias is used. 1058 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.3 Name: Timing Register TIM Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 • • • • • 31 30 29 28 - - - 23 22 21 - - - 15 14 13 - - FC0PB 7 6 5 4 - - - - 27 26 25 24 17 16 9 8 1 0 FC2 20 19 18 FC1 12 11 10 FC0 3 2 CLKDIV PRESC CLKDIV and PRESC shall not be modified when LCD controller is enabled. FCx shall not be modified when Frame Counter x is enabled. FC2: Frame Counter 2 Number of frame before rollover = ((FC2 * 8) + 1). FC1: Frame Counter 1 Number of frame before rollover = ((FC1 * 8) + 1). FC0PB: Frame Counter 0 Prescaler Bypass 0: FC Prescaler is not bypassed 1: FC Prescaler is bypassed FC0: Frame Counter 0 Number of frame before rollover = ((FC0 * 8) + 1) if FC0PB=0 else (FC0 + 1). CLKDIV: LCD Clock Division Defines the LCD frame rate. F ( clk LCD ) FrameRate = ---------------------------------------------------------------------------------------------------( 1 – WMOD ) ( K × N × ( 1 + CLKDIV ) × 2 ) K = 8 for 1/4, 1/2 and static duty. K = 6 for 1/3 duty. • PRESC: LCD Prescaler Select 0: N = 8 1: N = 16 1059 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.4 Name: Status Register SR Access Type: Read-Only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - CPS 7 6 5 4 3 2 1 0 CSRS BLKS WEN EN FC2S FC1S FC0S FC0R • CPS: Charge Pump Status 0: Charge pump is inactive or not ready. 1: Charge pump is ready. • CSRS: Circular Shift Register Status 0: CSR is not running. 1: CSR is running. • BLKS: Blink Status 0: Blinking is not running. 1: Blinking is running. • WEN: Wake up Status 0: Wake up mechanism is disabled. 1: Wake up mechanism is enabled. • EN: LCDCA Status 0: LCD controller is disabled. 1: LCD controller is enabled. • FC2S: Frame Counter 2 Status 0: Frame counter 2 is stopped. 1: Frame counter 2 is running. • FC1S: Frame Counter 1 Status 0: Frame counter 1 is stopped. 1: Frame counter 1 is running. • FC0S: Frame Counter 0 Status 0: Frame counter 0 is stopped. 1: Frame counter 0 is running. • FC0R: Frame Counter 0 Rollover This bit is set when frame counter 0 rollover. This bit is cleared when corresponding bit SCR is written to one. 1060 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.5 Name: Status Clear Register SCR Access Type: Write-Only Offset: 0x10 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - FC0R Writing a zero to a bit in this register has no effect. Writing a one to a bit clears the corresponding SR bit. 1061 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.6 Name: Data Register Low DRLx Access Type: Read/Write Offset: 0x14+8*x Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] Display memory is not initialized at startup. • DATA: Segments Value Each bit defines the segment value in display memory. 1062 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.7 Name: Data Register High DRHx Access Type: Read/Write Offset: 0x18+8*x Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 DATA • DATA: Segments Value Each bit defines the segment value in display memory. 1063 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.8 Name: Indirect Access Data Register IADR Access Type: Write-Only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 OFF 12 11 10 9 8 3 2 1 0 DMASK 7 6 5 4 DATA • OFF: Byte Offset Byte offset in display memory. • DMASK: Data Mask Each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to display memory. • DATA: Segments Value Each bit defines the segment value. 1064 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.9 Name: Blink Configuration Register BCFG Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 1 0 BSS1 BSS0 7 6 5 4 3 - - - - - 2 FCS MODE • BSS1: Blink Segment Selection 1 If BSS1[x] is set, segment connected to SEG1/COMx is selected. • BSS0: Blink Segment Selection 0 If BSS0[x] is set, segment connected to SEG0/COMx is selected. • FCS: Frame Counter Selection Table 39-14. Frame Counter Selection FCS Frame Counter 00 FC0 01 FC1 10 FC2 11 reserved • MODE: Blinking Mode 0: All segments are allowed to blink. 1: Selected segments are allowed to blink. 1065 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.10 Name: Circular Shift Register Configuration CSRCFG Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 DATA 7 6 - - 5 4 SIZE FCS DIR • DATA: Circular Shift Register Value • SIZE: Size Defines the size of the circular shift register, (SIZE + 1) bits. • FCS: Frame Counter Selection Table 39-15. Frame Counter Selection FCS Frame Counter 00 FC0 01 FC1 10 FC2 11 reserved • DIR: Direction 0: Left shifting. 1: Right shifting. 1066 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.11 Name: Character Mapping Configuration Register CMCFG Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - 7 6 5 4 3 2 1 0 - - - - - STSEG TDG DREV • STSEG: Start Segment Defines the first segment terminal used to write the decoded display. • TDG: Type of Digit Table 39-16. Type of Digit TDG Digit 00 7-segment with 3 common terminals, COM[2:0] 01 7-segment with 4 common terminals, COM[3:0] 10 14-segment with 4 common terminals, COM[3:0] 11 16-segment with 3 common terminals, COM[2:0] • DREV: Digit Reverse Mode 0: Digit reverse mode is disabled. 1: Digit reverse mode is enabled. 1067 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.12 Name: Character Mapping Data Register CMDR Access Type: Write-Only Offset: 0x44 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - ASCII • ASCII: ASCII Code 1068 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.13 Name: Automated Character Mapping Configuration Register ACMCFG Access Type: Read/Write Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 26 25 24 DIGN 19 18 17 16 11 10 9 8 2 1 0 STEPS 15 14 - - 7 6 - 13 12 STSEG 5 TDG 4 3 DREV MODE FCS EN • DIGN: Digit Number Defines the number of digit used (must be >1). • STEPS: Scrolling Steps Defines the number of steps in scrolling mode. STEPS = string length - DIGN + 1. • STSEG: Start Segment Defines the first segment terminal used to write the decoded display. • TDG: Type of Digit Table 39-17. Type of Digit TDG Digit 00 7-segment with 3 common terminals, COM[2:0] 01 7-segment with 4 common terminals, COM[3:0] 10 14-segment with 4 common terminals, COM[3:0] 11 16-segment with 3 common terminals, COM[2:0] • DREV: Digit Reverse 0: Digit reverse mode is disabled. 1: Digit reverse mode is enabled. • MODE: Mode 0: Sequential. 1: Scrolling. 1069 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • FCS: Frame Counter Selection Table 39-18. Frame Counter Selection FCS Frame Counter 00 FC0 01 FC1 10 FC2 11 reserved • EN: Enable 0: Automated character mapping is disabled. 1: Automated character mapping is enabled. 1070 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.14 Name: Automated Character Mapping Data Register ACMDR Access Type: Write-Only Offset: 0x4C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - ASCII • ASCII: ASCII Code 1071 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.15 Name: Automated Bit Mapping Configuration Register ABMCFG Access Type: Read/Write Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - 7 6 5 4 3 1 0 - - - - - SIZE 2 FCS EN • SIZE: Size Defines the number of PDCA writes to ABMDR to form a frame (must be >1). • FCS: Frame Counter Selection Table 39-19. Frame Counter Selection FCS Frame Counter 00 FC0 01 FC1 10 FC2 11 reserved • EN: Enable 0: Automated bit mapping is disabled. 1: Automated bit mapping is enabled. 1072 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.16 Name: Automated Bit Mapping Data Register ABMDR Access Type: Write-Only Offset: 0x54 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 OFF 12 11 10 9 8 3 2 1 0 DMASK 7 6 5 4 DATA • OFF: Byte Offset Byte offset in display memory. • DMASK: Data Mask Each bit is a mask for DATA field. When DMASK[x]=1, DATA[x] is not written to display memory. • DATA: Segments Value Each bit defines the segment value. 1073 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.17 Name: Interrupt Enable Register IER Access Type: Write-Only Offset: 0x58 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - FC0R Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 1074 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.18 Name: Interrupt Disable Register IDR Access Type: Write-Only Offset: 0x5C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - FC0R Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 1075 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.19 Name: Interrupt Mask Register IMR Access Type: Read-Only Offset: 0x60 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 - - - - 15 14 13 12 - - - - 7 6 5 4 - - - - 27 26 25 24 - - - 18 17 16 - - - 10 9 8 - - - 3 2 1 0 - - - FC0R 19 11 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 1076 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.7.20 Name: Module Version VERSION Access Type: Read-Only Offset: 0x64 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 1077 42023H–SAM–11/2016 ATSAM4L8/L4/L2 39.8 Module Configuration The specific configuration for LCDCA is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. ”Power Manager (PM)” on page 109 for details. Table 39-20. LCDCA Clocks Clock Name Description CLK_LCDCA LCDCA bus interface clock CLK_LCD LCD 32kHz clock Table 39-21. Register Reset Values Register Reset Value VERSION 0x00000100 1078 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 39-22. LCDCA Pinout vs Packages Pin Cluster Package TQFP100 TQFP64/QFN64 TQFP48/QFN48 PA12 COM0 COM0 COM0 PA11 COM1 COM1 COM1 PA10 COM2 COM2 COM2 PA09 COM3 COM3 COM3 PC15 SEG0 PC16 SEG1 PC17 SEG2 PC18 SEG3 PC19 SEG4 PA13 SEG5 SEG0 SEG0 PA14 SEG6 SEG1 SEG1 PA15 SEG7 SEG2 SEG2 PA16 SEG8 SEG3 SEG3 SEG9 SEG4 SEG4 PA17 A PC20 SEG10 PC21 SEG11 PC22 SEG12 PC23 SEG13 PB08 SEG14 SEG5 PB09 SEG15 SEG6 PB10 SEG16 SEG7 PB11 SEG17 SEG8 PA18 SEG18 SEG9 SEG5 PA19 SEG19 SEG10 SEG6 PA20 SEG20 SEG11 SEG7 PB07 SEG21 SEG12 PB06 SEG22 SEG13 PA08 SEG23 SEG14 SEG8 1079 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 39-22. LCDCA Pinout vs Packages Pin Cluster Package TQFP100 PC24 SEG24 PC25 SEG25 PC26 SEG26 PC27 TQFP64/QFN64 TQFP48/QFN48 SEG27 B PC28 SEG28 PC29 SEG29 PC30 SEG30 PC31 SEG31 PB12 SEG32 SEG15 PB13 SEG33 SEG16 PA21 SEG34 SEG17 SEG9 SEG35 SEG18 SEG10 PB14 SEG36 SEG19 PB15 SEG37 SEG20 PA23 SEG38 SEG21 SEG11 PA24 SEG39 SEG22 SEG12 PA22 C 1080 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40. Parallel Capture (PARC) Rev: 1.0.0.0 40.1 Features • • • • • 40.2 Captures 8-bits data with external input clock External data enables supported Various enable conditions Peripheral DMA supported Peripheral events supported Overview The Parallel Capture peripheral samples an external 8-bit bus with an external input clock. It can be connected to a CMOS digital image sensor, an ADC, a DSP synchronous port,... The number of PARC modules implemented is device specific. Refer to the Module Configuration section for details. 40.3 Block Diagram Figure 40-1. PARC Block Diagram Events PCCK PEVC Buffer Peripheral Bus CPU / PDCA I/O Controller RHR PCDATA[7:0] PCEN1 PCEN2 PARC 40.4 I/O Lines Description Table 40-1. 40.5 I/O Lines Description Pin Name Pin Description Type PCCK Clock Input PCD[7:0] Data Input PCEN1 Data Enable 1 Input PCEN2 Data Enable 2 Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 1081 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.5.1 I/O Lines The PARC pins are multiplexed with other peripherals. The user must first configure the I/O Controller to give control of the pins to the PARC. 40.5.2 Power Management PARC stops functioning when the system enters a sleep mode that disables its clock. 40.5.3 Clocks The clock for PARC (CLK_PARC) is generated by the Power Manager. It can be disabled either manually through the user interface of the Power Manager or automatically when the system enters a sleep mode that disables the clocks to the peripheral bus modules. For correct behavior, CLK_PARC frequency must be at least twice the PCCK frequency. 40.5.4 DMA The PARC DMA handshake interface is connected to the Peripheral DMA Controller (PDCA). Using the PARC DMA functionality requires the PDCA to be configured first. 40.5.5 Interrupt The PARC interrupt request line is connected to the NVIC. Using the PARC interrupt requires the NVIC to be configured first. 40.5.6 40.6 40.6.1 Peripheral Events The PARC peripheral events are connected via the Peripheral Event System. Refer to Section 31. ”Peripheral Event Controller (PEVC)” on page 845 for details. Functional Description Capture Operation PARC is enabled by writing a one to the Enable bit in the Control Register (CR.EN). Data capture is enabled by writing a one to the Start bit in the Control Register (CR.START) and stopped by writing a one to the Stop bit in the Control Register (CR.STOP). Data capture is made by sampling the data bus PCD[7:0] on the rising or falling edge of the PCCK input clock then re-synchronized to the PB clock domain. PCCK sampling edge is selected with EDGE bit in the Configuration Register (CFG.EDGE). User can select a sampling condition to capture the data. There are four modes defined by Sampling Mode field (CFG.SMODE): when PCEN1 is high, when PCEN1 and PCEN2 are high, when PCEN1 or PCEN2 is high and in last mode data is sampled without condition. Data can be captured every two cycles if CFG.HALF bit is set to one. It can be used, for example, to capture the luminance Y of a CMOS digital image sensor. In addition, bit CFG.ODD specifies which of odd or even bytes are captured. Considering that first byte captured (byte 0), after reset, is an even byte. Captured data are stored in the Receive Holding Register (RHR). Concatenated data can also be stored in RHR to make a 16-bit or a 32-bit data, with the first byte received in LSB position. Concatenated data size is configured by Data Size bit in CFG register (CFG.DSIZE). When the configured data bytes are captured, the Data Ready bit is set to one in the Status Register (SR.DRDY). DRDY is also set to one when internal buffer is not full but CR.STOP is set to one or stop event occurs (see “Peripheral Events” ). 1082 42023H–SAM–11/2016 ATSAM4L8/L4/L2 An overrun condition is detected if RHR is not read before internal buffer is full. Data in RHR is corrupted and Overrun bit is set to one in the Status Register (SR.OVR). 40.6.2 Peripheral DMA PARC can be associated to a Peripheral DMA Controller (PDCA) channel. It will then perform data transfer from PARC to a memory buffer without any CPU intervention (see PDCA chapter for channel configuration). PDCA and PARC data size must be equal, if CFG.DSIZE is 32-bit PDCA must be configured to read 32-bit data size. PARC requests data transfer when internal buffer is full. When data capture is disabled (with CR.STOP), PARC requests a last data transfer if internal buffer contains at least one byte. 40.6.3 Peripheral Events Data capture can be enabled or disabled by peripheral events if Event Mode is enabled (CFG.EMODE). Start event enables the data capture whereas stop event disables it. 40.6.4 Interrupt Generation PARC has two interrupt sources, Data Ready (DRDY) and Overrun (OVR). The status of each interrupt source can be read from the Status Register. An interrupt request will be generated if a bit in SR and the corresponding bit in the Interrupt Mask Register (IMR) are set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one to the corresponding bit in the Interrupt Status Clear Register (ICR). The interrupt sources are ORed together to make one interrupt request which remains active until all interrupt bits in SR are cleared. 1083 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 40-2. Parallel Capture Waveforms CLK_PARC PCCK PCD[7:0] 0x01 0x12 0x23 0x34 0x45 0x56 0x67 0x78 0x89 0x9A PCEN1 PCEN2 RHR (1) 0x01 0x12 0x23 0x34 0x45 0x56 0x67 RHR (2) 0x01 0x12 0x23 0x34 0x45 0x56 0x67 RHR (3) 0x01 RHR (4) 0x23 0x12 RHR (5) 0x45 0x34 0x34231201 0x78 0x89 0x9A 0x78 0x67 0x56 0x78 0x78675645 (1) DSIZE=0, ALWYS=1, HALFS=0, ODD=0 (2) DSIZE=0, ALWYS=0, HALFS=0, ODD=0 (3) DSIZE=0, ALWYS=0, HALFS=1, ODD=0 (4) DSIZE=0, ALWYS=0, HALFS=1, ODD=1 (5) DSIZE=2, ALWYS=0, HALFS=0, ODD=0 1084 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7 User Interface Table 40-2. Note: PARC Register Memory Map Offset Register Register Name Access Reset 0x00 Configuration Register CFG Read/Write 0x00000000 0x04 Control Register CR Read/Write 0x00000000 0x08 Interrupt Enable Register IER Write-only 0x00000000 0x0C Interrupt Disable Register IDR Write-only 0x00000000 0x10 Interrupt Mask Register IMR Read-only 0x00000000 0x14 Status Register SR Read-only 0x00000000 0x18 Interrupt Status Clear Register ICR Write-only 0x00000000 0x1C Receive Holding Register RHR Read 0x00000000 0x20 Version Register VERSION Read-only -(1) 1. The reset values for these registers are device specific. Refer to the Module Configuration section at the end of this chapter. 1085 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.1 Name: Configuration Register CFG Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ODD HALF EDGE EMODE SMODE DSIZE To avoid unexpected behavior CFG must be written when PARC is disabled. • ODD: Odd Capture 0: only bytes with even index are captured. 1: only bytes with odd index are captured. • HALF: Half Capture 0: all bytes are captured. 1: one out of two bytes are captured. • EDGE: Sampling Edge Select 0: rising edge. 1: falling edge. • EMODE: Events Mode 0: Events mode disabled. 1: Events mode enabled. Peripheral events start/stop data capture. • SMODE: Sampling Mode SMODE Mode 0 0 Capture data if PCEN1 is high 0 1 Capture data if PCEN1 and PCEN2 are high 1 0 Capture data if PCEN1 or PCEN2 is high 1 1 Always capture data 1086 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • DSIZE: Data Size DSIZE Size 0 0 data size in RHR is a byte (8-bit) 0 1 data size in RHR is a half-word (16-bit) 1 0 data size in RHR is a word (32-bit) 1 1 data size in RHR is a word (32-bit) 1087 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.2 Name: Control Register CR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - STOP START DIS EN • STOP: Stop Capture Writing a zero to this bit has no effect. Writing a one to this bit disables data capture. This bit always reads as zero. • START: Start Capture Writing a zero to this bit has no effect. Writing a one to this bit enables data capture. This bit always reads as zero. • DIS: Disable Writing a zero to this bit has no effect. Writing a one to this bit disables PARC. This bit always reads as zero. • EN: Enable Writing a zero to this bit has no effect. Writing a one to this bit enables PARC. This bit always reads as zero. 1088 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 1089 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 1090 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 1091 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.6 Name: Status Register SR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY CS EN • OVR: Overrun 0: No overrun error occurred since last read of RHR. 1: At least one overrun error occurred since last read of RHR. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when a new byte has been captured and previous data in RHR has not been read. • DRDY: Data Ready 0: No data is ready in RHR. 1: A new data is ready. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when a new data is captured (according to CR.DSIZE). • CS: Capture Status 0: PARC is not in capture mode. 1: PARC is in capture mode. • EN: Enable Status 0: PARC is disabled. 1: PARC is enabled. 1092 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.7 Name: Interrupt Status Clear Register ICR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - OVR DRDY - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 1093 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.8 Name: Receive Holding Register RHR Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 CDATA[31:24] 23 22 21 20 19 CDATA[23:16] 15 14 13 12 CDATA[15:8] 7 6 5 4 CDATA[7:0] • CDATA: Captured Data Captured data size is defined by CR.DSIZE. 1094 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.7.9 Name: Version Register VERSION Access Type: Read-only Offset: 0x20 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 1095 42023H–SAM–11/2016 ATSAM4L8/L4/L2 40.8 Module Configuration The specific configuration for each PARC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. “Power Manager (PM)” on page 109 for details. Table 40-3. PARC Clock Name Module Name Clock Name Description PARC CLK_PARC Peripheral clock for PARC Table 40-4. Register Reset Values Register Reset Value VERSION 0x00000100 1096 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41. Cyclic Redundancy Check Calculation Unit (CRCCU) Rev: 2.0.2.0 41.1 Features • Performs Cyclic Redundancy Check Operation on Memory Area • Single AHB Master Interface • APB Configuration Interface 41.2 Overview The CRCCU performs CRC check on memory area. 41.3 Block Diagram Figure 41-1. CRCCU Block Diagram APB Interface CLK_CRCCU_APB AHB DMA CRC irq CLK_CRCCU_AHB 41.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 41.4.1 Power Management CRCCU stops functioning when the system enters a sleep mode that disables its clock. CRCCU resumes operation after the system wakes up from sleep mode. 41.4.2 Clocks CRCCU clocks (CLK_CRCCU_APB, CLK_CRCCU_AHB) are generated by the Power Manager. they can be disabled either manually through the user interface of the Power Manager or automatically when the system enters a sleep mode that disables the clocks to the peripheral bus modules. 41.4.3 Interrupts The CRCCU interrupt request line is connected to the NVIC. Using the CRCCU interrupt requires the NVIC to be configured first. 41.4.4 Debug Operation When an external debugger forces the CPU into debug mode, CRCCU continues normal operation. If the CRCCU is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 1097 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.5 Functional Description Once configured (Mode Register, MR) and enabled by writing a one to MR.ENABLE, the CRC engine performs a checksum computation from memory data. CRC computation is performed from LSB to MSB bit. Three different polynomials (CCIT802.3, CASTAGNOLI, CCIT16) can be configured in MR.PTYPE. CRCCU uses its own DMA mechanism to read memory area (Flash or RAM area). DMA uses a descriptor located in memory area. Descriptor location is defined by the Descriptor Base Address Register (DSCR). Figure 41-2. CRCCU Descriptor Memory area DSCR ADDR DSCR+0x04 CTRL reserved reserved DSCR+0x10 CRC data1 data2 data3 ... Once enabled (DMAEN register), DMA reads descriptor to get instructions: • ADDR returns the address of memory area to compute, • CTRL.TRWIDTH indicates the transfer size (byte, halfword or word), • CTRL.BTSIZE indicates the buffer size, • CTRL.IEN enables the transfer-complete interrupt. Then reads data located at ADDR and CRC engine computes the checksum. The CRC result is available in Status Register (SR). BTSIZE is automatically decremented after each read. When BTSIZE is zero, DMA is stopped and the status bit DMASR in DMASR register is set to zero. If MR.COMPARE is set to one, CRC register in descriptor is compared with the last CRC computed. If a mismatch occurs, the error bit ERRISR in ISR register is set to one and interrupt is generated (if not masked, see IER/IDR/IMR register). CRCCU makes single access (TRWIDTH size) to memory in order to limit the bandwidth usage. The field DIVIDER in MR can be used to lower the bandwidth by dividing the frequency of single accesses. The transfer request frequency is then divided by 2^(DIVIDER+1). 1098 42023H–SAM–11/2016 ATSAM4L8/L4/L2 To compute CRC for a memory size larger than 256Kbytes of for non-contiguous memory area, CRCCU can be enabled again for a new memory area. CRC will be updated accordingly. Conversely, set CR.RESET to one to reset the intermediate CRC to its default value (0xFFFFFFFF). 1099 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6 User Interface Table 41-1. CRCCU Register Memory Map Offset Notes: Register Register Name Access Reset DSCR Read/Write 0x00000000 0x00 Descriptor Base Register 0x08 DMA Enable Register DMAEN Write-only - 0x0C DMA Disable Register DMADIS Write-only - 0x10 DMA Status Register DMASR Read-only 0x00000000 0x14 DMA Interrupt Enable Register DMAIER Write-only - 0x18 DMA Interrupt Disable Register DMAIDR Write-only - 0x1C DMA Interrupt Mask Register DMAIMR Read-only 0x00000000 0x20 DMA Interrupt Status Register DMAISR Read-only 0x00000000 0x34 Control Register CR Write-only - 0x38 Mode Register MR Read/Write 0x00000000 0x3C Status Register SR Read-only 0xFFFFFFFF 0x40 Interrupt Enable Register IER Write-only - 0x44 Interrupt Disable Register IDR Write-only - 0x48 Interrupt Mask Register IMR Read-only 0x00000000 0x4C Interrupt Status Register ISR Read-only 0x00000000 0xFC Version Register VERSION Read-only -(1) 1. The reset value is device specific. Refer to the Module Configuration section at the en of this chapter. Table 41-2. CRCCU Register Memory Map (RAM) Offset Register Register Name Access Reset DSCR Address Register ADDR Read/Write - DSCR + 0x04 Control Register CTRL Read/Write - DSCR + 0x10 CRC Reference Register CRC Read/Write - 1100 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.1 Name: Descriptor Base Address Register DSCR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DSCR[22:15] 23 22 21 20 DSCR[14:7] 15 14 13 12 DSCR[6:0] - 7 6 5 4 3 2 1 0 - - - - - - - - • DSCR: Description Base Address Address of CRC descriptor (512-byte aligned). 1101 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.2 Name: DMA Enable Register DMAEN Access Type: Write-only Offset: 0x08 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAEN • DMAEN: DMA Enable Write a one to enable DMA channel. Writing a zero has no effect. 1102 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.3 Name: DMA Disable Register DMADIS Access Type: Write-only Offset: 0x0C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMADIS • DMADIS: DMA Disable Write a one to disable DMA channel. Writing a zero has no effect. 1103 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.4 Name: DMA Status Register DMASR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMASR • DMASR: DMA Channel Status 0: DMA channel is disabled. 1: DMA channel is enabled. 1104 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.5 Name: DMA Interrupt Enable Register DMAIER Access Type: Write-only Offset: 0x14 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAIER • DMAIER: DMA Interrupt Enable Write a one to enable DMA interrupt. Writing a zero has no effect. 1105 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.6 Name: DMA Interrupt Disable Register DMAIDR Access Type: Write-only Offset: 0x18 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAIDR • DMAIDR: DMA Interrupt Disable Write a one to disable DMA interrupt. Writing a zero has no effect. 1106 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.7 Name: DMA Interrupt Mask Register DMAIMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAIMR • DMAIMR: DMA Interrupt Mask Status 0: DMA interrupt is disabled. 1: DMA interrupt is enabled. 1107 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.8 Name: DMA Interrupt Status Register DMAISR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - DMAISR • DMAISR: DMA Interrupt Status 0: No DMA transfer or in-progress. 1: DMA transfer is completed. This bit is set to zero when DMAISR is read. 1108 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.9 Name: Control Register CR Access Type: Write-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - RESET • RESET: Reset CRCComputation Write a one to reset SR. Writing a zero has no effect. 1109 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.10 Name: Mode Register MR Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 COMPARE ENABLE DIVIDER PTYPE • DIVIDER: Bandwidth Divider DMA bandwidth, required for CRC computation, is divided by 2^(DIVIDER+1). • PTYPE: Polynomial Type Value Name Description 0 CCIT8023 Polynom 0x04C11DB7 1 CASTAGNOLI Polynom 0x1EDC6F41 2 CCIT16 Polynom 0x1021 • COMPARE: CRC Compare 0: No comparison. 1: CRC computed is compared with stored value. • ENABLE: CRC Computation Enable 0: No computation. 1: CRC computation enabled. 1110 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.11 Name: Status Register SR Access Type: Read-only Offset: 0x3C Reset Value: 0xFFFFFFFF 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRC[31:24] 23 22 21 20 CRC[23:16] 15 14 13 12 CRC[15:8] 7 6 5 4 CRC[7:0] • CRC: Cyclic Redundancy Check Value CRC computation result. If MR.COMPARE=1, SR is not readable. 1111 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.12 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x40 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRIER Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR 1112 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.13 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x44 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRIDR Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR 1113 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.14 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRIMR 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 1114 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.15 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - ERRISR • ERRISR: CRC Error Interrupt Status 0: No CRC error 1: CRC error, CRC computed and CRC stored are different. ERRISR is cleared when this register is read. 1115 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.16 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 - - - - 7 6 5 4 VARIANT 10 9 8 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 1116 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.17 Name: Transfer Address Register ADDR Access Type: Read/Write Offset: DSCR Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR[31:24] 23 22 21 20 ADDR[23:16] 15 14 13 12 ADDR[15:8] 7 6 5 4 ADDR[7:0] • ADDR: Transfer Address Address of memory block to compute. 1117 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.18 Name: Transfer Control Register CTRL Access Type: Read/Write Offset: DSCR + 0x04 Reset Value: - 31 30 29 28 27 26 25 24 - - - - IEN - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 TRWIDTH BTSIZE[15:8] 0 BTSIZE[7:0] • IEN: Interrupt Mask Enable 0: Interrupt is enabled 1: Interrupt is masked • TRWIDTH: Transfer Width TRWIDTH Size 00 Byte 01 Halfword 10 Word • BTSIZE: Buffer Transfer Size Buffer Transfert Size 1118 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.6.19 Name: Transfer Reference Register CRC Access Type: Read/Write Offset: DSCR + 0x10 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 REFCRC[31:24] 23 22 21 20 19 REFCRC[23:16] 15 14 13 12 11 REFCRC[15:8] 7 6 5 4 3 REFCRC[7:0] • REFCRC: Reference CRC When compare mode is enabled, checksum is compared with this register. 1119 42023H–SAM–11/2016 ATSAM4L8/L4/L2 41.7 Module Configuration The specific configuration for each CRCCU instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to Section 10. “Power Manager (PM)” on page 109 for details. Table 41-3. CRCCU Clock Name Clock Name Description CLK_CRCCU_APB Clock for the CRCCU bus interface CLK_CRCCU_AHB Clock for the CRCCU AHB interface Register Reset Value VERSION 0x00000202 1120 42023H–SAM–11/2016 ATSAM4L8/L4/L2 42. Electrical Characteristics 42.1 Absolute Maximum Ratings* Table 42-1. Absolute Maximum Ratings Operating temperature .................................... -40°C to +85°C *NOTICE: Storage temperature ...................................... -60°C to +150°C Voltage on input pins with respect to ground ..........................-0.3V to VVDD (1)+0.3V Total DC output current on all I/O pins VDDIO ......................................................................... 120 mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Total DC output current on all I/O pins VDDIN ........................................................................ 100 mA Total DC output current on all I/O pins VDDANA........................................................................ 50 mA Maximum operating voltage VDDIO, VDDIN .................... 3.6V 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3-5 on page 13 for details 42.2 Operating Conditions All the electrical characteristics are applicable to the following conditions unless otherwise specified : – operating voltage range 1,68V to 3,6V for VDDIN, VDDIO & VDDANA – Power Scaling 0 and 2 modes – operating temperature range: TA = -40°C to 85°C and for a junction temperature up to TJ = 100°C. Typical values are base on TA = 25°c and VDDIN,VDDIO,VDDANA = 3,3V unless otherwise specified 42.3 Supply Characteristics Table 42-2. Supply Characteristics Voltage Symbol VVDDIO, VVDDIN, VVDDANA Conditions Min PS1 (FCPU12MHz) Linear mode 1.8 Switching mode 1. Max Unit 3.6 V 2.0 (1) Below 2.3V, linear mode is more power efficient than switching mode. Refer to Section 5. ”Power and Startup Considerations” on page 43 for details about Power Supply 1121 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-3. Supply Rise Rates and Order (1) VDDIO, VDDIN and VDDANA must be connected together and as a consequence, rise synchronously Rise Rate Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 0.0001 2.5 V/µs VVDDIN DC supply peripheral I/Os and internal regulator 0.0001 2.5 V/µs VVDDANA Analog supply voltage 0.0001 2.5 V/µs 1. Comment These values are based on characterization. These values are not covered by test limits in production. 1122 42023H–SAM–11/2016 ATSAM4L8/L4/L2 42.4 Maximum Clock Frequencies Table 42-4. Maximum Clock Frequencies in Power Scaling Mode 0/2 and RUN Mode Symbol Parameter Description Max fCPU CPU clock frequency 48 fPBA PBA clock frequency 48 fPBB PBB clock frequency 48 fPBC PBC clock frequency 48 fPBD PBD clock frequency 48 fGCLK0 GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 50 fGCLK1 GCLK1 clock frequency DFLLIF dithering and SSG reference, GCLK1 pin 50 fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 20 fGCLK3 GCLK3 clock frequency CATB, GCLK3 pin 50 fGCLK4 GCLK4 clock frequency FLO and AESA 50 fGCLK5 GCLK5 clock frequency GLOC, TC0 and RC32KIFB_REF 80 fGCLK6 GCLK6 clock frequency ABDACB and IISC 50 fGCLK7 GCLK7 clock frequency USBC 50 fGCLK8 GCLK8 clock frequency TC1 and PEVC[0] 50 fGCLK9 GCLK9 clock frequency PLL0 and PEVC[1] 50 fGCLK10 GCLK10 clock frequency ADCIFE 50 fGCLK11 GCLK11 clock frequency Master generic clock. Can be used as source for other generic clocks 150 Oscillator 0 in crystal mode 30 fOSC0 OSC0 output frequency Oscillator 0 in digital clock mode 50 fPLL PLL output frequency Phase Locked Loop 240 fDFLL DFLL output frequency Digital Frequency Locked Loop 220 fRC80M RC80M output frequency Internal 80MHz RC Oscillator 80 Units MHz 1123 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-5. Maximum Clock Frequencies in Power Scaling Mode 1 and RUN Mode Symbol Parameter Description Max fCPU CPU clock frequency 12 fPBA PBA clock frequency 12 fPBB PBB clock frequency 12 fPBC PBC clock frequency 12 fPBD PBD clock frequency 12 fGCLK0 GCLK0 clock frequency DFLLIF main reference, GCLK0 pin 16.6 fGCLK1 GCLK1 clock frequency DFLLIF dithering and SSGreference, GCLK1 pin 16.6 fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 6.6 fGCLK3 GCLK3 clock frequency CATB, GCLK3 pin 17.3 fGCLK4 GCLK4 clock frequency FLO and AESA 16.6 fGCLK5 GCLK5 clock frequency GLOC, TC0 and RC32KIFB_REF 26.6 fGCLK6 GCLK6 clock frequency ABDACB and IISC 16.6 fGCLK7 GCLK7 clock frequency USBC 16.6 fGCLK8 GCLK8 clock frequency TC1 and PEVC[0] 16.6 fGCLK9 GCLK9 clock frequency PLL0 and PEVC[1] 16.6 fGCLK10 GCLK10 clock frequency ADCIFE 16.6 fGCLK11 GCLK11 clock frequency Master generic clock. Can be used as source for other generic clocks 51.2 fOSC0 OSC0 output frequency fPLL Oscillator 0 in crystal mode 16 Oscillator 0 in digital clock mode 16 PLL output frequency Phase Locked Loop N/A fDFLL DFLL output frequency Digital Frequency Locked Loop N/A fRC80M RC80M output frequency Internal 80MHz RC Oscillator N/A Units MHz 1124 42023H–SAM–11/2016 ATSAM4L8/L4/L2 42.5 42.5.1 Power Consumption Power Scaling 0 and 2 The values in Table 42-6 are measured values of power consumption under the following conditions, except where noted: • Operating conditions for power scaling mode 0 and 2 – VVDDIN = 3.3V – Power Scaling mode 0 is used for CPU frequencies under 36MHz – Power Scaling mode 2 is used for CPU frequencies above 36MHz • Wake up time from low power modes is measured from the edge of the wakeup signal to the first instruction fetched in flash. • Oscillators – OSC0 (crystal oscillator) stopped – OSC32K (32kHz crystal oscillator) running with external 32kHz crystal – DFLL using OSC32K as reference and running at 48MHz • Clocks – DFLL used as main clock source – CPU, AHB clocks undivided – APBC and APBD clocks divided by 4 – APBA and APBB bridges off – The following peripheral clocks running • PM, SCIF, AST, FLASHCALW, APBC and APBD bridges – All other peripheral clocks stopped • I/Os are inactive with internal pull-up • CPU is running on flash with 1 wait state • Low power cache enabled • BOD18 and BOD33 disabled Table 42-6. ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 0 and 2 Mode Conditions TA CPU running a Fibonacci algorithm Linear mode 25°C Typical Wakeup Time Typ Max (1) 296 326 300 332 320 377 326 380 177 198 179 200 186 232 195 239 Unit N/A 85°C CPU running a CoreMark algorithm Linear mode 25°C CPU running a Fibonacci algorithm Switching mode 25°C CPU running a CoreMark algorithm Switching mode 25°C N/A 85°C RUN µA/MHz N/A 85°C 85°C N/A 1125 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-6. ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 0 and 2 Max (1) 3817 4033 3934 4174 2341 2477 2437 2585 1758 1862 1847 1971 51 60 5.9 8.7 4.7 7.6 3.1 5.1 AST and OSC32K stopped 2.2 4.2 OSC32K running AST running at 1kHz 1.5 3.1 AST and OSC32K stopped 0.9 1.7 Conditions SLEEP0 Switching mode TA 25°C 85°C 25°C SLEEP1 Switching mode 85°C 25°C SLEEP2 Switching mode 85°C SLEEP3 Typical Wakeup Time Typ Mode 9 * Main clock cycles 9 * Main clock cycles + 500ns 9 * Main clock cycles + 500ns Linear mode OSC32K and AST running Fast wake-up enable WAIT µA 1.5µs OSC32K and AST stopped Fast wake-up enable OSC32K running AST running at 1kHz RETENTION BACKUP 1. Unit 25°C 1.5µs These values are based on characterization. These values are not covered by test limits in production. Table 42-7. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2 Mode Conditions TA CPU running a Fibonacci algorithm Linear mode 25°C Typical Wakeup Time Typ Max (1) 319 343 326 350 343 387 351 416 181 198 186 203 192 232 202 239 Unit N/A 85°C CPU running a CoreMark algorithm Linear mode 25°C CPU running a Fibonacci algorithm Switching mode 25°C CPU running a CoreMark algorithm Switching mode 25°C N/A 85°C RUN µA/MHz N/A 85°C 85°C N/A 1126 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-7. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 0 and 2 Mode Conditions TA SLEEP0 Switching mode 25°C 85°C 25°C SLEEP1 Switching mode 85°C 25°C SLEEP2 Switching mode 85°C SLEEP3 Typical Wakeup Time 9 * Main clock cycles 9 * Main clock cycles + 500ns 9 * Main clock cycles + 500ns Linear mode OSC32K and AST running Fast wake-up enable 3817 4033 4050 4507 2341 2477 2525 2832 1758 1862 1925 1971 51 60 Unit µA 1.5µs OSC32K and AST stopped Fast wake-up enable RETENTION BACKUP 42.5.2 Max (1) 6.7 WAIT 1. Typ OSC32K running AST running at 1kHz 5.5 25°C 3.9 1.5µs AST and OSC32K stopped 3.0 OSC32K running AST running at 1kHz 1.5 3.1 AST and OSC32K stopped 0.9 1.7 These values are based on characterization. These values are not covered by test limits in production. Power Scaling 1 The values in Table 34-7 are measured values of power consumption under the following conditions, except where noted: • Operating conditions for power scaling mode 1 – VVDDIN = 3.3V • Wake up time from low power modes is measured from the edge of the wakeup signal to the first instruction fetched in flash. • Oscillators – OSC0 (crystal oscillator) and OSC32K (32kHz crystal oscillator) stopped – RCFAST Running at 12MHz • Clocks – RCFAST used as main clock source – CPU, AHB clocks undivided – APBC and APBD clocks divided by 4 – APBA and APBB bridges off – The following peripheral clocks running • PM, SCIF, AST, FLASHCALW, APBC and APBD bridges 1127 42023H–SAM–11/2016 ATSAM4L8/L4/L2 – All other peripheral clocks stopped • I/Os are inactive with internal pull-up • CPU is running on flash with 1 wait state • Low power cache enabled • BOD18 and BOD33 disabled Table 42-8. ATSAM4L4/2 Current consumption and Wakeup time for power scaling mode 1 Mode Typical Wakeup Time Typ Max (1) 205 224 212 231 213 244 230 270 95 112 100 119 100 128 107 138 527 627 579 739 369 445 404 564 305 381 334 442 Linear mode 46 55 OSC32K and AST running Fast wake-up enable 4.7 7.5 3.5 6.3 2.6 4.8 AST and OSC32K stopped 1.5 4 OSC32K running AST running at 1kHz 1.5 3.1 AST and OSC32K stopped 0.9 1.7 Conditions TA CPU running a Fibonacci algorithm Linear mode 25°C N/A 85°C CPU running a CoreMark algorithm Linear mode 25°C CPU running a Fibonacci algorithm Switching mode 25°C CPU running a CoreMark algorithm Switching mode 25°C N/A 85°C µA/MHz RUN Switching mode 25°C Switching mode 85°C 25°C SLEEP2 Switching mode 85°C SLEEP3 N/A 85°C 85°C SLEEP1 N/A 85°C 25°C SLEEP0 WAIT 9 * Main clock cycles 9 * Main clock cycles + 500ns 9 * Main clock cycles + 500ns µA 1.5µs OSC32K and AST stopped Fast wake-up enable RETENTION BACKUP 1. Unit OSC32K running AST running at 1kHz 25°C 1.5µs These values are based on characterization. These values are not covered by test limits in production. 1128 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-9. ATSAM4L8 Current consumption and Wakeup time for power scaling mode 1 Mode Conditions TA CPU running a Fibonacci algorithm Linear mode 25°C Typical Wakeup Time Typ Max (1) 222 240 233 276 233 276 230 270 100 112 100 119 104 128 107 138 527 627 579 739 369 445 404 564 305 381 334 442 46 55 N/A 85°C CPU running a CoreMark algorithm Linear mode 25°C CPU running a Fibonacci algorithm Switching mode 25°C CPU running a CoreMark algorithm Switching mode 25°C N/A 85°C µA/MHz RUN Switching mode 25°C Switching mode 85°C 25°C SLEEP2 Switching mode 85°C SLEEP3 N/A 85°C 85°C SLEEP1 N/A 85°C 25°C SLEEP0 9 * Main clock cycles 9 * Main clock cycles + 500ns 9 * Main clock cycles + 500ns Linear mode OSC32K and AST running Fast wake-up enable 5.5 WAIT µA 1.5µs OSC32K and AST stopped Fast wake-up enable RETENTION BACKUP 1. Unit OSC32K running AST running at 1kHz 4.3 25°C 3.4 1.5µs AST and OSC32K stopped 2.3 OSC32K running AST running at 1kHz 1.5 3.1 AST and OSC32K stopped 0.9 1.7 These values are based on characterization. These values are not covered by test limits in production. Table 42-10. Typical Power Consumption running CoreMark on CPU clock sources (1) Clock Source Conditions Regulator Frequency (MHz) Typ Unit 1129 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-10. Typical Power Consumption running CoreMark on CPU clock sources (1) RCSYS (MCSEL = 0) Power scaling mode 1 0.115 978 0.5 354 12 114 12 228 30 219 0.6 292 12 111 12 193 50 194 40 188 50 185 Power scaling mode 0 Input Freq = 32kHz from OSC32K 20 214 Power scaling mode 2 Input Freq = 32kHz from OSC32K 50 195 RC1M (MCSEL = 4) Power scaling mode 1 1 267 RCFAST (MCSEL = 5) Power scaling mode 1 RCFAST frequency is configurable from 4 to 12MHz 4 153 12 114 RC80M (MCSEL = 6) Power scaling mode 2 fCPU = RC80M / 2 = 40MHz 40 211 Power scaling mode 1 OSC0 (MCSEL = 1) Power scaling mode 0 OSC0 (MCSEL = 1) External Clock (MODE=0) PLL (MCSEL = 2) DFLL (MCSEL = 3) 1. Power scaling mode 1 Power scaling mode 0 Power scaling mode 2 Power scaling mode 2 Input Freq = 4MHz from OSC0 Switching Mode µA/MHz These values are based on characterization. These values are not covered by test limits in production. 1130 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Figure 42-1. Typical Power Consumption running Coremark (from above table) Note: For variable frequency oscillators, linear interpolation between high and low settings Figure 42-2. Measurement Schematic, Switching Mode VDDIN VDDANA VDDIO VDDOUT Amp 0 VDDCORE 1131 42023H–SAM–11/2016 ATSAM4L8/L4/L2 42.5.3 Peripheral Power Consumption in Power Scaling mode 0 and 2 The values in Table 42-11 are measured values of power consumption under the following conditions: • Operating conditions, internal core supply (Figure 42-2) – VVDDIN = 3.3V – VVDDCORE supplied by the internal regulator in switching mode • TA = 25°C • Oscillators – OSC0 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) running with external 32KHz crystal – DFLL running at 48MHz with OSC32K as reference clock • Clocks – DFLL used as main clock source – CPU, AHB, and PB clocks undivided • I/Os are inactive with internal pull-up • Flash enabled in high speed mode • CPU in SLEEP0 mode • BOD18 and BOD33 disabled Consumption active is the added current consumption when the module clock is turned on. 1132 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-11. Typical Current Consumption by Peripheral in Power Scaling Mode 0 and 2 (1) Peripheral IISC 1.0 SPI 1.9 TC 6.3 TWIM 1.5 TWIS 1.2 USART Unit 8.5 (2) 42.5.4 Typ Consumption Active ADCIFE 3.1 DACC 1.3 ACIFC (2) 3.1 GLOC 0.4 ABDACB 0.7 TRNG 0.9 PARC 0.7 CATB 3.0 LCDCA 4.4 PDCA 1.0 CRCCU 0.3 USBC 1.5 PEVC 5.6 CHIPID 0.1 SCIF 6.4 FREQM 0.5 GPIO 7.1 BPM 0.9 BSCIF 4.6 AST 1.5 WDT 1.4 EIC 0.6 PICOUART 0.3 µA/MHz 1. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies 2. Includes the current consumption on VDDANA and ADVREFP. .Peripheral Power Consumption in Power Scaling mode 1 The values in Table 42-13 are measured values of power consumption under the following conditions: 1133 42023H–SAM–11/2016 ATSAM4L8/L4/L2 • Operating conditions, internal core supply (Figure 42-2) – VVDDIN = 3.3V – VVDDCORE = 1.2 V, supplied by the internal regulator in switching mode • TA = 25°C • Oscillators – OSC0 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) running with external 32KHz crystal – RCFAST running @ 12MHz • Clocks – RCFAST used as main clock source – CPU, AHB, and PB clocks undivided • I/Os are inactive with internal pull-up • Flash enabled in normal mode • CPU in SLEEP0 mode • BOD18 and BOD33 disabled Consumption active is the added current consumption when the module clock is turned on 1134 42023H–SAM–11/2016 ATSAM4L8/L4/L2 Table 42-12. Typical Current Consumption by Peripheral in Power Scaling Mode 1 (1) Peripheral Typ Consumption Active IISC 0.5 SPI 1.1 TC 3.1 TWIM 0.8 TWIS 0.7 USART Unit 4.4 (2) ADCIFE 1.6 DACC 0.6 ACIFC (2) 1.6 GLOC 0.1 ABDACB 0.3 TRNG 0.3 PARC 0.3 CATB 1.5 LCDCA 2.2 PDCA 0.4 CRCCU 0.3 USBC 0.9 PEVC 2.8 CHIPID 0.1 SCIF 3.1 FREQM 0.2 GPIO 3.4 BPM 0.4 BSCIF 2.3 AST 0.8 WDT 0.8 EIC 0.3 PICOUART 0.2 µA/MHz 1. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies 2. Includes the current consumption on VDDANA and ADVREFP. 1135 42023H–SAM–11/2016 ATSAM4L8/L4/L2 42.6 I/O Pin Characteristics 42.6.1 Normal I/O Pin Table 42-13. Normal I/O Pin Characteristics (1) Symbol RPULLUP Parameter Pull-up resistance Conditions Min (2) (2) Typ Max 40 kΩ 40 kΩ RPULLDOWN Pull-down resistance VIL Input low-level voltage -0.3 0.2 * VVDD VIH Input high-level voltage 0.8 * VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage Output low-level current VVDD - 0.4 (3) ODCR0=1 ODCR0=0 IOH Output high-level current (3) ODCR0=1 OSRR0=0 OSRR0=1 tRISE Rise time(2) OSRR0=0 OSRR0=1 OSRR0=0 OSRR0=1 tFALL Fall time(2) OSRR0=0 OSRR0=1 OSRR0=0 FPINMAX Output frequency(2) OSRR0=1 OSRR0=0 OSRR0=1 ILEAK Input leakage current(3) CIN Input capacitance(2) V 0.4 ODCR0=0 IOL Units 1.68V