SAM4N8 / SAM4N16
Atmel | SMART ARM-based MCU
DATASHEET
Description
The Atmel ® | SMART SAM4N series is a member of a family of Flash
microcontrollers based on the high performance 32-bit ARM® Cortex®-M4 RISC
processor. It operates at a maximum speed of 100 MHz and features up to 1024
Kbytes of Flash and up to 80 Kbytes of SRAM. The peripheral set includes 3
USARTs, 4 UARTs, 3 TWIs, 1 SPI, as well as 1 PWM timer, 2 three-channel
general-purpose 16-bit timers (with stepper motor and quadrature decoder logic
support), a low-power RTC, a low-power RTT, 256-bit general purpose backup
registers, a 10-bit ADC (up to 12-bit with digital averaging) and a 10-bit DAC with
an internal voltage reference.
The SAM4N devices have three software-selectable low-power modes: Sleep,
Wait and Backup. In Sleep mode, the processor is stopped while all other
functions can be kept running. In Wait mode, all clocks and functions are stopped
but some peripherals can be configured to wake up the system based on
predefined conditions. In Backup mode, only the RTC, RTT, and wake-up logic
are running.
The Real-time Event Managment allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM4N device is a medium range general purpose microcontroller with the
best ratio in terms of reduced power consumption, processing power and
peripheral set. This enables the SAM4N to sustain a wide range of applications
including industrial automation and M2M (machine-to-machine), energy metering,
consumer and appliance, building and home control.
It operates from 1.62V to 3.6V and is available in 48, 64, and 100-pin QFP, 48 and
64-pin QFN, and 100-ball BGA packages.
The SAM4N series offers pin-to-pin compatibility with Atmel SAM4S, SAM3S,
SAM3N and SAM7S devices, facilitating easy migration within the portfolio.
The SAM4N series is the ideal migration path from the SAM4S for applications
that require a reduced BOM cost.
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
1.
2
Features
Core
̶ ARM Cortex-M4 running at up to 100 MHz
̶ Memory Protection Unit (MPU)
̶ Thumb®-2 instruction Set
Pin-to-pin compatible with SAM3N, SAM3S products (48/64/100-pin versions), SAM4S (64/100-pin versions)
and SAM7S legacy products (64-pin version)
Memories
̶ Up to 1024 Kbytes embedded Flash
̶ Up to 80 Kbytes embedded SRAM
̶ 8 Kbytes ROM with embedded boot loader routines (UART) and IAP routines, single-cycle access at maximum
speed
System
̶ Embedded voltage regulator for single supply operation
̶ Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
̶ Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power
32.768 kHz for RTC or device clock
̶ High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup.
In-application trimming access for frequency adjustment
̶ Slow Clock Internal RC oscillator as permanent low-power mode device clock
̶ PLL up to 240 MHz for device clock
̶ Temperature Sensor
̶ Up to 23 peripheral DMA (PDC) channels
Low-power Modes
̶ Sleep, Wait, and Backup modes, down to 0.7 µA in Backup mode with RTC, RTT, and GPBR
Peripherals
̶ Up to 3 USARTs with ISO7816, IrDA (only USART0), RS-485, and SPI Mode
̶ Up to 4 two-wire UARTs
̶ Up to 3 Two-wire Interfaces (TWI)
̶ 1 SPI
̶ 2 Three-channel 16-bit Timer Counter blocks with capture, waveform, compare and PWM mode, Quadrature
Decoder Logic and 2-bit Gray Up/Down for Stepper Motor
̶ 1 Four-channel 16-bit PWM
̶ 32-bit low-power Real-time Timer (RTT) and low-power Real-time Clock (RTC) with calendar and alarm features
̶ 256-bit General Purpose Backup Registers (GPBR)
I/Os
̶ Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and ondie Series Resistor Termination. Individually Programmable Open-drain, Pull-up and Pull-down resistor and
Synchronous Output
̶ Three 32-bit Parallel Input/Output Controllers
Analog
̶ One 10-bit ADC up to 510 ksps, with Digital Averaging Function providing Enhanced Resolution Mode up to 12bit, up to 16-channels
̶ One 10-bit DAC up to 1 msps
̶ Internal voltage reference, 3V typ
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
1.1
Packages
̶ 100-lead LQFP – 14 x 14 mm, pitch 0.5 mm
̶ 100-ball TFBGA – 9 x 9 mm, pitch 0.8 mm
̶ 100-ball VFBGA – 7 x 7 mm, pitch 0.65 mm
̶ 64-lead LQFP – 10 x 10 mm, pitch 0.5 mm
̶ 64-pad QFN – 9 x 9 mm, pitch 0.5 mm
̶ 48-lead LQFP – 7 x7 mm, pitch 0.5 mm
̶ 48-pad QFN – 7 x 7 mm, pitch 0.5 mm
Configuration Summary
The SAM4N series devices differ in memory size, package and features. Table 1-1 summarizes the configurations
of the device family.
Table 1-1.
Configuration Summary
Feature
SAM4N16C
SAM4N16B
SAM4N8C
SAM4N8B
SAM4N8A
Flash
1024 Kbytes
1024 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
SRAM
80 Kbytes
80 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Package
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
LQFP100
TFBGA100
VFBGA100
LQFP64
QFN64
LQFP48
QFN48
Number of PIOs
79
47
79
47
34
(1)
10-bit ADC
17 ch
10-bit DAC
1 ch
11 ch
(1)
1 ch
1 ch
11 ch
(1)
1 ch
–
6
6
6
6
6(5)
PDC Channels
23
23
23
23
23
USART/UART
3/4
2/4
3/4
2/4
1/4
(3)
(3)
(3)
(3)
2(3)
Notes:
4
3
4
(2)
9 ch (1)
16-bit Timer
SPI
(2)
17 ch
(1)
3
TWI
3
3
3
3
3
PWM
7(4)
4(4)
7(4)
4(4)
4(4)
1.
2.
3.
4.
5.
Includes Temperature Sensor
Only 3 channels output
USARTs with SPI mode are taken into account.
Timer Counter in PWM mode is taken into account
Only 2 channels output
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
3
4
2.
Block Diagram
See Table 1-1 for detailed configurations of memory size, package and features of the SAM4N devices.
UT
DO
VD
VD
DI
N
TD
I
TD
O
TM
S
TC /S
K/ WD
SW IO
CL
JT
K
AG
SE
L
SAM4N 100-pin Version Block Diagram
System Controller
TST
XIN
XOUT
Voltage
Regulator
3–20 MHz
Oscillator
PCK[2:0]
JTAG and Serial Wire
RC Oscillator
4/8/12 MHz
Flash
Unique ID
In-Circuit Emulator
PMC
Cortex-M4 Processor
fMAX 100 MHz
PLL
ROM
SRAM
8 Kbytes
80 Kbytes
64 Kbytes
1024 Kbytes
512 Kbytes
S
S
S
Flash
24-bit SysTick Counter
NVIC
WKUP[15:0]
SUPC
XIN32
XOUT32
32K Osc
ERASE
32K RC
8 GPBR
RTC
RTT
M
M
POR
3-layer Bus Matrix
fMAX 100 MHz
RSTC
NRST
SM
S
WDT
M
PDC
Peripheral Bridge
PIO A/B/C
PIO
Timer
Counter
0
Timer
Counter
1
10-bit
ADC
10-bit
DACC
PDC
SPI
PWM
Temp.
Sensor
PW
M
0.
.3
3x
USART
PDC
DA
DA C0
TR
G
M
IS
M O
O
S
NP SP I
CS CK
0.
.3
X
UT D3
XD
3
UR
X
UT D0
XD ..2
0.
.2
UR
UART3
PDC
PDC
PI PI
O OD
DC 0
PI EN ..7
O 1
DC ..2
CL
K
TC
LK
TI 0.
O .2
TI A0.
O .2
B0
..2
TC
LK
TI 3.
O .5
TI A3.
O .5
B3
..5
AD
T
AD RG
0.
.1
5
UART0
UART1
UART2
3x
TWI
PDC
P
PDC
EF
PDC
SC
K
TX 0..2
D
RX 0..
D 2
RT 0..
S 2
CT 0..
S0 2
..2
PDC
VR
VDDPLL
VDDIO
VDDCORE
I/D
S
AD
RTCOUT0
MPU
Tamper Detection
TW
TW D
0
CK ..2
0.
.2
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 2-1.
3.
Signals Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1.
Signal Name
Signal Description List
Function
Type
Active
Level
Voltage
Reference
Comments
Power Supplies
VDDIO
Peripherals I/O Lines Power Supply
Power
1.62V to 3.6V
VDDIN
Voltage Regulator, ADC and DAC Power
Supply
Power
1.6V to 3.6V
VDDOUT
Voltage Regulator Output
Power
1.2V Output
VDDPLL
Oscillator Power Supply
Power
1.08V to 1.32V
VDDCORE
Core Chip Power Supply
Power
1.08V to 1.32V
Connected externally to
VDDOUT
GND
Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
Output
PCK0–PCK2
Programmable Clock Output
Output
VDDIO
Output
Input
VDDIO
ICE and JTAG
TCK
Test Clock
Input
VDDIO
No pull-up resistor
TDI
Test Data In
Input
VDDIO
No pull-up resistor
TDO
Test Data Out
Output
VDDIO
TRACESWO
Trace Asynchronous Data Out
Output
VDDIO
SWDIO
Serial Wire Input/Output
I/O
VDDIO
SWCLK
Serial Wire Clock
Input
VDDIO
TMS
Test Mode Select
Input
VDDIO
No pull-up resistor
JTAGSEL
JTAG Selection
Input
High
VDDIO
Pull-down resistor
High
VDDIO
Pull-down (15 kΩ) resistor
Low
VDDIO
Pull-up resistor
VDDIO
Pull-down resistor
Flash Memory
ERASE
Flash and NVM Configuration Bits Erase
Command
Input
Reset/Test
NRST
Microcontroller Reset
TST
Test Mode Select
I/O
Input
Universal Asynchronous Receiver Transmitter - UARTx
URXDx
UART Receive Data
Input
UTXDx
UART Transmit Data
Output
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
5
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
Reference
Comments
PIO Controller - PIOA - PIOB - PIOC
PA0–PA31
Parallel IO Controller A
I/O
VDDIO
Pulled-up input at reset
PB0–PB14
Parallel IO Controller B
I/O
VDDIO
Pulled-up input at reset
PC0–PC31
Parallel IO Controller C
I/O
VDDIO
Pulled-up input at reset
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
Output
Input
Timer Counter - TCx
TCLKx
TC Channel x External Clock Input
Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller - PWMC
PWM
PWM Waveform Output for channel
Output
Serial Peripheral Interface - SPI
MISO
Master In Slave Out
I/O
MOSI
Master Out Slave In
I/O
SPCK
SPI Serial Clock
I/O
NPCS0
SPI Peripheral Chip Select 0
I/O
Low
NPCS1–NPCS3
SPI Peripheral Chip Select
Output
Low
Two-wire Interface - TWIx
TWDx
TWIx Two-wire Serial Data
I/O
TWCKx
TWIx Two-wire Serial Clock
I/O
Analog
ADVREFP
(1)
ADC and DAC Reference
Analog
10-bit Analog-to-Digital Converter - ADC
AD0–AD15
Analog Inputs
Analog
ADTRG
ADC Trigger
Input
Digital-to-Analog Converter - DAC
DAC0
DAC Channel Analog Output
DACTRG
DAC Trigger
6
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Analog
Input
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Voltage
Reference
Comments
Fast Flash Programming Interface - FFPI
PGMEN0–PGMEN2
Programming Enabling
Input
VDDIO
PGMM0–PGMM3
Programming Mode
Input
VDDIO
PGMD0–PGMD15
Programming Data
I/O
VDDIO
PGMRDY
Programming Ready
Output
High
VDDIO
PGMNVALID
Data Direction
Output
Low
VDDIO
PGMNOE
Programming Read
Input
Low
VDDIO
PGMCK
Programming Clock
Input
PGMNCMD
Programming Command
Input
Note:
VDDIO
Low
VDDIO
1. “ADVREFP” is named “ADVREF” in Section 17. “Supply Controller (SUPC)” and in Section 34. “Analog-to-Digital Converter
(ADC)”.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
7
4.
Package and Pinout
SAM4N devices are pin-to-pin compatible with SAM3N4.
Table 4-1.
4.1
SAM4N Packages
Device
100 Pins/Balls
64 Pins/Balls
48 Pins/Balls
SAM4N16
LQFP, TFBGA and VFBGA
LQFP and QFN
–
SAM4N8
LQFP, TFBGA and VFBGA
LQFP and QFN
LQFP and QFN
Overview of the 100-lead LQFP Package
Figure 4-1.
Orientation of the 100-lead LQFP Package
75
51
76
50
100
26
1
25
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
4.2
Overview of the 100-ball TFBGA Package
The 100-ball TFBGA package respects the Green Standards.
Figure 4-2.
Orientation of the 100-ball TFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
BALL A1
A
B
C
D
E
F
G
H
J
K
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
8
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
4.3
Overview of the 100-ball VFBGA Package (7 x 7 x 1 mm - 0.65 mm ball pitch)
The 100-ball VFBGA package respects the Green Standards.
Figure 4-3.
Orientation of the 100-ball VFBGA Package
Top View
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
9
4.4
100-lead LQFP, TFBGA and VFBGA Pinout
Table 4-2.
SAM4N8/16 100-lead LQFP Pinout
1
ADVREFP
26
GND
51
TDI/PB4
76
TDO/TRACESWO/PB5
2
GND
27
VDDIO
52
PA6/PGMNOE
77
JTAGSEL
3
PB0/AD4
28
PA16/PGMD4
53
PA5/PGMRDY
78
PC18
4
PC29/AD13
29
PC7
54
PC28
79
TMS/SWDIO/PB6
5
PB1/AD5
30
PA15/PGMD3
55
PA4/PGMNCMD
80
PC19
6
PC30/AD14
31
PA14/PGMD2
56
VDDCORE
81
PA31
7
PB2/AD6
32
PC6
57
PA27
82
PC20
8
PC31/AD15
33
PA13/PGMD1
58
PC8
83
TCK/SWCLK/PB7
9
PB3/AD7
34
PA24
59
PA28
84
PC21
10
VDDIN
35
PC5
60
NRST
85
VDDCORE
11
VDDOUT
36
VDDCORE
61
TST
86
PC22
12
PA17/PGMD5/AD0
37
PC4
62
PC9
87
ERASE/PB12
13
PC26
38
PA25
63
PA29
88
PB10
14
PA18/PGMD6/AD1
39
PA26
64
PA30
89
PB11
15
PA21/AD8
40
PC3
65
PC10
90
PC23
16
VDDCORE
41
PA12/PGMD0
66
PA3
91
VDDIO
17
PC27
42
PA11/PGMM3
67
PA2/PGMEN2
92
PC24
18
PA19/PGMD7/AD2
43
PC2
68
PC11
93
PB13/DAC0
19
PC15/AD11
44
PA10/PGMM2
69
VDDIO
94
PC25
20
PA22/AD9
45
GND
70
GND
95
GND
21
PC13/AD10
46
PA9/PGMM1
71
PC14
96
PB8/XOUT
22
PA23
47
PC1
72
PA1/PGMEN1
97
PB9/PGMCK/XIN
23
PC12/AD12
48
PA8/XOUT32/PGMM0
73
PC16
98
VDDIO
24
PA20/AD3
49
PA7/XIN32/PGMNVALID
74
PA0/PGMEN0
99
PB14
25
PC0
50
VDDIO
75
PC17
100
VDDPLL
10
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 4-3.
SAM4N8/16 100-ball TFBGA Pinout
A1
PB1/AD5
C6
TCK/SWCLK/PB7
F1
PA18/PGMD6/AD1
H6
PC4
A2
PC29/AD13
C7
PC16
F2
PC26
H7
PA11/PGMM3
A3
VDDIO
C8
PA1/PGMEN1
F3
VDDOUT
H8
PC1
A4
PB9/PGMCK/XIN
C9
PC17
F4
GND
H9
PA6/PGMNOE
A5
PB8/XOUT
C10
PA0/PGMEN0
F5
VDDIO
H10
TDI/PB4
A6
PB13/DAC0
D1
PB3/AD7
F6
PA27
J1
PC15/AD11
A7
PB11
D2
PB0/AD4
F7
PC8
J2
PC0
A8
PB10
D3
PC24
F8
PA28
J3
PA16/PGMD4
A9
TMS/SWDIO/PB6
D4
PC22
F9
TST
J4
PC6
A10
JTAGSEL
D5
GND
F10
PC9
J5
PA24
B1
PC30
D6
GND
G1
PA21/AD8
J6
PA25
B2
ADVREFP
D7
VDDCORE
G2
PC27
J7
PA10/PGMM2
B3
GND
D8
PA2/PGMEN2
G3
PA15/PGMD3
J8
GND
B4
PB14
D9
PC11
G4
VDDCORE
J9
VDDCORE
B5
PC21
D10
PC14
G5
VDDCORE
J10
VDDIO
B6
PC20
E1
PA17/PGMD5/
AD0
G6
PA26
K1
PA22/AD9
B7
PA31
E2
PC31
G7
PA12/PGMD0
K2
PC13/AD10
B8
PC19
E3
VDDIN
G8
PC28
K3
PC12/AD12
B9
PC18
E4
GND
G9
PA4/PGMNCMD
K4
PA20/AD3
B10
TDO/TRACESWO/
PB5
E5
GND
G10
PA5/PGMRDY
K5
PC5
C1
PB2/AD6
E6
NRST
H1
PA19/PGMD7/
AD2
K6
PC3
C2
VDDPLL
E7
PA29
H2
PA23
K7
PC2
C3
PC25
E8
PA30/AD14
H3
PC7
K8
PA9/PGMM1
C4
PC23
E9
PC10
H4
PA14/PGMD2
K9
PA8/XOUT32/
PGMM0
C5
ERASE/PB12
E10
PA3
H5
PA13/PGMD1
K10
PA7/XIN32/
PGMNVALID
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11
Table 4-4.
SAM4N8/16 100-ball VFBGA Pinout
A1
ADVREFP
C6
PC9
F1
VDDOUT
H6
PA12/PGMD0
A2
VDDPLL
C7
TMS/SWDIO/PB6
F2
PA18/PGMD6/AD1
H7
PA9/PGMM1
A3
PB9/PGMCK/XIN
C8
PA1/PGMEN1
F3
PA17/PGMD5/AD0
H8
VDDCORE
A4
PB8/XOUT
C9
PA0/PGMEN0
F4
GND
H9
PA6/PGMNOE
A5
JTAGSEL
C10
PC16
F5
GND
H10
PA5/PGMRDY
A6
PB11
D1
PB1/AD5
F6
PC26
J1
PA20/AD3
A7
PB10
D2
PC30
F7
PA4/PGMNCMD
J2
PC12/AD12
A8
PC20
D3
PC31
F8
PA28
J3
PA16/PGMD4
A9
PC19
D4
PC22
F9
TST
J4
PC6
A10
TDO/TRACESWO/
PB5
D5
PC5
F10
PC8
J5
PA24
B1
GND
D6
PA29
G1
PC15/AD11
J6
PA25
B2
PC25
D7
PA30/AD14
G2
PA19/PGMD7/AD2
J7
PA11/PGMM3
B3
PB14
D8
GND
G3
PA21/PGMD9/AD8
J8
VDDCORE
B4
PB13/DAC0
D9
PC14
G4
PA15/PGMD3
J9
VDDCORE
B5
PC23
D10
PC11
G5
PC3
J10
TDI/PB4
B6
PC21
E1
VDDIN
G6
PA10/PGMM2
K1
PA23
B7
TCK/SWCLK/PB7
E2
PB3/AD7
G7
PC1
K2
PC0
B8
PA31
E3
PB2/AD6
G8
PC28
K3
PC7
B9
PC18
E4
GND
G9
NRST
K4
PA13/PGMD1
B10
PC17
E5
GND
G10
PA27
K5
PA26
C1
PB0/AD4
E6
GND
H1
PC13/AD10
K6
PC2
C2
PC29/AD13
E7
VDDIO
H2
PA22/AD9
K7
VDDIO
C3
PC24
E8
PC10
H3
PC27
K8
VDDIO
C4
ERASE/PB12
E9
PA2/PGMEN2
H4
PA14/PGMD2
K9
PA8/XOUT32/
PGMM0
C5
VDDCORE
E10
PA3
H5
PC4
K10
PA7/XIN32/
PGMNVALID
12
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
4.5
Overview of the 64-lead LQFP Package
Figure 4-4.
Orientation of the 64-lead LQFP Package
33
48
49
32
64
17
16
1
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
4.6
Overview of the 64-lead QFN Package
Figure 4-5.
Orientation of the 64-lead QFN Package
64
49
1
48
16
33
32
17
TOP VIEW
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
SAM4N8/SAM4N16 [DATASHEET]
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13
4.7
64-lead LQFP and QFN Pinout
Table 4-5.
64-pin SAM4N8/16 Pinout
1
ADVREFP
17
GND
33
TDI/PB4
49
TDO/TRACESWO/PB5
2
GND
18
VDDIO
34
PA6/PGMNOE
50
JTAGSEL
3
PB0/AD4
19
PA16/PGMD4
35
PA5/PGMRDY
51
TMS/SWDIO/PB6
4
PB1/AD5
20
PA15/PGMD3
36
PA4/PGMNCMD
52
PA31
5
PB2/AD6
21
PA14/PGMD2
37
PA27/PGMD15
53
TCK/SWCLK/PB7
6
PB3/AD7
22
PA13/PGMD1
38
PA28
54
VDDCORE
7
VDDIN
23
PA24/PGMD12
39
NRST
55
ERASE/PB12
8
VDDOUT
24
VDDCORE
40
TST
56
PB10
9
PA17/PGMD5/AD0
25
PA25/PGMD13
41
PA29
57
PB11
10
PA18/PGMD6/AD1
26
PA26/PGMD14
42
PA30
58
VDDIO
11
PA21/PGMD9/AD8
27
PA12/PGMD0
43
PA3
59
PB13/DAC0
12
VDDCORE
28
PA11/PGMM3
44
PA2/PGMEN2
60
GND
13
PA19/PGMD7/AD2
29
PA10/PGMM2
45
VDDIO
61
XOUT/PB8
14
PA22/PGMD10/AD9
30
PA9/PGMM1
46
GND
62
XIN/PGMCK/PB9
15
PA23/PGMD11
31
PA8/XOUT32/PGMM0
47
PA1/PGMEN1
63
PB14
16
PA20/PGMD8/AD3
32
PA7/XIN32/XOUT32/
PGMNVALID
48
PA0/PGMEN0
64
VDDPLL
Note: The bottom pad of the QFN package must be connected to ground.
14
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
4.8
Overview of the 48-lead LQFP Package
Figure 4-6.
Orientation of the 48-lead LQFP Package
25
36
37
24
48
13
12
1
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
4.9
Overview of the 48-lead QFN Package
Figure 4-7.
Orientation of the 48-lead QFN Package
48
37
1
36
12
25
24
13
TOP VIEW
Refer to Section 37. “SAM4N Mechanical Characteristics” for mechanical drawings and specifications.
SAM4N8/SAM4N16 [DATASHEET]
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15
4.10
48-lead LQFP and QFN Pinout
Table 4-6.
48-pin SAM4N8 Pinout
1
ADVREFP
13
VDDIO
25
TDI/PB4
37
TDO/TRACESWO/PB5
2
GND
14
PA16/PGMD4
26
PA6/PGMNOE
38
JTAGSEL
3
PB0/AD4
15
PA15/PGMD3
27
PA5/PGMRDY
39
TMS/SWDIO/PB6
4
PB1/AD5
16
PA14/PGMD2
28
PA4/PGMNCMD
40
TCK/SWCLK/PB7
5
PB2/AD6
17
PA13/PGMD1
29
NRST
41
VDDCORE
6
PB3/AD7
18
VDDCORE
30
TST
42
ERASE/PB12
7
VDDIN
19
PA12/PGMD0
31
PA3
43
PB10
8
VDDOUT
20
PA11/PGMM3
32
PA2/PGMEN2
44
PB11
9
PA17/PGMD5/AD0
21
PA10/PGMM2
33
VDDIO
45
XOUT/PB8
10
PA18/PGMD6/AD1
22
PA9/PGMM1
34
GND
46
XIN/P/PB9/GMCK
11
PA19/PGMD7/AD2
23
PA8/XOUT32/PGMM0
35
PA1/PGMEN1
47
VDDIO
12
PA20/AD3
24
PA7/XIN32/PGMNVALID
36
PA0/PGMEN0
48
VDDPLL
Note: The bottom pad of the QFN package must be connected to ground.
16
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
5.
Power Considerations
5.1
Power Supplies
The SAM4N8/16 product has several types of power supply pins:
VDDCORE pins: power the core, including the processor, the embedded memories and the peripherals;
voltage ranges from 1.08V to 1.32V.
VDDIO pins: power the Peripherals I/O lines; voltage ranges from 1.62V to 3.6V.
VDDIN pin: Voltage Regulator, ADC and DAC power supply; voltage ranges from 1.6V to 3.6V for Voltage
Regulator, ADC and DAC.
VDDPLL pin: powers the Main Oscillator; voltage ranges from 1.08V to 1.32V.
5.2
Power-up Considerations
5.2.1
VDDIO Versus VDDCORE
VDDIO must always be higher than or equal to VDDCORE.
VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached VDDCORE(min). The minimum
slope for VDDCORE is defined by (VDDCORE(min) - VT+) / tRST.
If VDDCORE rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 8.8 V/ms.
If VDDCORE is powered by the internal regulator, all power-up considerations are met
Figure 5-1.
VDDCORE and VDDIO Constraints at Startup
Supply (V)
VDDIO
VDDIO(min)
VDDCORE
VDDCORE(min)
VT+
Time (t)
tRST
Core supply POR output
SLCK
5.2.2
VDDIO Versus VDDIN
At power-up, VDDIO needs to reach 0.6 V before VDDIN reaches 1.0 V.
VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5 V).
SAM4N8/SAM4N16 [DATASHEET]
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17
5.3
Voltage Regulator
The SAM4N embeds a core voltage regulator that is managed by the Supply Controller and that supplies the
Cortex-M4 core, internal memories (SRAM, ROM and Flash logic) and the peripherals. An internal adaptive
biasing adjusts the regulator quiescent current depending on the required load current.
For adequate input and output power supply decoupling/bypassing, refer to Table 36-3, “1.2V Voltage Regulator
Characteristics,” on page 795.
5.4
Typical Powering Schematics
The SAM4N8/16 supports a 1.62–3.6 V single supply mode. The internal regulator input connected to the source
and its output feeds VDDCORE. Figure 5-2 shows the power schematics.
As VDDIN powers voltage regulator and ADC/DAC, when the user does not want to use the embedded voltage
regulator, he can disable it by software via the SUPC (note that it is different from backup mode).
Figure 5-2.
Single Supply
VDDIO
Main Supply (1.62–3.6 V)
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDPLL
Note:
18
For temperature sensor, VDDIO needs to be greater than 2.4V.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 5-3.
Core Externally Supplied
Main Supply (1.62–3.6 V)
ADC/DAC Supply (1.62–3.6 V)
VDDIO
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE Supply (1.08–1.32 V)
VDDCORE
VDDPLL
Note:
For temperature sensor, VDDIO needs to be greater than 2.4V.
Figure 5-4 provides an example of the powering scheme when using a backup battery. Since the PIO state is
preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the
PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from
a push button or any signal, see Section 5.7 “Wake-up Sources” for further details.
Figure 5-4.
Core Externally Supplied (Backup Battery)
VDDIO
IOs
Backup battery
ADC, DAC,
Analog Comp.
VDDIN
Main Supply
VDDOUT
Voltage
Regulator
3.3V LDO
VDDCORE
VDDPLL
External wakeup signal
Note: The two diodes provide a “switchover circuit (for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
Note:
For temperature sensor, VDDIO needs to be greater than 2.4V.
SAM4N8/SAM4N16 [DATASHEET]
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19
5.5
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLL. The power management controller can be used to adapt the frequency and to disable the
peripheral clocks.
5.6
Low-power Modes
The SAM4N has the following low-power modes: Backup, Wait, and Sleep.
Note:
The Wait For Event instruction (WFE) of the Cortex-M4 core can be used to enter any of the low-power modes,
however, this may add complexity in the design of application state machines. This is due to the fact that the WFE
instruction goes along with an event flag of the Cortex core (cannot be managed by the software application). The
event flag can be set by interrupts, a debug event or an event signal from another processor. Since it is possible for an
interrupt to occur just before the execution of WFE, WFE takes into account events that happened in the past. As a
result, WFE prevents the device from entering Wait mode if an interrupt event has occurred.
Atmel has made provisions to avoid using the WFE instruction. The workarounds to ease application design are as
follows:
- For Backup mode, switch off the voltage regulator and configure the VROFF bit in the Supply Controller Control
Register (SUPC_CR).
- For Wait mode, configure the WAITMODE bit in the PMC Clock Generator Main Oscillator Register of the Power
Management Controller (PMC)
- For Sleep mode, use the Wait for Interrupt (WFI) instruction.
Complete information is available in Table 5-1 “Low Power Mode Configuration Summary”.
5.6.1
Backup Mode
The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is
performing periodic wake-ups to perform tasks but not requiring fast startup time. Total current consumption is
1 µA typical (VDDIO = 1.8V at 25°C).
The Supply Controller, zero-power power-on reset, RTT, RTC, backup registers and 32 kHz oscillator (RC or
crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are
off.
The SAM4N can be awakened from this mode using the pins WKUP0–15, the supply monitor (SM), the RTT or
RTC wake-up event.
Backup mode can be entered by using the VROFF bit in the Supply Controller Control Register (SUPC_CR) or by
using the WFE instruction. The corresponding procedures are described below.
The procedure to enter Backup mode using the VROFF bit is the following:
Write a 1 to the VROFF bit in SUPC_CR (SUPC_CR.KEY field value must be configured correctly; refer to
Section 17.5.3 “Supply Controller Control Register”).
The procedure to enter Backup mode using the WFE instruction is the following:
1.
Write a 1 to the SLEEPDEEP bit in the Cortex-M4 processor System Control Register (SBC_SCR) (refer to
Section 11.9.1.6 “System Control Register”).
2.
Execute the WFE instruction of the processor.
In both cases, exit from Backup mode happens if one of the following enable wake-up events occurs:
20
Level transition, configurable debouncing on pins WKUPEN0–15
Supply Monitor alarm
RTC alarm
RTT alarm
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
5.6.2
Wait Mode
The purpose of the Wait mode is to achieve very low power consumption while maintaining the whole device in a
powered state for a startup time of less than 10 µs. Current consumption in wait mode is typically 32 µA (total
current consumption) if the internal voltage regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered. From this mode, a fast startup is available.
This mode is entered by setting the WAITMODE bit in the PMC Clock Generator Main Oscillator Register
(CKGR_MOR) in conjunction with configuring the Flash Low Power Mode field (FLPM = 00 or 01) in the PMC Fast
Startup Mode Register (PMC_FSMR) or by the WFE instruction.
The Cortex-M4 is able to handle external events or internal events in order to wake up the core. This is done by
configuring the external lines WKUP0–15 as fast startup wake-up pins (refer to Section 5.8 “Fast Startup”). RTC or
RTT alarm can be used to wake up the CPU.
The procedure to enter Wait mode using the WAITMODE bit is the following:
1.
Select the 4/8/12 MHz fast RC oscillator as source of MCK Clock
2.
Configure the FLPM field in PMC_FSMR
3.
Set Flash wait state to 0
4.
Set the WAITMODE bit in CKGR_MOR
5.
Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR)
The procedure to enter Wait mode using the WFE instruction is the following:
1.
Select the 4/8/12 MHz fast RC oscillator as Main Clock.
2.
Set the FLPM field in the PMC_FSMR.
3.
Set Flash wait state to 0.
4.
Set the LPM bit in the PMC_FSMR.
5.
Execute the WFE instruction of the processor.
In both cases, depending on the value of the field FLPM, the Flash enters one of three different modes:
FLPM = 0 in Standby mode (low consumption)
FLPM = 1 in Deep power-down mode (extra low consumption)
FLPM = 2 in Idle mode. Memory ready for Read access
Table 5-1 summarizes the power consumption, wake-up time and system state in Wait mode.
5.6.3
Sleep Mode
The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode,
only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is
application dependent.
This mode is entered via WFI or WFE instructions with bit LPM = 0 in PMC_FSMR.
The processor can be awakened from an interrupt if the WFI instruction of the Cortex-M4 is used or from an event
if the WFE instruction is used.
5.6.4
Low Power Mode Summary Table
The modes detailed above are the main low power modes. Each part can be set to on or off separately and wakeup sources can be individually configured. Table 5-1 shows a summary of the configurations of the low power
modes.
SAM4N8/SAM4N16 [DATASHEET]
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21
22
Table 5-1.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Mode
Low Power Mode Configuration Summary
SUPC, 32 kHz Osc.,
RTC, RTT, GPBR,
POR
Core Memory
(VDDBU Region) Regulator Peripherals
Mode Entry
VROFF = 1
Backup Mode
Wait Mode
w/Flash in
Standby Mode
ON
OFF
+ SLEEPDEEP = 1
Pins WKUP0–15
SM alarm
RTC alarm
RTT alarm
WAITMODE = 1
+ FLPM = 0
Any event from:
OFF
or
(Not powered) WFE
or
ON
ON
Powered
(Not clocked) WFE
+ SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 0
WAITMODE = 1
+ FLPM = 1
Wait Mode
w/Flash in
Deep Power
Down Mode
or
ON
ON
Potential Wake-up Sources
Powered
(Not clocked) WFE
+ SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 1
- Fast startup through pins
WKUP0–15
- RTC alarm
- RTT alarm
PIO State
Core at while in Low- PIO State at Consumption Wake-up
(2) (3)
Time(1)
Wake-up power Mode
Wake-up
Reset
PIOA &
PIOB &
Previous state
PIOC
saved
Inputs with
pull-ups
0.9 µA typ(4)
< 1 ms
Clocked
back
Previous state
Unchanged
saved
28.4 µA(5)
< 10 µs
Clocked
back
Previous state
Unchanged
saved
23.9 µA(5)
< 100 µs
Clocked
back
Previous state
Unchanged
saved
(6)
(6)
Any event from:
- Fast startup through pins
WKUP0–15
- RTC alarm
- RTT alarm
Entry mode = WFI
WFE
Sleep Mode
Notes:
ON
ON
or
Powered(7)
(Not clocked) WFI
+ SLEEPDEEP = 0
+ LPM = 0
Interrupt only; any enabled
interrupt
Entry mode = WFE
Any enabled interrupt and/or
any event from:
- Fast startup through pins
WKUP0–15
- RTC alarm
- RTT alarm
1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz fast RC
oscillator. The user has to add the PLL startup time if it is needed in the system. The wake-up time is defined as the time taken for wake-up until the first
instruction is fetched.
2. The external loads on PIOs are not taken into account in the calculation.
3. BOD current consumption is not included.
4. Total consumption 0.9 µA typ at 1.8V on VDDIO at 25°C.
5. Total consumption (VDDIO + VDDIN)
6. Depends on MCK frequency.
7. In this mode the core is supplied and not clocked but some peripherals can be clocked.
5.7
Wake-up Sources
The wake-up events allow the device to exit the Backup mode. When a wake-up event is detected, the Supply
Controller performs a sequence which automatically reenables the core power supply and the SRAM power
supply, if they are not already enabled. See Figure 17-4, "Wake-up Sources" on page 311.
5.8
Fast Startup
The SAM4N8/16 allows the processor to restart in a few microseconds while the processor is in Wait mode. A fast
startup can occur upon detection of a low level on one of the 18 wake-up inputs (WKUP0 to 15 + RTC + RTT).
The fast restart circuitry (shown in Figure 25-3, "Fast Start-up Circuitry" on page 401) is fully asynchronous and
provides a fast startup signal to the Power Management Controller. As soon as the fast startup signal is asserted,
the PMC automatically restarts the embedded 4/18/12 MHz fast RC oscillator, switches the master clock on this 4
MHz clock by default and reenables the processor clock.
SAM4N8/SAM4N16 [DATASHEET]
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23
6.
Input/Output Lines
The SAM4N8/16 has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system
I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO
line can be used whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins,
oscillators, erase or analog inputs.
6.1
General Purpose I/O Lines
GPIO lines are managed by PIO controllers. All I/Os have several input or output modes such as pull-up or pulldown, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt.
Programming of these modes is performed independently for each I/O line through the PIO controller user
interface. For more details, refer to Section 27. “Parallel Input/Output (PIO) Controller”.
Some GPIOs can have alternate function as analog input. When the GPIO is set in analog mode, all digital
features of the I/O are disabled.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM4N8/16 embeds high-speed pads. See Section 36.10 “AC Characteristics” for more details.
Each I/O line also embeds an ODT (On-Die Termination) (see Figure 6-1). It consists of an internal series resistor
termination scheme for impedance matching between the driver output (SAM4N) and the PCB track impedance,
preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in
turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between
devices or between boards. In conclusion, ODT helps diminish signal integrity issues.
Figure 6-1.
On-die Termination
Z0 ~ ZO + RODT
ODT
36 Ω Typ.
RODT
Receiver
SAM4 Driver with
ZO ~ 10 Ω
24
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
PCB Track
Z0 ~ 50 Ω
6.2
System I/O Lines
Table 6-1 lists the SAM4N system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup, the default function of
these pins is always used.
Table 6-1.
System I/O Configuration
CCFG_SYSIO
Bit No.
Default Function
after Reset
Other Function
Constraints for
Normal Start
12
ERASE
PB12
Low level at startup(1)
7
TCK/SWCLK
PB7
–
6
TMS/SWDIO
PB6
–
5
TDO/TRACESWO
PB5
–
4
TDI
PB4
–
–
PA7
XIN32
–
–
PA8
XOUT32
–
–
PB9
XIN
–
–
PB8
XOUT
–
Configuration
In Matrix User Interface Registers (Refer
to System I/O Configuration Register in
Section 22. “Bus Matrix (MATRIX)”.)
(2)
(3)
Notes:
1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
user application sets PB12 into PIO mode.
2. Refer to Section 17.4.2 “Slow Clock Generator”.
3. Refer to Section 24.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator”.
6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/TRACESWO, TDI and commonly provided on a standard
20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table
3-1 on page 5.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer
to Section 12. “Debug and Test Features”.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port
is not needed in the end application. Mode selection between SWJ-DP mode (system IO mode) and general IO
mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad
for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it
must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and
enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be
used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to
Section 12. “Debug and Test Features”.
6.3
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4N
series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left
unconnected for normal operations. To enter fast programming mode, see Section 20. “Fast Flash Programming
Interface (FFPI)”. For more on the manufacturing and test mode, refer to Section 12. “Debug and Test Features”.
SAM4N8/SAM4N16 [DATASHEET]
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25
6.4
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset
signal to the external components or asserted low externally to reset the microcontroller. It will reset the core and
the peripherals except the backup region (RTC, RTT and Supply Controller). There is no constraint on the length
of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a
permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read
as logic level 1). The ERASE pin and the ROM code ensure an in-situ re-programmability of the Flash content
without the use of a debug tool. When the security bit is activated, the ERASE pin provides a capability to
reprogram the Flash array. It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left
unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. To avoid unexpected erase at power-up, a
minimum ERASE pin assertion time is required. This time is defined in Table 36-46 "AC Flash Characteristics".
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured
as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted
erasing. Refer to Section 10.2 “Peripherals Signals Multiplexing on I/O Lines” on page 36. Also, if the ERASE pin
is used as a standard I/O output, asserting the pin to low does not erase the Flash.
6.6
Anti-tamper Pins/Low-power Tamper Detection
WKUP0 and WKUP1 generic wake-up pins can be used as anti-tamper pins. Anti-tamper pins detect intrusion, for
example, into a housing box. Upon detection through a tamper switch, automatic, asynchronous and immediate
clear of registers in the backup area will be performed. Anti-tamper pins can be used in all power modes
(Backup/Wait/Sleep/Active). Anti-tampering events can be programmed so that half of the General Purpose
Backup Registers (GPBR) are erased automatically. See Section 17. “Supply Controller (SUPC)” for further
description.
26
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7.
Memories
7.1
Product Mapping
Figure 7-1.
SAM4N8/16 Product Mapping
0x00000000
Address memory space
Code
0x00000000
0x400E0000
System Controller
Boot Memory
Code
Reserved
0x00400000
0x400E0200
Internal Flash
0x20000000
MATRIX
0x00800000
0x400E0400
Internal ROM
PMC
0x00C00000
Internal SRAM
5
0x400E0600
Reserved
UART0
0x1FFFFFFF
0x40000000
Peripherals
0x20000000
8
0x400E0740
CHIPID
Internal SRAM
0x400E0800
SRAM
0x60000000
UART1
9
0x400E0A00
0x20080000
Undefined (Abort)
Reserved
EFC
0x40000000
0xE0000000
6
0x400E0C00
Reserved
Peripherals
0x40000000
0x400E0E00
Reserved
System
PIOA
0x40004000
11
0x400E1000
Reserved
PIOB
0x40008000
0xFFFFFFFF
12
0x400E1200
SPI
PIOC
21
0x4000C000
0x400E1400
Reserved
offset
block
0x40010000
peripheral
ID
(+ : wired-or)
+0x40
+0x80
0x40014000
+0x40
+0x80
TC0
+0x10
TC0
23
TC0
24
TC0
+0x90
TC4
27
TC1
+0x60
TC3
26
TC1
+0x50
TC2
25
TC1
+0x30
TC1
13
SYSC
RSTC
1
SYSC
SYSC
SUPC
RTT
3
SYSC
WDT
4
SYSC
RTC
2
SYSC
GPBR
0x400E1600
TC5
Reserved
28
0x40018000
0x4007FFFF
TWI0
19
0x4001C000
TWI1
20
0x40020000
PWM
31
0x40024000
USART0
14
0x40028000
USART1
15
0x4002C000
USART2
17
0x40030000
Reserved
0x40034000
Reserved
0x40038000
ADC
29
0x4003C000
DACC
30
0x40040000
TWI2
22
0x40044000
UART2
10
0x40048000
UART3
16
0x4004C000
Reserved
0x400E0000
System Controller
0x400E2600
Reserved
0x60000000
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27
7.2
Embedded Memories
7.2.1
Internal SRAM
The SAM4N8 product embeds a total of 64-Kbytes high-speed SRAM.
The SAM4N16 product embeds a total of 80-Kbytes high-speed SRAM.
The SRAM is accessible over system Cortex-M4 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 to 0x23FF FFFF.
RAM size must be configurable by calibration fuses.
7.2.2
Internal ROM
The SAM4N8/16 product embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA® ), In
Application Programming (IAP) routines and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
7.2.3
Embedded Flash
7.2.3.1 Flash Overview
The memory is organized in sectors. Each sector has a size of 64 Kbytes. The first sector of 64 Kbytes is divided
into three smaller sectors.
The three smaller sectors are organized to consist of two sectors of 8 Kbytes and one sector of 48 Kbytes. Refer to
Figure 7-2 “Global Flash Organization”.
Figure 7-2.
Global Flash Organization
Flash Organization
Sector size
28
Sector name
8 Kbytes
Small sector 0
8 Kbytes
Small sector 1
48 Kbytes
Larger sector
64 Kbytes
Sector 1
64 Kbytes
Sector n
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Sector 0
Each sector is organized in pages of 512 bytes.
For sector 0:
The smaller sector 0 has 16 pages of 512 bytes
The smaller sector 1 has 16 pages of 512 bytes
The larger sector has 96 pages of 512 bytes
From sector 1 to n:
The rest of the array is composed of 64 Kbytes sectors each of 128 pages of 512 bytes. Refer to Figure 7-3 “Flash
Sector Organization”.
Figure 7-3.
Flash Sector Organization
Flash Sector Organization
A sector size is 64 Kbytes
Sector 0
Sector n
16 pages of 512 bytes
Smaller sector 0
16 pages of 512 bytes
Smaller sector 1
96 pages of 512 bytes
Larger sector
128 pages of 512 bytes
Flash size varies by product:
SAM4N16 the Flash size is 1024 Kbytes
SAM4N8 the Flash size is 512 Kbytes
Figure 7-4 “Flash Size” illustrates the Flash organization by size.
Figure 7-4.
Flash Size
Flash 1 Mbyte
Flash 512 Kbytes
2 * 8 Kbytes
2 * 8 Kbytes
1 * 48 Kbytes
1 * 48 Kbytes
15 * 64 Kbytes
7 * 64 Kbytes
Erasing the memory can be performed as follows:
Note:
On a 512-byte page inside a sector of 8 Kbytes
EWP and EWPL commands can be only used in 8 Kbytes sectors.
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29
Note:
Note:
On a 4-Kbyte block inside a sector of 8 Kbytes/48 Kbytes/64 Kbytes
Erase Page commands can be only used with FARG[1:0] = 1
On a sector of 8 Kbytes/48 Kbytes/64 Kbytes
Erase Page commands can be only used with FARG[1:0] = 2
On chip
The memory has one additional reprogrammable page that can be used as page signature by the user. It is
accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the
User Signature page.
7.2.3.2 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller manages accesses performed by the masters of the system. It enables
reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
7.2.3.3 Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to Section 36.10 “AC Characteristics”.
7.2.3.4 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of
several consecutive pages, and each lock region has its associated lock bit.
Table 7-1.
Lock Bit Number
Product
Number of Lock Bits
Lock Region Size
SAM4N8
64
8 Kbytes
SAM4N16
128
8 Kbytes
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an
interrupt.
The lock bits are software programmable through the EEFC User Interface. The “Set Lock Bit” command enables
the protection. The “Clear Lock Bit” command unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
7.2.3.5 Security Bit Feature
The SAM4N8/16 features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the
security is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the
ICE interface or through the Fast Flash Programming Interface (FFPI), is forbidden. This ensures the
confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the “Set General Purpose NVM Bit 0” command of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash
erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core Registers, Internal
Peripherals are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
30
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Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation.
However, it is safer to connect it directly to GND for the final application.
7.2.3.6 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured
and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
7.2.3.7 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed
by the user. The ERASE pin has no effect on the unique identifier.
7.2.3.8 Fast Flash Programming Interface (FFPI)
The FFPI allows programming the device through either a serial JTAG interface or through a multiplexed fullyhandshaked parallel port. It allows gang programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
The FFPI is enabled and the Fast Programming mode is entered when TST and PA0 and PA1 are tied low.
7.2.3.9 SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash
memory.
The SAM-BA Boot Assistant supports serial communication via the UART0.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
7.2.3.10 GPNVM Bits
The SAM4N features two GPNVM bits that can be cleared or set respectively through the “Clear GPNVM Bit” and
“Set GPNVM Bit” commands of the EEFC User Interface.
Table 7-2.
7.2.4
General-purpose Non-volatile Memory Bits
GPNVM Bit[#]
Function
0
Security bit
1
Boot mode selection
Boot Strategies
The system always boots at address 0x0. To ensure a maximum boot possibilities the memory layout can be
changed via GPNVM.
A General Purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the "Clear General-purpose NVM Bit" and "Set
General-purpose NVM Bit" commands of the EEFC User Interface.
Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting
ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
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31
8.
Real-time Event Management
The events generated by peripherals are designed to be directly routed to peripherals managing/using these
events without processor intervention. Peripherals receiving events contain logic by which to determine and
perform the action required.
8.1
8.2
Embedded Characteristics
Timers, IO peripherals generate event triggers which are directly routed to event managers such as ADC,
DACC, for example, to start measurement/conversion without processor intervention.
UART, USART, SPI, TWI, ADC, DACC, PIO also generate event triggers directly connected to Peripheral
DMA Controller (PDC) for data transfer without processor intervention.
PMC security event (clock failure detection) can be programmed to switch the MCK on reliable main RC
internal clock without processor intervention.
Real-time Event Mapping List
Table 8-1.
32
Real-time Event Mapping List
Event Generator
Event Manager
IO (WKUP0/1)
General Purpose Backup Register
(GPBR)
Power Management Controller
(PMC)
PMC
IO (ADTRG)
Analog-to-Digital Converter (ADC)
Trigger for measurement. Selection in ADC module
TC Output 0
ADC
Trigger for measurement. Selection in ADC module
TC Output 1
ADC
Trigger for measurement. Selection in ADC module
TC Output 2
ADC
Trigger for measurement. Selection in ADC module
IO (DATRG)
Digital-Analog Converter Controller
(DACC)
Trigger for conversion. Selection in DAC module
TC Output 0
DACC
Trigger for conversion. Selection in DAC module
TC Output 1
DACC
Trigger for conversion. Selection in DAC module
TC Output 2
DACC
Trigger for conversion. Selection in DAC module
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Function
Security / Immediate GPBR clear (asynchronous)
on tamper detection through WKUP0/1 IO pins
Safety / Automatic switch to reliable main RC
oscillator in case of main crystal clock failure
9.
System Controller
The System Controller is a set of peripherals which allow handling of key elements of the system, such as but not
limited to power, resets, clocks, time, interrupts, and watchdog.
9.1
System Controller and Peripherals Mapping
Please refer to Figure 7-1 “SAM4N8/16 Product Mapping”.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
9.2
Power-on-Reset, Brownout and Supply Monitor
The SAM4N embeds three features to monitor, warn and/or reset the chip:
9.2.1
Power-on-Reset on VDDIO
Brownout Detector on VDDCORE
Supply Monitor on VDDIO
Power-on-Reset on VDDIO
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at startup but also during power
down. If VDDIO goes below the threshold voltage, the entire chip is reset.
For more information, refer to Section 36. “SAM4N Electrical Characteristics”.
9.2.2
Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the
Supply Controller Mode Register (SUPC_MR). It is especially recommended to disable it during low-power modes
such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to
Section 17. “Supply Controller (SUPC)” and Section 36. “SAM4N Electrical Characteristics”.
9.2.3
Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully
programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller
(SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to
2048.
For more information, refer to Section 17. “Supply Controller (SUPC)” and Section 36. “SAM4N Electrical
Characteristics”.
9.3
SysTick Timer
24-bit down counter
Self-reload capability
Flexible system timer
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33
10.
Peripherals
10.1
Peripheral Identifiers
Table 10-1 defines the peripheral identifiers of the SAM4N8/16. A peripheral identifier is required for the control of
the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with
the Power Management Controller.
Table 10-1.
Peripheral Identifiers
Instance ID
Instance Name
NVIC
Interrupt
0
SUPC
X
Supply Controller
1
RSTC
X
Reset Controller
2
RTC
X
Real-time Clock
3
RTT
X
Real-time Timer
4
WDT
X
Watchdog Timer
5
PMC
X
Power Management Controller
6
EFC
X
Enhanced Flash Controller
7
–
–
–
Reserved
8
UART0
X
X
Universal Asynchronous Receiver Transmitter 0
9
UART1
X
X
Universal Asynchronous Receiver Transmitter 1
10
UART2
X
X
Universal Asynchronous Receiver Transmitter 2
11
PIOA
X
X
Parallel I/O Controller A
12
PIOB
X
X
Parallel I/O Controller B
13
PIOC
X
X
Parallel I/O Controller C
14
USART0
X
X
Universal Synchronous Asynchronous Receiver Transmitter 0
15
USART1
X
X
Universal Synchronous Asynchronous Receiver Transmitter 1
16
UART3
X
X
Universal Asynchronous Receiver Transmitter 3
17
USART2
X
X
Universal Synchronous Asynchronous Receiver Transmitter 2
18
–
–
–
Reserved
19
TWI0
X
X
Two-wire Interface 0
20
TWI1
X
X
Two-wire Interface 1
21
SPI
X
X
Serial Peripheral Interface
22
TWI2
X
X
Two-wire Interface 2
23
TC0
X
X
Timer Counter Channel 0
24
TC1
X
X
Timer Counter Channel 1
25
TC2
X
X
Timer Counter Channel 2
26
TC3
X
X
Timer Counter Channel 3
27
TC4
X
X
Timer Counter Channel 4
28
TC5
X
X
Timer Counter Channel 5
34
PMC
Clock Control
SAM4N8/SAM4N16 [DATASHEET]
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Instance Description
Table 10-1.
Peripheral Identifiers (Continued)
Instance ID
Instance Name
NVIC
Interrupt
PMC
Clock Control
29
ADC
X
X
Analog-to-Digital Converter
30
DACC
X
X
Digital-to-Analog Converter Controller
31
PWM
X
X
Pulse Width Modulation
Instance Description
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35
10.2
Peripherals Signals Multiplexing on I/O Lines
The SAM4N8/16 product features two PIO (48-pin and 64-pin version) or three PIO (100-pin version) controllers,
PIOA, PIOB and PIOC, which multiplex the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of three peripheral functions: A, B or
C. The following multiplexing tables define how the I/O lines of the peripherals A, B and C are multiplexed on the
PIO controllers.
Note that some output-only peripheral functions might be duplicated within the tables.
36
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10.2.1 PIO Controller A Multiplexing
Table 10-2.
I/O Line
PA0
Multiplexing on PIO Controller A (PIOA)
Peripheral A
PWM0
Peripheral B
Peripheral C
TIOA0
PA1
PWM1
TIOB0
PA2
PWM2
SCK0
PA3
TWD0
NPCS3
DATRG
Extra Function
System Function
Comments
WKUP0
(1)
High Drive
WKUP1
(1)
High Drive
WKUP2(1)
High Drive
High Drive
(1)
PA4
TWCK0
TCLK0
WKUP3
PA5
RXD0
NPCS3
WKUP4(1)
PA6
TXD0
PCK0
PA7
RTS0
PWM3
PA8
CTS0
ADTRG
WKUP5(1)
PA9
URXD0
NPCS1
WKUP6(1)
PA10
UTXD0
NPCS2
PA11
NPCS0
PWM0
PA12
MISO
PWM1
PA13
MOSI
PWM2
PA14
SPCK
PWM3
WKUP8(1)
PA15
UTXD2
TIOA1
WKUP14(1)
PA16
URXD2
TIOB1
WKUP15(1)
PA17
PCK1
AD0(3)
PA18
PCK2
AD1(3)
XIN32(2)
XOUT32(2)
WKUP7(1)
PA19
AD2/WKUP9(4)
PA20
AD3/WKUP10(4)
PA21
RXD1
PCK1
AD8(3)
64/100 pins versions
PA22
TXD1
NPCS3
AD9(3)
64/100 pins versions
PA23
SCK1
PWM0
64/100 pins versions
PA24
RTS1
PWM1
64/100 pins versions
PA25
CTS1
PWM2
64/100 pins versions
PA26
TIOA2
64/100 pins versions
PA27
TIOB2
64/100 pins versions
PA28
TCLK1
64/100 pins versions
PA29
TCLK2
64/100 pins versions
PA30
NPCS2
PA31
Notes:
NPCS1
1.
2.
3.
4.
WKUP11(1)
PCK2
64/100 pins versions
64/100 pins versions
WKUPx can be used if PIO controller defines the I/O line as "input".
Refer to Section 6.2 “System I/O Lines”.
To select this extra function, refer to Section 34.5.3 “Analog Inputs”.
Analog input has priority over WKUPx pin.
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37
10.2.2 PIO Controller B Multiplexing
Table 10-3.
I/O Line
Multiplexing on PIO Controller B (PIOB)
Peripheral A
Peripheral B
Peripheral C
Extra Function
System Function
PB0
PWM0
TWD2
PB1
PWM1
TWCK2
AD5(1)
PB2
URXD1
NPCS2
AD6/WKUP12(2)
PB3
UTXD1
PCK2
AD7(1)
PB4
TWD1
PWM2
PB5
TWCK1
AD4
TDI(3)
WKUP13(4)
TDO/TRACESWO(3)
PB6
TMS/SWDIO(3)
PB7
TCK/SWCLK(3)
PB8
XOUT(3)
PB9
XIN(3)
PB10
URXD3
PB11
UTXD3
ERASE(3)
PB12
PB13
PCK0
PB14
Notes:
38
Comments
(1)
NPCS1
1.
2.
3.
4.
5.
DAC0(5)
PWM3
To select this extra function, refer to Section 34.5.3 “Analog Inputs”.
Analog input has priority over WKUPx pin.
Refer to Section 6.2 “System I/O Lines”.
WKUPx can be used if PIO controller defines the I/O line as "input".
DAC0 is enabled when DACC_MR.DACEN is set. See Section 35.7.2 “DACC Mode Register”.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
64/100 pins versions
64/100 pins versions
10.2.3 PIO Controller C Multiplexing
Table 10-4.
I/O Line
Multiplexing on PIO Controller C (PIOC)
Peripheral A
Peripheral B
Peripheral C
Extra Function
System Function
Comments
PC0
100 pins version
PC1
100 pins version
PC2
100 pins version
PC3
100 pins version
PC4
NPCS1
100 pins version
PC5
100 pins version
PC6
100 pins version
PC7
NPCS2
100 pins version
PC8
PWM0
100 pins version
PC9
RXD2
PWM1
100 pins version
PC10
TXD2
PWM2
100 pins version
PC11
PWM3
PC12
PC13
PC14
SCK2
100 pins version
AD12
(1)
100 pins version
AD10
(1)
100 pins version
PCK2
100 pins version
(1)
PC15
AD11
100 pins version
PC16
RTS2
PCK0
100 pins version
PC17
CTS2
PCK1
100 pins version
PC18
PWM0
100 pins version
PC19
PWM1
100 pins version
PC20
PWM2
100 pins version
PC21
PWM3
100 pins version
PC22
PWM0
100 pins version
PC23
TIOA3
100 pins version
PC24
TIOB3
100 pins version
PC25
TCLK3
100 pins version
PC26
TIOA4
100 pins version
PC27
TIOB4
100 pins version
PC28
TCLK4
100 pins version
(1)
100 pins version
PC29
TIOA5
AD13
PC30
TIOB5
AD14(1)
100 pins version
TCLK5
(1)
100 pins version
PC31
Notes:
AD15
1. To select this extra function, refer to Section 34.5.3 “Analog Inputs”.
SAM4N8/SAM4N16 [DATASHEET]
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39
10.3
Embedded Peripherals Overview
10.3.1 Analog Mux
The Analog Mux is used to enable any of the 16 ADC analog inputs and the temperature sensor by means of the
ADC Channel Enable Register (ADC_CHER).
The temperature sensor is internally connected to the 17th input of the analog mux.
10.3.2 Voltage Reference Block
The ADC/DAC cell features one internal voltage reference block
3V typ., 2V to 3.6V supply voltage operation
Power by analog power supply voltage
20 µA typ. current consumption
4 bits trimmable output value from 1.6V to 3.4V, 121 mV steps
3 bits trimmable temperature compensation
Low noise in the 10 Hz–100 kHz bandwidth (-74 dBV typ.), usable for a 10-bit ADC reference
PSRR DC higher than 60 dB typ.
3.6 kΩ/100 nF load availability
Sense pin for VREF output
Only one external component needed (100 nF decoupling)
Direct reference connection to the supply voltage possible using force control pin
Level shifters with reset included (for digital supply detection flat)
Five output currents available (one 1 µA, three 2 µA and one 10 µA PTAT sourced form analog power
supply) and can be activated independently from the VREF buffer
10.3.3 Peripheral DMA Controller (PDC)
Handles data transfer between peripherals and memories
Twenty-three channels
̶
Six for USART0/1/2
̶
Six for the UART0/1/2
̶
Six for Two-wire Interface (TWI0/1/2)
̶
Two for Serial Peripheral Interface (SPI)
̶
One for Timer Counter 0
̶
One for Analog-to-Digital Converter
̶
One for the Digital-to-Analog Converter
Low bus arbitration overhead
̶
One Master Clock cycle needed for a transfer from memory to peripheral
̶
Two Master Clock cycles needed for a transfer from peripheral to memory
Next pointer management for reducing interrupt latency requirement
The PDC handles transfer requests from the channel according to the priorities (low to high priorities) defined in
Table 10-5.
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Table 10-5.
Peripheral DMA Controller
Instance Name
Channel T/R
TWI0
Transmit
TWI1
Transmit
TWI2
Transmit
UART0
Transmit
UART1
Transmit
UART2
Transmit
USART0
Transmit
USART1
Transmit
USART2
Transmit
DACC
Transmit
SPI
Transmit
TC0–TC2
Receive
TWI0
Receive
TWI1
Receive
TWI2
Receive
UART0
Receive
UART1
Receive
UART2
Receive
USART0
Receive
USART1
Receive
USART2
Receive
ADC
Receive
SPI
Receive
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11.
ARM Cortex-M4
11.1
Description
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers
significant benefits to developers, including outstanding processing performance combined with fast interrupt
handling, enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core,
system and memories, ultra-low power consumption with integrated sleep modes, and platform security
robustness, with integrated memory protection unit (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power
efficiency through an efficient instruction set and extensively optimized design, providing high-end processing
hardware including a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities,
saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system
components that reduce processor area while significantly improving interrupt handling and system debug
capabilities. The Cortex-M4 processor implements a version of the Thumb® instruction set based on Thumb-2
technology, ensuring high code density and reduced program memory requirements. The Cortex-M4 instruction
set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of
8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt
performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs),
dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the
ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in
assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces
the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that
enables the entire device to be rapidly powered down while still retaining program state.
11.1.1 System Level Interface
The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency
memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables
faster peripheral controls, system spinlocks and thread-safe Boolean data handling.
The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling
applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task
basis. Such requirements are becoming critical in many embedded applications such as automotive.
11.1.2 Integrated Configurable Debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of
the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is
ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints
and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial
Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information
through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides up to 8 hardware breakpoint comparators that debuggers can
use. The comparators in the FPB also provide remap functions of up to 8 words in the program code in the CODE
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memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be patched if a
small programmable memory, for example flash, is available in the device. During initialization, the application in
ROM detects, from the programmable memory, whether a patch is required. If a patch is required, the application
programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are
redirected to a remap table specified in the FPB configuration, which means the program in the non-modifiable
ROM can be patched.
11.2
Embedded Characteristics
Tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
Code-patch ability for ROM system updates
Power control optimization of system components
Integrated sleep modes for low power consumption
Fast code execution permits slower processor clock or increases sleep mode time
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory Protection Unit (MPU) for safety-critical applications
Extensive debug and trace capabilities:
̶
11.3
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing,
and code profiling.
Block Diagram
Figure 11-1.
TTypical Cortex-M4 Implementation
Cortex-M4
Processor
NVIC
Debug
Access
Port
Processor
Core
Serial
Wire
Viewer
Memory
Protection Unit
Flash
Patch
Data
Watchpoints
Bus Matrix
Code
Interface
SRAM and
Peripheral Interface
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11.4
Cortex-M4 Models
11.4.1 Programmers Model
This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it
contains information about the processor modes and privilege levels for software execution and stacks.
11.4.1.1 Processor Modes and Privilege Levels for Software Execution
The processor modes are:
Thread mode
Used to execute application software. The processor enters the Thread mode when it comes out of reset.
Handler mode
Used to handle exceptions. The processor returns to the Thread mode when it has finished exception
processing.
The privilege levels for software execution are:
Unprivileged
The software:
̶
Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
̶
Cannot access the System Timer, NVIC, or System Control Block
̶
Might have a restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
Privileged
The software can use all the instructions and has access to all resources. Privileged software executes at
the privileged level.
In Thread mode, the CONTROL register controls whether the software execution is privileged or unprivileged, see
“CONTROL Register” . In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software execution in
Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to
privileged software.
11.4.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked
item in memory When the processor pushes a new item onto the stack, it decrements the stack pointer and then
writes the item to the new memory location. The processor implements two stacks, the main stack and the process
stack, with a pointer for each held in independent registers, see “Stack Pointer” .
In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack,
see “CONTROL Register” .
In Handler mode, the processor always uses the main stack.
The options for processor operations are:
Table 11-1.
Summary of processor mode, execution privilege level, and stack use options
Processor Mode
Privilege Level for
Software Execution
Thread
Applications
Privileged or unprivileged
Handler
Exception handlers
Always privileged
Note:
44
Used to Execute
1.
See “CONTROL Register” .
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Stack Used
(1)
Main stack or process stack(1)
Main stack
11.4.1.3 Core Registers
Figure 11-2.
Processor Core Registers
R0
R1
R2
R3
Low registers
R4
R5
R6
General-purpose registers
R7
R8
R9
High registers
R10
R11
R12
Stack Pointer
SP (R13)
Link Register
LR (R14)
Program Counter
PC (R15)
PSR
PSP‡
MSP‡
‡
Banked version of SP
Program status register
PRIMASK
FAULTMASK
Exception mask registers
Special registers
BASEPRI
CONTROL
Table 11-2.
CONTROL register
Core Processor Registers
Register
Name
Access(1)
Required
Privilege(2)
Reset
General-purpose registers
R0-R12
Read-write
Either
Unknown
Stack Pointer
MSP
Read-write
Privileged
See description
Stack Pointer
PSP
Read-write
Either
Unknown
Link Register
LR
Read-write
Either
0xFFFFFFFF
Program Counter
PC
Read-write
Either
See description
Program Status Register
PSR
Read-write
Privileged
0x01000000
Application Program Status Register
APSR
Read-write
Either
0x00000000
Interrupt Program Status Register
IPSR
Read-only
Privileged
0x00000000
Execution Program Status Register
EPSR
Read-only
Privileged
0x01000000
Priority Mask Register
PRIMASK
Read-write
Privileged
0x00000000
Fault Mask Register
FAULTMASK
Read-write
Privileged
0x00000000
Base Priority Mask Register
BASEPRI
Read-write
Privileged
0x00000000
CONTROL register
CONTROL
Read-write
Privileged
0x00000000
Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
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11.4.1.4 General-purpose Registers
R0-R12 are 32-bit general-purpose registers for data operations.
11.4.1.5 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer
to use:
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address 0x00000000.
11.4.1.6 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and
exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.
11.4.1.7 Program Counter
The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads
the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loaded into the
EPSR T-bit at reset and must be 1.
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11.4.1.8 Program Status Register
Name:
PSR
Access:
Read-write
Reset:
0x000000000
31
N
30
Z
29
C
28
V
27
Q
26
23
22
21
20
25
24
T
19
18
17
16
12
11
10
9
–
8
ISR_NUMBER
4
3
2
1
0
ICI/IT
–
15
14
13
ICI/IT
7
6
5
ISR_NUMBER
The Program Status Register (PSR) combines:
Application Program Status Register (APSR)
Interrupt Program Status Register (IPSR)
Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR.
The PSR register accesses these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example:
Read of all the registers using PSR with the MRS instruction
Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction.
The PSR combinations and attributes are:
Name
Access
Combination
(1)(2)
PSR
Read-write
APSR, EPSR, and IPSR
IEPSR
Read-only
EPSR and IPSR
IAPSR
Read-write(1)
EAPSR
Notes:
(2)
Read-write
APSR and IPSR
APSR and EPSR
1. The processor ignores writes to the IPSR bits.
2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits
See the instruction descriptions “MRS” and “MSR” for more information about how to access the program status registers.
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11.4.1.9
Application Program Status Register
Name:
APSR
Access:
Read-write
Reset:
0x000000000
31
N
30
Z
23
22
29
C
28
V
27
Q
26
21
20
19
18
–
15
14
25
–
24
17
16
GE[3:0]
13
12
11
10
9
8
3
2
1
0
–
7
6
5
4
–
The APSR contains the current state of the condition flags from previous instruction executions.
• N: Negative Flag
0: Operation result was positive, zero, greater than, or equal
1: Operation result was negative or less than.
• Z: Zero Flag
0: Operation result was not zero
1: Operation result was zero.
• C: Carry or Borrow Flag
Carry or borrow flag:
0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit
1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
• V: Overflow Flag
0: Operation did not result in an overflow
1: Operation resulted in an overflow.
• Q: DSP Overflow and Saturation Flag
Sticky saturation flag:
0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero
1: Indicates when an SSAT or USAT instruction results in saturation.
This bit is cleared to zero by software using an MRS instruction.
• GE[19:16]: Greater Than or Equal Flags
See “SEL” for more information.
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11.4.1.10
Interrupt Program Status Register
Name:
IPSR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
–
23
22
21
20
–
15
14
13
12
–
11
10
9
8
ISR_NUMBER
7
6
5
4
3
2
1
0
ISR_NUMBER
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
• ISR_NUMBER: Number of the Current Exception
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
45 = IRQ29
See “Exception Types” for more information.
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11.4.1.11
Execution Program Status Register
Name:
EPSR
Access:
Read-write
Reset:
0x000000000
31
30
23
22
29
–
28
21
20
27
26
25
24
T
16
ICI/IT
19
18
17
11
10
9
–
15
14
13
12
ICI/IT
7
6
5
8
–
4
3
2
1
0
–
The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to
write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR
value in the stacked PSR to indicate the operation that is at fault. See “Exception Entry and Return”
• ICI: Interruptible-continuable Instruction
When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH,
or VPOP instruction, the processor:
– Stops the load multiple or store multiple instruction operation temporarily
– Stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
– Returns to the register pointed to by bits[15:12]
– Resumes the execution of the multiple load or store instruction.
When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.
• IT: If-Then Instruction
Indicates the execution state bits of the IT instruction.
The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional.
The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” for more
information.
• T: Thumb State
The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0:
– Instructions BLX, BX and POP{PC}
– Restoration from the stacked xPSR value on an exception return
– Bit[0] of the vector value on an exception entry or reset.
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See “Lockup” for more information.
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11.4.1.12 Exception Mask Registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they
might impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the
value of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information.
11.4.1.13 Priority Mask Register
Name:
PRIMASK
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PRIMASK
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
–
The PRIMASK register prevents the activation of all exceptions with a configurable priority.
• PRIMASK
0: No effect
1: Prevents the activation of all exceptions with a configurable priority.
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11.4.1.14 Fault Mask Register
Name:
FAULTMASK
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
FAULTMASK
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
–
The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI).
• FAULTMASK
0: No effect.
1: Prevents the activation of all exceptions except for NMI.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
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11.4.1.15 Base Priority Mask Register
Name:
BASEPRI
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
BASEPRI
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it
prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.
• BASEPRI
Priority mask bits:
0x0000 = No effect.
Nonzero = Defines the base priority for exception processing.
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this
field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” for more information. Remember that
higher priority field values correspond to lower exception priorities.
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11.4.1.16 CONTROL Register
Name:
CONTROL
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
–
1
SPSEL
0
nPRIV
–
23
22
21
20
–
15
14
13
12
–
7
6
5
–
4
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in
Thread mode.
• SPSEL: Active Stack Pointer
Defines the current stack:
0: MSP is the current stack pointer.
1: PSP is the current stack pointer.
In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception
return.
• nPRIV: Thread Mode Privilege Level
Defines the Thread mode privilege level:
0: Privileged.
1: Unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register based
on the EXC_RETURN value.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and
exception handlers use the main stack.
By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
• Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR” , or
• Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 11-10.
Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures
that instructions after the ISB execute using the new stack pointer. See “ISB” .
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11.4.1.17 Exceptions and Interrupts
The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored
Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software
control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry”
and “Exception Return” for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more
information.
11.4.1.18 Data Types
The processor supports the following data types:
32-bit words
16-bit halfwords
8-bit bytes
The processor manages all data memory accesses as little-endian. Instruction memory and Private
Peripheral Bus (PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” for
more information.
11.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)
For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:
A common way to:
̶
Access peripheral registers
̶
Define exception vectors
The names of:
̶
The registers of the core peripherals
̶
The core exception vectors
A device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor.
The CMSIS simplifies the software development by enabling the reuse of template code and the combination of
CMSIS-compliant software components from various middleware vendors. Software vendors can expand the
CMSIS to include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS
functions that address the processor core and the core peripherals.
Note:
This document uses the register short names defined by the CMSIS. In a few cases, these differ from the architectural
short names that might be used in other documents.
The following sections give more information about the CMSIS:
Section 11.5.3 “Power Management Programming Hints”
Section 11.6.2 “CMSIS Functions”
Section 11.8.2.1 “NVIC Programming Hints”.
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11.4.2 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the bit-banding
features. The processor has a fixed memory map that provides up to 4GB of addressable memory.
Figure 11-3.
Memory Map
0xFFFFFFFF
Vendor-specific
memory
511MB
Private peripheral
1.0MB
bus
External device
0xE0100000
0xE00FFFFF
0xE000 0000
0x DFFFFFFF
1.0GB
0xA0000000
0x9FFFFFFF
External RAM
0x43FFFFFF
1.0GB
32 MB Bit band alias
0x60000000
0x5FFFFFFF
0x42000000
0x400FFFFF
0x40000000
Peripheral
0.5GB
1 MB Bit Band region
0x40000000
0x3FFFFFFF
0x23FFFFFF
32 MB Bit band alias
SRAM
0.5GB
0x20000000
0x1FFFFFFF
0x22000000
Code
0x200FFFFF
0x20000000
1 MB Bit Band region
0.5GB
0x00000000
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit
data, see “Bit-banding” .
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers.
This memory mapping is generic to ARM Cortex-M4 products. To get the specific memory mapping of this product,
refer to the Memories section of the datasheet.
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11.4.2.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region has a defined
memory type, and some regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
Memory Types
Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
Device
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered
memory.
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can
buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory.
Additional Memory Attributes
Shareable
For a shareable memory region, the memory system provides data synchronization between bus masters in
a system with multiple bus masters, for example, a processor with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, the software must ensure data
coherency between the bus masters.
Execute Never (XN)
Means the processor prevents instruction accesses. A fault exception is generated only on execution of an
instruction executed from an XN region.
11.4.2.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions, providing
this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on
two memory accesses completing in program order, the software must insert a memory barrier instruction between
the memory access instructions, see “Software Ordering of Memory Accesses” .
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered
memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of
the memory accesses is described below.
Table 11-3.
Ordering of the Memory Accesses Caused by Two Instructions
A2
Device Access
Normal Access
Non-shareable
Shareable
Strongly-ordered
Access
Normal Access
–
–
–
–
Device access, non-shareable
–
<
–
<
Device access, shareable
–
–
<
<
Strongly-ordered access
–
<
<
<
A1
Where:
–
Means that the memory system does not guarantee the ordering of the accesses.
<
Means that accesses are observed in program order, that is, A1 is always observed
before A2.
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11.4.2.3 Behavior of Memory Accesses
The behavior of accesses to each region in the memory map is:
Table 11-4.
Memory Access Behavior
Address Range
Memory Region
Memory
Type
XN
Description
0x00000000 - 0x1FFFFFFF
Code
Normal(1)
-
Executable region for program code. Data can also be
put here.
0x20000000 - 0x3FFFFFFF
SRAM
Normal (1)
-
0x40000000 - 0x5FFFFFFF
Peripheral
Device (1)
XN
This region includes bit band and bit band alias areas,
see Table 11-6.
0x60000000 - 0x9FFFFFFF
External RAM
Normal (1)
-
Executable region for data.
XN
External Device memory
Executable region for data. Code can also be put here.
(1)
This region includes bit band and bit band alias areas,
see Table 11-6.
0xA0000000 - 0xDFFFFFFF
External device
Device
0xE0000000 - 0xE00FFFFF
Private Peripheral Bus
Stronglyordered (1)
XN
This region includes the NVIC, System timer, and
system control block.
0xE0100000 - 0xFFFFFFFF
Reserved
Device (1)
XN
Reserved
Note:
1.
See “Memory Regions, Types and Attributes” for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs
always use the Code region. This is because the processor has separate buses that enable instruction fetches and
data accesses to occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more information, see
“Memory Protection Unit (MPU)” .
Additional Memory Access Constraints For Shared Memory
When a system includes shared memory, some memory regions have additional access constraints, and some
regions are subdivided, as Table 11-5 shows:
Table 11-5.
Memory Region Shareability Policies
Address Range
Memory Region
Memory Type
Shareability
0x00000000- 0x1FFFFFFF
Code
Normal (1)
-
(2)
0x20000000- 0x3FFFFFFF
SRAM
Normal (1)
-
(2)
0x40000000- 0x5FFFFFFF
Peripheral
Device (1)
-
External RAM
Normal (1)
-
External device
Device (1)
0xE0000000- 0xE00FFFFF
Private Peripheral Bus
Strongly- ordered(1)
Shareable (1)
-
0xE0100000- 0xFFFFFFFF
Vendor-specific device
Device (1)
-
-
0x60000000- 0x7FFFFFFF
WBWA (2)
0x80000000- 0x9FFFFFFF
0xA0000000- 0xBFFFFFFF
0xC0000000- 0xDFFFFFFF
Notes:
58
1.
2.
WT (2)
Shareable (1)
Non-shareable (1)
-
See “Memory Regions, Types and Attributes” for more information.
WT = Write through, no write allocate. WBWA = Write back, write allocate. See the “Glossary” for more
information.
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Instruction Prefetch and Branch Prediction
The Cortex-M4 processor:
Prefetches instructions ahead of execution
Speculatively prefetches from branch target addresses.
11.4.2.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory
transactions. This is because:
The processor can reorder some memory accesses to improve efficiency, providing this does not affect the
behavior of the instruction sequence.
The processor has multiple bus interfaces
Memory or devices in the memory map have different wait states
Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the
order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include
memory barrier instructions to force that ordering. The processor provides the following memory barrier
instructions:
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before
subsequent memory transactions. See “DMB” .
DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete
before subsequent instructions execute. See “DSB” .
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is
recognizable by subsequent instructions. See “ISB” .
MPU Programming
Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by
subsequent instructions
11.4.2.5 Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band
regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:
Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 11-6.
Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in
Table 11-7.
Table 11-6.
SRAM Memory Bit-banding Regions
Address Range
0x200000000x200FFFFF
0x220000000x23FFFFFF
Memory Region
Instruction and Data Accesses
SRAM bit-band region
Direct accesses to this memory range behave as SRAM memory
accesses, but this region is also bit-addressable through bit-band alias.
SRAM bit-band alias
Data accesses to this region are remapped to bit-band region. A write
operation is performed as read-modify-write. Instruction accesses are not
remapped.
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Table 11-7.
Peripheral Memory Bit-banding Regions
Address Range
0x400000000x400FFFFF
0x420000000x43FFFFFF
Notes:
1.
2.
Memory Region
Instruction and Data Accesses
Peripheral bit-band alias
Direct accesses to this memory range behave as peripheral memory
accesses, but this region is also bit-addressable through bit-band alias.
Peripheral bit-band region
Data accesses to this region are remapped to bit-band region. A write
operation is performed as read-modify-write. Instruction accesses are
not permitted.
A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bitband region.
Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size
of the instruction making the bit-band access.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
Bit_word_offset is the position of the target bit in the bit-band memory region.
Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.
Bit_band_base is the starting address of the alias region.
Byte_offset is the number of the byte in the bit-band region that contains the targeted bit.
Bit_number is the bit position, 0-7, of the targeted bit.
Figure 11-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bitband region:
60
The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0 = 0x22000000 +
(0xFFFFF*32) + (0*4).
The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 +
(0xFFFFF*32) + (7*4).
The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 +
(0*32) + (0 *4).
The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C = 0x22000000+
(0*32) + (7*4).
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Figure 11-4.
Bit-band Mapping
32 MB alias region
0x23FFFFFC
0x23FFFFF8
0x23FFFFF4
0x23FFFFF0
0x23FFFFEC
0x23FFFFE8
0x23FFFFE4
0x23FFFFE0
0x2200001C
0x22000018
0x22000014
0x22000010
0x2200000C
0x22000008
0x22000004
0x22000000
1 MB SRAM bit-band region
7
6
5
4
3
2
1
0
7
6
0x200FFFFF
7
6
5
4
3
2
5
4
3
2
1
0
7
6
0x200FFFFE
1
0
7
6
0x20000003
5
4
3
2
0x20000002
5
4
3
2
1
0
7
6
0x200FFFFD
1
0
7
6
5
4
3
2
0x20000001
5
4
3
2
1
0
1
0
0x200FFFFC
1
0
7
6
5
4
3
2
0x20000000
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bitband region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0
writes a 0 to the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF.
Writing 0x00 has the same effect as writing 0x0E.
Reading a word in the alias region:
0x00000000 indicates that the targeted bit in the bit-band region is set to 0
0x00000001 indicates that the targeted bit in the bit-band region is set to 1
Directly Accessing a Bit-band Region
“Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band
regions.
11.4.2.6 Memory Endianness
The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example,
bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. “Little-endian Format” describes
how words of data are stored in memory.
Figure 11-5.
Little-endian Format
In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and
the most significant byte at the highest-numbered byte. For example:
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Figure 11-6.
Little-endian Format
Memory
7
Register
0
31
Address A
B0
A+1
B1
A+2
B2
A+3
B3
lsbyte
24 23
B3
16 15
B2
8 7
B1
0
B0
msbyte
11.4.2.7 Synchronization Primitives
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking
mechanism that a thread or process can use to obtain exclusive access to a memory location. The software can
use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that
location.
A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a
register. If this bit is:
0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds,
1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX
The halfword instructions LDREXH and STREXH
The byte instructions LDREXB and STREXB.
The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, the software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3.
Use a Store-Exclusive instruction to attempt to write the new value back to the memory location
4.
Test the returned status bit. If this bit is:
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of date. The
software must retry the read-modify-write sequence.
The software can use the synchronization primitives to implement a semaphore as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.
2. If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore
address.
3.
62
If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the
software has claimed the semaphore. However, if the Store-Exclusive instruction failed, another process
might have claimed the semaphore after the software performed the first step.
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The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a LoadExclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory
locations addressed by exclusive accesses by each processor.
The processor removes its exclusive access tag if:
It executes a CLREX instruction
It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
An exception occurs. This means that the processor can resolve semaphore conflicts between different
threads.
In a multiprocessor implementation:
Executing a CLREX instruction removes only the local exclusive access tag for the processor
Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all
global exclusive access tags for the processor.
For more information about the synchronization primitive instructions, see “LDREX and STREX” and “CLREX” .
11.4.2.8 Programming Hints for the Synchronization Primitives
ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for
generation of these instructions:
Table 11-8.
CMSIS Functions for Exclusive Access Instructions
Instruction
CMSIS Function
LDREX
uint32_t __LDREXW (uint32_t *addr)
LDREXH
uint16_t __LDREXH (uint16_t *addr)
LDREXB
uint8_t __LDREXB (uint8_t *addr)
STREX
uint32_t __STREXW (uint32_t value, uint32_t *addr)
STREXH
uint32_t __STREXH (uint16_t value, uint16_t *addr)
STREXB
uint32_t __STREXB (uint8_t value, uint8_t *addr)
CLREX
void __CLREX (void)
The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic
function. For example, the following C code generates the required LDREXB operation:
__ldrex((volatile char *) 0xFF);
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11.4.3 Exception Model
This section describes the exception model.
11.4.3.1 Exception States
Each exception is in one of the following states:
Inactive
The exception is not active and not pending.
Pending
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to
pending.
Active
An exception is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in
the active state.
Active and Pending
The exception is being serviced by the processor and there is a pending exception from the same source.
11.4.3.2 Exception Types
The exception types are:
Reset
Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception.
When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset
is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution
restarts as privileged execution in Thread mode.
Non Maskable Interrupt (NMI)
A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest
priority exception other than reset. It is permanently enabled and has a fixed priority of -2.
NMIs cannot be:
Masked or prevented from activation by any other exception.
Preempted by any exception other than Reset.
Hard Fault
A hard fault is an exception that occurs because of an error during exception processing, or because an exception
cannot be managed by any other exception mechanism. Hard Faults have a fixed priority of -1, meaning they have
higher priority than any exception with configurable priority.
Memory Management Fault (MemManage)
A Memory Management Fault is an exception that occurs because of a memory protection related fault. The MPU
or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions.
This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is
disabled.
Bus Fault
A Bus Fault is an exception that occurs because of a memory related fault for an instruction or data memory
transaction. This might be from an error detected on a bus in the memory system.
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Usage Fault
A Usage Fault is an exception that occurs because of a fault related to an instruction execution. This includes:
An undefined instruction
An illegal unaligned access
An invalid state on instruction execution
An error on exception return.
The following can cause a Usage Fault when the core is configured to report them:
An unaligned address on word and halfword memory access
A division by zero.
SVCall
A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications
can use SVC instructions to access OS kernel functions and device drivers.
PendSV
PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context
switching when no other exception is active.
SysTick
A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate
a SysTick exception. In an OS environment, the processor can use this exception as system tick.
Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are
asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the
processor.
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Table 11-9.
Properties of the Different Exception Types
Exception
Number (1)
Irq Number (1)
Exception Type
Priority
Vector Address or Offset (2)
Activation
1
-
Reset
-3, the highest
0x00000004
Asynchronous
2
-14
NMI
-2
0x00000008
Asynchronous
3
-13
Hard fault
-1
0x0000000C
-
4
-12
Memory
management fault
Configurable (3)
0x00000010
Synchronous
(3)
0x00000014
Synchronous when
precise,
asynchronous when
imprecise
5
-11
Bus fault
Configurable
6
-10
Usage fault
Configurable (3)
0x00000018
Synchronous
7-10
-
-
-
Reserved
-
11
-5
SVCall
Configurable (3)
0x0000002C
Synchronous
12-13
-
-
-
14
-2
PendSV
Reserved
-
Configurable
(3)
0x00000038
Asynchronous
(3)
0x0000003C
Asynchronous
0x00000040 and above (5)
Asynchronous
15
-1
SysTick
Configurable
16 and above
0 and above
Interrupt (IRQ)
Configurable(4)
Notes:
1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other
than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register” .
2. See “Vector Table” for more information
3. See “System Handler Priority Registers”
4. See “Interrupt Priority Registers”
5. Increasing in steps of 4.
For an asynchronous exception, other than reset, the processor can execute another instruction between when the
exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 11-9 shows as having configurable priority, see:
“System Handler Control and State Register”
“Interrupt Clear-enable Registers” .
For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault
Handling” .
11.4.3.3 Exception Handlers
The processor handles exceptions using:
66
Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ29 are the exceptions handled by ISRs.
Fault Handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault
handlers.
System Handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by
system handlers.
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11.4.3.4 Vector Table
The vector table contains the reset value of the stack pointer, and the start addresses, also called exception
vectors, for all exception handlers. Figure 11-7 shows the order of the exception vectors in the vector table. The
least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code.
Figure 11-7.
Vector Table
Exception number IRQ number
255
239
.
.
.
18
2
17
1
16
0
15
-1
14
-2
13
IRQ239
0x03FC
.
.
.
0x004C
.
.
.
IRQ2
0x0048
IRQ1
0x0044
IRQ0
0x0040
SysTick
0x003C
PendSV
0x0038
Reserved
Reserved for Debug
12
11
Vector
Offset
-5
10
SVCall
0x002C
9
Reserved
8
7
6
-10
5
-11
4
-12
3
-13
2
-14
1
Usage fault
0x0018
0x0014
0x0010
Bus fault
Memory management fault
Hard fault
0x000C
NMI
0x0008
0x0004
0x0000
Reset
Initial SP value
On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the SCB_VTOR
register to relocate the vector table start address to a different memory location, in the range 0x00000080 to
0x3FFFFF80, see “Vector Table Offset Register” .
11.4.3.5 Exception Priorities
As Table 11-9 shows, all exceptions have an associated priority, with:
A lower priority value indicating a higher priority
Configurable priorities for all exceptions except Reset, Hard fault and NMI.
If the software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0.
For information about configuring exception priorities see “System Handler Priority Registers” , and “Interrupt
Priority Registers” .
Note:
Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions, with
fixed negative priority values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has
higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
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If multiple pending exceptions have the same priority, the pending exception with the lowest exception number
takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is
processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority
exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not
preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.
11.4.3.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each
interrupt priority register entry into two fields:
An upper field that defines the group priority
A lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an
interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not
preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they
are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the
lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see “Application
Interrupt and Reset Control Register” .
11.4.3.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
Preemption
When the processor is executing an exception handler, an exception can preempt the exception handler if its
priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” for more
information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” more
information.
Return
This occurs when the exception handler is completed, and:
There is no pending exception with sufficient priority to be serviced
The completed exception handler was not handling a late-arriving exception.
The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
See “Exception Return” for more information.
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending
exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the
new exception handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous
exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that
exception. State saving is not affected by late arrival because the state saved is the same for both exceptions.
Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the
first instruction of the exception handler of the original exception enters the execute stage of the processor. On
return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply.
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Exception Entry
An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in
Thread mode, or the new exception is of a higher priority than the exception being handled, in which case the new
exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means that the exception has more priority than any limits set by the mask registers, see
“Exception Mask Registers” . An exception with less priority than this is pending but is not handled by the
processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the
processor pushes information onto the current stack. This operation is referred as stacking and the structure of
eight data words is referred to as stack frame.
Figure 11-8.
Exception Stack Frame
...
{aligner}
FPSCR
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
xPSR
PC
LR
R12
R3
R2
R1
R0
Exception frame with
floating-point storage
Pre-IRQ top of stack
Decreasing
memory
address
IRQ top of stack
...
{aligner}
xPSR
PC
LR
R12
R3
R2
R1
R0
Pre-IRQ top of stack
IRQ top of stack
Exception frame without
floating-point storage
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the
stack frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR).
The stack frame includes the return address. This is the address of the next instruction in the interrupted program.
This value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start
address from the vector table. When stacking is complete, the processor starts executing the exception handler. At
the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer
corresponds to the stack frame and what operation mode the processor was in before the entry occurred.
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If no higher priority exception occurs during the exception entry, the processor starts executing the exception
handler and automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during the exception entry, the processor starts executing the exception
handler for this exception and does not change the pending status of the earlier exception. This is the late arrival
case.
Exception Return
An Exception return occurs when the processor is in Handler mode and executes one of the following instructions
to load the EXC_RETURN value into the PC:
An LDM or POP instruction that loads the PC
An LDR instruction with the PC as the destination.
A BX instruction using any register.
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value
to detect when the processor has completed an exception handler. The lowest five bits of this value provide
information on the return stack and processor mode. Table 11-10 shows the EXC_RETURN values with a
description of the exception return behavior.
All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the
processor that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 11-10.
Exception Return Behavior
EXC_RETURN[31:0]
Description
0xFFFFFFF1
Return to Handler mode, exception return uses non-floating-point state
from the MSP and execution uses MSP after return.
0xFFFFFFF9
Return to Thread mode, exception return uses non-floating-point state from
MSP and execution uses MSP after return.
0xFFFFFFFD
Return to Thread mode, exception return uses non-floating-point state from
the PSP and execution uses PSP after return.
11.4.3.8 Fault Handling
Faults are a subset of the exceptions, see “Exception Model” . The following generate a fault:
A bus error on:
̶
An instruction fetch or vector table load
̶
A data access
An internally-detected error such as an undefined instruction
An attempt to execute an instruction from a memory region marked as Non-Executable (XN).
A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
Fault Types
Table 11-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the
register bit that indicates that the fault has occurred. See “Configurable Fault Status Register” for more information
about the fault status registers.
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Table 11-11.
Faults
Fault
Handler
Bus error on a vector read
Bit Name
Fault Status Register
VECTTBL
Hard fault
“Hard Fault Status Register”
Fault escalated to a hard fault
FORCED
MPU or default memory map mismatch:
-
on instruction access
-
IACCVIOL
Memory
management
fault
on data access
during exception stacking
DACCVIOL(2)
during exception unstacking
MUNSKERR
during lazy floating-point state preservation
MLSPERR
Bus error:
“MMFSR: Memory Management Fault
Status Subregister”
MSTKERR
-
-
during exception stacking
STKERR
during exception unstacking
UNSTKERR
during instruction prefetch
Bus fault
IBUSERR
“BFSR: Bus Fault Status Subregister”
during lazy floating-point state preservation
LSPERR
Precise data bus error
PRECISERR
Imprecise data bus error
IMPRECISERR
Attempt to access a coprocessor
NOCP
Undefined instruction
Attempt to enter an invalid instruction set state
UNDEFINSTR
(1)
INVSTATE
Usage fault
“UFSR: Usage Fault Status Subregister”
Invalid EXC_RETURN value
INVPC
Illegal unaligned load or store
UNALIGNED
Divide By 0
DIVBYZERO
Notes:
1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with
ICI continuation.
Fault Escalation and Hard Faults
All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority
Registers” . The software can disable the execution of the handlers for these faults, see “System Handler Control
and State Register” .
Usually, the exception priority, together with the values of the exception mask registers, determines whether the
processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in
“Exception Model” .
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In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and
the fault is described as escalated to hard fault. Escalation to hard fault occurs when:
A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs
because a fault handler cannot preempt itself; it must have the same priority as the current priority level.
A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the
handler for the new fault cannot preempt the currently executing fault handler.
An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a
hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack
push for the handler failed. The fault handler operates but the stack contents are corrupted.
Note:
Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than
Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault
address register indicates the address accessed by the operation that caused the fault, as shown in Table 11-12.
Table 11-12.
Fault Status and Fault Address Registers
Handler
Status Register
Name
Address
Register Name
Register Description
Hard fault
SCB_HFSR
-
“Hard Fault Status Register”
Memory
management fault
MMFSR
SCB_MMFAR
“MMFSR: Memory Management Fault Status Subregister”
“MemManage Fault Address Register”
Bus fault
BFSR
SCB_BFAR
Usage fault
UFSR
-
“BFSR: Bus Fault Status Subregister”
“Bus Fault Address Register”
“UFSR: Usage Fault Status Subregister”
Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the
processor is in lockup state, it does not execute any instructions. The processor remains in lockup state until
either:
It is reset
An NMI occurs
It is halted by a debugger.
Note:
72
If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup
state.
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11.5
Power Management
The Cortex-M4 processor sleep modes reduce the power consumption:
Sleep mode stops the processor clock
Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” .
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep
mode.
11.5.1 Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor.
Therefore, the software must be able to put the processor back into sleep mode after such an event. A program
might have an idle loop to put the processor back to sleep mode.
11.5.1.1 Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a
WFI instruction it stops executing instructions and enters sleep mode. See “WFI” for more information.
11.5.1.2 Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception
handler, it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that
only require the processor to run when an exception occurs.
11.5.2 Wakeup from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.
11.5.2.1 Wakeup from WFI or Sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception
entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it
executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an
interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes
up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information
about PRIMASK and FAULTMASK, see “Exception Mask Registers” .
11.5.3 Power Management Programming Hints
ISO/IEC C cannot directly generate the WFI instructions. The CMSIS provides the following functions for these
instructions:
void __WFI(void) // Wait for Interrupt
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11.6
Cortex-M4 Instruction Set
11.6.1 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 11-13 lists the supported instructions.
Angle brackets, , enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 11-13.
Cortex-M4 Instructions
Mnemonic
Operands
Description
Flags
ADC, ADCS
{Rd,} Rn, Op2
Add with Carry
N,Z,C,V
ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V
ADD, ADDW
{Rd,} Rn, #imm12
Add
N,Z,C,V
ADR
Rd, label
Load PC-relative address
-
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
ASR, ASRS
Rd, Rm,
Arithmetic Shift Right
N,Z,C
B
label
Branch
-
BFC
Rd, #lsb, #width
Bit Field Clear
-
BFI
Rd, Rn, #lsb, #width
Bit Field Insert
-
BIC, BICS
{Rd,} Rn, Op2
Bit Clear
N,Z,C
BKPT
#imm
Breakpoint
-
BL
label
Branch with Link
-
BLX
Rm
Branch indirect with Link
-
BX
Rm
Branch indirect
-
CBNZ
Rn, label
Compare and Branch if Non Zero
-
CBZ
Rn, label
Compare and Branch if Zero
-
CLREX
-
Clear Exclusive
-
CLZ
Rd, Rm
Count leading zeros
-
CMN
Rn, Op2
Compare Negative
N,Z,C,V
CMP
Rn, Op2
Compare
N,Z,C,V
CPSID
i
Change Processor State, Disable Interrupts
-
CPSIE
i
Change Processor State, Enable Interrupts
-
DMB
-
Data Memory Barrier
-
DSB
-
Data Synchronization Barrier
-
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
ISB
-
Instruction Synchronization Barrier
-
IT
-
If-Then condition block
-
LDM
Rn{!}, reglist
Load Multiple registers, increment after
-
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Table 11-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
LDMDB, LDMEA
Rn{!}, reglist
Load Multiple registers, decrement before
-
LDMFD, LDMIA
Rn{!}, reglist
Load Multiple registers, increment after
-
LDR
Rt, [Rn, #offset]
Load Register with word
-
LDRB, LDRBT
Rt, [Rn, #offset]
Load Register with byte
-
LDRD
Rt, Rt2, [Rn, #offset]
Load Register with two bytes
-
LDREX
Rt, [Rn, #offset]
Load Register Exclusive
-
LDREXB
Rt, [Rn]
Load Register Exclusive with byte
-
LDREXH
Rt, [Rn]
Load Register Exclusive with halfword
-
LDRH, LDRHT
Rt, [Rn, #offset]
Load Register with halfword
-
LDRSB, DRSBT
Rt, [Rn, #offset]
Load Register with signed byte
-
LDRSH, LDRSHT
Rt, [Rn, #offset]
Load Register with signed halfword
-
LDRT
Rt, [Rn, #offset]
Load Register with word
-
LSL, LSLS
Rd, Rm,
Logical Shift Left
N,Z,C
LSR, LSRS
Rd, Rm,
Logical Shift Right
N,Z,C
MLA
Rd, Rn, Rm, Ra
Multiply with Accumulate, 32-bit result
-
MLS
Rd, Rn, Rm, Ra
Multiply and Subtract, 32-bit result
-
MOV, MOVS
Rd, Op2
Move
N,Z,C
MOVT
Rd, #imm16
Move Top
-
MOVW, MOV
Rd, #imm16
Move 16-bit constant
N,Z,C
MRS
Rd, spec_reg
Move from special register to general register
-
MSR
spec_reg, Rm
Move from general register to special register
N,Z,C,V
MUL, MULS
{Rd,} Rn, Rm
Multiply, 32-bit result
N,Z
MVN, MVNS
Rd, Op2
Move NOT
N,Z,C
NOP
-
No Operation
-
ORN, ORNS
{Rd,} Rn, Op2
Logical OR NOT
N,Z,C
ORR, ORRS
{Rd,} Rn, Op2
Logical OR
N,Z,C
PKHTB, PKHBT
{Rd,} Rn, Rm, Op2
Pack Halfword
-
POP
reglist
Pop registers from stack
-
PUSH
reglist
Push registers onto stack
-
QADD
{Rd,} Rn, Rm
Saturating double and Add
Q
QADD16
{Rd,} Rn, Rm
Saturating Add 16
-
QADD8
{Rd,} Rn, Rm
Saturating Add 8
-
QASX
{Rd,} Rn, Rm
Saturating Add and Subtract with Exchange
-
QDADD
{Rd,} Rn, Rm
Saturating Add
Q
QDSUB
{Rd,} Rn, Rm
Saturating double and Subtract
Q
QSAX
{Rd,} Rn, Rm
Saturating Subtract and Add with Exchange
-
QSUB
{Rd,} Rn, Rm
Saturating Subtract
Q
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Table 11-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
QSUB16
{Rd,} Rn, Rm
Saturating Subtract 16
-
QSUB8
{Rd,} Rn, Rm
Saturating Subtract 8
-
RBIT
Rd, Rn
Reverse Bits
-
REV
Rd, Rn
Reverse byte order in a word
-
REV16
Rd, Rn
Reverse byte order in each halfword
-
REVSH
Rd, Rn
Reverse byte order in bottom halfword and sign extend
-
ROR, RORS
Rd, Rm,
Rotate Right
N,Z,C
RRX, RRXS
Rd, Rm
Rotate Right with Extend
N,Z,C
RSB, RSBS
{Rd,} Rn, Op2
Reverse Subtract
N,Z,C,V
SADD16
{Rd,} Rn, Rm
Signed Add 16
GE
SADD8
{Rd,} Rn, Rm
Signed Add 8 and Subtract with Exchange
GE
SASX
{Rd,} Rn, Rm
Signed Add
GE
SBC, SBCS
{Rd,} Rn, Op2
Subtract with Carry
N,Z,C,V
SBFX
Rd, Rn, #lsb, #width
Signed Bit Field Extract
-
SDIV
{Rd,} Rn, Rm
Signed Divide
-
SEL
{Rd,} Rn, Rm
Select bytes
-
SEV
-
Send Event
-
SHADD16
{Rd,} Rn, Rm
Signed Halving Add 16
-
SHADD8
{Rd,} Rn, Rm
Signed Halving Add 8
-
SHASX
{Rd,} Rn, Rm
Signed Halving Add and Subtract with Exchange
-
SHSAX
{Rd,} Rn, Rm
Signed Halving Subtract and Add with Exchange
-
SHSUB16
{Rd,} Rn, Rm
Signed Halving Subtract 16
-
SHSUB8
{Rd,} Rn, Rm
Signed Halving Subtract 8
-
SMLABB, SMLABT,
SMLATB, SMLATT
Rd, Rn, Rm, Ra
Signed Multiply Accumulate Long (halfwords)
Q
SMLAD, SMLADX
Rd, Rn, Rm, Ra
Signed Multiply Accumulate Dual
Q
SMLAL
RdLo, RdHi, Rn, Rm
Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result
-
SMLALBB, SMLALBT,
SMLALTB, SMLALTT
RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long, halfwords
-
SMLALD, SMLALDX
RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long Dual
-
SMLAWB, SMLAWT
Rd, Rn, Rm, Ra
Signed Multiply Accumulate, word by halfword
Q
SMLSD
Rd, Rn, Rm, Ra
Signed Multiply Subtract Dual
Q
SMLSLD
RdLo, RdHi, Rn, Rm
Signed Multiply Subtract Long Dual
SMMLA
Rd, Rn, Rm, Ra
Signed Most significant word Multiply Accumulate
-
SMMLS, SMMLR
Rd, Rn, Rm, Ra
Signed Most significant word Multiply Subtract
-
SMMUL, SMMULR
{Rd,} Rn, Rm
Signed Most significant word Multiply
-
SMUAD
{Rd,} Rn, Rm
Signed dual Multiply Add
Q
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Table 11-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
SMULBB, SMULBT
SMULTB, SMULTT
{Rd,} Rn, Rm
Signed Multiply (halfwords)
-
SMULL
RdLo, RdHi, Rn, Rm
Signed Multiply (32 x 32), 64-bit result
-
SMULWB, SMULWT
{Rd,} Rn, Rm
Signed Multiply word by halfword
-
SMUSD, SMUSDX
{Rd,} Rn, Rm
Signed dual Multiply Subtract
-
SSAT
Rd, #n, Rm {,shift #s}
Signed Saturate
Q
SSAT16
Rd, #n, Rm
Signed Saturate 16
Q
SSAX
{Rd,} Rn, Rm
Signed Subtract and Add with Exchange
GE
SSUB16
{Rd,} Rn, Rm
Signed Subtract 16
-
SSUB8
{Rd,} Rn, Rm
Signed Subtract 8
-
STM
Rn{!}, reglist
Store Multiple registers, increment after
-
STMDB, STMEA
Rn{!}, reglist
Store Multiple registers, decrement before
-
STMFD, STMIA
Rn{!}, reglist
Store Multiple registers, increment after
-
STR
Rt, [Rn, #offset]
Store Register word
-
STRB, STRBT
Rt, [Rn, #offset]
Store Register byte
-
STRD
Rt, Rt2, [Rn, #offset]
Store Register two words
-
STREX
Rd, Rt, [Rn, #offset]
Store Register Exclusive
-
STREXB
Rd, Rt, [Rn]
Store Register Exclusive byte
-
STREXH
Rd, Rt, [Rn]
Store Register Exclusive halfword
-
STRH, STRHT
Rt, [Rn, #offset]
Store Register halfword
-
STRT
Rt, [Rn, #offset]
Store Register word
-
SUB, SUBS
{Rd,} Rn, Op2
Subtract
N,Z,C,V
SUB, SUBW
{Rd,} Rn, #imm12
Subtract
N,Z,C,V
SVC
#imm
Supervisor Call
-
SXTAB
{Rd,} Rn, Rm,{,ROR #}
Extend 8 bits to 32 and add
-
SXTAB16
{Rd,} Rn, Rm,{,ROR #}
Dual extend 8 bits to 16 and add
-
SXTAH
{Rd,} Rn, Rm,{,ROR #}
Extend 16 bits to 32 and add
-
SXTB16
{Rd,} Rm {,ROR #n}
Signed Extend Byte 16
-
SXTB
{Rd,} Rm {,ROR #n}
Sign extend a byte
-
SXTH
{Rd,} Rm {,ROR #n}
Sign extend a halfword
-
TBB
[Rn, Rm]
Table Branch Byte
-
TBH
[Rn, Rm, LSL #1]
Table Branch Halfword
-
TEQ
Rn, Op2
Test Equivalence
N,Z,C
TST
Rn, Op2
Test
N,Z,C
UADD16
{Rd,} Rn, Rm
Unsigned Add 16
GE
UADD8
{Rd,} Rn, Rm
Unsigned Add 8
GE
USAX
{Rd,} Rn, Rm
Unsigned Subtract and Add with Exchange
GE
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Table 11-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
UHADD16
{Rd,} Rn, Rm
Unsigned Halving Add 16
-
UHADD8
{Rd,} Rn, Rm
Unsigned Halving Add 8
-
UHASX
{Rd,} Rn, Rm
Unsigned Halving Add and Subtract with Exchange
-
UHSAX
{Rd,} Rn, Rm
Unsigned Halving Subtract and Add with Exchange
-
UHSUB16
{Rd,} Rn, Rm
Unsigned Halving Subtract 16
-
UHSUB8
{Rd,} Rn, Rm
Unsigned Halving Subtract 8
-
UBFX
Rd, Rn, #lsb, #width
Unsigned Bit Field Extract
-
UDIV
{Rd,} Rn, Rm
Unsigned Divide
-
UMAAL
RdLo, RdHi, Rn, Rm
Unsigned Multiply Accumulate Accumulate Long (32 x 32 + 32 +32),
64-bit result
-
UMLAL
RdLo, RdHi, Rn, Rm
Unsigned Multiply with Accumulate
(32 x 32 + 64), 64-bit result
-
UMULL
RdLo, RdHi, Rn, Rm
Unsigned Multiply (32 x 32), 64-bit result
-
UQADD16
{Rd,} Rn, Rm
Unsigned Saturating Add 16
-
UQADD8
{Rd,} Rn, Rm
Unsigned Saturating Add 8
-
UQASX
{Rd,} Rn, Rm
Unsigned Saturating Add and Subtract with Exchange
-
UQSAX
{Rd,} Rn, Rm
Unsigned Saturating Subtract and Add with Exchange
-
UQSUB16
{Rd,} Rn, Rm
Unsigned Saturating Subtract 16
-
UQSUB8
{Rd,} Rn, Rm
Unsigned Saturating Subtract 8
-
USAD8
{Rd,} Rn, Rm
Unsigned Sum of Absolute Differences
-
USADA8
{Rd,} Rn, Rm, Ra
Unsigned Sum of Absolute Differences and Accumulate
-
USAT
Rd, #n, Rm {,shift #s}
Unsigned Saturate
Q
USAT16
Rd, #n, Rm
Unsigned Saturate 16
Q
UASX
{Rd,} Rn, Rm
Unsigned Add and Subtract with Exchange
GE
USUB16
{Rd,} Rn, Rm
Unsigned Subtract 16
GE
USUB8
{Rd,} Rn, Rm
Unsigned Subtract 8
GE
UXTAB
{Rd,} Rn, Rm,{,ROR #}
Rotate, extend 8 bits to 32 and Add
-
UXTAB16
{Rd,} Rn, Rm,{,ROR #}
Rotate, dual extend 8 bits to 16 and Add
-
UXTAH
{Rd,} Rn, Rm,{,ROR #}
Rotate, unsigned extend and Add Halfword
-
UXTB
{Rd,} Rm {,ROR #n}
Zero extend a byte
-
UXTB16
{Rd,} Rm {,ROR #n}
Unsigned Extend Byte 16
-
UXTH
{Rd,} Rm {,ROR #n}
Zero extend a halfword
-
VABS.F32
Sd, Sm
Floating-point Absolute
-
VADD.F32
{Sd,} Sn, Sm
Floating-point Add
-
VCMP.F32
Sd,
Compare two floating-point registers, or one floating-point register
and zero
FPSCR
VCMPE.F32
Sd,
Compare two floating-point registers, or one floating-point register
and zero with Invalid Operation check
FPSCR
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Table 11-13.
Cortex-M4 Instructions (Continued)
Mnemonic
Operands
Description
Flags
VCVT.S32.F32
Sd, Sm
Convert between floating-point and integer
-
VCVT.S16.F32
Sd, Sd, #fbits
Convert between floating-point and fixed point
-
VCVTR.S32.F32
Sd, Sm
Convert between floating-point and integer with rounding
-
VCVT.F32.F16
Sd, Sm
Converts half-precision value to single-precision
-
VCVTT.F32.F16
Sd, Sm
Converts single-precision register to half-precision
-
VDIV.F32
{Sd,} Sn, Sm
Floating-point Divide
-
VFMA.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Accumulate
-
VFNMA.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply Accumulate
-
VFMS.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Subtract
-
VFNMS.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply Subtract
-
VLDM.F
Rn{!}, list
Load Multiple extension registers
-
VLDR.F
, [Rn]
Load an extension register from memory
-
VLMA.F32
{Sd,} Sn, Sm
Floating-point Multiply Accumulate
-
VLMS.F32
{Sd,} Sn, Sm
Floating-point Multiply Subtract
-
VMOV.F32
Sd, #imm
Floating-point Move immediate
-
VMOV
Sd, Sm
Floating-point Move register
-
VMOV
Sn, Rt
Copy ARM core register to single precision
-
VMOV
Sm, Sm1, Rt, Rt2
Copy 2 ARM core registers to 2 single precision
-
VMOV
Dd[x], Rt
Copy ARM core register to scalar
-
VMOV
Rt, Dn[x]
Copy scalar to ARM core register
-
VMRS
Rt, FPSCR
Move FPSCR to ARM core register or APSR
N,Z,C,V
VMSR
FPSCR, Rt
Move to FPSCR from ARM Core register
FPSCR
VMUL.F32
{Sd,} Sn, Sm
Floating-point Multiply
-
VNEG.F32
Sd, Sm
Floating-point Negate
-
VNMLA.F32
Sd, Sn, Sm
Floating-point Multiply and Add
-
VNMLS.F32
Sd, Sn, Sm
Floating-point Multiply and Subtract
-
VNMUL
{Sd,} Sn, Sm
Floating-point Multiply
-
VPOP
list
Pop extension registers
-
VPUSH
list
Push extension registers
-
VSQRT.F32
Sd, Sm
Calculates floating-point Square Root
-
VSTM
Rn{!}, list
Floating-point register Store Multiple
-
VSTR.F
Sd, [Rn]
Stores an extension register to memory
-
VSUB.F
{Sd,} Sn, Sm
Floating-point Subtract
-
WFI
-
Wait For Interrupt
-
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11.6.2 CMSIS Functions
ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can
generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler
does not support an appropriate intrinsic function, the user might have to use inline assembler to access some
instructions.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly
access:
Table 11-14.
CMSIS Functions to Generate some Cortex-M4 Instructions
Instruction
CMSIS Function
CPSIE I
void __enable_irq(void)
CPSID I
void __disable_irq(void)
CPSIE F
void __enable_fault_irq(void)
CPSID F
void __disable_fault_irq(void)
ISB
void __ISB(void)
DSB
void __DSB(void)
DMB
void __DMB(void)
REV
uint32_t __REV(uint32_t int value)
REV16
uint32_t __REV16(uint32_t int value)
REVSH
uint32_t __REVSH(uint32_t int value)
RBIT
uint32_t __RBIT(uint32_t int value)
SEV
void __SEV(void)
WFI
void __WFI(void)
The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR
instructions:
Table 11-15.
CMSIS Intrinsic Functions to Access the Special Registers
Special Register
Access
CMSIS Function
Read
uint32_t __get_PRIMASK (void)
Write
void __set_PRIMASK (uint32_t value)
Read
uint32_t __get_FAULTMASK (void)
Write
void __set_FAULTMASK (uint32_t value)
Read
uint32_t __get_BASEPRI (void)
Write
void __set_BASEPRI (uint32_t value)
Read
uint32_t __get_CONTROL (void)
Write
void __set_CONTROL (uint32_t value)
Read
uint32_t __get_MSP (void)
Write
void __set_MSP (uint32_t TopOfMainStack)
Read
uint32_t __get_PSP (void)
Write
void __set_PSP (uint32_t TopOfProcStack)
PRIMASK
FAULTMASK
BASEPRI
CONTROL
MSP
PSP
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11.6.3 Instruction Descriptions
11.6.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions
act on the operands and often store the result in a destination register. When there is a destination register in the
instruction, it is usually specified before the operands.
Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” .
11.6.3.2 Restrictions when Using PC or SP
Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands
or destination register can be used. See instruction descriptions for more information.
Note:
Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution,
because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb instructions.
11.6.3.3 Flexible Second Operand
Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the
descriptions of the syntax of each instruction.
Operand2 can be a:
“Constant”
“Register with Optional Shift”
Constant
Specify an Operand2 constant in the form:
#constant
where constant can be:
Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
Any constant of the form 0x00XY00XY
Any constant of the form 0xXY00XY00
Any constant of the form 0xXYXYXYXY.
Note:
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are described in
the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS,
TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be
produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other
constant.
Instruction Substitution
The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant
that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the
equivalent instruction CMN Rd, #0x2.
Register with Optional Shift
Specify an Operand2 register in the form:
Rm {, shift}
where:
Rm
is the register holding the data for the second operand.
shift
is an optional shift to be applied to Rm. It can be one of:
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ASR #n
arithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL #n
logical shift left n bits, 1 ≤ n ≤ 31.
LSR #n
logical shift right n bits, 1 ≤ n ≤ 32.
ROR #n
rotate right n bits, 1 ≤ n ≤ 31.
RRX
rotate right one bit, with extend.
-
if omitted, no shift occurs, equivalent to LSL #0.
If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm.
If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the
instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also
updates the carry flag when used with certain instructions. For information on the shift operations and how they
affect the carry flag, see “Flexible Second Operand”
11.6.3.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits, the shift length.
Register shift can be performed:
Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register
During the calculation of Operand2 by the instructions that specify the second operand as a register with
shift. See “Flexible Second Operand” . The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs.
Register shift operations update the carry flag except when the specified shift length is 0. The following subsections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the
register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the
right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the
result. See Figure 11-9.
The ASR #n operation can be used to divide the value in the register Rm by 2n, with the result being rounded
towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the
register Rm.
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 11-9.
ASR #3
&DUU\
)ODJ
LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the righthand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 11-10.
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The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an
unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the
register Rm.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 11-10. LSR #3
&DUU\
)ODJ
LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand
32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 11-11.
The LSL #n operation can be used to multiply the value in the register Rm by 2n, if the value is regarded as an
unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 11-11. LSL #3
&DUU\
)ODJ
ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand
32-n bits of the result; and it moves the right-hand n bits of the register into the left-hand n bits of the result. See
Figure 11-12.
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register
Rm.
If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated
to bit[31] of Rm.
ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
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Figure 11-12. ROR #3
&DUU\
)ODJ
RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into
bit[31] of the result. See Figure 11-13.
When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 11-13. RRX
&DUU\
)ODJ
11.6.3.5 Address Alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word
access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.
The Cortex-M4 processor supports unaligned access only for the following instructions:
LDR, LDRT
LDRH, LDRHT
LDRSH, LDRSHT
STR, STRT
STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an unaligned access, and
therefore their accesses must be address-aligned. For more information about usage faults, see “Fault Handling” .
Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not
support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned.
To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control
Register to trap all unaligned accesses, see “Configuration and Control Register” .
11.6.3.6 PC-relative Expressions
A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is
represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the
required offset from the label and the address of the current instruction. If the offset is too big, the assembler
produces an error.
84
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4
bytes.
For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4
bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
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Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a
number, or an expression of the form [PC, #number].
11.6.3.7 Conditional Execution
Most data processing instructions can optionally update the condition flags in the Application Program Status
Register (APSR) according to the result of the operation, see “Application Program Status Register” . Some
instructions update all flags, and some only update a subset. If a flag is not updated, the original value is
preserved. See the instruction descriptions for the flags they affect.
An instruction can be executed conditionally, based on the condition flags set in another instruction, either:
Immediately after the instruction that updated the flags
After any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition code suffixes to
instructions. See Table 11-16 for a list of the suffixes to add to instructions to make them conditional instructions.
The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a
conditional instruction fails, the instruction:
Does not execute
Does not write any value to its destination register
Does not affect any of the flags
Does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” for
more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might
automatically insert an IT instruction if there are conditional instructions outside the IT block.
The CBZ and CBNZ instructions are used to compare the value of a register against zero and branch on the result.
This section describes:
“Condition Flags”
“Condition Code Suffixes” .
Condition Flags
The APSR contains the following condition flags:
N
Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z
Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C
Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V
Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR, see “Program Status Register” .
A carry occurs:
If the result of an addition is greater than or equal to 232
If the result of a subtraction is positive or zero
As the result of an inline barrel shifter operation in a move or logical instruction.
An overflow occurs when the sign of the result, in bit[31], does not match the sign of the result, had the operation
been performed at infinite precision, for example:
If adding two negative values results in a positive value
If adding two positive values results in a negative value
If subtracting a positive value from a negative value generates a positive value
If subtracting a negative value from a positive value generates a negative value.
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The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is
discarded. See the instruction descriptions for more information.
Note:
Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more
information.
Condition Code Suffixes
The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}.
Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if
the condition code flags in the APSR meet the specified condition. Table 11-16 shows the condition codes to use.
A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code.
Table 11-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.
Table 11-16.
Condition Code Suffixes
Suffix
Flags
Meaning
EQ
Z=1
Equal
NE
Z=0
Not equal
CS or
HS
C=1
Higher or same, unsigned ≥
CC or
LO
C=0
Lower, unsigned <
MI
N=1
Negative
PL
N=0
Positive or zero
VS
V=1
Overflow
VC
V=0
No overflow
HI
C = 1 and Z = 0
Higher, unsigned >
LS
C = 0 or Z = 1
Lower or same, unsigned ≤
GE
N=V
Greater than or equal, signed ≥
LT
N != V
Less than, signed <
GT
Z = 0 and N = V
Greater than, signed >
LE
Z = 1 and N != V
Less than or equal, signed ≤
AL
Can have any value
Always. This is the default when no suffix is specified.
Absolute Value
The example below shows the use of a conditional instruction to find the absolute value of a number. R0 =
ABS(R1).
MOVS
R0, R1
; R0 = R1, setting flags
IT
MI
; IT instruction for the negative condition
RSBMI
R0, R1, #0
; If negative, R0 = -R1
Compare and Update Value
The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is
greater than R1 and R2 is greater than R3.
CMP
R0, R1
; Compare R0 and R1, setting flags
ITT
GT
; IT instruction for the two GT conditions
CMPGT
R2, R3
; If 'greater than', compare R2 and R3, setting flags
MOVGT
R4, R5
; If still 'greater than', do R4 = R5
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11.6.3.8 Instruction Width Selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the
operands and destination register specified. For some of these instructions, the user can force a specific
instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix
forces a 16-bit instruction encoding.
If the user specifies an instruction width suffix and the assembler cannot generate an instruction encoding of the
requested width, it generates an error.
Note:
In some cases, it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or
literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the
right size encoding.
To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any.
The example below shows instructions with the instruction width suffix.
BCS.W label
; creates a 32-bit instruction even for a short
; branch
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
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11.6.4 Memory Access Instructions
The table below shows the memory access instructions:
Table 11-17.
88
Memory Access Instructions
Mnemonic
Description
ADR
Load PC-relative address
CLREX
Clear Exclusive
LDM{mode}
Load Multiple registers
LDR{type}
Load Register using immediate offset
LDR{type}
Load Register using register offset
LDR{type}T
Load Register with unprivileged access
LDR
Load Register using PC-relative address
LDRD
Load Register Dual
LDREX{type}
Load Register Exclusive
POP
Pop registers from stack
PUSH
Push registers onto stack
STM{mode}
Store Multiple registers
STR{type}
Store Register using immediate offset
STR{type}
Store Register using register offset
STR{type}T
Store Register with unprivileged access
STREX{type}
Store Register Exclusive
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11.6.4.1 ADR
Load PC-relative address.
Syntax
ADR{cond} Rd, label
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
label
is a PC-relative expression. See “PC-relative Expressions” .
Operation
ADR determines the address by adding an immediate value to the PC, and writes the result to the destination
register.
ADR produces position-independent code, because the address is PC-relative.
If ADR is used to generate a target address for a BX or BLX instruction, ensure that bit[0] of the address generated
is set to 1 for correct execution.
Values of label must be within the range of −4095 to +4095 from the address in the PC.
Note:
The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not wordaligned. See “Instruction Width Selection” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
ADR
R1, TextMessage
; Write address value of a location labelled as
; TextMessage to R1
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11.6.4.2 LDR and STR, Immediate Offset
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
Syntax
op{type}{cond} Rt,
op{type}{cond} Rt,
op{type}{cond} Rt,
opD{cond} Rt, Rt2,
opD{cond} Rt, Rt2,
opD{cond} Rt, Rt2,
[Rn {, #offset}]
[Rn, #offset]!
[Rn], #offset
[Rn {, #offset}]
[Rn, #offset]!
[Rn], #offset
;
;
;
;
;
;
immediate offset
pre-indexed
post-indexed
immediate offset, two words
pre-indexed, two words
post-indexed, two words
where:
op
is one of:
LDR
Load Register.
STR
Store Register.
type
is one of:
B
unsigned byte, zero extend to 32 bits on loads.
SB
signed byte, sign extend to 32 bits (LDR only).
H
unsigned halfword, zero extend to 32 bits on loads.
SH
signed halfword, sign extend to 32 bits (LDR only).
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution” .
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an offset from Rn. If offset is omitted, the address is the contents of Rn.
Rt2
is the additional register to load or store for two-word operations.
Operation
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
Offset Addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the
address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is:
[Rn, #offset]
Pre-indexed Addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the
address for the memory access and written back into the register Rn. The assembly language syntax for this mode
is:
[Rn, #offset]!
Post-indexed Addressing
The address obtained from the register Rn is used as the address for the memory access. The offset value is
added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for
this mode is:
[Rn], #offset
90
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The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed
or unsigned. See “Address Alignment” .
The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Table 11-18.
Offset Ranges
Instruction Type
Immediate Offset
Pre-indexed
Post-indexed
Word, halfword, signed
halfword, byte, or signed byte
-255 to 4095
-255 to 255
-255 to 255
Two words
multiple of 4 in the
range -1020 to
1020
multiple of 4 in the
range -1020 to
1020
multiple of 4 in the
range -1020 to 1020
Restrictions
For load instructions:
Rt can be SP or PC for word loads only
Rt must be different from Rt2 for two-word loads
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution
A branch occurs to the address created by changing bit[0] of the loaded value to 0
If the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
Rt can be SP for word stores only
Rt must not be PC
Rn must not be PC
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
Condition Flags
These instructions do not change the flags.
Examples
LDR
LDRNE
R8, [R10]
R2, [R5, #960]!
STR
R2, [R9,#const-struc]
STRH
R3, [R4], #4
LDRD
R8, R9, [R3, #0x20]
STRD
R0, R1, [R8], #-16
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Loads R8 from the address in R10.
Loads (conditionally) R2 from a word
960 bytes above the address in R5, and
increments R5 by 960.
const-struc is an expression evaluating
to a constant in the range 0-4095.
Store R3 as halfword data into address in
R4, then increment R4 by 4
Load R8 from a word 32 bytes above the
address in R3, and load R9 from a word 36
bytes above the address in R3
Store R0 to address in R8, and store R1 to
a word 4 bytes above the address in R8,
and then decrement R8 by 16.
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11.6.4.3 LDR and STR, Register Offset
Load and Store with register offset.
Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op
is one of:
LDR
Load Register.
STR
Store Register.
type
is one of:
B
unsigned byte, zero extend to 32 bits on loads.
SB
signed byte, sign extend to 32 bits (LDR only).
H
unsigned halfword, zero extend to 32 bits on loads.
SH
signed halfword, sign extend to 32 bits (LDR only).
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution” .
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
Rm
is a register containing a value to be used as the offset.
LSL #n
is an optional shift, with n in the range 0 to 3.
Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the
register Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment” .
Restrictions
In these instructions:
Rn must not be PC
Rm must not be SP and must not be PC
Rt can be SP only for word loads and word stores
Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
STR
LDRSB
92
R0, [R5, R1]
; Store value of R0 into an address equal to
; sum of R5 and R1
R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
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STR
;
;
R0, [R1, R2, LSL #2] ;
;
sum of R5 and two times R1, sign extended it
to a word value and put it in R0
Stores R0 to an address equal to sum of R1
and four times R2
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11.6.4.4 LDR and STR, Unprivileged
Load and Store with unprivileged access.
Syntax
op{type}T{cond} Rt, [Rn {, #offset}]
; immediate offset
where:
op
is one of:
LDR
Load Register.
STR
Store Register.
type is one of:
B
unsigned byte, zero extend to 32 bits on loads.
SB
signed byte, sign extend to 32 bits (LDR only).
H
unsigned halfword, zero extend to 32 bits on loads.
SH
signed halfword, sign extend to 32 bits (LDR only).
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution” .
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
Operation
These load and store instructions perform the same function as the memory access instructions with immediate
offset, see “LDR and STR, Immediate Offset” . The difference is that these instructions have only unprivileged
access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as normal memory access
instructions with immediate offset.
Restrictions
In these instructions:
Rn must not be PC
Rt must not be SP and must not be PC.
Condition Flags
These instructions do not change the flags.
Examples
94
STRBTEQ
R4, [R7]
LDRHT
R2, [R2, #8]
;
;
;
;
Conditionally store least significant byte in
R4 to an address in R7, with unprivileged access
Load halfword value from an address equal to
sum of R2 and 8 into R2, with unprivileged access
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11.6.4.5 LDR, PC-relative
Load register from memory.
Syntax
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
; Load two words
where:
type
is one of:
B
unsigned byte, zero extend to 32 bits.
SB
signed byte, sign extend to 32 bits.
H
unsigned halfword, zero extend to 32 bits.
SH
signed halfword, sign extend to 32 bits.
-
omit, for word.
cond
is an optional condition code, see “Conditional Execution” .
Rt
is the register to load or store.
Rt2
is the second register to load or store.
label
is a PC-relative expression. See “PC-relative Expressions” .
Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label
or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either
be signed or unsigned. See “Address Alignment” .
label must be within a limited range of the current instruction. The table below shows the possible offsets between
label and the PC.
Table 11-19.
Offset Ranges
Instruction Type
Offset Range
Word, halfword, signed halfword, byte, signed byte
-4095 to 4095
Two words
-1020 to 1020
The user might have to use the .W suffix to get the maximum offset range. See “Instruction Width Selection” .
Restrictions
In these instructions:
Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
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Condition Flags
These instructions do not change the flags.
Examples
96
LDR
R0, LookUpTable
LDRSB
R7, localdata
;
;
;
;
;
Load R0 with a word of data from an address
labelled as LookUpTable
Load a byte value from an address labelled
as localdata, sign extend it to a word
value, and put it in R7
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11.6.4.6 LDM and STM
Load and Store Multiple registers.
Syntax
op{addr_mode}{cond} Rn{!}, reglist
where:
op
is one of:
LDM
Load Multiple registers.
STM
Store Multiple registers.
addr_mode
is any one of the following:
IA
Increment address After each access. This is the default.
DB
Decrement address Before each access.
cond
is an optional condition code, see “Conditional Execution” .
Rn
is the register on which the memory addresses are based.
!
is an optional writeback suffix.
If ! is present, the final address, that is loaded from or stored to, is written back into Rn.
reglist
is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma separated if it contains more
than one register or register range, see “Examples” .
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending
stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending
stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks
Operation
LDM instructions load the registers in reglist with word values from memory addresses based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses based on Rn.
For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte
intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in
order of increasing register numbers, with the lowest numbered register using the lowest memory address and the
highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4
* (n-1) is written back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals
ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of
decreasing register numbers, with the highest numbered register using the highest memory address and the
lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 *
(n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” for details.
Restrictions
In these instructions:
Rn must not be PC
reglist must not contain SP
In any STM instruction, reglist must not contain PC
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In any LDM instruction, reglist must not contain PC if it contains LR
reglist must not contain Rn if the writeback suffix is specified.
When PC is in reglist in an LDM instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDM
STMDB
R8,{R0,R2,R9}
; LDMIA is a synonym for LDM
R1!,{R3-R6,R11,R12}
Incorrect Examples
STM
LDM
98
R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
R2, {}
; There must be at least one register in the list
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11.6.4.7 PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
Syntax
PUSH{cond} reglist
POP{cond} reglist
where:
cond
is an optional condition code, see “Conditional Execution” .
reglist
is a non-empty list of registers, enclosed in braces. It can contain register
ranges. It must be comma separated if it contains more than one register or
register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based
on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred
mnemonics in these cases.
Operation
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered
register using the highest memory address and the lowest numbered register using the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register
using the lowest memory address and the highest numbered register using the highest memory address.
See “LDM and STM” for more information.
Restrictions
In these instructions:
reglist must not contain SP
For the PUSH instruction, reglist must not contain PC
For the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
PUSH
PUSH
POP
{R0,R4-R7}
{R2,LR}
{R0,R10,PC}
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11.6.4.8 LDREX and STREX
Load and Store Register Exclusive.
Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register for the returned status.
Rt
is the register to load or store.
Rn
is the register on which the memory address is based.
offset
is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
Operation
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address.
The address used in any Store-Exclusive instruction must be the same as the address in the most recently
executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same
data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a
Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see
“Synchronization Primitives” .
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the
store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is
guaranteed that no other process in the system has accessed the memory location between the Load-exclusive
and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and StoreExclusive instruction to a minimum.
The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding
Load-Exclusive instruction is unpredictable.
Restrictions
In these instructions:
Do not use PC
Do not use SP for Rd and Rt
For STREX, Rd must be different from both Rt and Rn
The value of offset must be a multiple of four in the range 0-1020.
Condition Flags
These instructions do not change the flags.
Examples
MOV
LDREX
CMP
100
R1, #0x1
R0, [LockAddr]
R0, #0
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; Initialize the ‘lock taken’ value try
; Load the lock value
; Is the lock free?
ITT
STREXEQ
CMPEQ
BNE
....
EQ
R0, R1, [LockAddr]
R0, #0
try
;
;
;
;
;
IT instruction for STREXEQ and CMPEQ
Try and claim the lock
Did this succeed?
No – try again
Yes – we have the lock
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11.6.4.9 CLREX
Clear Exclusive.
Syntax
CLREX{cond}
where:
cond
is an optional condition code, see “Conditional Execution” .
Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to
perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception
occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization
operation.
See “Synchronization Primitives” for more information.
Condition Flags
These instructions do not change the flags.
Examples
CLREX
102
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11.6.5 General Data Processing Instructions
The table below shows the data processing instructions:
Table 11-20.
Data Processing Instructions
Mnemonic
Description
ADC
Add with Carry
ADD
Add
ADDW
Add
AND
Logical AND
ASR
Arithmetic Shift Right
BIC
Bit Clear
CLZ
Count leading zeros
CMN
Compare Negative
CMP
Compare
EOR
Exclusive OR
LSL
Logical Shift Left
LSR
Logical Shift Right
MOV
Move
MOVT
Move Top
MOVW
Move 16-bit constant
MVN
Move NOT
ORN
Logical OR NOT
ORR
Logical OR
RBIT
Reverse Bits
REV
Reverse byte order in a word
REV16
Reverse byte order in each halfword
REVSH
Reverse byte order in bottom halfword and sign extend
ROR
Rotate Right
RRX
Rotate Right with Extend
RSB
Reverse Subtract
SADD16
Signed Add 16
SADD8
Signed Add 8
SASX
Signed Add and Subtract with Exchange
SSAX
Signed Subtract and Add with Exchange
SBC
Subtract with Carry
SHADD16
Signed Halving Add 16
SHADD8
Signed Halving Add 8
SHASX
Signed Halving Add and Subtract with Exchange
SHSAX
Signed Halving Subtract and Add with Exchange
SHSUB16
Signed Halving Subtract 16
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Table 11-20.
104
Data Processing Instructions (Continued)
Mnemonic
Description
SHSUB8
Signed Halving Subtract 8
SSUB16
Signed Subtract 16
SSUB8
Signed Subtract 8
SUB
Subtract
SUBW
Subtract
TEQ
Test Equivalence
TST
Test
UADD16
Unsigned Add 16
UADD8
Unsigned Add 8
UASX
Unsigned Add and Subtract with Exchange
USAX
Unsigned Subtract and Add with Exchange
UHADD16
Unsigned Halving Add 16
UHADD8
Unsigned Halving Add 8
UHASX
Unsigned Halving Add and Subtract with Exchange
UHSAX
Unsigned Halving Subtract and Add with Exchange
UHSUB16
Unsigned Halving Subtract 16
UHSUB8
Unsigned Halving Subtract 8
USAD8
Unsigned Sum of Absolute Differences
USADA8
Unsigned Sum of Absolute Differences and Accumulate
USUB16
Unsigned Subtract 16
USUB8
Unsigned Subtract 8
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11.6.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
; ADD and SUB only
where:
op
is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
operation, see “Conditional Execution” .
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options.
imm12
is any value in the range 0-4095.
of
the
Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is
reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide
range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on.
See also “ADR” .
Note:
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses
the imm12 operand.
Restrictions
In these instructions:
Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
̶
Rn must also be SP
̶
Any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
̶
The user must not specify the S suffix
̶
Rm must not be PC and must not be SP
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̶
If the instruction is conditional, it must be the last instruction in the IT block
With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only
with the additional restrictions:
̶
The user must not specify the S suffix
̶
The second operand must be a constant in the range 0 to 4095.
̶
Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00
before performing the calculation, making the base address for the calculation word-aligned.
̶
Note: To generate the address of an instruction, the constant based on the value of the PC must be
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the
PC, because the assembler automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition Flags
If S is specified, these instructions update the N, Z, C and V flags according to the result.
Examples
ADD
SUBS
RSB
ADCHI
R2, R1, R3
R8, R6, #240
R4, R4, #1280
R11, R0, R3
;
;
;
;
Sets the flags on the result
Subtracts contents of R4 from 1280
Only executed if C flag set and Z
flag clear.
Multiword Arithmetic Examples
The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit
integer contained in R0 and R1, and place the result in R4 and R5.
64-bit Addition Example
ADDS
R4, R0, R2
ADC
R5, R1, R3
; add the least significant words
; add the most significant words with carry
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a
96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the
result in R6, R9, and R2.
96-bit Subtraction Example
SUBS
R6, R6, R9
SBCS
R9, R2, R1
SBC
R2, R8, R11
106
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; subtract the least significant words
; subtract the middle words with carry
; subtract the most significant words with carry
11.6.5.2 AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
Syntax
op{S}{cond} {Rd,} Rn, Operand2
where:
op
is one of:
AND logical AND.
ORR logical OR, or bit set.
EOR logical Exclusive OR.
BIC logical AND NOT, or bit clear.
ORN logical OR NOT.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
operation, see “Conditional Execution” .
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options
of
the
Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn
and Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in
the value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in
the value of Operand2.
Restrictions
Do not use SP and do not use PC.
Condition Flags
If S is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
AND
ORREQ
ANDS
EORS
BIC
ORN
ORNS
R9, R2, #0xFF00
R2, R0, R5
R9, R8, #0x19
R7, R11, #0x18181818
R0, R1, #0xab
R7, R11, R14, ROR #4
R7, R11, R14, ASR #32
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11.6.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op
is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
operation, see “Conditional Execution” .
Rd
is the destination register.
Rm
is the register holding the value to be shifted.
Rs
is the register holding the shift length to apply to the value in Rm. Only the least
of
the
significant byte is used and can be in the range 0 to 255.
n
is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 0 to 31
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by
constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on
what result is generated by the different instructions, see “Shift Operations” .
Restrictions
Do not use SP and do not use PC.
Condition Flags
If S is specified:
These instructions update the N and Z flags according to the result
The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” .
Examples
ASR
SLS
LSR
ROR
RRX
108
R7,
R1,
R4,
R4,
R4,
R8,
R2,
R5,
R5,
R5
#9
#3
#6
R6
;
;
;
;
;
Arithmetic shift right by 9 bits
Logical shift left by 3 bits with flag update
Logical shift right by 6 bits
Rotate right by the value in the bottom byte of R6
Rotate right with extend.
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11.6.5.4 CLZ
Count Leading Zeros.
Syntax
CLZ{cond} Rd, Rm
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rm
is the operand register.
Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result
value is 32 if no bits are set and zero if bit[31] is set.
Restrictions
Do not use SP and do not use PC.
Condition Flags
This instruction does not change the flags.
Examples
CLZ
CLZNE
R4,R9
R2,R3
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11.6.5.5 CMP and CMN
Compare and Compare Negative.
Syntax
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond
is an optional condition code, see “Conditional Execution” .
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
These instructions compare the value in a register with Operand2. They update the condition flags on the result,
but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction,
except that the result is discarded.
Restrictions
In these instructions:
Do not use PC
Operand2 must not be SP.
Condition Flags
These instructions update the N, Z, C and V flags according to the result.
Examples
CMP
CMN
CMPGT
110
R2, R9
R0, #6400
SP, R7, LSL #2
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11.6.5.6 MOV and MVN
Move and Move NOT.
Syntax
MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
operation, see “Conditional Execution” .
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options
imm16
is any value in the range 0-65535.
of
the
Operation
The MOV instruction copies the value of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the
corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See “ASR, LSL, LSR, ROR, and RRX” .
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and
places the result into Rd.
The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 operand.
Restrictions
SP and PC only can be used in the MOV instruction, with the following restrictions:
The second operand must be a register without shift
The S suffix must not be specified.
When Rd is PC in a MOV instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX
instruction to branch for software portability to the ARM instruction set.
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Condition Flags
If S is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
MOVS R11, #0x000B
; Write value of 0x000B to
R11, flags get updated
MOV
R1, #0xFA05
; Write value of 0xFA05 to
R1, flags are not updated
MOVS R10, R12
; Write value in R12 to R10,
flags get updated
MOV
R3, #23
; Write value of 23 to R3
MOV
R8, SP
; Write value of stack pointer to R8
MVNS R2, #0xF
; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags.
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11.6.5.7 MOVT
Move Top.
Syntax
MOVT{cond} Rd, #imm16
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
imm16
is a 16-bit immediate constant.
Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write
does not affect Rd[15:0].
The MOV, MOVT instruction pair enables to generate any 32-bit constant.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MOVT
R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged.
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11.6.5.8 REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
Syntax
op{cond} Rd, Rn
where:
op
is any of:
REV Reverse byte order in a word.
REV16 Reverse byte order in each halfword independently.
REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits.
RBIT Reverse the bit order in a 32-bit word.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the register holding the operand.
Operation
Use these instructions to change endianness of data:
REV converts either:
32-bit big-endian data into little-endian data
32-bit little-endian data into big-endian data.
REV16 converts either:
16-bit big-endian data into little-endian data
16-bit little-endian data into big-endian data.
REVSH converts either:
16-bit signed big-endian data into 32-bit signed little-endian data
16-bit signed little-endian data into 32-bit signed big-endian data.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
REV
REV16
REVSH
REVHS
RBIT
114
R3,
R0,
R0,
R3,
R7,
R7;
R0;
R5;
R7;
R8;
Reverse
Reverse
Reverse
Reverse
Reverse
byte order of value in R7 and write it to R3
byte order of each 16-bit halfword in R0
Signed Halfword
with Higher or Same condition
bit order of value in R8 and write the result to R7.
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11.6.5.9 SADD16 and SADD8
Signed Add 16 and Signed Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SADD16 Performs two 16-bit signed integer additions.
SADD8 Performs four 8-bit signed integer additions.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
Use these instructions to perform a halfword or byte add in parallel:
The SADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the result in the corresponding halfwords of the destination register.
The SADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
Writes the result in the corresponding bytes of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R1, R0
SADD8
;
;
;
R4, R0, R5 ;
;
Adds the halfwords in R0 to the corresponding
halfwords of R1 and writes to corresponding halfword
of R1.
Adds bytes of R0 to the corresponding byte in R5 and
writes to the corresponding byte in R4.
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11.6.5.10 SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SHADD16 Signed Halving Add 16.
SHADD8 Signed Halving Add 8.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the
destination register:
The SHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3.
Writes the halfword results in the destination register.
The SHADDB8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3.
Writes the byte results in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0
SHADD8
116
;
;
;
R4, R0, R5 ;
;
Adds halfwords in R0 to corresponding halfword of R1
and writes halved result to corresponding halfword in
R1
Adds bytes of R0 to corresponding byte in R5 and
writes halved result to corresponding byte in R4.
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11.6.5.11 SHASX and SHSAX
Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
where:
op
is any of:
SHASX Add and Subtract with Exchange and Halving.
SHSAX Subtract and Add with Exchange and Halving.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2. Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
3.
Subtracts the top halfword of the second operand from the bottom highword of the first operand.
4.
Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
The SHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Writes the halfword result of the addition to the bottom halfword of the destination register, shifted by one bit
to the right causing a divide by two, or halving.
3.
Adds the bottom halfword of the first operand with the top halfword of the second operand.
4.
Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to
the right causing a divide by two, or halving.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SHASX
R7, R4, R2
SHSAX
R0, R3, R5
;
;
;
;
;
;
;
;
Adds top halfword of R4 to bottom halfword of R2
and writes halved result to top halfword of R7
Subtracts top halfword of R2 from bottom halfword of
R4 and writes halved result to bottom halfword of R7
Subtracts bottom halfword of R5 from top halfword
of R3 and writes halved result to top halfword of R0
Adds top halfword of R5 to bottom halfword of R3 and
writes halved result to bottom halfword of R0.
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11.6.5.12 SHSUB16 and SHSUB8
Signed Halving Subtract 16 and Signed Halving Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SHSUB16 Signed Halving Subtract 16.
SHSUB8 Signed Halving Subtract 8.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the
destination register:
The SHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfwords of the first operand.
2. Shuffles the result by one bit to the right, halving the data.
3.
Writes the halved halfword results in the destination register.
The SHSUBB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand,
2. Shuffles the result by one bit to the right, halving the data,
3.
Writes the corresponding signed byte results in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SHSUB16 R1, R0
SHSUB8
118
;
;
R4, R0, R5 ;
;
Subtracts halfwords in R0 from corresponding halfword
of R1 and writes to corresponding halfword of R1
Subtracts bytes of R0 from corresponding byte in R5,
and writes to corresponding byte in R4.
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11.6.5.13 SSUB16 and SSUB8
Signed Subtract 16 and Signed Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
SSUB16 Performs two 16-bit signed integer subtractions.
SSUB8 Performs four 8-bit signed integer subtractions.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to change endianness of data:
The SSUB16 instruction:
1. Subtracts each halfword from the second operand from the corresponding halfword of the first operand
2. Writes the difference result of two signed halfwords in the corresponding halfword of the destination register.
The SSUB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand
2. Writes the difference result of four signed bytes in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SSUB16 R1, R0
SSUB8
;
;
R4, R0, R5 ;
;
Subtracts halfwords in R0 from corresponding halfword
of R1 and writes to corresponding halfword of R1
Subtracts bytes of R5 from corresponding byte in
R0, and writes to corresponding byte of R4.
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11.6.5.14 SASX and SSAX
Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rm, Rn
where:
op
is any of:
SASX Signed Add and Subtract with Exchange.
SSAX Signed Subtract and Add with Exchange.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SASX instruction:
1. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
2. Writes the signed result of the addition to the top halfword of the destination register.
3.
Subtracts the signed bottom halfword of the second operand from the top signed highword of the first
operand.
4.
Writes the signed result of the subtraction to the bottom halfword of the destination register.
The SSAX instruction:
1. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand.
2. Writes the signed result of the addition to the bottom halfword of the destination register.
3.
Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
4.
Writes the signed result of the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SASX
SSAX
120
R0, R4, R5 ;
;
;
;
R7, R3, R2 ;
;
;
;
Adds top halfword of R4 to bottom halfword of R5 and
writes to top halfword of R0
Subtracts bottom halfword of R5 from top halfword of R4
and writes to bottom halfword of R0
Subtracts top halfword of R2 from bottom halfword of R3
and writes to bottom halfword of R7
Adds top halfword of R3 with bottom halfword of R2 and
writes to top halfword of R7.
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11.6.5.15 TST and TEQ
Test bits and Test Equivalence.
Syntax
TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where
cond
is an optional condition code, see “Conditional Execution” .
Rn
is the register holding the first operand.
Operand2
is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
These instructions test the value in a register against Operand2. They update the condition flags based on the
result, but do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the
same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1
and all other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2.
This is the same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the
sign bits of the two operands.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
TST
TEQEQ
R0, #0x3F8 ;
;
R10, R9
;
;
Perform bitwise AND of R0 value to 0x3F8,
APSR is updated but result is discarded
Conditionally test if value in R10 is equal to
value in R9, APSR is updated but result is discarded.
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11.6.5.16 UADD16 and UADD8
Unsigned Add 16 and Unsigned Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
UADD16 Performs two 16-bit unsigned integer additions.
UADD8 Performs four 8-bit unsigned integer additions.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
Use these instructions to add 16- and 8-bit unsigned data:
The UADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the unsigned result in the corresponding halfwords of the destination register.
The UADD16 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Writes the unsigned result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
UADD16 R1, R0
UADD8
122
R4, R0, R5
;
;
;
;
Adds halfwords in R0 to corresponding halfword of R1,
writes to corresponding halfword of R1
Adds bytes of R0 to corresponding byte in R5 and
writes to corresponding byte in R4.
SAM4N8/SAM4N16 [DATASHEET]
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11.6.5.17 UASX and USAX
Add and Subtract with Exchange and Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
UASX Add and Subtract with Exchange.
USAX Subtract and Add with Exchange.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The UASX instruction:
1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand.
2. Writes the unsigned result from the subtraction to the bottom halfword of the destination register.
3.
Adds the top halfword of the first operand with the bottom halfword of the second operand.
4.
Writes the unsigned result of the addition to the top halfword of the destination register.
The USAX instruction:
1. Adds the bottom halfword of the first operand with the top halfword of the second operand.
2. Writes the unsigned result of the addition to the bottom halfword of the destination register.
3.
Subtracts the bottom halfword of the second operand from the top halfword of the first operand.
4.
Writes the unsigned result from the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UASX
USAX
R0, R4, R5 ;
;
;
;
R7, R3, R2 ;
;
;
;
Adds top halfword of R4 to bottom halfword of R5 and
writes to top halfword of R0
Subtracts bottom halfword of R5 from top halfword of R0
and writes to bottom halfword of R0
Subtracts top halfword of R2 from bottom halfword of R3
and writes to bottom halfword of R7
Adds top halfword of R3 to bottom halfword of R2 and
writes to top halfword of R7.
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11.6.5.18 UHADD16 and UHADD8
Unsigned Halving Add 16 and Unsigned Halving Add 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
UHADD16 Unsigned Halving Add 16.
UHADD8 Unsigned Halving Add 8.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the register holding the first operand.
Rm
is the register holding the second operand.
Operation
Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the
destination register:
The UHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the halfword result by one bit to the right, halving the data.
3.
Writes the unsigned results to the corresponding halfword in the destination register.
The UHADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the byte result by one bit to the right, halving the data.
3.
Writes the unsigned results in the corresponding byte in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
UHADD16 R7, R3
UHADD8
124
R4, R0, R5
;
;
;
;
;
Adds halfwords in R7 to corresponding halfword of R3
and writes halved result to corresponding halfword
in R7
Adds bytes of R0 to corresponding byte in R5 and
writes halved result to corresponding byte in R4.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.5.19 UHASX and UHSAX
Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange.
Syntax
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
UHASX Add and Subtract with Exchange and Halving.
UHSAX Subtract and Add with Exchange and Halving.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The UHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3.
Writes the halfword result of the addition to the top halfword of the destination register.
4.
Subtracts the top halfword of the second operand from the bottom highword of the first operand.
5.
Shifts the result by one bit to the right causing a divide by two, or halving.
6.
Writes the halfword result of the division in the bottom halfword of the destination register.
The UHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3.
Writes the halfword result of the subtraction in the top halfword of the destination register.
4.
Adds the bottom halfword of the first operand with the top halfword of the second operand.
5.
Shifts the result by one bit to the right causing a divide by two, or halving.
6.
Writes the halfword result of the addition to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UHASX
UHSAX
R7, R4, R2 ;
;
;
;
R0, R3, R5 ;
;
;
;
Adds top halfword of R4 with bottom halfword of R2
and writes halved result to top halfword of R7
Subtracts top halfword of R2 from bottom halfword of
R7 and writes halved result to bottom halfword of R7
Subtracts bottom halfword of R5 from top halfword of
R3 and writes halved result to top halfword of R0
Adds top halfword of R5 to bottom halfword of R3 and
writes halved result to bottom halfword of R0.
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11.6.5.20 UHSUB16 and UHSUB8
Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where:
op
is any of:
UHSUB16 Performs two unsigned 16-bit integer additions, halves the results,
and writes the results to the destination register.
UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and
writes the results to the destination register.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the
destination register:
The UHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfword of the first operand.
2. Shuffles each halfword result to the right by one bit, halving the data.
3.
Writes each unsigned halfword result to the corresponding halfwords in the destination register.
The UHSUB8 instruction:
1. Subtracts each byte of second operand from the corresponding byte of the first operand.
2. Shuffles each byte result by one bit to the right, halving the data.
3.
Writes the unsigned byte results to the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
UHSUB16 R1, R0
UHSUB8
126
R4, R0, R5
;
;
;
;
Subtracts halfwords in R0 from corresponding halfword of
R1 and writes halved result to corresponding halfword in R1
Subtracts bytes of R5 from corresponding byte in R0 and
writes halved result to corresponding byte in R4.
SAM4N8/SAM4N16 [DATASHEET]
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11.6.5.21 SEL
Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the
values of the GE flags.
Syntax
SEL{}{} {,} ,
where:
c, q
are standard assembler syntax fields.
Rd
is the destination register.
Rn
is the first register holding the operand.
Rm
is the second register holding the operand.
Operation
The SEL instruction:
1. Reads the value of each bit of APSR.GE.
2. Depending on the value of APSR.GE, assigns the destination register the value of either the first or second
operand register.
Restrictions
None.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R0, R1, R2
SEL
R0, R0, R3
; Set GE bits based on result
; Select bytes from R0 or R3, based on GE.
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11.6.5.22 USAD8
Unsigned Sum of Absolute Differences
Syntax
USAD8{cond}{Rd,} Rn, Rm
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
The USAD8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Adds the absolute values of the differences together.
3.
Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
USAD8 R1, R4, R0 ;
;
USAD8 R0, R5
;
;
128
Subtracts each byte in R0 from corresponding byte of R4
adds the differences and writes to R1
Subtracts bytes of R5 from corresponding byte in R0,
adds the differences and writes to R0.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.5.23 USADA8
Unsigned Sum of Absolute Differences and Accumulate
Syntax
USADA8{cond}{Rd,} Rn, Rm, Ra
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Ra
is the register that contains the accumulation value.
Operation
The USADA8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Adds the unsigned absolute differences together.
3.
Adds the accumulation value to the sum of the absolute differences.
4.
Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
USADA8 R1, R0, R6
USADA8 R4, R0, R5, R2
;
;
;
;
Subtracts bytes in R0 from corresponding halfword of R1
adds differences, adds value of R6, writes to R1
Subtracts bytes of R5 from corresponding byte in R0
adds differences, adds value of R2 writes to R4.
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11.6.5.24 USUB16 and USUB8
Unsigned Subtract 16 and Unsigned Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
where
op
is any of:
USUB16 Unsigned Subtract 16.
USUB8 Unsigned Subtract 8.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the second operand register.
Operation
Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register:
The USUB16 instruction:
1. Subtracts each halfword from the second operand register from the corresponding halfword of the first operand
register.
2. Writes the unsigned result in the corresponding halfwords of the destination register.
The USUB8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Writes the unsigned byte result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
USUB16 R1, R0
130
;
;
;
;
Subtracts halfwords in R0 from corresponding halfword of R1
and writes to corresponding halfword in R1USUB8 R4, R0, R5
Subtracts bytes of R5 from corresponding byte in R0 and
writes to the corresponding byte in R4.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.6 Multiply and Divide Instructions
The table below shows the multiply and divide instructions:
Table 11-21.
Multiply and Divide Instructions
Mnemonic
Description
MLA
Multiply with Accumulate, 32-bit result
MLS
Multiply and Subtract, 32-bit result
MUL
Multiply, 32-bit result
SDIV
Signed Divide
SMLA[B,T]
Signed Multiply Accumulate (halfwords)
SMLAD, SMLADX
Signed Multiply Accumulate Dual
SMLAL
Signed Multiply with Accumulate (32x32+64), 64-bit result
SMLAL[B,T]
Signed Multiply Accumulate Long (halfwords)
SMLALD, SMLALDX
Signed Multiply Accumulate Long Dual
SMLAW[B|T]
Signed Multiply Accumulate (word by halfword)
SMLSD
Signed Multiply Subtract Dual
SMLSLD
Signed Multiply Subtract Long Dual
SMMLA
Signed Most Significant Word Multiply Accumulate
SMMLS, SMMLSR
Signed Most Significant Word Multiply Subtract
SMUAD, SMUADX
Signed Dual Multiply Add
SMUL[B,T]
Signed Multiply (word by halfword)
SMMUL, SMMULR
Signed Most Significant Word Multiply
SMULL
Signed Multiply (32x32), 64-bit result
SMULWB, SMULWT
Signed Multiply (word by halfword)
SMUSD, SMUSDX
Signed Dual Multiply Subtract
UDIV
Unsigned Divide
UMAAL
Unsigned Multiply Accumulate Accumulate Long
(32x32+32+32), 64-bit result
UMLAL
Unsigned Multiply with Accumulate (32x32+64), 64-bit result
UMULL
Unsigned Multiply (32x32), 64-bit result
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11.6.6.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result.
Syntax
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond
is an optional condition code, see “Conditional Execution” .
S
is an optional suffix. If S is specified, the condition code flags are updated on the result
operation, see “Conditional Execution” .
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm
are registers holding the values to be multiplied.
Ra
is a register holding the value to be added or subtracted from.
of
the
Operation
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in
Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least
significant 32 bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and
places the least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or unsigned.
Restrictions
In these instructions, do not use SP and do not use PC.
If the S suffix is used with the MUL instruction:
Rd, Rn, and Rm must all be in the range R0 to R7
Rd must be the same as Rm
The cond suffix must not be used.
Condition Flags
If S is specified, the MUL instruction:
Updates the N and Z flags according to the result
Does not affect the C and V flags.
Examples
MUL
MLA
MULS
MULLT
MLS
132
R10, R2, R5
R10, R2, R1, R5
R0, R2, R2
R2, R3, R2
R4, R5, R6, R7
SAM4N8/SAM4N16 [DATASHEET]
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;
;
;
;
;
Multiply, R10
Multiply with
Multiply with
Conditionally
Multiply with
= R2 x R5
accumulate, R10 =
flag update, R0 =
multiply, R2 = R3
subtract, R4 = R7
(R2 x R1) + R5
R2 x R2
x R2
- (R5 x R6)
11.6.6.2 UMULL, UMAAL, UMLAL
Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op
is one of:
UMULL Unsigned Long Multiply.
UMAAL Unsigned Long Multiply with Accumulate Accumulate.
UMLAL Unsigned Long Multiply, with Accumulate.
cond
is an optional condition code, see “Conditional Execution” .
RdHi, RdLo
are the destination registers. For UMAAL, UMLAL and UMLAL they also hold
the accumulating value.
Rn, Rm
are registers holding the first and second operands.
Operation
These instructions interpret the values from Rn and Rm as unsigned 32-bit integers.
The UMULL instruction:
Multiplies the two unsigned integers in the first and second operands.
Writes the least significant 32 bits of the result in RdLo.
Writes the most significant 32 bits of the result in RdHi.
The UMAAL instruction:
Multiplies the two unsigned 32-bit integers in the first and second operands.
Adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication.
Adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition.
Writes the top 32-bits of the result to RdHi.
Writes the lower 32-bits of the result to RdLo.
The UMLAL instruction:
Multiplies the two unsigned integers in the first and second operands.
Adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.
Writes the result back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL
R0, R4, R5, R6
UMAAL
R3, R6, R2, R7
UMLAL
R2, R1, R3, R5
;
;
;
;
;
Multiplies R5 and R6, writes the top 32 bits to R4
and the bottom 32 bits to R0
Multiplies R2 and R7, adds R6, adds R3, writes the
top 32 bits to R6, and the bottom 32 bits to R3
Multiplies R5 and R3, adds R1:R2, writes to R1:R2.
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11.6.6.3 SMLA and SMLAW
Signed Multiply Accumulate (halfwords).
Syntax
op{XY}{cond} Rd, Rn, Rm
op{Y}{cond} Rd, Rn, Rm, Ra
where:
op
is one of:
SMLA Signed Multiply Accumulate Long (halfwords).
X and Y specifies which half of the source registers Rn and Rm are used as the
first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used
SMLAW Signed Multiply Accumulate (word by halfword).
Y specifies which half of the source register Rm is used as the second multiply
operand.
If Y is T, then the top halfword, bits [31:16] of Rm is used.
If Y is B, then the bottom halfword, bits [15:0] of Rm is used.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm
are registers holding the values to be multiplied.
Ra
is a register holding the value to be added or subtracted from.
Operation
The SMALBB, SMLABT, SMLATB, SMLATT instructions:
Multiplies the specified signed halfword, top or bottom, values from Rn and Rm.
Adds the value in Ra to the resulting 32-bit product.
Writes the result of the multiplication and addition in Rd.
The non-specified halfwords of the source registers are ignored.
The SMLAWB and SMLAWT instructions:
Multiply the 32-bit signed values in Rn with:
̶
̶
The top signed halfword of Rm, T instruction suffix.
The bottom signed halfword of Rm, B instruction suffix.
Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product
Writes the result of the multiplication and addition in Rd.
The bottom 16 bits of the 48-bit product are ignored.
If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No
overflow can occur during the multiplication.
Restrictions
In these instructions, do not use SP and do not use PC.
Condition Flags
If an overflow is detected, the Q flag is set.
134
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Examples
SMLABB
SMLATB
SMLATT
SMLABT
SMLABT
SMLAWB
SMLAWT
R5, R6, R4, R1
;
;
R5, R6, R4, R1 ;
;
R5, R6, R4, R1 ;
;
R5, R6, R4, R1 ;
;
R4, R3, R2
;
;
R10, R2, R5, R3 ;
;
R10, R2, R1, R5 ;
;
Multiplies bottom halfwords of R6 and R4, adds
R1 and writes to R5
Multiplies top halfword of R6 with bottom halfword
of R4, adds R1 and writes to R5
Multiplies top halfwords of R6 and R4, adds
R1 and writes the sum to R5
Multiplies bottom halfword of R6 with top halfword
of R4, adds R1 and writes to R5
Multiplies bottom halfword of R4 with top halfword of
R3, adds R2 and writes to R4
Multiplies R2 with bottom halfword of R5, adds
R3 to the result and writes top 32-bits to R10
Multiplies R2 with top halfword of R1, adds R5
and writes top 32-bits to R10.
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11.6.6.4 SMLAD
Signed Multiply Accumulate Long Dual
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
;
where:
op
is one of:
SMLAD Signed Multiply Accumulate Dual.
SMLADX Signed Multiply Accumulate Dual Reverse.
X specifies which halfword of the source register Rn is used as the multiply
operand.
If X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register holding the values to be multiplied.
Rm
the second operand register.
Ra
is the accumulate value.
Operation
The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values. The SMLAD and
SMLADX instructions:
If X is not present, multiply the top signed halfword value in Rn with the top signed halfword of Rm and the
bottom signed halfword values in Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and
the bottom signed halfword values in Rn with the top signed halfword of Rm.
Add both multiplication results to the signed 32-bit value in Ra.
Writes the 32-bit signed result of the multiplication and addition to Rd.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SMLAD
R10, R2, R1, R5 ;
;
;
SMLALDX R0, R2, R4, R6 ;
;
;
;
136
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Multiplies two halfword values in R2 with
corresponding halfwords in R1, adds R5 and
writes to R10
Multiplies top halfword of R2 with bottom
halfword of R4, multiplies bottom halfword of R2
with top halfword of R4, adds R6 and writes to
R0.
11.6.6.5 SMLAL and SMLALD
Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate
Long Dual.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
op{XY}{cond} RdLo, RdHi, Rn, Rm
op{X}{cond} RdLo, RdHi, Rn, Rm
where:
op
is one of:
MLAL Signed Multiply Accumulate Long.
SMLAL Signed Multiply Accumulate Long (halfwords, X and Y).
X and Y specify which halfword of the source registers Rn and Rm are used as
the first and second multiply operand:
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMLALD Signed Multiply Accumulate Long Dual.
SMLALDX Signed Multiply Accumulate Long Dual Reversed.
If the X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond
is an optional condition code, see “Conditional Execution” .
RdHi, RdLo
are the destination registers.
RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer.
For SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD and SMLA
LDX, they also hold the accumulating value.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMLAL instruction:
Multiplies the two’s complement signed word values from Rn and Rm.
Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The SMLALBB, SMLALBT, SMLALTB and SMLALTT instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The non-specified halfwords of the source registers are ignored.
The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement
signed 16-bit integers. These instructions:
If X is not present, multiply the top signed halfword value of Rn with the top signed halfword of Rm and the
bottom signed halfword values of Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value of Rn with the bottom signed halfword of Rm and
the bottom signed halfword values of Rn with the top signed halfword of Rm.
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137
Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit
product.
Write the 64-bit product in RdLo and RdHi.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMLAL
R4, R5, R3, R8
SMLALBT
R2, R1, R6, R7
SMLALTB
R2, R1, R6, R7
SMLALD
R6, R8, R5, R1
SMLALDX
R6, R8, R5, R1
138
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Multiplies R3 and R8, adds R5:R4 and writes to
R5:R4
Multiplies bottom halfword of R6 with top
halfword of R7, sign extends to 32-bit, adds
R1:R2 and writes to R1:R2
Multiplies top halfword of R6 with bottom
halfword of R7,sign extends to 32-bit, adds R1:R2
and writes to R1:R2
Multiplies top halfwords in R5 and R1 and bottom
halfwords of R5 and R1, adds R8:R6 and writes to
R8:R6
Multiplies top halfword in R5 with bottom
halfword of R1, and bottom halfword of R5 with
top halfword of R1, adds R8:R6 and writes to
R8:R6.
SAM4N8/SAM4N16 [DATASHEET]
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11.6.6.6 SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
where:
op
is one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
SMLAW Signed Multiply Accumulate (word by halfword).
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Ra
is the register holding the accumulate value.
Operation
The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This
instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the signed accumulate value to the result of the subtraction.
Writes the result of the addition to the destination register.
The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords.
This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.
Writes the 64-bit result of the addition to the RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the
multiplications or subtraction.
For the Thumb instruction set, these instructions do not affect the condition code flags.
Examples
SMLSD
R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom
; halfword of R5, multiplies top halfword of R4
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139
;
;
SMLSDX R1, R3, R2, R0 ;
;
;
;
SMLSLD R3, R6, R2, R7 ;
;
;
;
SMLSLDX R3, R6, R2, R7 ;
;
;
;
140
with top halfword of R5, subtracts second from
first, adds R6, writes to R0
Multiplies bottom halfword of R3 with top
halfword of R2, multiplies top halfword of R3
with bottom halfword of R2, subtracts second from
first, adds R0, writes to R1
Multiplies bottom halfword of R6 with bottom
halfword of R2, multiplies top halfword of R6
with top halfword of R2, subtracts second from
first, adds R6:R3, writes to R6:R3
Multiplies bottom halfword of R6 with top
halfword of R2, multiplies top halfword of R6
with bottom halfword of R2, subtracts second from
first, adds R6:R3, writes to R6:R3.
SAM4N8/SAM4N16 [DATASHEET]
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11.6.6.7 SMMLA and SMMLS
Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract
Syntax
op{R}{cond} Rd, Rn, Rm, Ra
where:
op
is one of:
SMMLA Signed Most Significant Word Multiply Accumulate.
SMMLS Signed Most Significant Word Multiply Subtract.
If the X is omitted, the multiplications are bottom × bottom and top × top.
R
is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second multiply operands.
Ra
is the register holding the accumulate value.
Operation
The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLA instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Adds the value of Ra to the signed extracted value.
Writes the result of the addition in Rd.
The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLS instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Subtracts the extracted value of the result from the value in Ra.
Writes the result of the subtraction in Rd.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMMLA
R0, R4, R5, R6
SMMLAR R6, R2, R1, R4
;
;
;
;
Multiplies R4 and R5, extracts top 32 bits, adds
R6, truncates and writes to R0
Multiplies R2 and R1, extracts top 32 bits, adds
R4, rounds and writes to R6
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141
SMMLSR R3, R6, R2, R7
SMMLS
142
R4, R5, R3, R8
;
;
;
;
Multiplies R6
subtracts R7,
Multiplies R5
subtracts R8,
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and R2, extracts top
rounds and writes to
and R3, extracts top
truncates and writes
32 bits,
R3
32 bits,
to R4.
11.6.6.8 SMMUL
Signed Most Significant Word Multiply
Syntax
op{R}{cond} Rd, Rn, Rm
where:
op
is one of:
SMMUL Signed Most Significant Word Multiply.
R
is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The
SMMUL instruction:
Multiplies the values from Rn and Rm.
Optionally rounds the result, otherwise truncates the result.
Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction:
do not use SP and do not use PC.
Condition Flags
This instruction does not affect the condition code flags.
Examples
SMULL
SMULLR
R0, R4, R5
R6, R2
;
;
;
;
Multiplies
and writes
Multiplies
and writes
R4
to
R6
to
and R5, truncates top 32 bits
R0
and R2, rounds the top 32 bits
R6.
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11.6.6.9 SMUAD and SMUSD
Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax
op{X}{cond} Rd, Rn, Rm
where:
op
is one of:
SMUAD Signed Dual Multiply Add.
SMUADX Signed Dual Multiply Add Reversed.
SMUSD Signed Dual Multiply Subtract.
SMUSDX Signed Dual Multiply Subtract Reversed.
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each
operand. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Adds the two multiplication results together.
Writes the result of the addition to the destination register.
The SMUSD instruction interprets the values from the first and second operands as two’s complement signed
integers. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.
Writes the result of the subtraction to the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
Sets the Q flag if the addition overflows. The multiplications cannot overflow.
Examples
SMUAD
R0, R4, R5
SMUADX
R3, R7, R4
SMUSD
R3, R6, R2
SMUSDX
R4, R5, R3
144
;
;
;
;
;
;
;
;
;
;
Multiplies bottom halfword of R4 with the bottom
halfword of R5, adds multiplication of top halfword
of R4 with top halfword of R5, writes to R0
Multiplies bottom halfword of R7 with top halfword
of R4, adds multiplication of top halfword of R7
with bottom halfword of R4, writes to R3
Multiplies bottom halfword of R4 with bottom halfword
of R6, subtracts multiplication of top halfword of R6
with top halfword of R3, writes to R3
Multiplies bottom halfword of R5 with top halfword of
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; R3, subtracts multiplication of top halfword of R5
; with bottom halfword of R3, writes to R4.
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11.6.6.10 SMUL and SMULW
Signed Multiply (halfwords) and Signed Multiply (word by halfword)
Syntax
op{XY}{cond} Rd,Rn, Rm
op{Y}{cond} Rd. Rn, Rm
For SMULXY only:
op
is one of:
SMUL{XY}
Signed Multiply (halfwords).
X and Y specify which halfword of the source registers Rn and Rm is used as
the first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0] of Rn is used.
If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot
tom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMULW{Y}
Signed Multiply (word by halfword).
Y specifies which halfword of the source register Rm is used as the second mul
tiply operand.
If Y is B, then the bottom halfword (bits [15:0]) of Rm is used.
If Y is T, then the top halfword (bits [31:16]) of Rm is used.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMULBB, SMULTB, SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed
16-bit integers. These instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Writes the 32-bit result of the multiplication in Rd.
The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two
halfword 16-bit signed integers. These instructions:
Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.
Writes the signed most significant 32 bits of the 48-bit result in the destination register.
Restrictions
In these instructions:
146
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Examples
SMULBT
R0, R4, R5
SMULBB
R0, R4, R5
SMULTT
R0, R4, R5
SMULTB
R0, R4, R5
;
;
;
;
;
;
;
;
;
;
SAM4N8/SAM4N16 [DATASHEET]
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Multiplies the bottom halfword of R4 with the
top halfword of R5, multiplies results and
writes to R0
Multiplies the bottom halfword of R4 with the
bottom halfword of R5, multiplies results and
writes to R0
Multiplies the top halfword of R4 with the top
halfword of R5, multiplies results and writes
to R0
Multiplies the top halfword of R4 with the
SMULWT
R4, R5, R3
SMULWB
R4, R5, R3
;
;
;
;
;
;
bottom halfword of R5, multiplies results and
and writes to R0
Multiplies R5 with the top halfword of R3,
extracts top 32 bits and writes to R4
Multiplies R5 with the bottom halfword of R3,
extracts top 32 bits and writes to R4.
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11.6.6.11 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit
result.
Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op
is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
cond
is an optional condition code, see “Conditional Execution” .
RdHi, RdLo
are the destination registers. For UMLAL and SMLAL they also hold the accu
mulating value.
Rn, Rm
are registers holding the operands.
Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and
places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers,
adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to
RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the
result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies
these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result
back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL
SMLAL
148
R0, R4, R5, R6
R4, R5, R3, R8
SAM4N8/SAM4N16 [DATASHEET]
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; Unsigned (R4,R0) = R5 x R6
; Signed (R5,R4) = (R5,R4) + R3 x R8
11.6.6.12 SDIV and UDIV
Signed Divide and Unsigned Divide.
Syntax
SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register. If Rd is omitted, the destination register is Rn.
Rn
is the register holding the value to be divided.
Rm
is a register holding the divisor.
Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not change the flags.
Examples
SDIV
UDIV
R0, R2, R4
R8, R8, R1
; Signed divide, R0 = R2/R4
; Unsigned divide, R8 = R8/R1
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11.6.7 Saturating Instructions
The table below shows the saturating instructions:
Table 11-22.
Saturating Instructions
Mnemonic
Description
SSAT
Signed Saturate
SSAT16
Signed Saturate Halfword
USAT
Unsigned Saturate
USAT16
Unsigned Saturate Halfword
QADD
Saturating Add
QSUB
Saturating Subtract
QSUB16
Saturating Subtract 16
QASX
Saturating Add and Subtract with Exchange
QSAX
Saturating Subtract and Add with Exchange
QDADD
Saturating Double and Add
QDSUB
Saturating Double and Subtract
UQADD16
Unsigned Saturating Add 16
UQADD8
Unsigned Saturating Add 8
UQASX
Unsigned Saturating Add and Subtract with Exchange
UQSAX
Unsigned Saturating Subtract and Add with Exchange
UQSUB16
Unsigned Saturating Subtract 16
UQSUB8
Unsigned Saturating Subtract 8
For signed n-bit saturation, this means that:
If the value to be saturated is less than -2n-1, the result returned is -2n-1
If the value to be saturated is greater than 2n-1-1, the result returned is 2n-1-1
Otherwise, the result returned is the same as the value to be saturated.
For unsigned n-bit saturation, this means that:
If the value to be saturated is less than 0, the result returned is 0
If the value to be saturated is greater than 2n-1, the result returned is 2n-1
Otherwise, the result returned is the same as the value to be saturated.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, the
MSR instruction must be used; see “MSR” .
To read the state of the Q flag, the MRS instruction must be used; see “MRS” .
150
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11.6.7.1 SSAT and USAT
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.
Syntax
op{cond} Rd, #n, Rm {, shift #s}
where:
op
is one of:
SSAT Saturates a signed value to a signed range.
USAT Saturates a signed value to an unsigned range.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
n
specifies the bit position to saturate to:
n ranges from 1
n ranges from 0 to 31 for USAT.
to 32 for SSAT
Rm
is the register containing the value to saturate.
shift #s
is an optional shift applied to Rm before saturating. It must be one of the
following:
ASR #s
where s is in the range 1 to 31.
LSL #s
where s is in the range 0 to 31.
Operation
These instructions saturate to a signed or unsigned n-bit value.
The SSAT instruction applies the specified shift, then saturates to the signed range -2n–1 £ x £ 2n–1-1.
The USAT instruction applies the specified shift, then saturates to the unsigned range 0 £ x £ 2n-1.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
SSAT
R7, #16, R7, LSL #4
USATNE
R0, #7, R5
;
;
;
;
;
Logical shift left value in R7 by 4, then
saturate it as a signed 16-bit value and
write it back to R7
Conditionally saturate value in R5 as an
unsigned 7 bit value and write it to R0.
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11.6.7.2 SSAT16 and USAT16
Signed Saturate and Unsigned Saturate to any bit position for two halfwords.
Syntax
op{cond} Rd, #n, Rm
where:
op
is one of:
SSAT16 Saturates a signed halfword value to a signed range.
USAT16 Saturates a signed halfword value to an unsigned range.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
n
specifies the bit position to saturate to:
n ranges from 1
n ranges from 0 to 15 for USAT.
to 16 for SSAT
Rm
is the register containing the value to saturate.
Operation
The SSAT16 instruction:
Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two signed 16-bit halfwords to the destination register.
The USAT16 instruction:
Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit
position in n.
Writes the results as two unsigned halfwords in the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
SSAT16
USAT16NE
152
R7, #9, R2
R0, #13, R5
;
;
;
;
;
;
Saturates the top and bottom highwords of R2
as 9-bit values, writes to corresponding halfword
of R7
Conditionally saturates the top and bottom
halfwords of R5 as 13-bit values, writes to
corresponding halfword of R0.
SAM4N8/SAM4N16 [DATASHEET]
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11.6.7.3 QADD and QSUB
Saturating Add and Saturating Subtract, signed.
Syntax
op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
QADD Saturating 32-bit add.
QADD8 Saturating four 8-bit integer additions.
QADD16 Saturating two 16-bit integer additions.
QSUB Saturating 32-bit subtraction.
QSUB8 Saturating four 8-bit integer subtraction.
QSUB16 Saturating two 16-bit integer subtraction.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
These instructions add or subtract two, four or eight values from the first and second operands and then writes a
signed saturated value in the destination register.
The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed
range -2n–1 £ x £ 2n–1-1, where x is given by the number of bits applied in the instruction, 32, 16 or 8.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the
QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit
and 16-bit QADD and QSUB instructions always leave the Q flag unchanged.
To clear the Q flag to 0, the MSR instruction must be used; see “MSR” .
To read the state of the Q flag, the MRS instruction must be used; see “MRS” .
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
QADD16
R7, R4, R2
QADD8
R3, R1, R6
QSUB16
R4, R2, R3
QSUB8
R4, R2, R5
;
;
;
;
;
;
;
;
;
;
;
;
Adds halfwords of R4 with corresponding halfword of
R2, saturates to 16 bits and writes to
corresponding halfword of R7
Adds bytes of R1 to the corresponding bytes of R6,
saturates to 8 bits and writes to corresponding
byte of R3
Subtracts halfwords of R3 from corresponding
halfword of R2, saturates to 16 bits, writes to
corresponding halfword of R4
Subtracts bytes of R5 from the corresponding byte
in R2, saturates to 8 bits, writes to corresponding
byte of R4.
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11.6.7.4 QASX and QSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed.
Syntax
op{cond} {Rd}, Rm, Rn
where:
op
is one of:
QASX Add and Subtract with Exchange and Saturate.
QSAX Subtract and Add with Exchange and Saturate.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The QASX instruction:
1. Adds the top halfword of the source operand with the bottom halfword of the second operand.
2. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
3.
Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1,
where x equals 16, to the bottom halfword of the destination register.
4.
Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.
The QSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Adds the bottom halfword of the source operand with the top halfword of the second operand.
3.
Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register.
4.
Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where
x equals 16, to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
QASX
QSAX
154
R7, R4, R2 ;
;
;
;
;
R0, R3, R5 ;
;
;
;
Adds top halfword of R4 to bottom halfword of R2,
saturates to 16 bits, writes to top halfword of R7
Subtracts top highword of R2 from bottom halfword of
R4, saturates to 16 bits and writes to bottom halfword
of R7
Subtracts bottom halfword of R5 from top halfword of
R3, saturates to 16 bits, writes to top halfword of R0
Adds bottom halfword of R3 to top halfword of R5,
saturates to 16 bits, writes to bottom halfword of R0.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.7.5 QDADD and QDSUB
Saturating Double and Add and Saturating Double and Subtract, signed.
Syntax
op{cond} {Rd}, Rm, Rn
where:
op
is one of:
QDADD Saturating Double and Add.
QDSUB Saturating Double and Subtract.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rm, Rn
are registers holding the first and second operands.
Operation
The QDADD instruction:
Doubles the second operand value.
Adds the result of the doubling to the signed saturated value in the first operand.
Writes the result to the destination register.
The QDSUB instruction:
Doubles the second operand value.
Subtracts the doubled value from the signed saturated value in the first operand.
Writes the result to the destination register.
Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range –
231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR.
Restrictions
Do not use SP and do not use PC.
Condition Flags
If saturation occurs, these instructions set the Q flag to 1.
Examples
QDADD
R7, R4, R2
QDSUB
R0, R3, R5
;
;
;
;
Doubles and saturates R4 to 32 bits, adds R2,
saturates to 32 bits, writes to R7
Subtracts R3 doubled and saturated to 32 bits
from R5, saturates to 32 bits, writes to R0.
SAM4N8/SAM4N16 [DATASHEET]
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11.6.7.6 UQASX and UQSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned.
Syntax
op{cond} {Rd}, Rm, Rn
where:
type
is one of:
UQASX Add and Subtract with Exchange and Saturate.
UQSAX Subtract and Add with Exchange and Saturate.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The UQASX instruction:
1. Adds the bottom halfword of the source operand with the top halfword of the second operand.
2. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
3.
Saturates the results of the sum and writes a 16-bit unsigned integer in the range
0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.
4.
Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where
x equals 16, to the bottom halfword of the destination register.
The UQSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Adds the bottom halfword of the first operand with the top halfword of the second operand.
3.
Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where
x equals 16, to the top halfword of the destination register.
4.
Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x
equals 16, to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQASX
R7, R4, R2
UQSAX
R0, R3, R5
156
;
;
;
;
;
;
;
;
Adds top halfword of R4 with bottom halfword of R2,
saturates to 16 bits, writes to top halfword of R7
Subtracts top halfword of R2 from bottom halfword of
R4, saturates to 16 bits, writes to bottom halfword of R7
Subtracts bottom halfword of R5 from top halfword of R3,
saturates to 16 bits, writes to top halfword of R0
Adds bottom halfword of R4 to top halfword of R5
saturates to 16 bits, writes to bottom halfword of R0.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.7.7 UQADD and UQSUB
Saturating Add and Saturating Subtract Unsigned.
Syntax
op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op
is one of:
UQADD8 Saturating four unsigned 8-bit integer additions.
UQADD16 Saturating two unsigned 16-bit integer additions.
UDSUB8 Saturating four unsigned 8-bit integer subtractions.
UQSUB16 Saturating two unsigned 16-bit integer subtractions.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
These instructions add or subtract two or four values and then writes an unsigned saturated value in the
destination register.
The UQADD16 instruction:
Adds the respective top and bottom halfwords of the first and second operands.
Saturates the result of the additions for each halfword in the destination register to the unsigned range
0 £ x £ 216-1, where x is 16.
The UQADD8 instruction:
Adds each respective byte of the first and second operands.
Saturates the result of the addition for each byte in the destination register to the unsigned range 0 £ x £ 281, where x is 8.
The UQSUB16 instruction:
Subtracts both halfwords of the second operand from the respective halfwords of the first operand.
Saturates the result of the differences in the destination register to the unsigned range 0 £ x £ 216-1, where x
is 16.
The UQSUB8 instructions:
Subtracts the respective bytes of the second operand from the respective bytes of the first operand.
Saturates the results of the differences for each byte in the destination register to the unsigned range
0 £ x £ 28-1, where x is 8.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQADD16
R7, R4, R2
UQADD8
R4, R2, R5
UQSUB16
R6, R3, R0
;
;
;
;
;
;
Adds halfwords in R4 to corresponding halfword in R2,
saturates to 16 bits, writes to corresponding halfword of R7
Adds bytes of R2 to corresponding byte of R5, saturates
to 8 bits, writes to corresponding bytes of R4
Subtracts halfwords in R0 from corresponding halfword
in R3, saturates to 16 bits, writes to corresponding
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157
UQSUB8
158
R1, R5, R6
; halfword in R6
; Subtracts bytes in R6 from corresponding byte of R5,
; saturates to 8 bits, writes to corresponding byte of R1.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.8 Packing and Unpacking Instructions
The table below shows the instructions that operate on packing and unpacking data:
Table 11-23.
Packing and Unpacking Instructions
Mnemonic
Description
PKH
Pack Halfword
SXTAB
Extend 8 bits to 32 and add
SXTAB16
Dual extend 8 bits to 16 and add
SXTAH
Extend 16 bits to 32 and add
SXTB
Sign extend a byte
SXTB16
Dual extend 8 bits to 16 and add
SXTH
Sign extend a halfword
UXTAB
Extend 8 bits to 32 and add
UXTAB16
Dual extend 8 bits to 16 and add
UXTAH
Extend 16 bits to 32 and add
UXTB
Zero extend a byte
UXTB16
Dual zero extend 8 bits to 16 and add
UXTH
Zero extend a halfword
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11.6.8.1 PKHBT and PKHTB
Pack Halfword
Syntax
op{cond} {Rd}, Rn, Rm {, LSL #imm}
op{cond} {Rd}, Rn, Rm {, ASR #imm}
where:
op
is one of:
PKHBT Pack Halfword, bottom and top with shift.
PKHTB Pack Halfword, top and bottom with shift.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register
Rm
is the second operand register holding the value to be optionally shifted.
imm
is the shift length. The type of shift length depends on the instruction:
For PKHBT
LSL a left shift with a shift length from 1 to 31, 0 means no shift.
For PKHTB
ASR an arithmetic shift right with a shift length from 1 to 32,
a shift of 32-bits is encoded as 0b00000.
Operation
The PKHBT instruction:
1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register.
2. If shifted, the shifted value of the second operand is written to the top halfword of the destination register.
The PKHTB instruction:
1. Writes the value of the top halfword of the first operand to the top halfword of the destination register.
2. If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
PKHBT
R3, R4, R5 LSL #0
PKHTB
R4, R0, R2 ASR #1
160
;
;
;
;
;
;
Writes bottom halfword of R4 to bottom halfword of
R3, writes top halfword of R5, unshifted, to top
halfword of R3
Writes R2 shifted right by 1 bit to bottom halfword
of R4, and writes top halfword of R0 to top
halfword of R4.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.8.2 SXT and UXT
Sign extend and Zero extend.
Syntax
op{cond} {Rd,} Rm {, ROR #n}
op{cond} {Rd}, Rm {, ROR #n}
where:
op
is one of:
SXTB Sign extends an 8-bit value to a 32-bit value.
SXTH Sign extends a 16-bit value to a 32-bit value.
SXTB16 Sign extends two 8-bit values to two 16-bit values.
UXTB Zero extends an 8-bit value to a 32-bit value.
UXTH Zero extends a 16-bit value to a 32-bit value.
UXTB16 Zero extends two 8-bit values to two 16-bit values.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rm
is the register holding the value to extend.
ROR #n
is one of:
ROR #8 Value from Rm is rotated right 8 bits.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
̶
SXTB extracts bits[7:0] and sign extends to 32 bits.
̶
UXTB extracts bits[7:0] and zero extends to 32 bits.
̶
SXTH extracts bits[15:0] and sign extends to 32 bits.
̶
UXTH extracts bits[15:0] and zero extends to 32 bits.
̶
SXTB16 extracts bits[7:0] and sign extends to 16 bits,
and extracts bits [23:16] and sign extends to 16 bits.
̶
UXTB16 extracts bits[7:0] and zero extends to 16 bits,
and extracts bits [23:16] and zero extends to 16 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH
R4, R6, ROR #16
UXTB
R3, R10
;
;
;
;
Rotates R6 right by 16 bits, obtains bottom halfword of
of result, sign extends to 32 bits and writes to R4
Extracts lowest byte of value in R10, zero extends, and
writes to R3.
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11.6.8.3 SXTA and UXTA
Signed and Unsigned Extend and Add
Syntax
op{cond} {Rd,} Rn, Rm {, ROR #n}
op{cond} {Rd,} Rn, Rm {, ROR #n}
where:
op
is one of:
SXTAB Sign extends an 8-bit value to a 32-bit value and add.
SXTAH Sign extends a 16-bit value to a 32-bit value and add.
SXTAB16 Sign extends two 8-bit values to two 16-bit values and add.
UXTAB Zero extends an 8-bit value to a 32-bit value and add.
UXTAH Zero extends a 16-bit value to a 32-bit value and add.
UXTAB16 Zero extends two 8-bit values to two 16-bit values and add.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the first operand register.
Rm
is the register holding the value to rotate and extend.
ROR #n
is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
̶
SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits.
̶
̶
̶
̶
̶
3.
UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits.
SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits.
UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits.
SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits,
and extracts bits [23:16] from Rm and sign extends to 16 bits.
UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits,
and extracts bits [23:16] from Rm and zero extends to 16 bits.
Adds the signed or zero extended value to the word or corresponding halfword of Rn and writes the result in
Rd.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
162
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
SXTAH
UXTAB
R4, R8, R6, ROR #16 ;
;
;
R3, R4, R10
;
;
Rotates R6 right by 16 bits, obtains bottom
halfword, sign extends to 32 bits, adds
R8,and writes to R4
Extracts bottom byte of R10 and zero extends
to 32 bits, adds R4, and writes to R3.
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11.6.9 Bitfield Instructions
The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields:
Table 11-24.
164
Packing and Unpacking Instructions
Mnemonic
Description
BFC
Bit Field Clear
BFI
Bit Field Insert
SBFX
Signed Bit Field Extract
SXTB
Sign extend a byte
SXTH
Sign extend a halfword
UBFX
Unsigned Bit Field Extract
UXTB
Zero extend a byte
UXTH
Zero extend a halfword
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.9.1 BFC and BFI
Bit Field Clear and Bit Field Insert.
Syntax
BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the source register.
lsb
is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width
is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are
unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit
position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
BFC
BFI
R4, #8, #12
R9, R2, #8, #12
; Clear bit 8 to bit 19 (12 bits) of R4 to 0
; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2.
SAM4N8/SAM4N16 [DATASHEET]
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11.6.9.2 SBFX and UBFX
Signed Bit Field Extract and Unsigned Bit Field Extract.
Syntax
SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rn
is the source register.
lsb
is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width
is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination
register.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SBFX
UBFX
166
R0, R1, #20, #4
;
;
R8, R11, #9, #10 ;
;
Extract bit 20 to bit 23 (4 bits) from R1 and sign
extend to 32 bits and then write the result to R0.
Extract bit 9 to bit 18 (10 bits) from R11 and zero
extend to 32 bits and then write the result to R8.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.9.3 SXT and UXT
Sign extend and Zero extend.
Syntax
SXTextend{cond} {Rd,} Rm {, ROR #n}
UXTextend{cond} {Rd}, Rm {, ROR #n}
where:
extend
is one of:
B Extends an 8-bit value to a 32-bit value.
H Extends a 16-bit value to a 32-bit value.
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
Rm
is the register holding the value to extend.
ROR #n
is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
̶
SXTB extracts bits[7:0] and sign extends to 32 bits.
̶
UXTB extracts bits[7:0] and zero extends to 32 bits.
̶
SXTH extracts bits[15:0] and sign extends to 32 bits.
̶
UXTH extracts bits[15:0] and zero extends to 32 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH
R4, R6, ROR #16
UXTB
R3, R10
;
;
;
;
;
Rotate R6 right by 16 bits, then obtain the lower
halfword of the result and then sign extend to
32 bits and write the result to R4.
Extract lowest byte of the value in R10 and zero
extend it, and write the result to R3.
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11.6.10 Branch and Control Instructions
The table below shows the branch and control instructions:
Table 11-25.
168
Branch and Control Instructions
Mnemonic
Description
B
Branch
BL
Branch with Link
BLX
Branch indirect with Link
BX
Branch indirect
CBNZ
Compare and Branch if Non Zero
CBZ
Compare and Branch if Zero
IT
If-Then
TBB
Table Branch Byte
TBH
Table Branch Halfword
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
11.6.10.1 B, BL, BX, and BLX
Branch instructions.
Syntax
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B
is branch (immediate).
BL
is branch with link (immediate).
BX
is branch indirect (register).
BLX
is branch indirect with link (register).
cond
is an optional condition code, see “Conditional Execution” .
label
is a PC-relative expression. See “PC-relative Expressions” .
Rm
is a register that indicates an address to branch to. Bit[0] of the value in Rm
must be 1, but the address to branch to is created by changing bit[0] to 0.
Operation
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
The BL and BLX instructions write the address of the next instruction to LR (the link register, R14).
The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch
instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT” .
The table below shows the ranges for the various branch instructions.
Table 11-26.
Branch Ranges
Instruction
Branch Range
B label
−16 MB to +16 MB
Bcond label (outside IT block)
−1 MB to +1 MB
Bcond label (inside IT block)
−16 MB to +16 MB
BL{cond} label
−16 MB to +16 MB
BX{cond} Rm
Any value in register
BLX{cond} Rm
Any value in register
The .W suffix might be used to get the maximum branch range. See “Instruction Width Selection” .
Restrictions
The restrictions are:
Do not use PC in the BLX instruction
For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address
created by changing bit[0] to 0
When any of these instructions is inside an IT block, it must be the last instruction of the IT block.
Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer
branch range when it is inside an IT block.
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Condition Flags
These instructions do not change the flags.
Examples
170
B
BLE
B.W
BEQ
BEQ.W
BL
loopA
ng
target
target
target
funC
BX
BXNE
BLX
LR
R0
R0
;
;
;
;
;
;
;
;
;
;
Branch to loopA
Conditionally branch to label ng
Branch to target within 16MB range
Conditionally branch to target
Conditionally branch to target within 1MB
Branch with link (Call) to function funC, return address
stored in LR
Return from function call
Conditionally branch to address stored in R0
Branch with link and exchange (Call) to a address stored in R0.
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11.6.10.2 CBZ and CBNZ
Compare and Branch on Zero, Compare and Branch on Non-Zero.
Syntax
CBZ Rn, label
CBNZ Rn, label
where:
Rn
is the register holding the operand.
label
is the branch destination.
Operation
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of
instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP
Rn, #0
BEQ
label
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP
Rn, #0
BNE
label
Restrictions
The restrictions are:
Rn must be in the range of R0 to R7
The branch destination must be within 4 to 130 bytes after the instruction
These instructions must not be used inside an IT block.
Condition Flags
These instructions do not change the flags.
Examples
CBZ
CBNZ
R5, target
R0, target
; Forward branch if R5 is zero
; Forward branch if R0 is not zero
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11.6.10.3 IT
If-Then condition instruction.
Syntax
IT{x{y{z}}} cond
where:
x
specifies the condition switch for the second instruction in the IT block.
y
specifies the condition switch for the third instruction in the IT block.
z
specifies the condition switch for the fourth instruction in the IT block.
cond
specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT block can be either:
T
Then. Applies the condition cond to the instruction.
E
Else. Applies the inverse condition of cond to the instruction.
It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in
the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E.
Operation
The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some
of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT
block.
The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their
syntax.
The assembler might be able to generate the required IT instructions for conditional instructions automatically, so
that the user does not have to write them. See the assembler documentation for details.
A BKPT instruction in an IT block is always executed, even if its condition fails.
Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an
exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked
PSR.
Instructions designed for use for exception returns can be used as normal to return from the exception, and
execution of the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to
branch to an instruction in an IT block.
Restrictions
The following instructions are not permitted in an IT block:
IT
CBZ and CBNZ
CPSID and CPSIE.
Other restrictions when using an IT block are:
172
A branch or any instruction that modifies the PC must either be outside an IT block or must be the last
instruction inside the IT block. These are:
̶
ADD PC, PC, Rm
̶
MOV PC, Rm
̶
B, BL, BX, BLX
̶
Any LDM, LDR, or POP instruction that writes to the PC
̶
TBB and TBH
Do not branch to any instruction inside an IT block, except when returning from an exception handler
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All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside
an IT block but has a larger branch range if it is inside one
Each instruction inside the IT block must specify a condition code suffix that is either the same or logical
inverse as for the other instructions in the block.
Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler
directives within them.
Condition Flags
This instruction does not change the flags.
Example
ITTE
ANDNE
ADDSNE
MOVEQ
NE
R0, R0, R1
R2, R2, #1
R2, R3
;
;
;
;
Next 3 instructions are conditional
ANDNE does not update condition flags
ADDSNE updates condition flags
Conditional move
CMP
R0, #9
ITE
ADDGT
ADDLE
GT
R1, R0, #55
R1, R0, #48
;
;
;
;
;
Convert R0 hex value (0 to 15) into ASCII
('0'-'9', 'A'-'F')
Next 2 instructions are conditional
Convert 0xA -> 'A'
Convert 0x0 -> '0'
IT
ADDGT
GT
R1, R1, #1
; IT block with only one conditional instruction
; Increment R1 conditionally
ITTEE
MOVEQ
ADDEQ
ANDNE
BNE.W
EQ
R0, R1
R2, R2, #10
R3, R3, #1
dloop
;
;
;
;
;
;
IT
ADD
NE
R0, R0, R1
; Next instruction is conditional
; Syntax error: no condition code used in IT block
Next 4 instructions are conditional
Conditional move
Conditional add
Conditional AND
Branch instruction can only be used in the last
instruction of an IT block
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11.6.10.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
Syntax
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn
is the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately
following the TBB or TBH instruction.
Rm
is the index register. This contains an index into the table. For halfword tables,
LSL #1 doubles the value in Rm to form the right offset into the table.
Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword
offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch
offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the
unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the
address of the byte immediately after the TBB or TBH instruction.
Restrictions
The restrictions are:
Rn must not be SP
Rm must not be SP and must not be PC
When any of these instructions is used inside an IT block, it must be the last instruction of the IT block.
Condition Flags
These instructions do not change the flags.
Examples
ADR.W
TBB
R0, BranchTable_Byte
[R0, R1]
; R1 is the index, R0 is the base address of the
; branch table
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
DCB
0
; Case1 offset calculation
DCB
((Case2-Case1)/2) ; Case2 offset calculation
DCB
((Case3-Case1)/2) ; Case3 offset calculation
TBH
[PC, R1, LSL #1]
; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI
((CaseA - BranchTable_H)/2)
DCI
((CaseB - BranchTable_H)/2)
DCI
((CaseC - BranchTable_H)/2)
CaseA
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; CaseA offset calculation
; CaseB offset calculation
; CaseC offset calculation
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
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11.6.11 Miscellaneous Instructions
The table below shows the remaining Cortex-M4 instructions:
Table 11-27.
176
Miscellaneous Instructions
Mnemonic
Description
BKPT
Breakpoint
CPSID
Change Processor State, Disable Interrupts
CPSIE
Change Processor State, Enable Interrupts
DMB
Data Memory Barrier
DSB
Data Synchronization Barrier
ISB
Instruction Synchronization Barrier
MRS
Move from special register to register
MSR
Move from register to special register
NOP
No Operation
SEV
Send Event
SVC
Supervisor Call
WFI
Wait For Interrupt
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11.6.11.1 BKPT
Breakpoint.
Syntax
BKPT #imm
where:
imm
is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system
state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional information about the
breakpoint.
The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition
specified by the IT instruction.
Condition Flags
This instruction does not change the flags.
Examples
BKPT 0xAB
Note:
; Breakpoint with immediate value set to 0xAB (debugger can
; extract the immediate value by locating it using the PC)
ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other
than Semi-hosting.
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11.6.11.2 CPS
Change Processor State.
Syntax
CPSeffect iflags
where:
effect
is one of:
IE
Clears the special purpose register.
ID
Sets the special purpose register.
iflags
is a sequence of one or more flags:
i
Set or clear PRIMASK.
f
Set or clear FAULTMASK.
Operation
CPS changes the PRIMASK and FAULTMASK special register values. See “Exception Mask Registers” for more
information about these registers.
Restrictions
The restrictions are:
Use CPS only from privileged software, it has no effect if used in unprivileged software
CPS cannot be conditional and so must not be used inside an IT block.
Condition Flags
This instruction does not change the condition flags.
Examples
CPSID
CPSID
CPSIE
CPSIE
178
i
f
i
f
;
;
;
;
Disable interrupts and configurable fault handlers (set PRIMASK)
Disable interrupts and all fault handlers (set FAULTMASK)
Enable interrupts and configurable fault handlers (clear PRIMASK)
Enable interrupts and fault handlers (clear FAULTMASK)
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11.6.11.3 DMB
Data Memory Barrier.
Syntax
DMB{cond}
where:
cond
is an optional condition code, see “Conditional Execution” .
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order,
before the DMB instruction are completed before any explicit memory accesses that appear, in program order,
after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access
memory.
Condition Flags
This instruction does not change the flags.
Examples
DMB
; Data Memory Barrier
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11.6.11.4 DSB
Data Synchronization Barrier.
Syntax
DSB{cond}
where:
cond
is an optional condition code, see “Conditional Execution” .
Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program
order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory
accesses before it complete.
Condition Flags
This instruction does not change the flags.
Examples
DSB ; Data Synchronisation Barrier
180
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11.6.11.5 ISB
Instruction Synchronization Barrier.
Syntax
ISB{cond}
where:
cond
is an optional condition code, see “Conditional Execution” .
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions
following the ISB are fetched from memory again, after the ISB instruction has been completed.
Condition Flags
This instruction does not change the flags.
Examples
ISB
; Instruction Synchronisation Barrier
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11.6.11.6 MRS
Move the contents of a special register to a general-purpose register.
Syntax
MRS{cond} Rd, spec_reg
where:
cond
is an optional condition code, see “Conditional Execution” .
Rd
is the destination register.
spec_reg
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to
clear the Q flag.
In process swap code, the programmers model state of the process being swapped out must be saved, including
relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These
operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence.
Note:
BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See “MSR” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MRS
182
R0, PRIMASK ; Read PRIMASK value and write it to R0
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11.6.11.7 MSR
Move the contents of a general-purpose register into the specified special register.
Syntax
MSR{cond} spec_reg, Rn
where:
cond
is an optional condition code, see “Conditional Execution” .
Rn
is the source register.
spec_reg
can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
The register access operation in MSR depends on the privilege level. Unprivileged software can only access the
APSR. See “Application Program Status Register” . Privileged software can access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
Note:
When the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
Rn is non-zero and the current BASEPRI value is 0
Rn is non-zero and less than the current BASEPRI value.
See “MRS” .
Restrictions
Rn must not be SP and must not be PC.
Condition Flags
This instruction updates the flags explicitly based on the value in Rn.
Examples
MSR
CONTROL, R1 ; Read R1 value and write it to the CONTROL register
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11.6.11.8 NOP
No Operation.
Syntax
NOP{cond}
where:
cond
is an optional condition code, see “Conditional Execution” .
Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the
pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
Condition Flags
This instruction does not change the flags.
Examples
NOP
184
; No operation
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11.6.11.9 SEV
Send Event.
Syntax
SEV{cond}
where:
cond
is an optional condition code, see “Conditional Execution” .
Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register to 1, see “Power Management” .
Condition Flags
This instruction does not change the flags.
Examples
SEV ; Send Event
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11.6.11.10 SVC
Supervisor Call.
Syntax
SVC{cond} #imm
where:
cond
is an optional condition code, see “Conditional Execution” .
imm
is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The SVC instruction causes the SVC exception.
imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service
is being requested.
Condition Flags
This instruction does not change the flags.
Examples
SVC
186
0x32
; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
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11.6.11.11 WFI
Wait for Interrupt.
Syntax
WFI{cond}
where:
cond
is an optional condition code, see “Conditional Execution” .
Operation
WFI is a hint instruction that suspends execution until one of the following events occurs:
An exception
A Debug Entry request, regardless of whether Debug is enabled.
Condition Flags
This instruction does not change the flags.
Examples
WFI ; Wait for interrupt
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11.7
Cortex-M4 Core Peripherals
11.7.1 Peripherals
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low
latency interrupt processing. See Section 11.8 “Nested Vectored Interrupt Controller (NVIC)”
System Control Block (SCB)
The System Control Block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions. See Section 11.9 “System Control Block (SCB)”
System Timer (SysTick)
The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System
(RTOS) tick timer or as a simple counter. See Section 11.10 “System Timer (SysTick)”
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region.
See Section 11.11 “Memory Protection Unit (MPU)”
11.7.2
Address Map
The address map of the Private peripheral bus (PPB) is:
Table 11-28.
Core Peripheral Register Regions
Address
Core Peripheral
0xE000E008-0xE000E00F
System Control Block
0xE000E010-0xE000E01F
System Timer
0xE000E100-0xE000E4EF
Nested Vectored Interrupt Controller
0xE000ED00-0xE000ED3F
System control block
0xE000ED90-0xE000EDB8
Memory Protection Unit
0xE000EF00-0xE000EF03
Nested Vectored Interrupt Controller
In register descriptions:
188
The required privilege gives the privilege level required to access the register, as follows:
̶
Privileged: Only privileged software can access the register.
̶
Unprivileged: Both unprivileged and privileged software can access the register.
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11.8
Nested Vectored Interrupt Controller (NVIC)
This section describes the NVIC and the registers it uses. The NVIC supports:
1 to 30 interrupts.
A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so
level 0 is the highest interrupt priority.
Level detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction overhead. This provides low latency exception handling.
11.8.1 Level-sensitive Interrupts
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral
deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware
and Software Control of Interrupts” ). For a level-sensitive interrupt, if the signal is not deasserted before the
processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR
again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.
11.8.1.1 Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
The NVIC detects a rising edge on the interrupt signal
A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending
Registers” , or to the NVIC_STIR register to make an interrupt pending, see “Software Trigger Interrupt
Register” .
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active.
Then:
̶
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to
inactive.
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not
change. Otherwise, the state of the interrupt changes to inactive.
11.8.2 NVIC Design Hints and Tips
Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from
taking that interrupt.
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Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector
table are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the
“Vector Table Offset Register” .
11.8.2.1 NVIC Programming Hints
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides
the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 11-29.
CMSIS Functions for NVIC Control
CMSIS Interrupt Control Function
Description
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
Set the priority grouping
void NVIC_EnableIRQ(IRQn_t IRQn)
Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn)
Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
Return true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn)
Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
Clear IRQn pending status
uint32_t NVIC_GetActive (IRQn_t IRQn)
Return the IRQ number of the active interrupt
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn)
Read priority of IRQn
void NVIC_SystemReset (void)
Reset the system
The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS
documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit
integers, so that:
̶
The array ISER[0] corresponds to the registers ISER0
̶
The array ICER[0] corresponds to the registers ICER0
̶
The array ISPR[0] corresponds to the registers ISPR0
̶
The array ICPR[0]corresponds to the registers ICPR0
̶
The array IABR[0]corresponds to the registers IABR0
The 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to
IP[29] corresponds to the registers IPR0-IPR7, and the array entry IP[n] holds the interrupt priority for
interrupt n.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. Table 11-30
shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables
that have one bit per interrupt.
Table 11-30.
Mapping of Interrupts to the Interrupt Variables
CMSIS Array Elements (1)
Interrupts
0-29
Notes:
190
Set-enable
Clear-enable
Set-pending
Clear-pending
Active Bit
ISER[0]
ICER[0]
ISPR[0]
ICPR[0]
IABR[0]
1. Each array element corresponds to a single NVIC register, for example the ICER[0] element corresponds to the ICER0
register.
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11.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface
Table 11-31.
Nested Vectored Interrupt Controller (NVIC) Register Mapping
Offset
Register
Name
Access
Reset
0xE000E100
Interrupt Set-enable Register 0
NVIC_ISER0
Read-write
0x00000000
...
...
...
...
...
0xE000E11C
Interrupt Set-enable Register 7
NVIC_ISER7
Read-write
0x00000000
0XE000E180
Interrupt Clear-enable Register0
NVIC_ICER0
Read-write
0x00000000
...
...
...
...
...
0xE000E19C
Interrupt Clear-enable Register 7
NVIC_ICER7
Read-write
0x00000000
0XE000E200
Interrupt Set-pending Register 0
NVIC_ISPR0
Read-write
0x00000000
...
...
...
...
...
0xE000E21C
Interrupt Set-pending Register 7
NVIC_ISPR7
Read-write
0x00000000
0XE000E280
Interrupt Clear-pending Register 0
NVIC_ICPR0
Read-write
0x00000000
...
...
...
...
...
0xE000E29C
Interrupt Clear-pending Register 7
NVIC_ICPR7
Read-write
0x00000000
0xE000E300
Interrupt Active Bit Register 0
NVIC_IABR0
Read-write
0x00000000
...
...
...
...
...
0xE000E31C
Interrupt Active Bit Register 7
NVIC_IABR7
Read-write
0x00000000
0xE000E400
Interrupt Priority Register 0
NVIC_IPR0
Read-write
0x00000000
...
...
...
...
...
0xE000E41C
Interrupt Priority Register 7
NVIC_IPR7
Read-write
0x00000000
0xE000EF00
Software Trigger Interrupt Register
NVIC_STIR
Write-only
0x00000000
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11.8.3.1 Interrupt Set-enable Registers
Name:
NVIC_ISERx [x=0..7]
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SETENA
23
22
21
20
SETENA
15
14
13
12
SETENA
7
6
5
4
SETENA
These registers enable interrupts and show which interrupts are enabled.
• SETENA: Interrupt Set-enable
Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
Notes:
192
1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates
the interrupt, regardless of its priority.
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11.8.3.2 Interrupt Clear-enable Registers
Name:
NVIC_ICERx [x=0..7]
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CLRENA
23
22
21
20
CLRENA
15
14
13
12
CLRENA
7
6
5
4
CLRENA
These registers disable interrupts, and show which interrupts are enabled.
• CLRENA: Interrupt Clear-enable
Write:
0: No effect.
1: Disables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
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11.8.3.3 Interrupt Set-pending Registers
Name:
NVIC_ISPRx [x=0..7]
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SETPEND
23
22
21
20
SETPEND
15
14
13
12
SETPEND
7
6
5
4
SETPEND
These registers force interrupts into the pending state, and show which interrupts are pending.
• SETPEND: Interrupt Set-pending
Write:
0: No effect.
1: Changes the interrupt state to pending.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Notes:
194
1. Writing 1 to an ISPR bit corresponding to an interrupt that is pending has no effect.
2. Writing 1 to an ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to pending.
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11.8.3.4 Interrupt Clear-pending Registers
Name:
NVIC_ICPRx [x=0..7]
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CLRPEND
23
22
21
20
CLRPEND
15
14
13
12
CLRPEND
7
6
5
4
CLRPEND
These registers remove the pending state from interrupts, and show which interrupts are pending.
• CLRPEND: Interrupt Clear-pending
Write:
0: No effect.
1: Removes the pending state from an interrupt.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
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11.8.3.5 Interrupt Active Bit Registers
Name:
NVIC_IABRx [x=0..7]
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ACTIVE
23
22
21
20
ACTIVE
15
14
13
12
ACTIVE
7
6
5
4
ACTIVE
These registers indicate which interrupts are active.
• ACTIVE: Interrupt Active Flags
0: Interrupt is not active.
1: Interrupt is active.
Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
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11.8.3.6 Interrupt Priority Registers
Name:
NVIC_IPRx [x=0..7]
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PRI3
23
22
21
20
PRI2
15
14
13
12
PRI1
7
6
5
4
PRI0
The NVIC_IPR0-NVIC_IPR7 registers provide a 4-bit priority field for each interrupt. These registers are byte-accessible.
Each register holds four priority fields, that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[29]
• PRI3: Priority (4m+3)
Priority, Byte Offset 3, refers to register bits [31:24].
• PRI2: Priority (4m+2)
Priority, Byte Offset 2, refers to register bits [23:16].
• PRI1: Priority (4m+1)
Priority, Byte Offset 1, refers to register bits [15:8].
• PRI0: Priority (4m)
Priority, Byte Offset 0, refers to register bits [7:0].
Notes:
1. Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt. The
processor implements only bits[7:4] of each field; bits[3:0] read as zero and ignore writes.
2. for more information about the IP[0] to IP[29] interrupt priority array, that provides the software view of the interrupt priorities,
see Table 11-29, “CMSIS Functions for NVIC Control” .
3. The corresponding IPR number n is given by n = m DIV 4.
4. The byte offset of the required Priority field in this register is m MOD 4.
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11.8.3.7 Software Trigger Interrupt Register
Name:
NVIC_STIR
Access:
Write-only
Reset:
0x000000000
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
INTID
7
6
5
4
3
2
1
0
INTID
Write to this register to generate an interrupt from the software.
• INTID: Interrupt ID
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3.
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11.9
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions.
Ensure that the software uses aligned accesses of the correct size to access the system control block registers:
Except for the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it must use aligned word accesses
For the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it can use byte or aligned halfword or word
accesses.
The processor does not support unaligned accesses to system control block registers.
In a fault handler, to determine the true faulting address:
1. Read and save the MMFAR or SCB_BFAR value.
2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The
SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1.
The software must follow this sequence because another higher priority exception might change the SCB_MMFAR
or SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault
might change the SCB_MMFAR or SCB_BFAR value.
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11.9.1 System Control Block (SCB) User Interface
Table 11-32.
System Control Block (SCB) Register Mapping
Offset
Register
Name
Access
Reset
0xE000E008
Auxiliary Control Register
SCB_ACTLR
Read-write
0x00000000
0xE000ED00
CPUID Base Register
SCB_CPUID
Read-only
0x410FC240
(1)
0x00000000
0xE000ED04
Interrupt Control and State Register
SCB_ICSR
Read-write
0xE000ED08
Vector Table Offset Register
SCB_VTOR
Read-write
0x00000000
0xE000ED0C
Application Interrupt and Reset Control Register
SCB_AIRCR
Read-write
0xFA050000
0xE000ED10
System Control Register
SCB_SCR
Read-write
0x00000000
0xE000ED14
Configuration and Control Register
SCB_CCR
Read-write
0x00000200
0xE000ED18
System Handler Priority Register 1
SCB_SHPR1
Read-write
0x00000000
0xE000ED1C
System Handler Priority Register 2
SCB_SHPR2
Read-write
0x00000000
0xE000ED20
System Handler Priority Register 3
SCB_SHPR3
Read-write
0x00000000
0xE000ED24
System Handler Control and State Register
SCB_SHCSR
Read-write
0x00000000
(2)
Read-write
0x00000000
0xE000ED28
Configurable Fault Status Register
SCB_CFSR
0xE000ED2C
HardFault Status Register
SCB_HFSR
Read-write
0x00000000
0xE000ED34
MemManage Fault Address Register
SCB_MMFAR
Read-write
Unknown
0xE000ED38
BusFault Address Register
SCB_BFAR
Read-write
Unknown
0xE000ED3C
Auxiliary Fault Status Register
SCB_AFSR
Read-write
0x00000000
Notes: 1. See the register description for more information.
2. This register contains the subregisters: “MMFSR: Memory Management Fault Status Subregister” (0xE000ED28 - 8 bits),
“BFSR: Bus Fault Status Subregister” (0xE000ED29 - 8 bits), “UFSR: Usage Fault Status Subregister” (0xE000ED2A - 16
bits).
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11.9.1.1 Auxiliary Control Register
Name:
SCB_ACTLR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
12
11
10
9
DISOOFP
8
DISFPCA
4
3
2
1
0
DISFOLD
DISDEFWBUF
DISMCYCINT
–
23
22
21
20
–
15
14
13
–
7
6
5
–
The SCB_ACTLR register provides disable bits for the following processor functions:
IT folding
Write buffer use for accesses to the default memory map
Interruption of multi-cycle instructions.
By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally
require modification.
• DISOOFP: Disable Out Of Order Floating Point
Disables floating point instructions that complete out of order with respect to integer instructions.
• DISFPCA: Disable FPCA
Disables an automatic update of CONTROL.FPCA.
• DISFOLD: Disable Folding
When set to 1, disables the IT folding.
Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction.
This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must
avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding.
• DISDEFWBUF: Disable Default Write Buffer
When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise
but decreases the performance, as any store to memory must complete before the processor can execute the next
instruction.
This bit only affects write buffers implemented in the Cortex-M4 processor.
• DISMCYCINT: Disable Multiple Cycle Interruption
When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the interrupt
latency of the processor, as any LDM or STM must complete before the processor can stack the current state and enter the
interrupt handler.
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11.9.1.2 CPUID Base Register
Name:
SCB_CPUID
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
19
18
25
24
17
16
Implementer
23
22
21
20
Variant
15
14
Constant
13
12
11
10
9
8
3
2
1
0
PartNo
7
6
5
4
PartNo
Revision
The SCB_CPUID register contains the processor part number, version, and implementation information.
• Implementer: Implementer Code
0x41: ARM.
• Variant: Variant Number
It is the r value in the rnpn product revision identifier:
0x0: Revision 0.
• Constant
Reads as 0xF.
• PartNo: Part Number of the Processor
0xC24 = Cortex-M4.
• Revision: Revision Number
It is the p value in the rnpn product revision identifier:
0x0: Patch 0.
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11.9.1.3 Interrupt Control and State Register
Name:
SCB_ICSR
Access:
Read-write
Reset:
0x000000000
31
NMIPENDSET
30
23
–
22
ISRPENDING
15
7
29
28
PENDSVSET
21
20
14
13
VECTPENDING
12
6
4
–
5
27
PENDSVCLR
26
PENDSTSET
19
18
VECTPENDING
11
RETTOBASE
10
3
2
25
PENDSTCLR
24
–
17
16
9
8
VECTACTIVE
1
0
–
VECTACTIVE
The SCB_ICSR register provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and
clear-pending bits for the PendSV and SysTick exceptions.
It indicates:
The exception number of the exception being processed, and whether there are preempted active
exceptions,
The exception number of the highest priority pending exception, and whether any interrupts are pending.
• NMIPENDSET: NMI Set-pending
Write:
PendSV set-pending bit.
Write:
0: No effect.
1: Changes NMI exception state to pending.
Read:
0: NMI exception is not pending.
1: NMI exception is pending.
As NMI is the highest-priority exception, the processor normally enters the NMI exception handler as soon as it registers a
write of 1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if
the NMI signal is reasserted while the processor is executing that handler.
• PENDSVSET: PendSV Set-pending
Write:
0: No effect.
1: Changes PendSV exception state to pending.
Read:
0: PendSV exception is not pending.
1: PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
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• PENDSVCLR: PendSV Clear-pending
Write:
0: No effect.
1: Removes the pending state from the PendSV exception.
• PENDSTSET: SysTick Exception Set-pending
Write:
0: No effect.
1: Changes SysTick exception state to pending.
Read:
0: SysTick exception is not pending.
1: SysTick exception is pending.
• PENDSTCLR: SysTick Exception Clear-pending
Write:
0: No effect.
1: Removes the pending state from the SysTick exception.
This bit is Write-only. On a register read, its value is Unknown.
• ISRPENDING: Interrupt Pending Flag (Excluding NMI and Faults)
0: Interrupt not pending.
1: Interrupt pending.
• VECTPENDING: Exception Number of the Highest Priority Pending Enabled Exception
0: No pending exceptions.
Nonzero: The exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
• RETTOBASE: Preempted Active Exceptions Present or Not
0: There are preempted active exceptions to execute.
1: There are no active exceptions, or the currently-executing exception is the only active exception.
• VECTACTIVE: Active Exception Number Contained
0: Thread mode.
Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See “Interrupt
Program Status Register” .
Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, ClearPending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” .
Note: When the user writes to the SCB_ICSR register, the effect is unpredictable if:
- Writing 1 to the PENDSVSET bit and writing 1 to the PENDSVCLR bit
- Writing 1 to the PENDSTSET bit and writing 1 to the PENDSTCLR bit.
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11.9.1.4 Vector Table Offset Register
Name:
SCB_VTOR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
–
2
1
0
TBLOFF
23
22
21
20
TBLOFF
15
14
13
12
TBLOFF
7
TBLOFF
6
5
4
The SCB_VTOR register indicates the offset of the vector table base address from memory address 0x00000000.
• TBLOFF: Vector Table Base Offset
It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
Bit [29] determines whether the vector table is in the code or SRAM memory region:
0: Code.
1: SRAM.
It is sometimes called the TBLBASE bit.
Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the next
statement to give the information required for your implementation; the statement reminds the user of how to determine the
alignment requirement. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the
alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the alignment must be on a 64-word
boundary because the required table size is 37 words, and the next power of two is 64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
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11.9.1.5 Application Interrupt and Reset Control Register
Name:
SCB_AIRCR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
VECTKEYSTAT/VECTKEY
26
25
24
23
22
21
20
19
VECTKEYSTAT/VECTKEY
18
17
16
15
ENDIANNESS
14
13
9
PRIGROUP
8
7
6
12
11
10
4
3
2
–
5
–
1
VECTCLRACTI
SYSRESETREQ
VE
0
VECTRESET
The SCB_AIRCR register provides priority grouping control for the exception model, endian status for data accesses, and
reset control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores
the write.
• VECTKEYSTAT: Register Key
Read:
Reads as 0xFA05.
• VECTKEY: Register Key
Write:
Writes 0x5FA to VECTKEY, otherwise the write is ignored.
• ENDIANNESS: Data Endianness
0: Little-endian.
1: Big-endian.
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• PRIGROUP: Interrupt Priority Grouping
This field determines the split of group priority from subpriority. It shows the position of the binary point that splits the PRI_n
fields in the Interrupt Priority Registers into separate group priority and subpriority fields. The table below shows how the
PRIGROUP value controls this split:
Interrupt Priority Level Value, PRI_N[7:0]
PRIGROUP
Binary Point
0b000
(1)
Number of
Group Priority Bits
Subpriority Bits
Group Priorities
Subpriorities
bxxxxxxx.y
[7:1]
None
128
2
0b001
bxxxxxx.yy
[7:2]
[4:0]
64
4
0b010
bxxxxx.yyy
[7:3]
[4:0]
32
8
0b011
bxxxx.yyyy
[7:4]
[4:0]
16
16
0b100
bxxx.yyyyy
[7:5]
[4:0]
8
32
0b101
bxx.yyyyyy
[7:6]
[5:0]
4
64
0b110
bx.yyyyyyy
[7]
[6:0]
2
128
0b111
b.yyyyyyy
None
[7:0]
1
256
Note:
1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.
Determining preemption of an exception uses only the group priority field.
• SYSRESETREQ: System Reset Request
0: No system reset request.
1: Asserts a signal to the outer system that requests a reset.
This is intended to force a large system reset of all major components except for debug. This bit reads as 0.
• VECTCLRACTIVE
Reserved for Debug use. This bit reads as 0. When writing to the register, write 0 to this bit, otherwise the behavior is
unpredictable.
• VECTRESET
Reserved for Debug use. This bit reads as 0. When writing to the register, write 0 to this bit, otherwise the behavior is
unpredictable.
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11.9.1.6 System Control Register
Name:
SCB_SCR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
–
2
SLEEPDEEP
1
SLEEPONEXIT
0
–
–
23
22
21
20
–
15
14
13
12
–
7
6
–
5
4
SEVONPEND
• SEVONPEND: Send Event on Pending Bit
0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded.
1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
The processor also wakes up on execution of an SEV instruction or an external event.
• SLEEPDEEP: Sleep or Deep Sleep
Controls whether the processor uses sleep or deep sleep as its low power mode:
0: Sleep.
1: Deep sleep.
• SLEEPONEXIT: Sleep-on-exit
Indicates sleep-on-exit when returning from the Handler mode to the Thread mode:
0: Do not sleep when returning to Thread mode.
1: Enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
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11.9.1.7 Configuration and Control Register
Name:
SCB_CCR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
12
11
10
9
STKALIGN
8
BFHFNMIGN
4
3
2
DIV_0_TRP
UNALIGN_TRP
–
–
23
22
21
20
–
15
14
13
–
7
6
5
–
1
0
USERSETMPE NONBASETHR
ND
DENA
The SCB_CCR register controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults
escalated by FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the
access to the NVIC_STIR register by unprivileged software (see “Software Trigger Interrupt Register” ).
• STKALIGN: Stack Alignment
Indicates the stack alignment on exception entry:
0: 4-byte aligned.
1: 8-byte aligned.
On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the
exception, it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN: Bus Faults Ignored
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the
hard fault and FAULTMASK escalated handlers:
0: Data bus faults caused by load and store instructions cause a lock-up.
1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.
• DIV_0_TRP: Division by Zero Trap
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: Do not trap divide by 0.
1: Trap divide by 0.
When this bit is set to 0, a divide by zero returns a quotient of 0.
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• UNALIGN_TRP: Unaligned Access Trap
Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses.
1: Trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND
Enables unprivileged software access to the NVIC_STIR register, see “Software Trigger Interrupt Register” :
0: Disable.
1: Enable.
• NONEBASETHRDENA: Thread Mode Enable
Indicates how the processor enters Thread mode:
0: The processor can enter the Thread mode only when no exception is active.
1: The processor can enter the Thread mode from any level under the control of an EXC_RETURN value, see “Exception
Return” .
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11.9.1.8 System Handler Priority Registers
The SCB_SHPR1-SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. They are byte-accessible.
The system fault handlers and the priority field and register for each handler are:
Table 11-33.
System Fault Handler Priority Fields
Handler
Field
Memory management fault (MemManage)
PRI_4
Bus fault (BusFault)
PRI_5
Usage fault (UsageFault)
PRI_6
SVCall
PRI_11
PendSV
PRI_14
SysTick
PRI_15
Register Description
“System Handler Priority Register 1”
“System Handler Priority Register 2”
“System Handler Priority Register 3”
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and
ignore writes.
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11.9.1.9 System Handler Priority Register 1
Name:
SCB_SHPR1
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
–
23
22
21
20
PRI_6
15
14
13
12
PRI_5
7
6
5
4
PRI_4
• PRI_6: Priority
Priority of system handler 6, UsageFault.
• PRI_5: Priority
Priority of system handler 5, BusFault.
• PRI_4: Priority
Priority of system handler 4, MemManage.
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11.9.1.10 System Handler Priority Register 2
Name:
SCB_SHPR2
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PRI_11
23
22
21
20
–
15
14
13
12
–
7
6
5
4
–
• PRI_11: Priority
Priority of system handler 11, SVCall.
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11.9.1.11 System Handler Priority Register 3
Name:
SCB_SHPR3
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
PRI_15
23
22
21
20
PRI_14
15
14
13
12
–
7
6
5
4
–
• PRI_15: Priority
Priority of system handler 15, SysTick exception.
• PRI_14: Priority
Priority of system handler 14, PendSV.
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11.9.1.12 System Handler Control and State Register
Name:
SCB_SHCSR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
–
23
22
21
–
20
19
18
17
16
USGFAULTENA BUSFAULTENA MEMFAULTENA
15
14
13
12
11
SVCALLPENDE BUSFAULTPEN MEMFAULTPEN USGFAULTPEN
SYSTICKACT
D
DED
DED
DED
7
SVCALLAVCT
6
5
–
4
3
USGFAULTACT
10
9
8
PENDSVACT
–
MONITORACT
2
–
1
0
BUSFAULTACT MEMFAULTACT
The SHCSR register enables the system handlers, and indicates the pending status of the bus fault, memory management
fault, and SVC exceptions; it also indicates the active status of the system handlers.
• USGFAULTENA: Usage Fault Enable
0: Disables the exception.
1: Enables the exception.
• BUSFAULTENA: Bus Fault Enable
0: Disables the exception.
1: Enables the exception.
• MEMFAULTENA: Memory Management Fault Enable
0: Disables the exception.
1: Enables the exception.
• SVCALLPENDED: SVC Call Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• BUSFAULTPENDED: Bus Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
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• MEMFAULTPENDED: Memory Management Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• USGFAULTPENDED: Usage Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• SYSTICKACT: SysTick Exception Active
Read:
0: The exception is not active.
1: The exception is active.
Note: The user can write to these bits to change the active status of the exceptions.
- Caution: A software that changes the value of an active bit in this register without a correct adjustment to the stacked content
can cause the processor to generate a fault exception. Ensure that the software writing to this register retains and subsequently
restores the current active status.
- Caution: After enabling the system handlers, to change the value of a bit in this register, the user must use a read-modify-write
procedure to ensure that only the required bit is changed.
• PENDSVACT: PendSV Exception Active
0: The exception is not active.
1: The exception is active.
• MONITORACT: Debug Monitor Active
0: Debug monitor is not active.
1: Debug monitor is active.
• SVCALLACT: SVC Call Active
0: SVC call is not active.
1: SVC call is active.
• USGFAULTACT: Usage Fault Exception Active
0: Usage fault exception is not active.
1: Usage fault exception is active.
• BUSFAULTACT: Bus Fault Exception Active
0: Bus fault exception is not active.
1: Bus fault exception is active.
• MEMFAULTACT: Memory Management Fault Exception Active
0: Memory management fault exception is not active.
1: Memory management fault exception is active.
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If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault.
The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to
the active bits to perform a context switch that changes the current exception type.
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11.9.1.13 Configurable Fault Status Register
Name:
SCB_CFSR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
DIVBYZERO
24
UNALIGNED
21
20
19
NOCP
18
INVPC
17
INVSTATE
16
UNDEFINSTR
13
12
STKERR
11
UNSTKERR
10
IMPRECISERR
9
PRECISERR
8
IBUSERR
5
MLSPERR
4
MSTKERR
3
MUNSTKERR
2
–
1
DACCVIOL
0
IACCVIOL
–
23
22
–
15
BFRVALID
14
7
MMARVALID
6
–
–
• IACCVIOL: Instruction Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No instruction access violation fault.
1: The processor attempted an instruction fetch from a location that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not
written a fault address to the SCB_MMFAR register.
• DACCVIOL: Data Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No data access violation fault.
1: The processor attempted a load or store at a location that does not permit the operation.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded
the SCB_MMFAR register with the address of the attempted access.
• MUNSTKERR: Memory Manager Fault on Unstacking for a Return From Exception
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more access violations.
This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The processor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a
fault address to the SCB_MMFAR register.
• MSTKERR: Memory Manager Fault on Stacking for Exception Entry
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor
has not written a fault address to SCB_MMFAR register.
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• MLSPERR: MemManage during Lazy State Preservation
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No MemManage fault occurred during the floating-point lazy state preservation.
1: A MemManage fault occurred during the floating-point lazy state preservation.
• MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: The value in SCB_MMFAR is not a valid fault address.
1: SCB_MMFAR register holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose SCB_MMFAR
value has been overwritten.
• IBUSERR: Instruction Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No instruction bus error.
1: Instruction bus error.
The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it
attempts to issue the faulting instruction.
When the processor sets this bit to 1, it does not write a fault address to the BFAR register.
• PRECISERR: Precise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No precise data bus error.
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused
the fault.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR register.
• IMPRECISERR: Imprecise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No imprecise data bus error.
1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the
error.
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR register.
This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault
priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects
that both this bit and one of the precise fault status bits are set to 1.
• UNSTKERR: Bus Fault on Unstacking for a Return From Exception
This is part of “BFSR: Bus Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more bus faults.
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This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still
present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write
a fault address to the BFAR.
• STKERR: Bus Fault on Stacking for Exception Entry
This is part of “BFSR: Bus Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the SCB_BFAR register.
• BFARVALID: Bus Fault Address Register (BFAR) Valid flag
This is part of “BFSR: Bus Fault Status Subregister” .
0: The value in SCB_BFAR is not a valid fault address.
1: SCB_BFAR holds a valid fault address.
The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a
memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This
prevents problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten.
• UNDEFINSTR: Undefined Instruction Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No undefined instruction usage fault.
1: The processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
• INVSTATE: Invalid State Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No invalid state usage fault.
1: The processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal
use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
• INVPC: Invalid PC Load Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN:
0: No invalid PC load usage fault.
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC.
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• NOCP: No Coprocessor Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” . The processor does not support coprocessor instructions:
0: No usage fault caused by attempting to access a coprocessor.
1: The processor has attempted to access a coprocessor.
• UNALIGNED: Unaligned Access Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No unaligned access fault, or unaligned access trapping not enabled.
1: The processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR register to 1. See “Configuration
and Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
• DIVBYZERO: Divide by Zero Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No divide by zero fault, or divide by zero trapping not enabled.
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed
the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR register to 1. See
“Configuration and Control Register” .
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11.9.1.14 Configurable Fault Status Register (Byte Access)
Name:
SCB_CFSR (BYTE)
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
UFSR
23
22
21
20
UFSR
15
14
13
12
BFSR
7
6
5
4
MMFSR
• MMFSR: Memory Management Fault Status Subregister
The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section
11.9.1.13.
• BFSR: Bus Fault Status Subregister
The flags in the BFSR subregister indicate the cause of a bus access fault. See bitfield [14..8] description in Section
11.9.1.13.
• UFSR: Usage Fault Status Subregister
The flags in the UFSR subregister indicate the cause of a usage fault. See bitfield [31..15] description in Section 11.9.1.13.
Note: The UFSR bits are sticky. This means that as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing 1 to that bit, or by a reset.
The SCB_CFSR register indicates the cause of a memory management fault, bus fault, or usage fault. It is byte accessible.
The user can access the SCB_CFSR register or its subregisters as follows:
222
Access complete SCB_CFSR with a word access to 0xE000ED28
Access MMFSR with a byte access to 0xE000ED28
Access MMFSR and BFSR with a halfword access to 0xE000ED28
Access BFSR with a byte access to 0xE000ED29
Access UFSR with a halfword access to 0xE000ED2A.
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11.9.1.15 Hard Fault Status Register
Name:
SCB_HFSR
Access:
Read-write
Reset:
0x000000000
31
DEBUGEVT
30
FORCED
29
23
22
21
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
VECTTBL
0
–
–
20
–
15
14
13
12
–
7
6
5
4
–
The HFSR register gives information about events that activate the hard fault handler. This register is read, write to clear.
This means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
• DEBUGEVT: Reserved for Debug Use
When writing to the register, write 0 to this bit, otherwise the behavior is unpredictable.
• FORCED: Forced Hard Fault
It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either
because of priority or because it is disabled:
0: No forced hard fault.
1: Forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL: Bus Fault on a Vector Table
It indicates a bus fault on a vector table read during an exception processing:
0: No bus fault on vector table read.
1: Bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
Note: The HFSR bits are sticky. This means that, as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is
cleared to 0 only by writing 1 to that bit, or by a reset.
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11.9.1.16 MemManage Fault Address Register
Name:
SCB_MMFAR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDRESS
23
22
21
20
ADDRESS
15
14
13
12
ADDRESS
7
6
5
4
ADDRESS
The MMFAR register contains the address of the location that generated a memory management fault.
• ADDRESS
When the MMARVALID bit of the MMFSR subregister is set to 1, this field holds the address of the location that generated
the memory management fault.
Notes:
224
1. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction
can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size.
2. Flags in the MMFSR subregister indicate the cause of the fault, and whether the value in the SCB_MMFAR register is valid.
See “MMFSR: Memory Management Fault Status Subregister” .
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11.9.1.17 Bus Fault Address Register
Name:
SCB_BFAR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ADDRESS
23
22
21
20
ADDRESS
15
14
13
12
ADDRESS
7
6
5
4
ADDRESS
The BFAR register contains the address of the location that generated a bus fault.
• ADDRESS
When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the
bus fault.
Notes:
1. When an unaligned access faults, the address in the SCB_BFAR register is the one requested by the instruction, even if it is
not the address of the fault.
2. Flags in the BFSR indicate the cause of the fault, and whether the value in the SCB_BFAR register is valid. See “BFSR: Bus
Fault Status Subregister” .
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11.10 System Timer (SysTick)
The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps
to) the value in the SYST_RVR register on the next clock edge, then counts down on subsequent clocks.
When the processor is halted for debugging, the counter does not decrement.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick
counter stops.
Ensure that the software uses aligned word accesses to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the
SysTick counter is:
1. Program the reload value.
2. Clear the current value.
3.
Program the Control and Status register.
11.10.1 System Timer (SysTick) User Interface
Table 11-34.
System Timer (SYST) Register Mapping
Offset
Register
Name
Access
Reset
0xE000E010
SysTick Control and Status Register
SYST_CSR
Read-write
0x00000004
0xE000E014
SysTick Reload Value Register
SYST_RVR
Read-write
Unknown
0xE000E018
SysTick Current Value Register
SYST_CVR
Read-write
Unknown
0xE000E01C
SysTick Calibration Value Register
SYST_CALIB
Read-only
0xC0000000
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11.10.1.1 SysTick Control and Status
Name:
SYST_CSR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
COUNTFLAG
11
10
9
8
3
2
CLKSOURCE
1
TICKINT
0
ENABLE
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
The SysTick SYST_CSR register enables the SysTick features.
• COUNTFLAG: Count Flag
Returns 1 if the timer counted to 0 since the last time this was read.
• CLKSOURCE: Clock Source
Indicates the clock source:
0: External Clock.
1: Processor Clock.
• TICKINT
Enables a SysTick exception request:
0: Counting down to zero does not assert the SysTick exception request.
1: Counting down to zero asserts the SysTick exception request.
The software can use COUNTFLAG to determine if SysTick has ever counted to zero.
• ENABLE
Enables the counter:
0: Counter disabled.
1: Counter enabled.
When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR register and then counts down. On
reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then
loads the RELOAD value again, and begins counting.
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11.10.1.2 SysTick Reload Value Registers
Name:
SYST_RVR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
–
23
22
21
20
RELOAD
15
14
13
12
RELOAD
7
6
5
4
RELOAD
The SYST_RVR register specifies the start value to load into the SYST_CVR register.
• RELOAD
Value to load into the SYST_CVR register when the counter is enabled and when it reaches 0.
The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. A start value of 0 is possible, but has no
effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0.
The RELOAD value is calculated according to its use: For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD
to 99.
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11.10.1.3 SysTick Current Value Register
Name:
SYST_CVR
Access:
Read-write
Reset:
0x000000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
–
23
22
21
20
CURRENT
15
14
13
12
CURRENT
7
6
5
4
CURRENT
The SysTick SYST_CVR register contains the current value of the SysTick counter.
• CURRENT
Reads return the current value of the SysTick counter.
A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
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11.10.1.4 SysTick Calibration Value Register
Name:
SYST_CALIB
Access:
Read-write
Reset:
0x000000000
31
NOREF
30
SKEW
29
23
22
21
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
–
20
TENMS
15
14
13
12
TENMS
7
6
5
4
TENMS
The SysTick SYST_CSR register indicates the SysTick calibration properties.
• NOREF: No Reference Clock
It indicates whether the device provides a reference clock to the processor:
0: Reference clock provided.
1: No reference clock provided.
If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes.
• SKEW
It indicates whether the TENMS value is exact:
0: TENMS value is exact.
1: TENMS value is inexact, or not given.
An inexact TENMS value can affect the suitability of SysTick as a software real time clock.
• TENMS: Ten Milliseconds
The reload value for 10 ms (100 Hz) timing is subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
Read as 0x000030D4. The SysTick calibration value is fixed at 0x000030D4 (12500), which allows the generation of a time
base of 1 ms with SysTick clock at 12.5 MHz (100/8 = 12.5 MHz).
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11.11 Memory Protection Unit (MPU)
The MPU divides the memory map into a number of regions, and defines the location, size, access permissions,
and memory attributes of each region. It supports:
Independent attribute settings for each region
Overlapping regions
Export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines:
Eight separate memory regions, 0-7
A background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the highest
number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps
region 7.
The background region has the same memory access attributes as the default memory map, but is accessible
from privileged software only.
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the
same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory
management fault. This causes a fault exception, and might cause the termination of the process in an OS
environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be
executed. Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” ).
Table 11-35 shows the possible MPU region attributes. These include Share ability and cache behavior attributes
that are not relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” for
guidelines for programming such an implementation.
Table 11-35.
Memory Attributes Summary
Memory Type
Shareability
Other Attributes
Description
Strongly- ordered
-
-
All accesses to Strongly-ordered memory occur in program order. All
Strongly-ordered regions are assumed to be shared.
Shared
-
Memory-mapped peripherals that several processors share.
Non-shared
-
Memory-mapped peripherals that only a single processor uses.
Device
Shared
Normal memory that is shared between several processors.
Non-shared
Normal memory that only a single processor uses.
Normal
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11.11.1 MPU Access Permission Attributes
This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and
XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of
memory without the required permissions, then the MPU generates a permission fault.
The table below shows the encodings for the TEX, C, B, and S access permission bits.
Table 11-36.
TEX
TEX, C, B, and S Encoding
C
B
S
Memory Type
Shareability
Other Attributes
0
0
x (1)
Stronglyordered
Shareable
-
1
x (1)
Device
Shareable
-
Normal
Not
shareable
0
0
b000
1
Outer and inner write-through. No
write allocate.
Shareable
1
0
1
0
Normal
1
Shareable
0
Not
shareable
0
Normal
1
x
0
x (1)
1
Reserved encoding
-
Implementation defined
attributes.
-
0
1
Normal
1
1
b1B
B
1.
Not
shareable
x (1)
Device
1
x (1)
Reserved encoding
-
(1)
Reserved encoding
-
x
(1)
x
A
Normal
1
Note:
Outer and inner write-back. Write and
read allocate.
0
0
A
Not
shareable
Shareable
0
b010
Outer and inner write-back. No write
allocate.
Shareable
(1)
1
b001
Not
shareable
Nonshared Device.
Not
shareable
Shareable
The MPU ignores the value of this bit.
Table 11-37 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7.
Table 11-37.
232
Cache Policy for Memory Attribute Encoding
Encoding, AA or BB
Corresponding Cache Policy
00
Non-cacheable
01
Write back, write and read allocate
10
Write through, no write allocate
11
Write back, no write allocate
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Table 11-38 shows the AP encodings that define the access permissions for privileged and unprivileged software.
Table 11-38.
AP Encoding
AP[2:0]
Privileged
Permissions
Unprivileged
Permissions
Description
000
No access
No access
All accesses generate a permission fault
001
RW
No access
Access from privileged software only
010
RW
RO
Writes by unprivileged software generate a permission fault
011
RW
RW
Full access
100
Unpredictable
Unpredictable
Reserved
101
RO
No access
Reads by privileged software only
110
RO
RO
Read only, by privileged or unprivileged software
111
RO
RO
Read only, by privileged or unprivileged software
11.11.1.1 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management fault, see
“Exceptions and Interrupts” . The MMFSR indicates the cause of the fault. See “MMFSR: Memory Management
Fault Status Subregister” for more information.
11.11.1.2 Updating an MPU Region
To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASR registers. Each
register can be programed separately, or a multiple-word write can be used to program all of these registers.
MPU_RBAR and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM
instruction.
11.11.1.3 Updating an MPU Region Using Separate Words
Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR
STR R1, [R0, #0x0]
STR R4, [R0, #0x4]
STRH R2, [R0, #0x8]
STRH R3, [R0, #0xA]
;
;
;
;
;
0xE000ED98, MPU region number register
Region Number
Region Base Address
Region Size and Enable
Region Attribute
Disable a region before writing new region settings to the MPU, if the region being changed was previously
enabled. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR
; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0]
; Region Number
BIC R2, R2, #1
; Disable
STRH R2, [R0, #0x8]
; Region Size and Enable
STR R4, [R0, #0x4]
; Region Base Address
STRH R3, [R0, #0xA]
; Region Attribute
ORR R2, #1
; Enable
STRH R2, [R0, #0x8]
; Region Size and Enable
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The software must use memory barrier instructions:
Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might
be affected by the change in MPU settings
After the MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering an exception
handler, or is followed by an exception return, because the exception entry and exception return mechanisms
cause memory barrier behavior.
The software does not need any memory barrier instructions during an MPU setup, because it accesses the MPU
through the PPB, which is a Strongly-Ordered memory region.
For example, if the user wants all of the memory access behavior to take effect immediately after the programming
sequence, a DSB instruction and an ISB instruction must be used. A DSB is required after changing MPU settings,
such as at the end of a context switch. An ISB is required if the code that programs the MPU region or regions is
entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking
an exception, then an ISB is not required.
11.11.1.4 Updating an MPU Region Using Multi-word Writes
The user can program directly using multi-word writes, depending on how the information is divided. Consider the
following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region Number, address, attribute, size and enable
This can be done in two words for pre-packed information. This means that the MPU_RBAR contains the required
region number and had the VALID bit set to 1. See “MPU Region Base Address Register” . Use this when the data
is statically packed, for example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPU_RBAR
; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and
; region number combined with VALID (bit 4) set to 1
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPU_RBAR
; 0xE000ED9C, MPU Region Base register
STM R0, {R1-R2}
; Region base address, region number and VALID bit,
; and Region Attribute, Size and Enable
11.11.1.5 Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD
field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” . The least
significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling
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a subregion means another region overlapping the disabled range matches instead. If no other enabled region
overlaps the disabled subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be
set to 0x00, otherwise the MPU behavior is unpredictable.
11.11.1.6 Example of SRD Use
Two regions with the same base address overlap. Region 1 is 128 KB, and region 2 is 512 KB. To ensure the
attributes from region 1 apply to the first 128 KB region, set the SRD field for region 2 to b00000011 to disable the
first two subregions, as in Figure 11-14 below:
Figure 11-14. SRD Use
Region 2, with
subregions
Region 1
Base address of both regions
Offset from
base address
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Disabled subregion
64KB
Disabled subregion
0
11.11.1.7 MPU Design Hints And Tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt
handlers might access.
Ensure the software uses aligned accesses of the correct size to access MPU registers:
Except for the MPU_RASR register, it must use aligned word accesses
For the MPU_RASR register, it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent
any previous region settings from affecting the new MPU setup.
MPU Configuration for a Microcontroller
Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU
as follows:
Table 11-39.
Memory Region Attributes for a Microcontroller
Memory Region
TEX
C
B
S
Memory Type and Attributes
Flash memory
b000
1
0
0
Normal memory, non-shareable, write-through
Internal SRAM
b000
1
0
1
Normal memory, shareable, write-through
External SRAM
b000
1
1
1
Normal memory, shareable, write-back, write-allocate
Peripherals
b000
0
1
1
Device memory, shareable
In most microcontroller implementations, the shareability and cache policy attributes do not affect the system
behavior. However, using these settings for the MPU regions can make the application code more portable. The
values given are for typical situations. In special systems, such as multiprocessor designs or designs with a
separate DMA engine, the shareability attribute might be important. In these cases, refer to the recommendations
of the memory device manufacturer.
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11.11.2 Memory Protection Unit (MPU) User Interface
Table 11-40.
Memory Protection Unit (MPU) Register Mapping
Offset
Register
Name
Access
Reset
0xE000ED90
MPU Type Register
MPU_TYPE
Read-only
0x00000800
0xE000ED94
MPU Control Register
MPU_CTRL
Read-write
0x00000000
0xE000ED98
MPU Region Number Register
MPU_RNR
Read-write
0x00000000
0xE000ED9C
MPU Region Base Address Register
MPU_RBAR
Read-write
0x00000000
0xE000EDA0
MPU Region Attribute and Size Register
MPU_RASR
Read-write
0x00000000
0xE000EDA4
Alias of RBAR, see MPU Region Base Address Register
MPU_RBAR_A1
Read-write
0x00000000
0xE000EDA8
Alias of RASR, see MPU Region Attribute and Size Register
MPU_RASR_A1
Read-write
0x00000000
0xE000EDAC
Alias of RBAR, see MPU Region Base Address Register
MPU_RBAR_A2
Read-write
0x00000000
0xE000EDB0
Alias of RASR, see MPU Region Attribute and Size Register
MPU_RASR_A2
Read-write
0x00000000
0xE000EDB4
Alias of RBAR, see MPU Region Base Address Register
MPU_RBAR_A3
Read-write
0x00000000
0xE000EDB8
Alias of RASR, see MPU Region Attribute and Size Register
MPU_RASR_A3
Read-write
0x00000000
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11.11.2.1 MPU Type Register
Name:
MPU_TYPE
Access:
Read-write
Reset:
0x00000800
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
SEPARATE
–
23
22
21
20
IREGION
15
14
13
12
DREGION
7
6
5
4
–
The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports.
• IREGION: Instruction Region
Indicates the number of supported MPU instruction regions.
Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.
• DREGION: Data Region
Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
• SEPARATE: Separate Instruction
Indicates support for unified or separate instruction and date memory maps:
0: Unified.
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11.11.2.2 MPU Control Register
Name:
MPU_CTRL
Access:
Read-write
Reset:
0x00000800
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
PRIVDEFENA
1
HFNMIENA
0
ENABLE
–
23
22
21
20
–
15
14
13
12
–
7
6
5
–
4
The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of
the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
• PRIVDEFENA: Privileged Default Memory Map Enabled
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by
any enabled region causes a fault.
1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software
accesses.
When enabled, the background region acts as a region number -1. Any region that is defined and enabled has priority over
this default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA: Hard Fault and NMI Enabled
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable.
• ENABLE
Enables the MPU:
0: MPU disabled.
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the default memory map is as described in “Memory Model” . Any access by privileged
software that does not address an enabled memory region behaves as defined by the default memory map.
• Any access by unprivileged software that does not address an enabled memory region causes a memory management
fault.
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XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless
the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the
MPU is not implemented. The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are
accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with
priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is
enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
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11.11.2.3 MPU Region Number Register
Name:
MPU_RNR
Access:
Read-write
Reset:
0x00000800
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
–
23
22
21
20
–
15
14
13
12
–
7
6
5
4
REGION
The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers.
• REGION
Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
Normally, the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR. However, the region number can be changed by writing to the MPU_RBAR with the VALID bit set to 1; see “MPU Region Base
Address Register” . This write updates the value of the REGION field.
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11.11.2.4 MPU Region Base Address Register
Name:
MPU_RBAR
Access:
Read-write
Reset:
0x00000000
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
N
3
2
1
0
ADDR
23
22
21
20
ADDR
15
14
13
12
ADDR
N-1
6
–
5
4
VALID
REGION
Note: If the region size is 32B, the ADDR field is bits [31:5] and there is no Reserved field.
The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified
by the SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies
the complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB,
for example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and
ignores the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for
the region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
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11.11.2.5 MPU Region Attribute and Size Register
Name:
MPU_RASR
Access:
Read-write
Reset:
0x00000000
31
23
30
–
29
28
XN
27
–
26
25
AP
24
22
21
20
TEX
19
18
S
17
C
16
B
14
13
12
11
10
9
8
3
SIZE
2
1
0
ENABLE
–
15
SRD
7
6
5
4
–
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and
enables that region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
The most significant halfword holds the region attributes.
The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 11-38.
• TEX, C, B: Memory Access Attributes
See Table 11-36.
• S: Shareable
See Table 11-36.
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding sub-region is enabled.
1: Corresponding sub-region is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD
field as 0x00.
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• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE
values, with the corresponding region size and value of N in the MPU_RBAR.
SIZE Value
Region Size
Value of N (1)
Note
b00100 (4)
32 B
5
Minimum permitted size
b01001 (9)
1 KB
10
-
b10011 (19)
1 MB
20
-
b11101 (29)
1 GB
30
-
b11111 (31)
4 GB
b01100
Maximum possible size
Note:
1. In the MPU_RBAR, see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes” .
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11.12 Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort
A mechanism that indicates to a processor that the value associated with a memory access is invalid.
An abort can be caused by the external or internal memory system as a result of attempting to access
invalid instruction or data memory.
Aligned
A data item stored at an address that is divisible by the number of bytes that defines the data size is
said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two
respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are
divisible by four and two respectively.
Banked register
Base register
A register that has multiple physical copies, where the state of the processor determines which copy is
used. The Stack Pointer, SP (R13) is a banked register.
In instruction descriptions, a register specified by a load or store instruction that is used to hold the
base value for the instruction’s address calculation. Depending on the instruction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the address that is
sent to memory.
See also “Index register”
Big-endian (BE)
Byte ordering scheme in which bytes of decreasing significance in a data word are stored at
increasing addresses in memory.
See also “Byte-invariant” , “Endianness” , “Little-endian (LE)” .
Big-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the most significant byte within the halfword at that address.
See also “Little-endian memory” .
Breakpoint
A breakpoint is a mechanism provided by debuggers to identify an instruction at which program
execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register
contents, memory locations, variable values at fixed points in the program execution to test that the
program is operating correctly. Breakpoints are removed after the program is successfully tested.
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Byte-invariant
In a byte-invariant system, the address of each byte of memory remains unchanged when switching
between little-endian and big-endian operation. When a data item larger than a byte is loaded from or
stored to memory, the bytes making up that data item are arranged into the correct order depending
on the endianness of the memory access.
An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses.
It expects multi-word accesses to be word-aligned.
Condition field
A four-bit field in an instruction that specifies a condition under which the instruction can execute.
Conditional execution
If the condition code flags indicate that the corresponding condition is true when the instruction starts
executing, it executes normally. Otherwise, the instruction does nothing.
Context
The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the physical address range that it can access in memory and the
associated memory access permissions.
Coprocessor
A processor that supplements the main processor. Cortex-M4 does not support any coprocessors.
Debugger
A debugging system that includes a program, used to detect, locate, and correct software faults,
together with custom hardware that supports software debugging.
Direct Memory Access
(DMA)
An operation that accesses main memory directly, without the processor performing any accesses to
the data concerned.
Doubleword
A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.
Doubleword-aligned
A data item having a memory address that is divisible by eight.
Endianness
Byte ordering. The scheme that determines the order that successive bytes of a data word are stored
in memory. An aspect of the system’s memory mapping.
See also “Little-endian (LE)” and “Big-endian (BE)”
Exception
An event that interrupts program execution. When an exception occurs, the processor suspends the
normal program flow and starts execution at the address indicated by the corresponding exception
vector. The indicated address contains the first instruction of the handler for the exception.
An exception can be an interrupt request, a fault, or a software-generated system exception. Faults
include attempting an invalid memory access, attempting to execute an instruction in an invalid
processor state, and attempting to execute an undefined instruction.
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Exception service routine
See “Interrupt handler” .
Exception vector
See “Interrupt vector” .
Flat address mapping
A system of organizing memory in which each physical address in the memory space is the same as
the corresponding virtual address.
Halfword
A 16-bit data item.
Illegal instruction
An instruction that is architecturally Undefined.
Implementation-defined
The behavior is not architecturally defined, but is defined and documented by individual
implementations.
Implementation-specific
The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the option
chosen does not affect software compatibility.
Index register
In some load and store instruction descriptions, the value of this register is used as an offset to be
added to or subtracted from the base register value to form the address that is sent to memory. Some
addressing modes optionally enable the index register value to be shifted prior to the addition or
subtraction.
See also “Base register” .
Instruction cycle count
The number of cycles that an instruction occupies the Execute stage of the pipeline.
Interrupt handler
A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector
One of a number of fixed addresses in low memory, or in high memory if high vectors are configured,
that contains the first instruction of the corresponding interrupt handler.
Little-endian (LE)
Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing
addresses in memory.
See also “Big-endian (BE)” , “Byte-invariant” , “Endianness” .
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Little-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
See also “Big-endian memory” .
Load/store architecture
A processor architecture where data-processing operations only operate on register contents, not
directly on memory contents.
Memory Protection Unit
(MPU)
Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
Prefetching
In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before
the preceding instructions have finished executing. Prefetching an instruction does not mean that the
instruction has to be executed.
Preserved
Preserved by writing the same value back that has been previously read from the same field on the
same processor.
Read
Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb
instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Region
A partition of memory space.
Reserved
A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These fields
are reserved for use in future extensions of the architecture or are implementation-specific. All
reserved bits not used by the implementation must be written as 0 and read as 0.
Thread-safe
In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing
shared resources, to ensure correct operation without the risk of shared access conflicts.
Thumb instruction
One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be
halfword-aligned.
Unaligned
A data item stored at an address that is not divisible by the number of bytes that defines the data size
is said to be unaligned. For example, a word stored at an address that is not divisible by four.
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Undefined
Indicates an instruction that generates an Undefined instruction exception.
Unpredictable
One cannot rely on the behavior. Unpredictable behavior must not represent security holes.
Unpredictable behavior must not halt or hang the processor, or any parts of the system.
Warm reset
Also known as a core reset. Initializes the majority of the processor excluding the debug controller and
debug logic. This type of reset is useful if debugging features of a processor.
Word
A 32-bit data item.
Write
Writes are defined as operations that have the semantics of a store. Writes include the Thumb
instructions STM, STR, STRH, STRB, and PUSH.
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12.
Debug and Test Features
12.1
Description
The SAM4N Series microcontrollers feature a number of complementary debug and test capabilities. The Serial
Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug Port (JTAGDP) is used for standard debugging functions, such as downloading code and single-stepping through programs. It
also embeds a serial wire trace.
12.2
Embedded Characteristics
Debug access to all memories and registers in the system, including Cortex-M4 register bank when the core
is running, halted, or held in reset
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
IEEE1149.1 JTAG Boundary-scan on all digital pins
Figure 12-1.
Debug and Test Block Diagram
TMS
TCK/SWCLK
TDI
Boundary
TAP
JTAGSEL
SWJ-DP
TDO/TRACESWO
Reset
and
Test
POR
TST
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12.3
Application Examples
12.3.1 Debug Environment
Figure 12-2 shows a complete debug environment example. The SWJ-DP interface is used for standard
debugging functions, such as downloading code and single-stepping through the program, and viewing core and
peripheral registers.
Figure 12-2.
Application Debug Environment Example
Host Debugger
PC
SWJ-DP
Emulator/Probe
SWJ-DP
Connector
SAM4
SAM4-based Application Board
12.3.2 Test Environment
Figure 12-3 shows a test environment example (JTAG boundary scan). Test vectors are sent and interpreted by
the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These
devices can be connected to form a single scan chain.
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Figure 12-3.
Application Test Environment Example
Test Adaptor
Tester
JTAG
Probe
JTAG
Connector
Chip n
SAM4
Chip 2
Chip 1
SAM4-based Application Board In Test
12.4
Debug and Test Pin Description
Table 12-1.
Debug and Test Signal List
Signal Name
Function
Type
Active Level
Input/Output
Low
Reset/Test
NRST
Microcontroller Reset
TST
Test Select
Input
SWD/JTAG
TCK/SWCLK
Test Clock/Serial Wire Clock
Input
TDI
Test Data In
Input
TDO/TRACESWO
Test Data Out/Trace Asynchronous Data Out
TMS/SWDIO
Test Mode Select/Serial Wire Input/Output
Input
JTAGSEL
JTAG Selection
Input
Note:
1.
Output
(1)
High
TDO pin is set in input mode when the Cortex-M4 Core is not in debug mode. Thus the internal pull-up
corresponding to this PIO line must be enabled to avoid current consumption due to floating input.
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12.5
Functional Description
12.5.1 Test Pin
One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during powerup, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST
pin integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal
operation. Note that when setting the TST pin to low or high level at power up, it must remain in the same state
during the duration of the whole operation.
12.5.2 Debug Architecture
Figure 12-4 shows the Debug Architecture used in the SAM4. The Cortex-M4 embeds five functional units for
debug:
SWJ-DP (Serial Wire/JTAG Debug Port)
FPB (Flash Patch Breakpoint
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP emulators/probes
and debugging tool vendors for Cortex M4-based microcontrollers. For further details on SWJ-DP see the Cortex
M4 technical reference manual.
Figure 12-4.
Debug Architecture
DWT
4 watchpoints
FPB
SWJ-DP
PC sampler
6 breakpoints
data address sampler
SWD/JTAG
data sampler
ITM
software trace
32 channels
interrupt trace
time stamping
CPU statistics
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SWO trace
TPIU
12.5.3 Serial Wire/JTAG Debug Port (SWJ-DP)
The Cortex-M4 embeds a SWJ-DP debug port which is the standard CoreSight™ debug port. It combines Serial
Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG Debug Port(JTAG-DP), 5 pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial Wire Debug Port, it
must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and
enables SW-DP.
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE
output (TRACESWO) is multiplexed with TDO. The asynchronous trace can only be used with SW-DP, not JTAGDP.
Table 12-2.
SWJ-DP Pin List
Pin Name
JTAG Port
Serial Wire Debug Port
TMS/SWDIO
TMS
SWDIO
TCK/SWCLK
TCK
SWCLK
TDI
TDI
–
TDO/TRACESWO
TDO
TRACESWO (optional: trace)
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP
and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.
12.5.3.1 SW-DP and JTAG-DP Selection Mechanism
Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by
default after reset.
Switch from JTAG-DP to SW-DP. The sequence is:
̶
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
̶
Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
̶
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Switch from SWD to JTAG. The sequence is:
̶
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
̶
Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
̶
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
12.5.4 FPB (Flash Patch Breakpoint)
The FPB:
Implements hardware breakpoints.
Patches code and data from code space to system space.
The FPB unit contains:
Two literal comparators for matching against literal loads from code space, and remapping to a
corresponding area in system space.
Six instruction comparators for matching against instruction fetches from code space and remapping to a
corresponding area in system space.
Alternatively, comparators can also be configured to generate a breakpoint instruction to the processor core
on a match.
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12.5.5 DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to generate the following:
PC sampling packets at set intervals
PC or data watchpoint packets
Watchpoint event to halt core
The DWT contains counters for the items that follow:
Clock cycle (CYCCNT)
Folded instructions
Load Store Unit (LSU) operations
Sleep cycles
CPI (all instruction cycles except for the first cycle)
Interrupt overhead
12.5.6 ITM (Instrumentation Trace Macrocell)
The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS)
and application events, and emits diagnostic system information. The ITM emits trace information as packets
which can be generated by three different sources with several priority levels:
Software trace: Software can write directly to ITM stimulus registers. This can be done using the printf
function. For more information, refer to Section 12.5.6.1 “How to Configure the ITM”.
Hardware trace: The ITM emits packets generated by the DWT.
Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate
the timestamp.
12.5.6.1 How to Configure the ITM
The following example describes how to output trace data in asynchronous trace mode.
Configure the TPIU for asynchronous trace mode (refer to Section 12.5.6.3 “How to Configure the TPIU”).
Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register
(address: 0xE0000FB0).
Write 0x00010015 into the Trace Control Register:
̶
Enable ITM.
̶
Enable synchronization packets.
̶
Enable SWO behavior.
̶
Fix the ATB ID to 1.
Write 0x1 into the Trace Enable Register:
̶
Enable the stimulus port 0.
Write 0x1 into the Trace Privilege Register:
̶
Write into the Stimulus Port 0 Register: TPIU (Trace Port Interface Unit).
̶
̶
254
Stimulus port 0 only accessed in privileged mode (clearing a bit in this register will result in the
corresponding stimulus port being accessible in user mode).
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
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12.5.6.2 Asynchronous Mode
The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The
TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous
trace mode is only available when the serial wire debug mode is selected since TDO signal is used in JTAG debug
mode.
Two encoding formats are available for the single pin output:
Manchester encoded stream. This is the reset value.
NRZ-based UART byte structure
12.5.6.3 How to Configure the TPIU
This example only concerns the asynchronous trace mode.
Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of
trace and debug blocks.
Write 0x2 into the Selected Pin Protocol Register.
̶
Select the Serial Wire Output – NRZ.
Write 0x100 into the Formatter and Flush Control Register.
Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the
asynchronous output (this can be done automatically by the debugging tool).
12.5.7 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up
and must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS
functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID
that identifies the processor. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset
must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file to set up the
test is provided on www.atmel.com.
12.5.7.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains a number of bits which corresponds to active pins and associated
control signals.
Each SAM4 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be
forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects
the direction of the pad.
For more information, please refer to BSDL files available for the SAM4 Series.
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12.5.8 ID Code Register
Access: Read-only
31
30
29
28
27
21
20
19
PART NUMBER
VERSION
23
22
15
14
13
PART NUMBER
7
6
5
12
11
4
3
MANUFACTURER IDENTITY
26
25
PART NUMBER
24
18
16
17
10
9
MANUFACTURER IDENTITY
2
1
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
Chip Name
Chip ID
SAM4N
0x05B2E
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1
Set to 0x1.
Chip Name
SAM4N
256
JTAG ID Code
0x05B3_603F
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0
1
13.
Reset Controller (RSTC)
13.1
Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any
external components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and
processor resets.
13.2
Embedded Characteristics
Manages all Resets of the System, Including
̶
Processor Reset
̶
Peripheral Set Reset
Based on Embedded Power-on Cell
Reset Source Status
13.3
External Devices through the NRST Pin
̶
̶
Status of the Last Reset
̶
Either Software Reset, User Reset, Watchdog Reset
External Reset Signal Shaping
Block Diagram
Figure 13-1.
Reset Controller Block Diagram
Reset Controller
core_backup_reset
rstc_irq
vddcore_nreset
user_reset
NRST
nrst_out
NRST
Manager
Reset
State
Manager
proc_nreset
periph_nreset
exter_nreset
WDRPROC
wd_fault
SLCK
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13.4
Functional Description
13.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and
generates the following reset signals:
proc_nreset: Processor reset line. It also resets the Watchdog Timer
periph_nreset: Affects the whole set of embedded peripherals
nrst_out: Drives the NRST pin
These reset signals are asserted by the Reset Controller, either on external events or on software action. The
Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an
assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device
resets.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered
with VDDIO, so that its configuration is saved as long as VDDIO is on.
13.4.2 NRST Manager
After power-up, NRST is an output during the ERSTL time period defined in the RSTC_MR. When ERSTL has
elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external
signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State
Manager. Figure 13-2 shows the block diagram of the NRST Manager.
Figure 13-2.
NRST Manager
RSTC_MR
URSTIEN
RSTC_SR
URSTS
NRSTL
rstc_irq
RSTC_MR
URSTEN
Other
interrupt
sources
user_reset
NRST
RSTC_MR
ERSTL
nrst_out
External Reset Timer
exter_nreset
13.4.2.1 NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is
reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs.
Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin
NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the
bit URSTIEN in RSTC_MR must be written at 1.
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13.4.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion
duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate
duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the system power-up
reset for devices requiring a longer startup time than the Slow Clock Oscillator.
13.4.3 Brownout Manager
The Brownout manager is embedded within the Supply Controller, please refer to the product Supply Controller
section for a detailed description.
13.4.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports
the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is
performed when the processor reset is released.
13.4.4.1 General Reset
A general reset occurs when a Power-on-reset is detected, a Brownout or a Voltage regulation loss is detected by
the Supply controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs.
All the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR
is reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL defaults at value 0x0.
Figure 13-3 shows how the General Reset affects the reset signals.
Figure 13-3.
General Reset State
SLCK
Any
Freq.
MCK
backup_nreset
Processor Startup
= 2 cycles
proc_nreset
RSTTYP
XXX
0x0 = General Reset
XXX
periph_nreset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
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13.4.4.2 Backup Reset
A Backup reset occurs when the chip returns from Backup Mode. The core_backup_reset signal is asserted by the
Supply Controller when a Backup reset occurs.
The field RSTTYP in RSTC_SR is updated to report a Backup Reset.
13.4.4.3 User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral
Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup.
The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with
the value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock
cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH
because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.
Figure 13-4.
User Reset State
SLCK
MCK
Any
Freq.
NRST
Resynch.
2 cycles
Resynch.
2 cycles
Processor Startup
= 2 cycles
proc_nreset
RSTTYP
Any
XXX
periph_nreset
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
260
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0x4 = User Reset
13.4.4.4 Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These commands are
performed by writing the Control Register (RSTC_CR) with the following bits at 1:
PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer
PERRST: Writing PERRST at 1 resets all the embedded peripherals including the memory system, and, in
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously).
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the
Mode Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the
Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the
Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be
performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
Figure 13-5.
Software Reset
SLCK
MCK
Any
Freq.
Write RSTC_CR
Resynch. Processor Startup
1 cycle
= 2 cycles
proc_nreset
if PROCRST=1
RSTTYP
Any
XXX
0x3 = Software Reset
periph_nreset
if PERRST=1
NRST
(nrst_out)
if EXTRST=1
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
SRCMP in RSTC_SR
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13.4.4.5 Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:
If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also
asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST
does not result in a User Reset state.
If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by
default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
Figure 13-6.
Watchdog Reset
SLCK
MCK
Any
Freq.
wd_fault
Processor Startup
= 2 cycles
proc_nreset
RSTTYP
Any
XXX
0x2 = Watchdog Reset
periph_nreset
Only if
WDRPROC = 0
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
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13.4.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in
descending order:
General Reset
Backup Reset
Watchdog Reset
Software Reset
User Reset
Particular cases are listed below:
When in User Reset:
̶
̶
A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
A software reset is impossible, since the processor reset is being activated.
When in Software Reset:
̶
A watchdog event has priority over the current state.
̶
The NRST has no effect.
When in Watchdog Reset:
̶
The processor reset is active and so a Software Reset cannot be programmed.
̶
A User Reset cannot be entered.
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13.4.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software
reset should be performed until the end of the current one. This bit is automatically cleared at the end of the
current software reset.
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK
rising edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This
transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-7). If the User Reset is
disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the
URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the
interrupt.
Figure 13-7.
Reset Controller Status and Interrupt
MCK
read
RSTC_SR
Peripheral Access
2 cycle
resynchronization
NRST
NRSTL
URSTS
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
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2 cycle
resynchronization
13.5
Reset Controller (RSTC) User Interface
Table 13-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Control Register
RSTC_CR
Write-only
-
0x04
Status Register
RSTC_SR
Read-only
0x0000_0000
0x08
Mode Register
RSTC_MR
Read-write
0x0000 0001
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13.5.1 Reset Controller Control Register
Name:
RSTC_CR
Address:
0x400E1400
Access:
Write-only
31
30
29
28
27
26
25
24
KEY
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
EXTRST
2
PERRST
1
–
0
PROCRST
• PROCRST: Processor Reset
0 = No effect.
1 = If KEY is correct, resets the processor.
• PERRST: Peripheral Reset
0 = No effect.
1 = If KEY is correct, resets the peripherals.
• EXTRST: External Reset
0 = No effect.
1 = If KEY is correct, asserts the NRST pin and resets the processor and the peripherals.
• KEY: System Reset Key
266
Value
Name
Description
0xA5
PASSWD
Writing any other value in this field aborts the write operation.
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13.5.2 Reset Controller Status Register
Name:
RSTC_SR
Address:
0x400E1404
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
SRCMP
16
NRSTL
15
–
14
–
13
–
12
–
11
–
10
9
RSTTYP
8
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
URSTS
• URSTS: User Reset Status
0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Value
Name
Description
0
General Reset
First power-up Reset
1
Backup Reset
Return from Backup Mode
2
Watchdog Reset
Watchdog fault occurred
3
Software Reset
Processor reset required by the software
4
User Reset
NRST pin detected low
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.
1 = A software reset command is being performed by the reset controller. The reset controller is busy.
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13.5.3 Reset Controller Mode Register
Name:
RSTC_MR
Address:
0x400E1408
Access:
Read-write
31
30
29
28
27
26
25
24
17
–
16
–
9
8
1
–
0
URSTEN
KEY
23
–
22
–
21
–
20
–
19
–
18
–
15
–
14
–
13
–
12
–
11
10
7
–
6
–
5
4
URSTIEN
3
–
ERSTL
2
–
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles.
This allows assertion duration to be programmed between 60 µs and 2 seconds.
• KEY: Write Access Password
268
Value
Name
0xA5
PASSWD
Description
Writing any other value in this field aborts the write operation.
Always reads as 0.
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14.
Real-time Timer (RTT)
14.1
Description
The Real-time Timer is built around a 32-bit counter used to count roll-over events of the programmable 16-bit
prescaler which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic
interrupt and/or triggers an alarm on a programmed value.
It can be configured to be driven by the 1 Hz signal generated by the RTC, thus taking advantage of a calibrated 1
Hz clock.
The slow clock source can be fully disabled to reduce power consumption when RTT is not required.
14.2
14.3
Embedded Characteristics
32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1 Hz clock
16-bit Configurable Prescaler
Interrupt on Alarm
Block Diagram
Figure 14-1.
RTT_MR
RTTDIS
Real-time Timer
RTT_MR
RTT_MR
RTTRST
RTPRES
RTT_MR
reload
16-bit
Divider
SLCK
RTTINCIEN
set
0
RTT_MR
RTC 1Hz
RTTRST
RTT_MR
RTC1HZ
1
RTTINC
RTT_SR
1
reset
0
rtt_int
0
32-bit
Counter
read
RTT_SR
RTT_MR
ALMIEN
RTT_VR
reset
CRTV
RTT_SR
ALMS
set
rtt_alarm
=
RTT_AR
ALMV
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14.4
Functional Description
The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock
divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time
Mode Register (RTT_MR).
Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow
Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then
roll over to 0.
The real-time 32-bit counter can also be supplied by the RTC 1 Hz clock. This mode is interesting when the RTC
1Hz is calibrated (CORRECTION field of RTC_MR register differs from 0) in order to guaranty the synchronism
between RTC and RTT counters.
Setting the RTC 1HZ clock to 1 in RTT_MR register allows to drive the 32-bit RTT counter with the RTC 1Hz clock.
In this mode, RTPRES field has no effect on 32-bit counter but RTTINC is still triggered by RTPRES.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is
achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status
events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to
trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several
executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the
status register is clear.
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As
this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the
same value to improve accuracy of the returned value.
The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR register) when writing a new ALMV
value in Real-time Alarm Register.
The bit RTTINC in RTT_SR is set each time there is a prescaler roll-over, so each time the Real-time Timer
counter is incremented if RTC1HZ=0 else if RTC1HZ=1 the RTTINC bit can be triggered according to RTPRES
value, in a fully independent way from the 32-bit counter increment. This bit can be used to start a periodic
interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to
32.768 Hz.
The RTTINCIEN field must be cleared prior to write a new RTPRES value in RTT_MR register.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed
value. This also resets the 32-bit counter.
When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this
module. This can be achieved by setting the RTTDIS field to 1 in RTT_MR register.
270
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Figure 14-2.
RTT Counting
APB cycle
APB cycle
SCLK
RTPRES - 1
Prescaler
0
RTT
0
...
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR)
ALMS (RTT_SR)
APB Interface
read RTT_SR
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14.5
Real-time Timer (RTT) User Interface
Table 14-1.
Register Mapping
Offset
Register
Name
Access
Reset
0x00
Mode Register
RTT_MR
Read-write
0x0000_8000
0x04
Alarm Register
RTT_AR
Read-write
0xFFFF_FFFF
0x08
Value Register
RTT_VR
Read-only
0x0000_0000
0x0C
Status Register
RTT_SR
Read-only
0x0000_0000
272
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14.5.1 Real-time Timer Mode Register
Name:
RTT_MR
Address:
0x400E1430
Access:
Read-write
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
RTC1HZ
23
–
22
–
21
–
20
RTTDIS
19
–
18
RTTRST
17
RTTINCIEN
16
ALMIEN
15
14
13
12
11
10
9
8
3
2
1
0
RTPRES
7
6
5
4
RTPRES
• RTPRES: Real-time Timer Prescaler Value
Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows:
RTPRES = 0: The prescaler period is equal to 216 * SCLK period.
RTPRES ≠ 0: The prescaler period is equal to RTPRES * SCLK period.
Note: The RTTINCIEN field must be cleared prior to write a new RTPRES value.
• ALMIEN: Alarm Interrupt Enable
0 = The bit ALMS in RTT_SR has no effect on interrupt.
1 = The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0 = The bit RTTINC in RTT_SR has no effect on interrupt.
1 = The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart
0 = No effect.
1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
• RTTDIS: Real-time Timer Disable
0 = The real-time timer is enabled.
1 = The real-time timer is disabled (no dynamic power consumption).
• RTC1HZ: Real-Time Clock 1Hz Clock Selection
0 = The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events.
1 = The RTT 32-bit counter is driven by the RTC 1 Hz clock.
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14.5.2 Real-time Timer Alarm Register
Name:
RTT_AR
Address:
0x400E1434
Access:
Read-write
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
ALMV
23
22
21
20
ALMV
15
14
13
12
ALMV
7
6
5
4
ALMV
• ALMV: Alarm Value
Defines the alarm value (ALMV+1) compared with the Real-time Timer.
Note: The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR register) when writing a new ALMV
value.
274
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14.5.3 Real-time Timer Value Register
Name:
RTT_VR
Address:
0x400E1438
Access:
Read-only
31
30
29
28
27
26
25
24
19
18
17
16
11
10
9
8
3
2
1
0
CRTV
23
22
21
20
CRTV
15
14
13
12
CRTV
7
6
5
4
CRTV
• CRTV: Current Real-time Value
Returns the current value of the Real-time Timer.
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14.5.4 Real-time Timer Status Register
Name:
RTT_SR
Address:
0x400E143C
Access:
Read-only
31
–
30
–
29
–
28
–
27
–
26
–
25
–
24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
RTTINC
0
ALMS
• ALMS: Real-time Alarm Status
0 = The Real-time Alarm has not occurred since the last read of RTT_SR.
1 = The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Real-time Timer Increment
0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.
1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
276
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15.
Real-time Clock (RTC)
15.1
Description
The Real-time Clock (RTC) peripheral is designed for very low power consumption.
It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian or Persian calendar,
complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit
data bus.
The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour
mode or 12-hour mode with an AM/PM indicator.
Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit
data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an
incompatible date according to the current month/year/century.
A clock divider calibration circuitry enables to compensate crystal oscillator frequency inaccuracy.
15.2
Embedded Characteristics
Ultra Low Power Consumption
Full Asynchronous Design
Gregorian Calendar up to 2099 or Persian Calendar
Programmable Periodic Interrupt
Safety/security features:
̶
Valid Time and Date Programmation Check
̶
On-The-Fly Time and Date Validity Check
Crystal Oscillator Clock Calibration
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15.3
Block Diagram
Figure 15-1.
RTC Block Diagram
Slow Clock: SLCK
32768 Divider
Time
Date
Clock Calibration
APB
15.4
User Interface
Entry
Control
Alarm
Interrupt
Control
RTC Interrupt
Product Dependencies
15.4.1 Power Management
The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on
RTC behavior.
15.4.2 Interrupt
RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the
interrupt controller to be programmed first.
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15.5
Functional Description
The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years),
month, date, day, hours, minutes and seconds.
The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar(or 1300 to 1499 in Persian
mode).
The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.
Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year
2099.
15.5.1 Reference Clock
The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal.
During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal
selection has to take into account the current consumption for power saving and the frequency drift due to
temperature effect on the circuit for time accuracy.
15.5.2 Timing
The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at oneminute intervals for the counter of minutes and so on.
Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read
in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is
necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of
two and a maximum of three accesses are required.
15.5.3 Alarm
The RTC has five programmable fields: month, date, hours, minutes and seconds.
Each of these fields can be enabled or disabled to match the alarm condition:
If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt
generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute.
Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging
from minutes to 365/366 days.
Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC,
MIN, HOUR fields.
Note:
To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing
the value and re-enable it after the value has been changed. This requires up to 3 accesses to the RTC_TIMALR or
RTC_CALALR registers. First access to only clear the enable corresponding to the field to change (SECEN, MINEN,
HOUREN, DATEEN, MTHEN), this access is not required if the field is already cleared. The second access performs
the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by
writing 1 in SECEN, MINEN, HOUREN, DATEEN, MTHEN fields.
15.5.4 Error Checking when Programming
Verification on user interface data is performed when accessing the century, year, month, date, day, hours,
minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with
regard to the year and century configured.
If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity
register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids
any further side effects in the hardware. The same procedure is done for the alarm.
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The following checks are performed:
1. Century (check if it is in range 19 - 20 or 13-14 in Persian mode)
2. Year (BCD entry check)
3.
Date (check range 01 - 31)
4.
Month (check if it is in BCD range 01 - 12, check validity regarding “date”)
5.
Day (check range 1 - 7)
6.
Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set
in 24-hour mode; in 12-hour mode check range 01 - 12)
7.
Minute (check BCD and range 00 - 59)
8.
Second (check BCD and range 00 - 59)
Note:
If the 12-hour mode is selected by means of the RTC_MR register, a 12-hour value can be programmed and the
returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the
AM/PM indicator (bit 22 of RTC_TIMR register) to determine the range to be checked.
15.5.5 RTC Internal Free Running Counter Error Checking
To improve the reliability and security of the RTC, a permanent check is performed on the internal free running
counters to report non-BCD or invalid date/time values.
An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The
flag can be cleared by programming the TDERRCLR in the RTC status clear control register (RTC_SCCR).
Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the
TDERR flag. The clearing of the source of such error can be done either by reprogramming a correct value on
RTC_CALR and/or RTC_TIMR registers.
The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e.
every 10 seconds for SECONDS[3:0] bitfield in RTC_TIMR register). In this case the TDERR is held high until a
clear command is asserted by TDERRCLR bit in RTC_SCCR register.
15.5.6 Updating Time/Calendar
To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the
Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be
set to update calendar fields (century, year, month, date, day).
Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit
reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to
the appropriate Time and Calendar register.
Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control
When entering programming mode of the calendar fields, the time fields remain enabled. When entering the
programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the
calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the
fields to be updated before entering programming mode. In successive update operations, the user must wait at
least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these
bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit.
After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared.
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Figure 15-2.
Update Sequence
Begin
Prepare TIme or Calendar Fields
Set UPDTIM and/or UPDCAL
bit(s) in RTC_CR
Read RTC_SR
Polling or
IRQ (if enabled)
ACKUPD
=1?
No
Yes
Clear ACKUPD bit in RTC_SCCR
Update Time and/or Calendar values in
RTC_TIMR/RTC_CALR
Clear UPDTIM and/or UPDCAL bit in
RTC_CR
End
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15.5.7 RTC Accurate Clock Calibration
The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation.
The RTC is equipped with circuitry able to correct slow clock crystal drift.
To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be
programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal
frequency accuracy at room temperature (20-25°C). The typical clock drift range at room temperature is ±20 ppm.
In a temperature range of -40°C to +85°C, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200
ppm.
The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm. After
correction, the remaining crystal drift is as follows:
Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 90 ppm
Below 2 ppm, for an initial crystal drift between 90 ppm up to 130 ppm
Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm
The calibration circuitry acts by slightly modifying the 1 Hz clock period from time to time. When the period is
modified, depending on the sign of the correction, the 1 Hz clock period increases or reduces by around 4 ms. The
period interval between 2 correction events is programmable in order to cover the possible crystal oscillator clock
variations.
The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20-25 degrees Celsius) can be
compensated if a reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can
be set up during the final product manufacturing by means of measurement equipment embedding such a
reference clock. The correction of value must be programmed into the RTC Mode Register (RTC_MR), and this
value is kept as long as the circuitry is powered (backup area). Removing the backup power supply cancels this
calibration. This room temperature calibration can be further processed by means of the networking capability of
the target application.
In any event, this adjustment does not take into account the temperature variation.
The frequency drift (up to -200 ppm) due to temperature variation can be compensated using a reference time if
the application can access such a reference. If a reference time cannot be used, a temperature sensor can be
placed close to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once
obtained, the temperature may be converted using a lookup table (describing the accuracy/temperature curve of
the crystal oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This
adjustment method is not based on a measurement of the crystal frequency/drift and therefore can be improved by
means of the networking capability of the target application.
If no crystal frequency adjustment has been done during manufacturing, it is still possible to do it. In the case
where a reference time of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of
the application crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and
programming the HIGHPPM and CORRECTION bitfields on RTC_MR according to the difference measured
between the reference time and those of RTC_TIMR.
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15.6
Real-time Clock (RTC) User Interface
Table 15-1.
Offset
Register Mapping
Register
Name
Access
Reset
0x00
Control Register
RTC_CR
Read-write
0x0
0x04
Mode Register
RTC_MR
Read-write
0x0
0x08
Time Register
RTC_TIMR
Read-write
0x0
0x0C
Calendar Register
RTC_CALR
Read-write
0x01A11020
0x10
Time Alarm Register
RTC_TIMALR
Read-write
0x0
0x14
Calendar Alarm Register
RTC_CALALR
Read-write
0x01010000
0x18
Status Register
RTC_SR
Read-only
0x0
0x1C
Status Clear Command Register
RTC_SCCR
Write-only
–
0x20
Interrupt Enable Register
RTC_IER
Write-only
–
0x24
Interrupt Disable Register
RTC_IDR
Write-only
–
0x28
Interrupt Mask Register
RTC_IMR
Read-only
0x0
0x2C
Valid Entry Register
RTC_VER
Read-only
0x0
0x30–0xC4
Reserved Register
–
–
–
0xC8–0xF8
Reserved Register
–
–
–
0xFC
Reserved Register
–
–
–
Note: If an offset is not listed in the table it must be considered as reserved.
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15.6.1 RTC Control Register
Name:
RTC_CR
Address:
0x400E1460
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
–
–
–
16
CALEVSEL
9
8
TIMEVSEL
7
6
5
4
3
2
1
0
–
–
–
–
–
–
UPDCAL
UPDTIM
• UPDTIM: Update Request Time Register
0 = No effect.
1 = Stops the RTC time counting.
Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and
acknowledged by the bit ACKUPD of the Status Register.
• UPDCAL: Update Request Calendar Register
0 = No effect.
1 = Stops the RTC calendar counting.
Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once
this bit is set.
• TIMEVSEL: Time Event Selection
The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.
Value
Name
Description
0
MINUTE
Minute change
1
HOUR
Hour change
2
MIDNIGHT
Every day at midnight
3
NOON
Every day at noon
• CALEVSEL: Calendar Event Selection
The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL
Value
Name
Description
0
WEEK
Week change (every Monday at time 00:00:00)
1
MONTH
Month change (every 01 of each month at time 00:00:00)
2
YEAR
Year change (every January 1 at time 00:00:00)
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15.6.2 RTC Mode Register
Name:
RTC_MR
Address:
0x400E1464
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
HIGHPPM
CORRECTION
7
6
5
4
3
2
1
0
–
–
–
NEGPPM
–
–
PERSIAN
HRMOD
• HRMOD: 12-/24-hour Mode
0 = 24-hour mode is selected.
1 = 12-hour mode is selected.
• PERSIAN: PERSIAN Calendar
0 = Gregorian Calendar.
1 = Persian Calendar.
• NEGPPM: NEGative PPM Correction
0 = positive correction (the divider will be slightly lower than 32768).
1 = negative correction (the divider will be slightly higher than 32768).
Refer to CORRECTION and HIGHPPM field descriptions.
• CORRECTION: Slow Clock Correction
0 = No correction
1..127 = The slow clock will be corrected according to the formula given below in HIGHPPM description.
• HIGHPPM: HIGH PPM Correction
0 = lower range ppm correction with accurate correction.
1 = higher range ppm correction with accurate correction.
If the absolute value of the correction to be applied is lower than 30ppm, it is recommended to clear HIGHPPM. HIGHPPM
set to 1 is recommended for 30 ppm correction and above.
Formula:
If HIGHPPM = 0, then the clock frequency correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less
than 1 ppm for a range correction from 1.5 ppm up to 30 ppm..
The correction field must be programmed according to the required correction in ppm, the formula is as follows:
3906
CORRECTION = ----------------------- – 1
20 × ppm
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The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field.
If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less
than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
The correction field must be programmed according to the required correction in ppm, the formula is as follows:
3906
CORRECTION = ------------ – 1
ppm
The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field.
If NEGPPM is set to 1, the ppm correction is negative.
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15.6.3 RTC Time Register
Name:
RTC_TIMR
Address:
0x400E1468
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
AMPM
15
14
10
9
8
2
1
0
HOUR
13
12
–
7
11
MIN
6
5
–
4
3
SEC
• SEC: Current Second
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MIN: Current Minute
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• HOUR: Current Hour
The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.
• AMPM: Ante Meridiem Post Meridiem Indicator
This bit is the AM/PM indicator in 12-hour mode.
0 = AM.
1 = PM.
All non-significant bits read zero.
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15.6.4 RTC Calendar Register
Name:
RTC_CALR
Address:
0x400E146C
Access:
Read-write
31
30
–
–
23
22
29
28
27
21
20
19
DAY
15
14
26
25
24
18
17
16
DATE
MONTH
13
12
11
10
9
8
3
2
1
0
YEAR
7
6
5
–
4
CENT
• CENT: Current Century
The range that can be set is 19 - 20 (gregorian) or 13-14 (persian) (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• YEAR: Current Year
The range that can be set is 00 - 99 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MONTH: Current Month
The range that can be set is 01 - 12 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• DAY: Current Day in Current Week
The range that can be set is 1 - 7 (BCD).
The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.
• DATE: Current Day in Current Month
The range that can be set is 01 - 31 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
All non-significant bits read zero.
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15.6.5 RTC Time Alarm Register
Name:
RTC_TIMALR
Address:
0x400E1470
Access:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
21
20
19
18
17
16
10
9
8
2
1
0
23
22
HOUREN
AMPM
15
14
HOUR
13
12
MINEN
7
11
MIN
6
5
SECEN
4
3
SEC
Note: To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and re-enable it
after the value has been changed. This requires up to 3 accesses to the RTC_TIMALR register. First access to only clear the
enable corresponding to the field to change (SECEN, MINEN, HOUREN), this access is not required if the field is already cleared.
The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by
writing 1 in SECEN, MINEN, HOUREN fields.
• SEC: Second Alarm
This field is the alarm field corresponding to the BCD-coded second counter.
• SECEN: Second Alarm Enable
0 = The second-matching alarm is disabled.
1 = The second-matching alarm is enabled.
• MIN: Minute Alarm
This field is the alarm field corresponding to the BCD-coded minute counter.
• MINEN: Minute Alarm Enable
0 = The minute-matching alarm is disabled.
1 = The minute-matching alarm is enabled.
• HOUR: Hour Alarm
This field is the alarm field corresponding to the BCD-coded hour counter.
• AMPM: AM/PM Indicator
This field is the alarm field corresponding to the BCD-coded hour counter.
• HOUREN: Hour Alarm Enable
0 = The hour-matching alarm is disabled.
1 = The hour-matching alarm is enabled.
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15.6.6 RTC Calendar Alarm Register
Name:
RTC_CALALR
Address:
0x400E1474
Access:
Read-write
31
30
DATEEN
–
29
28
27
26
25
24
18
17
16
DATE
23
22
21
MTHEN
–
–
20
19
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
MONTH
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
Note: To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and re-enable it after
the value has been changed. This requires up to 3 accesses to the RTC_CALALR register. First access to only clear the enable
corresponding to the field to change (DATEEN, MTHEN), this access is not required if the field is already cleared. The second
access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in
DATEEN, MTHEN fields.
• MONTH: Month Alarm
This field is the alarm field corresponding to the BCD-coded month counter.
• MTHEN: Month Alarm Enable
0 = The month-matching alarm is disabled.
1 = The month-matching alarm is enabled.
• DATE: Date Alarm
This field is the alarm field corresponding to the BCD-coded date counter.
• DATEEN: Date Alarm Enable
0 = The date-matching alarm is disabled.
1 = The date-matching alarm is enabled.
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15.6.7 RTC Status Register
Name:
RTC_SR
Address:
0x400E1478
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
TDERR
CALEV
TIMEV
SEC
ALARM
ACKUPD
• ACKUPD: Acknowledge for Update
0 (FREERUN) = Time and calendar registers cannot be updated.
1 (UPDATE) = Time and calendar registers can be updated.
• ALARM: Alarm Flag
0 (NO_ALARMEVENT) = No alarm matching condition occurred.
1 (ALARMEVENT) = An alarm matching condition has occurred.
• SEC: Second Event
0 (NO_SECEVENT) = No second event has occurred since the last clear.
1 (SECEVENT) = At least one second event has occurred since the last clear.
• TIMEV: Time Event
0 (NO_TIMEVENT) = No time event has occurred since the last clear.
1 (TIMEVENT) = At least one time event has occurred since the last clear.
The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following
events: minute change, hour change, noon, midnight (day change).
• CALEV: Calendar Event
0 (NO_CALEVENT) = No calendar event has occurred since the last clear.
1 (CALEVENT) = At least one calendar event has occurred since the last clear.
The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week
change, month change and year change.
• TDERR: Time and/or Date Free Running Error
0 (CORRECT) = The internal free running counters are carrying valid values since the last read of RTC_SR.
1 (ERR_TIMEDATE) = The internal free running counters have been corrupted (invalid date or time, non-BCD values)
since the last read and/or they are still invalid.
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15.6.8 RTC Status Clear Command Register
Name:
RTC_SCCR
Address:
0x400E147C
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
TDERRCLR
CALCLR
TIMCLR
SECCLR
ALRCLR
ACKCLR
• ACKCLR: Acknowledge Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• ALRCLR: Alarm Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• SECCLR: Second Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• TIMCLR: Time Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• CALCLR: Calendar Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• TDERRCLR: Time and/or Date Free Running Error Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
292
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15.6.9 RTC Interrupt Enable Register
Name:
RTC_IER
Address:
0x400E1480
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
TDERREN
CALEN
TIMEN
SECEN
ALREN
ACKEN
• ACKEN: Acknowledge Update Interrupt Enable
0 = No effect.
1 = The acknowledge for update interrupt is enabled.
• ALREN: Alarm Interrupt Enable
0 = No effect.
1 = The alarm interrupt is enabled.
• SECEN: Second Event Interrupt Enable
0 = No effect.
1 = The second periodic interrupt is enabled.
• TIMEN: Time Event Interrupt Enable
0 = No effect.
1 = The selected time event interrupt is enabled.
• CALEN: Calendar Event Interrupt Enable
0 = No effect.
1 = The selected calendar event interrupt is enabled.
• TDERREN: Time and/or Date Error Interrupt Enable
0 = No effect.
1 = The time and date error interrupt is enabled.
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15.6.10 RTC Interrupt Disable Register
Name:
RTC_IDR
Address:
0x400E1484
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
TDERRDIS
CALDIS
TIMDIS
SECDIS
ALRDIS
ACKDIS
• ACKDIS: Acknowledge Update Interrupt Disable
0 = No effect.
1 = The acknowledge for update interrupt is disabled.
• ALRDIS: Alarm Interrupt Disable
0 = No effect.
1 = The alarm interrupt is disabled.
• SECDIS: Second Event Interrupt Disable
0 = No effect.
1 = The second periodic interrupt is disabled.
• TIMDIS: Time Event Interrupt Disable
0 = No effect.
1 = The selected time event interrupt is disabled.
• CALDIS: Calendar Event Interrupt Disable
0 = No effect.
1 = The selected calendar event interrupt is disabled.
• TDERRDIS: Time and/or Date Error Interrupt Disable
0 = No effect.
• 1 = The time and date error interrupt is disabled.
294
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15.6.11 RTC Interrupt Mask Register
Name:
RTC_IMR
Address:
0x400E1488
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
CAL
TIM
SEC
ALR
ACK
• ACK: Acknowledge Update Interrupt Mask
0 = The acknowledge for update interrupt is disabled.
1 = The acknowledge for update interrupt is enabled.
• ALR: Alarm Interrupt Mask
0 = The alarm interrupt is disabled.
1 = The alarm interrupt is enabled.
• SEC: Second Event Interrupt Mask
0 = The second periodic interrupt is disabled.
1 = The second periodic interrupt is enabled.
• TIM: Time Event Interrupt Mask
0 = The selected time event interrupt is disabled.
1 = The selected time event interrupt is enabled.
• CAL: Calendar Event Interrupt Mask
0 = The selected calendar event interrupt is disabled.
1 = The selected calendar event interrupt is enabled.
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15.6.12 RTC Valid Entry Register
Name:
RTC_VER
Address:
0x400E148C
Access:
Read-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
NVCALALR
NVTIMALR
NVCAL
NVTIM
• NVTIM: Non-valid Time
0 = No invalid data has been detected in RTC_TIMR (Time Register).
1 = RTC_TIMR has contained invalid data since it was last programmed.
• NVCAL: Non-valid Calendar
0 = No invalid data has been detected in RTC_CALR (Calendar Register).
1 = RTC_CALR has contained invalid data since it was last programmed.
• NVTIMALR: Non-valid Time Alarm
0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register).
1 = RTC_TIMALR has contained invalid data since it was last programmed.
• NVCALALR: Non-valid Calendar Alarm
0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).
1 = RTC_CALALR has contained invalid data since it was last programmed.
296
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16.
Watchdog Timer (WDT)
16.1
Description
The Watchdog Timer (WDT) can be used to prevent system lock-up if the software becomes trapped in a
deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around
32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the
processor is in debug mode or idle mode.
16.2
16.3
Embedded Characteristics
12-bit key-protected programmable counter
Watchdog Clock is independent from Processor Clock
Provides reset or interrupt signals to the system
Counter may be stopped while the processor is in debug state or in idle mode
Block Diagram
Figure 16-1.
Watchdog Timer Block Diagram
write WDT_MR
WDT_MR
WDV
WDT_CR
WDRSTT
reload
1
0
12-bit Down
Counter
WDT_MR
reload
WDD
Current
Value
1/128
SLCK
32
kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher
frequency on XIN speeds up the programmer handshake.
20.3.4 Programmer Handshaking
An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY
signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once
NCMD signal is high and RDY is high.
20.3.4.1 Write Handshaking
For details on the write handshaking sequence, refer to Figure 20-2 and Table 20-4.
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351
Figure 20-2.
Parallel Programming Timing, Write Sequence
NCMD
2
4
3
RDY
5
NOE
NVALID
DATA[15:0]
1
MODE[3:0]
Table 20-4.
Write Handshake
Step
Programmer Action
Device Action
Data I/O
1
Sets MODE and DATA signals
Waits for NCMD low
Input
2
Clears NCMD signal
Latches MODE and DATA
Input
3
Waits for RDY low
Clears RDY signal
Input
4
Releases MODE and DATA signals
Executes command and polls NCMD high
Input
5
Sets NCMD signal
Executes command and polls NCMD high
Input
6
Waits for RDY high
Sets RDY
Input
20.3.4.2 Read Handshaking
For details on the read handshaking sequence, refer to Figure 20-3 and Table 20-5.
Figure 20-3.
Parallel Programming Timing, Read Sequence
NCMD
12
2
3
RDY
13
NOE
9
5
NVALID
6
4
Adress IN
DATA[15:0]
1
MODE[3:0]
352
11
7
ADDR
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Z
8
Data OUT
10
X
IN
Table 20-5.
Read Handshake
Step
Programmer Action
Device Action
DATA I/O
1
Sets MODE and DATA signals
Waits for NCMD low
Input
2
Clears NCMD signal
Latch MODE and DATA
Input
3
Waits for RDY low
Clears RDY signal
Input
4
Sets DATA signal in tristate
Waits for NOE Low
Input
5
Clears NOE signal
6
Waits for NVALID low
Tristate
7
Sets DATA bus in output mode and outputs the flash contents.
Output
Clears NVALID signal
Output
Waits for NOE high
Output
8
Reads value on DATA Bus
9
Sets NOE signal
10
Waits for NVALID high
Sets DATA bus in input mode
X
11
Sets DATA in output mode
Sets NVALID signal
Input
12
Sets NCMD signal
Waits for NCMD high
Input
13
Waits for RDY high
Sets RDY signal
Input
Output
20.3.5 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 20-3 on page
351. Each command is driven by the programmer through the parallel interface running several read/write
handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command
after a write automatically flushes the load buffer in the Flash.
20.3.5.1 Flash Read Command
This command is used to read the contents of the Flash memory. The read command can start at any valid
address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an
internal address buffer is automatically increased.
Table 20-6.
Read Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
READ
2
Write handshaking
ADDR0
Memory Address LSB
3
Write handshaking
ADDR1
Memory Address
4
Read handshaking
DATA
*Memory Address++
5
Read handshaking
DATA
*Memory Address++
...
...
...
...
n
Write handshaking
ADDR0
Memory Address LSB
n+1
Write handshaking
ADDR1
Memory Address
n+2
Read handshaking
DATA
*Memory Address++
n+3
Read handshaking
DATA
*Memory Address++
...
...
...
...
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353
20.3.5.2 Flash Write Command
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that
corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:
before access to any page other than the current one
when a new command is validated (MODE = CMDE)
The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
Table 20-7.
Write Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
WP or WPL or EWP or EWPL
2
Write handshaking
ADDR0
Memory Address LSB
3
Write handshaking
ADDR1
Memory Address
4
Write handshaking
DATA
*Memory Address++
5
Write handshaking
DATA
*Memory Address++
...
...
...
...
n
Write handshaking
ADDR0
Memory Address LSB
n+1
Write handshaking
ADDR1
Memory Address
n+2
Write handshaking
DATA
*Memory Address++
n+3
Write handshaking
DATA
*Memory Address++
...
...
...
...
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock
bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the
programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of
the lock region using a Flash write and lock command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.
20.3.5.3 Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the
erase command is aborted and no page is erased.
Table 20-8.
354
Full Erase Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
EA
2
Write handshaking
DATA
0
SAM4N8/SAM4N16 [DATASHEET]
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20.3.5.4 Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command
(SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the
command. When bit 0 of the bit mask is set, then the first lock bit is activated.
In the same way, the Clear Lock command (CLB) is used to clear lock bits.
Table 20-9.
Set and Clear Lock Bit Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
SLB or CLB
2
Write handshaking
DATA
Bit Mask
Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask
is set..
Table 20-10.
Get Lock Bit Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
GLB
Lock Bit Mask Status
2
Read handshaking
DATA
0 = Lock bit is cleared
1 = Lock bit is set
20.3.5.5 Flash General-purpose NVM Commands
General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command
also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set,
then the first GP NVM bit is activated.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The generalpurpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1.
Table 20-11.
Set/Clear GP NVM Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
SGPB or CGPB
2
Write handshaking
DATA
GP NVM bit pattern value
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is
active when bit n of the bit mask is set..
Table 20-12.
Get GP NVM Bit Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
GGPB
GP NVM Bit Mask Status
2
Read handshaking
DATA
0 = GP NVM bit is cleared
1 = GP NVM bit is set
20.3.5.6 Flash Security Bit Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash
programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit
once the contents of the Flash have been erased.
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Table 20-13.
Set Security Bit Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
SSE
2
Write handshaking
DATA
0
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the
Flash.
In order to erase the Flash, the user must perform the following:
Power-off the chip
Power-on the chip with TST = 0
Assert Erase during a period of more than 220 ms
Power-off the chip
Then it is possible to return to FFPI mode and check that Flash is erased.
20.3.5.7 Memory Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
Table 20-14.
Write Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
WRAM
2
Write handshaking
ADDR0
Memory Address LSB
3
Write handshaking
ADDR1
Memory Address
4
Write handshaking
DATA
*Memory Address++
5
Write handshaking
DATA
*Memory Address++
...
...
...
...
n
Write handshaking
ADDR0
Memory Address LSB
n+1
Write handshaking
ADDR1
Memory Address
n+2
Write handshaking
DATA
*Memory Address++
n+3
Write handshaking
DATA
*Memory Address++
...
...
...
...
20.3.5.8 Get Version Command
The Get Version (GVE) command retrieves the version of the FFPI interface.
Table 20-15.
356
Get Version Command
Step
Handshake Sequence
MODE[3:0]
DATA[15:0]
1
Write handshaking
CMDE
GVE
2
Read handshaking
DATA
Version
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 20-4.
Serial Programing
VDDIO
VDDIO
VDDIO
TST
PGMEN0
PGMEN1
VDDCORE
VDDIO
TDI
TDO
VDDPLL
TMS
VDDFLASH
TCK
GND
0-50MHz
XIN
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21.
SAM-BA Boot Program
21.1
Description
The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different
memories of the product.
21.2
Hardware and Software Constraints
SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size
can be used for user's code.
UART0 requirements: None.
Table 21-1.
21.3
Pins Driven during Boot Program Execution
Peripheral
Pin
PIO Line
UART0
URXD0
PA9
UART0
UTXD0
PA10
Flow Diagram
The Boot Program implements the algorithm illustrated in Figure 21-1.
Figure 21-1.
Boot Program Algorithm Flow Diagram
No
Device
Setup
Character # received
from UART0?
Yes
Run SAM-BA Monitor
The SAM-BA Boot Program uses the internal 12 MHz RC oscillator as source clock for PLL. The MCK runs from
PLL divided by 2. The core runs at 48 MHz.
21.4
Device Initialization
The initialization sequence is the following:
1.
358
Stack setup
2.
Set up the Embedded Flash Controller
3.
Switch on internal 12 MHz RC oscillator
4.
Configure PLL to run at 96 MHz
5.
Switch MCK to run on PLL divided by 2
6.
Configure UART0
7.
Disable Watchdog
8.
Wait for a character on UART0
9.
Jump to SAM-BA monitor (see Section 21.5 “SAM-BA Monitor”)
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21.5
SAM-BA Monitor
Once the communication interface is identified, the monitor runs in an infinite loop waiting for different commands
as shown in Table 21-2.
Table 21-2.
Commands Available through the SAM-BA Boot
Command
Action
Argument(s)
Example
N
Set Normal mode
No argument
N#
T
Set Terminal mode
No argument
T#
O
Write a byte
Address, Value#
O200001,CA#
o
Read a byte
Address,#
o200001,#
H
Write a half-word
Address, Value#
H200002,CAFE#
h
Read a half-word
Address,#
h200002,#
W
Write a word
Address, Value#
W200000,CAFEDECA#
w
Read a word
Address,#
w200000,#
S
Send a file
Address,#
S200000,#
R
Receive a file
Address, NbOfBytes#
R200000,1234#
G
Go
Address#
G200200#
V
Display version
No argument
V#
Mode commands:
̶
Normal mode configures SAM-BA Monitor to send/receive data in binary format
̶
Terminal mode configures SAM-BA Monitor to send/receive data in ASCII format
Write commands: Write a byte (O), a half-word (H) or a word (W) to the target
̶
Address: Address in hexadecimal
̶
Value: Byte, half-word or word to write in hexadecimal
̶
Read commands: Read a byte (o), a half-word (h) or a word (w) from the target
̶
Output: The byte, half-word or word read in hexadecimal following by ‘>’
Address: Address in hexadecimal
̶
Output: ‘>’
There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command
execution.
Receive a file (R): Receive data into a file from a specified address
̶
̶
Address: Address in hexadecimal
̶
̶
̶
Send a file (S): Send a file to a specified address
Note:
Output: ‘>’
Address: Address in hexadecimal
NbOfBytes: Number of bytes in hexadecimal to receive
Output: ‘>’
Go (G): Jump to a specified address and execute the code
̶
Address: Address to jump in hexadecimal
̶
Output: ‘>’
Get Version (V): Return the SAM-BA boot version
̶
Output: ‘>’
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21.5.1 UART0 Serial Port
Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send the application file to the target. The size of the binary file to send depends on the
SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size
because the Xmodem protocol requires some SRAM memory to work. See Section 21.2 “Hardware and Software
Constraints”.
21.5.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to
guarantee detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each
block of the transfer looks like:
in which:
̶
= 01 hex
̶
= binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
̶
= 1’s complement of the blk#.
̶
= 2 bytes CRC16
Figure 21-2 shows a transmission using this protocol.
Figure 21-2.
Xmodem Transfer Example
Host
Device
C
SOH 01 FE Data[128] CRC CRC
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
360
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21.5.3 In Application Programming (IAP) Feature
The IAP feature is a function located in ROM that can be called by any software application.
When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready
(looping while the FRDY bit is not set in the EEFC_FSR).
Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by
code running in Flash.
The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008).
This function takes one argument in parameter: the command to be sent to the EEFC.
This function returns the value of the EEFC_FSR.
IAP software code example:
(unsigned int) (*IAP_Function)(unsigned long);
void main (void){
unsigned
unsigned
unsigned
unsigned
long
long
long
long
FlashSectorNum = 200; //
flash_cmd = 0;
flash_status = 0;
EFCIndex = 0; // 0:EEFC0, 1: EEFC1
/* Initialize the function pointer (retrieve function address from NMI vector)
*/
IAP_Function = ((unsigned long) (*)(unsigned long))
0x00800008;
/* Send your data to the sector here */
/* build the command to send to EEFC */
flash_cmd =
(0x5A 10 MHz
10
mV
PLL Characteristics
Symbol
IPLL
Conditions
Current Consumption
Settling Time
Conditions
Min
Typ
Max
Unit
8
32
MHz
80
240
MHz
Active mode @ 80 MHz @ 1.2V
0.94
1.2
Active mode @ 96 MHz @ 1.2V
1.2
1.5
Active mode @ 160 MHz @ 1.2V
2.1
2.5
Active Mode @ 240 MHz @ 1.2V
3.34
4
60
150
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
mA
µs
813
36.6
10-bit ADC Characteristics
Table 36-28.
Analog Power Supply Characteristics
Symbol
Parameter
VVDDIN
Min
Typ
Max
ADC Analog Supply
1.62
3.0
3.6
VVDDcore
ADC Digital Supply
1.08
1.2
1.32
Vrip(max)
Max. Voltage Ripple
IVDDIN
Current Consumption
IVDD
Current Consumption
Table 36-29.
RMS value, 10 kHz to 10 MHz
Parameter
fADC
ADC Clock Frequency
tCP_ADC
ADC Clock Period
tCONV
ADC Conversion Time
Normal mode
220
Standby mode
1
Normal mode
tSTART
ADC Startup time
tTRACK
Track and Hold Time
1
V
mV
µA
µA
Conditions
Min
Max
Unit
1
16
MHz
62.5
1000
ns
ADC clock frequency = 16MHz
1.45
µs
VVDDIN > 3V @Temperature max
@ fADC = 16 MHz
510
VVDDIN > 3V
@ fADC = 14 MHz
450
VVDDIN > 2.4V
@ fADC = 14 MHz
380
VVDDIN < 2.4V
@ fADC = 10 MHz
300
After normal mode
40
ksps
1000
VDDIN < 3.0V
3.0V < VDDIN < 3.6V
Typ
(1)
µs
ns
500
1. The full speed is obtained for an input source impedance < 50 Ω or tTRACK = 500 ns.
Table 36-30.
External Voltage Reference Input
Parameter
Conditions
ADVREFP Input Voltage Range
(1)
ADVREFN Input Voltage Range(1)
Min
Typ
Max
Unit
Positive Reference Input
Vrefn + 1.62
–
VDDIN
V
Negative Reference Input
0
–
–
V
–
250
400
µA
ADVREF Current
Note:
814
290
10
Standby mode
Sampling Rate
fS
30
Unit
Channel Conversion Time and ADC Clock
Symbol
Note:
Conditions
1.
Reference voltages must be decoupled externally with large capacitors: 1 µF/10 nF.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.6.1 Static Performance Characteristics
In the following tables, the LSB is relative to analog scale:
Single Ended (ex: ADVREFP = 3.0V),
̶
Gain = 1, LSB = (3.0V / 1024) = 2.93 mV
Table 36-31.
Symbol
Static Performance Characteristics (1)
Parameter
Conditions
Min
Native ADC Resolution
Typ
Max
10
Unit
bit
Resolution with Digital Averaging
See ADC Controller
10
12
bit
INL
Integral Non-linearity
Native ADC resolution
-2
+2
LSB
DNL
Differential Non-linearity
Native ADC resolution
-1
+1
LSB
EO
Offset Error
Native ADC resolution
-5
5
LSB
EG
Gain Error
Native ADC resolution
-3
+3
LSB
Note:
1.
Table 36-32.
Single ended or differential mode, any gain values.
Dynamic Performance Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SNR
Signal to Noise Ratio
55
60
61
dB
THD
Total Harmonic Distortion
-68
-55
dB
SINAD
Signal to Noise and Distortion
52
59
ENOB
Effective Number of Bits
8.3
9.6
dB
10
bit
36.6.1.1 Track and Hold Time versus Source Output Impedance
The following figure shows a simplified acquisition path.
Figure 36-13. Simplified Acquisition Path
ADC
Input
Mux.
Sample & Hold
12-bit ADC
ZSOURCE
RON
Ci
During the tracking phase the ADC needs to track the input signal during the tracking time shown below:
10-bit mode: tTRACK = 0.12 × ZSOURCE + 500 (for 3.0V < VDDIO < 3.6V)
10-bit mode: tTRACK = 0.12 × ZSOURCE + 1000 (for VDDIO < 3.0V)
With tTRACK expressed in ns and ZSOURCE expressed in ohms.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
815
Table 36-33.
Symbol
Parameter
VIR
Input Voltage Range(1)
Ci
Input Capacitance
6
pF
ZSOURCE
Input Source Impedance
50
Ω
Note:
1.
Table 36-34.
Notes:
816
Analog Inputs
1.
2.
3.
Min
Typ
0
Programmable Voltage Reference Selection Values
ADC_ACR.IRVS Field Value
VREF (V)
0
2.426(1)
1
2.305
2
2.184
3
2.063
4
1.941
5
1.820
6
1.699
7
1.578(2)
8
3.396(3)
9
3.275
10
3.154
11
3.032
12
2.911
13
2.790
14
2.669
15
2.547
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Unit
VADVREFP
Input voltage range can be up to VDDIN without destruction or over-consumption.
If VDDIO < VADVREFP max input voltage is VDDIO.
Default value
Minimum value
Maximum value
Max
36.7
10-bit DAC Characteristics
Table 36-35.
Analog Power Supply Characteristics
Symbol
Parameter
VVDDIN
Conditions
Min
Typ
Max
DAC Analog Supply
1.62
3.0
3.6
VVDDcore
DAC Digital Supply
1.08
1.2
1.32
IVDDIN
Current Consumption
On VDDIN
200
280
360
µA
IVREFP
Current Consumption
On VREF
35
130
180
µA
2.2
µA
On VDDIN
1.5
µA
On VDDCORE
200
nA
Max
Unit
1
MHz
V
On VREF
IDD(standby)
Table 36-36.
Unit
Standby Current Consumption
Channel Conversion Time and DAC Clock
Symbol
Parameter
Conditions
Min
Typ
fDAC
Clock Frequency
Duty cycle is 50%
tCP_DAC
Clock Period
1
µs
tSTART
Startup time
20
µs
tCONV
Conversion Time
1
tCP_DAC
External voltage reference for DAC is ADVREFP. See the ADC voltage reference characteristics in Table 36-30 on
page 814.
Table 36-37.
Symbol
Static Performance Characteristics
Parameter
Conditions
Min
Resolution
Typ
Max
10
Unit
bit
DACin
DAC IN RANGE
0
1023
code
INL
Integral Non-linearity
Code Range [32 to 991]
-2
+2
LSB
DNL
Differential Non-linearity
Code Range [32 to 991]
-1
+1
LSB
EO
Offset Error
DACin = Mid Code
-10
+10
LSB
EG
Gain Error
-8
+8
LSB
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
817
36.8
Voltage Reference Description
Note:
Table 36-38.
Unless otherwise noted, Reference Voltage must be decoupled externally with large capacitors: 1 µF/10 nF.
Voltage Reference Characteristics
Symbol
Parameter
VREFINT
Reference Voltage Internal Available
VREF
Conditions
Min
Typ
Max
Unit
2
3.4
V
Reference Voltage
1.6
3.4
V
VREFACC
Reference Voltage Accuracy
-50
50
mV
IVDD
Current Consumption
Active mode
20
30
µA
IDDBIAS
Current Consumption
Voltage reference Off, ADC On or DAC On
7
10
µA
IDD(standby)
Standby Current
VDD @ 3.6V, leakage current
700
nA
IVDDI
Current Consumption, Digital
70
nA
IVDDI(standby)
Standby Current Consumption, Digital
50
nA
tSTART
Startup time
VDD @ 2V
100
VDD @ 3V
50
70
VDD @ 3.6V
36.9
µs
40
Temperature Sensor
The temperature sensor is connected to channel 15 of the ADC.
The temperature sensor provides an output voltage (VO_TS) that is proportional to absolute temperature (PTAT).
VO_TS linearly varies with a temperature slope dVO_TS/dT = 4.72 mV/°C.
VO_TS equals 1.44V at TA 27°C, with a ±60 mV accuracy. The VO_TS slope versus temperature dVO_TS/dT = 4.72
mV/°C only shows a ±7% slight variation over process, mismatch and supply voltage.
The user needs to calibrate it (offset calibration) at ambient temperature to eliminate the VO_TS spread at ambient
temperature (±15%).
Table 36-39.
Symbol
Temperature Sensor Characteristics
Parameter
Conditions
Power Supply
VO_TS
Output Voltage
TA = 27°C
VO_TS(accuracy)
Output Voltage Accuracy
TA = 27°C (needs to be calibrated in
application)
dVO_TS/dT
Temperature Sensitivity (Slope
Voltage vs Temperature
Slope Accuracy
Min
Typ
Max
Unit
2.4
3.3
3.6
V
1.44
-60
V
60
4.72
mV
mV/°C
Over temperature range -40 to 85 °C
-7
7
%
After offset calibration
Over temperature range -40 to 85 °C
-8
+8
°C
After offset calibration
Over temperature range 0 to 80 °C
-4
+4
°C
5
10
µs
70
80
Temperature Accuracy
tSTART
Startup Time
IVDDCORE
Current Consumption
Active mode
818
50
µA
Standby mode
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
1
36.10 AC Characteristics
36.10.1 Master Clock Characteristics
Table 36-40.
Symbol
1/(tCPMCK)
Master Clock Waveform Parameters
Parameter
Master Clock Frequency
Conditions
Min
Max
VDDCORE @ 1.20V
100
VDDCORE @ 1.08V
80
Unit
MHz
36.10.2 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
Output duty cycle (40%–60%)
Minimum output swing: 100 mV to VDDIO - 100 mV
Minimum output swing: 100 mV to VDDIO - 100 mV
Addition of rising and falling time inferior to 75% of the period
Table 36-41.
I/O Characteristics
Symbol
Parameter
FreqMax1
Pin Group 1 (1) Maximum Output Frequency
PulseminH1
Pin Group 1 (1) High Level Pulse Width
PulseminL1
Pin Group 1 (1) Low Level Pulse Width
FreqMax2
Pin Group 2 (2)Maximum Output Frequency
PulseminH2
Pin Group 2 (2) High Level Pulse Width
PulseminL2
Pin Group 2 (2) Low Level Pulse Width
FreqMax3
Pin Group 3(3) Maximum Output Frequency
PulseminH3
Pin Group 3 (3) High Level Pulse Width
PulseminL3
Pin Group 3 (3) Low Level Pulse Width
FreqMax4
Pin Group 4(4)Maximum Output Frequency
PulseminH4
Pin Group 4(4) High Level Pulse Width
PulseminL4
Pin Group 4(4) Low Level Pulse Width
FreqMax5
Pin Group 5(5)Maximum Output Frequency
Conditions
Min
Max
10 pF
70
25 pF
35
10 pF
7.2
25 pF
14.2
10 pF
7.2
25 pF
14.2
ns
70
25 pF
35
7.2
25pF
14.2
10 pF
7.2
25 pF
14.2
10 pF
25 pF
ns
35
10 pF
7.2
25 pF
14.2
10 pF
7.2
25 pF
14.2
ns
70
25 pF
35
7.2
25pF
14.2
10 pF
7.2
25 pF
14.2
MHz
ns
10 pF
10 pF
MHz
ns
70
VDDIO = 1.62V
MHz
ns
10 pF
10 pF
Unit
MHz
ns
ns
10 pF
70
25 pF
35
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
MHz
819
Table 36-41.
I/O Characteristics (Continued)
Symbol
Parameter
Conditions
PulseminH5
Pin Group 5(5) High Level Pulse Width
PulseminL5
Pin Group 5(5) Low Level Pulse Width
FreqMax6
Pin Group 6(6)Maximum Output Frequency
PulseminH6
Pin Group 6(6) High Level Pulse Width
PulseminL6
Pin Group 6(6) Low Level Pulse Width
FreqMax7
Pin Group 7(7)Maximum Output Frequency
PulseminH7
Pin Group 7(7) High Level Pulse Width
(7)
PulseminL7
Pin Group 7
FreqMax8
Pin Group 8(8)Maximum Output Frequency
PulseminH8
Pin Group 8(8) High Level Pulse Width
PulseminL8
Pin Group 8(8) Low Level Pulse Width
FreqMax9
Pin Group 9(9)Maximum Output Frequency
PulseminH9
Pin Group 9(9) High Level Pulse Width
PulseminL9
Pin Group 9(9) Low Level Pulse Width
Notes:
820
1.
2.
3.
4.
5.
6.
7.
8.
9.
Low Level Pulse Width
Min
10 pF
7.2
25 pF
14.2
10 pF
7.2
25 pF
14.2
Max
ns
ns
10 pF
70
25 pF
35
10 pF
7.2
25 pF
14.2
10 pF
7.2
25 pF
14.2
ns
70
30 pF
45
7.2
30 pF
11
10 pF
30 pF
VDDIO = 1.62V
ns
11
10 pF
70
25 pF
35
7.2
25 pF
14.2
10 pF
7.2
25 pF
14.2
ns
70
25 pF
35
7.2
25 pF
14.2
10 pF
7.2
25 pF
14.2
MHz
ns
10 pF
10 pF
MHz
ns
7.2
10 pF
MHz
ns
10 pF
10 pF
Unit
MHz
ns
ns
Pin Group 1 = PB0
Pin Group 2 = PA[22–17], PB[2–3], PB[13–14], PC[12–13], PC[15], PC[29–31]
Pin Group 3 = PB[1]
Pin Group 4 = PA[0–6], PA[9–11], PA[15–16], PA[23–28], PA[30–31], PB[4–7], PB[10–11], PC[0–11], PC[14], PC[16–28]
Pin Group 5 = PA[12]
Pin Group 6 = PA[13]
Pin Group 7 = PA[14], PA[19]
Pin Group 8 = PA[8–7], PB[8–9]
Pin Group 9 = PB[12]
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.10.3 SPI Characteristics
Figure 36-14. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
SPCK
SPI1
SPI0
MISO
SPI2
MOSI
Figure 36-15. SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
SPCK
SPI4
SPI3
MISO
SPI5
MOSI
Figure 36-16. SPI Slave Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
NPCSS
SPI13
SPI12
SPCK
SPI6
MISO
SPI7
SPI8
MOSI
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
821
Figure 36-17. SPI Slave Mode with(CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
NPCS0
SPI15
SPI14
SPCK
SPI9
MISO
SPI10
SPI11
MOSI
36.10.3.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write
modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or
SPI5) timing. Since it gives a maximum frequency above the maximum pad speed (see Section 36.10.2 “I/O
Characteristics”), the maximum SPI frequency is defined by the pin FreqMax value.
Master Read Mode
1
f SPCK Max = -----------------------------------------------------SPI 0 ( orSPI 3 ) + t valid
tvalid is the slave time response to output data after detecting an SPCK edge. For a non-volatile memory with
tvalid (or tv) = 12 ns, fSPCKmax = 43 MHz at VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold
timings SPI7/SPI8(or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in slave
read mode is given by SPCK pad.
Slave Write Mode
1
f SPCK Max = ------------------------------------------------------------------------------------2x ( S PI 6max ( orSPI 9max ) + t setup )
For 3.3V I/O domain and SPI6, fSPCKMax = 42 MHz. tsetup is the setup time from the master before sampling
data.
822
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
36.10.3.2 SPI Timings
SPI timings are given for the following domains:
3.3V domain: VVDDIO from 2.85 V to 3.6V, maximum external capacitor = 30 pF
1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF
Table 36-42.
SPI Timings
Symbol
Parameter
SPI0
MISO Setup Time before SPCK Rises (Master)
SPI1
MISO Hold Time after SPCK Rises (Master)
SPI2
SPCK Rising to MOSI Delay (Master)
SPI3
MISO Setup Time before SPCK Falls (Master)
SPI4
MISO Hold Time after SPCK Falls (Master)
SPI5
SPCK Falling to MOSI Delay (Master)
SPI6
SPCK Falling to MISO Delay (Slave)
SPI7
MOSI Setup Time before SPCK Rises (Slave)
SPI8
MOSI Hold Time after SPCK Rises (Slave)
SPI9
SPCK Rising to MISO Delay (Slave)
SPI10
MOSI Setup Time before SPCK Falls (Slave)
SPI11
MOSI Hold Time after SPCK Falls (Slave)
SPI12
NPCS Setup to SPCK Rising (Slave)
SPI13
NPCS Hold after SPCK Falling (Slave)
SPI14
NPCS Setup to SPCK Falling (Slave)
SPI15
NPCS Hold after SPCK Falling (Slave)
Conditions
Min
Max
3.3V domain
11.1
ns
1.8V domain
14.4
ns
3.3V domain
0
ns
1.8V domain
0
ns
3.3V domain
-2.5
3.6
ns
1.8V domain
-3.1
3.6
ns
3.3V domain
20.0
ns
1.8V domain
23.5
ns
3.3V domain
0
ns
1.8V domain
0
ns
3.3V domain
-6.5
-2.4
ns
1.8V domain
-6.6
-2.2
ns
3.3V domain
3.8
11.7
ns
1.8V domain
4.4
15.3
ns
3.3V domain
0
ns
1.8V domain
0
ns
3.3V domain
0.6
ns
1.8V domain
0.7
ns
3.3V domain
3.8
11.6
ns
1.8V domain
4.3
14.8
ns
3.3V domain
0.1
ns
1.8V domain
0.4
ns
3.3V domain
0.5
ns
1.8V domain
1.0
ns
3.3V domain
5.0
ns
1.8V domain
5.2
ns
3.3V domain
0
ns
1.8V domain
0
ns
3.3V domain
5.2
ns
1.8V domain
5.0
ns
3.3V domain
0
ns
1.8V domain
0
ns
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Unit
823
Note that in SPI master mode the SAM4N does not sample the data (MISO) on the opposite edge where data
clocks out (MOSI) but the same edge is used as shown in Figure 36-14 and Figure 36-15.
36.10.4 USART in SPI Mode Timings
Timings are given in the following domains:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF
Figure 36-18. USART SPI Master Mode
• MOSI line is driven by the output pin TXD
• MISO line drives the input pin RXD
• SCK line is driven by the output pin SCK
• NSS line is driven by the output pin RTS
NSS
SPI5
SPI3
CPOL = 1
SPI0
SCK
CPOL = 0
SPI4
MISO
SPI4
SPI1
SPI2
LSB
MSB
MOSI
The full speed is obtained for an input source impedance < 50 Ω or tTRACK = 500 ns.
Figure 36-19. USART SPI Slave Mode (Mode 1 or 2)
• MOSI line drives the input pin RXD
• MISO line is driven by the output pin TXD
• SCK line drives the input pin SCK
• NSS line drives the input pin CTS
NSS
SPI13
SPI12
SCK
SPI6
MISO
SPI7
MOSI
824
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
SPI8
36.10.4.1 USART SPI TImings
USART SPI timings are given for the following domains:
3.3V domain: VDDIO from 2.85 V to 3.6V, maximum external capacitor = 25 pF
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 25 pF
Table 36-43.
Symbol
USART SPI Timings
Parameter
Conditions
Min
Max
Unit
Master Mode
SPI0
SCK Period
SPI1
Input Data Setup Time
SPI2
Input Data Hold Time
SPI3
Chip Select Active to Serial Clock
SPI4
Output Data Setup Time
SPI5
Serial Clock to Chip Select Inactive
1.8V domain
3.3V domain
MCK/6
ns
1.8V domain
0.5 × MCK + 2.8
3.3V domain
0.5 × MCK + 2.1
1.8V domain
1.5 × MCK - 0.3
3.3V domain
1.5 × MCK - 0.4
1.8V domain
1.5 × SPCK - 2.6
3.3V domain
1.5 × SPCK - 2.0
1.8V domain
-6.5
12.7
3.3V domain
-3.3
10.5
1.8V domain
1 × SPCK - 5.0
3.3V domain
1 × SPCK - 3.1
ns
ns
ns
ns
ns
Slave Mode
SPI6
SCK Falling to MISO
SPI7
MOSI Setup Time before SCK Rises
SPI8
MOSI Hold Time after SCK Rises
SPI9
SCK Rising to MISO
SPI10
MOSI Setup Time before SCK Falls
SPI11
MOSI Hold Time after SCK Falls
SPI12
NPCS0 Setup to SCK Rising
SPI13
NPCS0 Hold after SCK Falling
SPI14
NPCS0 Setup to SCK Falling
SPI15
NPCS0 Hold after SCK Rising
1.8V domain
4.4
19.7
3.3V domain
3.7
13.3
1.8V domain
3.3V domain
2 × MCK + 1.9
2 × MCK + 1.4
1.8V domain
0
3.3V domain
0
1.8V domain
4.3
19.4
3.3V domain
3.8
13.3
1.8V domain
3.3Vdomain
2 × MCK + 1.5
2 × MCK + 1.3
1.8V domain
0
3.3V domain
0
1.8V domain
3.3V domain
2.5 × MCK + 2.1
2.5 × MCK + 1.8
1.8V domain
1.5 × MCK + 1.0
3.3V domain
1.5 × MCK + 0.5
1.8V domain
2.5 × MCK + 2.0
3.3V domain
2.5 × MCK + 1.9
1.8V domain
1.5 × MCK + 0.5
3.3V domain
1.5 × MCK + 0.3
ns
ns
ns
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
ns
ns
ns
ns
ns
ns
ns
825
36.10.5 Two-wire Serial Interface Characteristics
Table 36-44 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols
refer to Figure 36-20.
Table 36-44.
Two-wire Serial Bus Requirements
Symbol
Parameter
VIL
Condition
Min
Max
Unit
Input Low-voltage
-0.3
0.3 × VDDIO
V
VIH
Input High-voltage
0.7 × VDDIO
VCC + 0.3
V
Vhys
Hysteresis of Schmitt Trigger Inputs
0.150
–
V
VOL
Output Low-voltage
3 mA sink current
-
0.4
V
(1)(2)
300
ns
20 + 0.1Cb(1)(2)
250
ns
tr
Rise Time for both TWD and TWCK
tof
Output Fall Time from VIHmin to VILmax
Ci(1)
Capacitance for each I/O Pin
–
10
pF
fTWCK
TWCK Clock Frequency
0
400
kHz
Rp
Value of Pull-up Resistor
fTWCK ≤ 100 kHz
(VDDIO - 0.4V) ÷ 3mA
1000ns ÷ Cb
Ω
fTWCK > 100 kHz
(VDDIO - 0.4V) ÷ 3mA
300ns ÷ Cb
Ω
fTWCK ≤ 100 kHz
(3)
–
µs
fTWCK > 100 kHz
(3)
–
µs
fTWCK ≤ 100 kHz
(4)
–
µs
fTWCK > 100 kHz
(4)
–
µs
fTWCK ≤ 100 kHz
tHIGH
–
µs
fTWCK > 100 kHz
tHIGH
–
µs
fTWCK ≤ 100 kHz
tHIGH
–
µs
fTWCK > 100 kHz
tHIGH
–
tLOW
Low Period of the TWCK Clock
tHIGH
High period of the TWCK Clock
th(start)
Hold Time (Repeated) START Condition
tsu(start)
Set-up Time for a Repeated START
Condition
th(data)
Data Hold Time
tsu(data)
Data Setup Time
tsu(stop)
Setup Time for STOP Condition
tBUF
Bus Free Time between a STOP and
START Condition
Notes:
826
20 + 0.1Cb
10 pF < Cb < 400 pF
Figure 36-20
fTWCK ≤ 100 kHz
fTWCK > 100 kHz
0
3 × tCPMCK
0
3 × tCPMCK
(5)
fTWCK ≤ 100 kHz
tLOW - 3 ×
fTWCK > 100 kHz
tLOW - 3 × tCP_MCK
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
tCPMCK(5)
(5)
µs
µs
–
ns
–
ns
fTWCK ≤ 100 kHz
tHIGH
–
µs
fTWCK > 100 kHz
tHIGH
–
µs
fTWCK ≤ 100 kHz
tLOW
–
µs
fTWCK > 100 kHz
tLOW
–
µs
1. Required only for fTWCK > 100 kHz.
2. Cb = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF
3. The TWCK low period is defined as follows: tLOW = ((CLDIV × 2CKDIV) + 4) × tMCK
4. The TWCK high period is defined as follows: tHIGH = ((CHDIV × 2CKDIV) + 4) × tMCK
5. tCPMCK = MCK bus period.
SAM4N8/SAM4N16 [DATASHEET]
µs
(5)
Figure 36-20. Two-wire Serial Bus Timing
tHIGH
tfo
tr
tLOW
tLOW
TWCK
tsu(start)
th(start)
th(data)
tsu(data)
tsu(stop)
TWD
tBUF
36.10.6 Embedded Flash Characteristics
The embedded flash is fully tested during production test. The flash contents are not set to a known state prior to
shipment. Therefore, the flash contents should be erased prior to programming an application.
The maximum operating frequency given in Table 36-45 is limited by the embedded Flash access time when the
processor is fetching code out of it. The table provides the device maximum operating frequency defined by the
value of the field FWS in the EEFC_FMR. This field defines the number of wait states required to access the
Embedded Flash Memory.
Table 36-45.
Embedded Flash Wait State at 85°C
Maximum Operating Frequency (MHz)
VDDCORE 1.08V
VDDCORE 1.2V
EEFC_FMR.FWS
Read Operations
VDDIO 1.62–3.6 V
VDDIO 2.7–3.6 V
VDDIO 1.62–3.6 V
VDDIO 2.7–3.6 V
0
1 cycle
16
20
17
21
1
2 cycles
33
40
35
42
2
3 cycles
50
60
52
63
3
4 cycles
67
80
70
84
4
5 cycles
84
86
87
106
Table 36-46.
AC Flash Characteristics
Parameter
Typ
Max
Unit
Erase Page Mode
10
50
ms
Erase Block Mode (by 4 Kbytes)
50
200
ms
Erase Sector Mode
400
950
ms
Write Page Mode: write page
1.5
3
ms
Write Page Mode: write 64-bit Word
20
40
µs
Write Page Mode: write 128-bit Word
40
80
µs
–
–
ms
9
18
512 Kbytes
5.5
11
256 Kbytes
3
6
128 Kbytes
2
4
Data Retention
Not powered or powered
20
Endurance
Write/Erase cycles per page, block or sector @ 85°C
Program Cycle Time
Erase Pin Assertion Time
Conditions
Min
Erase pin high
220
1 Mbyte
Full Chip Erase
10k
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
s
years
cycles
827
37.
SAM4N Mechanical Characteristics
Figure 37-1.
100-lead LQFP Package Mechanical Drawing
CONTROL DIMENSIONS ARE IN MILLIMETERS.
Note: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
Table 37-1.
Device and 100-lead LQFP Package Maximum Weight
SAM4N
Table 37-2.
800
mg
100-lead LQFP Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
e3
Table 37-3.
100-lead LQFP Package Characteristics
Moisture Sensitivity Level
3
This package respects the recommendations of the NEMI User Group.
828
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Figure 37-2.
100-ball TFBGA Package Drawing
0.0433
Table 37-4.
100-ball TFBGA Package Reference - Soldering Information (Substrate Level)
Ball Land
Diameter 0.35 mm
Soldering Mask Opening
350 µm
Table 37-5.
Device and 100-ball TFBGA Package Maximum Weight
SAM4N
140
Table 37-6.
100-ball TFBGA Package Characteristics
Moisture Sensitivity Level
Table 37-7.
mg
3
100-ball TFBGA Package Reference
JEDEC Drawing Reference
MO-275-DDAC-01
JESD97 Classification
e8
This package respects the recommendations of the NEMI User Group.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
829
Figure 37-3.
830
100-ball VFBGA Package Drawing
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 37-8.
100-ball VFBGA Package Reference - Soldering Information (Substrate Level)
Ball Land
Diameter 0.27 mm
Soldering Mask Opening
275 µm
Table 37-9.
Device and 100-ball VFBGA Package Maximum Weight
SAM4N
75
Table 37-10.
100-ball VFBGA Package Characteristics
Moisture Sensitivity Level
Table 37-11.
mg
3
100-ball VFBGA Package Reference
JEDEC Drawing Reference
MO-275-BBE-1
JESD97 Classification
e8
This package respects the recommendations of the NEMI User Group.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
831
Figure 37-4.
832
64-lead LQFP Package Drawing
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 37-12.
64-lead LQFP Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
Nom
Max
Min
Nom
Max
A
–
–
1.60
–
–
0.063
A1
0.05
–
0.15
0.002
–
0.006
A2
1.35
1.40
1.45
0.053
0.055
0.057
D
12.00 BSC
0.472 BSC
D1
10.00 BSC
0.383 BSC
E
12.00 BSC
0.472 BSC
E1
10.00 BSC
0.383 BSC
R2
0.08
–
0.20
0.003
–
0.008
R1
0.08
–
–
0.003
–
–
q
0°
3.5°
7°
0°
3.5°
7°
θ1
0°
–
–
0°
–
–
θ2
11°
12°
13°
11°
12°
13°
θ3
11°
12°
13°
11°
12°
13°
c
0.09
–
0.20
0.004
–
0.008
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00 REF
0.039 REF
S
0.20
–
–
0.008
–
–
b
0.17
0.20
0.27
0.007
0.008
0.011
e
0.50 BSC.
0.020 BSC.
D2
7.50
0.285
E2
7.50
0.285
Tolerances of Form and Position
aaa
0.20
0.008
bbb
0.20
0.008
ccc
0.08
0.003
ddd
0.08
0.003
Table 37-13.
Device and 64-lead LQFP Package Maximum Weight
SAM4N
Table 37-14.
750
mg
64-lead LQFP Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
e3
Table 37-15.
64-lead LQFP Package Characteristics
Moisture Sensitivity Level
3
This package respects the recommendations of the NEMI User Group.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
833
Figure 37-5.
834
64-pad QFN Package Drawing
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 37-16.
64-pad QFN Package Dimensions (in mm)
Millimeter
Symbol
Inch
Min
Nom
Max
Min
Nom
Max
A
–
–
090
–
–
0.035
A1
–
–
0.05
–
–
0.001
A2
–
0.65
0.70
–
0.026
0.028
A3
0.20 REF
b
0.23
D
0.25
0.008 REF
0.28
0.009
0.010
9.00 BSC
D2
6.95
E
7.10
0.011
0.354 BSC
7.25
0.274
0.280
9.00 BSC
0.285
0.354 BSC
E2
6.95
7.10
7.25
0.274
0.280
0.285
L
0.35
0.40
0.45
0.014
0.016
0.018
e
0.50 BSC
R
0.125
–
0.020 BSC
–
0.0005
–
–
Tolerances of Form and Position
aaa
0.10
0.004
bbb
0.10
0.004
ccc
0.05
0.002
Table 37-17.
Device and 64-pad QFN Package Maximum Weight (Preliminary)
SAM4N
Table 37-18.
280
mg
64-pad QFN Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
e3
Table 37-19.
64-pad QFN Package Characteristics
Moisture Sensitivity Level
3
This package respects the recommendations of the NEMI User Group.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
835
Figure 37-6.
836
48-lead LQFP Package Drawing
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 37-20.
48-lead LQFP Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
Nom
Max
Min
Nom
Max
A
–
–
1.60
–
–
0.063
A1
0.05
–
0.15
0.002
–
0.006
A2
1.35
1.40
1.45
0.053
0.055
0.057
D
9.00 BSC
0.354SC
D1
7.00 BSC
0.276 BSC
E
9.00 BSC
0.354 BSC
E1
7.00 BSC
0.276 BSC
R2
0.08
–
0.20
0.003
–
0.008
R1
0.08
–
–
0.003
–
–
q
0°
3.5°
7°
0°
3.5°
7°
θ1
0°
–
–
0°
–
–
θ2
11°
12°
13°
11°
12°
13°
θ3
11°
12°
13°
11°
12°
13°
c
0.09
–
0.20
0.004
–
0.008
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00 REF
0.039 REF
S
0.20
–
–
0.008
–
–
b
0.17
0.20
0.27
0.007
0.008
0.011
e
0.50 BSC.
0.020 BSC.
D2
5.50
0.217
E2
5.50
0.217
Tolerances of Form and Position
aaa
0.20
0.008
bbb
0.20
0.008
ccc
0.08
0.003
ddd
0.08
0.003
Table 37-21.
Device and 48-lead LQFP Package Maximum Weight
SAM4N
Table 37-22.
190
48-lead LQFP Package Characteristics
Moisture Sensitivity Level
Table 37-23.
mg
3
48-lead LQFP Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
e3
This package respects the recommendations of the NEMI User Group.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
837
Figure 37-7.
838
48-pad QFN Package Drawing
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 37-24.
48-pad QFN Package Dimensions (in mm)
Millimeter
Inch
Symbol
Min
Nom
Max
Min
Nom
Max
A
–
–
0.90
–
–
0.035
A1
–
–
0.05
–
–
0.002
A2
–
0.65
0.70
–
0.026
0.028
A3
0.20 REF
b
0.18
D
0.20
0.008 REF
0.23
0.007
0.008
7.00 BSC
D2
5.45
E
5.60
0.009
0.276 BSC
5.75
0.215
0.220
7.00 BSC
0.226
0.274 BSC
E2
5.45
5.60
5.75
0.215
0.220
0.226
L
0.35
0.40
0.45
0.014
0.016
0.018
e
0.50 BSC
R
0.09
–
0.020 BSC
–
0.004
–
–
Tolerances of Form and Position
aaa
0.10
0.004
bbb
0.10
0.004
ccc
0.05
0.002
Table 37-25.
Device and 48-pad QFN Package Maximum Weight
SAM4N
Table 37-26.
142
48-pad QFN Package Characteristics
Moisture Sensitivity Level
Table 37-27.
mg
3
48-pad QFN Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
e3
This package respects the recommendations of the NEMI User Group.
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
839
37.1
Soldering Profile
Table 37-28 gives the recommended soldering profile from J-STD-020C.
Table 37-28.
Soldering Profile
Profile Feature
Green Package
Average Ramp-up Rate (217°C to Peak)
3°C/sec. max.
Preheat Temperature 175°C ± 25°C
180 sec. max.
Temperature Maintained above 217°C
60 sec. to 150 sec.
Time within 5°C of Actual Peak Temperature
20 sec. to 40 sec.
Peak Temperature Range
260°C
Ramp-down Rate
6°C/sec. max.
Time 25°C to Peak Temperature
8 min. max.
Note:
The package is certified to be backward compatible with Pb/Sn soldering profile.
A maximum of three reflow passes is allowed per component.
37.2
Packaging Resources
Land Pattern Definition.
Refer to the following IPC Standards:
840
IPC-7351A and IPC-782 (Generic Requirements for Surface Mount Design and Land Pattern Standards)
http://landpatterns.ipc.org/default.asp
Atmel Green and RoHS Policy and Package Material Declaration Data Sheet available on www.atmel.com
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
38.
Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking is as follows:
YYWW
V
XXXXXXXXX
ARM
where
“YY” manufactory year
“WW”: manufactory week
“V”: revision
“XXXXXXXXX”: lot number
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
841
39.
Ordering Information
Table 39-1.
Ordering Codes for SAM4N Devices
MRL
Flash
(Kbytes)
RAM
(Kbytes)
Package
Carrier Type
ATSAM4N16CA-CFU
A
1024
80
VFBGA 100
Tray
ATSAM4N16CA-CFUR
A
1024
80
VFBGA 100
Reel
ATSAM4N16CA-CU
A
1024
80
TFBGA100
Tray
ATSAM4N16CA-CUR
A
1024
80
TFBGA100
Reel
ATSAM4N16CA-AU
A
1024
80
QFP100
Tray
ATSAM4N16CA-AUR
A
1024
80
QFP100
Reel
ATSAM4N16BA-AU
A
1024
80
QFP64
Tray
ATSAM4N16BA-AUR
A
1024
80
QFP64
Reel
ATSAM4N16BA-MU
A
1024
80
QFN64
Tray
ATSAM4N16BA-MUR
A
1024
80
QFN64
Reel
ATSAM4N8CA-CFU
A
512
64
VFBGA 100
Tray
ATSAM4N8CA-CFUR
A
512
64
VFBGA 100
Reel
ATSAM4N8CA-CU
A
512
64
TFBGA100
Tray
ATSAM4N8CA-CUR
A
512
64
TFBGA100
Reel
ATSAM4N8CA-AU
A
512
64
QFP100
Tray
ATSAM4N8CA-AUR
A
512
64
QFP100
Reel
ATSAM4N8BA-AU
A
512
64
QFP64
Tray
ATSAM4N8BA-AUR
A
512
64
QFP64
Reel
ATSAM4N8BA-MU
A
512
64
QFN64
Tray
ATSAM4N8BA-MUR
A
512
64
QFN64
Reel
ATSAM4N8AA-AU
A
512
64
QFP48
Tray
ATSAM4N8AA-AUR
A
512
64
QFP48
Reel
ATSAM4N8AA-MU
A
512
64
QFN48
Tray
ATSAM4N8AA-MUR
A
512
64
QFN48
Reel
Ordering Code
842
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Operating
Temperature
Range
Industrial
-40°C to 85°C
40.
Errata
40.1
Watchdog
40.1.1 Get a reset at the Wake up of Wait Mode when the Watchdog is enabled
When the Watchdog is enabled and the bit WAITMODE = 1 (entry in Wait mode through WAITMODE bit in
CKGR_MOR). The wakeup of the low power mode (Wait mode) is done by the reset.
Problem Fix/Workaround
Execute the Wait-For-Event (WFE) instruction of the processor Cortex-M4 to enter in Wait mode when the
watchdog is enabled.
40.2
Brownout Detector
40.2.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected
In Active mode or in Wait mode, if the Brownout Detector is disabled (SUPC_MR.BODDIS = 1) and power is lost
on VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.
Problem Fix/Workaround
When the Brownout Detector is disabled in Active or in Wait mode, VDDCORE always needs to be powered.
40.3
Flash
40.3.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State
Flash read issues leading to wrong instruction fetch or incorrect data read may occur under the following operating
conditions:
VDDIO < 2.4V and Flash wait state(1) ≥ 1
If the core clock frequency does not require the use of the Flash wait state (2) (FWS = 0 in EEFC_FMR), or if only
data reads are performed on the Flash (e.g., if the code is running out of SRAM), there are no constraints on
VDDIO voltage. The usable voltage range for VDDIO is defined in Table 36-2 “DC Characteristics”.
Notes:
1.
2.
Defined in FWS field in EEFC_FMR.
See Section 36.10.6 “Embedded Flash Characteristics” for the maximum core clock frequency at zero (0) wait
state.
Problem Fix/Workaround
Two workarounds are available:
Reduce the device speed to decrease the number of wait states to 0.
Copy the code from Flash to SRAM at 0 wait states and then run the code out of SRAM.
SAM4E [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
843
41.
Revision History
In the tables that follow, the most recent version of the document appears first.
Table 41-1.
SAM4N Datasheet Rev. 11158B Revision History
Issue Date Comments
Formatting and editorial changes throughout
“Description”:
- in first paragraph, replaced “an RTC” with “a low-power RTC, a low-power RTT”
- added paragraph relating to low-power modes
- added paragraph relating to Real-time Event Management
Section 1. “Features”
Updated description of “Low-power Modes”
Under “Peripherals”:
- updated RTT and RTC descriptions
- added bullet “256-bit General Purpose Backup Registers (GPBR)”
Table 1-1 ”Configuration Summary”: updated footnotes for 16-bit Timer
Revised Section 2. “Block Diagram”
Section 3. “Signals Description”
Table 3-1 ”Signal Description List”: renamed “ADVREF” to “ADVREFP”
Section 4. “Package and Pinout”
Renamed “ADVREF” to “ADVREFP”
23-Mar-15 Table 4-3 ”SAM4N8/16 100-ball TFBGA Pinout”: transferred AD13 from ball E7 to A2 (E7 is now PA29 and A2 is now
PC29/AD13)
Table 4-4 ”SAM4N8/16 100-ball VFBGA Pinout”: transferred AD13 from ball D6 to C2 (D6 is now PA29 and C2 is now
PC29/AD13)
Section 5. “Power Considerations”:
Inserted new Section 5.2 “Power-up Considerations”
Revised Section 5.3 “Voltage Regulator”
Figure 5-3 “Core Externally Supplied”: corrected range “2.4V-3.6V” to “1.62–3.6 V” for ADC/DAC supply
Figure 5-4 “Core Externally Supplied (Backup Battery)”: deleted caption “ADC, DAC, Analog Comparator Supply (2.0V3.6V)”; below figure, added note “For temperature sensor, VDDIO needs to be greater than 2.4V.”
Section 5.5 “Active Mode”: corrected instances of “WUP” to “WKUP” throughout
Added Section 5.6 “Low-power Modes”
Revised Section 5.6.1 “Backup Mode”
Revised Section 5.6.2 “Wait Mode”
Revised Section 5.6.3 “Sleep Mode”
Table 5-1 ”Low Power Mode Configuration Summary”: updated contents in columns “Mode Entry” and “Potential Wake-up
Sources”
Updated Section 5.7 “Wake-up Sources”
Updated Section 5.8 “Fast Startup”
844
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 41-1.
SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
Section 6. “Input/Output Lines”
Section 6.2 “System I/O Lines”: in first paragraph, deleted sentence “System I/O lines are pins used by oscillators, test
mode, reset and JTAG to name but a few.”
Table 6-1 ”System I/O Configuration”: changed column header “SYSTEM_IO Bit Number” to “CCFG_SYSIO Bit No.”
Section 6.5 “ERASE Pin”: in first paragraph, added details relative to reprogamming Flash content; updated content
concerning ERASE pin assertion time
Added Section 6.6 “Anti-tamper Pins/Low-power Tamper Detection”
Removed section 7. “Processor and Architecture”
Section 7. “Memories”
Added Section 7.1 “Product Mapping” (was previously in section 7. “Processor and Architecture”)
Section 9. “System Controller”
Removed Figure 10-1 “System Controller Block Diagram” (reference diagram provided in Section 17. “Supply Controller
(SUPC)”)
Removed subsection 10.3 “Reset Controller” (reset controller described in Section 13. “Reset Controller (RSTC)”)
Removed subsection 10.5 “Chip Identification” (chip identification provided in Section 26. “Chip Identifier (CHIPID)”; JTAG
ID provided in Section 12.5.8 “ID Code Register”)
Section 10. “Peripherals”
23-Mar-15 Table 10-1 ”Peripheral Identifiers”: inserted two columns “NVIC Interrupt“ and “PMC Clock Control”
Table 10-2 ”Multiplexing on PIO Controller A (PIOA)”: added footnotes on selecting extra functions and system functions
Table 10-3 ”Multiplexing on PIO Controller B (PIOB)”: added footnotes on selecting extra functions and system functions
Table 10-4 ”Multiplexing on PIO Controller C (PIOC)”: added footnotes on selecting extra functions
Added Section 10.3.3 “Peripheral DMA Controller (PDC)” (was previously in section 7. “Processor and Architecture”)
Section 10.3 “Embedded Peripherals Overview”
Section 10.3.1 “Analog Mux”: in first sentence, corrected “ADC Channel Register” to “ADC Channel Enable Register”
Section 12. “Debug and Test Features”
Section 12.5.2 “Debug Architecture”: in first paragraph, corrected “Cortex-M4 embeds four functional units” to “Cortex-M4
embeds five functional units”
Section 12.5.8 “ID Code Register”: corrected JTAG ID from ‘0x05B2E03F’ to ‘0x05B3_603F’
Section 18. “General Purpose Backup Registers (GPBR)”
Table 18-1 ”Register Mapping”: corrected offset to ‘0x1C’ for General Purpose Backup Register 7
Section 18.3.1 “General Purpose Backup Register x”: added missing last address “0x400E14AC” for SYS_GPBR7
Section 21. “SAM-BA Boot Program”
Section 21.5.3 “In Application Programming (IAP) Feature”: replaced two instances of “MC_FSR register” with
“EEFC_FSR”
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
845
Table 41-1.
SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
Section 25. “Power Management Controller (PMC)”
Section 25.5 “Processor Clock Controller”: updated first paragraph to add content on WFE instruction
Section 25.10 “Fast Start-up”: updated second paragraph to add content on WFE instruction
Section 25.16.4 “PMC Peripheral Clock Enable Register 0”: removed bits PID2–PID7 from bitmap (register bits 2–7 now
reserved)
Section 25.16.5 “PMC Peripheral Clock Disable Register 0”: removed bits PID2–PID7 from bitmap (register bits 2–7 now
reserved)
Section 25.16.6 “PMC Peripheral Clock Status Register 0”: removed bits PID2–PID7 from bitmap (register bits 2–7 now
reserved)
Section 25.16.16 “PMC Fast Start-up Mode Register”: added bit LPM (Low Power Mode)
Section 29. “Two-wire Interface (TWI)”
Section 29.11.5 “TWI Clock Waveform Generator Register”: removed HOLD field (register bits 28:24 now reserved)
Section 32. “Timer Counter (TC)”
Instances of “Master clock” or “MCK” replaced with “peripheral clock”
Section 32.1 “Description”: modified first paragraph to read “A Timer Counter (TC) module includes three identical TC
channels. The number of implemented TC modules is device-specific.”
Section 32.2 “Embedded Characteristics”: deleted “Two global registers that act on all TC channels” from bullet list
Moved Table 32-1 ”Timer Counter Clock Assignment” from Section 32.1 “Description” to Section 32.3 “Block Diagram”
Section 32.5.2 “Power Management”: added “of each channel” after "to enable the Timer Counter clock"
Section 32.5.3 “Interrupt Sources”: changed title (was “Interrupt”), updated text and added Table 32-5 ”Peripheral IDs”
Figure 32-5 “Example of Transfer with PDC” replaced instances of “Internal PDC trigger” with “Peripheral trigger”
23-Mar-15
Section 32.6.2 “16-bit Counter”: in first paragraph, replaced instance of “0xFFFF” with “216-1”
Updated list of internal clock signals in Section 32.6.3 “Clock Selection”
Section 32.6.12.1 “WAVSEL = 00”: replaced instances of “0xFFFF” with “216-1”
Figure 32-10 “WAVSEL = 10 without Trigger” and Figure 32-11 “WAVSEL = 10 with Trigger”: replaced “0xFFFF” with “2n-1
(n = counter size)”
Section 32.6.12.3 “WAVSEL = 01”: replaced instances of “0xFFFF” with “216-1”
Figure 32-14 “WAVSEL = 11 without Trigger” and Figure 32-15 “WAVSEL = 11 with Trigger”: replaced “0xFFFF” with “2n-1
(n = counter size)”
Section 32.6.15.2 “Input Pre-processing”: deleted sentence “Filters can be disabled using the FILTER bit in the TC_BMR”
Figure 32-17 “Input Stage”: replaced “FILTER” with “MAXFILTER > 0”
Section 32.6.15.3 “Direction Status and Change Detection”: rewrote sixth paragraph for clarity
Section 32.6.15.4 “Position and Rotation Measurement”: rewrote first paragraph for clarity; at end of second paragraph,
defined “External Trigger Edge” and “External Trigger” configuration in TC_CMR
Section 32.6.15.5 “Speed Measurement”:
- replaced sentence “The speed can be read on TC_RA0 register in TC_CMR0” with “The speed can be read on field RA in
register TC_RA0”
- in fifth paragraph, replaced “EDGTRG can be set to 0x01” with “ETRGEDG must be set to 0x01”
Section 32.6.18 “Register Write Protection”: modified title (was “Write Protection System”) and revised content
Section 32.7.2 “TC Channel Mode Register: Capture Mode”: in ‘Name’ line, replaced “(WAVE = 0)” with
“(CAPTURE_MODE)”; updated names internal clock signals in TCCLKS field description (values 0–4)
Section 32.7.3 “TC Channel Mode Register: Waveform Mode”: in ‘Name’ line, replaced “(WAVE = 1)” with
“(WAVEFORM_MODE)”; updated names internal clock signals in TCCLKS field description (values 0–4)
846
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Table 41-1.
SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
Section 32. “Timer Counter (TC)” (cont’d)
Section 32.7.5 “TC Counter Value Register”: added notation “IMPORTANT: For 16-bit channels, CV field size is limited to
register bits 15:0”
Section 32.7.6 “TC Register A”: added notation “IMPORTANT: For 16-bit channels, RA field size is limited to register bits
15:0”
Section 32.7.7 “TC Register B”: added notation “IMPORTANT: For 16-bit channels, RB field size is limited to register bits
15:0”
Section 32.7.8 “TC Register C”: added notation “IMPORTANT: For 16-bit channels, RC field size is limited to register bits
15:0”
Section 32.7.9 “TC Status Register”: updated bit descriptions
Section 32.7.14 “TC Block Mode Register”: removed FILTER bit (register bit 19 now reserved); corrected TC2XC2S field
configuration values: value 2 is TIOA0 (was TIOA1); value 3 is TIOA1 (was TIOA2)
Section 32.7.20 “TC Write Protection Mode Register”: modified register name (was “TC Write Protect Mode Register”);
updated WPEN bit description (replaced list of protectable registers with link to Section 32.6.18 “Register Write Protection”)
Section 36. “SAM4N Electrical Characteristics”
Updated and harmonized parameter symbols
Table 36-2 ”DC Characteristics”: replaced two footnotes with single footnote
Table 36-3 ”1.2V Voltage Regulator Characteristics”: replaced two footnotes with single footnote in VDDIN conditions;
deleted “Cf. External Capacitor Requirements” from CDIN and CDOUT conditions
Table 36-4 ”Core Power Supply Brownout Detector Characteristics”: added parameter “Reset Period”
Table 36-7 ”Zero-Power-On Reset Characteristics”: modified parameter name “Reset Time-out Period” to “Reset Period”
Table 36-20 ”4/8/12 MHz RC Oscillators Characteristics”: updated Startup Time conditions
23-Mar-15 Table 36-21 ”32.768 kHz Crystal Oscillator Characteristics”: added parameter “Allowed Crystal Capacitance Load”
Table 36-23 ”3 to 20 MHz Crystal Oscillator Characteristics”: added “pF” unit for “Internal Load Capacitance” parameter;
deleted all footnotes
Section 36.3.3 “Active Mode Power Consumption”: updated conditions (VDDCORE and ambient temperature) for
“CoreMark Active Power Consumption” tables and for Figure 36-9 “SAM4N8/16 Active Power Consumption with
VDDCORE @ 1.2V, TA = 25°C”
Figure 36-10 “32.768 kHz Crystal Oscillator Schematics”: added caption “Ccrystal” to diagram
Updated Figure 36-12 “XIN Clock Timing”
Table 36-27 ”PLL Characteristics”: changed parameter “Start-up Time” to “Settling Time”
Figure 36-13 “Simplified Acquisition Path”: renamed caption “Csample” to “Ci”; renamed caption “12-bit ADC Core” to “12bit ADC”
Figure 36-19 “USART SPI Slave Mode (Mode 1 or 2)”: inserted correct diagram (was previously TWI diagram)
Figure 36-20 “Two-wire Serial Bus Timing”: inserted correct diagram (was previously USART diagram)
Section 36.10.3.1 “Maximum SPI Frequency”: updated contents under “Master Write Mode” and “Master Read Mode”
Added Table 36-34 ”Programmable Voltage Reference Selection Values”
Table 36-38 ”Voltage Reference Characteristics”: in bias current consumption, corrected conditions “Voltage reference
OFF, ADC ON OR ADC ON” to “Voltage reference Off, ADC On or DAC On”
Table 36-39 ”Temperature Sensor Characteristics”: deleted “After TSON = 1” from Startup Time conditions
Table 36-42 ”SPI Timings”: removed footnotes defining 1.8V and 3.3V domains (this information is now found at the
beginning of Section 36.10.3.2 “SPI Timings”)
Table 36-43 ”USART SPI Timings”: removed footnotes defining 1.8V and 3.3V domains (this information is now found at
the beginning of Section 36.10.4.1 “USART SPI TImings”)
Table 36-44 ”Two-wire Serial Bus Requirements”: added parameter “Bus free time between a STOP and START condition”
SAM4N8/SAM4N16 [DATASHEET]
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847
Table 41-1.
SAM4N Datasheet Rev. 11158B Revision History (Continued)
Issue Date Comments
Section 36. “SAM4N Electrical Characteristics” (cont’d)
Section 36.10.6 “Embedded Flash Characteristics”: inserted content about erasing flash content prior to programming an
application; corrected instance of “field FWS of the MC_FMR” to “field FWS in the EEFC_FMR”; replaced four “Embedded
Flash Wait State” tables with single Table 36-45 ”Embedded Flash Wait State at 85°C”
Table 36-46 ”AC Flash Characteristics”: added parameter “Erase Pin Assertion Time”; added Program Cycle Time values
for Write Page Mode
23-Mar-15
Section 37. “SAM4N Mechanical Characteristics”
Figure 37-2 “100-ball TFBGA Package Drawing”: corrected ‘A’ maximum dimension in inches from 0.0575 to 0.0433
Added Section 38. “Marking”
Section 39. “Ordering Information”
Table 39-1 ”Ordering Codes for SAM4N Devices”: updated column headers; removed “Package Type” column (this
information is provided on the Atmel website)
Added Section 40. “Errata”
Doc. Rev.
11158A
Comments
First Issue
848
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
Change
Request
Ref.
Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1
Configuration Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.
Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.
Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
5.
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
6.
General Purpose I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ERASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Anti-tamper Pins/Low-power Tamper Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
25
26
26
26
Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Real-time Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1
8.2
9.
17
17
18
18
20
20
23
23
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
7.2
8.
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Powering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1
6.2
6.3
6.4
6.5
6.6
7.
Overview of the 100-lead LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overview of the 100-ball TFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overview of the 100-ball VFBGA Package (7 x 7 x 1 mm - 0.65 mm ball pitch) . . . . . . . . . . . . . . . . . 9
100-lead LQFP, TFBGA and VFBGA Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overview of the 64-lead LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overview of the 64-lead QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
64-lead LQFP and QFN Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overview of the 48-lead LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overview of the 48-lead QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
48-lead LQFP and QFN Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Real-time Event Mapping List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.1
System Controller and Peripherals Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SAM4N8/SAM4N16 [DATASHEET]
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i
9.2
9.3
Power-on-Reset, Brownout and Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SysTick Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1
10.2
10.3
Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Peripherals Signals Multiplexing on I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Embedded Peripherals Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. ARM Cortex-M4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Cortex-M4 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Cortex-M4 Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
System Control Block (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
System Timer (SysTick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
12. Debug and Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
12.1
12.2
12.3
12.4
12.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
249
249
250
251
252
13. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.1
13.2
13.3
13.4
13.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
257
257
257
258
265
14. Real-time Timer (RTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
14.1
14.2
14.3
14.4
14.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
269
269
269
270
272
15. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
15.1
15.2
15.3
15.4
15.5
15.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
277
277
278
278
279
283
16. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
ii
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16.1
16.2
16.3
16.4
16.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
297
297
297
298
300
17. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
17.1
17.2
17.3
17.4
17.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
305
305
306
307
315
18. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
18.1
18.2
18.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
General Purpose Backup Registers (GPBR) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
19. Embedded Flash Controller (EFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
19.1
19.2
19.3
19.4
19.5
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Enhanced Embedded Flash Controller (EEFC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
20. Fast Flash Programming Interface (FFPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
20.1
20.2
20.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Parallel Fast Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
21. SAM-BA Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
21.1
21.2
21.3
21.4
21.5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware and Software Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
358
358
358
358
359
22. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Bus Granting Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Matrix (MATRIX) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
362
362
363
363
364
366
366
367
23. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
23.1
23.2
23.3
23.4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
374
374
375
376
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iii
23.5
Peripheral DMA Controller (PDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
24. Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
24.1
24.2
24.3
24.4
24.5
24.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Slow Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Main Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Divider and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
25. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
25.10
25.11
25.12
25.13
25.14
25.15
25.16
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Master Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
SysTick Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Peripheral Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Free Running Processor Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Programmable Clock Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Fast Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Main Crystal Clock Failure Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Slow Crystal Clock Frequency Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Clock Switching Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Write Protection Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Power Management Controller (PMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
26. Chip Identifier (CHIPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
26.1
26.2
26.3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
27. Parallel Input/Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
27.1
27.2
27.3
27.4
27.5
27.6
27.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
I/O Lines Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
28. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
28.1
28.2
28.3
28.4
28.5
28.6
28.7
28.8
iv
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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502
502
503
503
504
504
506
519
29. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
29.9
29.10
29.11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Two-wire Interface (TWI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
535
535
536
536
537
537
539
540
552
555
562
30. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . 577
30.1
30.2
30.3
30.4
30.5
30.6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . . . . . . . . . . . . . . . . . .
577
577
577
578
579
585
31. Universal Synchronous Asynchronous Receiver Transmitter (USART) . . . . . . . . . 596
31.1
31.2
31.3
31.4
31.5
31.6
31.7
31.8
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface . . . . . . . . .
596
596
597
598
598
599
601
628
32. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
32.1
32.2
32.3
32.4
32.5
32.6
32.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Counter (TC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
657
657
658
659
660
661
681
33. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
33.1
33.2
33.3
33.4
33.5
33.6
33.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Width Modulation Controller (PWM) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
711
711
712
712
713
715
722
34. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
34.1
34.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
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34.3
34.4
34.5
34.6
34.7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
738
738
739
741
753
35. Digital-to-Analog Converter Controller (DACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
35.1
35.2
35.3
35.4
35.5
35.6
35.7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Converter Controller (DACC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .
778
778
779
779
780
781
783
36. SAM4N Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
36.1
36.2
36.3
36.4
36.5
36.6
36.7
36.8
36.9
36.10
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-bit DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
793
794
799
808
813
814
817
818
818
819
37. SAM4N Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
37.1
37.2
Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Packaging Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
38. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
39. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
40. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
40.1
40.2
40.3
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Brownout Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
41. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i
vi
SAM4N8/SAM4N16 [DATASHEET]
Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15
ARM Connected Logo
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Atmel Corporation
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© 2015 Atmel Corporation. / Rev.: Atmel-11158B-ATARM-SAM4N8-SAM4N16-Datasheet_23-Mar-15.
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other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be
trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
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BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information
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authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where
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