ATSAM4S16CA-CFUR

SAM4S Series Atmel | SMART ARM-based Flash MCU DATASHEET Description The Atmel ® | SMART SAM4S series is a member of a family of Flash microcontrollers based on the high-performance 32-bit ARM® Cortex®-M4 RISC processor. It operates at a maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with optional dual-bank implementation and cache memory, and up to 160 Kbytes of SRAM. The peripheral set includes a full-speed U S B D e v ic e p o r t w i t h e m b e d d e d t r a n s c e i v e r , a h i g h - s p e e d M C I f o r SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Controller to connect to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2 USARTs, 2 UARTs, 2 TWIs, 3 SPIs, an I2S, as well as a PWM timer, two 3channel general-purpose 16-bit timers (with stepper motor and quadrature decoder logic support), an RTC, a 12-bit ADC, a 12-bit DAC and an analog comparator. The SAM4S series is ready for capacitive touch, offering native support for the Atmel QTouch® library for easy implementation of buttons, wheels and sliders. The Atmel | SMART SAM4S devices have three software-selectable low-power modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while all other functions can be kept running. In Wait mode, all clocks and functions are stopped but some peripherals can be configured to wake up the system based on predefined conditions. In Backup mode, only the low-power RTC and wakeup logic are running. The real-time event management allows peripherals to receive, react to and send events in Active and Sleep modes without processor intervention. The SAM4S device is a medium-range general-purpose microcontroller with the best ratio in terms of reduced power consumption, processing power and peripheral set. This enables the SAM4S to sustain a wide range of applications that includes consumer, industrial control, and PC peripherals. SAM4S devices operate from 1.62V to 3.6V. The SAM4S series is pin-to-pin compatible with the SAM3N, SAM3S series (48-, 64- and 100-pin versions), SAM4N and SAM7S legacy series (64-pin versions). Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Features 2  Core ̶ ARM Cortex-M4 with 2 Kbytes of cache running at up to 120 MHz ̶ Memory Protection Unit (MPU) ̶ DSP Instruction Set ̶ Thumb®-2 instruction set  Pin-to-pin compatible with SAM3N, SAM3S, SAM4N and SAM7S legacy products (64-pin version)  Memories ̶ Up to 2048 Kbytes embedded Flash with optional dual-bank and cache memory, ECC, Security Bit and Lock Bits ̶ Up to 160 Kbytes embedded SRAM ̶ 16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines ̶ 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support  System ̶ Embedded voltage regulator for single supply operation ̶ Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation ̶ Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with failure detection and optional low-power 32.768 kHz for RTC or device clock ̶ RTC with Gregorian and Persian calendar mode, waveform generation in low-power modes ̶ RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency inaccuracy ̶ High-precision 8/12 MHz factory-trimmed internal RC oscillator with 4 MHz default frequency for device startup, in-application trimming access for frequency adjustment ̶ Slow clock internal RC oscillator as permanent low-power mode device clock ̶ Two PLLs up to 240 MHz for device clock and for USB ̶ Temperature sensor ̶ Low-power tamper detection on two inputs, anti-tampering by immediate clear of general-purpose backup registers (GPBR) ̶ Up to 22 Peripheral DMA (PDC) channels  Low-power Modes ̶ Sleep, Wait and Backup modes; consumption down to 1 µA in Backup mode  Peripherals ̶ USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints, on-chip transceiver ̶ Up to two USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode ̶ Two 2-wire UARTs ̶ Up to two 2-Wire Interface modules (I2C-compatible), one SPI, one Serial Synchronous Controller (I2S), one high-speed Multimedia Card Interface (SDIO/SD Card/MMC) ̶ Two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature decoder logic and 2-bit Gray up/down counter for stepper motor ̶ 4-channel 16-bit PWM with complementary output, fault input, 12-bit dead time generator counter for motor control ̶ 32-bit Real-time Timer and RTC with calendar, alarm and 32 kHz trimming features ̶ 256-bit General Purpose Backup Registers (GPBR) ̶ Up to 16-channel, 1Msps ADC with differential input mode and programmable gain stage and auto calibration ̶ One 2-channel 12-bit 1Msps DAC ̶ One Analog Comparator with flexible input selection, selectable input hysteresis ̶ 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) for data integrity check of off-/on-chip memories ̶ Register Write Protection SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15  I/O ̶ Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and ondie series resistor termination ̶ Three 32-bit Parallel Input/Output Controllers, Peripheral DMA-assisted Parallel Capture mode  Packages ̶ 100-lead packages ̶  LQFP – 14 x 14 mm, pitch 0.5 mm  TFBGA – 9 x 9 mm, pitch 0.8 mm  VFBGA – 7 x 7 mm, pitch 0.65 mm ̶ 64-lead packages  LQFP – 10 x 10 mm, pitch 0.5 mm  QFN – 9 x 9 mm, pitch 0.5 mm  WLCSP – 4.42 x 4.72 mm, pitch 0.4 mm (SAM4SD32/SAM4SD16)  WLCSP – 4.42 x 3.42 mm, pitch 0.4 mm (SAM4S16/S8)  WLCSP – 3.32 x 3.32 mm, pitch 0.4 mm (SAM4S4/S2) 48-lead packages  LQFP – 7 x 7 mm, pitch 0.5 mm  QFN – 7 x 7 mm, pitch 0.5 mm SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 3 Safety Features Highlight  4 Flash ̶ Built-in ECC (hamming), single error correction ̶ Security bit and lock bits SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1. Configuration Summary The SAM4S series devices differ in memory size, package and features. Table 1-1 and Table 1-2 summarize the configurations of the device family. Table 1-1. Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices Feature SAM4SD32C Flash SAM4SD32B SAM4SD16C SAM4SD16B 2 x 1024 Kbytes 2 x 1024 Kbytes 2 x 512 Kbytes 2 x 512 Kbytes SRAM SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B 1024 Kbytes 1024 Kbytes 1024 Kbytes 1024 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 128 Kbytes 128 Kbytes HCACHE 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes – – Package LQFP100 TFBGA100 VFBGA100 LQFP64 QFN64 WLCSP64 LQFP100 TFBGA100 VFBGA100 LQFP64 QFN64 WLCSP64 LQFP100 TFBGA100 VFBGA100 LQFP64 QFN64 LQFP100 TFBGA100 VFBGA100 LQFP64 QFN64 WLCSP64 79 47 79 47 79 47 79 47 8-bit data, 4 chip selects, 24-bit address – 8-bit data, 4 chip selects, 24-bit address – 8-bit data, 4 chip selects, 24-bit address – 8-bit data, 4 chip selects, 24-bit address – 12-bit ADC 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 12-bit DAC 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. Timer Counter Channels 6 6(2) 6 6(2) 6 6(2) 6 6(2) PDC Channels 22 22 22 22 22 22 22 22 Number of PIOs External Bus Interface USART/UART 2/2 HSMCI (3) 1 port, 4 bits Table 1-2. (3) 2/2 1 port, 4 bits 2/2 (3) 1 port, 4 bits 2/2 (3) 1 port, 4 bits 2/2 (3) 2/2 (3) 2/2 (3) 1 port, 4 bits 1 port, 4 bits 1 port, 4 bits 2/2(3) 1 port, 4 bits Configuration Summary for SAM4S8/S4/S2 Devices Feature SAM4S8C SAM4S8B SAM4S4C SAM4S4B SAM4S4A SAM4S2C SAM4S2B SAM4S2A Flash 512 Kbytes 512 Kbytes 256 Kbytes 256 Kbytes 256 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes SRAM 128 Kbytes 128 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes HCACHE – – – – – – – – Package LQFP100 TFBGA100 VFBGA100 LQFP64 QFN64 WLCSP64 LQFP100 TFBGA100 VFBGA100 LQFP64 QFN64 WLCSP64 LQFP48 QFN48 LQFP100 TFBGA100 VFBGA100 LQFP64 QFN64 WLCSP64 LQFP48 QFN48 79 47 79 47 34 79 47 34 8-bit data, 4 chip selects, 24-bit address – 8-bit data, 4 chip selects, 24-bit address – – 8-bit data, 4 chip selects, 24-bit address – – 12-bit ADC 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 8 ch. 16 ch.(1) 16 ch.(1) 8 ch 12-bit DAC 2 ch. 2 ch. 2 ch. 2 ch. – 2 ch. 2 ch. – Timer Counter Channels 6 6(2) 6 6(2) 6(2) 6 6(2) 6(2) PDC Channels 22 22 22 22 22 22 22 22 Number of PIOs External Bus Interface USART/UART HSMCI Notes: 2/2 (3) 1 port, 4 bits 2/2 (3) 1 port, 4 bits 2/2 (3) 1 port, 4 bits 2/2 (3) 1 port, 4 bits 2/1 – 2/2 (3) 1 port, 4 bits 2/2 (3) 1 port, 4 bits 2/1 – 1. One channel is reserved for internal temperature sensor. 2. Three TC channels are reserved for internal use. 3. Full modem support on USART1. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 5 Block Diagram SAM4SD32/SD16/SA16 100-pin Version Block Diagram TD VD TST O D D IO U T I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-1. VD 2. Voltage Regulator PCK[2:0] PLLA PLLB Power Management Controller JTAG and Serial Wire RC Osc 4/8/12 MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3–20 MHz Oscillator XOUT ERASE Supply Controller WKUP[15:0] Backup XIN32 XOUT32 DSP MPU 32K Cryst Osc I S 32K typ. RC Osc VDDIO VDDCORE VDDPLL Power-on Reset 256-bit GPBR RTCOUT0 RTCOUT1 Real-time Clock Real-time Timer Watchdog Timer Supply Monitor Flash Unique Identifier D CMCC (2 Kbyte Cache) M Reset Controller NRST 24-bit SysTick Counter NVIC Tamper Detection User Signature Flash M S 2*1024/2*512/1024 Kbytes 4-layer AHB Bus Matrix fMAX 120 MHz S 160 Kbytes S M SRAM ROM S S 16 Kbytes PIOA/PIOB/PIOC AHB/APB Bridge System Controller External Bus Interface PDC NAND Flash Logic TWI0 TWCK1 TWD1 TWI1 URXD0 UTXD0 UART0 URXD1 UTXD1 UART1 PDC Static Memory Controller PDC PDC 2668 bytes FIFO USB 2.0 Full-speed PDC PDC High-speed SCK0 TXD0 RXD0 RTS0 CTS0 PDC MCI USART0 PDC SPI SCK1 TXD1 RXD1 RTS1 CTS1 DTR1 DSR1 DCD1 RI1 PDC PDC USART1 PIODC[7:0] PIODCCLK PIODCEN[2:1] SSC DDP DDM MCCK MCCDA MCDA[3:0] MISO MOSI SPCK NPCS[3:0] TD RD TK RK TF RF CRCCU PDC PIO Timer Counter 0 TC[0..2] PDC AD[14:0] ADTRG TCLK[2:0] TIOA[2:0] TIOB[2:0] ADC PDC DAC[1:0] DATRG DAC ADC DAC Temp. Sensor ADVREF Analog Comparator SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Event System Timer Counter 1 Temp Sensor ADVREF 6 Transceiver TWCK0 TWD0 D[7:0] A[23:0] A21/NANDALE A22/NANDCLE NANDOE NANDWE NWAIT NCS[3:0] NRD NWE TC[3..5] PDC PWM TCLK[5:3] TIOA[5:3] TIOB[5:3] PWMH[3:0] PWML[3:0] PWMFI0 SAM4SD32/SD16/SA16 64-pin Version Block Diagram TST U O D VD VD D IO T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-2. Voltage Regulator PCK[2:0] PLLA PLLB Power Management Controller JTAG and Serial Wire RC Osc 4/8/12 MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3–20 MHz Oscillator XOUT ERASE Supply Controller WKUP[15:0] Backup XIN32 XOUT32 DSP Tamper Detection MPU 32K Cryst Osc I S 32K typ. RC Osc VDDIO VDDCORE VDDPLL Power-on Reset 256-bit GPBR RTCOUT0 RTCOUT1 Real-time Clock Real-time Timer Watchdog Timer Supply Monitor Flash Unique Identifier D CMCC (2 Kbyte Cache) M Reset Controller NRST 24-bit SysTick Counter NVIC User Signature Flash M S 2*1024/2*512/1024 Kbytes 4-layer AHB Bus Matrix fMAX 120 MHz S 160 Kbytes S M AHB/APB Bridge PDC SRAM ROM S S 16 Kbytes System Controller TWCK0 TWD0 TWI0 TWCK1 TWD1 TWI1 URXD0 UTXD0 UART0 PDC 2668 bytes FIFO USB 2.0 Full-speed PDC UART1 SCK0 TXD0 RXD0 RTS0 CTS0 MCI PDC PDC PDC USART0 SCK1 TXD1 RXD1 RTS1 CTS1 DTR1 DSR1 DCD1 RI1 DDP DDM PDC PDC High-speed URXD1 UTXD1 Transceiver PIOA/PIOB/PIOC SPI MCCK MCCDA MCDA[3:0] MISO MOSI SPCK NPCS[3:0] PDC PDC SSC USART1 TD RD TK RK TF RF CRCCU PIODC[7:0] PIODCCLK PIODCEN[2:1] PDC PIO Timer Counter 0 TC[0..2] ADC Temp Sensor ADVREF PDC DAC[1:0] DATRG DAC Event System PDC AD[9:0] ADTRG Timer Counter 1 TC[3..5] PDC PWM ADC DAC Temp Sensor ADVREF TCLK[2:0] TIOA[2:0] TIOB[2:0] PWMH[3:0] PWML[3:0] PWMFI0 Analog Comparator SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 7 PLLA PLLB Power Management Controller U JTAG and Serial Wire RC Osc 4/8/12 MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3–20 MHz Oscillator XOUT ERASE Supply Controller WKUP[15:0] Backup XIN32 XOUT32 DSP 24-bit SysTick Counter NVIC Tamper Detection MPU Flash Unique Identifier 32K Cryst Osc 32K typ. RC Osc RTCOUT0 RTCOUT1 D Voltage Regulator PCK[2:0] VDDIO VDDCORE VDDPLL O IO D TST VD VD TD TD T O TM S TC /SW K/ D SW IO JT C LK AG SE L SAM4S16/S8 100-pin Version Block Diagram I Figure 2-3. Power-on Reset 256-bit GPBR Real-time Clock Real-time Timer Watchdog Timer I/D S M M 4-layer AHB Bus Matrix fMAX 120 MHz Reset Controller NRST Supply Monitor User Signature S M Flash S 1024/512 Kbytes S 128 Kbytes SRAM ROM S S 16 Kbytes PIOA/PIOB/PIOC AHB/APB Bridge System Controller External Bus Interface PDC NAND Flash Logic TWI0 TWCK1 TWD1 TWI1 URXD0 UTXD0 UART0 URXD1 UTXD1 UART1 PDC Static Memory Controller PDC PDC 2668 bytes FIFO USB 2.0 Full-speed PDC PDC High-speed SCK0 TXD0 RXD0 RTS0 CTS0 PDC MCI USART0 PDC SPI SCK1 TXD1 RXD1 RTS1 CTS1 DTR1 DSR1 DCD1 RI1 PDC PDC USART1 PIODC[7:0] PIODCCLK PIODCEN[2:1] SSC DDP DDM MCCK MCCDA MCDA[3:0] MISO MOSI SPCK NPCS[3:0] TD RD TK RK TF RF CRCCU PDC PIO Timer Counter 0 TC[0..2] PDC AD[14:0] ADTRG TCLK[2:0] TIOA[2:0] TIOB[2:0] ADC PDC DAC[1:0] DATRG DAC ADC DAC Temp Sensor ADVREF Analog Comparator SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Event System Timer Counter 1 Temp Sensor ADVREF 8 Transceiver TWCK0 TWD0 D[7:0] A[23:0] A21/NANDALE A22/NANDCLE NANDOE NANDWE NWAIT NCS[3:0] NRD NWE TC[3..5] PDC PWM TCLK[5:3] TIOA[5:3] TIOB[5:3] PWMH[3:0] PWML[3:0] PWMFI0 SAM4S16/S8 64-pin Version Block Diagram TST PLLA Power Management Controller PLLB U O JTAG and Serial Wire RC Osc 4/8/12 MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3–20 MHz Oscillator XOUT ERASE Supply Controller WKUP[15:0] Backup DSP 24-bit SysTick Counter NVIC Tamper Detection MPU 32K Cryst Osc XIN32 XOUT32 Flash Unique Identifier 32K typ. RC Osc RTCOUT0 RTCOUT1 D Voltage Regulator PCK[2:0] VDDIO VDDCORE VDDPLL VD VD D IO T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-4. Power-on Reset 256-bit GPBR Real-time Clock Real-time Timer Watchdog Timer I/D S M M 4-layer AHB Bus Matrix fMAX 120 MHz Reset Controller NRST Supply Monitor User Signature S M AHB/APB Bridge PDC Flash S 1024/512 Kbytes S 128 Kbytes SRAM ROM S S 16 Kbytes System Controller TWCK0 TWD0 TWI0 TWCK1 TWD1 TWI1 URXD0 UTXD0 UART0 PDC 2668 bytes FIFO PDC USB 2.0 Full-speed UART1 SCK0 TXD0 RXD0 RTS0 CTS0 MCI PDC PDC PDC USART0 SCK1 TXD1 RXD1 RTS1 CTS1 DTR1 DSR1 DCD1 RI1 DDP DDM PDC PDC High-speed URXD1 UTXD1 Transceiver PIOA/PIOB SPI MCCK MCCDA MCDA[3:0] MISO MOSI SPCK NPCS[3:0] PDC PDC SSC USART1 PIODC[7:0] PIODCCLK PIODCEN[2:1] CRCCU PDC PIO Timer Counter 0 TC[0..2] ADC Temp Sensor ADVREF PDC DAC[1:0] DATRG DAC ADC DAC Temp Sensor ADVREF Event System PDC AD[9:0] ADTRG TD RD TK RK TF RF TCLK[2:0] TIOA[2:0] TIOB[2:0] Timer Counter 1 TC[3..5] PDC PWM PWMH[3:0] PWML[3:0] PWMFI0 Analog Comparator SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 9 SAM4S4/S2 100-pin Version Block Diagram TST PLLA PLLB Power Management Controller U O JTAG and Serial Wire RC Osc 4/8/12 MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3–20 MHz Oscillator XOUT ERASE Supply Controller WKUP[15:0] Backup XIN32 XOUT32 DSP 24-bit SysTick Counter NVIC Tamper Detection MPU Flash Unique Identifier 32K Cryst Osc 32K typ. RC Osc RTCOUT0 RTCOUT1 D Voltage Regulator PCK[2:0] VDDIO VDDCORE VDDPLL VD VD D IO T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-5. Power-on Reset 256-bit GPBR Real-time Clock Real-time Timer Watchdog Timer I/D S M M 4-layer AHB Bus Matrix fMAX 120 MHz Reset Controller NRST Supply Monitor User Signature S M Flash S 256/128 Kbytes S 64 Kbytes SRAM ROM S S 16 Kbytes PIOA/PIOB/PIOC AHB/APB Bridge System Controller External Bus Interface PDC NAND Flash Logic TWI0 TWCK1 TWD1 TWI1 URXD0 UTXD0 UART0 URXD1 UTXD1 UART1 PDC Static Memory Controller PDC PDC 2668 bytes FIFO USB 2.0 Full-speed PDC PDC High-speed SCK0 TXD0 RXD0 RTS0 CTS0 PDC MCI USART0 PDC SPI SCK1 TXD1 RXD1 RTS1 CTS1 DTR1 DSR1 DCD1 RI1 PDC PDC USART1 PIODC[7:0] PIODCCLK PIODCEN[2:1] SSC DDP DDM MCCK MCCDA MCDA[3:0] MISO MOSI SPCK NPCS[3:0] TD RD TK RK TF RF CRCCU PDC PIO Timer Counter 0 TC[0..2] PDC AD[14:0] ADTRG TCLK[2:0] TIOA[2:0] TIOB[2:0] ADC PDC DAC[1:0] DATRG DAC ADC DAC Temp Sensor ADVREF Analog Comparator SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Event System Timer Counter 1 Temp Sensor ADVREF 10 Transceiver TWCK0 TWD0 D[7:0] A[23:0] A21/NANDALE A22/NANDCLE NANDOE NANDWE NWAIT NCS[3:0] NRD NWE TC[3..5] PDC PWM TCLK[5:3] TIOA[5:3] TIOB[5:3] PWMH[3:0] PWML[3:0] PWMFI0 SAM4S4/S2 64-pin Version Block Diagram TST D VD VD D O IO U T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-6. Voltage Regulator PCK[2:0] PLLA Power Management Controller PLLB JTAG and Serial Wire RC Osc 4/8/12 MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3–20 MHz Oscillator XOUT ERASE WKUP[15:0] Supply Controller Backup XIN32 XOUT32 DSP 24-bit SysTick Counter NVIC Tamper Detection MPU Flash Unique Identifier 32K Cryst Osc 32K typ. RC Osc VDDIO VDDCORE VDDPLL Power-on Reset 256-bit GPBR RTCOUT0 RTCOUT1 Real-time Clock Real-time Timer Watchdog Timer I/D S M M 4-layer AHB Bus Matrix fMAX 120 MHz Reset Controller NRST Supply Monitor User Signature S M AHB/APB Bridge PDC Flash S 256/128 Kbytes S 64 Kbytes SRAM ROM S 16 Kbytes System Controller TWCK0 TWD0 TWI0 TWCK1 TWD1 TWI1 URXD0 UTXD0 UART0 PDC 2668 bytes FIFO PDC USB 2.0 Full-speed UART1 SCK0 TXD0 RXD0 RTS0 CTS0 MCI PDC PDC PDC USART0 SCK1 TXD1 RXD1 RTS1 CTS1 DTR1 DSR1 DCD1 RI1 DDP DDM PDC PDC High-speed URXD1 UTXD1 Transceiver PIOA/PIOB SPI MCCK MCCDA MCDA[3:0] MISO MOSI SPCK NPCS[3:0] PDC PDC SSC USART1 PIODC[7:0] PIODCCLK PIODCEN[2:1] CRCCU PDC PIO Timer Counter 0 TC[0..2] PDC AD[9:0] ADTRG ADC PDC DAC Event System Temp Sensor ADC DAC Temp Sensor ADVREF TCLK[2:0] TIOA[2:0] TIOB[2:0] Timer Counter 1 ADVREF DAC[1:0] DATRG TD RD TK RK TF RF TC[3..5] PDC PWM PWMH[3:0] PWML[3:0] PWMFI0 Analog Comparator SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 11 SAM4S4/S2 48-pin Version Block Diagram TST PLLA Power Management Controller PLLB U O JTAG and Serial Wire RC Osc 4/8/12 MHz XIN In-Circuit Emulator Cortex-M4 Processor fMAX 120 MHz 3–20 MHz Oscillator XOUT ERASE WKUP[15:0] Supply Controller Backup XIN32 XOUT32 DSP 24-bit SysTick Counter NVIC Tamper Detection MPU Flash Unique Identifier 32K Cryst Osc 32K typ. RC Osc RTCOUT0 RTCOUT1 D Voltage Regulator PCK[2:0] VDDIO VDDCORE VDDPLL VD VD D IO T TD I TD O TM S TC /SW K/ D SW IO JT C LK AG SE L Figure 2-7. Power-on Reset 256-bit GPBR Real-time Clock Real-time Timer Watchdog Timer I/D S M M 4-layer AHB Bus Matrix fMAX 120 MHz Reset Controller NRST Supply Monitor User Signature S M AHB/APB Bridge PDC Flash S 256/128 Kbytes S 64 Kbytes SRAM ROM S 16 Kbytes System Controller TWCK0 TWD0 TWI0 TWCK1 TWD1 TWI1 URXD0 UTXD0 UART0 2668 bytes FIFO PDC USB 2.0 Full-speed PDC PDC SPI PDC PDC URXD1 UTXD1 UART1 SCK0 TXD0 RXD0 RTS0 CTS0 USART0 AD[7:0] ADTRG ADC SSC PDC Timer Counter 0 PDC Temp Sensor ADC DAC Temp Sensor ADVREF Analog Comparator SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Event System TC[0..2] ADVREF 12 PDC Transceiver PIOA/PIOB DDP DDM MISO MOSI SPCK NPCS[3:0] TD RD TK RK TF RF TCLK[2:0] TIOA[2:0] TIOB[2:0] Timer Counter 1 TC[3..5] PDC PWM PWMH[3:0] PWML[3:0] PWMFI0 3. Signal Description Table 3-1 gives details on signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage Reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power – – 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power – – 1.62V to 3.6V(4) VDDOUT Voltage Regulator Output Power – – 1.2V output VDDPLL Oscillator and PLL Power Supply Power – – 1.08V to 1.32V VDDCORE Power the core, the embedded memories and the peripherals Power – – 1.08V to 1.32V GND Ground Ground – – – Clocks, Oscillators and PLLs XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output Input – Reset State: Output – - PIO Input Input – - Internal Pull-up disabled Output – - Schmitt Trigger enabled(1) VDDIO Reset State: PCK0–PCK2 Programmable Clock Output Output - PIO Input – - Internal Pull-up enabled - Schmitt Trigger enabled(1) Real Time Clock - RTC RTCOUT0 Programmable RTC waveform output Output Reset State: – VDDIO RTCOUT1 Programmable RTC waveform output Output – - PIO Input - Internal Pull-up enabled - Schmitt Trigger enabled(1) Serial Wire/JTAG Debug Port - SWJ-DP TCK/SWCLK Test Clock/Serial Wire Clock Input – TDI Test Data In Input – TDO/TRACESWO Test Data Out / Trace Asynchronous Data Out Output – TMS/SWDIO Test Mode Select /Serial Wire Input/Output JTAGSEL JTAG Selection Reset State: - SWJ-DP Mode VDDIO Input / I/O – Input High - Internal pull-up disabled(5) - Schmitt Trigger enabled(1) Permanent Internal pull-down SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 13 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage Reference Comments Flash Memory Reset State: Flash and NVM Configuration Bits Erase Command ERASE - Erase Input Input High VDDIO - Internal pull-down enabled - Schmitt Trigger enabled(1) Reset/Test NRST Synchronous Microcontroller Reset I/O Permanent Internal Low pull-up VDDIO TST Test Select Input Permanent Internal – pull-down Wake-up WKUP[15:0] Wake-up Inputs Input – VDDIO – Universal Asynchronous Receiver Transceiver - UARTx URXDx UART Receive Data Input – – – UTXDx UART Transmit Data Output – – – PIO Controller - PIOA - PIOB - PIOC PA0–PA31 Parallel IO Controller A I/O – PB0–PB14 Parallel IO Controller B I/O – PC0–PC31 Parallel IO Controller C I/O – Reset State: VDDIO - PIO or System IOs(2) - Internal pull-up enabled - Schmitt Trigger enabled(1) PIO Controller - Parallel Capture Mode PIODC0–PIODC7 Parallel Capture Mode Data Input – PIODCCLK Parallel Capture Mode Clock Input – PIODCEN1–2 Parallel Capture Mode Enable Input – VDDIO – External Bus Interface D0–D7 Data Bus A0–A23 Address Bus NWAIT External Wait Signal I/O – – – Output – – – Input Low – – Static Memory Controller - SMC NCS0–NCS3 Chip Select Lines Output Low – – NRD Read Signal Output Low – – NWE Write Enable Output Low – – NAND Flash Logic NANDOE NAND Flash Output Enable Output Low – – NANDWE NAND Flash Write Enable Output Low – – 14 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage Reference Comments High Speed Multimedia Card Interface - HSMCI MCCK Multimedia Card Clock Output – – – MCCDA Multimedia Card Slot A Command I/O – – – MCDA0–MCDA3 Multimedia Card Slot A Data I/O – – – Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock I/O – – – TXDx USARTx Transmit Data I/O – – – RXDx USARTx Receive Data Input – – – RTSx USARTx Request To Send Output – – – CTSx USARTx Clear To Send Input – – – DTR1 USART1 Data Terminal Ready Output – – – DSR1 USART1 Data Set Ready Input – – – DCD1 USART1 Data Carrier Detect Output – – – RI1 USART1 Ring Indicator Input – – – Synchronous Serial Controller - SSC TD SSC Transmit Data Output – – – RD SSC Receive Data Input – – – TK SSC Transmit Clock I/O – – – RK SSC Receive Clock I/O – – – TF SSC Transmit Frame Sync I/O – – – RF SSC Receive Frame Sync I/O – – – Input – – – Timer/Counter - TC TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A I/O – – – TIOBx TC Channel x I/O Line B I/O – – – – – Pulse Width Modulation Controller - PWMC PWMHx PWM Waveform Output High for channel x PWMLx PWM Waveform Output Low for channel x PWMFI0–2 PWM Fault Input Output – Output – – Only output in complementary mode when dead time insertion is enabled. Input – – PWMFI1 and PWMFI2 on SAM4S4/S2 only SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 15 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage Reference Comments Serial Peripheral Interface - SPI MISO Master In Slave Out I/O – – – MOSI Master Out Slave In I/O – – – SPCK SPI Serial Clock I/O – – – SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low – – SPI_NPCS1–SPI_NPCS3 SPI Peripheral Chip Select Output Low – – Two-Wire Interface - TWI TWDx TWIx Two-wire Serial Data I/O – – – TWCKx TWIx Two-wire Serial Clock I/O – – – Analog – – – Analog ADC, DAC and Analog Comparator Reference ADVREF 12-bit Analog-to-Digital Converter - ADC AD0–AD14 Analog Inputs Analog, Digital – – – ADTRG ADC Trigger Input – VDDIO – 12-bit Digital-to-Analog Converter - DAC DAC0–DAC1 Analog output DACTRG DAC Trigger Analog, Digital – – – Input – VDDIO – VDDIO – Fast Flash Programming Interface - FFPI PGMEN0-PGMEN2 Programming Enabling Input – PGMM0–PGMM3 Programming Mode Input – – PGMD0–PGMD15 Programming Data I/O – – PGMRDY Programming Ready Output High – PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low – PGMCK Programming Clock Input – – PGMNCMD Programming Command Input Low – VDDIO – USB Full Speed Device DDM USB Full Speed Data - DDP Note: 16 USB Full Speed Data + 1. 2. 3. 4. 5. Reset State: Analog, Digital – VDDIO - USB Mode - Internal Pull-down(3) Schmitt triggers can be disabled through PIO registers. Some PIO lines are shared with system I/Os. Refer to USB section of the product Electrical Characteristics for information on pull-down value in USB mode. See “Typical Powering Schematics” section for restrictions on voltage range of analog cells. TDO pin is set in input mode when the Cortex-M4 processor is not in debug mode. Thus the internal pull-up corresponding to this PIO line must be enabled to avoid current consumption due to floating input SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 4. Package and Pinout SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 48-, 64- and 100-pin versions, SAM4N and SAM7S legacy products in 64-pin versions. 4.1 100-lead Packages and Pinouts Refer to Table 1-1 and Table 1-2 for the overview of devices available in 100-lead packages. 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 4.1.2 25 100-ball TFBGA Package Outline The 100-ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm. Figure 4-2 shows the orientation of the 100-ball TFBGA package. Figure 4-2. Orientation of the 100-ball TFBGA Package TOP VIEW 10 9 8 7 6 5 4 3 2 1 BALL A1 A B C D E F G H J K SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 17 4.1.3 100-ball VFBGA Package Outline Figure 4-3. 18 Orientation of the 100-ball VFBGA Package SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 4.1.4 100-lead LQFP Pinout Table 4-1. SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-lead LQFP Pinout 1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/PB5 2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL 3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18 4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6 5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19 6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31 7 PB2/AD6 32 PC6 57 PA27/PGMD15 82 PC20 8 PC31 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7 9 PB3/AD7 34 PA24/PGMD12 59 PA28 84 PC21 10 VDDIN 35 PC5 60 NRST 85 VDDCORE 11 VDDOUT 36 VDDCORE 61 TST 86 PC22 12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12 13 PC26 38 PA25/PGMD13 63 PA29 88 DDM/PB10 14 PA18/PGMD6/AD1 39 PA26/PGMD14 64 PA30 89 DDP/PB11 15 PA21/PGMD9/AD8 40 PC3 65 PC10 90 PC23 16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO 17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24 18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0 19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25 20 PA22/PGMD10/AD9 45 GND 70 GND 95 GND 21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT 22 PA23/PGMD11 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN 23 PC12/AD12 48 PA8/XOUT32/PGMM0 73 PC16 98 VDDIO 24 PA20/PGMD8/AD3 49 PA7/XIN32/ PGMNVALID 74 PA0/PGMEN0 99 PB14/DAC1 25 PC0 50 VDDIO 75 PC17 100 VDDPLL SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 19 4.1.5 100-ball TFBGA Pinout Table 4-2. SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-ball TFBGA Pinout A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1 PA18/PGMD6/AD1 H6 PC4 A2 PC29/AD13 C7 PC16 F2 PC26 H7 PA11/PGMM3 A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1 A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4 A6 PB13/DAC0 D1 PB3/AD7 F6 PA27/PGMD15 J1 PC15/AD11 A7 DDP/PB11 D2 PB0/AD4 F7 PC8 J2 PC0 A8 DDM/PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4 A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6 A10 JTAGSEL D5 GND F10 PC9 J5 PA24/PGMD12 B1 PC30/AD14 D6 GND G1 PA21/PGMD9/AD8 J6 PA25/PGMD13 B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10/PGMM2 B3 GNDANA D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND B4 PB14/DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO B6 PC20 E1 PA17/PGMD5/AD0 G6 PA26/PGMD14 K1 PA22/PGMD10/AD9 B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10 B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12 B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/PGMD8/AD3 B10 TDO/TRACESWO/PB5 E5 GND G10 PA5/PGMRDY K5 PC5 C1 PB2/AD6 E6 NRST H1 PA19/PGMD7/AD2 K6 PC3 C2 VDDPLL E7 PA29 H2 PA23/PGMD11 K7 PC2 C3 PC25 E8 PA30 H3 PC7 K8 PA9/PGMM1 C4 PC23 E9 PC10 H4 PA14/PGMD2 K9 PA8/XOUT32/PGMM0 C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10 PA7/XIN32/ PGMNVALID 20 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 4.1.6 100-ball VFBGA Pinout Table 4-3. SAM4SD32/SD16/SA16/S16/S8/S4/S2 100-ball VFBGA Pinout A1 ADVREF C6 PC9 F1 VDDOUT H6 PA12/PGMD0 A2 VDDPLL C7 TMS/SWDIO/PB6 F2 PA18/PGMD6/AD1 H7 PA9/PGMM1 A3 PB9/PGMCK/XIN C8 PA1/PGMEN1 F3 PA17/PGMD5/AD0 H8 VDDCORE A4 PB8/XOUT C9 PA0/PGMEN0 F4 GND H9 PA6/PGMNOE A5 JTAGSEL C10 PC16 F5 GND H10 PA5/PGMRDY A6 DDP/PB11 D1 PB1/AD5 F6 PC26 J1 PA20/AD3/PGMD8 A7 DDM/PB10 D2 PC30/AD14 F7 PA4/PGMNCMD J2 PC12/AD12 A8 PC20 D3 PC31 F8 PA28 J3 PA16/PGMD4 A9 PC19 D4 PC22 F9 TST J4 PC6 A10 TDO/TRACESWO/PB5 D5 PC5 F10 PC8 J5 PA24/PGMD12 B1 GNDANA D6 PA29 G1 PC15/AD11 J6 PA25/PGMD13 B2 PC25 D7 PA30 G2 PA19/PGMD7/AD2 J7 PA11/PGMM3 B3 PB14/DAC1 D8 GND G3 PA21/AD8/PGMD9 J8 VDDCORE B4 PB13/DAC0 D9 PC14 G4 PA15/PGMD3 J9 VDDCORE B5 PC23 D10 PC11 G5 PC3 J10 TDI/PB4 B6 PC21 E1 VDDIN G6 PA10/PGMM2 K1 PA23/PGMD11 B7 TCK/SWCLK/PB7 E2 PB3/AD7 G7 PC1 K2 PC0 B8 PA31 E3 PB2/AD6 G8 PC28 K3 PC7 B9 PC18 E4 GND G9 NRST K4 PA13/PGMD1 B10 PC17 E5 GND G10 PA27/PGMD15 K5 PA26/PGMD14 C1 PB0/AD4 E6 GND H1 PC13/AD10 K6 PC2 C2 PC29/AD13 E7 VDDIO H2 PA22/AD9/PGMD10 K7 VDDIO C3 PC24 E8 PC10 H3 PC27 K8 VDDIO C4 ERASE/PB12 E9 PA2/PGMEN2 H4 PA14/PGMD2 K9 PA8/XOUT32/PGMM0 C5 VDDCORE E10 PA3 H5 PC4 K10 PA7/XIN32/ PGMNVALID SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 21 4.2 64-lead Packages and Pinouts Refer to Table 1-1 and Table 1-2 for the overview of devices available in 64-lead packages. 4.2.1 64-lead LQFP Package Outline Figure 4-4. Orientation of the 64-lead LQFP Package 33 48 49 32 64 17 16 1 4.2.2 64-lead QFN Package Outline Figure 4-5. Orientation of the 64-lead QFN Package 64 1 48 16 33 17 4.2.3 TOP VIEW 64-ball WLCSP Package Outline Figure 4-6. 22 49 Orientation of the 64-ball WLCSP Package SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 32 4.2.4 64-lead LQFP and QFN Pinout Table 4-4. 64-pin SAM4SD32/SD16/SA16/S16/S8/S4/S2 Pinout 1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5 2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL 3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6 4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31 5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7 6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE 7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12 8 VDDOUT 24 VDDCORE 40 TST 56 DDM/PB10 9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 DDP/PB11 10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO 11 PA21/PGMD9/AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0 12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND 13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8 14 PA22/PGMD10/AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9 15 PA23/PGMD11 31 PA8/XOUT32/PGMM0 47 PA1/PGMEN1 63 PB14/DAC1 16 PA20/PGMD8/AD3 32 PA7/XIN32/PGMNVALID 48 PA0/PGMEN0 64 VDDPLL Note: The bottom pad of the QFN package must be connected to ground. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 23 4.2.5 64-ball WLCSP Pinout Table 4-5. SAM4SD32/S32/SD16/S16/S8 64-ball WLCSP Pinout A1 PA31 C1 GND E1 PA29 G1 PA5 A2 PB7 C2 PA1 E2 TST G2 PA6 A3 VDDCORE C3 PA0 E3 NRST G3 PA9 A4 PB10 C4 PB12 E4 PA28 G4 PA11 A5 VDDIO C5 ADVREF E5 PA25 G5 VDDCORE A6 GND C6 PB3 E6 PA23 G6 PA14 A7 PB9 C7 PB1 E7 PA18 G7 PA20 A8 PB14 C8 PB0 E8 VDDIN G8 PA19 B1 PB5 D1 VDDIO F1 PA27 H1 PA7 B2 JTAGSEL D2 PA3 F2 VDDCORE H2 PA8 B3 PB6 D3 PA30 F3 PA4 H3 PA10 B4 PB11 D4 PA2 F4 PB4 H4 PA12 B5 PB13 D5 PA13 F5 PA26 H5 PA24 B6 VDDPLL D6 PA21 F6 PA16 H6 PA15 B7 PB8 D7 PA17 F7 PA22 H7 VDDIO B8 GND D8 PB2 F8 VDDOUT H8 GND Table 4-6. SAM4S4/S2 64-ball WLCSP Pinout A1 PB5 C1 GND E1 PA3 G1 VDDCORE A2 PA31 C2 PA0 E2 PA30 G2 PA4 A3 VDDCORE C3 PB7 E3 PA29 G3 PA9 A4 VDDIO C4 PB12 E4 PA27 G4 PA11 A5 GND C5 PA10 E5 PA24 G5 PA25 A6 PB8 C6 PB0 E6 PA18 G6 PA14 A7 PB9 C7 PB2 E7 PA17 G7 VDDIO A8 ADVREF C8 PB1 E8 VDDIN G8 PA19 B1 PA1 D1 VDDIO F1 TST H1 PB4 B2 JTAGSEL D2 PA2 F2 NRST H2 PA7 B3 PB10 D3 PA28 F3 PA5 H3 PA8 B4 PB11 D4 PB6 F4 PA6 H4 PA12 B5 PB13 D5 PA26 F5 PA13 H5 VDDCORE B6 VDDPLL D6 PA23 F6 PA22 H6 PA15 B7 PB14 D7 PA16 F7 PA21 H7 GND B8 GNDANA D8 PB3 F8 VDDOUT H8 PA20 24 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 4.3 48-lead Packages and Pinouts Refer to Table 1-1 for the overview of devices available in 48-lead packages. 4.3.1 48-lead LQFP Package Outline Figure 4-7. 4.3.2 Orientation of the 48-lead LQFP Package 48-lead QFN Package Outline Figure 4-8. Orientation of the 48-lead QFN Package SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 25 4.3.3 48-lead LQFP and QFN Pinout Table 4-7. SAM4S4/S2 48-pin LQFP and QFN Pinout 1 ADVREF 13 VDDIO 25 TDI/PB4 37 TDO/TRACESWO/PB5 2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL 3 PB0/AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS/SWDIO/PB6 4 PB1/AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK/SWCLK/PB7 5 PB2/AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE 6 PB3/AD7 18 VDDCORE 30 TST 42 ERASE/PB12 7 VDDIN 19 PA12/PGMD0 31 PA3 43 DDM/PB10 8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 DDP/PB11 9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT/PB8 10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/PB9/PGMCK 11 PA19/PGMD7/AD2 23 PA8/XOUT32/PGMM0 35 PA1/PGMEN1 47 VDDIO 12 PA20/AD3 24 PA7/XIN32/PGMNVALID 36 PA0/PGMEN0 48 VDDPLL Note: The bottom pad of the QFN package must be connected to ground. 26 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 5. Power Considerations 5.1 Power Supplies The SAM4S has several types of power supply pins:  VDDCORE pins: Power the core, the first flash rail and the embedded memories and peripherals. Voltage ranges from 1.08 to 1.32 V.  VDDIO pins: Power the peripheral I/O lines (input/output buffers), the second Flash rail, USB transceiver, backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62 to 3.6 V.  VDDIN pin: Voltage regulator input, ADC, DAC and analog comparator power supply. Voltage ranges from 1.62 to 3.6 V.  VDDPLL pin: Powers the PLLA, PLLB, the fast RC and the 3 to 20 MHz oscillator. Voltage ranges from 1.08 to 1.32 V. 5.2 Power-up Considerations 5.2.1 VDDIO Versus VDDCORE VDDIO must always be higher than or equal to VDDCORE. VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached VDDCORE(min). The minimum slope for VDDCORE is defined by (VDDCORE(min) - VT+) / tRST. If VDDCORE rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 8.8 V/ms. If VDDCORE is powered by the internal regulator, all power-up considerations are met. Figure 5-1. VDDCORE and VDDIO Constraints at Startup Supply (V) VDDIO VDDIO(min) VDDCORE VDDCORE(min) VT+ tRST Time (t) Core supply POR output SLCK SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 27 5.2.2 VDDIO Versus VDDIN At power-up, VDDIO needs to reach 0.6 V before VDDIN reaches 1.0 V. VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5 V). 5.3 Voltage Regulator The SAM4S embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is designed to supply the internal core of SAM4S. It features two operating modes:  In Normal mode, the voltage regulator consumes less than 500 µA static current and draws 80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait mode quiescent current is only 5 µA.  In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT) is driven internally to GND. The default output voltage is 1.20 V and the start-up time to reach Normal mode is less than 300 µs. For adequate input and output power supply decoupling/bypassing, refer to Table 44-4 "1.2V Voltage Regulator Characteristics" in Section 44. “Electrical Characteristics”. 28 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 5.4 Typical Powering Schematics The SAM4S supports a 1.62–3.6 V single supply mode. The internal regulator input is connected to the source and its output feeds VDDCORE. Figure 5-2 below shows the power schematics. As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the user does not want to use the embedded voltage regulator, it can be disabled by software via the SUPC (note that this is different from Backup mode). Figure 5-2. Single Supply VDDIO Main Supply (1.62–3.6 V) USB Transceivers ADC, DAC, Analog Comp. VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Note: Restrictions: For USB, VDDIO needs to be greater than 3.0V. For ADC, DAC and Analog Comparator, VDDIN needs to be greater than 2.4V. Figure 5-3. Core Externally Supplied Main Supply (1.62–3.6 V) VDDIO USB Transceivers Can be the same supply ADC, DAC, Analog Comparator Supply (2.4–3.6 V) ADC, DAC, Analog Comp. VDDIN VDDOUT VDDCORE Supply (1.08–1.32V) Voltage Regulator VDDCORE VDDPLL Note: Restrictions: For USB, VDDIO needs to be greater than 3.0V. For ADC, DAC and Analog Comparator, VDDIN needs to be greater than 2.4V. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 29 Figure 5-4 provides an example of the powering scheme when using a backup battery. Since the PIO state is preserved when in Backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from a push button or any signal. See Section 5.7 “Wake-up Sources” for further details. Figure 5-4. Backup Battery Backup Battery VDDIO USB Transceivers + ADC, DAC, Analog Comp. VDDIN Main Supply IN OUT 3.3V LDO VDDOUT Voltage Regulator VDDCORE ON/OFF VDDPLL PIOx (Output) WKUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. Note: 5.5 Restrictions: For USB, VDDIO needs to be greater than 3.0V. For ADC, DAC and Analog Comparator, VDDIN needs to be greater than 2.4V. Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The Power Management Controller can be used to adapt the frequency and to disable the peripheral clocks. 5.6 Low-power Modes The SAM4S has the following low-power modes: Backup mode, Wait mode and Sleep mode. Note: The Wait For Event instruction (WFE) of the Cortex-M4 core can be used to enter any of the low-power modes, however, this may add complexity in the design of application state machines. This is due to the fact that the WFE instruction goes along with an event flag of the Cortex core (cannot be managed by the software application). The event flag can be set by interrupts, a debug event or an event signal from another processor. Since it is possible for an interrupt to occur just before the execution of WFE, WFE takes into account events that happened in the past. As a result, WFE prevents the device from entering Wait mode if an interrupt event has occurred. Atmel has made provision to avoid using the WFE instruction. The workarounds to ease application design are as follows: - For Backup mode, switch off the voltage regulator and configure the VROFF bit in the Supply Controller Control Register (SUPC_CR). - For Wait mode, configure the WAITMODE bit in the PMC Clock Generator Main Oscillator Register of the Power Management Controller (PMC) - For Sleep mode, use the Wait for Interrupt (WFI) instruction. Complete information is available in Table 5-1 “Low-power Mode Configuration Summary". 30 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 5.6.1 Backup Mode The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. Total current consumption is 1 µA typical (VDDIO = 1.8V at 25°C). The Supply Controller, zero-power power-on reset, RTT, RTC, backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. The SAM4S can be woke up from this mode using the pins WKUP0–15, the supply monitor (SM), the RTT or RTC wake-up event. Backup mode is entered by writing a 1 to the VROFF bit of the Supply Controller Control Register (SUPC_CR) (A key is needed to write the VROFF bit; refer to Section 18. “Supply Controller (SUPC)”.) and with the SLEEPDEEP bit in the Cortex-M4 System Control Register set to 1. (See the power management description in Section 12. “ARM Cortex-M4 Processor”). To enter Backup mode using the VROFF bit: 1. Write a 1 to the VROFF bit of SUPC_CR. To enter Backup mode using the WFE instruction: 1. Write a 1 to the SLEEPDEEP bit of the Cortex-M4 processor. 2. Execute the WFE instruction of the processor. In both cases, exit from Backup mode happens if one of the following enable wake-up events occurs: 5.6.2  Level transition, configurable debouncing on pins WKUPEN0–15  Supply Monitor alarm  RTC alarm  RTT alarm Wait Mode The purpose of Wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. Current consumption in Wait mode is typically 32 µA (total current consumption) if the internal voltage regulator is used. In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. From this mode, a fast start up is available. This mode is entered by setting the WAITMODE bit to 1 in the PMC Clock Generator Main Oscillator Register (CKGR_MOR) in conjunction with the Flash Low Power Mode field FLPM = 0 or FLPM = 1 in the PMC Fast Startup Mode Register (PMC_FSMR) or by the WFE instruction. The Cortex-M4 is able to handle external or internal events in order to wake-up the core. This is done by configuring the external lines WKUP0–15 as fast startup wake-up pins (refer to Section 5.8 “Fast Start-up”). RTC or RTT Alarm and USB wake-up events can be used to wake up the CPU. To enter Wait mode with WAITMODE bit: 1. Select the 4/8/12 MHz fast RC oscillator as Main Clock. 2. Set the FLPM field in the PMC_FSMR. 3. Set Flash wait state to 0. 4. Set the WAITMODE bit = 1 in CKGR_MOR. 5. Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 31 To enter Wait mode with WFE: 1. Select the 4/8/12 MHz fast RC oscillator as Main Clock. 2. Set the FLPM field in the PMC_FSMR. 3. Set Flash wait state to 0. 4. Set the LPM bit in the PMC_FSMR. 5. Execute the Wait-For-Event (WFE) instruction of the processor. In both cases, depending on the value of the field FLPM, the Flash enters three different modes:  FLPM = 0 in Standby mode (low consumption)  FLPM = 1 in Deep power-down mode (extra low consumption)  FLPM = 2 in Idle mode. Memory ready for Read access Table 5-1 summarizes the power consumption, wake-up time and system state in Wait mode. 5.6.3 Sleep Mode The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application dependent. This mode is entered via Wait for Interrupt (WFI) or WFE instructions with bit LPM = 0 in PMC_FSMR. The processor can be woken up from an interrupt if the WFI instruction of the Cortex-M4 is used or from an event if the WFE instruction is used. 5.6.4 Low-power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wakeup sources can be configured individually. Table 5-1 provides the configuration summary of the low-power modes. 32 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 5-1. Low-power Mode Configuration Summary SUPC, 32 kHz Osc., RTC, RTT, GPBR, POR (Backup Region) Mode Regulator Core Memory Peripherals Mode Entry VROFF = 1 Backup Mode ON OFF OFF (Not powered) or WFE + SLEEPDEEP = 1 WAITMODE = 1 + FLPM = 0 Wait Mode w/Flash in Standby Mode ON ON Powered (Not clocked) or WFE + SLEEPDEEP = 0 + LPM = 1 + FLPM = 0 WAITMODE = 1 + FLPM = 1 Wait Mode w/Flash in Deep Power Down Mode ON ON Powered (Not clocked) or WFE + SLEEPDEEP = 0 + LPM = 1 + FLPM = 1 WFE SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Sleep Mode ON ON Powered(6) (Not clocked) or WFI + SLEEPDEEP = 0 + LPM = 0 Notes: Potential Wake Up Sources Core at Wake Up PIO State while in Low- PIO State Consumption (1) (2) Power Mode at Wake Up Wake-up Time(3) Previous state saved PIOA & PIOB & PIOC Inputs with pull ups 1 µA typ(4) < 1 ms Clocked back Previous state saved Unchanged 32.2 µA(5) < 10 µs Any Event from: Fast startup through WKUP0-15 pins RTC alarm RTT alarm USB wake-up Clocked back Previous state saved Unchanged 27.6 µA < 100 µs Entry mode =WFI Interrupt Only; Entry mode =WFE Any Enabled Interrupt and/or Any Event from: Fast start-up through WKUP0-15 pins RTC alarm RTT alarm USB wake-up Clocked back Previous state saved Unchanged (7) (7) WKUP0-15 pins SM alarm RTC alarm RTT alarm Reset Any Event from: Fast startup through WKUP0-15 pins RTC alarm RTT alarm USB wake-up 33 1. The external loads on PIOs are not taken into account in the calculation. 2. Supply Monitor current consumption is not included. 3. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is fetched. 4. Total consumption 1 µA typ to 1.8V on VDDIO at 25°C. 5. 20.4 µA on VDDCORE, 32.2 µA for total current consumption. 6. Depends on MCK frequency. 7. Depends on MCK frequency. In this mode, the core is supplied but some peripherals can be clocked. 5.7 Wake-up Sources The wake-up events allow the device to exit the Backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. 5.8 Fast Start-up The SAM4S allows the processor to restart in a few microseconds while the processor is in Wait mode. A fast start-up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + USB + RTC + RTT). The fast restart circuitry is fully asynchronous and provides a fast start-up signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 4/8/12 MHz Fast RC oscillator, switches the master clock on this 4 MHz clock and reenables the processor clock. 34 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 6. Input/Output Lines The SAM4S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO controllers. All I/Os have several input or output modes such as pull-up or pulldown, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to Section 31. “Parallel Input/Output Controller (PIO)”. Some GPIOs can have alternate function as analog input. When the GPIO is set in analog mode, all digital features of the I/O are disabled. The input/output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM4S embeds high-speed pads able to handle up to 70 MHz for HSMCI (MCK/2), 70 MHz for SPI clock lines and 46 MHz on other lines. See Section 44.12 “AC Characteristics” for more details. Typical pull-up and pulldown value is 100 kΩ for all I/Os. Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1). It consists of an internal series resistor termination scheme for impedance matching between the driver output (SAM4S) and the PCB trace impedance preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. In conclusion ODT helps diminish signal integrity issues. Figure 6-1. On-Die Termination Z0 ~ ZO + RODT ODT 36 Ω Typ. RODT Receiver SAM4 Driver with ZO ~ 10 Ω PCB Trace Z0 ~ 50 Ω SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 35 6.2 System I/O Lines System I/O lines are pins used by oscillators, test mode, reset and JTAG. Table 6-1 provides the SAM4S system I/O lines shared with PIO lines. These pins are software configurable as general-purpose I/O or system pins. At startup, the default function of these pins is always used. Table 6-1. System I/O Configuration Pin List SYSTEM_IO Bit Number Default Function After Reset Other Function Constraints For Normal Start 12 ERASE PB12 Low Level at startup(1) 10 DDM PB10 – 11 DDP PB11 – 7 TCK/SWCLK PB7 – 6 TMS/SWDIO PB6 – 5 TDO/TRACESWO PB5 – 4 TDI PB4 – – PA7 XIN32 – – PA8 XOUT32 – – PB9 XIN – – PB8 XOUT – Configuration In Matrix User Interface Registers (Refer to the System I/O Configuration Register in Section 25. “Bus Matrix (MATRIX)”.) (2) (3) Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PB12 into PIO mode, 2. Refer to “Slow Clock Generator” in Section 18. “Supply Controller (SUPC)”. 3. Refer to the 3 to 20 MHZ crystal oscillator information in Section 29. “Power Management Controller (PMC)”. 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on page 13. At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer to Section 13. “Debug and Test Features”. SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode. The JTAG pin and PA7 pin are used to select the JTAG Boundary Scan when asserted JTAGSEL at a high level and PA7 at low level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to Section 13. “Debug and Test Features”. 36 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 6.3 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see Section 21. “Fast Flash Programming Interface (FFPI)”. For more on the manufacturing and test mode, refer to Section 13. “Debug and Test Features”. 6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input. 6.5 ERASE Pin The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as logic level 1). The ERASE pin and the ROM code ensure an in-situ reprogrammability of the Flash content without the use of a debug tool. When the security bit is activated, the ERASE pin provides the capability to reprogram the Flash content. It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations. This pin is debounced by SCLK to improve the glitch tolerance. To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in Table 44-74 “AC Flash Characteristics”. The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing. Refer to Section 11.2 “Peripheral Signal Multiplexing on I/O Lines” on page 51. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash. 6.6 Anti-tamper Pins/Low-power Tamper Detection WKUP0 and WKUP1 generic wake-up pins can be used as anti-tamper pins. Anti-tamper pins detect intrusion, for example, into a housing box. Upon detection through a tamper switch, automatic, asynchronous and immediate clear of registers in the backup area will be performed. Anti-tamper pins can be used in all power modes (Backup/Wait/Sleep/Active). Anti-tampering events can be programmed so that half of the General Purpose Backup Registers (GPBR) are erased automatically. See "Supply Controller" section for further description. RTCOUT0 and RTCOUT1 pins can be used to generate waveforms from the RTC in order to take advantage of the RTC inherent prescalers while the RTC is the only powered circuitry (low-power mode, Backup mode) or in any active mode. Entering backup or low-power modes does not affect the waveform generation outputs. Antitampering pin detection can be synchronized with this signal. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37 7. Product Mapping Figure 7-1. SAM4S Product Mapping Code 0x00000000 0x00000000 Address memory space 0x40000000 Code 0x40004000 Peripherals HSMCI Boot Memory 0x00400000 0x00800000 Internal Flash Internal ROM 1 Mbyte bit band region 0x00C00000 0x20100000 0x40008000 SRAM SPI 0x4000C000 0x20400000 Reserved 0x22000000 0x24000000 0x40000000 External RAM 0x61000000 SMC Chip Select 0 0x62000000 SMC Chip Select 1 0x63000000 SMC Chip Select 2 0x64000000 SMC Chip Select 3 0x60000000 0x40010000 32 Mbytes bit band alias +0x40 Undefined +0x80 Peripherals 0x40014000 External SRAM +0x40 0xA0000000 +0x80 Reserved TC0 TC0 TC0 TC1 TC0 TC2 TC1 TC3 TC1 TC4 TC1 TC5 0x40018000 0xE0000000 TWI0 System Reserved 0x9FFFFFFF 0x4001C000 0xFFFFFFFF TWI1 0x40020000 0x400E0000 System Controller SMC 0x400E0200 offset block peripheral PWM 0x40024000 10 0x40028000 PMC 0x4002C000 USART1 0x400E0600 UART0 0x400E0740 5 8 UART1 UDP 0x400E0C00 9 6 EEFC1 PIOA 0x400E1000 PIOB 0x400E1200 PIOC 0x400E1400 RSTC +0x10 0x4003C000 DACC 0x40040000 0x40044000 11 12 13 1 SUPC CRCCU 0x40048000 RTT +0x50 WDT +0x60 RTC +0x90 GPBR 0x400E1600 Reserved 4 2 25 26 27 28 19 20 31 14 15 33 29 30 34 35 0x400E0000 System Controller 0x400E2600 0x40100000 Reserved 0x42000000 3 24 Reserved Reserved +0x30 Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 ADC ACC 0x400E0E00 23 Reserved 0x40038000 EEFC0 SAM4S Series [DATASHEET] 21 0x40030000 0x40034000 0x400E0A00 38 22 Reserved CHIPID 0x400E0800 0x4007FFFF USART0 MATRIX 0x400E0400 ID 18 Reserved Undefined 0x1FFFFFFF 0x60000000 SSC 0x20000000 0x43FFFFFF 32 Mbytes bit band alias Reserved 0x60000000 1 Mbyte bit band regiion 8. Memories 8.1 Embedded Memories 8.1.1 Internal SRAM The following table shows the amount of high-speed SRAM embedded in the SAM4Sx devices. Table 8-1. Embedded High-speed SRAM per Device Device Flash Total Embedded High-speed SRAM SAM4SD32 2 x 1024 Kbytes 160 Kbytes SAM4SD16 2 x 512 Kbytes 160 Kbytes SAM4SA16 1024 Kbytes 160 Kbytes SAM4S16 1024 Kbytes 128 Kbytes SAM4S8 512 Kbytes 128 Kbytes SAM4S4 256 Kbytes 64 Kbytes SAM4S2 128 Kbytes 64 Kbytes The SRAM is accessible over system Cortex-M4 bus at address 0x2000 0000. The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 to 0x23FF FFFF. 8.1.2 Internal ROM The SAM4S embeds an internal ROM, which contains the SAM boot assistant (SAM-BA ® ), In-Application Programming (IAP) routines and Fast Flash Programming Interface (FFPI). At any time, the ROM is mapped at address 0x0080 0000. 8.1.3 8.1.3.1 Embedded Flash Flash Overview The memory is organized in sectors. Each sector has a size of 64 Kbytes. The first sector of 64 Kbytes is divided into three smaller sectors. The three smaller sectors are organized to consist of two sectors of 8 Kbytes and one sector of 48 Kbytes. Refer to Figure 8-1, "Global Flash Organization". SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 39 Figure 8-1. Global Flash Organization Sector size Sector name 8 Kbytes Small Sector 0 8 Kbytes Small Sector 1 48 Kbytes Larger Sector 64 Kbytes Sector 1 64 Kbytes Sector n Sector 0 Each sector is organized in pages of 512 bytes. For sector 0:  The smaller sector 0 has 16 pages of 512 bytes  The smaller sector 1 has 16 pages of 512 bytes  The larger sector has 96 pages of 512 bytes From Sector 1 to n: The rest of the array is composed of 64-Kbyte sectors of 128 pages, each page of 512 bytes. Refer to Figure 8-2, "Flash Sector Organization". 40 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 8-2. Flash Sector Organization A sector size is 64 Kbytes Sector 0 16 pages of 512 bytes Smaller sector 0 16 pages of 512 bytes Smaller sector 1 96 pages of 512 bytes Larger sector Sector 1 128 pages of 512 bytes Sector n 128 pages of 512 bytes Flash size varies by product:  SAM4S2: the Flash size is 128 Kbytes in a single plane  SAM4S4: the Flash size is 256 Kbytes in a single plane  SAM4S8/S16: the Flash size is 512 Kbytes in a single plane ̶   Internal Flash address is 0x0040_0000 SAM4SD16/SA16: the Flash size is 2 x 512 Kbytes ̶ Internal Flash0 address is 0x0040_0000 ̶ Internal Flash1 address is 0x0048_0000 SAM4SD32: the Flash size is 2 x 1024 Kbytes ̶ Internal Flash0 address is 0x0040_0000 ̶ Internal Flash1 address is 0x0050_0000 Refer to Figure 8-3, "Flash Size" for the organization of the Flash depending on its size. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 41 Figure 8-3. Flash Size Flash 1 Mbytes Flash 512 Kbytes Flash 256 Kbytes 2 * 8 Kbytes 2 * 8 Kbytes 2 * 8 Kbytes 1 * 48 Kbytes 1 * 48 Kbytes 1 * 48 Kbytes 3 * 64 Kbytes 7 * 64 Kbytes 15 * 64 Kbytes The following erase commands can be used depending on the sector size:    8 Kbyte small sector ̶ Erase and write page (EWP) ̶ Erase and write page and lock (EWPL) ̶ Erase sector (ES) with FARG set to a page number in the sector to erase ̶ Erase pages (EPA) with FARG [1:0] = 0 to erase four pages or FARG [1:0] = 1 to erase eight pages. FARG [1:0] = 2 and FARG [1:0] = 3 must not be used. 48 Kbyte and 64 Kbyte sectors ̶ One block of 8 pages inside any sector, with the command Erase pages (EPA) with FARG[1:0] = 1 ̶ One block of 16 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 2 ̶ One block of 32 pages inside any sector, with the command Erase pages (EPA) and FARG[1:0] = 3 ̶ One sector with the command Erase sector (ES) and FARG set to a page number in the sector to erase Entire memory plane ̶ The entire Flash, with the command Erase all (EA) The Write commands of the Flash cannot be used under 330 kHz. 8.1.3.2 Enhanced Embedded Flash Controller The Enhanced Embedded Flash Controller manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block. It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 8.1.3.3 Flash Speed The user must set the number of wait states depending on the frequency used. For more details, refer to Section 44.12 “AC Characteristics”. 42 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 8.1.3.4 Error Code Correction (ECC) The Flash embeds an ECC module with 8 parity bits for each 64 data bits. The ECC is able to correct one unique error. The errors are detected while a read access is performed into memory array. The ECC (Hamming Algorithm) is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. The ECC is capable of single bit error correction. 8.1.3.5 Lock Regions Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 8-2. Lock Bit Number Product Number of Lock Bits Lock Region Size SAM4SD32 256 (128 + 128) 8 Kbytes SAM4SD16 128 (64 + 64) 8 Kbytes SAM4S16/SA16 128 8 Kbytes SAM4S8 64 8 Kbytes SAM4S4 32 8 Kbytes SAM4S2 16 8 Kbytes If a locked region erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.1.3.6 Security Bit The SAM4SD32/SD16/S16/SA16/S8/S4/S2 feature one security bit based on a specific General Purpose NVM bit (GPNVM bit 0). When the security bit is enabled, any access to the Flash, SRAM, core registers and internal peripherals through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled through the command “Set General Purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted. The ERASE pin integrates a permanent pull-down. Consequently, it can be left unconnected during normal operation. However, it is recommended, in harsh environment, to connect it directly to GND if the erase operation is not used in the application. To avoid unexpected erase at power-up, a minimum ERASE pin assertion time is required. This time is defined in Table 44-74 “AC Flash Characteristics”. The erase operation is not performed when the system is in Wait mode with the Flash in deep-power-down mode. To make sure that the erase operation is performed after power-up, the system must not reconfigure the ERASE pin as GPIO or enter Wait mode with Flash in Deep-power-down mode before the ERASE pin assertion time has elapsed. The following sequence ensures the erase operation in all cases: 1. Assert the ERASE pin (High) 2. Assert the NRST pin (Low) 3. Power cycle the device SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 43 4. 8.1.3.7 Maintain the ERASE pin high for at least the minimum assertion time. Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 8.1.3.8 Unique Identifier Each device integrates its own 128-bit unique identifier. These bits are factory-configured and cannot be changed by the user. The ERASE pin has no effect on the unique identifier. 8.1.3.9 User Signature Each device contains a user signature of 512 bytes. It can be used by the user to store user information such as trimming, keys, etc., that the customer does not want to be erased by asserting the ERASE pin or by software ERASE command. Read, write and erase of this area is allowed. 8.1.3.10 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. 8.1.3.11 SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART and USB. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 8.1.3.12 GPNVM Bits The SAM4S16/S8/S4/S2 feature two GPNVM bits. The SAM4SA16/SD32/SD16 feature three GPNVM bits, coming from Flash 0, that can be cleared or set, respectively, through the "Clear GPNVM Bit" and "Set GPNVM Bit" commands of the EEFC0 User Interface. There is no GPNVM bit on Flash 1. The GPNVM0 is the security bit. The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or Flash. The SAM4SD32/16 embeds an additional GPNVM bit, GPNVM2. GPNVM2 is used only to swap the Flash 0 and Flash 1. If GPNVM2 is ENABLE, the Flash 1 is mapped at address 0x0040_0000 (Flash 1 and Flash 0 are 44 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 continuous). If GPNVM2 is DISABLE, the Flash 0 is mapped at address 0x0040_0000 (Flash 0 and Flash 1 are continuous). Table 8-3. General-purpose Non-volatile Memory Bits Device Name GPNVM0 GPNVM1 GPNVM2 SAM4SD32 Flash Selection (Flash 0 or Flash 1) SAM4SD16 SAM4SA16 SAM4S16 Security Bit Boot Mode Selection SAM4S8 Not available SAM4S4 SAM4S2 8.1.4 Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed using GPNVM bits. A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Setting GPNVM1 selects the boot from the Flash. Clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM1 and thus selects the boot from the ROM by default. Setting the GPNVM2 selects Flash 1, clearing it selects the boot from Flash 0. Asserting ERASE clears GPNVM2 and thus selects the boot from Flash 0 by default. GPNVM2 is available only on SAM4SD32/SD16/SA16. 8.2 External Memories The SAM4S features one External Bus Interface to provide an interface to a wide range of external memories and to any parallel peripheral. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 45 9. Real Time Event Management The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 9.1 46 Embedded Characteristics  Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as ADC or DACC, for example, to start measurement/conversion without processor intervention.  UART, USART, SPI, TWI, SSC, PWM, HSMCI, ADC, DACC, PIO also generate event triggers directly connected to Peripheral DMA Controller (PDC) for data transfer without processor intervention.  Parallel capture logic is directly embedded in PIO and generates trigger event to PDC to capture data without processor intervention.  PWM security events (faults) are in combinational form and directly routed from event generators (ADC, ACC, PMC, TIMER) to PWM module.  PMC security event (clock failure detection) can be programmed to switch the MCK on reliable main RC internal clock without processor intervention. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 9.2 Real Time Event Mapping List Table 9-1. Real-time Event Mapping List Function Application Security General-purpose General-purpose Generalpurpose, motor control Safety Motor control Image capture Description Event Source Event Destination Immediate GPBR clear (asynchronous) on Tamper detection through WKUP0/1 IO pins (1) Parallel Input/Output Controller (PIO): WKUP0/1 General Purpose Backup Registers (GPBR) Automatic Switch to reliable main RC oscillator in case of Main Crystal Clock Failure (2) Power Management Controller (PMC) PMC Puts the PWM Outputs in Safe Mode (Main Crystal Clock Failure Detection) (2)(3) PMC Puts the PWM Outputs in Safe Mode (Overcurrent sensor, ...) (3)(4) Analog Comparator Controller (ACC) Puts the PWM Outputs in Safe Mode (Overspeed, Overcurrent detection ...) (3)(5) Analog-Front-EndController (ADC) Puts the PWM Outputs in Safe Mode (Overspeed detection through TIMER Quadrature Decoder) (3)(6) Timer Counter (TC) Generalpurpose, motor control Puts the PWM Outputs in Safe Mode (General Purpose Fault Inputs) (3) PIO Low-cost image sensor PC is embedded in PIO (Capture Image from Sensor directly to System Memory) (7) PIO Pulse Width Modulation (PWM) PDC PIO (ADTRG) General-purpose Trigger source selection in ADC (8) TC Output 1 Measurement trigger ADC TC Output 2 Motor control Delay measurement TC Output 0 Motor control ADC-PWM synchronization (9)(10) Trigger source selection in ADC (8) Propagation delay of external components (IOs, power transistor bridge driver, etc.) (11)(12) PWM Event Line 0 PWM Event Line 1 PWM Output Compare Line 0 TC Input (A/B) 0 PWM Output Compare Line 1 TC Input (A/B) 1 PWM Output Compare Line 2 TC Input (A/B) 2 PIO DATRG TC Output 0 Conversion trigger General-purpose Trigger source selection in DACC (13) TC Output 1 TC Output 2 Digital-Analog Converter Controller (DACC) PWM Event Line 0 (10) PWM Event Line 1 (10) Notes: 1. Refer to “Low-power Tamper Detection and Anti-Tampering” in Section 18. “Supply Controller (SUPC)” and “General Purpose Backup Register x” in “General Purpose Backup Registers (GPBR)” . 2. Refer to “Main Clock Failure Detector” in Section 29. “Power Management Controller (PMC)”. 3. Refer to “Fault Inputs” and “Fault Protection” in “Pulse Width Modulation Controller (PWM)” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 47 4. Refer to “Fault Mode” in “Analog Comparator Controller (ACC)” . 5. Refer to “Fault Output” in Section 42. “Analog-to-Digital Converter (ADC)”. 6. Refer to “Fault Mode” in Section 37. “Timer Counter (TC)”. 7. Refer to “Parallel Capture Mode” in “Parallel Input/Output Controller (PIO)” . 8. Refer to “Conversion Triggers” and the ADC Mode Register (ADC_MR) in Section 42., “Analog-to-Digital Converter (ADC)”. 9. Refer to PWM Comparison Value Register (PWM_CMPV) in Section 39. “Pulse Width Modulation Controller (PWM)”. 10. Refer to “PWM Comparison Units” and “PWM Event Lines” in Section 39. “Pulse Width Modulation Controller (PWM)”. 11. Refer to Section 39.6.2.2 “Comparator” in Section 39. “Pulse Width Modulation Controller (PWM)”. 12. Refer to Section 37. “Timer Counter (TC)”. 13. Refer to DACC Trigger Register (DACC_TRIGR) in Section 43. “Digital-to-Analog Converter Controller (DACC)”. 48 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 10. System Controller The System Controller is a set of peripherals which allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. 10.1 System Controller and Peripheral Mapping Refer to Figure 7-1, "SAM4S Product Mapping". All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM4S embeds three features to monitor, warn and/or reset the chip:  Power-on-Reset on VDDIO  Brownout Detector on VDDCORE  Supply Monitor on VDDIO 10.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to Section 44. “Electrical Characteristics”. 10.2.2 Brownout Detector on VDDCORE The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply Controller Mode Register (SUPC_MR). It is especially recommended to disable it during low-power modes such as Wait or Sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to Section 18. “Supply Controller (SUPC)” and Section 44. “Electrical Characteristics”. 10.2.3 Supply Monitor on VDDIO The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information, refer to Section 18. “Supply Controller (SUPC)” and Section 44. “Electrical Characteristics”. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 49 11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM4S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power Management Controller. Table 11-1. 50 Peripheral Identifiers Instance ID Instance Name NVIC Interrupt 0 SUPC X Supply Controller 1 RSTC X Reset Controller 2 RTC X Real-Time Clock 3 RTT X Real-Time Timer 4 WDT X Watchdog Timer 5 PMC X Power Management Controller 6 EEFC0 X Enhanced Embedded Flash Controller 0 7 EEFC1 – Enhanced Embedded Flash Controller 1 8 UART0 X X Universal Asynchronous Receiver Transmitter 0 9 UART1 X X Universal Asynchronous Receiver Transmitter 1 10 SMC – X Static Memory Controller 11 PIOA X X Parallel I/O Controller A 12 PIOB X X Parallel I/O Controller B 13 PIOC X X Parallel I/O Controller C 14 USART0 X X Universal Synchronous Asynchronous Receiver Transmitter 0 15 USART1 X X Universal Synchronous Asynchronous Receiver Transmitter 1 16 – – – Reserved 17 – – – Reserved 18 HSMCI X X Multimedia Card Interface 19 TWI0 X X Two-Wire Interface 0 20 TWI1 X X Two-Wire Interface 1 21 SPI X X Serial Peripheral Interface 22 SSC X X Synchronous Serial Controller 23 TC0 X X Timer/Counter 0 24 TC1 X X Timer/Counter 1 25 TC2 X X Timer/Counter 2 26 TC3 X X Timer/Counter 3 27 TC4 X X Timer/Counter 4 28 TC5 X X Timer/Counter 5 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 PMC Clock Control Instance Description Table 11-1. 11.2 Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description 29 ADC X X Analog-to-Digital Converter 30 DACC X X Digital-to-Analog Converter Controller 31 PWM X X Pulse Width Modulation 32 CRCCU X X CRC Calculation Unit 33 ACC X X Analog Comparator Controller 34 UDP X X USB Device Port Peripheral Signal Multiplexing on I/O Lines The SAM4S features two PIO controllers on 64-pin versions (PIOA and PIOB) or three PIO controllers on the 100pin version (PIOA, PIOB and PIOC), that multiplex the I/O lines of the peripheral set. The SAM4S 64-pin and 100-pin PIO controllers control up to 32 lines. Each line can be assigned to one of three peripheral functions: A, B or C. The multiplexing tables in the following tables define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO Controllers. The column “Comments” has been inserted in this table for the user’s own comments; it may be used to track how pins are defined in an application. Note that some peripheral functions which are output only, might be duplicated within the tables. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 51 11.2.1 PIO Controller A Multiplexing Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B Peripheral C Peripheral D(1) Extra Function System Function Comments (2) PA0 PWMH0 TIOA0 A17 WKUP0 PA1 PWMH1 TIOB0 A18 WKUP1(2) PA2 PWMH2 SCK0 DATRG WKUP2(2) PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 WKUP3(2) PA5 RXD0 NPCS3 WKUP4(2) PA6 TXD0 PCK0 PA7 RTS0 PWMH3 PA8 CTS0 ADTRG PA9 URXD0 NPCS1 PWMFI0 PA10 UTXD0 NPCS2 PWMFI1(1) PA11 NPCS0 PWMH0 PA12 MISO PWMH1 PA13 MOSI PWMH2 PA14 SPCK PWMH3 PA15 TF TIOA1 PWML3 WKUP14/PIODCEN1(4) PA16 TK TIOB1 PWML2 WKUP15/PIODCEN2(4) PA17 TD PCK1 PWMH3 AD0(5) PA18 RD PCK2 A14 PA19 RK PWML0 A15 AD2/WKUP9(2) PA20 RF PWML1 A16 AD3/WKUP10(2) PA21 RXD1 PCK1 XIN32(3) WKUP5(2) XOUT32(3) WKUP6(2) WKUP7(2) WKUP8(2) PWMFI2(1) AD1(5) AD8(5) 64-/100-pin versions (5) 64-/100-pin versions PA22 TXD1 NPCS3 NCS2 AD9 PA23 SCK1 PWMH0 A19 PIODCCLK(6) 64-/100-pin versions PA24 RTS1 PWMH1 A20 PIODC0 64-/100-pin versions PA25 CTS1 PWMH2 A23 PIODC1 64-/100-pin versions PA26 DCD1 TIOA2 MCDA2 PIODC2 64-/100-pin versions PA27 DTR1 TIOB2 MCDA3 PIODC3 64-/100-pin versions PA28 DSR1 TCLK1 MCCDA PIODC4 64-/100-pin versions PA29 RI1 TCLK2 MCCK PIODC5 64-/100-pin versions (2) PA30 PWML2 NPCS2 MCDA0 WKUP11 /PIODC6 64-/100-pin versions PA31 NPCS1 PCK2 MCDA1 PIODC7 64-/100-pin versions Notes: 52 1. Only available in SAM4S4x and SAM4S2x. 2. WKUPx can be used if PIO controller defines the I/O line as "input". 3. Refer to Section 6.2 “System I/O Lines”. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 4. PIODCENx/PIODCx has priority over WKUPx. Refer to Section 31.5.13 “Parallel Capture Mode”. 5. To select this extra function, refer to Section 42.5.3 “Analog Inputs”. 6. To select this extra function, refer to “Section 31.5.13 “Parallel Capture Mode”. 11.2.2 PIO Controller B Multiplexing Table 11-3. I/O Line Multiplexing on PIO Controller B (PIOB) Peripheral A Peripheral B Peripheral C Extra Function System Function Comments (1) PB0 PWMH0 AD4/RTCOUT0 PB1 PWMH1 AD5/RTCOUT1(1) PB2 URXD1 NPCS2 AD6/WKUP12(2) PB3 UTXD1 PCK2 AD7(3) PB4 TWD1 PWMH2 PB5 TWCK1 PWML0 TDI(4) WKUP13(2) TDO/TRACESWO(4) PB6 TMS/SWDIO(4) PB7 TCK/SWCLK(4) PB8 XOUT(4) PB9 XIN(4) PB10 DDM PB11 DDP ERASE(4) PB12 PWML1 PB13 PWML2 PCK0 DAC0(5) 64-/100-pin versions PB14 NPCS1 PWMH3 DAC1(5) 64-/100-pin versions Notes: 1. 2. 3. 4. 5. Analog input has priority over RTCOUTx pin. See Section 16.5.8 “Waveform Generation”. WKUPx can be used if PIO controller defines the I/O line as "input". To select this extra function, refer to Section 42.5.3 “Analog Inputs”. Refer to Section 6.2 “System I/O Lines”. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. See Section 43.7.3 “DACC Channel Enable Register”. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 53 11.2.3 PIO Controller C Multiplexing Table 11-4. I/O Line Multiplexing on PIO Controller C (PIOC) System Function Peripheral B PC0 D0 PWML0 100-pin version PC1 D1 PWML1 100-pin version PC2 D2 PWML2 100-pin version PC3 D3 PWML3 100-pin version PC4 D4 NPCS1 100-pin version PC5 D5 100-pin version PC6 D6 100-pin version PC7 D7 100-pin version PC8 NWE 100-pin version PC9 NANDOE 100-pin version PC10 NANDWE 100-pin version PC11 NRD PC12 Peripheral C Extra Function Peripheral A Comments 100-pin version NCS3 100-pin version AD10 (1) 100-pin version PC13 NWAIT PC14 NCS0 PC15 NCS1 PC16 A21/NANDALE 100-pin version PC17 A22/NANDCLE 100-pin version PC18 A0 PWMH0 100-pin version PC19 A1 PWMH1 100-pin version PC20 A2 PWMH2 100-pin version PC21 A3 PWMH3 100-pin version PC22 A4 PWML3 100-pin version PC23 A5 TIOA3 100-pin version PC24 A6 TIOB3 100-pin version PC25 A7 TCLK3 100-pin version PC26 A8 TIOA4 100-pin version PC27 A9 TIOB4 100-pin version PC28 A10 TCLK4 PC29 A11 PWML0 AD12 (1) 100-pin version PWML1 TIOA5 PC30 A12 TIOB5 PC31 A13 TCLK5 Note: 54 1. To select this extra function, refer to Section 42.5.3 “Analog Inputs”. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 AD11(1) 100-pin version 100-pin version AD13 (1) 100-pin version AD14 (1) 100-pin version 100-pin version 12. ARM Cortex-M4 Processor 12.1 Description The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including outstanding processing performance combined with fast interrupt handling, enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core, system and memories, ultra-low power consumption with integrated sleep modes, and platform security robustness, with integrated memory protection unit (MPU). The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M4 processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex-M4 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt performance. The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down while still retaining program state. 12.1.1 System Level Interface The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications such as automotive. 12.1.2 Integrated Configurable Debug The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 55 CODE memory region. This enables applications stored on a non-erasable, ROM-based microcontroller to be patched if a small programmable memory, for example flash, is available in the device. During initialization, the application in ROM detects, from the programmable memory, whether a patch is required. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration, which means the program in the nonmodifiable ROM can be patched. 12.2 Embedded Characteristics  Tight integration of system peripherals reduces area and development costs  Thumb instruction set combines high code density with 32-bit performance  Code-patch ability for ROM system updates  Power control optimization of system components  Integrated sleep modes for low power consumption  Fast code execution permits slower processor clock or increases sleep mode time  Hardware division and fast digital-signal-processing oriented multiply accumulate  Saturating arithmetic for signal processing  Deterministic, high-performance interrupt handling for time-critical applications  Memory Protection Unit (MPU) for safety-critical applications  Extensive debug and trace capabilities: ̶ 12.3 Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing, and code profiling. Block Diagram Figure 12-1. Typical Cortex-M4 Implementation Cortex-M4 Processor NVIC Debug Access Port Processor Core Memory Protection Unit Flash Patch Serial Wire Viewer Data Watchpoints Bus Matrix Code Interface 56 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 SRAM and Peripheral Interface 12.4 Cortex-M4 Models 12.4.1 Programmers Model This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it contains information about the processor modes and privilege levels for software execution and stacks. 12.4.1.1 Processor Modes and Privilege Levels for Software Execution The processor modes are:  Thread mode Used to execute application software. The processor enters the Thread mode when it comes out of reset.  Handler mode Used to handle exceptions. The processor returns to the Thread mode when it has finished exception processing. The privilege levels for software execution are:  Unprivileged The software: ̶ Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction ̶ Cannot access the System Timer, NVIC, or System Control Block ̶ Might have a restricted access to memory or peripherals. Unprivileged software executes at the unprivileged level.  Privileged The software can use all the instructions and has access to all resources. Privileged software executes at the privileged level. In Thread mode, the Control Register controls whether the software execution is privileged or unprivileged, see “Control Register” . In Handler mode, software execution is always privileged. Only privileged software can write to the Control Register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 12.4.1.2 Stacks The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked item in memory When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements two stacks, the main stack and the process stack, with a pointer for each held in independent registers, see “Stack Pointer” . In Thread mode, the Control Register controls whether the processor uses the main stack or the process stack, see “Control Register” . In Handler mode, the processor always uses the main stack. The options for processor operations are: Table 12-1. Processor Mode Summary of processor mode, execution privilege level, and stack use options Used to Execute Privilege Level for Software Execution Thread Applications Privileged or unprivileged Handler Exception handlers Always privileged Note: 1. Stack Used (1) Main stack or process stack(1) Main stack See “Control Register” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 57 12.4.1.3 Core Registers Figure 12-2. Processor Core Registers R0 R1 R2 R3 Low registers R4 R5 R6 General-purpose registers R7 R8 R9 High registers R10 R11 R12 Stack Pointer SP (R13) Link Register LR (R14) Program Counter PC (R15) PSR PSP‡ MSP‡ ‡ Banked version of SP Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL Table 12-2. CONTROL register Core Processor Registers Register Name Access(1) Required Privilege(2) Reset General-purpose registers R0–R12 Read/Write Either Unknown Stack Pointer MSP Read/Write Privileged See description Stack Pointer PSP Read/Write Either Unknown Link Register LR Read/Write Either 0xFFFFFFFF Program Counter PC Read/Write Either See description Program Status Register PSR Read/Write Privileged 0x01000000 Application Program Status Register APSR Read/Write Either 0x00000000 Interrupt Program Status Register IPSR Read-only Privileged 0x00000000 Execution Program Status Register EPSR Read-only Privileged 0x01000000 Priority Mask Register PRIMASK Read/Write Privileged 0x00000000 Fault Mask Register FAULTMASK Read/Write Privileged 0x00000000 Base Priority Mask Register BASEPRI Read/Write Privileged 0x00000000 Control Register CONTROL Read/Write Privileged 0x00000000 Notes: 58 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ. 2. An entry of Either means privileged and unprivileged software can access the register. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.4.1.4 General-purpose Registers R0–R12 are 32-bit general-purpose registers for data operations. 12.4.1.5 Stack Pointer The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the Control Register indicates the stack pointer to use:  0 = Main Stack Pointer (MSP). This is the reset value.  1 = Process Stack Pointer (PSP). On reset, the processor loads the MSP with the value from address 0x00000000. 12.4.1.6 Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF. 12.4.1.7 Program Counter The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 59 12.4.1.8 Program Status Register Name: PSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 29 C 28 V 27 Q 26 23 22 21 20 25 24 T 19 18 17 16 12 11 10 9 – 8 ISR_NUMBER 4 3 2 1 0 ICI/IT – 15 14 13 ICI/IT 7 6 5 ISR_NUMBER The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) • Execution Program Status Register (EPSR). These registers are mutually exclusive bitfields in the 32-bit PSR. The PSR accesses these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: • Read of all the registers using PSR with the MRS instruction • Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction. The PSR combinations and attributes are: Name Access Combination PSR Read/Write(1)(2) APSR, EPSR, and IPSR IEPSR Read-only EPSR and IPSR IAPSR APSR and IPSR (2) APSR and EPSR Read/Write EAPSR Notes: (1) Read/Write 1. The processor ignores writes to the IPSR bits. 2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. See the instruction descriptions “MRS” and “MSR” for more information about how to access the program status registers. 60 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.4.1.9 Application Program Status Register Name: APSR Access: Read/Write Reset: 0x000000000 31 N 30 Z 23 22 29 C 28 V 27 Q 26 21 20 19 18 – 15 14 25 – 24 17 16 GE[3:0] 13 12 11 10 9 8 3 2 1 0 – 7 6 5 4 – The APSR contains the current state of the condition flags from previous instruction executions. • N: Negative Flag 0: Operation result was positive, zero, greater than, or equal 1: Operation result was negative or less than. • Z: Zero Flag 0: Operation result was not zero 1: Operation result was zero. • C: Carry or Borrow Flag Carry or borrow flag: 0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit. • V: Overflow Flag 0: Operation did not result in an overflow 1: Operation resulted in an overflow. • Q: DSP Overflow and Saturation Flag Sticky saturation flag: 0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero 1: Indicates when an SSAT or USAT instruction results in saturation. This bit is cleared to zero by software using an MRS instruction. • GE[19:16]: Greater Than or Equal Flags See “SEL” for more information. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 61 12.4.1.10 Interrupt Program Status Register Name: IPSR Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 – 23 22 21 20 – 15 14 13 12 – 11 10 9 8 ISR_NUMBER 7 6 5 4 3 2 1 0 ISR_NUMBER The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). • ISR_NUMBER: Number of the Current Exception 0 = Thread mode 1 = Reserved 2 = NMI 3 = Hard fault 4 = Memory management fault 5 = Bus fault 6 = Usage fault 7–10 = Reserved 11 = SVCall 12 = Reserved for Debug 13 = Reserved 14 = PendSV 15 = SysTick 16 = IRQ0 49 = IRQ34 See “Exception Types” for more information. 62 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.4.1.11 Execution Program Status Register Name: EPSR Access: Read/Write Reset: 0x000000000 31 23 30 22 29 – 28 21 20 27 26 25 24 T 16 ICI/IT 19 18 17 11 10 9 – 15 14 13 12 ICI/IT 7 6 5 8 – 4 3 2 1 0 – The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR value in the stacked PSR to indicate the operation that is at fault. See “Exception Entry and Return” . • ICI: Interruptible-continuable Instruction When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor: – Stops the load multiple or store multiple instruction operation temporarily – Stores the next register operand in the multiple operation to EPSR bits[15:12]. After servicing the interrupt, the processor: – Returns to the register pointed to by bits[15:12] – Resumes the execution of the multiple load or store instruction. When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero. • IT: If-Then Instruction Indicates the execution state bits of the IT instruction. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See “IT” for more information. • T: Thumb State The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0: – Instructions BLX, BX and POP{PC} – Restoration from the stacked xPSR value on an exception return – Bit[0] of the vector value on an exception entry or reset. Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See “Lockup” for more information. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 63 12.4.1.12 Exception Mask Registers The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might impact on timing critical tasks. To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information. 12.4.1.13 Priority Mask Register Name: PRIMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRIMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The PRIMASK register prevents the activation of all exceptions with a configurable priority. • PRIMASK 0: No effect 1: Prevents the activation of all exceptions with a configurable priority. 64 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.4.1.14 Fault Mask Register Name: FAULTMASK Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FAULTMASK – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 – The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI). • FAULTMASK 0: No effect. 1: Prevents the activation of all exceptions except for NMI. The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 65 12.4.1.15 Base Priority Mask Register Name: BASEPRI Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 BASEPRI The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. • BASEPRI Priority mask bits: 0x0000: No effect Nonzero: Defines the base priority for exception processing The processor does not process any exception with a priority value greater than or equal to BASEPRI. This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field, bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” for more information. Remember that higher priority field values correspond to lower exception priorities. 66 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.4.1.16 Control Register Name: CONTROL Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 – 1 SPSEL 0 nPRIV – 23 22 21 20 – 15 14 13 12 – 7 6 5 – 4 The Control Register controls the stack used and the privilege level for software execution when the processor is in Thread mode. • SPSEL: Active Stack Pointer Defines the current stack: 0: MSP is the current stack pointer. 1: PSP is the current stack pointer. In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception return. • nPRIV: Thread Mode Privilege Level Defines the Thread mode privilege level: 0: Privileged. 1: Unprivileged. Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the Control Register when in Handler mode. The exception entry and return mechanisms update the Control Register based on the EXC_RETURN value. In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and exception handlers use the main stack. By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either: • Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR” , or • Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 12-10. Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See “ISB” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 67 12.4.1.17 Exceptions and Interrupts The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and “Exception Return” for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more information. 12.4.1.18 Data Types The processor supports the following data types:  32-bit words  16-bit halfwords  8-bit bytes  The processor manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus (PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” for more information. 12.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS) For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:    A common way to: ̶ Access peripheral registers ̶ Define exception vectors The names of: ̶ The registers of the core peripherals ̶ The core exception vectors A device-independent interface for RTOS kernels, including a debug channel. The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor. The CMSIS simplifies the software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. Note: This document uses the register short names defined by the CMSIS. In a few cases, these differ from the architectural short names that might be used in other documents. The following sections give more information about the CMSIS: 68  Section 12.5.3 ”Power Management Programming Hints”  Section 12.6.2 ”CMSIS Functions”  Section 12.8.2.1 ”NVIC Programming Hints”. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.4.2 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. Figure 12-3. Memory Map 0xFFFFFFFF Vendor-specific 511 MB memory Private peripheral 1.0 MB bus External device 0xE0100000 0xE00FFFFF 0xE000 0000 0x DFFFFFFF 1.0 GB 0xA0000000 0x9FFFFFFF External RAM 0x43FFFFFF 1.0 GB 32 MB Bit-band alias 0x60000000 0x5FFFFFFF 0x42000000 0x400FFFFF 0x40000000 Peripheral 0.5 GB 1 MB Bit-band region 0x40000000 0x3FFFFFFF 0x23FFFFFF 32 MB Bit-band alias SRAM 0.5 GB 0x20000000 0x1FFFFFFF 0x22000000 Code 0x200FFFFF 0x20000000 1 MB Bit-band region 0.5 GB 0x00000000 The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see “Bit-banding” . The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers. This memory mapping is generic to ARM Cortex-M4 products. To get the specific memory mapping of this product, refer to the Memories section of the datasheet. 12.4.2.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 69 Memory Types  Normal The processor can re-order transactions for efficiency, or perform speculative reads.  Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory.  Strongly-ordered The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. Additional Memory Attributes  Shareable For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, the software must ensure data coherency between the bus masters.  Execute Never (XN) Means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. 12.4.2.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, the software must insert a memory barrier instruction between the memory access instructions, see “Software Ordering of Memory Accesses” . However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses is described below. Table 12-3. Ordering of the Memory Accesses Caused by Two Instructions A2 Device Access Normal Access Nonshareable Shareable Stronglyordered Access Normal Access – – – – Device access, non-shareable – < – < Device access, shareable – – < < Strongly-ordered access – < < < A1 Where: 12.4.2.3 – Means that the memory system does not guarantee the ordering of the accesses. < Means that accesses are observed in program order, that is, A1 is always observed before A2. Behavior of Memory Accesses The following table describes the behavior of accesses to each region in the memory map. 70 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 12-4. Memory Access Behavior Address Range Memory Region Memory Type XN 0x00000000–0x1FFFFFFF Code Normal(1) – Executable region for program code. Data can also be put here. 0x20000000–0x3FFFFFFF SRAM Normal (1) – Executable region for data. Code can also be put here. This region includes bit band and bit band alias areas, see Table 12-6. 0x40000000–0x5FFFFFFF Peripheral Device (1) XN This region includes bit band and bit band alias areas, see Table 12-6. 0x60000000–0x9FFFFFFF External RAM Normal (1) – Executable region for data XN External Device memory Stronglyordered (1) XN This region includes the NVIC, system timer, and system control block. Device (1) XN Reserved 0xA0000000–0xDFFFFFFF External device Device 0xE0000000–0xE00FFFFF Private Peripheral Bus 0xE0100000–0xFFFFFFFF Reserved Note: (1) Description 1. See “Memory Regions, Types and Attributes” for more information. The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” . Additional Memory Access Constraints For Caches and Shared Memory When a system includes caches or shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 12-5 shows. Table 12-5. Memory Region Shareability and Cache Policies Address Range Memory Region Memory Type Shareability Cache Policy (1) – WT(2) 0x00000000–0x1FFFFFFF Code Normal 0x20000000–0x3FFFFFFF SRAM Normal (1) – WBWA(2) 0x40000000–0x5FFFFFFF Peripheral Device (1) – – External RAM Normal (1) – External device Device (1) 0xE0000000–0xE00FFFFF Private Peripheral Bus Strongly-ordered(1) Shareable (1) – 0xE0100000–0xFFFFFFFF Vendor-specific device Device (1) – – 0x60000000–0x7FFFFFFF WBWA(2) WT (2) 0x80000000–0x9FFFFFFF 0xA0000000–0xBFFFFFFF 0xC0000000–0xDFFFFFFF Notes: Shareable (1) Non-shareable (1) – 1. See “Memory Regions, Types and Attributes” for more information. 2. WT = Write through, no write allocate. WBWA = Write back, write allocate. See the “Glossary” for more information. Instruction Prefetch and Branch Prediction The Cortex-M4 processor: SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 71  Prefetches instructions ahead of execution  Speculatively prefetches from branch target addresses. 12.4.2.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because:  The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence.  The processor has multiple bus interfaces  Memory or devices in the memory map have different wait states  Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions: DMB The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See “DMB” . DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB” . ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See “ISB” . MPU Programming Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by subsequent instructions. 12.4.2.5 Bit-banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:  Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 12-6.  Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table 12-7. Table 12-6. SRAM Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses 0x20000000–0x200FFFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit-addressable through bit-band alias. 0x22000000–0x23FFFFFF SRAM bit-band alias Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. 72 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 12-7. Peripheral Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses 0x40000000–0x400FFFFF Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit-addressable through bit-band alias. 0x42000000–0x43FFFFFF Peripheral bit-band region Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. Notes: 1. A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region. 2. Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size of the instruction making the bit-band access. The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where:  Bit_word_offset is the position of the target bit in the bit-band memory region.  Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.  Bit_band_base is the starting address of the alias region.  Byte_offset is the number of the byte in the bit-band region that contains the targeted bit.  Bit_number is the bit position, 0–7, of the targeted bit. Figure 12-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bitband region:  The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x200FFFFF: 0x23FFFFE0 = 0x22000000 + (0xFFFFF*32) + (0*4).  The alias word at 0x23FFFFFC maps to bit[7] of the bit-band byte at 0x200FFFFF: 0x23FFFFFC = 0x22000000 + (0xFFFFF*32) + (7*4).  The alias word at 0x22000000 maps to bit[0] of the bit-band byte at 0x20000000: 0x22000000 = 0x22000000 + (0*32) + (0*4).  The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x20000000: 0x2200001C = 0x22000000+ (0*32) + (7*4). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 73 Figure 12-4. Bit-band Mapping 32 MB alias region 0x23FFFFFC 0x23FFFFF8 0x23FFFFF4 0x23FFFFF0 0x23FFFFEC 0x23FFFFE8 0x23FFFFE4 0x23FFFFE0 0x2200001C 0x22000018 0x22000014 0x22000010 0x2200000C 0x22000008 0x22000004 0x22000000 1 MB SRAM bit-band region 7 6 5 4 3 2 1 0 7 6 0x200FFFFF 7 6 5 4 3 2 5 4 3 2 1 0 7 6 0x200FFFFE 1 0 0x20000003 7 6 5 4 3 2 0x20000002 5 4 3 2 1 0 7 6 0x200FFFFD 1 0 7 6 5 4 3 2 5 4 3 2 1 0 1 0 0x200FFFFC 1 0 7 0x20000001 6 5 4 3 2 0x20000000 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bitband region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0 writes a 0 to the bit-band bit. Bits[31:1] of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. Reading a word in the alias region:  0x00000000 indicates that the targeted bit in the bit-band region is set to 0  0x00000001 indicates that the targeted bit in the bit-band region is set to 1 Directly Accessing a Bit-band Region “Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 12.4.2.6 Memory Endianness The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0–3 hold the first stored word, and bytes 4–7 hold the second stored word. “Little-endian Format” describes how words of data are stored in memory. Little-endian Format In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and the most significant byte at the highest-numbered byte. For example: 74 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 12-5. Little-endian Format Memory 7 Register 0 31 12.4.2.7 Address A B0 A+1 B1 A+2 B2 A+3 B3 lsbyte 24 23 B3 16 15 B2 8 7 B1 0 B0 msbyte Synchronization Primitives The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a guaranteed read-modify-write memory update sequence, or for a semaphore mechanism. A pair of synchronization primitives comprises: A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that location. A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a register. If this bit is:  0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds,  1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is performed. The pairs of Load-Exclusive and Store-Exclusive instructions are:  The word instructions LDREX and STREX  The halfword instructions LDREXH and STREXH  The byte instructions LDREXB and STREXB. The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform an exclusive read-modify-write of a memory location, the software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location 4. Test the returned status bit. If this bit is: 0: The read-modify-write completed successfully. 1: No write was performed. This indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence. The software can use the synchronization primitives to implement a semaphore as follows: 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore address. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 75 3. If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the software has claimed the semaphore. However, if the Store-Exclusive instruction failed, another process might have claimed the semaphore after the software performed the first step. The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a LoadExclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory locations addressed by exclusive accesses by each processor. The processor removes its exclusive access tag if:  It executes a CLREX instruction  It executes a Store-Exclusive instruction, regardless of whether the write succeeds.  An exception occurs. This means that the processor can resolve semaphore conflicts between different threads. In a multiprocessor implementation:  Executing a CLREX instruction removes only the local exclusive access tag for the processor  Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all global exclusive access tags for the processor. For more information about the synchronization primitive instructions, see “LDREX and STREX” and “CLREX” . 12.4.2.8 Programming Hints for the Synchronization Primitives ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for generation of these instructions: Table 12-8. CMSIS Functions for Exclusive Access Instructions Instruction CMSIS Function LDREX uint32_t __LDREXW (uint32_t *addr) LDREXH uint16_t __LDREXH (uint16_t *addr) LDREXB uint8_t __LDREXB (uint8_t *addr) STREX uint32_t __STREXW (uint32_t value, uint32_t *addr) STREXH uint32_t __STREXH (uint16_t value, uint16_t *addr) STREXB uint32_t __STREXB (uint8_t value, uint8_t *addr) CLREX void __CLREX (void) The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic function. For example, the following C code generates the required LDREXB operation: __ldrex((volatile char *) 0xFF); 12.4.3 Exception Model This section describes the exception model. 12.4.3.1 Exception States Each exception is in one of the following states: Inactive The exception is not active and not pending. Pending The exception is waiting to be serviced by the processor. 76 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. Active An exception is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. Active and Pending The exception is being serviced by the processor and there is a pending exception from the same source. 12.4.3.2 Exception Types The exception types are: Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. Non Maskable Interrupt (NMI) A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be:  Masked or prevented from activation by any other exception.  Preempted by any exception other than Reset. Hard Fault A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard Faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. Memory Management Fault (MemManage) A Memory Management Fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. Bus Fault A Bus Fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. Usage Fault A Usage Fault is an exception that occurs because of a fault related to an instruction execution. This includes:  An undefined instruction  An illegal unaligned access  An invalid state on instruction execution  An error on exception return. The following can cause a Usage Fault when the core is configured to report them:  An unaligned address on word and halfword memory access  A division by zero. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 77 SVCall A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. PendSV PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. SysTick A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick. Interrupt (IRQ) A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 12-9. Properties of the Different Exception Types Exception Number (1) Irq Number (1) Exception Type Priority Vector Address or Offset (2) Activation 1 – Reset -3, the highest 0x00000004 Asynchronous 2 -14 NMI -2 0x00000008 Asynchronous 3 -13 Hard fault -1 0x0000000C – 4 -12 Memory management fault Configurable (3) 0x00000010 Synchronous 5 -11 Bus fault Configurable (3) 0x00000014 Synchronous when precise, asynchronous when imprecise 6 -10 Usage fault Configurable (3) 0x00000018 Synchronous 7–10 – – – Reserved – 0x0000002C Synchronous 11 -5 SVCall Configurable 12–13 – – – (3) Reserved – (3) 0x00000038 Asynchronous 0x0000003C 14 -2 PendSV Configurable 15 -1 SysTick Configurable (3) 16 and above Notes: 0 and above Interrupt (IRQ) (4) Configurable 0x00000040 and above Asynchronous (5) Asynchronous 1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register” . 2. See “Vector Table” for more information 3. See “System Handler Priority Registers” 4. See “Interrupt Priority Registers” 5. Increasing in steps of 4. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 12-9 shows as having configurable priority, see: 78  “System Handler Control and State Register”  “Interrupt Clear-enable Registers” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” . 12.4.3.3 Exception Handlers The processor handles exceptions using: 12.4.3.4  Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ34 are the exceptions handled by ISRs.  Fault Handlers Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers.  System Handlers NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. Vector Table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 12-6 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code. Figure 12-6. Vector Table Exception number IRQ number 255 239 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x03FC . . . 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 12 11 Vector IRQ239 . . . IRQ2 IRQ1 IRQ0 SysTick PendSV Reserved Reserved for Debug -5 10 0x002C 9 SVCall Reserved 8 7 6 -10 5 -11 4 -12 3 -13 2 -14 1 0x0018 0x0014 0x0010 0x000C 0x0008 0x0004 0x0000 Usage fault Bus fault Memory management fault Hard fault NMI Reset Initial SP value On system reset, the vector table is fixed at address 0x00000000. Privileged software can write to the SCB_VTOR to relocate the vector table start address to a different memory location, in the range 0x00000080 to 0x3FFFFF80, see “Vector Table Offset Register” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 79 12.4.3.5 Exception Priorities As Table 12-9 shows, all exceptions have an associated priority, with:  A lower priority value indicating a higher priority  Configurable priorities for all exceptions except Reset, Hard fault and NMI. If the software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities see “System Handler Priority Registers” , and “Interrupt Priority Registers” . Note: Configurable priority values are in the range 0–15. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 12.4.3.6 Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt priority register entry into two fields:  An upper field that defines the group priority  A lower field that defines a subpriority within the group. Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see “Application Interrupt and Reset Control Register” . 12.4.3.7 Exception Entry and Return Descriptions of exception handling use the following terms: Preemption When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” more information. Return This occurs when the exception handler is completed, and:  There is no pending exception with sufficient priority to be serviced  The completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” for more information. 80 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Tail-chaining This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. Late-arriving This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. Exception Entry An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode, or the new exception is of a higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means that the exception has more priority than any limits set by the mask registers, see “Exception Mask Registers” . An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred as stacking and the structure of eight data words is referred to as stack frame. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 81 Figure 12-7. Exception Stack Frame ... {aligner} FPSCR S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack Decreasing memory address IRQ top of stack Exception frame with floating-point storage ... {aligner} xPSR PC LR R12 R3 R2 R1 R0 Pre-IRQ top of stack IRQ top of stack Exception frame without floating-point storage Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the stack frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR). The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher priority exception occurs during the exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher priority exception occurs during the exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case. Exception Return An Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: 82  An LDM or POP instruction that loads the PC  An LDR instruction with the PC as the destination.  A BX instruction using any register. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. Table 12-10 shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 12-10. Exception Return Behavior EXC_RETURN[31:0] Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 12.4.3.8 Fault Handling Faults are a subset of the exceptions, see “Exception Model” . The following generate a fault:  A bus error on: ̶ An instruction fetch or vector table load ̶ A data access  An internally-detected error such as an undefined instruction  An attempt to execute an instruction from a memory region marked as Non-Executable (XN).  A privilege violation or an attempt to access an unmanaged region causing an MPU fault. Fault Types Table 12-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates that the fault has occurred. See “Configurable Fault Status Register” for more information about the fault status registers. Table 12-11. Faults Fault Handler Bus error on a vector read Bit Name VECTTBL Hard fault “Hard Fault Status Register” Fault escalated to a hard fault FORCED MPU or default memory map mismatch: – during exception stacking – IACCVIOL (1) on instruction access on data access Fault Status Register Memory management fault DACCVIOL(2) MSTKERR during exception unstacking MUNSTKERR during lazy floating-point state preservation MLSPERR(3) “MMFSR: Memory Management Fault Status Subregister” SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 83 Table 12-11. Faults (Continued) Fault Handler Bus error: Bit Name Fault Status Register – – during exception stacking STKERR during exception unstacking UNSTKERR during instruction prefetch Bus fault IBUSERR LSPERR(3) during lazy floating-point state preservation Precise data bus error PRECISERR Imprecise data bus error IMPRECISERR Attempt to access a coprocessor NOCP Undefined instruction UNDEFINSTR Attempt to enter an invalid instruction set state “BFSR: Bus Fault Status Subregister” INVSTATE Usage fault “UFSR: Usage Fault Status Subregister” Invalid EXC_RETURN value INVPC Illegal unaligned load or store UNALIGNED Divide By 0 DIVBYZERO Notes: 1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled. 2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with ICI continuation. 3. Only present in a Cortex-M4F device Fault Escalation and Hard Faults All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers” . The software can disable the execution of the handlers for these faults, see “System Handler Control and State Register” . Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in “Exception Model” . In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when:  A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself; it must have the same priority as the current priority level.  A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler for the new fault cannot preempt the currently executing fault handler.  An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception.  A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 12-12. 84 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 12-12. Fault Status and Fault Address Registers Handler Status Register Name Address Register Name Register Description Hard fault SCB_HFSR – “Hard Fault Status Register” Memory management fault MMFSR SCB_MMFAR Bus fault BFSR SCB_BFAR Usage fault UFSR – “MMFSR: Memory Management Fault Status Subregister” “MemManage Fault Address Register” “BFSR: Bus Fault Status Subregister” “Bus Fault Address Register” “UFSR: Usage Fault Status Subregister” Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in lockup state, it does not execute any instructions. The processor remains in lockup state until either:  It is reset  An NMI occurs  It is halted by a debugger. Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 85 12.5 Power Management The Cortex-M4 processor sleep modes reduce the power consumption:  Sleep mode stops the processor clock  Deep sleep mode stops the system clock and switches off the PLL and flash memory. The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” . This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode. 12.5.1 Entering Sleep Mode This section describes the mechanisms software can use to put the processor into sleep mode. The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore, the software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 12.5.1.1 Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI instruction it stops executing instructions and enters sleep mode. See “WFI” for more information. 12.5.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of an one-bit event register. When the processor executes a WFE instruction, it checks this register:  If the register is 0, the processor stops executing instructions and enters sleep mode  If the register is 1, the processor clears the register to 0 and continues executing instructions without entering sleep mode. See “WFE” for more information. 12.5.1.3 Sleep-on-exit If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception handler, it returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the processor to run when an exception occurs. 12.5.2 Wakeup from Sleep Mode The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 12.5.2.1 Wakeup from WFI or Sleep-on-exit Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than the current exception priority, the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULTMASK, see “Exception Mask Registers” . 12.5.2.2 Wakeup from WFE The processor wakes up if: 86  It detects an exception with sufficient priority to cause an exception entry  It detects an external event signal. See “External Event Input”  In a multiprocessor system, another processor in the system executes an SEV instruction. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause an exception entry. For more information about the SCR, see “System Control Register” . 12.5.2.3 External Event Input The processor provides an external event input signal. Peripherals can drive this signal, either to wake the processor from WFE, or to set the internal WFE event register to 1 to indicate that the processor must not enter sleep mode on a later WFE instruction. See “Wait for Event” for more information. 12.5.3 Power Management Programming Hints ISO/IEC C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following functions for these instructions: void __WFE(void) // Wait for Event void __WFI(void) // Wait for Interrupt SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 87 12.6 Cortex-M4 Instruction Set 12.6.1 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions.  Angle brackets, , enclose alternative forms of the operand  Braces, {}, enclose optional operands  The Operands column is not exhaustive  Op2 is a flexible second operand that can be either a register or a constant  Most instructions can use an optional condition code suffix. For more information on the instructions and operands, see the instruction descriptions. Table 12-13. Cortex-M4 Instructions Mnemonic Operands Description Flags ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V ADR Rd, label Load PC-relative address – AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C ASR, ASRS Rd, Rm, Arithmetic Shift Right N,Z,C B label Branch – BFC Rd, #lsb, #width Bit Field Clear – BFI Rd, Rn, #lsb, #width Bit Field Insert – BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C BKPT #imm Breakpoint – BL label Branch with Link – BLX Rm Branch indirect with Link – BX Rm Branch indirect – CBNZ Rn, label Compare and Branch if Non Zero – CBZ Rn, label Compare and Branch if Zero – CLREX – Clear Exclusive – CLZ Rd, Rm Count leading zeros – CMN Rn, Op2 Compare Negative N,Z,C,V CMP Rn, Op2 Compare N,Z,C,V CPSID i Change Processor State, Disable Interrupts – CPSIE i Change Processor State, Enable Interrupts – DMB – Data Memory Barrier – DSB – Data Synchronization Barrier – EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C ISB – Instruction Synchronization Barrier – IT – If-Then condition block – LDM Rn{!}, reglist Load Multiple registers, increment after – 88 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before – LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after – LDR Rt, [Rn, #offset] Load Register with word – LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte – LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes – LDREX Rt, [Rn, #offset] Load Register Exclusive – LDREXB Rt, [Rn] Load Register Exclusive with byte – LDREXH Rt, [Rn] Load Register Exclusive with halfword – LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword – LDRSB, DRSBT Rt, [Rn, #offset] Load Register with signed byte – LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword – LDRT Rt, [Rn, #offset] Load Register with word – LSL, LSLS Rd, Rm, Logical Shift Left N,Z,C LSR, LSRS Rd, Rm, Logical Shift Right N,Z,C MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result – MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result – MOV, MOVS Rd, Op2 Move N,Z,C MOVT Rd, #imm16 Move Top – MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C MRS Rd, spec_reg Move from special register to general register – MSR spec_reg, Rm Move from general register to special register N,Z,C,V MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z MVN, MVNS Rd, Op2 Move NOT N,Z,C NOP – No Operation – ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword – POP reglist Pop registers from stack – PUSH reglist Push registers onto stack – QADD {Rd,} Rn, Rm Saturating double and Add Q QADD16 {Rd,} Rn, Rm Saturating Add 16 – QADD8 {Rd,} Rn, Rm Saturating Add 8 – QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange – QDADD {Rd,} Rn, Rm Saturating Add Q QDSUB {Rd,} Rn, Rm Saturating double and Subtract Q QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange – QSUB {Rd,} Rn, Rm Saturating Subtract Q SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 89 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 – QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 – RBIT Rd, Rn Reverse Bits – REV Rd, Rn Reverse byte order in a word – REV16 Rd, Rn Reverse byte order in each halfword – REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend – ROR, RORS Rd, Rm, Rotate Right N,Z,C RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V SADD16 {Rd,} Rn, Rm Signed Add 16 GE SADD8 {Rd,} Rn, Rm Signed Add 8 and Subtract with Exchange GE SASX {Rd,} Rn, Rm Signed Add GE SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract – SDIV {Rd,} Rn, Rm Signed Divide – SEL {Rd,} Rn, Rm Select bytes – SEV – Send Event – SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 – SHADD8 {Rd,} Rn, Rm Signed Halving Add 8 – SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange – SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange – SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16 – SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 – SMLABB, SMLABT, SMLATB, SMLATT Rd, Rn, Rm, Ra Signed Multiply Accumulate Long (halfwords) Q SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 × 32 + 64), 64-bit result – SMLALBB, SMLALBT, SMLALTB, SMLALTT RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords – SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual – SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multiply Accumulate, word by halfword Q SMLSD Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q SMLSLD RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual SMMLA Rd, Rn, Rm, Ra Signed Most significant word Multiply Accumulate – SMMLS, SMMLR Rd, Rn, Rm, Ra Signed Most significant word Multiply Subtract – SMMUL, SMMULR {Rd,} Rn, Rm Signed Most significant word Multiply – SMUAD {Rd,} Rn, Rm Signed dual Multiply Add Q 90 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags SMULBB, SMULBT SMULTB, SMULTT {Rd,} Rn, Rm Signed Multiply (halfwords) – SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 × 32), 64-bit result – SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword – SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract – SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q SSAT16 Rd, #n, Rm Signed Saturate 16 Q SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE SSUB16 {Rd,} Rn, Rm Signed Subtract 16 – SSUB8 {Rd,} Rn, Rm Signed Subtract 8 – STM Rn{!}, reglist Store Multiple registers, increment after – STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before – STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after – STR Rt, [Rn, #offset] Store Register word – STRB, STRBT Rt, [Rn, #offset] Store Register byte – STRD Rt, Rt2, [Rn, #offset] Store Register two words – STREX Rd, Rt, [Rn, #offset] Store Register Exclusive – STREXB Rd, Rt, [Rn] Store Register Exclusive byte – STREXH Rd, Rt, [Rn] Store Register Exclusive halfword – STRH, STRHT Rt, [Rn, #offset] Store Register halfword – STRT Rt, [Rn, #offset] Store Register word – SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V SVC #imm Supervisor Call – SXTAB {Rd,} Rn, Rm,{,ROR #} Extend 8 bits to 32 and add – SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add – SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add – SXTB16 {Rd,} Rm {,ROR #n} Signed Extend Byte 16 – SXTB {Rd,} Rm {,ROR #n} Sign extend a byte – SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword – TBB [Rn, Rm] Table Branch Byte – TBH [Rn, Rm, LSL #1] Table Branch Halfword – TEQ Rn, Op2 Test Equivalence N,Z,C TST Rn, Op2 Test N,Z,C UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE USAX {Rd,} Rn, Rm Unsigned Subtract and Add with Exchange GE SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 91 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags UHADD16 {Rd,} Rn, Rm Unsigned Halving Add 16 – UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 – UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchange – UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange – UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 – UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 – UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract – UDIV {Rd,} Rn, Rm Unsigned Divide – UMAAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result – UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result – UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 × 32), 64-bit result – UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 – UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 – UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange – UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange – UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 – UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 – USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences – USADA8 {Rd,} Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate – USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q USAT16 Rd, #n, Rm Unsigned Saturate 16 Q UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE UXTAB {Rd,} Rn, Rm,{,ROR #} Rotate, extend 8 bits to 32 and Add – UXTAB16 {Rd,} Rn, Rm,{,ROR #} Rotate, dual extend 8 bits to 16 and Add – UXTAH {Rd,} Rn, Rm,{,ROR #} Rotate, unsigned extend and Add Halfword – UXTB {Rd,} Rm {,ROR #n} Zero extend a byte – UXTB16 {Rd,} Rm {,ROR #n} Unsigned Extend Byte 16 – UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword – VABS.F32 Sd, Sm Floating-point Absolute – VADD.F32 {Sd,} Sn, Sm Floating-point Add – VCMP.F32 Sd, Compare two floating-point registers, or one floating-point register and zero FPSCR VCMPE.F32 Sd, Compare two floating-point registers, or one floating-point register and zero with Invalid Operation check FPSCR VCVT.S32.F32 Sd, Sm Convert between floating-point and integer – 92 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 12-13. Cortex-M4 Instructions (Continued) Mnemonic Operands Description Flags VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point – VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding – VCVT.F32.F16 Sd, Sm Converts half-precision value to single-precision – VCVTT.F32.F16 Sd, Sm Converts single-precision register to half-precision – VDIV.F32 {Sd,} Sn, Sm Floating-point Divide – VFMA.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate – VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate – VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract – VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract – VLDM.F Rn{!}, list Load Multiple extension registers – VLDR.F , [Rn] Load an extension register from memory – VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate – VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract – VMOV.F32 Sd, #imm Floating-point Move immediate – VMOV Sd, Sm Floating-point Move register – VMOV Sn, Rt Copy ARM core register to single precision – VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 single precision – VMOV Dd[x], Rt Copy ARM core register to scalar – VMOV Rt, Dn[x] Copy scalar to ARM core register – VMRS Rt, FPSCR Move FPSCR to ARM core register or APSR N,Z,C,V VMSR FPSCR, Rt Move to FPSCR from ARM Core register FPSCR VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply – VNEG.F32 Sd, Sm Floating-point Negate – VNMLA.F32 Sd, Sn, Sm Floating-point Multiply and Add – VNMLS.F32 Sd, Sn, Sm Floating-point Multiply and Subtract – VNMUL {Sd,} Sn, Sm Floating-point Multiply – VPOP list Pop extension registers – VPUSH list Push extension registers – VSQRT.F32 Sd, Sm Calculates floating-point Square Root – VSTM Rn{!}, list Floating-point register Store Multiple – VSTR.F Sd, [Rn] Stores an extension register to memory – VSUB.F {Sd,} Sn, Sm Floating-point Subtract – WFE – Wait For Event – WFI – Wait For Interrupt – 12.6.2 CMSIS Functions ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 93 does not support an appropriate intrinsic function, the user might have to use inline assembler to access some instructions. The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access: Table 12-14. CMSIS Functions to Generate some Cortex-M4 Instructions Instruction CMSIS Function CPSIE I void __enable_irq(void) CPSID I void __disable_irq(void) CPSIE F void __enable_fault_irq(void) CPSID F void __disable_fault_irq(void) ISB void __ISB(void) DSB void __DSB(void) DMB void __DMB(void) REV uint32_t __REV(uint32_t int value) REV16 uint32_t __REV16(uint32_t int value) REVSH uint32_t __REVSH(uint32_t int value) RBIT uint32_t __RBIT(uint32_t int value) SEV void __SEV(void) WFE void __WFE(void) WFI void __WFI(void) The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions: Table 12-15. CMSIS Intrinsic Functions to Access the Special Registers Special Register Access CMSIS Function Read uint32_t __get_PRIMASK (void) Write void __set_PRIMASK (uint32_t value) Read uint32_t __get_FAULTMASK (void Write void __set_FAULTMASK (uint32_t value) Read uint32_t __get_BASEPRI (void) Write void __set_BASEPRI (uint32_t value) Read uint32_t __get_CONTROL (void) Write void __set_CONTROL (uint32_t value) Read uint32_t __get_MSP (void) Write void __set_MSP (uint32_t TopOfMainStack) Read uint32_t __get_PSP (void) Write void __set_PSP (uint32_t TopOfProcStack) PRIMASK FAULTMASK BASEPRI CONTROL MSP PSP 94 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.3 Instruction Descriptions 12.6.3.1 Operands An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the operands and often store the result in a destination register. When there is a destination register in the instruction, it is usually specified before the operands. Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” . 12.6.3.2 Restrictions when Using PC or SP Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands or destination register can be used. See instruction descriptions for more information. Note: 12.6.3.3 Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution, because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb instructions. Flexible Second Operand Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the descriptions of the syntax of each instruction. Operand2 can be a:  “Constant”  “Register with Optional Shift” Constant Specify an Operand2 constant in the form: #constant where constant can be:  Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word  Any constant of the form 0x00XY00XY  Any constant of the form 0xXY00XY00  Any constant of the form 0xXYXYXYXY. Note: In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions. When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant. Instruction Substitution The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the equivalent instruction CMN Rd, #0x2. Register with Optional Shift Specify an Operand2 register in the form: Rm {, shift} where: Rm is the register holding the data for the second operand. shift is an optional shift to be applied to Rm. It can be one of: SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 95 ASR #n arithmetic shift right n bits, 1 ≤ n ≤ 32. LSL #n logical shift left n bits, 1 ≤ n ≤ 31. LSR #n logical shift right n bits, 1 ≤ n ≤ 32. ROR #n rotate right n bits, 1 ≤ n ≤ 31. RRX rotate right one bit, with extend. - if omitted, no shift occurs, equivalent to LSL #0. If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm. If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions. For information on the shift operations and how they affect the carry flag, see “Flexible Second Operand” . 12.6.3.4 Shift Operations Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed:  Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register  During the calculation of Operand2 by the instructions that specify the second operand as a register with shift. See “Flexible Second Operand” . The result is used by the instruction. The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following subsections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length. ASR Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result. See Figure 12-8. The ASR #n operation can be used to divide the value in the register Rm by 2n, with the result being rounded towards negative-infinity. When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.  If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.  If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm. Figure 12-8. ASR #3 &DUU\ )ODJ        LSR Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the righthand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 12-9. 96 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an unsigned integer. When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.  If n is 32 or more, then all the bits in the result are cleared to 0.  If n is 33 or more and the carry flag is updated, it is updated to 0. Figure 12-9. LSR #3 &DUU\ )ODJ           LSL Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 12-10. The LSL #n operation can be used to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning. When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.  If n is 32 or more, then all the bits in the result are cleared to 0.  If n is 33 or more and the carry flag is updated, it is updated to 0. Figure 12-10. LSL #3           &DUU\ )ODJ ROR Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n bits of the result; and it moves the right-hand n bits of the register into the left-hand n bits of the result. See Figure 12-11. When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm.  If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to bit[31] of Rm.  ROR with shift length, n, more than 32 is the same as ROR with shift length n-32. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 97 Figure 12-11. ROR #3 &DUU\ )ODJ        RRX Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into bit[31] of the result. See Figure 12-12. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm. Figure 12-12. RRX &DUU\ )ODJ   12.6.3.5   Address Alignment An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned. The Cortex-M4 processor supports unaligned access only for the following instructions:  LDR, LDRT  LDRH, LDRHT  LDRSH, LDRSHT  STR, STRT  STRH, STRHT All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore their accesses must be address-aligned. For more information about usage faults, see “Fault Handling” . Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses, see “Configuration and Control Register” . 12.6.3.6 PC-relative Expressions A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error.  98 For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15  For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.  Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number]. 12.6.3.7 Conditional Execution Most data processing instructions can optionally update the condition flags in the Application Program Status Register (APSR) according to the result of the operation, see “Application Program Status Register” . Some instructions update all flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect. An instruction can be executed conditionally, based on the condition flags set in another instruction, either:  Immediately after the instruction that updated the flags  After any number of intervening instructions that have not updated the flags. Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See Table 12-16 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction:  Does not execute  Does not write any value to its destination register  Does not affect any of the flags  Does not generate any exception. Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” for more information and restrictions when using the IT instruction. Depending on the vendor, the assembler might automatically insert an IT instruction if there are conditional instructions outside the IT block. The CBZ and CBNZ instructions are used to compare the value of a register against zero and branch on the result. This section describes:  “Condition Flags”  “Condition Code Suffixes” . Condition Flags The APSR contains the following condition flags: N Set to 1 when the result of the operation was negative, cleared to 0 otherwise. Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise. C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise. V Set to 1 when the operation caused overflow, cleared to 0 otherwise. For more information about the APSR, see “Program Status Register” . A carry occurs:  If the result of an addition is greater than or equal to 232  If the result of a subtraction is positive or zero  As the result of an inline barrel shifter operation in a move or logical instruction. An overflow occurs when the sign of the result, in bit[31], does not match the sign of the result, had the operation been performed at infinite precision, for example:  If adding two negative values results in a positive value  If adding two positive values results in a negative value  If subtracting a positive value from a negative value generates a positive value SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 99  If subtracting a negative value from a positive value generates a negative value. The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is discarded. See the instruction descriptions for more information. Note: Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more information. Condition Code Suffixes The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR meet the specified condition. Table 12-16 shows the condition codes to use. A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code. Table 12-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 12-16. Condition Code Suffixes Suffix Flags Meaning EQ Z=1 Equal NE Z=0 Not equal CS or HS C=1 Higher or same, unsigned ≥ CC or LO C=0 Lower, unsigned < MI N=1 Negative PL N=0 Positive or zero VS V=1 Overflow VC V=0 No overflow HI C = 1 and Z = 0 Higher, unsigned > LS C = 0 or Z = 1 Lower or same, unsigned ≤ GE N=V Greater than or equal, signed ≥ LT N != V Less than, signed < GT Z = 0 and N = V Greater than, signed > LE Z = 1 and N != V Less than or equal, signed ≤ AL Can have any value Always. This is the default when no suffix is specified. Absolute Value The example below shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1). MOVS R0, R1 ; R0 = R1, setting flags IT MI ; IT instruction for the negative condition RSBMI R0, R1, #0 ; If negative, R0 = -R1 Compare and Update Value The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater than R1 and R2 is greater than R3. CMP R0, R1 ; Compare R0 and R1, setting flags ITT GT ; IT instruction for the two GT conditions CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags MOVGT R4, R5 ; If still 'greater than', do R4 = R5 100 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.3.8 Instruction Width Selection There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, the user can force a specific instruction size by using an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction encoding. If the user specifies an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width, it generates an error. Note: In some cases, it might be necessary to specify the .W suffix, for example if the operand is the label of an instruction or literal data, as in the case of branch instructions. This is because the assembler might not automatically generate the right size encoding. To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The example below shows instructions with the instruction width suffix. BCS.W label ; creates a 32-bit instruction even for a short ; branch ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same ; operation can be done by a 16-bit instruction SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 101 12.6.4 Memory Access Instructions The table below shows the memory access instructions. Table 12-17. 102 Memory Access Instructions Mnemonic Description ADR Load PC-relative address CLREX Clear Exclusive LDM{mode} Load Multiple registers LDR{type} Load Register using immediate offset LDR{type} Load Register using register offset LDR{type}T Load Register with unprivileged access LDR Load Register using PC-relative address LDRD Load Register Dual LDREX{type} Load Register Exclusive POP Pop registers from stack PUSH Push registers onto stack STM{mode} Store Multiple registers STR{type} Store Register using immediate offset STR{type} Store Register using register offset STR{type}T Store Register with unprivileged access STREX{type} Store Register Exclusive SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.4.1 ADR Load PC-relative address. Syntax ADR{cond} Rd, label where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. label is a PC-relative expression. See “PC-relative Expressions” . Operation ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register. ADR produces position-independent code, because the address is PC-relative. If ADR is used to generate a target address for a BX or BLX instruction, ensure that bit[0] of the address generated is set to 1 for correct execution. Values of label must be within the range of −4095 to +4095 from the address in the PC. Note: The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not wordaligned. See “Instruction Width Selection” . Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. Examples ADR R1, TextMessage ; Write address value of a location labelled as ; TextMessage to R1 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 103 12.6.4.2 LDR and STR, Immediate Offset Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset. Syntax op{type}{cond} Rt, op{type}{cond} Rt, op{type}{cond} Rt, opD{cond} Rt, Rt2, opD{cond} Rt, Rt2, opD{cond} Rt, Rt2, [Rn {, #offset}] [Rn, #offset]! [Rn], #offset [Rn {, #offset}] [Rn, #offset]! [Rn], #offset ; ; ; ; ; ; immediate offset pre-indexed post-indexed immediate offset, two words pre-indexed, two words post-indexed, two words where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn. If offset is omitted, the address is the contents of Rn. Rt2 is the additional register to load or store for two-word operations. Operation LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes: Offset Addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is: [Rn, #offset] 104 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Pre-indexed Addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! Post-indexed Addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned. See “Address Alignment” . The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms. Table 12-18. Offset Ranges Instruction Type Immediate Offset Pre-indexed Post-indexed Word, halfword, signed halfword, byte, or signed byte -255 to 4095 -255 to 255 -255 to 255 Two words multiple of 4 in the range -1020 to 1020 multiple of 4 in the range -1020 to 1020 multiple of 4 in the range -1020 to 1020 Restrictions For load instructions:  Rt can be SP or PC for word loads only  Rt must be different from Rt2 for two-word loads  Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. When Rt is PC in a word load instruction:  Bit[0] of the loaded value must be 1 for correct execution  A branch occurs to the address created by changing bit[0] of the loaded value to 0  If the instruction is conditional, it must be the last instruction in the IT block. For store instructions:  Rt can be SP for word stores only  Rt must not be PC  Rn must not be PC  Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. Condition Flags These instructions do not change the flags. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 105 Examples LDR LDRNE R8, [R10] R2, [R5, #960]! STR R2, [R9,#const-struc] STRH R3, [R4], #4 LDRD R8, R9, [R3, #0x20] STRD R0, R1, [R8], #-16 12.6.4.3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; Loads R8 from the address in R10. Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960. const-struc is an expression evaluating to a constant in the range 0-4095. Store R3 as halfword data into address in R4, then increment R4 by 4 Load R8 from a word 32 bytes above the address in R3, and load R9 from a word 36 bytes above the address in R3 Store R0 to address in R8, and store R1 to a word 4 bytes above the address in R8, and then decrement R8 by 16. LDR and STR, Register Offset Load and Store with register offset. Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}] where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rn is the register on which the memory address is based. Rm is a register containing a value to be used as the offset. LSL #n is an optional shift, with n in the range 0 to 3. Operation LDR instructions load a register with a value from memory. STR instructions store a register value into memory. The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address Alignment” . Restrictions In these instructions:  106 Rn must not be PC SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15  Rm must not be SP and must not be PC  Rt can be SP only for word loads and word stores  Rt can be PC only for word loads. When Rt is PC in a word load instruction:  Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address  If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples STR LDRSB STR R0, [R5, R1] ; ; R0, [R5, R1, LSL #1] ; ; ; R0, [R1, R2, LSL #2] ; ; Store value of R0 into an address equal to sum of R5 and R1 Read byte value from an address equal to sum of R5 and two times R1, sign extended it to a word value and put it in R0 Stores R0 to an address equal to sum of R1 and four times R2 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 107 12.6.4.4 LDR and STR, Unprivileged Load and Store with unprivileged access. Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset where: op is one of: LDR Load Register. STR Store Register. type is one of: B unsigned byte, zero extend to 32 bits on loads. SB signed byte, sign extend to 32 bits (LDR only). H unsigned halfword, zero extend to 32 bits on loads. SH signed halfword, sign extend to 32 bits (LDR only). - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an offset from Rn and can be 0 to 255. If offset is omitted, the address is the value in Rn. Operation These load and store instructions perform the same function as the memory access instructions with immediate offset, see “LDR and STR, Immediate Offset” . The difference is that these instructions have only unprivileged access even when used in privileged software. When used in unprivileged software, these instructions behave in exactly the same way as normal memory access instructions with immediate offset. Restrictions In these instructions:  Rn must not be PC  Rt must not be SP and must not be PC. Condition Flags These instructions do not change the flags. Examples 108 STRBTEQ R4, [R7] LDRHT R2, [R2, #8] ; ; ; ; Conditionally store least significant byte in R4 to an address in R7, with unprivileged access Load halfword value from an address equal to sum of R2 and 8 into R2, with unprivileged access SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.4.5 LDR, PC-relative Load register from memory. Syntax LDR{type}{cond} Rt, label LDRD{cond} Rt, Rt2, label ; Load two words where: type is one of: B unsigned byte, zero extend to 32 bits. SB signed byte, sign extend to 32 bits. H unsigned halfword, zero extend to 32 bits. SH signed halfword, sign extend to 32 bits. - omit, for word. cond is an optional condition code, see “Conditional Execution” . Rt is the register to load or store. Rt2 is the second register to load or store. label is a PC-relative expression. See “PC-relative Expressions” . Operation LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by an offset from the PC. The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be signed or unsigned. See “Address Alignment” . label must be within a limited range of the current instruction. The table below shows the possible offsets between label and the PC. Table 12-19. Offset Ranges Instruction Type Offset Range Word, halfword, signed halfword, byte, signed byte -4095 to 4095 Two words -1020 to 1020 The user might have to use the .W suffix to get the maximum offset range. See “Instruction Width Selection” . Restrictions In these instructions:  Rt can be SP or PC only for word loads  Rt2 must not be SP and must not be PC  Rt must be different from Rt2. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 109 When Rt is PC in a word load instruction:  Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address  If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples LDR R0, LookUpTable LDRSB R7, localdata 12.6.4.6 ; ; ; ; ; Load R0 with a word of data from an address labelled as LookUpTable Load a byte value from an address labelled as localdata, sign extend it to a word value, and put it in R7 LDM and STM Load and Store Multiple registers. Syntax op{addr_mode}{cond} Rn{!}, reglist where: op is one of: LDM Load Multiple registers. STM Store Multiple registers. addr_mode is any one of the following: IA Increment address After each access. This is the default. DB Decrement address Before each access. cond is an optional condition code, see “Conditional Execution” . Rn is the register on which the memory addresses are based. ! is an optional writeback suffix. If ! is present, the final address, that is loaded from or stored to, is written back into Rn. reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range, see “Examples” . LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending stacks. LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks. STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending stacks. STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks Operation LDM instructions load the registers in reglist with word values from memory addresses based on Rn. STM instructions store the word values in the registers in reglist to memory addresses based on Rn. For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the 110 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing register numbers, with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn. The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” for details. Restrictions In these instructions:  Rn must not be PC  reglist must not contain SP  In any STM instruction, reglist must not contain PC  In any LDM instruction, reglist must not contain PC if it contains LR  reglist must not contain Rn if the writeback suffix is specified. When PC is in reglist in an LDM instruction:  Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address  If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples LDM STMDB R8,{R0,R2,R9} ; LDMIA is a synonym for LDM R1!,{R3-R6,R11,R12} Incorrect Examples STM LDM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable R2, {} ; There must be at least one register in the list SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 111 12.6.4.7 PUSH and POP Push registers onto, and pop registers off a full-descending stack. Syntax PUSH{cond} reglist POP{cond} reglist where: cond is an optional condition code, see “Conditional Execution” . reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range. PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based on SP, and with the final address for the access written back to the SP. PUSH and POP are the preferred mnemonics in these cases. Operation PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address. See “LDM and STM” for more information. Restrictions In these instructions:  reglist must not contain SP  For the PUSH instruction, reglist must not contain PC  For the POP instruction, reglist must not contain PC if it contains LR. When PC is in reglist in a POP instruction:  Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfwordaligned address  If the instruction is conditional, it must be the last instruction in the IT block. Condition Flags These instructions do not change the flags. Examples PUSH PUSH POP 112 {R0,R4-R7} {R2,LR} {R0,R10,PC} SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.4.8 LDREX and STREX Load and Store Register Exclusive. Syntax LDREX{cond} Rt, [Rn {, #offset}] STREX{cond} Rd, Rt, [Rn {, #offset}] LDREXB{cond} Rt, [Rn] STREXB{cond} Rd, Rt, [Rn] LDREXH{cond} Rt, [Rn] STREXH{cond} Rd, Rt, [Rn] where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register for the returned status. Rt is the register to load or store. Rn is the register on which the memory address is based. offset is an optional offset applied to the value in Rn. If offset is omitted, the address is the value in Rn. Operation LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address. STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address. The address used in any Store-Exclusive instruction must be the same as the address in the most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see “Synchronization Primitives” . If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is guaranteed that no other process in the system has accessed the memory location between the Load-exclusive and Store-Exclusive instructions. For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and StoreExclusive instruction to a minimum. The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding Load-Exclusive instruction is unpredictable. Restrictions In these instructions:  Do not use PC  Do not use SP for Rd and Rt  For STREX, Rd must be different from both Rt and Rn  The value of offset must be a multiple of four in the range 0–1020. Condition Flags These instructions do not change the flags. Examples MOV LDREX CMP R1, #0x1 R0, [LockAddr] R0, #0 ; Initialize the ‘lock taken’ value try ; Load the lock value ; Is the lock free? SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 113 ITT STREXEQ CMPEQ BNE .... 12.6.4.9 EQ R0, R1, [LockAddr] R0, #0 try ; ; ; ; ; IT instruction for STREXEQ and CMPEQ Try and claim the lock Did this succeed? No – try again Yes – we have the lock CLREX Clear Exclusive. Syntax CLREX{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write a 1 to its destination register and fail to perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation. See “Synchronization Primitives” for more information. Condition Flags These instructions do not change the flags. Examples CLREX 114 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.5 General Data Processing Instructions The table below shows the data processing instructions. Table 12-20. Data Processing Instructions Mnemonic Description ADC Add with Carry ADD Add ADDW Add AND Logical AND ASR Arithmetic Shift Right BIC Bit Clear CLZ Count leading zeros CMN Compare Negative CMP Compare EOR Exclusive OR LSL Logical Shift Left LSR Logical Shift Right MOV Move MOVT Move Top MOVW Move 16-bit constant MVN Move NOT ORN Logical OR NOT ORR Logical OR RBIT Reverse Bits REV Reverse byte order in a word REV16 Reverse byte order in each halfword REVSH Reverse byte order in bottom halfword and sign extend ROR Rotate Right RRX Rotate Right with Extend RSB Reverse Subtract SADD16 Signed Add 16 SADD8 Signed Add 8 SASX Signed Add and Subtract with Exchange SSAX Signed Subtract and Add with Exchange SBC Subtract with Carry SHADD16 Signed Halving Add 16 SHADD8 Signed Halving Add 8 SHASX Signed Halving Add and Subtract with Exchange SHSAX Signed Halving Subtract and Add with Exchange SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 115 Table 12-20. 116 Data Processing Instructions (Continued) Mnemonic Description SHSUB16 Signed Halving Subtract 16 SHSUB8 Signed Halving Subtract 8 SSUB16 Signed Subtract 16 SSUB8 Signed Subtract 8 SUB Subtract SUBW Subtract TEQ Test Equivalence TST Test UADD16 Unsigned Add 16 UADD8 Unsigned Add 8 UASX Unsigned Add and Subtract with Exchange USAX Unsigned Subtract and Add with Exchange UHADD16 Unsigned Halving Add 16 UHADD8 Unsigned Halving Add 8 UHASX Unsigned Halving Add and Subtract with Exchange UHSAX Unsigned Halving Subtract and Add with Exchange UHSUB16 Unsigned Halving Subtract 16 UHSUB8 Unsigned Halving Subtract 8 USAD8 Unsigned Sum of Absolute Differences USADA8 Unsigned Sum of Absolute Differences and Accumulate USUB16 Unsigned Subtract 16 USUB8 Unsigned Subtract 8 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: op is one of: ADD Add. ADC Add with Carry. SUB Subtract. SBC Subtract with Carry. RSB Reverse Subtract. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. imm12 is any value in the range 0–4095. Operation The ADD instruction adds the value of Operand2 or imm12 to the value in Rn. The ADC instruction adds the values in Rn and Operand2, together with the carry flag. The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn. The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one. The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2. Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on. See also “ADR” . Note: ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax that uses the imm12 operand. Restrictions In these instructions:  Operand2 must not be SP and must not be PC  Rd can be SP only in ADD and SUB, and only with the additional restrictions: ̶ Rn must also be SP ̶ Any shift in Operand2 must be limited to a maximum of 3 bits using LSL  Rn can be SP only in ADD and SUB  Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where: ̶ The user must not specify the S suffix ̶ Rm must not be PC and must not be SP SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 117 ̶  If the instruction is conditional, it must be the last instruction in the IT block With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with the additional restrictions: ̶ The user must not specify the S suffix ̶ The second operand must be a constant in the range 0 to 4095. ̶ Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before performing the calculation, making the base address for the calculation word-aligned. ̶ Note: To generate the address of an instruction, the constant based on the value of the PC must be adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because the assembler automatically calculates the correct constant for the ADR instruction. When Rd is PC in the ADD{cond} PC, PC, Rm instruction:  Bit[0] of the value written to the PC is ignored  A branch occurs to the address created by forcing bit[0] of that value to 0. Condition Flags If S is specified, these instructions update the N, Z, C and V flags according to the result. Examples ADD SUBS RSB ADCHI R2, R1, R3 R8, R6, #240 R4, R4, #1280 R11, R0, R3 ; ; ; ; Sets the flags on the result Subtracts contents of R4 from 1280 Only executed if C flag set and Z flag clear. Multiword Arithmetic Examples The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5. 64-bit Addition Example ADDS R4, R0, R2 ADC R5, R1, R3 ; add the least significant words ; add the most significant words with carry Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9, and R2. 96-bit Subtraction Example SUBS R6, R6, R9 SBCS R9, R2, R1 SBC R2, R8, R11 12.6.5.2 ; subtract the least significant words ; subtract the middle words with carry ; subtract the most significant words with carry AND, ORR, EOR, BIC, and ORN Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT. Syntax op{S}{cond} {Rd,} Rn, Operand2 where: op is one of: AND logical AND. ORR logical OR, or bit set. EOR logical Exclusive OR. BIC logical AND NOT, or bit clear. ORN logical OR NOT. 118 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. Operation The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2. The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2. Restrictions Do not use SP and do not use PC. Condition Flags If S is specified, these instructions:  Update the N and Z flags according to the result  Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”  Do not affect the V flag. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 119 Examples AND ORREQ ANDS EORS BIC ORN ORNS 12.6.5.3 R9, R2, #0xFF00 R2, R0, R5 R9, R8, #0x19 R7, R11, #0x18181818 R0, R1, #0xab R7, R11, R14, ROR #4 R7, R11, R14, ASR #32 ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op is one of: ASR Arithmetic Shift Right. LSL Logical Shift Left. LSR Logical Shift Right. ROR Rotate Right. S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . Rd is the destination register. Rm is the register holding the value to be shifted. Rs is the register holding the shift length to apply to the value in Rm. Only the least significant byte is used and can be in the range 0 to 255. n is the shift length. The range of shift length depends on the instruction: ASR shift length from 1 to 32 LSL shift length from 0 to 31 LSR shift length from 1 to 32 ROR shift length from 0 to 31 MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0. Operation ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by constant n or register Rs. RRX moves the bits in register Rm to the right by 1. In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on what result is generated by the different instructions, see “Shift Operations” . Restrictions Do not use SP and do not use PC. Condition Flags 120 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 If S is specified:  These instructions update the N and Z flags according to the result  The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” . Examples ASR SLS LSR ROR RRX 12.6.5.4 R7, R1, R4, R4, R4, R8, R2, R5, R5, R5 #9 #3 #6 R6 ; ; ; ; ; Arithmetic shift right by 9 bits Logical shift left by 3 bits with flag update Logical shift right by 6 bits Rotate right by the value in the bottom byte of R6 Rotate right with extend. CLZ Count Leading Zeros. Syntax CLZ{cond} Rd, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the operand register. Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value is 32 if no bits are set and zero if bit[31] is set. Restrictions Do not use SP and do not use PC. Condition Flags This instruction does not change the flags. Examples CLZ CLZNE R4,R9 R2,R3 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 121 12.6.5.5 CMP and CMN Compare and Compare Negative. Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see “Conditional Execution” . Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. Operation These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do not write the result to a register. The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS instruction, except that the result is discarded. The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction, except that the result is discarded. Restrictions In these instructions:  Do not use PC  Operand2 must not be SP. Condition Flags These instructions update the N, Z, C and V flags according to the result. Examples CMP CMN CMPGT 122 R2, R9 R0, #6400 SP, R7, LSL #2 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.5.6 MOV and MVN Move and Move NOT. Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation, see “Conditional Execution” . cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. imm16 is any value in the range 0–65535. Operation The MOV instruction copies the value of Operand2 into Rd. When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the corresponding shift instruction:  ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n  LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0  LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n  ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n  RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX. Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:  MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs  MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs  MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs  MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs See “ASR, LSL, LSR, ROR, and RRX” . The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd. The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 operand. Restrictions SP and PC only can be used in the MOV instruction, with the following restrictions:  The second operand must be a register without shift  The S suffix must not be specified. When Rd is PC in a MOV instruction:  Bit[0] of the value written to the PC is ignored  A branch occurs to the address created by forcing bit[0] of that value to 0. Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM instruction set. Condition Flags SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 123 If S is specified, these instructions:  Update the N and Z flags according to the result  Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”  Do not affect the V flag. Examples MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated MOVS R10, R12 ; Write value in R12 to R10, flags get updated MOV R3, #23 ; Write value of 23 to R3 MOV R8, SP ; Write value of stack pointer to R8 MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF) ; to the R2 and update flags. 12.6.5.7 MOVT Move Top. Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. imm16 is a 16-bit immediate constant. Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT instruction pair enables to generate any 32-bit constant. Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. Examples MOVT 12.6.5.8 R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword ; and APSR are unchanged. REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. Syntax op{cond} Rd, Rn where: op is any of: REV Reverse byte order in a word. REV16 Reverse byte order in each halfword independently. 124 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits. RBIT Reverse the bit order in a 32-bit word. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the operand. Operation Use these instructions to change endianness of data: REV converts either:  32-bit big-endian data into little-endian data  32-bit little-endian data into big-endian data. REV16 converts either:  16-bit big-endian data into little-endian data  16-bit little-endian data into big-endian data. REVSH converts either:  16-bit signed big-endian data into 32-bit signed little-endian data  16-bit signed little-endian data into 32-bit signed big-endian data. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples REV REV16 REVSH REVHS RBIT R3, R0, R0, R3, R7, R7; R0; R5; R7; R8; Reverse Reverse Reverse Reverse Reverse byte order of value in R7 and write it to R3 byte order of each 16-bit halfword in R0 Signed Halfword with Higher or Same condition bit order of value in R8 and write the result to R7. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 125 12.6.5.9 SADD16 and SADD8 Signed Add 16 and Signed Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SADD16 Performs two 16-bit signed integer additions. SADD8 Performs four 8-bit signed integer additions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation Use these instructions to perform a halfword or byte add in parallel: The SADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Writes the result in the corresponding halfwords of the destination register. The SADD8 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. Writes the result in the corresponding bytes of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SADD16 R1, R0 SADD8 126 ; ; ; R4, R0, R5 ; ; SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Adds the halfwords in R0 to the corresponding halfwords of R1 and writes to corresponding halfword of R1. Adds bytes of R0 to the corresponding byte in R5 and writes to the corresponding byte in R4. 12.6.5.10 SHADD16 and SHADD8 Signed Halving Add 16 and Signed Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHADD16 Signed Halving Add 16. SHADD8 Signed Halving Add 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register: The SHADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Shuffles the result by one bit to the right, halving the data. 3. Writes the halfword results in the destination register. The SHADDB8 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. 2. Shuffles the result by one bit to the right, halving the data. 3. Writes the byte results in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SHADD16 R1, R0 SHADD8 ; ; ; R4, R0, R5 ; ; Adds halfwords in R0 to corresponding halfword of R1 and writes halved result to corresponding halfword in R1 Adds bytes of R0 to corresponding byte in R5 and writes halved result to corresponding byte in R4. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 127 12.6.5.11 SHASX and SHSAX Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is any of: SHASX Add and Subtract with Exchange and Halving. SHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SHASX instruction: 1. Adds the top halfword of the first operand with the bottom halfword of the second operand. 2. Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. 3. Subtracts the top halfword of the second operand from the bottom highword of the first operand. 4. Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. The SHSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Writes the halfword result of the addition to the bottom halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. 3. Adds the bottom halfword of the first operand with the top halfword of the second operand. 4. Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to the right causing a divide by two, or halving. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. 128 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Examples SHASX R7, R4, R2 SHSAX R0, R3, R5 ; ; ; ; ; ; ; ; Adds top halfword of R4 to bottom halfword of R2 and writes halved result to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4 and writes halved result to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3 and writes halved result to top halfword of R0 Adds top halfword of R5 to bottom halfword of R3 and writes halved result to bottom halfword of R0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 129 12.6.5.12 SHSUB16 and SHSUB8 Signed Halving Subtract 16 and Signed Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SHSUB16 Signed Halving Subtract 16. SHSUB8 Signed Halving Subtract 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register: The SHSUB16 instruction: 1. Subtracts each halfword of the second operand from the corresponding halfwords of the first operand. 2. Shuffles the result by one bit to the right, halving the data. 3. Writes the halved halfword results in the destination register. The SHSUBB8 instruction: 1. Subtracts each byte of the second operand from the corresponding byte of the first operand, 2. Shuffles the result by one bit to the right, halving the data, 3. Writes the corresponding signed byte results in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SHSUB16 R1, R0 SHSUB8 130 ; ; R4, R0, R5 ; ; SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Subtracts halfwords in R0 from corresponding halfword of R1 and writes to corresponding halfword of R1 Subtracts bytes of R0 from corresponding byte in R5, and writes to corresponding byte in R4. 12.6.5.13 SSUB16 and SSUB8 Signed Subtract 16 and Signed Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: SSUB16 Performs two 16-bit signed integer subtractions. SSUB8 Performs four 8-bit signed integer subtractions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to change endianness of data: The SSUB16 instruction: 1. Subtracts each halfword from the second operand from the corresponding halfword of the first operand 2. Writes the difference result of two signed halfwords in the corresponding halfword of the destination register. The SSUB8 instruction: 1. Subtracts each byte of the second operand from the corresponding byte of the first operand 2. Writes the difference result of four signed bytes in the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SSUB16 R1, R0 SSUB8 ; ; R4, R0, R5 ; ; Subtracts halfwords in R0 from corresponding halfword of R1 and writes to corresponding halfword of R1 Subtracts bytes of R5 from corresponding byte in R0, and writes to corresponding byte of R4. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 131 12.6.5.14 SASX and SSAX Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rm, Rn where: op is any of: SASX Signed Add and Subtract with Exchange. SSAX Signed Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SASX instruction: 1. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand. 2. Writes the signed result of the addition to the top halfword of the destination register. 3. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand. 4. Writes the signed result of the subtraction to the bottom halfword of the destination register. The SSAX instruction: 1. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand. 2. Writes the signed result of the addition to the bottom halfword of the destination register. 3. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand. 4. Writes the signed result of the subtraction to the top halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples SASX SSAX 12.6.5.15 R0, R4, R5 ; ; ; ; R7, R3, R2 ; ; ; ; Adds top halfword of R4 to bottom halfword of R5 and writes to top halfword of R0 Subtracts bottom halfword of R5 from top halfword of R4 and writes to bottom halfword of R0 Subtracts top halfword of R2 from bottom halfword of R3 and writes to bottom halfword of R7 Adds top halfword of R3 with bottom halfword of R2 and writes to top halfword of R7. TST and TEQ Test bits and Test Equivalence. Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 132 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 where cond is an optional condition code, see “Conditional Execution” . Rn is the register holding the first operand. Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the options. Operation These instructions test the value in a register against Operand2. They update the condition flags based on the result, but do not write the result to a register. The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as the ANDS instruction, except that it discards the result. To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0. The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. This is the same as the EORS instruction, except that it discards the result. Use the TEQ instruction to test if two values are equal without affecting the V or C flags. TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign bits of the two operands. Restrictions Do not use SP and do not use PC. Condition Flags These instructions:  Update the N and Z flags according to the result  Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”  Do not affect the V flag. Examples TST TEQEQ 12.6.5.16 R0, #0x3F8 ; ; R10, R9 ; ; Perform bitwise AND of R0 value to 0x3F8, APSR is updated but result is discarded Conditionally test if value in R10 is equal to value in R9, APSR is updated but result is discarded. UADD16 and UADD8 Unsigned Add 16 and Unsigned Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UADD16 Performs two 16-bit unsigned integer additions. UADD8 Performs four 8-bit unsigned integer additions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 133 Use these instructions to add 16- and 8-bit unsigned data: The UADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Writes the unsigned result in the corresponding halfwords of the destination register. The UADD16 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. 2. Writes the unsigned result in the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples UADD16 R1, R0 UADD8 134 R4, R0, R5 ; ; ; ; SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Adds halfwords in R0 to corresponding halfword of R1, writes to corresponding halfword of R1 Adds bytes of R0 to corresponding byte in R5 and writes to corresponding byte in R4. 12.6.5.17 UASX and USAX Add and Subtract with Exchange and Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UASX Add and Subtract with Exchange. USAX Subtract and Add with Exchange. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UASX instruction: 1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand. 2. Writes the unsigned result from the subtraction to the bottom halfword of the destination register. 3. Adds the top halfword of the first operand with the bottom halfword of the second operand. 4. Writes the unsigned result of the addition to the top halfword of the destination register. The USAX instruction: 1. Adds the bottom halfword of the first operand with the top halfword of the second operand. 2. Writes the unsigned result of the addition to the bottom halfword of the destination register. 3. Subtracts the bottom halfword of the second operand from the top halfword of the first operand. 4. Writes the unsigned result from the subtraction to the top halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples UASX USAX 12.6.5.18 R0, R4, R5 ; ; ; ; R7, R3, R2 ; ; ; ; Adds top halfword of R4 to bottom halfword of R5 and writes to top halfword of R0 Subtracts bottom halfword of R5 from top halfword of R0 and writes to bottom halfword of R0 Subtracts top halfword of R2 from bottom halfword of R3 and writes to bottom halfword of R7 Adds top halfword of R3 to bottom halfword of R2 and writes to top halfword of R7. UHADD16 and UHADD8 Unsigned Halving Add 16 and Unsigned Halving Add 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHADD16 Unsigned Halving Add 16. UHADD8 Unsigned Halving Add 8. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 135 cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the register holding the first operand. Rm is the register holding the second operand. Operation Use these instructions to add 16- and 8-bit data and then to halve the result before writing the result to the destination register: The UHADD16 instruction: 1. Adds each halfword from the first operand to the corresponding halfword of the second operand. 2. Shuffles the halfword result by one bit to the right, halving the data. 3. Writes the unsigned results to the corresponding halfword in the destination register. The UHADD8 instruction: 1. Adds each byte of the first operand to the corresponding byte of the second operand. 2. Shuffles the byte result by one bit to the right, halving the data. 3. Writes the unsigned results in the corresponding byte in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples UHADD16 R7, R3 UHADD8 12.6.5.19 R4, R0, R5 ; ; ; ; ; Adds halfwords in R7 to corresponding halfword of R3 and writes halved result to corresponding halfword in R7 Adds bytes of R0 to corresponding byte in R5 and writes halved result to corresponding byte in R4. UHASX and UHSAX Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange. Syntax op{cond} {Rd}, Rn, Rm where: op is one of: UHASX Add and Subtract with Exchange and Halving. UHSAX Subtract and Add with Exchange and Halving. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UHASX instruction: 1. Adds the top halfword of the first operand with the bottom halfword of the second operand. 136 2. Shifts the result by one bit to the right causing a divide by two, or halving. 3. Writes the halfword result of the addition to the top halfword of the destination register. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 4. Subtracts the top halfword of the second operand from the bottom highword of the first operand. 5. Shifts the result by one bit to the right causing a divide by two, or halving. 6. Writes the halfword result of the division in the bottom halfword of the destination register. The UHSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Shifts the result by one bit to the right causing a divide by two, or halving. 3. Writes the halfword result of the subtraction in the top halfword of the destination register. 4. Adds the bottom halfword of the first operand with the top halfword of the second operand. 5. Shifts the result by one bit to the right causing a divide by two, or halving. 6. Writes the halfword result of the addition to the bottom halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples UHASX UHSAX R7, R4, R2 ; ; ; ; R0, R3, R5 ; ; ; ; Adds top halfword of R4 with bottom halfword of R2 and writes halved result to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R7 and writes halved result to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3 and writes halved result to top halfword of R0 Adds top halfword of R5 to bottom halfword of R3 and writes halved result to bottom halfword of R0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 137 12.6.5.20 UHSUB16 and UHSUB8 Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where: op is any of: UHSUB16 Performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination register: The UHSUB16 instruction: 1. Subtracts each halfword of the second operand from the corresponding halfword of the first operand. 2. Shuffles each halfword result to the right by one bit, halving the data. 3. Writes each unsigned halfword result to the corresponding halfwords in the destination register. The UHSUB8 instruction: 1. Subtracts each byte of second operand from the corresponding byte of the first operand. 2. Shuffles each byte result by one bit to the right, halving the data. 3. Writes the unsigned byte results to the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples UHSUB16 R1, R0 UHSUB8 12.6.5.21 R4, R0, R5 ; ; ; ; Subtracts halfwords in R0 from corresponding halfword of R1 and writes halved result to corresponding halfword in R1 Subtracts bytes of R5 from corresponding byte in R0 and writes halved result to corresponding byte in R4. SEL Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. Syntax SEL{}{} {,} , where: c, q 138 are standard assembler syntax fields. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Rd is the destination register. Rn is the first register holding the operand. Rm is the second register holding the operand. Operation The SEL instruction: 1. Reads the value of each bit of APSR.GE. 2. Depending on the value of APSR.GE, assigns the destination register the value of either the first or second operand register. Restrictions None. Condition Flags These instructions do not change the flags. Examples SADD16 R0, R1, R2 SEL R0, R0, R3 ; Set GE bits based on result ; Select bytes from R0 or R3, based on GE. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 139 12.6.5.22 USAD8 Unsigned Sum of Absolute Differences Syntax USAD8{cond}{Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation The USAD8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the absolute values of the differences together. 3. Writes the result to the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples USAD8 R1, R4, R0 ; ; USAD8 R0, R5 ; ; 140 Subtracts each byte in R0 from corresponding byte of R4 adds the differences and writes to R1 Subtracts bytes of R5 from corresponding byte in R0, adds the differences and writes to R0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.5.23 USADA8 Unsigned Sum of Absolute Differences and Accumulate Syntax USADA8{cond}{Rd,} Rn, Rm, Ra where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Ra is the register that contains the accumulation value. Operation The USADA8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Adds the unsigned absolute differences together. 3. Adds the accumulation value to the sum of the absolute differences. 4. Writes the result to the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples USADA8 R1, R0, R6 USADA8 R4, R0, R5, R2 ; ; ; ; Subtracts bytes in R0 from corresponding halfword of R1 adds differences, adds value of R6, writes to R1 Subtracts bytes of R5 from corresponding byte in R0 adds differences, adds value of R2 writes to R4. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 141 12.6.5.24 USUB16 and USUB8 Unsigned Subtract 16 and Unsigned Subtract 8 Syntax op{cond}{Rd,} Rn, Rm where op is any of: USUB16 Unsigned Subtract 16. USUB8 Unsigned Subtract 8. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the second operand register. Operation Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register: The USUB16 instruction: 1. Subtracts each halfword from the second operand register from the corresponding halfword of the first operand register. 2. Writes the unsigned result in the corresponding halfwords of the destination register. The USUB8 instruction: 1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register. 2. Writes the unsigned byte result in the corresponding byte of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples USUB16 R1, R0 142 ; ; ; ; Subtracts halfwords in R0 from corresponding halfword of R1 and writes to corresponding halfword in R1USUB8 R4, R0, R5 Subtracts bytes of R5 from corresponding byte in R0 and writes to the corresponding byte in R4. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.6 Multiply and Divide Instructions The table below shows the multiply and divide instructions. Table 12-21. Multiply and Divide Instructions Mnemonic Description MLA Multiply with Accumulate, 32-bit result MLS Multiply and Subtract, 32-bit result MUL Multiply, 32-bit result SDIV Signed Divide SMLA[B,T] Signed Multiply Accumulate (halfwords) SMLAD, SMLADX Signed Multiply Accumulate Dual SMLAL Signed Multiply with Accumulate (32 × 32 + 64), 64-bit result SMLAL[B,T] Signed Multiply Accumulate Long (halfwords) SMLALD, SMLALDX Signed Multiply Accumulate Long Dual SMLAW[B|T] Signed Multiply Accumulate (word by halfword) SMLSD Signed Multiply Subtract Dual SMLSLD Signed Multiply Subtract Long Dual SMMLA Signed Most Significant Word Multiply Accumulate SMMLS, SMMLSR Signed Most Significant Word Multiply Subtract SMUAD, SMUADX Signed Dual Multiply Add SMUL[B,T] Signed Multiply (word by halfword) SMMUL, SMMULR Signed Most Significant Word Multiply SMULL Signed Multiply (32x32), 64-bit result SMULWB, SMULWT Signed Multiply (word by halfword) SMUSD, SMUSDX Signed Dual Multiply Subtract UDIV Unsigned Divide UMAAL Unsigned Multiply Accumulate Accumulate Long (32 × 32 + 32 + 32), 64-bit result UMLAL Unsigned Multiply with Accumulate (32 × 32 + 64), 64-bit result UMULL Unsigned Multiply (32 × 32), 64-bit result SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 143 12.6.6.1 MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result. Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract where: cond is an optional condition code, see “Conditional Execution” . S is an optional suffix. If S is specified, the condition code flags are updated on the result operation, see “Conditional Execution” . Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be added or subtracted from. of the Operation The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd. The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32 bits of the result in Rd. The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and places the least significant 32 bits of the result in Rd. The results of these instructions do not depend on whether the operands are signed or unsigned. Restrictions In these instructions, do not use SP and do not use PC. If the S suffix is used with the MUL instruction:  Rd, Rn, and Rm must all be in the range R0 to R7  Rd must be the same as Rm  The cond suffix must not be used. Condition Flags If S is specified, the MUL instruction:  Updates the N and Z flags according to the result  Does not affect the C and V flags. Examples MUL MLA MULS MULLT MLS 12.6.6.2 R10, R2, R5 R10, R2, R1, R5 R0, R2, R2 R2, R3, R2 R4, R5, R6, R7 ; ; ; ; ; Multiply, R10 Multiply with Multiply with Conditionally Multiply with = R2 x R5 accumulate, R10 = flag update, R0 = multiply, R2 = R3 subtract, R4 = R7 (R2 x R1) + R5 R2 x R2 x R2 - (R5 x R6) UMULL, UMAAL, UMLAL Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op 144 is one of: SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 UMULL Unsigned Long Multiply. UMAAL Unsigned Long Multiply with Accumulate Accumulate. UMLAL Unsigned Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold the accumulating value. Rn, Rm are registers holding the first and second operands. Operation These instructions interpret the values from Rn and Rm as unsigned 32-bit integers. The UMULL instruction:  Multiplies the two unsigned integers in the first and second operands.  Writes the least significant 32 bits of the result in RdLo.  Writes the most significant 32 bits of the result in RdHi. The UMAAL instruction:  Multiplies the two unsigned 32-bit integers in the first and second operands.  Adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication.  Adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition.  Writes the top 32-bits of the result to RdHi.  Writes the lower 32-bits of the result to RdLo. The UMLAL instruction:  Multiplies the two unsigned integers in the first and second operands.  Adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.  Writes the result back to RdHi and RdLo. Restrictions In these instructions:  Do not use SP and do not use PC.  RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags. Examples UMULL R0, R4, R5, R6 UMAAL R3, R6, R2, R7 UMLAL R2, R1, R3, R5 12.6.6.3 ; ; ; ; ; Multiplies R5 and R6, writes the top 32 bits to R4 and the bottom 32 bits to R0 Multiplies R2 and R7, adds R6, adds R3, writes the top 32 bits to R6, and the bottom 32 bits to R3 Multiplies R5 and R3, adds R1:R2, writes to R1:R2. SMLA and SMLAW Signed Multiply Accumulate (halfwords). Syntax op{XY}{cond} Rd, Rn, Rm op{Y}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLA Signed Multiply Accumulate Long (halfwords). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 145 X and Y specifies which half of the source registers Rn and Rm are used as the first and second multiply operand. If X is B, then the bottom halfword, bits [15:0], of Rn is used. If X is T, then the top halfword, bits [31:16], of Rn is used. If Y is B, then the bottom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used SMLAW Signed Multiply Accumulate (word by halfword). Y specifies which half of the source register Rm is used as the second multiply operand. If Y is T, then the top halfword, bits [31:16] of Rm is used. If Y is B, then the bottom halfword, bits [15:0] of Rm is used. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn, Rm are registers holding the values to be multiplied. Ra is a register holding the value to be added or subtracted from. Operation The SMALBB, SMLABT, SMLATB, SMLATT instructions:  Multiplies the specified signed halfword, top or bottom, values from Rn and Rm.  Adds the value in Ra to the resulting 32-bit product.  Writes the result of the multiplication and addition in Rd. The non-specified halfwords of the source registers are ignored. The SMLAWB and SMLAWT instructions:  Multiply the 32-bit signed values in Rn with: ̶ ̶ The top signed halfword of Rm, T instruction suffix. The bottom signed halfword of Rm, B instruction suffix.  Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product  Writes the result of the multiplication and addition in Rd. The bottom 16 bits of the 48-bit product are ignored. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No overflow can occur during the multiplication. Restrictions In these instructions, do not use SP and do not use PC. Condition Flags If an overflow is detected, the Q flag is set. Examples SMLABB R5, R6, R4, R1 SMLATB R5, R6, R4, R1 SMLATT R5, R6, R4, R1 SMLABT R5, R6, R4, R1 SMLABT R4, R3, R2 146 ; ; ; ; ; ; ; ; ; ; Multiplies bottom halfwords of R6 and R4, adds R1 and writes to R5 Multiplies top halfword of R6 with bottom halfword of R4, adds R1 and writes to R5 Multiplies top halfwords of R6 and R4, adds R1 and writes the sum to R5 Multiplies bottom halfword of R6 with top halfword of R4, adds R1 and writes to R5 Multiplies bottom halfword of R4 with top halfword of R3, adds R2 and writes to R4 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 SMLAWB SMLAWT R10, R2, R5, R3 ; ; R10, R2, R1, R5 ; ; Multiplies R2 with bottom halfword of R5, adds R3 to the result and writes top 32-bits to R10 Multiplies R2 with top halfword of R1, adds R5 and writes top 32-bits to R10. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 147 12.6.6.4 SMLAD Signed Multiply Accumulate Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra ; where: op is one of: SMLAD Signed Multiply Accumulate Dual. SMLADX Signed Multiply Accumulate Dual Reverse. X specifies which halfword of the source register Rn is used as the multiply operand. If X is omitted, the multiplications are bottom × bottom and top × top. If X is present, the multiplications are bottom × top and top × bottom. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register holding the values to be multiplied. Rm the second operand register. Ra is the accumulate value. Operation The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values. The SMLAD and SMLADX instructions:  If X is not present, multiply the top signed halfword value in Rn with the top signed halfword of Rm and the bottom signed halfword values in Rn with the bottom signed halfword of Rm.  Or if X is present, multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and the bottom signed halfword values in Rn with the top signed halfword of Rm.  Add both multiplication results to the signed 32-bit value in Ra.  Writes the 32-bit signed result of the multiplication and addition to Rd. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SMLAD R10, R2, R1, R5 ; ; ; SMLALDX R0, R2, R4, R6 ; ; ; ; 12.6.6.5 Multiplies two halfword values in R2 with corresponding halfwords in R1, adds R5 and writes to R10 Multiplies top halfword of R2 with bottom halfword of R4, multiplies bottom halfword of R2 with top halfword of R4, adds R6 and writes to R0. SMLAL and SMLALD Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long Dual. Syntax op{cond} RdLo, RdHi, Rn, Rm 148 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 op{XY}{cond} RdLo, RdHi, Rn, Rm op{X}{cond} RdLo, RdHi, Rn, Rm where: op is one of: MLAL Signed Multiply Accumulate Long. SMLAL Signed Multiply Accumulate Long (halfwords, X and Y). X and Y specify which halfword of the source registers Rn and Rm are used as the first and second multiply operand: If X is B, then the bottom halfword, bits [15:0], of Rn is used. If X is T, then the top halfword, bits [31:16], of Rn is used. If Y is B, then the bottom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used. SMLALD Signed Multiply Accumulate Long Dual. SMLALDX Signed Multiply Accumulate Long Dual Reversed. If the X is omitted, the multiplications are bottom × bottom and top × top. If X is present, the multiplications are bottom × top and top × bottom. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers. RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer. For SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD and SMLA LDX, they also hold the accumulating value. Rn, Rm are registers holding the first and second operands. Operation The SMLAL instruction:  Multiplies the two’s complement signed word values from Rn and Rm.  Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product.  Writes the 64-bit result of the multiplication and addition in RdLo and RdHi. The SMLALBB, SMLALBT, SMLALTB and SMLALTT instructions:  Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.  Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi.  Writes the 64-bit result of the multiplication and addition in RdLo and RdHi. The non-specified halfwords of the source registers are ignored. The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement signed 16-bit integers. These instructions:  If X is not present, multiply the top signed halfword value of Rn with the top signed halfword of Rm and the bottom signed halfword values of Rn with the bottom signed halfword of Rm.  Or if X is present, multiply the top signed halfword value of Rn with the bottom signed halfword of Rm and the bottom signed halfword values of Rn with the top signed halfword of Rm.  Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit product.  Write the 64-bit product in RdLo and RdHi. Restrictions In these instructions: SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 149  Do not use SP and do not use PC.  RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags. Examples SMLAL R4, R5, R3, R8 SMLALBT R2, R1, R6, R7 SMLALTB R2, R1, R6, R7 SMLALD R6, R8, R5, R1 SMLALDX R6, R8, R5, R1 150 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Multiplies R3 and R8, adds R5:R4 and writes to R5:R4 Multiplies bottom halfword of R6 with top halfword of R7, sign extends to 32-bit, adds R1:R2 and writes to R1:R2 Multiplies top halfword of R6 with bottom halfword of R7,sign extends to 32-bit, adds R1:R2 and writes to R1:R2 Multiplies top halfwords in R5 and R1 and bottom halfwords of R5 and R1, adds R8:R6 and writes to R8:R6 Multiplies top halfword in R5 with bottom halfword of R1, and bottom halfword of R5 with top halfword of R1, adds R8:R6 and writes to R8:R6. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.6.6 SMLSD and SMLSLD Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual Syntax op{X}{cond} Rd, Rn, Rm, Ra where: op is one of: SMLSD Signed Multiply Subtract Dual. SMLSDX Signed Multiply Subtract Dual Reversed. SMLSLD Signed Multiply Subtract Long Dual. SMLSLDX Signed Multiply Subtract Long Dual Reversed. SMLAW Signed Multiply Accumulate (word by halfword). If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Ra is the register holding the accumulate value. Operation The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This instruction:  Optionally rotates the halfwords of the second operand.  Performs two signed 16 × 16-bit halfword multiplications.  Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.  Adds the signed accumulate value to the result of the subtraction.  Writes the result of the addition to the destination register. The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords. This instruction:  Optionally rotates the halfwords of the second operand.  Performs two signed 16 × 16-bit halfword multiplications.  Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.  Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.  Writes the 64-bit result of the addition to the RdHi and RdLo. Restrictions In these instructions:  Do not use SP and do not use PC. Condition Flags This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. For the Thumb instruction set, these instructions do not affect the condition code flags. Examples SMLSD R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom ; halfword of R5, multiplies top halfword of R4 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 151 ; ; SMLSDX R1, R3, R2, R0 ; ; ; ; SMLSLD R3, R6, R2, R7 ; ; ; ; SMLSLDX R3, R6, R2, R7 ; ; ; ; 152 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 with top halfword of R5, subtracts second from first, adds R6, writes to R0 Multiplies bottom halfword of R3 with top halfword of R2, multiplies top halfword of R3 with bottom halfword of R2, subtracts second from first, adds R0, writes to R1 Multiplies bottom halfword of R6 with bottom halfword of R2, multiplies top halfword of R6 with top halfword of R2, subtracts second from first, adds R6:R3, writes to R6:R3 Multiplies bottom halfword of R6 with top halfword of R2, multiplies top halfword of R6 with bottom halfword of R2, subtracts second from first, adds R6:R3, writes to R6:R3. 12.6.6.7 SMMLA and SMMLS Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract Syntax op{R}{cond} Rd, Rn, Rm, Ra where: op is one of: SMMLA Signed Most Significant Word Multiply Accumulate. SMMLS Signed Most Significant Word Multiply Subtract. If the X is omitted, the multiplications are bottom × bottom and top × top. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the high word is extracted. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second multiply operands. Ra is the register holding the accumulate value. Operation The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words. The SMMLA instruction:  Multiplies the values in Rn and Rm.  Optionally rounds the result by adding 0x80000000.  Extracts the most significant 32 bits of the result.  Adds the value of Ra to the signed extracted value.  Writes the result of the addition in Rd. The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words. The SMMLS instruction:  Multiplies the values in Rn and Rm.  Optionally rounds the result by adding 0x80000000.  Extracts the most significant 32 bits of the result.  Subtracts the extracted value of the result from the value in Ra.  Writes the result of the subtraction in Rd. Restrictions In these instructions:  Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples SMMLA R0, R4, R5, R6 SMMLAR R6, R2, R1, R4 SMMLSR R3, R6, R2, R7 ; ; ; ; ; ; Multiplies R4 and R5, extracts top R6, truncates and writes to R0 Multiplies R2 and R1, extracts top R4, rounds and writes to R6 Multiplies R6 and R2, extracts top subtracts R7, rounds and writes to 32 bits, adds 32 bits, adds 32 bits, R3 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 153 SMMLS 12.6.6.8 R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits, ; subtracts R8, truncates and writes to R4. SMMUL Signed Most Significant Word Multiply Syntax op{R}{cond} Rd, Rn, Rm where: op is one of: SMMUL Signed Most Significant Word Multiply. R is a rounding error flag. If R is specified, the result is rounded instead of being truncated. In this case the constant 0x80000000 is added to the product before the high word is extracted. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The SMMUL instruction:  Multiplies the values from Rn and Rm.  Optionally rounds the result, otherwise truncates the result.  Writes the most significant signed 32 bits of the result in Rd. Restrictions In this instruction:  do not use SP and do not use PC. Condition Flags This instruction does not affect the condition code flags. Examples SMULL SMULLR 12.6.6.9 R0, R4, R5 R6, R2 ; ; ; ; Multiplies and writes Multiplies and writes R4 to R6 to and R5, truncates top 32 bits R0 and R2, rounds the top 32 bits R6. SMUAD and SMUSD Signed Dual Multiply Add and Signed Dual Multiply Subtract Syntax op{X}{cond} Rd, Rn, Rm where: op is one of: SMUAD Signed Dual Multiply Add. SMUADX Signed Dual Multiply Add Reversed. SMUSD Signed Dual Multiply Subtract. 154 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 SMUSDX Signed Dual Multiply Subtract Reversed. If X is present, the multiplications are bottom × top and top × bottom. If the X is omitted, the multiplications are bottom × bottom and top × top. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each operand. This instruction:  Optionally rotates the halfwords of the second operand.  Performs two signed 16 × 16-bit multiplications.  Adds the two multiplication results together.  Writes the result of the addition to the destination register. The SMUSD instruction interprets the values from the first and second operands as two’s complement signed integers. This instruction:  Optionally rotates the halfwords of the second operand.  Performs two signed 16 × 16-bit multiplications.  Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.  Writes the result of the subtraction to the destination register. Restrictions In these instructions:  Do not use SP and do not use PC. Condition Flags Sets the Q flag if the addition overflows. The multiplications cannot overflow. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 155 Examples SMUAD R0, R4, R5 SMUADX R3, R7, R4 SMUSD R3, R6, R2 SMUSDX R4, R5, R3 12.6.6.10 ; ; ; ; ; ; ; ; ; ; ; ; Multiplies bottom halfword of R4 with the bottom halfword of R5, adds multiplication of top halfword of R4 with top halfword of R5, writes to R0 Multiplies bottom halfword of R7 with top halfword of R4, adds multiplication of top halfword of R7 with bottom halfword of R4, writes to R3 Multiplies bottom halfword of R4 with bottom halfword of R6, subtracts multiplication of top halfword of R6 with top halfword of R3, writes to R3 Multiplies bottom halfword of R5 with top halfword of R3, subtracts multiplication of top halfword of R5 with bottom halfword of R3, writes to R4. SMUL and SMULW Signed Multiply (halfwords) and Signed Multiply (word by halfword) Syntax op{XY}{cond} Rd,Rn, Rm op{Y}{cond} Rd. Rn, Rm For SMULXY only: op is one of: SMUL{XY} Signed Multiply (halfwords). X and Y specify which halfword of the source registers Rn and Rm is used as the first and second multiply operand. If X is B, then the bottom halfword, bits [15:0] of Rn is used. If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot tom halfword, bits [15:0], of Rm is used. If Y is T, then the top halfword, bits [31:16], of Rm is used. SMULW{Y} Signed Multiply (word by halfword). Y specifies which halfword of the source register Rm is used as the second mul tiply operand. If Y is B, then the bottom halfword (bits [15:0]) of Rm is used. If Y is T, then the top halfword (bits [31:16]) of Rm is used. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The SMULBB, SMULTB, SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed 16-bit integers. These instructions:  Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.  Writes the 32-bit result of the multiplication in Rd. The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two halfword 16-bit signed integers. These instructions:  Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.  Writes the signed most significant 32 bits of the 48-bit result in the destination register. Restrictions 156 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 In these instructions:  Do not use SP and do not use PC.  RdHi and RdLo must be different registers. Examples SMULBT R0, R4, R5 SMULBB R0, R4, R5 SMULTT R0, R4, R5 SMULTB R0, R4, R5 SMULWT R4, R5, R3 SMULWB R4, R5, R3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Multiplies the bottom halfword of R4 with the top halfword of R5, multiplies results and writes to R0 Multiplies the bottom halfword of R4 with the bottom halfword of R5, multiplies results and writes to R0 Multiplies the top halfword of R4 with the top halfword of R5, multiplies results and writes to R0 Multiplies the top halfword of R4 with the bottom halfword of R5, multiplies results and and writes to R0 Multiplies R5 with the top halfword of R3, extracts top 32 bits and writes to R4 Multiplies R5 with the bottom halfword of R3, extracts top 32 bits and writes to R4. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 157 12.6.6.11 UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result. Syntax op{cond} RdLo, RdHi, Rn, Rm where: op is one of: UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, with Accumulate. SMULL Signed Long Multiply. SMLAL Signed Long Multiply, with Accumulate. cond is an optional condition code, see “Conditional Execution” . RdHi, RdLo are the destination registers. For UMLAL and SMLAL they also hold the accu mulating value. Rn, Rm are registers holding the operands. Operation The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi. The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo. Restrictions In these instructions:  Do not use SP and do not use PC  RdHi and RdLo must be different registers. Condition Flags These instructions do not affect the condition code flags. Examples UMULL SMLAL 158 R0, R4, R5, R6 R4, R5, R3, R8 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 ; Unsigned (R4,R0) = R5 x R6 ; Signed (R5,R4) = (R5,R4) + R3 x R8 12.6.6.12 SDIV and UDIV Signed Divide and Unsigned Divide. Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. If Rd is omitted, the destination register is Rn. Rn is the register holding the value to be divided. Rm is a register holding the divisor. Operation SDIV performs a signed integer division of the value in Rn by the value in Rm. UDIV performs an unsigned integer division of the value in Rn by the value in Rm. For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not change the flags. Examples SDIV UDIV R0, R2, R4 R8, R8, R1 ; Signed divide, R0 = R2/R4 ; Unsigned divide, R8 = R8/R1 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 159 12.6.7 Saturating Instructions The table below shows the saturating instructions. Table 12-22. Saturating Instructions Mnemonic Description SSAT Signed Saturate SSAT16 Signed Saturate Halfword USAT Unsigned Saturate USAT16 Unsigned Saturate Halfword QADD Saturating Add QSUB Saturating Subtract QSUB16 Saturating Subtract 16 QASX Saturating Add and Subtract with Exchange QSAX Saturating Subtract and Add with Exchange QDADD Saturating Double and Add QDSUB Saturating Double and Subtract UQADD16 Unsigned Saturating Add 16 UQADD8 Unsigned Saturating Add 8 UQASX Unsigned Saturating Add and Subtract with Exchange UQSAX Unsigned Saturating Subtract and Add with Exchange UQSUB16 Unsigned Saturating Subtract 16 UQSUB8 Unsigned Saturating Subtract 8 For signed n-bit saturation, this means that:  If the value to be saturated is less than -2n-1, the result returned is -2n-1  If the value to be saturated is greater than 2n-1-1, the result returned is 2n-1-1  Otherwise, the result returned is the same as the value to be saturated. For unsigned n-bit saturation, this means that:  If the value to be saturated is less than 0, the result returned is 0  If the value to be saturated is greater than 2n-1, the result returned is 2n-1  Otherwise, the result returned is the same as the value to be saturated. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, the MSR instruction must be used; see “MSR” . To read the state of the Q flag, the MRS instruction must be used; see “MRS” . 160 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.7.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. Syntax op{cond} Rd, #n, Rm {, shift #s} where: op is one of: SSAT Saturates a signed value to a signed range. USAT Saturates a signed value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 31 for USAT. to 32 for SSAT Rm is the register containing the value to saturate. shift #s is an optional shift applied to Rm before saturating. It must be one of the following: ASR #s where s is in the range 1 to 31. LSL #s where s is in the range 0 to 31. Operation These instructions saturate to a signed or unsigned n-bit value. The SSAT instruction applies the specified shift, then saturates to the signed range -2n–1 ≤ x ≤ 2n–1-1. The USAT instruction applies the specified shift, then saturates to the unsigned range 0 ≤ x ≤ 2n-1. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. Examples SSAT R7, #16, R7, LSL #4 USATNE R0, #7, R5 ; ; ; ; ; Logical shift left value in R7 by 4, then saturate it as a signed 16-bit value and write it back to R7 Conditionally saturate value in R5 as an unsigned 7 bit value and write it to R0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 161 12.6.7.2 SSAT16 and USAT16 Signed Saturate and Unsigned Saturate to any bit position for two halfwords. Syntax op{cond} Rd, #n, Rm where: op is one of: SSAT16 Saturates a signed halfword value to a signed range. USAT16 Saturates a signed halfword value to an unsigned range. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. n specifies the bit position to saturate to: n ranges from 1 n ranges from 0 to 15 for USAT. to 16 for SSAT Rm is the register containing the value to saturate. Operation The SSAT16 instruction: Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit position in n. Writes the results as two signed 16-bit halfwords to the destination register. The USAT16 instruction: Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit position in n. Writes the results as two unsigned halfwords in the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. Examples SSAT16 USAT16NE 12.6.7.3 R7, #9, R2 R0, #13, R5 ; ; ; ; ; ; Saturates the top and bottom highwords of R2 as 9-bit values, writes to corresponding halfword of R7 Conditionally saturates the top and bottom halfwords of R5 as 13-bit values, writes to corresponding halfword of R0. QADD and QSUB Saturating Add and Saturating Subtract, signed. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: 162 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 op is one of: QADD Saturating 32-bit add. QADD8 Saturating four 8-bit integer additions. QADD16 Saturating two 16-bit integer additions. QSUB Saturating 32-bit subtraction. QSUB8 Saturating four 8-bit integer subtraction. QSUB16 Saturating two 16-bit integer subtraction. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation These instructions add or subtract two, four or eight values from the first and second operands and then writes a signed saturated value in the destination register. The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed range -2n–1 ≤ x ≤ 2n–1-1, where x is given by the number of bits applied in the instruction, 32, 16 or 8. If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit and 16-bit QADD and QSUB instructions always leave the Q flag unchanged. To clear the Q flag to 0, the MSR instruction must be used; see “MSR” . To read the state of the Q flag, the MRS instruction must be used; see “MRS” . Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 163 Examples QADD16 12.6.7.4 R7, R4, R2 QADD8 R3, R1, R6 QSUB16 R4, R2, R3 QSUB8 R4, R2, R5 ; ; ; ; ; ; ; ; ; ; ; ; Adds halfwords of R4 with corresponding halfword of R2, saturates to 16 bits and writes to corresponding halfword of R7 Adds bytes of R1 to the corresponding bytes of R6, saturates to 8 bits and writes to corresponding byte of R3 Subtracts halfwords of R3 from corresponding halfword of R2, saturates to 16 bits, writes to corresponding halfword of R4 Subtracts bytes of R5 from the corresponding byte in R2, saturates to 8 bits, writes to corresponding byte of R4. QASX and QSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QASX Add and Subtract with Exchange and Saturate. QSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The QASX instruction: 1. Adds the top halfword of the source operand with the bottom halfword of the second operand. 2. Subtracts the top halfword of the second operand from the bottom highword of the first operand. 3. Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register. 4. Saturates the results of the sum and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register. The QSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Adds the bottom halfword of the source operand with the top halfword of the second operand. 3. Saturates the results of the sum and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the bottom halfword of the destination register. 4. Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. 164 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Examples QASX QSAX R7, R4, R2 ; ; ; ; ; R0, R3, R5 ; ; ; ; Adds top halfword of R4 to bottom halfword of R2, saturates to 16 bits, writes to top halfword of R7 Subtracts top highword of R2 from bottom halfword of R4, saturates to 16 bits and writes to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3, saturates to 16 bits, writes to top halfword of R0 Adds bottom halfword of R3 to top halfword of R5, saturates to 16 bits, writes to bottom halfword of R0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 165 12.6.7.5 QDADD and QDSUB Saturating Double and Add and Saturating Double and Subtract, signed. Syntax op{cond} {Rd}, Rm, Rn where: op is one of: QDADD Saturating Double and Add. QDSUB Saturating Double and Subtract. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm, Rn are registers holding the first and second operands. Operation The QDADD instruction:  Doubles the second operand value.  Adds the result of the doubling to the signed saturated value in the first operand.  Writes the result to the destination register. The QDSUB instruction:  Doubles the second operand value.  Subtracts the doubled value from the signed saturated value in the first operand.  Writes the result to the destination register. Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range – 231 ≤ x ≤ 231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR. Restrictions Do not use SP and do not use PC. Condition Flags If saturation occurs, these instructions set the Q flag to 1. 166 Examples QDADD R7, R4, R2 QDSUB R0, R3, R5 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 ; ; ; ; Doubles and saturates R4 to 32 bits, adds R2, saturates to 32 bits, writes to R7 Subtracts R3 doubled and saturated to 32 bits from R5, saturates to 32 bits, writes to R0. 12.6.7.6 UQASX and UQSAX Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned. Syntax op{cond} {Rd}, Rm, Rn where: type is one of: UQASX Add and Subtract with Exchange and Saturate. UQSAX Subtract and Add with Exchange and Saturate. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation The UQASX instruction: 1. Adds the bottom halfword of the source operand with the top halfword of the second operand. 2. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 3. Saturates the results of the sum and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register. 4. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register. The UQSAX instruction: 1. Subtracts the bottom halfword of the second operand from the top highword of the first operand. 2. Adds the bottom halfword of the first operand with the top halfword of the second operand. 3. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register. 4. Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x equals 16, to the bottom halfword of the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 167 Examples UQASX R7, R4, R2 UQSAX R0, R3, R5 12.6.7.7 ; ; ; ; ; ; ; ; Adds top halfword of R4 with bottom halfword of R2, saturates to 16 bits, writes to top halfword of R7 Subtracts top halfword of R2 from bottom halfword of R4, saturates to 16 bits, writes to bottom halfword of R7 Subtracts bottom halfword of R5 from top halfword of R3, saturates to 16 bits, writes to top halfword of R0 Adds bottom halfword of R4 to top halfword of R5 saturates to 16 bits, writes to bottom halfword of R0. UQADD and UQSUB Saturating Add and Saturating Subtract Unsigned. Syntax op{cond} {Rd}, Rn, Rm op{cond} {Rd}, Rn, Rm where: op is one of: UQADD8 Saturating four unsigned 8-bit integer additions. UQADD16 Saturating two unsigned 16-bit integer additions. UDSUB8 Saturating four unsigned 8-bit integer subtractions. UQSUB16 Saturating two unsigned 16-bit integer subtractions. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn, Rm are registers holding the first and second operands. Operation These instructions add or subtract two or four values and then writes an unsigned saturated value in the destination register. The UQADD16 instruction:  Adds the respective top and bottom halfwords of the first and second operands.  Saturates the result of the additions for each halfword in the destination register to the unsigned range 0 ≤ x ≤ 216-1, where x is 16. The UQADD8 instruction:  Adds each respective byte of the first and second operands.  Saturates the result of the addition for each byte in the destination register to the unsigned range 0 ≤ x ≤ 281, where x is 8. The UQSUB16 instruction:  Subtracts both halfwords of the second operand from the respective halfwords of the first operand.  Saturates the result of the differences in the destination register to the unsigned range 0 ≤ x ≤ 216-1, where x is 16. The UQSUB8 instructions: 168  Subtracts the respective bytes of the second operand from the respective bytes of the first operand.  Saturates the results of the differences for each byte in the destination register to the unsigned range 0 ≤ x ≤ 28-1, where x is 8. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the condition code flags. Examples UQADD16 R7, R4, R2 UQADD8 R4, R2, R5 UQSUB16 R6, R3, R0 UQSUB8 R1, R5, R6 ; ; ; ; ; ; ; ; ; Adds halfwords in R4 to corresponding halfword in R2, saturates to 16 bits, writes to corresponding halfword of R7 Adds bytes of R2 to corresponding byte of R5, saturates to 8 bits, writes to corresponding bytes of R4 Subtracts halfwords in R0 from corresponding halfword in R3, saturates to 16 bits, writes to corresponding halfword in R6 Subtracts bytes in R6 from corresponding byte of R5, saturates to 8 bits, writes to corresponding byte of R1. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 169 12.6.8 Packing and Unpacking Instructions The table below shows the instructions that operate on packing and unpacking data. Table 12-23. 170 Packing and Unpacking Instructions Mnemonic Description PKH Pack Halfword SXTAB Extend 8 bits to 32 and add SXTAB16 Dual extend 8 bits to 16 and add SXTAH Extend 16 bits to 32 and add SXTB Sign extend a byte SXTB16 Dual extend 8 bits to 16 and add SXTH Sign extend a halfword UXTAB Extend 8 bits to 32 and add UXTAB16 Dual extend 8 bits to 16 and add UXTAH Extend 16 bits to 32 and add UXTB Zero extend a byte UXTB16 Dual zero extend 8 bits to 16 and add UXTH Zero extend a halfword SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.8.1 PKHBT and PKHTB Pack Halfword Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm} op{cond} {Rd}, Rn, Rm {, ASR #imm} where: op is one of: PKHBT Pack Halfword, bottom and top with shift. PKHTB Pack Halfword, top and bottom with shift. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register Rm is the second operand register holding the value to be optionally shifted. imm is the shift length. The type of shift length depends on the instruction: For PKHBT LSL a left shift with a shift length from 1 to 31, 0 means no shift. For PKHTB ASR an arithmetic shift right with a shift length from 1 to 32, a shift of 32-bits is encoded as 0b00000. Operation The PKHBT instruction: 1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register. 2. If shifted, the shifted value of the second operand is written to the top halfword of the destination register. The PKHTB instruction: 1. Writes the value of the top halfword of the first operand to the top halfword of the destination register. 2. If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register. Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 171 Examples PKHBT R3, R4, R5 LSL #0 PKHTB R4, R0, R2 ASR #1 12.6.8.2 ; ; ; ; ; ; Writes bottom halfword of R4 to bottom halfword of R3, writes top halfword of R5, unshifted, to top halfword of R3 Writes R2 shifted right by 1 bit to bottom halfword of R4, and writes top halfword of R0 to top halfword of R4. SXT and UXT Sign extend and Zero extend. Syntax op{cond} {Rd,} Rm {, ROR #n} op{cond} {Rd}, Rm {, ROR #n} where: op is one of: SXTB Sign extends an 8-bit value to a 32-bit value. SXTH Sign extends a 16-bit value to a 32-bit value. SXTB16 Sign extends two 8-bit values to two 16-bit values. UXTB Zero extends an 8-bit value to a 32-bit value. UXTH Zero extends a 16-bit value to a 32-bit value. UXTB16 Zero extends two 8-bit values to two 16-bit values. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. Operation These instructions do the following: 1. Rotate the value from Rm right by 0, 8, 16 or 24 bits. 2. Extract bits from the resulting value: ̶ SXTB extracts bits[7:0] and sign extends to 32 bits. ̶ UXTB extracts bits[7:0] and zero extends to 32 bits. ̶ SXTH extracts bits[15:0] and sign extends to 32 bits. ̶ UXTH extracts bits[15:0] and zero extends to 32 bits. ̶ SXTB16 extracts bits[7:0] and sign extends to 16 bits, and extracts bits [23:16] and sign extends to 16 bits. ̶ UXTB16 extracts bits[7:0] and zero extends to 16 bits, and extracts bits [23:16] and zero extends to 16 bits. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. 172 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Examples SXTH R4, R6, ROR #16 UXTB R3, R10 12.6.8.3 ; ; ; ; Rotates R6 right by 16 bits, obtains bottom halfword of of result, sign extends to 32 bits and writes to R4 Extracts lowest byte of value in R10, zero extends, and writes to R3. SXTA and UXTA Signed and Unsigned Extend and Add Syntax op{cond} {Rd,} Rn, Rm {, ROR #n} op{cond} {Rd,} Rn, Rm {, ROR #n} where: op is one of: SXTAB Sign extends an 8-bit value to a 32-bit value and add. SXTAH Sign extends a 16-bit value to a 32-bit value and add. SXTAB16 Sign extends two 8-bit values to two 16-bit values and add. UXTAB Zero extends an 8-bit value to a 32-bit value and add. UXTAH Zero extends a 16-bit value to a 32-bit value and add. UXTAB16 Zero extends two 8-bit values to two 16-bit values and add. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the first operand register. Rm is the register holding the value to rotate and extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits. ROR #24 Value from Rm is rotated right 24 bits. If ROR #n is omitted, no rotation is performed. Operation These instructions do the following: 1. Rotate the value from Rm right by 0, 8, 16 or 24 bits. 2. Extract bits from the resulting value: ̶ ̶ ̶ ̶ 3. ̶ SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits. ̶ UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits. SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits. UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits. SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits, and extracts bits [23:16] from Rm and sign extends to 16 bits. UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits, and extracts bits [23:16] from Rm and zero extends to 16 bits. Adds the signed or zero extended value to the word or corresponding halfword of Rn and writes the result in Rd. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 173 Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples SXTAH UXTAB 174 R4, R8, R6, ROR #16 ; ; ; R3, R4, R10 ; ; SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Rotates R6 right by 16 bits, obtains bottom halfword, sign extends to 32 bits, adds R8,and writes to R4 Extracts bottom byte of R10 and zero extends to 32 bits, adds R4, and writes to R3. 12.6.9 Bitfield Instructions The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields. Table 12-24. Packing and Unpacking Instructions Mnemonic Description BFC Bit Field Clear BFI Bit Field Insert SBFX Signed Bit Field Extract SXTB Sign extend a byte SXTH Sign extend a halfword UBFX Unsigned Bit Field Extract UXTB Zero extend a byte UXTH Zero extend a halfword SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 175 12.6.9.1 BFC and BFI Bit Field Clear and Bit Field Insert. Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb. Operation BFC clears a bitfield in a register. It clears width bits in Rd, starting at the low bit position lsb. Other bits in Rd are unchanged. BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit position lsb, with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples BFC BFI 176 R4, #8, #12 R9, R2, #8, #12 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0 ; Replace bit 8 to bit 19 (12 bits) of R9 with ; bit 0 to bit 11 from R2. 12.6.9.2 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb. Operation SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register. UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination register. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples SBFX UBFX R0, R1, #20, #4 ; ; R8, R11, #9, #10 ; ; Extract bit 20 to bit 23 (4 bits) from R1 and sign extend to 32 bits and then write the result to R0. Extract bit 9 to bit 18 (10 bits) from R11 and zero extend to 32 bits and then write the result to R8. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 177 12.6.9.3 SXT and UXT Sign extend and Zero extend. Syntax SXTextend{cond} {Rd,} Rm {, ROR #n} UXTextend{cond} {Rd}, Rm {, ROR #n} where: extend is one of: B Extends an 8-bit value to a 32-bit value. H Extends a 16-bit value to a 32-bit value. cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. Rm is the register holding the value to extend. ROR #n is one of: ROR #8 Value from Rm is rotated right 8 bits. ROR #16 Value from Rm is rotated right 16 bits. ROR #24 Value from Rm is rotated right 24 bits. If ROR #n is omitted, no rotation is performed. Operation These instructions do the following: 1. Rotate the value from Rm right by 0, 8, 16 or 24 bits. 2. Extract bits from the resulting value: ̶ SXTB extracts bits[7:0] and sign extends to 32 bits. ̶ UXTB extracts bits[7:0] and zero extends to 32 bits. ̶ SXTH extracts bits[15:0] and sign extends to 32 bits. ̶ UXTH extracts bits[15:0] and zero extends to 32 bits. Restrictions Do not use SP and do not use PC. Condition Flags These instructions do not affect the flags. Examples 178 SXTH R4, R6, ROR #16 UXTB R3, R10 ; ; ; ; ; Rotate R6 right by 16 bits, then obtain the lower halfword of the result and then sign extend to 32 bits and write the result to R4. Extract lowest byte of the value in R10 and zero extend it, and write the result to R3. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.10 Branch and Control Instructions The table below shows the branch and control instructions. Table 12-25. Branch and Control Instructions Mnemonic Description B Branch BL Branch with Link BLX Branch indirect with Link BX Branch indirect CBNZ Compare and Branch if Non Zero CBZ Compare and Branch if Zero IT If-Then TBB Table Branch Byte TBH Table Branch Halfword SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 179 12.6.10.1 B, BL, BX, and BLX Branch instructions. Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where: B is branch (immediate). BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see “Conditional Execution” . label is a PC-relative expression. See “PC-relative Expressions” . Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm must be 1, but the address to branch to is created by changing bit[0] to 0. Operation All these instructions cause a branch to label, or to the address indicated in Rm. In addition:  The BL and BLX instructions write the address of the next instruction to LR (the link register, R14).  The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0. Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch instructions must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT” . The table below shows the ranges for the various branch instructions. Table 12-26. Branch Ranges Instruction Branch Range B label −16 MB to +16 MB Bcond label (outside IT block) −1 MB to +1 MB Bcond label (inside IT block) −16 MB to +16 MB BL{cond} label −16 MB to +16 MB BX{cond} Rm Any value in register BLX{cond} Rm Any value in register The .W suffix might be used to get the maximum branch range. See “Instruction Width Selection” . Restrictions The restrictions are:  Do not use PC in the BLX instruction  For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit[0] to 0  When any of these instructions is inside an IT block, it must be the last instruction of the IT block. Bcond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch range when it is inside an IT block. 180 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Condition Flags These instructions do not change the flags. Examples B BLE B.W BEQ BEQ.W BL loopA ng target target target funC BX BXNE BLX LR R0 R0 ; ; ; ; ; ; ; ; ; ; Branch to loopA Conditionally branch to label ng Branch to target within 16MB range Conditionally branch to target Conditionally branch to target within 1MB Branch with link (Call) to function funC, return address stored in LR Return from function call Conditionally branch to address stored in R0 Branch with link and exchange (Call) to a address stored in R0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 181 12.6.10.2 CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. Syntax CBZ Rn, label CBNZ Rn, label where: Rn is the register holding the operand. label is the branch destination. Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions. CBZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BEQ label CBNZ Rn, label does not change condition flags but is otherwise equivalent to: CMP Rn, #0 BNE label Restrictions The restrictions are:  Rn must be in the range of R0 to R7  The branch destination must be within 4 to 130 bytes after the instruction  These instructions must not be used inside an IT block. Condition Flags These instructions do not change the flags. Examples CBZ CBNZ 182 R5, target R0, target SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 ; Forward branch if R5 is zero ; Forward branch if R0 is not zero 12.6.10.3 IT If-Then condition instruction. Syntax IT{x{y{z}}} cond where: x specifies the condition switch for the second instruction in the IT block. y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: T Then. Applies the condition cond to the instruction. E Else. Applies the inverse condition of cond to the instruction. It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in the IT block must be unconditional, and each of x, y, and z must be T or omitted but not E. Operation The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some of them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT block. The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their syntax. The assembler might be able to generate the required IT instructions for conditional instructions automatically, so that the user does not have to write them. See the assembler documentation for details. A BKPT instruction in an IT block is always executed, even if its condition fails. Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked PSR. Instructions designed for use for exception returns can be used as normal to return from the exception, and execution of the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to branch to an instruction in an IT block. Restrictions The following instructions are not permitted in an IT block:  IT  CBZ and CBNZ  CPSID and CPSIE. Other restrictions when using an IT block are:   A branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block. These are: ̶ ADD PC, PC, Rm ̶ MOV PC, Rm ̶ B, BL, BX, BLX ̶ Any LDM, LDR, or POP instruction that writes to the PC ̶ TBB and TBH Do not branch to any instruction inside an IT block, except when returning from an exception handler SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 183  All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one  Each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as for the other instructions in the block. Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives within them. Condition Flags This instruction does not change the flags. Example 12.6.10.4 ITTE ANDNE ADDSNE MOVEQ NE R0, R0, R1 R2, R2, #1 R2, R3 ; ; ; ; Next 3 instructions are conditional ANDNE does not update condition flags ADDSNE updates condition flags Conditional move CMP R0, #9 ITE ADDGT ADDLE GT R1, R0, #55 R1, R0, #48 ; ; ; ; ; Convert R0 hex value (0 to 15) into ASCII ('0'-'9', 'A'-'F') Next 2 instructions are conditional Convert 0xA -> 'A' Convert 0x0 -> '0' IT ADDGT GT R1, R1, #1 ; IT block with only one conditional instruction ; Increment R1 conditionally ITTEE MOVEQ ADDEQ ANDNE BNE.W EQ R0, R1 R2, R2, #10 R3, R3, #1 dloop ; ; ; ; ; ; IT ADD NE R0, R0, R1 ; Next instruction is conditional ; Syntax error: no condition code used in IT block Next 4 instructions are conditional Conditional move Conditional add Conditional AND Branch instruction can only be used in the last instruction of an IT block TBB and TBH Table Branch Byte and Table Branch Halfword. Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of the table is the address of the byte immediately following the TBB or TBH instruction. Rm 184 is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the value in Rm to form the right offset into the table. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Operation These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the address of the byte immediately after the TBB or TBH instruction. Restrictions The restrictions are:  Rn must not be SP  Rm must not be SP and must not be PC  When any of these instructions is used inside an IT block, it must be the last instruction of the IT block. Condition Flags These instructions do not change the flags. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 185 Examples ADR.W TBB R0, BranchTable_Byte [R0, R1] ; R1 is the index, R0 is the base address of the ; branch table Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 ; Case1 offset calculation DCB ((Case2-Case1)/2) ; Case2 offset calculation DCB ((Case3-Case1)/2) ; Case3 offset calculation TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the ; branch table BranchTable_H DCI ((CaseA - BranchTable_H)/2) DCI ((CaseB - BranchTable_H)/2) DCI ((CaseC - BranchTable_H)/2) CaseA ; an instruction sequence follows CaseB ; an instruction sequence follows CaseC ; an instruction sequence follows 186 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 ; CaseA offset calculation ; CaseB offset calculation ; CaseC offset calculation 12.6.11 Miscellaneous Instructions The table below shows the remaining Cortex-M4 instructions. Table 12-27. Miscellaneous Instructions Mnemonic Description BKPT Breakpoint CPSID Change Processor State, Disable Interrupts CPSIE Change Processor State, Enable Interrupts DMB Data Memory Barrier DSB Data Synchronization Barrier ISB Instruction Synchronization Barrier MRS Move from special register to register MSR Move from register to special register NOP No Operation SEV Send Event SVC Supervisor Call WFE Wait For Event WFI Wait For Interrupt SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 187 12.6.11.1 BKPT Breakpoint. Syntax BKPT #imm where: imm is an expression evaluating to an integer in the range 0–255 (8-bit value). Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition specified by the IT instruction. Condition Flags This instruction does not change the flags. Examples BKPT 0xAB Note: 12.6.11.2 ; Breakpoint with immediate value set to 0xAB (debugger can ; extract the immediate value by locating it using the PC) ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other than Semi-hosting. CPS Change Processor State. Syntax CPSeffect iflags where: effect is one of: IE Clears the special purpose register. ID Sets the special purpose register. iflags is a sequence of one or more flags: i Set or clear PRIMASK. f Set or clear FAULTMASK. Operation CPS changes the PRIMASK and FAULTMASK special register values. See “Exception Mask Registers” for more information about these registers. Restrictions The restrictions are: 188  Use CPS only from privileged software, it has no effect if used in unprivileged software  CPS cannot be conditional and so must not be used inside an IT block. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Condition Flags This instruction does not change the condition flags. Examples CPSID CPSID CPSIE CPSIE 12.6.11.3 i f i f ; ; ; ; Disable interrupts and configurable fault handlers (set PRIMASK) Disable interrupts and all fault handlers (set FAULTMASK) Enable interrupts and configurable fault handlers (clear PRIMASK) Enable interrupts and fault handlers (clear FAULTMASK) DMB Data Memory Barrier. Syntax DMB{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory. Condition Flags This instruction does not change the flags. Examples DMB ; Data Memory Barrier SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 189 12.6.11.4 DSB Data Synchronization Barrier. Syntax DSB{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. Condition Flags This instruction does not change the flags. Examples DSB ; Data Synchronisation Barrier 12.6.11.5 ISB Instruction Synchronization Barrier. Syntax ISB{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed. Condition Flags This instruction does not change the flags. Examples ISB 190 ; Instruction Synchronisation Barrier SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.11.6 MRS Move the contents of a special register to a general-purpose register. Syntax MRS{cond} Rd, spec_reg where: cond is an optional condition code, see “Conditional Execution” . Rd is the destination register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag. In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence. Note: BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction. See “MSR” . Restrictions Rd must not be SP and must not be PC. Condition Flags This instruction does not change the flags. Examples MRS 12.6.11.7 R0, PRIMASK ; Read PRIMASK value and write it to R0 MSR Move the contents of a general-purpose register into the specified special register. Syntax MSR{cond} spec_reg, Rn where: cond is an optional condition code, see “Conditional Execution” . Rn is the source register. spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 191 Operation The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR. See “Application Program Status Register” . Privileged software can access all special registers. In unprivileged software writes to unallocated or execution state bits in the PSR are ignored. Note: When the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either: Rn is non-zero and the current BASEPRI value is 0 Rn is non-zero and less than the current BASEPRI value. See “MRS” . Restrictions Rn must not be SP and must not be PC. Condition Flags This instruction updates the flags explicitly based on the value in Rn. Examples MSR 12.6.11.8 CONTROL, R1 ; Read R1 value and write it to the CONTROL register NOP No Operation. Syntax NOP{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to place the following instruction on a 64-bit boundary. Condition Flags This instruction does not change the flags. Examples NOP 192 ; No operation SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.6.11.9 SEV Send Event. Syntax SEV{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets the local event register to 1, see “Power Management” . Condition Flags This instruction does not change the flags. Examples SEV ; Send Event 12.6.11.10 SVC Supervisor Call. Syntax SVC{cond} #imm where: cond is an optional condition code, see “Conditional Execution” . imm is an expression evaluating to an integer in the range 0-255 (8-bit value). Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is being requested. Condition Flags This instruction does not change the flags. Examples SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value ; by locating it via the stacked PC) SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 193 12.6.11.11 WFE Wait For Event. Syntax WFE{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs:  An exception, unless masked by the exception mask registers or the current priority level  An exception enters the Pending state, if SEVONPEND in the System Control Register is set  A Debug Entry request, if Debug is enabled  An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction. If the event register is 1, WFE clears it to 0 and returns immediately. For more information, see “Power Management” . Condition Flags This instruction does not change the flags. Examples WFE 12.6.11.12 ; Wait for event WFI Wait for Interrupt. Syntax WFI{cond} where: cond is an optional condition code, see “Conditional Execution” . Operation WFI is a hint instruction that suspends execution until one of the following events occurs:  An exception  A Debug Entry request, regardless of whether Debug is enabled. Condition Flags This instruction does not change the flags. Examples WFI ; Wait for interrupt 194 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.7 Cortex-M4 Core Peripherals 12.7.1 Peripherals  Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. See Section 12.8 ”Nested Vectored Interrupt Controller (NVIC)”.  System Control Block (SCB) The System Control Block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. See Section 12.9 ”System Control Block (SCB)”.  System Timer (SysTick) The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick timer or as a simple counter. See Section 12.10 ”System Timer (SysTick)”.  Memory Protection Unit (MPU) The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different memory regions. It provides up to eight different regions, and an optional predefined background region. See Section 12.11 ”Memory Protection Unit (MPU)”. 12.7.2 Address Map The address map of the Private peripheral bus (PPB) is given in the following table. Table 12-28. Core Peripheral Register Regions Address Core Peripheral 0xE000E008–0xE000E00F System Control Block 0xE000E010–0xE000E01F System Timer 0xE000E100–0xE000E4EF Nested Vectored Interrupt Controller 0xE000ED00–0xE000ED3F System control block 0xE000ED90–0xE000EDB8 Memory Protection Unit 0xE000EF00–0xE000EF03 Nested Vectored Interrupt Controller In register descriptions:  The required privilege gives the privilege level required to access the register, as follows: ̶ Privileged: Only privileged software can access the register. ̶ Unprivileged: Both unprivileged and privileged software can access the register. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 195 12.8 Nested Vectored Interrupt Controller (NVIC) This section describes the NVIC and the registers it uses. The NVIC supports:  Up to 35 interrupts  A programmable priority level of 0–15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.  Level detection of interrupt signals  Dynamic reprioritization of interrupts  Grouping of priority values into group priority and subpriority fields  Interrupt tail-chaining  An external Non-maskable interrupt (NMI) The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling. 12.8.1 Level-sensitive Interrupts The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” ). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing. 12.8.1.1 Hardware and Software Control of Interrupts The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:  The NVIC detects that the interrupt signal is HIGH and the interrupt is not active  The NVIC detects a rising edge on the interrupt signal  A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending Registers” , or to the NVIC_STIR to make an interrupt pending, see “Software Trigger Interrupt Register” . A pending interrupt remains pending until one of the following:  The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then: ̶  For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. Software writes to the corresponding interrupt clear-pending register bit. For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 12.8.2 NVIC Design Hints and Tips Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt. 196 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector table are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the “Vector Table Offset Register” . 12.8.2.1 NVIC Programming Hints The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides the following intrinsic functions for these instructions: void __disable_irq(void) // Disable Interrupts void __enable_irq(void) // Enable Interrupts In addition, the CMSIS provides a number of functions for NVIC control, including: Table 12-29. CMSIS Functions for NVIC Control CMSIS Interrupt Control Function Description void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping void NVIC_EnableIRQ(IRQn_t IRQn) Enable IRQn void NVIC_DisableIRQ(IRQn_t IRQn) Disable IRQn uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn) Return true (IRQ-Number) if IRQn is pending void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status uint32_t NVIC_GetActive (IRQn_t IRQn) Return the IRQ number of the active interrupt void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn void NVIC_SystemReset (void) Reset the system The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS documentation. To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:   The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit integers, so that: ̶ The array ISER[0] to ISER[1] corresponds to the registers ISER0–ISER1 ̶ The array ICER[0] to ICER[1] corresponds to the registers ICER0–ICER1 ̶ The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0–ISPR1 ̶ The array ICPR[0] to ICPR[1] corresponds to the registers ICPR0–ICPR1 ̶ The array IABR[0] to IABR[1] corresponds to the registers IABR0–IABR1 The Interrupt Priority Registers (IPR0–IPR8) provide an 8-bit priority field for each interrupt and each register holds four priority fields. The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. Table 12-30 shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt. Table 12-30. Mapping of Interrupts CMSIS Array Elements (1) Interrupts Set-enable Clear-enable Set-pending Clear-pending Active Bit 0–31 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0] 32–35 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1] SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 197 Note: 198 1. Each array element corresponds to a single NVIC register, for example the ICER[0] element corresponds to the ICER0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface Table 12-31. Nested Vectored Interrupt Controller (NVIC) Register Mapping Offset Register Name Access Reset 0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read/Write 0x00000000 0XE000E180 Interrupt Clear-enable Register 0 NVIC_ICER0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E19C Interrupt Clear-enable Register 7 NVIC_ICER7 Read/Write 0x00000000 0XE000E200 Interrupt Set-pending Register 0 NVIC_ISPR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E21C Interrupt Set-pending Register 7 NVIC_ISPR7 Read/Write 0x00000000 0XE000E280 Interrupt Clear-pending Register 0 NVIC_ICPR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E29C Interrupt Clear-pending Register 7 NVIC_ICPR7 Read/Write 0x00000000 0xE000E300 Interrupt Active Bit Register 0 NVIC_IABR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E31C Interrupt Active Bit Register 7 NVIC_IABR7 Read/Write 0x00000000 0xE000E400 Interrupt Priority Register 0 NVIC_IPR0 Read/Write 0x00000000 ... ... ... ... ... 0xE000E420 Interrupt Priority Register 8 NVIC_IPR8 Read/Write 0x00000000 0xE000EF00 Software Trigger Interrupt Register NVIC_STIR Write-only 0x00000000 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 199 12.8.3.1 Interrupt Set-enable Registers Name: NVIC_ISERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETENA 23 22 21 20 SETENA 15 14 13 12 SETENA 7 6 5 4 SETENA These registers enable interrupts and show which interrupts are enabled. • SETENA: Interrupt Set-enable Write: 0: No effect. 1: Enables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled. Notes: 200 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. 2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never activates the interrupt, regardless of its priority. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.8.3.2 Interrupt Clear-enable Registers Name: NVIC_ICERx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRENA 23 22 21 20 CLRENA 15 14 13 12 CLRENA 7 6 5 4 CLRENA These registers disable interrupts, and show which interrupts are enabled. • CLRENA: Interrupt Clear-enable Write: 0: No effect. 1: Disables the interrupt. Read: 0: Interrupt disabled. 1: Interrupt enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 201 12.8.3.3 Interrupt Set-pending Registers Name: NVIC_ISPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SETPEND 23 22 21 20 SETPEND 15 14 13 12 SETPEND 7 6 5 4 SETPEND These registers force interrupts into the pending state, and show which interrupts are pending. • SETPEND: Interrupt Set-pending Write: 0: No effect. 1: Changes the interrupt state to pending. Read: 0: Interrupt is not pending. 1: Interrupt is pending. Notes: 202 1. Writing a 1 to an ISPR bit corresponding to an interrupt that is pending has no effect. 2. Writing a 1 to an ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to pending. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.8.3.4 Interrupt Clear-pending Registers Name: NVIC_ICPRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLRPEND 23 22 21 20 CLRPEND 15 14 13 12 CLRPEND 7 6 5 4 CLRPEND These registers remove the pending state from interrupts, and show which interrupts are pending. • CLRPEND: Interrupt Clear-pending Write: 0: No effect. 1: Removes the pending state from an interrupt. Read: 0: Interrupt is not pending. 1: Interrupt is pending. Note: Writing a 1 to an ICPR bit does not affect the active state of the corresponding interrupt. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 203 12.8.3.5 Interrupt Active Bit Registers Name: NVIC_IABRx [x=0..7] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACTIVE 23 22 21 20 ACTIVE 15 14 13 12 ACTIVE 7 6 5 4 ACTIVE These registers indicate which interrupts are active. • ACTIVE: Interrupt Active Flags 0: Interrupt is not active. 1: Interrupt is active. Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending. 204 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.8.3.6 Interrupt Priority Registers Name: NVIC_IPRx [x=0..8] Access: Read/Write Reset: 0x000000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PRI3 23 22 21 20 PRI2 15 14 13 12 PRI1 7 6 5 4 PRI0 The NVIC_IPR0–NVIC_IPR8 registers provide a 8-bit priority field for each interrupt. These registers are byte-accessible. Each register holds four priority fields that map up to four elements in the CMSIS interrupt priority array IP[0] to IP[34]. • PRI3: Priority (4m+3) Priority, Byte Offset 3, refers to register bits [31:24]. • PRI2: Priority (4m+2) Priority, Byte Offset 2, refers to register bits [23:16]. • PRI1: Priority (4m+1) Priority, Byte Offset 1, refers to register bits [15:8]. • PRI0: Priority (4m) Priority, Byte Offset 0, refers to register bits [7:0]. Notes: 1. Each priority field holds a priority value, 0–15. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:4] of each field; bits[3:0] read as zero and ignore writes. 2. For more information about the IP[0] to IP[34] interrupt priority array, that provides the software view of the interrupt priorities, see Table 12-29, “CMSIS Functions for NVIC Control” . 3. The corresponding IPR number n is given by n = m DIV 4. 4. The byte offset of the required Priority field in this register is m MOD 4. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 205 12.8.3.7 Software Trigger Interrupt Register Name: NVIC_STIR Access: Write-only Reset: 0x000000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INTID 7 6 5 4 3 2 1 0 INTID Write to this register to generate an interrupt from the software. • INTID: Interrupt ID Interrupt ID of the interrupt to trigger, in the range 0–239. For example, a value of 0x03 specifies interrupt IRQ3. 206 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9 System Control Block (SCB) The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. Ensure that the software uses aligned accesses of the correct size to access the system control block registers:  Except for the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it must use aligned word accesses  For the SCB_CFSR and SCB_SHPR1–SCB_SHPR3 registers, it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. In a fault handler, to determine the true faulting address: 1. Read and save the MMFAR or SCB_BFAR value. 2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1. The software must follow this sequence because another higher priority exception might change the SCB_MMFAR or SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the SCB_MMFAR or SCB_BFAR value. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 207 12.9.1 System Control Block (SCB) User Interface Table 12-32. System Control Block (SCB) Register Mapping Offset Register Name Access Reset 0xE000E008 Auxiliary Control Register SCB_ACTLR Read/Write 0x00000000 0xE000ED00 CPUID Base Register SCB_CPUID Read-only 0x410FC240 0xE000ED04 Interrupt Control and State Register SCB_ICSR Read/Write(1) 0x00000000 0xE000ED08 Vector Table Offset Register SCB_VTOR Read/Write 0x00000000 0xE000ED0C Application Interrupt and Reset Control Register SCB_AIRCR Read/Write 0xFA050000 0xE000ED10 System Control Register SCB_SCR Read/Write 0x00000000 0xE000ED14 Configuration and Control Register SCB_CCR Read/Write 0x00000200 0xE000ED18 System Handler Priority Register 1 SCB_SHPR1 Read/Write 0x00000000 0xE000ED1C System Handler Priority Register 2 SCB_SHPR2 Read/Write 0x00000000 0xE000ED20 System Handler Priority Register 3 SCB_SHPR3 Read/Write 0x00000000 0xE000ED24 System Handler Control and State Register SCB_SHCSR Read/Write 0x00000000 (2) Read/Write 0x00000000 0xE000ED28 Configurable Fault Status Register SCB_CFSR 0xE000ED2C HardFault Status Register SCB_HFSR Read/Write 0x00000000 0xE000ED34 MemManage Fault Address Register SCB_MMFAR Read/Write Unknown 0xE000ED38 BusFault Address Register SCB_BFAR Read/Write Unknown 0xE000ED3C Auxiliary Fault Status Register SCB_AFSR Read/Write 0x00000000 Notes: 208 1. See the register description for more information. 2. This register contains the subregisters: “MMFSR: Memory Management Fault Status Subregister” (0xE000ED28 - 8 bits), “BFSR: Bus Fault Status Subregister” (0xE000ED29 - 8 bits), “UFSR: Usage Fault Status Subregister” (0xE000ED2A - 16 bits). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.1 Auxiliary Control Register Name: SCB_ACTLR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 DISOOFP 8 DISFPCA 7 – 6 – 5 – 4 – 3 – 2 DISFOLD 1 DISDEFWBUF 0 DISMCYCINT The SCB_ACTLR provides disable bits for the following processor functions: • IT folding • Write buffer use for accesses to the default memory map • Interruption of multi-cycle instructions. By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally require modification. • DISOOFP: Disable Out Of Order Floating Point Disables floating point instructions that complete out of order with respect to integer instructions. • DISFPCA: Disable FPCA Disables an automatic update of CONTROL.FPCA. • DISFOLD: Disable Folding When set to 1, disables the IT folding. Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction. This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding. • DISDEFWBUF: Disable Default Write Buffer When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise but decreases the performance, as any store to memory must complete before the processor can execute the next instruction. This bit only affects write buffers implemented in the Cortex-M4 processor. • DISMCYCINT: Disable Multiple Cycle Interruption When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the interrupt latency of the processor, as any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 209 12.9.1.2 CPUID Base Register Name: SCB_CPUID Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 9 8 1 0 Implementer 23 22 21 20 Variant 15 14 Constant 13 12 11 10 3 2 PartNo 7 6 5 4 PartNo Revision The SCB_CPUID register contains the processor part number, version, and implementation information. • Implementer: Implementer Code 0x41: ARM. • Variant: Variant Number It is the r value in the rnpn product revision identifier: 0x0: Revision 0. • Constant: Reads as 0xF Reads as 0xF. • PartNo: Part Number of the Processor 0xC24 = Cortex-M4. • Revision: Revision Number It is the p value in the rnpn product revision identifier: 0x0: Patch 0. 210 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.3 Interrupt Control and State Register Name: SCB_ICSR Access: Read/Write 31 NMIPENDSET 30 29 28 PENDSVSET 23 – 22 ISRPENDING 21 20 15 14 13 VECTPENDING 12 7 6 4 – 5 27 PENDSVCLR 26 PENDSTSET 19 18 VECTPENDING 25 PENDSTCLR 24 – 17 16 11 RETTOBASE 10 – 9 – 8 VECTACTIVE 3 2 1 0 VECTACTIVE The SCB_ICSR provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and clearpending bits for the PendSV and SysTick exceptions. It indicates: • The exception number of the exception being processed, and whether there are preempted active exceptions, • The exception number of the highest priority pending exception, and whether any interrupts are pending. • NMIPENDSET: NMI Set-pending Write: PendSV set-pending bit. Write: 0: No effect. 1: Changes NMI exception state to pending. Read: 0: NMI exception is not pending. 1: NMI exception is pending. As NMI is the highest-priority exception, the processor normally enters the NMI exception handler as soon as it registers a write of 1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. • PENDSVSET: PendSV Set-pending Write: 0: No effect. 1: Changes PendSV exception state to pending. Read: 0: PendSV exception is not pending. 1: PendSV exception is pending. Writing a 1 to this bit is the only way to set the PendSV exception state to pending. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 211 • PENDSVCLR: PendSV Clear-pending Write: 0: No effect. 1: Removes the pending state from the PendSV exception. • PENDSTSET: SysTick Exception Set-pending Write: 0: No effect. 1: Changes SysTick exception state to pending. Read: 0: SysTick exception is not pending. 1: SysTick exception is pending. • PENDSTCLR: SysTick Exception Clear-pending Write: 0: No effect. 1: Removes the pending state from the SysTick exception. This bit is Write-only. On a register read, its value is Unknown. • ISRPENDING: Interrupt Pending Flag (Excluding NMI and Faults) 0: Interrupt not pending. 1: Interrupt pending. • VECTPENDING: Exception Number of the Highest Priority Pending Enabled Exception 0: No pending exceptions. Nonzero: The exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. • RETTOBASE: Preempted Active Exceptions Present or Not 0: There are preempted active exceptions to execute. 1: There are no active exceptions, or the currently-executing exception is the only active exception. • VECTACTIVE: Active Exception Number Contained 0: Thread mode. Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See “Interrupt Program Status Register” . Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, ClearPending, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” . Note: When the user writes to the SCB_ICSR, the effect is unpredictable if: - Writing a 1 to the PENDSVSET bit and writing a 1 to the PENDSVCLR bit - Writing a 1 to the PENDSTSET bit and writing a 1 to the PENDSTCLR bit. 212 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.4 Vector Table Offset Register Name: SCB_VTOR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 – TBLOFF 23 22 21 20 TBLOFF 15 14 13 12 TBLOFF 7 TBLOFF 6 – 5 – 4 – The SCB_VTOR indicates the offset of the vector table base address from memory address 0x00000000. • TBLOFF: Vector Table Base Offset It contains bits [29:7] of the offset of the table base from the bottom of the memory map. Bit [29] determines whether the vector table is in the code or SRAM memory region: 0: Code. 1: SRAM. It is sometimes called the TBLBASE bit. Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the next statement to give the information required for your implementation; the statement reminds the user of how to determine the alignment requirement. The minimum alignment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64. Table alignment requirements mean that bits[6:0] of the table offset are always zero. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 213 12.9.1.5 Application Interrupt and Reset Control Register Name: SCB_AIRCR Access: Read/Write 31 30 29 28 27 VECTKEYSTAT/VECTKEY 26 25 24 23 22 21 20 19 VECTKEYSTAT/VECTKEY 18 17 16 15 ENDIANNESS 14 – 13 – 12 – 11 – 10 9 PRIGROUP 8 7 – 6 – 5 – 4 – 3 – 2 1 0 SYSRESETREQ VECTCLRACTIVE VECTRESET The SCB_AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores the write. • VECTKEYSTAT: Register Key (Read) Reads as 0xFA05. • VECTKEY: Register Key (Write) Writes 0x5FA to VECTKEY, otherwise the write is ignored. • ENDIANNESS: Data Endianness 0: Little-endian. 1: Big-endian. • PRIGROUP: Interrupt Priority Grouping This field determines the split of group priority from subpriority. It shows the position of the binary point that splits the PRI_n fields in the Interrupt Priority Registers into separate group priority and subpriority fields. The table below shows how the PRIGROUP value controls this split. Interrupt Priority Level Value, PRI_N[7:0] Number of PRIGROUP Binary Point (1) Group Priority Bits Subpriority Bits Group Priorities Subpriorities 0b000 bxxxxxxx.y [7:1] None 128 2 0b001 bxxxxxx.yy [7:2] [4:0] 64 4 0b010 bxxxxx.yyy [7:3] [4:0] 32 8 0b011 bxxxx.yyyy [7:4] [4:0] 16 16 0b100 bxxx.yyyyy [7:5] [4:0] 8 32 0b101 bxx.yyyyyy [7:6] [5:0] 4 64 0b110 bx.yyyyyyy [7] [6:0] 2 128 0b111 b.yyyyyyy None [7:0] 1 256 Note: 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit. Determining preemption of an exception uses only the group priority field. 214 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • SYSRESETREQ: System Reset Request 0: No system reset request. 1: Asserts a signal to the outer system that requests a reset. This is intended to force a large system reset of all major components except for debug. This bit reads as 0. • VECTCLRACTIVE: Reserved for Debug use This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable. • VECTRESET: Reserved for Debug use This bit reads as 0. When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 215 12.9.1.6 System Control Register Name: SCB_SCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 SEVONPEND 3 – 2 SLEEPDEEP 1 SLEEPONEXIT 0 – • SEVONPEND: Send Event on Pending Bit 0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor. When an event or an interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. • SLEEPDEEP: Sleep or Deep Sleep Controls whether the processor uses sleep or deep sleep as its low power mode: 0: Sleep. 1: Deep sleep. • SLEEPONEXIT: Sleep-on-exit Indicates sleep-on-exit when returning from the Handler mode to the Thread mode: 0: Do not sleep when returning to Thread mode. 1: Enter sleep, or deep sleep, on return from an ISR. Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application. 216 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.7 Configuration and Control Register Name: SCB_CCR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 STKALIGN 8 BFHFNMIGN 7 6 5 4 3 2 1 0 – – – DIV_0_TRP UNALIGN_TRP – NONBASETHRDE USERSETMPEND NA The SCB_CCR controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the access to the NVIC_STIR by unprivileged software (see “Software Trigger Interrupt Register” ). • STKALIGN: Stack Alignment Indicates the stack alignment on exception entry: 0: 4-byte aligned. 1: 8-byte aligned. On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. • BFHFNMIGN: Bus Faults Ignored Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the hard fault and FAULTMASK escalated handlers: 0: Data bus faults caused by load and store instructions cause a lock-up. 1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. • DIV_0_TRP: Division by Zero Trap Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. 1: Trap divide by 0. When this bit is set to 0, a divide by zero returns a quotient of 0. • UNALIGN_TRP: Unaligned Access Trap Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses. 1: Trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 217 Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. • USERSETMPEND: Unprivileged Software Access Enables unprivileged software access to the NVIC_STIR, see “Software Trigger Interrupt Register” : 0: Disable. 1: Enable. • NONBASETHRDENA: Thread Mode Enable Indicates how the processor enters Thread mode: 0: The processor can enter the Thread mode only when no exception is active. 1: The processor can enter the Thread mode from any level under the control of an EXC_RETURN value, see “Exception Return” . 218 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.8 System Handler Priority Registers The SCB_SHPR1–SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority. They are byte-accessible. The system fault handlers and the priority field and register for each handler are: Table 12-33. System Fault Handler Priority Fields Handler Field Memory management fault (MemManage) PRI_4 Bus fault (BusFault) PRI_5 Usage fault (UsageFault) PRI_6 SVCall PRI_11 PendSV PRI_14 SysTick PRI_15 Register Description System Handler Priority Register 1 System Handler Priority Register 2 System Handler Priority Register 3 Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and ignore writes. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 219 12.9.1.9 System Handler Priority Register 1 Name: SCB_SHPR1 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 PRI_6 15 14 13 12 PRI_5 7 6 5 4 PRI_4 • PRI_6: Priority Priority of system handler 6, UsageFault. • PRI_5: Priority Priority of system handler 5, BusFault. • PRI_4: Priority Priority of system handler 4, MemManage. 220 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.10 System Handler Priority Register 2 Name: SCB_SHPR2 Access: Read/Write 31 30 29 28 27 26 25 24 PRI_11 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PRI_11: Priority Priority of system handler 11, SVCall. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 221 12.9.1.11 System Handler Priority Register 3 Name: SCB_SHPR3 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 PRI_15 23 22 21 20 PRI_14 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • PRI_15: Priority Priority of system handler 15, SysTick exception. • PRI_14: Priority Priority of system handler 14, PendSV. 222 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.12 System Handler Control and State Register Name: SCB_SHCSR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 23 – 22 – 21 – 20 – 19 – 15 14 13 12 11 SVCALLPENDED 7 SVCALLACT 26 – 5 – 4 – 24 – 18 17 16 USGFAULTENA BUSFAULTENA MEMFAULTENA BUSFAULTPEND MEMFAULTPEND USGFAULTPEND SYSTICKACT ED ED ED 6 – 25 – 3 USGFAULTACT 10 9 8 PENDSVACT – MONITORACT 2 – 1 0 BUSFAULTACT MEMFAULTACT The SHCSR enables the system handlers, and indicates the pending status of the bus fault, memory management fault, and SVC exceptions; it also indicates the active status of the system handlers. • USGFAULTENA: Usage Fault Enable 0: Disables the exception. 1: Enables the exception. • BUSFAULTENA: Bus Fault Enable 0: Disables the exception. 1: Enables the exception. • MEMFAULTENA: Memory Management Fault Enable 0: Disables the exception. 1: Enables the exception. • SVCALLPENDED: SVC Call Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • BUSFAULTPENDED: Bus Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 223 • MEMFAULTPENDED: Memory Management Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • USGFAULTPENDED: Usage Fault Exception Pending Read: 0: The exception is not pending. 1: The exception is pending. Note: The user can write to these bits to change the pending status of the exceptions. • SYSTICKACT: SysTick Exception Active Read: 0: The exception is not active. 1: The exception is active. Note: The user can write to these bits to change the active status of the exceptions. - Caution: A software that changes the value of an active bit in this register without a correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure that the software writing to this register retains and subsequently restores the current active status. - Caution: After enabling the system handlers, to change the value of a bit in this register, the user must use a read-modify-write procedure to ensure that only the required bit is changed. • PENDSVACT: PendSV Exception Active 0: The exception is not active. 1: The exception is active. • MONITORACT: Debug Monitor Active 0: Debug monitor is not active. 1: Debug monitor is active. • SVCALLACT: SVC Call Active 0: SVC call is not active. 1: SVC call is active. • USGFAULTACT: Usage Fault Exception Active 0: Usage fault exception is not active. 1: Usage fault exception is active. • BUSFAULTACT: Bus Fault Exception Active 0: Bus fault exception is not active. 1: Bus fault exception is active. • MEMFAULTACT: Memory Management Fault Exception Active 0: Memory management fault exception is not active. 1: Memory management fault exception is active. 224 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault. The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. 12.9.1.13 Configurable Fault Status Register Name: SCB_CFSR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 DIVBYZERO 24 UNALIGNED 23 – 22 – 21 – 20 – 19 NOCP 18 INVPC 17 INVSTATE 16 UNDEFINSTR 15 BFARVALID 14 – 13 12 STKERR 11 UNSTKERR 10 IMPRECISERR 9 PRECISERR 8 IBUSERR 7 MMARVALID 6 – 5 4 MSTKERR 3 MUNSTKERR 2 – 1 DACCVIOL 0 IACCVIOL – – • IACCVIOL: Instruction Access Violation Flag This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: No instruction access violation fault. 1: The processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not written a fault address to the SCB_MMFAR. • DACCVIOL: Data Access Violation Flag This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: No data access violation fault. 1: The processor attempted a load or store at a location that does not permit the operation. When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded the SCB_MMFAR with the address of the attempted access. • MUNSTKERR: Memory Manager Fault on Unstacking for a Return From Exception This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: No unstacking fault. 1: Unstack for an exception return has caused one or more access violations. This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The processor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a fault address to the SCB_MMFAR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 225 • MSTKERR: Memory Manager Fault on Stacking for Exception Entry This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: No stacking fault. 1: Stacking for an exception entry has caused one or more access violations. When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor has not written a fault address to SCB_MMFAR. • MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag This is part of “MMFSR: Memory Management Fault Status Subregister” . 0: The value in SCB_MMFAR is not a valid fault address. 1: SCB_MMFAR holds a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose SCB_MMFAR value has been overwritten. • IBUSERR: Instruction Bus Error This is part of “BFSR: Bus Fault Status Subregister” . 0: No instruction bus error. 1: Instruction bus error. The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting instruction. When the processor sets this bit to 1, it does not write a fault address to the BFAR. • PRECISERR: Precise Data Bus Error This is part of “BFSR: Bus Fault Status Subregister” . 0: No precise data bus error. 1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR. • IMPRECISERR: Imprecise Data Bus Error This is part of “BFSR: Bus Fault Status Subregister” . 0: No imprecise data bus error. 1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR. This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both this bit and one of the precise fault status bits are set to 1. 226 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • UNSTKERR: Bus Fault on Unstacking for a Return From Exception This is part of “BFSR: Bus Fault Status Subregister” . 0: No unstacking fault. 1: Unstack for an exception return has caused one or more bus faults. This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address to the BFAR. • STKERR: Bus Fault on Stacking for Exception Entry This is part of “BFSR: Bus Fault Status Subregister” . 0: No stacking fault. 1: Stacking for an exception entry has caused one or more bus faults. When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the SCB_BFAR. • BFARVALID: Bus Fault Address Register (BFAR) Valid flag This is part of “BFSR: Bus Fault Status Subregister” . 0: The value in SCB_BFAR is not a valid fault address. 1: SCB_BFAR holds a valid fault address. The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten. • UNDEFINSTR: Undefined Instruction Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . 0: No undefined instruction usage fault. 1: The processor has attempted to execute an undefined instruction. When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. • INVSTATE: Invalid State Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . 0: No invalid state usage fault. 1: The processor has attempted to execute an instruction that makes illegal use of the EPSR. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. This bit is not set to 1 if an undefined instruction uses the EPSR. • INVPC: Invalid PC Load Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN: 0: No invalid PC load usage fault. 1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 227 When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. • NOCP: No Coprocessor Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . The processor does not support coprocessor instructions: 0: No usage fault caused by attempting to access a coprocessor. 1: The processor has attempted to access a coprocessor. • UNALIGNED: Unaligned Access Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . 0: No unaligned access fault, or unaligned access trapping not enabled. 1: The processor has made an unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR to 1. See “Configuration and Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP. • DIVBYZERO: Divide by Zero Usage Fault This is part of “UFSR: Usage Fault Status Subregister” . 0: No divide by zero fault, or divide by zero trapping not enabled. 1: The processor has executed an SDIV or UDIV instruction with a divisor of 0. When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR to 1. See “Configuration and Control Register” . 228 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.14 Configurable Fault Status Register (Byte Access) Name: SCB_CFSR (BYTE) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UFSR 23 22 21 20 UFSR 15 14 13 12 BFSR 7 6 5 4 MMFSR • MMFSR: Memory Management Fault Status Subregister The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section 12.9.1.13. • BFSR: Bus Fault Status Subregister The flags in the BFSR subregister indicate the cause of a bus access fault. See bitfield [14..8] description in Section 12.9.1.13. • UFSR: Usage Fault Status Subregister The flags in the UFSR subregister indicate the cause of a usage fault. See bitfield [31..15] description in Section 12.9.1.13. Note: The UFSR bits are sticky. This means that as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by wrting a 1 to that bit, or by a reset. The SCB_CFSR indicates the cause of a memory management fault, bus fault, or usage fault. It is byte accessible. The user can access the SCB_CFSR or its subregisters as follows: • Access complete SCB_CFSR with a word access to 0xE000ED28 • Access MMFSR with a byte access to 0xE000ED28 • Access MMFSR and BFSR with a halfword access to 0xE000ED28 • Access BFSR with a byte access to 0xE000ED29 • Access UFSR with a halfword access to 0xE000ED2A. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 229 12.9.1.15 Hard Fault Status Register Name: SCB_HFSR Access: Read/Write 31 DEBUGEVT 30 FORCED 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 VECTTBL 0 – The SCB_HFSR gives information about events that activate the hard fault handler. This register is read, write to clear. This means that bits in the register read normally, but wrting a 1 to any bit clears that bit to 0. • DEBUGEVT: Reserved for Debug Use When writing to the register, write a 0 to this bit, otherwise the behavior is unpredictable. • FORCED: Forced Hard Fault It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled: 0: No forced hard fault. 1: Forced hard fault. When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault. • VECTTBL: Bus Fault on a Vector Table It indicates a bus fault on a vector table read during an exception processing: 0: No bus fault on vector table read. 1: Bus fault on vector table read. This error is always handled by the hard fault handler. When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the exception. Note: The HFSR bits are sticky. This means that, as one or more fault occurs, the associated bits are set to 1. A bit that is set to 1 is cleared to 0 only by wrting a 1 to that bit, or by a reset. 230 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.9.1.16 MemManage Fault Address Register Name: SCB_MMFAR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_MMFAR contains the address of the location that generated a memory management fault. • ADDRESS: Memory Management Fault Generation Location Address When the MMARVALID bit of the MMFSR subregister is set to 1, this field holds the address of the location that generated the memory management fault. Notes: 1. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. 2. Flags in the MMFSR subregister indicate the cause of the fault, and whether the value in the SCB_MMFAR is valid. See “MMFSR: Memory Management Fault Status Subregister” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 231 12.9.1.17 Bus Fault Address Register Name: SCB_BFAR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDRESS 23 22 21 20 ADDRESS 15 14 13 12 ADDRESS 7 6 5 4 ADDRESS The SCB_BFAR contains the address of the location that generated a bus fault. • ADDRESS: Bus Fault Generation Location Address When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the bus fault. Notes: 232 1. When an unaligned access faults, the address in the SCB_BFAR is the one requested by the instruction, even if it is not the address of the fault. 2. Flags in the BFSR indicate the cause of the fault, and whether the value in the SCB_BFAR is valid. See “BFSR: Bus Fault Status Subregister” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.10 System Timer (SysTick) The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the SYST_RVR on the next clock edge, then counts down on subsequent clocks. When the processor is halted for debugging, the counter does not decrement. The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure that the software uses aligned word accesses to access the SysTick registers. The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the SysTick counter is: 1. Program the reload value. 2. Clear the current value. 3. Program the Control and Status register. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 233 12.10.1 System Timer (SysTick) User Interface Table 12-34. System Timer (SYST) Register Mapping Offset Register Name Access Reset 0xE000E010 SysTick Control and Status Register SYST_CSR Read/Write 0x00000000 0xE000E014 SysTick Reload Value Register SYST_RVR Read/Write Unknown 0xE000E018 SysTick Current Value Register SYST_CVR Read/Write Unknown 0xE000E01C SysTick Calibration Value Register SYST_CALIB Read-only 0x000030D4 234 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.10.1.1 SysTick Control and Status Register Name: SYST_CSR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 COUNTFLAG 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 CLKSOURCE 1 TICKINT 0 ENABLE The SysTick SYST_CSR enables the SysTick features. • COUNTFLAG: Count Flag Returns 1 if the timer counted to 0 since the last time this was read. • CLKSOURCE: Clock Source Indicates the clock source: 0: External Clock. 1: Processor Clock. • TICKINT: SysTick Exception Request Enable Enables a SysTick exception request: 0: Counting down to zero does not assert the SysTick exception request. 1: Counting down to zero asserts the SysTick exception request. The software can use COUNTFLAG to determine if SysTick has ever counted to zero. • ENABLE: Counter Enable Enables the counter: 0: Counter disabled. 1: Counter enabled. When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR and then counts down. On reaching 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the RELOAD value again, and begins counting. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 235 12.10.1.2 SysTick Reload Value Registers Name: SYST_RVR Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 RELOAD 15 14 13 12 RELOAD 7 6 5 4 RELOAD The SYST_RVR specifies the start value to load into the SYST_CVR. • RELOAD: SYST_CVR Load Value Value to load into the SYST_CVR when the counter is enabled and when it reaches 0. The RELOAD value can be any value in the range 0x00000001–0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0. The RELOAD value is calculated according to its use: For example, to generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. 236 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.10.1.3 SysTick Current Value Register Name: SYST_CVR Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CURRENT 15 14 13 12 CURRENT 7 6 5 4 CURRENT The SysTick SYST_CVR contains the current value of the SysTick counter. • CURRENT: SysTick Counter Current Value Reads return the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 237 12.10.1.4 SysTick Calibration Value Register Name: SYST_CALIB Access: Read/Write 31 NOREF 30 SKEW 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 TENMS 15 14 13 12 TENMS 7 6 5 4 TENMS The SysTick SYST_CSR indicates the SysTick calibration properties. • NOREF: No Reference Clock It indicates whether the device provides a reference clock to the processor: 0: Reference clock provided. 1: No reference clock provided. If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes. • SKEW: TENMS Value Verification It indicates whether the TENMS value is exact: 0: TENMS value is exact. 1: TENMS value is inexact, or not given. An inexact TENMS value can affect the suitability of SysTick as a software real time clock. • TENMS: Ten Milliseconds The reload value for 10 ms (100 Hz) timing is subject to system clock skew errors. If the value reads as zero, the calibration value is not known. The TENMS field default value is 0x000030D4 (12500 decimal). In order to achieve a 1 ms timebase on SystTick, the TENMS field must be programmed to a value corresponding to the processor clock frequency (in kHz) divided by 8. For example, for devices running the processor clock at 48 MHz, the TENMS field value must be 0x0001770 (48000 kHz/8). 238 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11 Memory Protection Unit (MPU) The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports:  Independent attribute settings for each region  Overlapping regions  Export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines:  Eight separate memory regions, 0–7  A background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault. This causes a fault exception, and might cause the termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. The configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” ). Table 12-35 shows the possible MPU region attributes. These include Share ability and cache behavior attributes that are not relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” for guidelines for programming such an implementation. Table 12-35. Memory Attributes Summary Memory Type Shareability Other Attributes Description Strongly-ordered – – All accesses to Strongly-ordered memory occur in program order. All Strongly-ordered regions are assumed to be shared. Shared – Memory-mapped peripherals that several processors share. Non-shared – Memory-mapped peripherals that only a single processor uses. Shared Non-cacheable Writethrough Cacheable Write-back Cacheable Normal memory that is shared between several processors. Non-shared Non-cacheable Writethrough Cacheable Write-back Cacheable Normal memory that only a single processor uses. Device Normal 12.11.1 MPU Access Permission Attributes This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and XN) of the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 239 The table below shows the encodings for the TEX, C, B, and S access permission bits. Table 12-36. TEX C 0 TEX, C, B, and S Encoding B 0 1 S Memory Type Shareability Other Attributes x (1) Strongly-ordered Shareable – x (1) Device Shareable – Normal Not shareable 0 0 b000 1 Outer and inner write-through. No write allocate. Shareable 1 Not shareable 0 1 0 Normal 1 Shareable 0 Not shareable 0 Normal 1 x (1) Reserved encoding – 0 x (1) Implementation defined attributes. – 1 Not shareable 0 1 Normal 1 Not shareable 0 x (1) Device 1 x (1) Reserved encoding – (1) Reserved encoding – x (1) x 0 b1BB A A Normal 1 Note: 1. Outer and inner write-back. Write and read allocate. Shareable 0 1 Outer and inner noncacheable. Shareable 1 b001 b010 Outer and inner write-back. No write allocate. Not shareable Nonshared Device. Cached memory BB = outer policy, AA = inner policy. Shareable The MPU ignores the value of this bit. Table 12-37 shows the cache policy for memory attribute encodings with a TEX value is in the range 4–7. Table 12-37. 240 Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding Cache Policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 12-38 shows the AP encodings that define the access permissions for privileged and unprivileged software. Table 12-38. 12.11.1.1 AP Encoding AP[2:0] Privileged Permissions Unprivileged Permissions Description 000 No access No access All accesses generate a permission fault 001 RW No access Access from privileged software only 010 RW RO Writes by unprivileged software generate a permission fault 011 RW RW Full access 100 Unpredictable Unpredictable Reserved 101 RO No access Reads by privileged software only 110 RO RO Read only, by privileged or unprivileged software 111 RO RO Read only, by privileged or unprivileged software MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault, see “Exceptions and Interrupts” . The MMFSR indicates the cause of the fault. See “MMFSR: Memory Management Fault Status Subregister” for more information. 12.11.1.2 Updating an MPU Region To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASRs. Each register can be programed separately, or a multiple-word write can be used to program all of these registers. MPU_RBAR and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM instruction. 12.11.1.3 Updating an MPU Region Using Separate Words Simple code to configure one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR STR R1, [R0, #0x0] STR R4, [R0, #0x4] STRH R2, [R0, #0x8] STRH R3, [R0, #0xA] ; ; ; ; ; 0xE000ED98, MPU region number register Region Number Region Base Address Region Size and Enable Region Attribute Disable a region before writing new region settings to the MPU, if the region being changed was previously enabled. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 241 STRH R2, [R0, #0x8] ; Region Size and Enable The software must use memory barrier instructions:  Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings  After the MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanisms cause memory barrier behavior. The software does not need any memory barrier instructions during an MPU setup, because it accesses the MPU through the PPB, which is a Strongly-Ordered memory region. For example, if the user wants all of the memory access behavior to take effect immediately after the programming sequence, a DSB instruction and an ISB instruction must be used. A DSB is required after changing MPU settings, such as at the end of a context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. 12.11.1.4 Updating an MPU Region Using Multi-word Writes The user can program directly using multi-word writes, depending on how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region Number, address, attribute, size and enable This can be done in two words for pre-packed information. This means that the MPU_RBAR contains the required region number and had the VALID bit set to 1. See “MPU Region Base Address Register” . Use this when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and ; region number combined with VALID (bit 4) set to 1 STR R2, [R0, #0x4] ; Region Attribute, Size and Enable Use an STM instruction to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register 242 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 STM R0, {R1-R2} 12.11.1.5 ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” . The least significant bit of SRD controls the first subregion, and the most significant bit controls the last subregion. Disabling a subregion means another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be set to 0x00, otherwise the MPU behavior is unpredictable. 12.11.1.6 Example of SRD Use Two regions with the same base address overlap. Region 1 is 128 KB, and region 2 is 512 KB. To ensure the attributes from region 1 apply to the first 128 KB region, set the SRD field for region 2 to b00000011 to disable the first two subregions, as in Figure 12-13 below: Figure 12-13. SRD Use Region 2, with subregions Region 1 Base address of both regions 12.11.1.7 Offset from base address 512KB 448KB 384KB 320KB 256KB 192KB 128KB Disabled subregion 64KB Disabled subregion 0 MPU Design Hints And Tips To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure the software uses aligned accesses of the correct size to access MPU registers:  Except for the MPU_RASR, it must use aligned word accesses  For the MPU_RASR, it can use byte or aligned halfword or word accesses. The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. MPU Configuration for a Microcontroller Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as follows: Table 12-39. Memory Region Attributes for a Microcontroller Memory Region TEX C B S Memory Type and Attributes Flash memory b000 1 0 0 Normal memory, non-shareable, write-through Internal SRAM b000 1 0 1 Normal memory, shareable, write-through External SRAM b000 1 1 1 Normal memory, shareable, write-back, write-allocate Peripherals b000 0 1 1 Device memory, shareable SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 243 In most microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the shareability attribute might be important. In these cases, refer to the recommendations of the memory device manufacturer. 244 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11.2 Memory Protection Unit (MPU) User Interface Table 12-40. Memory Protection Unit (MPU) Register Mapping Offset Register Name Access Reset 0xE000ED90 MPU Type Register MPU_TYPE Read-only 0x00000800 0xE000ED94 MPU Control Register MPU_CTRL Read/Write 0x00000000 0xE000ED98 MPU Region Number Register MPU_RNR Read/Write 0x00000000 0xE000ED9C MPU Region Base Address Register MPU_RBAR Read/Write 0x00000000 0xE000EDA0 MPU Region Attribute and Size Register MPU_RASR Read/Write 0x00000000 0xE000EDA4 MPU Region Base Address Register Alias 1 MPU_RBAR_A1 Read/Write 0x00000000 0xE000EDA8 MPU Region Attribute and Size Register Alias 1 MPU_RASR_A1 Read/Write 0x00000000 0xE000EDAC MPU Region Base Address Register Alias 2 MPU_RBAR_A2 Read/Write 0x00000000 0xE000EDB0 MPU Region Attribute and Size Register Alias 2 MPU_RASR_A2 Read/Write 0x00000000 0xE000EDB4 MPU Region Base Address Register Alias 3 MPU_RBAR_A3 Read/Write 0x00000000 0xE000EDB8 MPU Region Attribute and Size Register Alias 3 MPU_RASR_A3 Read/Write 0x00000000 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 245 12.11.2.1 MPU Type Register Name: MPU_TYPE Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 SEPARATE IREGION 15 14 13 12 DREGION 7 – 6 – 5 – 4 – The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. • IREGION: Instruction Region Indicates the number of supported MPU instruction regions. Always contains 0x00. The MPU memory map is unified and is described by the DREGION field. • DREGION: Data Region Indicates the number of supported MPU data regions: 0x08 = Eight MPU regions. • SEPARATE: Separate Instruction Indicates support for unified or separate instruction and date memory maps: 0: Unified. 246 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11.2.2 MPU Control Register Name: MPU_CTRL Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 PRIVDEFENA 1 HFNMIENA 0 ENABLE The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. • PRIVDEFENA: Privileged Default Memory Map Enable Enables privileged software access to the default memory map: 0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as a region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. • HFNMIENA: Hard Fault and NMI Enable Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers. When the MPU is enabled: 0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable. • ENABLE: MPU Enable Enables the MPU: 0: MPU disabled. 1: MPU enabled. When ENABLE and PRIVDEFENA are both set to 1: • For privileged accesses, the default memory map is as described in “Memory Model” . Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. • Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 247 XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can operate. When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the MPU is not implemented. The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFENA is set to 1. Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities. 248 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11.2.3 MPU Region Number Register Name: MPU_RNR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 REGION The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASRs. • REGION: MPU Region Referenced by the MPU_RBAR and MPU_RASRs Indicates the MPU region referenced by the MPU_RBAR and MPU_RASRs. The MPU supports 8 memory regions, so the permitted values of this field are 0–7. Normally, the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR. However, the region number can be changed by writing to the MPU_RBAR with the VALID bit set to 1; see “MPU Region Base Address Register” . This write updates the value of the REGION field. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 249 12.11.2.4 MPU Region Base Address Register Name: MPU_RBAR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region (SIZE field in the MPU_RASR). If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. 250 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11.2.5 MPU Region Attribute and Size Register Name: MPU_RASR Access: Read/Write 31 – 30 – 29 – 28 XN 27 – 26 25 AP 24 23 – 22 – 21 20 TEX 19 18 S 17 C 16 B 15 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-38. • TEX, C, B: Memory Access Attributes See Table 12-36. • S: Shareable See Table 12-36. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 251 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes” . 252 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11.2.6 MPU Region Base Address Register Alias 1 Name: MPU_RBAR_A1 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region. The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 253 12.11.2.7 MPU Region Attribute and Size Register Alias 1 Name: MPU_RASR_A1 Access: Read/Write 31 – 23 30 – 29 – 28 XN 27 – 26 25 AP 24 22 21 20 TEX 19 18 S 17 C 16 B 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE – 15 SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-38. • TEX, C, B: Memory Access Attributes See Table 12-36. • S: Shareable See Table 12-36. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. 254 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 255 12.11.2.8 MPU Region Base Address Register Alias 2 Name: MPU_RBAR_A2 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region. The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. 256 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11.2.9 MPU Region Attribute and Size Register Alias 2 Name: MPU_RASR_A2 Access: Read/Write 31 – 30 – 29 – 28 XN 27 – 26 25 AP 24 23 – 22 – 21 20 TEX 19 18 S 17 C 16 B 15 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-38. • TEX, C, B: Memory Access Attributes See Table 12-36. • S: Shareable See Table 12-36. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 257 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes” . 258 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 12.11.2.10 MPU Region Base Address Register Alias 3 Name: MPU_RBAR_A3 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 ADDR 5 4 VALID REGION The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the MPU_RNR. Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR. • ADDR: Region Base Address Software must ensure that the value written to the ADDR field aligns with the size of the selected region. The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for example, at 0x00010000 or 0x00020000. • VALID: MPU Region Number Valid Write: 0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores the value of the REGION field. 1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the region specified in the REGION field. Always reads as zero. • REGION: MPU Region For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 259 12.11.2.11 MPU Region Attribute and Size Register Alias 3 Name: MPU_RASR_A3 Access: Read/Write 31 – 30 – 29 – 28 XN 27 – 26 25 AP 24 23 – 22 – 21 20 TEX 19 18 S 17 C 16 B 15 14 13 12 11 10 9 8 3 SIZE 2 1 0 ENABLE SRD 7 – 6 – 5 4 The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. MPU_RASR is accessible using word or halfword accesses: • The most significant halfword holds the region attributes. • The least significant halfword holds the region size, and the region and subregion enable bits. • XN: Instruction Access Disable 0: Instruction fetches enabled. 1: Instruction fetches disabled. • AP: Access Permission See Table 12-38. • TEX, C, B: Memory Access Attributes See Table 12-36. • S: Shareable See Table 12-36. • SRD: Subregion Disable For each bit in this field: 0: Corresponding subregion is enabled. 1: Corresponding subregion is disabled. See “Subregions” for more information. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field as 0x00. 260 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • SIZE: Size of the MPU Protection Region The minimum permitted value is 3 (b00010). The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values, with the corresponding region size and value of N in the MPU_RBAR. SIZE Value Region Size Value of N (1) Note b00100 (4) 32 B 5 Minimum permitted size b01001 (9) 1 KB 10 – b10011 (19) 1 MB 20 – b11101 (29) 1 GB 30 – b11111 (31) 4 GB b01100 Maximum possible size Note: 1. In the MPU_RBAR; see “MPU Region Base Address Register” • ENABLE: Region Enable Note: For information about access permission, see “MPU Access Permission Attributes” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 261 12.12 Glossary This glossary describes some of the terms used in technical documents from ARM. Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid. An abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction or data memory. Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are divisible by four and two respectively. Banked register Base register A register that has multiple physical copies, where the state of the processor determines which copy is used. The Stack Pointer, SP (R13) is a banked register. In instruction descriptions, a register specified by a load or store instruction that is used to hold the base value for the instruction’s address calculation. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the address that is sent to memory. See also “Index register” . Big-endian (BE) Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory. See also “Byte-invariant” , “Endianness” , “Little-endian (LE)” . Big-endian memory Memory in which: a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the most significant byte within the halfword at that address. See also “Little-endian memory” . Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested. 262 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned. Cache Condition field A block of on-chip or off-chip fast access memory locations, situated between the processor and main memory, used for storing and retrieving copies of often used instructions, data, or instructions and data. This is done to greatly increase the average speed of memory accesses and so improve processor performance. A four-bit field in an instruction that specifies a condition under which the instruction can execute. Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing. Context The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions. Coprocessor A processor that supplements the main processor. Cortex-M4 does not support any coprocessors. Debugger A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging. Direct Memory Access (DMA) An operation that accesses main memory directly, without the processor performing any accesses to the data concerned. Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated. Doubleword-aligned A data item having a memory address that is divisible by eight. Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian (LE)” and “Big-endian (BE)” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 263 Exception An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception. Faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction. Exception service routine See “Interrupt handler” . Exception vector See “Interrupt vector” . Flat address mapping A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address. Halfword A 16-bit data item. Illegal instruction An instruction that is architecturally Undefined. Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual implementations. Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility. Index register In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction. See also “Base register” . Instruction cycle count The number of cycles that an instruction occupies the Execute stage of the pipeline. Interrupt handler A program that control of the processor is passed to when an interrupt occurs. Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler. 264 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Big-endian (BE)” , “Byte-invariant” , “Endianness” . Little-endian memory Memory in which: a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address. See also “Big-endian memory” . Load/store architecture A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. Memory Protection Unit (MPU) Hardware that controls access permissions to blocks of memory. An MPU does not perform any address translation. Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed. Preserved Preserved by writing the same value back that has been previously read from the same field on the same processor. Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP. Region A partition of memory space. Reserved A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as 0. Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts. Thumb instruction One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfword-aligned. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 265 Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Undefined Indicates an instruction that generates an Undefined instruction exception. Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system. Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if debugging features of a processor. WA See “Write-allocate (WA)” . WB See “Write-back (WB)” . Word A 32-bit data item. Write Writes are defined as operations that have the semantics of a store. Writes include the Thumb instructions STM, STR, STRH, STRB, and PUSH. Write-allocate (WA) In a write-allocate cache, a cache miss on storing data causes a cache line to be allocated into the cache. Write-back (WB) In a write-back cache, data is only written to main memory when it is forced out of the cache on line replacement following a cache miss. Otherwise, writes by the processor only update the cache. This is also known as copyback. Write buffer A block of high-speed memory, arranged as a FIFO buffer, between the data cache and main memory, whose purpose is to optimize stores to main memory. Write-through (WT) 266 In a write-through cache, data is written to main memory at the same time as the cache is updated. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 13. Debug and Test Features 13.1 Description The SAM4 series microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. 13.2 Embedded Characteristics  Debug access to all memory and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset  Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access  Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches  Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling  Instrumentation Trace Macrocell (ITM) for support of printf style debugging  IEEE1149.1 JTAG Boundary scan on all digital pins Figure 13-1. Debug and Test Block Diagram TMS TCK/SWCLK TDI Boundary TAP JTAGSEL SWJ-DP TDO/TRACESWO Reset and Test POR TST SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 267 13.3 Application Examples 13.3.1 Debug Environment Figure 13-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers. Figure 13-2. Application Debug Environment Example Host Debugger PC SWJ-DP Emulator/Probe SWJ-DP Connector SAM4 SAM4-based Application Board 13.3.2 Test Environment Figure 13-3 shows a test environment example (JTAG Boundary scan). Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. 268 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Probe JTAG Connector Chip n SAM4 Chip 2 Chip 1 SAM4-based Application Board In Test 13.4 Debug and Test Pin Description Table 13-1. Debug and Test Signal List Signal Name Function Type Active Level Input/Output Low Reset/Test NRST Microcontroller Reset TST Test Select Input SWD/JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input TDI Test Data In Input TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input JTAGSEL JTAG Selection Input Output High SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 269 13.5 Functional Description 13.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during powerup, the device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates a permanent pull-down resistor of about 15 kW,so that it can be left unconnected for normal operation. Note that when setting the TST pin to low or high level at power up, it must remain in the same state during the duration of the whole operation. 13.5.2 Debug Architecture Figure 13-4 shows the Debug Architecture used in the SAM4. The Cortex-M4 embeds five functional units for debug:  SWJ-DP (Serial Wire/JTAG Debug Port)  FPB (Flash Patch Breakpoint)  DWT (Data Watchpoint and Trace)  ITM (Instrumentation Trace Macrocell)  TPIU (Trace Port Interface Unit) The debug architecture information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes and debugging tool vendors for Cortex-M4 based microcontrollers. For further details on SWJ-DP see the CortexM4 technical reference manual. Figure 13-4. Debug Architecture DWT 4 watchpoints FPB SWJ-DP PC sampler 6 breakpoints data address sampler SWD/JTAG data sampler ITM software trace 32 channels interrupt trace SWO trace TPIU time stamping CPU statistics 13.5.3 Serial Wire/JTAG Debug Port (SWJ-DP) The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight debug port. It combines Serial Wire Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP), 5 pins. By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and enables SW-DP. 270 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. Table 13-2. SWJ-DP Pin List Pin Name JTAG Port Serial Wire Debug Port TMS/SWDIO TMS SWDIO TCK/SWCLK TCK SWCLK TDI TDI – TDO/TRACESWO TDO TRACESWO (optional: trace) SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed. 13.5.3.1 SW-DP and JTAG-DP Selection Mechanism Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by default after reset.  Switch from JTAG-DP to SW-DP. The sequence is: ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 ̶ Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first) ̶  Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 Switch from SWD to JTAG. The sequence is: ̶ ̶ ̶ Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first) Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1 13.5.4 FPB (Flash Patch Breakpoint) The FPB:  Implements hardware breakpoints  Patches code and data from code space to system space. The FPB unit contains:  Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.  Six instruction comparators for matching against instruction fetches from Code space and remapping to a corresponding area in System space.  Alternatively, comparators can also be configured to generate a Breakpoint instruction to the processor core on a match. 13.5.5 DWT (Data Watchpoint and Trace) The DWT contains four comparators which can be configured to generate the following:  PC sampling packets at set intervals  PC or Data watchpoint packets  Watchpoint event to halt core SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 271 The DWT contains counters for the items that follow:  Clock cycle (CYCCNT)  Folded instructions  Load Store Unit (LSU) operations  Sleep Cycles  CPI (all instruction cycles except for the first cycle)  Interrupt overhead 13.5.6 ITM (Instrumentation Trace Macrocell) The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets which can be generated by three different sources with several priority levels:  Software trace: Software can write directly to ITM stimulus registers. This can be done thanks to the “printf” function. For more information, refer to Section 13.5.6.1 “How to Configure the ITM”.  Hardware trace: The ITM emits packets generated by the DWT.  Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. 13.5.6.1 How to Configure the ITM The following example describes how to output trace data in asynchronous trace mode.  Configure the TPIU for asynchronous trace mode (refer to Section 13.5.6.3 “5.4.3. How to Configure the TPIU”)  Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register (Address: 0xE0000FB0)  Write 0x00010015 into the Trace Control Register:  ̶ Enable ITM ̶ Enable Synchronization packets ̶ Enable SWO behavior ̶ Fix the ATB ID to 1 Write 0x1 into the Trace Enable Register: ̶  Enable the Stimulus port 0 Write 0x1 into the Trace Privilege Register: ̶  Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the corresponding stimulus port being accessible in user mode.) Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit) The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM). The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core. 13.5.6.2 Asynchronous Mode The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous trace mode is only available when the Serial Wire Debug mode is selected since TDO signal is used in JTAG debug mode. Two encoding formats are available for the single pin output: 272  Manchester encoded stream. This is the reset value.  NRZ_based UART byte structure SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 13.5.6.3 5.4.3. How to Configure the TPIU This example only concerns the asynchronous trace mode.  Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace and debug blocks.  Write 0x2 into the Selected Pin Protocol Register ̶ Select the Serial Wire Output – NRZ  Write 0x100 into the Formatter and Flush Control Register  Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the asynchronous output (this can be done automatically by the debugging tool). 13.5.7 IEEE® 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up, and must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS functions are implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided on Atmel’s web site to set up the test. 13.5.7.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins and associated control signals. Each SAM4 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. For more information, please refer to BDSL files available for the SAM4 Series. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 273 13.5.8 ID Code Register Access: Read-only 31 30 29 28 27 21 20 19 PART NUMBER VERSION 23 22 15 14 13 PART NUMBER 7 6 5 12 11 4 3 MANUFACTURER IDENTITY 26 25 PART NUMBER 24 18 16 17 10 9 MANUFACTURER IDENTITY 2 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Chip Name Chip ID SAM4S 0x05B32 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. 274 Chip Name JTAG ID Code SAM4S 0x05B3203F SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 8 0 1 14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.2 Embedded Characteristics  Management of All System Resets, Including ̶ Processor Reset ̶ Processor Peripheral Set Reset  Based on Embedded Power-on Cell  Reset Source Status  14.3 External Devices through the NRST Pin ̶ ̶ Status of the Last Reset ̶ Either Software Reset, User Reset, Watchdog Reset External Reset Signal Shaping Block Diagram Figure 14-1. Reset Controller Block Diagram Reset Controller core_backup_reset rstc_irq vddcore_nreset user_reset NRST nrst_out NRST Manager Reset State Manager proc_nreset periph_nreset exter_nreset WDRPROC wd_fault SLCK SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 275 14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made up of an NRST manager and a reset state manager. It runs at slow clock and generates the following reset signals:  proc_nreset: processor reset line (also resets the Watchdog Timer)  periph_nreset: affects the whole set of embedded peripherals  nrst_out: drives the NRST pin These reset signals are asserted by the Reset Controller, either on events generated by peripherals, events on NRST pin, or on software action. The reset state manager controls the generation of reset signals and provides a signal to the NRST manager when an assertion of the NRST pin is required. The NRST manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The Reset Controller Mode Register (RSTC_MR), used to configure the Reset Controller, is powered with VDDIO, so that its configuration is saved as long as VDDIO is on. 14.4.2 NRST Manager The NRST manager samples the NRST input pin and drives this pin low when required by the reset state manager. Figure 14-2 shows the block diagram of the NRST manager. Figure 14-2. NRST Manager RSTC_MR URSTIEN RSTC_SR URSTS NRSTL rstc_irq RSTC_MR URSTEN Other interrupt sources user_reset NRST RSTC_MR ERSTL nrst_out 14.4.2.1 External Reset Timer exter_nreset NRST Signal or Interrupt The NRST manager samples the NRST pin at slow clock speed. When the line is detected low, a User Reset is reported to the reset state manager. However, the NRST manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing a 0 to the URSTEN bit in the RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in the Reset Controller Status Register (RSTC_SR). As soon as the NRST pin is asserted, bit URSTS in the RSTC_SR is set. This bit is cleared only when the RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, set the URSTIEN bit in the RSTC_MR. 276 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 14.4.2.2 NRST External Reset Control The reset state manager asserts the signal exter_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST manager for a time programmed by field ERSTL in the RSTC_MR. This assertion duration, named External Reset Length, lasts 2(ERSTL+1) slow clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. RSTC_MR is backed up, making it possible to use the ERSTL field to shape the system power-up reset for devices requiring a longer startup time than that of the slow clock oscillator. 14.4.3 Reset States The reset state manager handles the different reset sources and generates the internal reset signals. It reports the reset status in field RSTTYP of the Status Register (RSTC_SR). The update of RSTC_SR.RSTTYP is performed when the processor reset is released. 14.4.3.1 General Reset A general reset occurs when a VDDIO power-on-reset is detected, a brownout or a voltage regulation loss is detected by the Supply Controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs. All the reset signals are released and field RSTC_SR.RSTTYP reports a general reset. As the RSTC_MR is reset, the NRST line rises two cycles after the vddcore_nreset, as ERSTL defaults at value 0x0. Figure 14-3 shows how the general reset affects the reset signals. Figure 14-3. General Reset State SLCK Any Freq. MCK vddio_nreset Processor Startup = 2 cycles proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) External Reset Length = 2 cycles 14.4.3.2 Backup Reset A backup reset occurs when the chip exits from Backup mode. While exiting Backup mode, the vddcore_nreset signal is asserted by the Supply Controller. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 277 Field RSTC_SR.RSTTYP is updated to report a backup reset. 14.4.3.3 Watchdog Reset The watchdog reset is entered when a watchdog fault occurs. This reset lasts three slow clock cycles. When in watchdog reset, assertion of the reset signals depends on the WDRPROC bit in the WDT_MR:  If WDRPROC = 0, the processor reset and the peripheral reset are asserted. The NRST line is also asserted, depending on how field RSTC_MR.ERSTL is programmed. However, the resulting low level on NRST does not result in a user reset state.  If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN in the WDT_MR is set, the Watchdog Timer is always reset after a watchdog reset, and the Watchdog is enabled by default and with a period set to a maximum. When bit WDT_MR.WDRSTEN is reset, the watchdog fault has no impact on the Reset Controller. Figure 14-4. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 14.4.3.4 Software Reset The Reset Controller offers commands to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: 278  RSTC_CR.PROCRST: Writing a 1 to PROCRST resets the processor and the watchdog timer.  RSTC_CR.PERRST: Writing a 1 to PERRST resets all the embedded peripherals including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously).  RSTC_CR.EXTRST: Writing a 1 to EXTRST asserts low the NRST pin during a time defined by the field RSTC_MR.ERSTL. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts three slow clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset has ended, i.e., synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the configuration of field RSTC_MR.ERSTL. However, the resulting falling edge on NRST does not lead to a user reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in field RSTC_SR.RSTTYP. Other software resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the RSTC_SR. SRCMP is cleared at the end of the software reset. No other software reset can be performed while the SRCMP bit is set, and writing any value in the RSTC_CR has no effect. Figure 14-5. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. Processor Startup 1 cycle = 2 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 14.4.3.5 User Reset The user reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The user reset is entered as soon as a low level is detected on NRST. The processor reset and the peripheral reset are asserted. The user reset ends when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, field RSTC_SR.RSTTYP is loaded with the value 0x4, indicating a user reset. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 279 The NRST manager guarantees that the NRST line is asserted for External Reset Length slow clock cycles, as programmed in field RSTC_MR.ERSTL. However, if NRST does not rise after External Reset Length because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 14-6. User Reset State SLCK Any Freq. MCK NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 14.4.4 Reset State Priorities The reset state manager manages the priorities among the different reset sources. The resets are listed in order of priority as follows: 1. General reset 2. Backup reset 3. Watchdog reset 4. Software reset 5. User reset Particular cases are listed below:  When in user reset: ̶ ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.   280 A software reset is impossible, since the processor reset is being activated. When in software reset: ̶ A watchdog event has priority over the current state. ̶ The NRST has no effect. When in watchdog reset: ̶ The processor reset is active and so a software reset cannot be programmed. ̶ A user reset cannot be entered. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 14.5 Reset Controller (RSTC) User Interface Table 14-1. Offset Note: Register Mapping Register Name Access Reset 0x00 Control Register RSTC_CR Write-only – 0x04 Status Register RSTC_SR Read-only 0x0000_0000(1) 0x08 Mode Register RSTC_MR Read/Write 0x0000 0001 1. This value assumes that a general reset has been performed, subject to change if other types of reset are generated. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 281 14.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0x400E1400 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect 1: If KEY is correct, resets the processor • PERRST: Peripheral Reset 0: No effect 1: If KEY is correct, resets the peripherals • EXTRST: External Reset 0: No effect 1: If KEY is correct, asserts the NRST pin • KEY: System Reset Key 282 Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 14.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0x400E1404 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the MCK rising edge. If the user reset is disabled (URSTEN = 0 in RSTC_MR) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit triggers an interrupt. Reading the RSTC_SR resets the URSTS bit and clears the interrupt. 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type This field reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. Value Name Description 0 GENERAL_RST First power-up reset 1 BACKUP_RST Return from Backup Mode 2 WDT_RST Watchdog fault occurred 3 SOFT_RST Processor reset required by the software 4 USER_RST NRST pin detected low 5 – Reserved 6 – Reserved 7 – Reserved • NRSTL: NRST Pin Level This bit registers the NRST pin level sampled on each Master Clock (MCK) rising edge. • SRCMP: Software Reset Command in Progress When set, this bit indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. 0: No software command is being performed by the Reset Controller. The Reset Controller is ready for a software command. 1: A software reset command is being performed by the Reset Controller. The Reset Controller is busy. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 283 14.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0x400E1408 Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 – 4 URSTIEN 3 – ERSTL 2 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • URSTEN: User Reset Enable 0: The detection of a low level on the NRST pin does not generate a user reset. 1: The detection of a low level on the NRST pin triggers a user reset. • URSTIEN: User Reset Interrupt Enable 0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) slow clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. Note that synchronization cycles must also be considered when calculating the actual reset length as previously described. • KEY: Write Access Password 284 Value Name 0xA5 PASSWD SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Description Writing any other value in this field aborts the write operation. Always reads as 0. 15. Real-time Timer (RTT) 15.1 Description The Real-time Timer (RTT) is built around a 32-bit counter used to count roll-over events of the programmable 16bit prescaler driven from the 32-kHz slow clock source. It generates a periodic interrupt and/or triggers an alarm on a programmed value. The RTT can also be configured to be driven by the 1Hz RTC signal, thus taking advantage of a calibrated 1Hz clock. The slow clock source can be fully disabled to reduce power consumption when only an elapsed seconds count is required. 15.2 15.3 Embedded Characteristics  32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1Hz clock  16-bit Configurable Prescaler  Interrupt on Alarm or Counter Increment Block Diagram Figure 15-1. RTT_MR RTTDIS Real-time Timer RTT_MR RTT_MR RTTRST RTPRES RTT_MR reload 16-bit Prescaler SLCK RTTINCIEN set 0 RTT_MR RTC 1Hz RTTRST RTT_MR RTC1HZ 1 RTTINC RTT_SR 1 reset 0 rtt_int 0 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set rtt_alarm = RTT_AR ALMV SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 285 15.4 Functional Description The programmable 16-bit prescaler value can be configured through the RTPRES field in the “Real-time Timer Mode Register” (RTT_MR). Configuring the RTPRES field value to 0x8000 (default value) corresponds to feeding the real-time counter with a 1Hz signal (if the slow clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. Bit RTTINC in the “Real-time Timer Status Register” (RTT_SR) is set each time there is a prescaler roll-over (see Figure 15-2) The real-time 32-bit counter can also be supplied by the 1Hz RTC clock. This mode is interesting when the RTC 1Hz is calibrated (CORRECTION field ≠ 0 in RTC_MR) in order to guaranty the synchronism between RTC and RTT counters. Setting the RTC1HZ bit in the RTT_MR drives the 32-bit RTT counter from the 1Hz RTC clock. In this mode, the RTPRES field has no effect on the 32-bit counter. The prescaler roll-over generates an increment of the real-time timer counter if RTC1HZ = 0. Otherwise, if RTC1HZ = 1, the real-time timer counter is incremented every second. The RTTINC bit is set independently from the 32-bit counter increment. The real-time timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3 in RTT_MR. Programming RTPRES to 1 or 2 is forbidden. If the RTT is configured to trigger an interrupt, the interrupt occurs two slow clock cycles after reading the RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the RTT_SR is cleared. The CRTV field can be read at any time in the “Real-time Timer Value Register” (RTT_VR). As this value can be updated asynchronously with the Master Clock, the CRTV field must be read twice at the same value to read a correct value. The current value of the counter is compared with the value written in the “Real-time Timer Alarm Register” (RTT_AR). If the counter value matches the alarm, the ALMS bit in the RTT_SR is set. The RTT_AR is set to its maximum value (0xFFFF_FFFF) after a reset. The ALMS flag is always a source of the RTT alarm signal that may be used to exit the system from low power modes (see Figure 15-1). The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value in the RTT_AR. The RTTINC bit can be used to start a periodic interrupt, the period being one second when the RTPRES field value = 0x8000 and the slow clock = 32.768 kHz. The RTTINCIEN bit must be cleared prior to writing a new RTPRES value in the RTT_MR. Reading the RTT_SR automatically clears the RTTINC and ALMS bits. Writing the RTTRST bit in the RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this module. This can be achieved by setting the RTTDIS bit in the RTT_MR. 286 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 15-2. RTT Counting SLCK RTPRES - 1 Prescaler 0 CRTV 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface APB cycle read RTT_SR APB cycle SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 287 15.5 Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read/Write 0x0000_8000 0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 288 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 15.5.1 Real-time Timer Mode Register Name: RTT_MR Address: 0x400E1430 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 RTC1HZ 23 – 22 – 21 – 20 RTTDIS 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 * SLCK periods. RTPRES = 1 or 2: forbidden. RTPRES ≠ 0,1 or 2: The prescaler period is equal to RTPRES * SLCK periods. Note: The RTTINCIEN bit must be cleared prior to writing a new RTPRES value. • ALMIEN: Alarm Interrupt Enable 0: The bit ALMS in RTT_SR has no effect on interrupt. 1: The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0: The bit RTTINC in RTT_SR has no effect on interrupt. 1: The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 0: No effect. 1: Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. • RTTDIS: Real-time Timer Disable 0: The real-time timer is enabled. 1: The real-time timer is disabled (no dynamic power consumption). Note: RTTDIS is write only. • RTC1HZ: Real-Time Clock 1Hz Clock Selection 0: The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events. 1: The RTT 32-bit counter is driven by the 1Hz RTC clock. Note: RTC1HZ is write only. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 289 15.5.2 Real-time Timer Alarm Register Name: RTT_AR Address: 0x400E1434 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value When the CRTV value in RTT_VR equals the ALMV field, the ALMS flag is set in RTT_SR. As soon as the ALMS flag rises, the CRTV value equals ALMV+1 (refer to Figure 15-2). Note: 290 The alarm interrupt must be disabled (ALMIEN must be cleared in RTT_MR) when writing a new ALMV value. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 15.5.3 Real-time Timer Value Register Name: RTT_VR Address: 0x400E1438 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. Note: As CRTV can be updated asynchronously, it must be read twice at the same value. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 291 15.5.4 Real-time Timer Status Register Name: RTT_SR Address: 0x400E143C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status (cleared on read) 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Prescaler Roll-over Status (cleared on read) 0: No prescaler roll-over occurred since the last read of the RTT_SR. 1: Prescaler roll-over occurred since the last read of the RTT_SR. 292 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16. Real-time Clock (RTC) 16.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. For optimal functionality, the RTC requires an accurate external 32.768 kHz clock, which can be provided by a crystal oscillator. It combines a complete time-of-day clock with alarm and a Gregorian or Persian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. A clock divider calibration circuitry can be used to compensate for crystal oscillator frequency inaccuracy. An RTC output can be programmed to generate several waveforms, including a prescaled clock derived from 32.768 kHz. 16.2 Embedded Characteristics  Ultra Low Power Consumption  Full Asynchronous Design  Gregorian Calendar up to 2099 or Persian Calendar  Programmable Periodic Interrupt  Safety/security features: ̶ Valid Time and Date Programmation Check ̶ On-The-Fly Time and Date Validity Check  Crystal Oscillator Clock Calibration  Waveform Generation  Register Write Protection SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 293 16.3 Block Diagram Figure 16-1. RTC Block Diagram Slow Clock: SLCK 32768 Divider Time Wave Generator Date RTCOUT0 RTCOUT1 Clock Calibration System Bus 16.4 User Interface Entry Control Alarm Interrupt Control RTC Interrupt Product Dependencies 16.4.1 Power Management The Real-time Clock is continuously clocked at 32.768 kHz. The Power Management Controller has no effect on RTC behavior. 16.4.2 Interrupt RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. Table 16-1. 16.5 Peripheral IDs Instance ID RTC 2 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds reported in RTC Time Register (RTC_TIMR) and RTC Calendar Register (RTC_CALR). The valid year range is up to 2099 in Gregorian mode (or 1300 to 1499 in Persian mode). The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years except 1900). This is correct up to the year 2099. The RTC can generate configurable waveforms on RTCOUT0/1 outputs. 16.5.1 Reference Clock The reference clock is the Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 294 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16.5.2 Timing The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at oneminute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 16.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition:  If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second.  If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC, MIN, HOUR fields. Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_TIMALR or RTC_CALALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN, DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREn, DATEEN, MTHEN fields. 16.5.4 Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is followed for the alarm. The following checks are performed: 1. Century (check if it is in range 19–20 or 13–14 in Persian mode) 2. Year (BCD entry check) 3. Date (check range 01–31) 4. Month (check if it is in BCD range 01–12, check validity regarding “date”) 5. Day (check range 1–7) 6. Hour (BCD checks: in 24-hour mode, check range 00–23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01–12) 7. Minute (check BCD and range 00–59) 8. Second (check BCD and range 00–59) Note: If the 12-hour mode is selected by means of the RTC Mode Register (RTC_MR), a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIMR) to determine the range to be checked. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 295 16.5.5 RTC Internal Free Running Counter Error Checking To improve the reliability and security of the RTC, a permanent check is performed on the internal free running counters to report non-BCD or invalid date/time values. An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The flag can be cleared by setting the TDERRCLR bit in the Status Clear Command Register (RTC_SCCR). Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the TDERR flag. The clearing of the source of such error can be done either by reprogramming a correct value on RTC_CALR and/or RTC_TIMR. The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e., every 10 seconds for SECONDS[3:0] field in RTC_TIMR). In this case the TDERR is held high until a clear command is asserted by TDERRCLR bit in RTC_SCCR. 16.5.6 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register (RTC_CR). Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). The ACKUPD bit is automatically set within a second after setting the UPDTIM and/or UPDCAL bit (meaning one second is the maximum duration of the polling or wait for interrupt period). Once ACKUPD is set, it is mandatory to clear this flag by writing the corresponding bit in the RTC_SCCR, after which the user can write to the Time Register, the Calendar Register, or both. Once the update is finished, the user must clear UPDTIM and/or UPDCAL in the RTC_CR. When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these bits again. This is done by waiting for the SEC flag in the RTC_SR before setting UPDTIM/UPDCAL bit. After clearing UPDTIM/UPDCAL, the SEC flag must also be cleared. 296 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 16-2. Update Sequence Begin Prepare Time or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD =1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 297 16.5.7 RTC Accurate Clock Calibration The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The RTC is equipped with circuitry able to correct slow clock crystal drift. To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at room temperature (20–25°C). The typical clock drift range at room temperature is ±20 ppm. In the device operating temperature range, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200 ppm. The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm. The calibration circuitry is fully digital. Thus, the configured correction is independent of temperature, voltage, process, etc., and no additional measurement is required to check that the correction is effective. If the correction value configured in the calibration circuitry results from an accurate crystal frequency measure, the remaining accuracy is bounded by the values listed below:  Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 20 ppm, and from 30 ppm to 90 ppm  Below 2 ppm, for an initial crystal drift between 20 ppm up to 30 ppm, and from 90 ppm to 130 ppm  Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm The calibration circuitry does not modify the 32.768 kHz crystal oscillator clock frequency but it acts by slightly modifying the 1 Hz clock period from time to time. When the period is modified, depending on the sign of the correction, the 1 Hz clock period increases or reduces by around 4 ms. Depending on the CORRECTION, NEGPPM and HIGHPPM values configured in RTC_MR, the period interval between two correction events differs. Figure 16-3. Calibration circuitry RTC Divider by 32768 32.768 kHz Oscillator Add 32.768 kHz Integrator Comparator Other Logic 298 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1Hz Time/Calendar Suppress CORRECTION, HIGHPPM NEGPPM Figure 16-4. Calibration circuitry waveforms Monotonic 1Hz Counter value Nominal 32.768 kHz 32.768 kHz +50ppm Phase adjustment (~4ms) 32.768 kHz -50ppm -25ppm Crystal frequency remains unadjusted -50ppm Internal 1Hz clock is adjusted Time -50ppm correction period -25ppm correction period User configurable period (integer multiple of 1s or 20s) Time NEGATIVE CORRECTION Crystal clock Internally divided clock (256Hz) Clock pulse periodically suppressed when correction period elapses Internally divided clock (128Hz) 1.000 second 128 Hz clock edge delayed by 3,906 ms when correction period elapses POSITIVE CORRECTION 1.003906 second Internally divided clock (256Hz) Internally divided clock (128Hz) Clock edge periodically added when correction period elapses Internally divided clock (64Hz) 128 Hz clock edge delayed by 3,906 ms when correction period elapses 0.996094 second 1.000 second The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20–25 °C) can be compensated if a reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can be set up during SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 299 the final product manufacturing by means of measurement equipment embedding such a reference clock. The correction of value must be programmed into the (RTC_MR), and this value is kept as long as the circuitry is powered (backup area). Removing the backup power supply cancels this calibration. This room temperature calibration can be further processed by means of the networking capability of the target application. To ease the comparison of the inherent crystal accuracy with the reference clock/signal during manufacturing, an internal prescaled 32.768 kHz clock derivative signal can be assigned to drive RTC output. To accommodate the measure, several clock frequencies can be selected among 1 Hz, 32 Hz, 64 Hz, 512 Hz. The clock calibration correction drives the internal RTC counters but can also be observed in the RTC output when one of the following three frequencies 1 Hz, 32 Hz or 64 Hz is configured. The correction is not visible in the RTC output if 512 Hz frequency is configured. In any event, this adjustment does not take into account the temperature variation. The frequency drift (up to -200 ppm) due to temperature variation can be compensated using a reference time if the application can access such a reference. If a reference time cannot be used, a temperature sensor can be placed close to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once obtained, the temperature may be converted using a lookup table (describing the accuracy/temperature curve of the crystal oscillator used) and RTC_MR configured accordingly. The calibration can be performed on-the-fly. This adjustment method is not based on a measurement of the crystal frequency/drift and therefore can be improved by means of the networking capability of the target application. If no crystal frequency adjustment has been done during manufacturing, it is still possible to do it. In the case where a reference time of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of the application crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and programming the HIGHPPM and CORRECTION fields on RTC_MR according to the difference measured between the reference time and those of RTC_TIMR. 16.5.8 Waveform Generation Waveforms can be generated by the RTC in order to take advantage of the RTC inherent prescalers while the RTC is the only powered circuitry (low power mode of operation, backup mode) or in any active modes. Going into backup or low power operating modes does not affect the waveform generation outputs. The RTC outputs (RTCOUT0 and RTCOUT1) have a source driver selected among seven possibilities. The first selection choice sticks the associated output at 0 (This is the reset value and it can be used at any time to disable the waveform generation). Selection choices 1 to 4 respectively select 1 Hz, 32 Hz, 64 Hz and 512 Hz. 32 Hz or 64 Hz can drive, for example, a TN LCD backplane signal while 1 Hz can be used to drive a blinking character like “:” for basic time display (hour, minute) on TN LCDs. Selection choice 5 provides a toggling signal when the RTC alarm is reached. Selection choice 6 provides a copy of the alarm flag, so the associated output is set high (logical 1) when an alarm occurs and immediately cleared when software clears the alarm interrupt source. Selection choice 7 provides a 1 Hz periodic high pulse of 15 µs duration that can be used to drive external devices for power consumption reduction or any other purpose. PIO lines associated to RTC outputs are automatically selecting these waveforms as soon as RTC_MR corresponding fields OUT0 and OUT1 differ from 0. 300 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 16-5. Waveform Generation ‘0’ 0 ‘0’ 0 1 Hz 1 1 Hz 1 32 Hz 2 32 Hz 2 64 Hz 3 64 Hz 3 512 Hz 4 512 Hz 4 toggle_alarm 5 toggle_alarm 5 flag_alarm 6 flag_alarm 6 pulse 7 pulse 7 RTCOUT0 RTC_MR(OUT0) RTCOUT1 RTC_MR(OUT1) alarm match event 2 alarm match event 1 flag_alarm RTC_SCCR(ALRCLR) RTC_SCCR(ALRCLR) toggle_alarm pulse Thigh Tperiod Tperiod SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 301 16.6 Real-time Clock (RTC) User Interface Table 16-2. Offset Register Mapping Register Name Access Reset 0x00 Control Register RTC_CR Read/Write 0x0 0x04 Mode Register RTC_MR Read/Write 0x0 0x08 Time Register RTC_TIMR Read/Write 0x0 0x0C Calendar Register RTC_CALR Read/Write 0x01A11020 0x10 Time Alarm Register RTC_TIMALR Read/Write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read/Write 0x01010000 0x18 Status Register RTC_SR Read-only 0x0 0x1C Status Clear Command Register RTC_SCCR Write-only – 0x20 Interrupt Enable Register RTC_IER Write-only – 0x24 Interrupt Disable Register RTC_IDR Write-only – 0x28 Interrupt Mask Register RTC_IMR Read-only 0x0 0x2C Valid Entry Register RTC_VER Read-only 0x0 0x30–0xC8 Reserved – – – 0xD0 Reserved – – – 0xD4–0xF8 Reserved – – – 0xFC Reserved – – – Note: If an offset is not listed in the table it must be considered as reserved. 302 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16.6.1 RTC Control Register Name: RTC_CR Address: 0x400E1460 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • UPDTIM: Update Request Time Register 0: No effect. 1: Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. • UPDCAL: Update Request Calendar Register 0: No effect. 1: Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the RTC_SR. • TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR depends on the value of TIMEVSEL. Value Name Description 0 MINUTE Minute change 1 HOUR Hour change 2 MIDNIGHT Every day at midnight 3 NOON Every day at noon SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 303 • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) 304 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16.6.2 RTC Mode Register Name: RTC_MR Address: 0x400E1464 Access: Read/Write 31 30 – – 23 22 – 15 29 28 27 TPERIOD 21 20 19 OUT1 14 13 26 25 – 18 17 – 12 HIGHPPM 11 24 THIGH 16 OUT0 10 9 8 CORRECTION 7 6 5 4 3 2 1 0 – – – NEGPPM – – PERSIAN HRMOD This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). • HRMOD: 12-/24-hour Mode 0: 24-hour mode is selected. 1: 12-hour mode is selected. • PERSIAN: PERSIAN Calendar 0: Gregorian calendar. 1: Persian calendar. • NEGPPM: NEGative PPM Correction 0: Positive correction (the divider will be slightly higher than 32768). 1: Negative correction (the divider will be slightly lower than 32768). Refer to CORRECTION and HIGHPPM field descriptions. Note: NEGPPM must be cleared to correct a crystal slower than 32.768 kHz. • CORRECTION: Slow Clock Correction 0: No correction 1–127: The slow clock will be corrected according to the formula given in HIGHPPM description. • HIGHPPM: HIGH PPM Correction 0: Lower range ppm correction with accurate correction. 1: Higher range ppm correction with accurate correction. If the absolute value of the correction to be applied is lower than 30 ppm, it is recommended to clear HIGHPPM. HIGHPPM set to 1 is recommended for 30 ppm correction and above. Formula: If HIGHPPM = 0, then the clock frequency correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less than 1 ppm for a range correction from 1.5 ppm up to 30 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 305 3906 CORRECTION = ----------------------- – 1 20 × ppm The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field. If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less than 1 ppm for a range correction from 30.5 ppm up to 90 ppm. The correction field must be programmed according to the required correction in ppm; the formula is as follows: 3906 CORRECTION = ------------ – 1 ppm The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field. If NEGPPM is set to 1, the ppm correction is negative (used to correct crystals that are faster than the nominal 32.768 kHz). • OUT0: RTCOUT0 OutputSource Selection Value Name Description 0 NO_WAVE No waveform, stuck at ‘0’ 1 FREQ1HZ 1 Hz square wave 2 FREQ32HZ 32 Hz square wave 3 FREQ64HZ 64 Hz square wave 4 FREQ512HZ 512 Hz square wave 5 ALARM_TOGGLE Output toggles when alarm flag rises 6 ALARM_FLAG Output is a copy of the alarm flag 7 PROG_PULSE Duty cycle programmable pulse • OUT1: RTCOUT1 Output Source Selection Value Name Description 0 NO_WAVE No waveform, stuck at ‘0’ 1 FREQ1HZ 1 Hz square wave 2 FREQ32HZ 32 Hz square wave 3 FREQ64HZ 64 Hz square wave 4 FREQ512HZ 512 Hz square wave 5 ALARM_TOGGLE Output toggles when alarm flag rises 6 ALARM_FLAG Output is a copy of the alarm flag 7 PROG_PULSE Duty cycle programmable pulse • THIGH: High Duration of the Output Pulse Value 306 Name Description 0 H_31MS 31.2 ms 1 H_16MS 15.6 ms 2 H_4MS 3.91 ms SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Value Name Description 3 H_976US 976 µs 4 H_488US 488 µs 5 H_122US 122 µs 6 H_30US 30.5 µs 7 H_15US 15.2 µs • TPERIOD: Period of the Output Pulse Value Name Description 0 P_1S 1 second 1 P_500MS 500 ms 2 P_250MS 250 ms 3 P_125MS 125 ms SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 307 16.6.3 RTC Time Register Name: RTC_TIMR Address: 0x400E1468 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0–59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set is 1–12 (BCD) in 12-hour mode or 0–23 (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0: AM. 1: PM. All non-significant bits read zero. 308 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16.6.4 RTC Calendar Register Name: RTC_CALR Address: 0x400E146C Access: Read/Write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19–20 (gregorian) or 13–14 (persian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00–99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MONTH: Current Month The range that can be set is 01–12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • DAY: Current Day in Current Week The range that can be set is 1–7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Day in Current Month The range that can be set is 01–31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 309 16.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0x400E1470 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 11 MIN 6 5 SECEN 4 3 SEC This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Note: To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then reenable it after the change has been made. This requires up to three accesses to the RTC_TIMALR. The first access clears the enable corresponding to the field to change (SECEN, MINEN, HOUREN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields. • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0: The second-matching alarm is disabled. 1: The second-matching alarm is enabled. • MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. • MINEN: Minute Alarm Enable 0: The minute-matching alarm is disabled. 1: The minute-matching alarm is enabled. • HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0: The hour-matching alarm is disabled. 1: The hour-matching alarm is enabled. 310 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0x400E1474 Access: Read/Write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 20 19 15 14 13 12 11 10 9 8 – – – – – – – – MONTH 7 6 5 4 3 2 1 0 – – – – – – – – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR). Note: To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to three accesses to the RTC_CALALR. The first access clears the enable corresponding to the field to change (DATEEN, MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE, MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields. • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0: The month-matching alarm is disabled. 1: The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0: The date-matching alarm is disabled. 1: The date-matching alarm is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 311 16.6.7 RTC Status Register Name: RTC_SR Address: 0x400E1478 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERR CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update Value Name Description 0 FREERUN Time and calendar registers cannot be updated. 1 UPDATE Time and calendar registers can be updated. • ALARM: Alarm Flag Value Name Description 0 NO_ALARMEVENT No alarm matching condition occurred. 1 ALARMEVENT An alarm matching condition has occurred. • SEC: Second Event Value Name Description 0 NO_SECEVENT No second event has occurred since the last clear. 1 SECEVENT At least one second event has occurred since the last clear. • TIMEV: Time Event Value Name Description 0 NO_TIMEVENT No time event has occurred since the last clear. 1 TIMEVENT At least one time event has occurred since the last clear. Note: The time event is selected in the TIMEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: minute change, hour change, noon, midnight (day change). • CALEV: Calendar Event Value Name Description 0 NO_CALEVENT No calendar event has occurred since the last clear. 1 CALEVENT At least one calendar event has occurred since the last clear. Note: The calendar event is selected in the CALEVSEL field in the Control Register (RTC_CR) and can be any one of the following events: week change, month change and year change. 312 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • TDERR: Time and/or Date Free Running Error Value Name Description 0 CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 1 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 313 16.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0x400E147C Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • SECCLR: Second Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). • TDERRCLR: Time and/or Date Free Running Error Clear 0: No effect. 1: Clears corresponding status flag in the Status Register (RTC_SR). 314 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0x400E1480 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERREN CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0: No effect. 1: The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0: No effect. 1: The alarm interrupt is enabled. • SECEN: Second Event Interrupt Enable 0: No effect. 1: The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable 0: No effect. 1: The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable 0: No effect. 1: The selected calendar event interrupt is enabled. • TDERREN: Time and/or Date Error Interrupt Enable 0: No effect. 1: The time and date error interrupt is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 315 16.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0x400E1484 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0: No effect. 1: The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0: No effect. 1: The alarm interrupt is disabled. • SECDIS: Second Event Interrupt Disable 0: No effect. 1: The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable 0: No effect. 1: The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable 0: No effect. 1: The selected calendar event interrupt is disabled. • TDERRDIS: Time and/or Date Error Interrupt Disable 0: No effect. 1: The time and date error interrupt is disabled. 316 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 16.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0x400E1488 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – TDERR CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0: The acknowledge for update interrupt is disabled. 1: The acknowledge for update interrupt is enabled. • ALR: Alarm Interrupt Mask 0: The alarm interrupt is disabled. 1: The alarm interrupt is enabled. • SEC: Second Event Interrupt Mask 0: The second periodic interrupt is disabled. 1: The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0: The selected time event interrupt is disabled. 1: The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0: The selected calendar event interrupt is disabled. 1: The selected calendar event interrupt is enabled. • TDERR: Time and/or Date Error Mask 0: The time and/or date error event is disabled. 1: The time and/or date error event is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 317 16.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0x400E148C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0: No invalid data has been detected in RTC_TIMR (Time Register). 1: RTC_TIMR has contained invalid data since it was last programmed. • NVCAL: Non-valid Calendar 0: No invalid data has been detected in RTC_CALR (Calendar Register). 1: RTC_CALR has contained invalid data since it was last programmed. • NVTIMALR: Non-valid Time Alarm 0: No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1: RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non-valid Calendar Alarm 0: No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1: RTC_CALALR has contained invalid data since it was last programmed. 318 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 Embedded Characteristics  12-bit Key-protected Programmable Counter  Watchdog Clock is Independent from Processor Clock  Provides Reset or Interrupt Signals to the System  Counter May Be Stopped while the Processor is in Debug State or in Idle Mode SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 319 17.3 Block Diagram Figure 17-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR WDD reload Current Value 1/128 SLCK 0, it must be checked that none of the WKUPx pins that are enabled for a wake-up (exit from Backup mode) holds an active polarity. This is checked by reading the pin status in the PIO Controller. If WKUPENx=1 and the pin WKUPx holds an active polarity, the system must not be instructed to enter Backup mode. Figure 18-5. Entering and Exiting Backup Mode with a WKUP Pin WKUPDBC > 0 WKUPTx=0 Edge detect + debounce time WKUPx Edge detect + debounce time VROFF=1 VROFF=1 System Active BACKUP Active BACKUP active runtime Active active runtime BACKUP check WKUPx status check WKUPx status 18.4.7.2 Low-power Tamper Detection and Anti-Tampering Low-power debouncer inputs (WKUP0, WKUP1) can be used for tamper detection. If the tamper sensor is biased through a resistor and constantly driven by the power supply, this leads to power consumption as long as the tamper detection switch is in its active state. To prevent power consumption when the switch is in active state, the tamper sensor circuitry must be intermittently powered, and thus a specific waveform must be applied to the sensor circuitry. The waveform is generated using RTCOUTx in all modes including Backup mode. Refer to the RTC section for waveform generation. Separate debouncers are embedded, one for WKUP0 input, one for WKUP1 input. The WKUP0 and/or WKUP1 inputs perform a system wake-up upon tamper detection. This is enabled by setting the LPDBCEN0/1 bit in the SUPC_WUMR. WKUP0 and/or WKUP1 inputs can also be used when VDDCORE is powered to detect a tamper. When the bit LPDBCENx is written to 1, WKUPx pins must not be configured to act as a debouncing source for the WKUPDBC counter (WKUPENx must be cleared in SUPC_WUIR). Low-power tamper detection or debounce requires RTC output (RTCOUTx) to be configured to generate a duty cycle programmable pulse (i.e., OUT0 = 0x7 in RTC_MR) in order to create the sampling points of both debouncers. The sampling point is the falling edge of the RTCOUTx waveform. Figure 18-6 shows an example of an application where two tamper switches are used. RTCOUTx powers the external pull-up used by the tamper sensor circuitry. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 335 Figure 18-6. Low-power Debouncer (Push-to-Make Switch, Pull-up Resistors) MCU RTCOUTx Pull-up Resistor WKUP0 Pull-up Resistor GND WKUP1 GND GND Figure 18-7. Low-power Debouncer (Push-to-Break Switch, Pull-down Resistors) MCU RTCOUTx WKUP0 WKUP1 Pull-down Resistors GND GND GND The debouncing period duration is configurable. The period is set for all debouncers (i.e., the duration cannot be adjusted for each debouncer). The number of successive identical samples to wake up the system can be configured from 2 up to 8 in the LPDBC field of SUPC_WUMR. The period of time between two samples can be configured by programming the TPERIOD field in the RTC_MR. Power parameters can be adjusted by modifying the period of time in the THIGH field in RTC_MR. The wake-up polarity of the inputs can be independently configured by writing WKUPT0 and/ or WKUPT1 fields in SUPC_WUMR. In order to determine which wake-up/tamper pin triggers the system wake-up, a status flag is associated for each low-power debouncer. These flags are read in SUPC_SR. A debounce event (tamper detection) can perform an immediate clear (0 delay) on the first half the generalpurpose backup registers (GPBR). The LPDBCCLR bit must be set in SUPC_WUMR. Note that it is not mandatory to use the RTCOUTx pin when using the WKUP0/WKUP1 pins as tampering inputs in any mode. Using the RTCOUTx pin provides a “sampling mode” to further reduce the power consumption of the 336 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 tamper detection circuitry. If RTCOUTx is not used, the RTC must be configured to create an internal sampling point for the debouncer logic. The period of time between two samples can be configured by programming the TPERIOD field in RTC_MR. Figure 18-8 illustrates the use of WKUPx without the RTCOUTx pin. Figure 18-8. Using WKUP Pins Without RTCOUTx Pins VDDIO MCU Pull-up Resistor WKUP0 Pull-up Resistor GND WKUP1 GND GND 18.4.7.3 Clock Alarms The RTC and the RTT alarms can generate a wake-up of the core power supply. This can be enabled by setting, respectively, the bits RTCEN and RTTEN in SUPC_WUMR. The Supply Controller does not provide any status as the information is available in the user interface of either the Real-Time Timer or the Real-Time Clock. 18.4.7.4 Supply Monitor Detection The supply monitor can generate a wake-up of the core power supply. See Section 18.4.4 ”Supply Monitor”. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 337 18.4.8 Register Write Protection To prevent any single software error from corrupting SYSC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the ”System Controller Write Protection Mode Register” (SYSC_WPMR). The following registers can be write-protected:  RSTC Mode Register  RTT Mode Register  RTT Alarm Register  RTC Control Register  RTC Mode Register  RTC Time Alarm Register  RTC Calendar Alarm Register  General Purpose Backup Registers  Supply Controller Control Register  Supply Controller Supply Monitor Mode Register  Supply Controller Mode Register  Supply Controller Wake-up Mode Register  Supply Controller Wake-up Inputs Register 18.4.9 Register Bits in Backup Domain (VDDIO) The following configuration registers, or certain bits of the registers, are physically located in the product backup domain: 338  RSTC Mode Register (all bits)  RTT Mode Register (all bits)  RTT Alarm Register (all bits)  RTC Control Register (all bits)  RTC Mode Register (all bits)  RTC Time Alarm Register (all bits)  RTC Calendar Alarm Register (all bits)  General Purpose Backup Registers (all bits)  Supply Controller Control Register (see register description for details)  Supply Controller Supply Monitor Mode Register (all bits)  Supply Controller Mode Register (see register description for details)  Supply Controller Wake-up Mode Register (all bits)  Supply Controller Wake-up Inputs Register (all bits)  Supply Controller Status Register (all bits) SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 18.5 Supply Controller (SUPC) User Interface The user interface of the Supply Controller is part of the System Controller user interface. 18.5.1 System Controller (SYSC) User Interface Table 18-1. System Controller Registers Offset System Controller Peripheral Name 0x00-0x0c Reset Controller RSTC 0x10-0x2C Supply Controller SUPC 0x30-0x3C Real Time Timer RTT 0x50-0x5C Watchdog Timer WDT 0x60-0x8C Real Time Clock RTC 0x90-0xDC General Purpose Backup Register GPBR 0xE0 Reserved – 0xE4 Write Protection Mode Register SYSC_WPMR 0xE8-0xF8 Reserved – 18.5.2 Supply Controller (SUPC) User Interface Table 18-2. Register Mapping Offset Register Name Access Reset 0x00 Supply Controller Control Register SUPC_CR Write-only – 0x04 Supply Controller Supply Monitor Mode Register SUPC_SMMR Read/Write 0x0000_0000 0x08 Supply Controller Mode Register SUPC_MR Read/Write 0x0000_5A00 0x0C Supply Controller Wake-up Mode Register SUPC_WUMR Read/Write 0x0000_0000 0x10 Supply Controller Wake-up Inputs Register SUPC_WUIR Read/Write 0x0000_0000 0x14 Supply Controller Status Register SUPC_SR Read-only 0x0000_0000 0x18 Reserved – – – SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 339 18.5.3 Supply Controller Control Register Name: SUPC_CR Address: 0x400E1410 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 XTALSEL 2 VROFF 1 – 0 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR). • VROFF: Voltage Regulator Off 0 (NO_EFFECT): No effect. 1 (STOP_VREG): If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. Note: This bit is located in the VDDIO domain. • XTALSEL: Crystal Oscillator Select 0 (NO_EFFECT): No effect. 1 (CRYSTAL_SEL): If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. Note: This bit is located in the VDDIO domain. • KEY: Password 340 Value Name 0xA5 PASSWD SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Description Writing any other value in this field aborts the write operation. 18.5.4 Supply Controller Supply Monitor Mode Register Name: SUPC_SMMR Address: 0x400E1414 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 SMIEN 12 SMRSTEN 11 – 10 9 SMSMPL 8 7 – 6 – 5 – 4 – 3 2 1 0 SMTH This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR). • SMTH: Supply Monitor Threshold Selects the threshold voltage of the supply monitor. Refer to the Electrical Characteristics for voltage values. • SMSMPL: Supply Monitor Sampling Period Value Name Description 0x0 SMD Supply Monitor disabled 0x1 CSM Continuous Supply Monitor 0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods • SMRSTEN: Supply Monitor Reset Enable 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. 1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. • SMIEN: Supply Monitor Interrupt Enable 0 (NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs. 1 (ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 341 18.5.5 Supply Controller Mode Register Name: SUPC_MR Address: 0x400E1418 Access: Read/Write 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 OSCBYPASS 19 – 18 – 17 – 16 – 15 – 14 ONREG 13 BODDIS 12 BODRSTEN 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR). • BODRSTEN: Brownout Detector Reset Enable 0 (NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a brownout detection occurs. 1 (ENABLE): The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. Note: This bit is located in the VDDIO domain. • BODDIS: Brownout Detector Disable 0 (ENABLE): The core brownout detector is enabled. 1 (DISABLE): The core brownout detector is disabled. Note: This bit is located in the VDDIO domain. • ONREG: Voltage Regulator Enable 0 (ONREG_UNUSED): Internal voltage regulator is not used (external power supply is used). 1 (ONREG_USED): Internal voltage regulator is used. Note: This bit is located in the VDDIO domain. • OSCBYPASS: Oscillator Bypass 0 (NO_EFFECT): No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). 1 (BYPASS): The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. Note: This bit is located in the VDDIO domain. • KEY: Password Key 342 Value Name 0xA5 PASSWD SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Description Writing any other value in this field aborts the write operation. 18.5.6 Supply Controller Wake-up Mode Register Name: SUPC_WUMR Address: 0x400E141C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 LPDBC 16 15 – 14 13 WKUPDBC 12 11 – 10 – 9 – 8 – 7 LPDBCCLR 6 LPDBCEN1 5 LPDBCEN0 4 – 3 RTCEN 2 RTTEN 1 SMEN 0 – This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR). • SMEN: Supply Monitor Wake-up Enable 0 (NOT_ENABLE): The supply monitor detection has no wake-up effect. 1 (ENABLE): The supply monitor detection forces the wake-up of the core power supply. • RTTEN: Real-time Timer Wake-up Enable 0 (NOT_ENABLE): The RTT alarm signal has no wake-up effect. 1 (ENABLE): The RTT alarm signal forces the wake-up of the core power supply. • RTCEN: Real-time Clock Wake-up Enable 0 (NOT_ENABLE): The RTC alarm signal has no wake-up effect. 1 (ENABLE): The RTC alarm signal forces the wake-up of the core power supply. • LPDBCEN0: Low-power Debouncer Enable WKUP0 0 (NOT_ENABLE): The WKUP0 input pin is not connected to the low-power debouncer. 1 (ENABLE): The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. • LPDBCEN1: Low-power Debouncer Enable WKUP1 0 (NOT_ENABLE): The WKUP1 input pin is not connected to the low-power debouncer. 1 (ENABLE): The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. • LPDBCCLR: Low-power Debouncer Clear 0 (NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of GPBR registers. 1 (ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 343 • WKUPDBC: Wake-up Inputs Debouncer Period Value Name Description 0 IMMEDIATE 1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods 2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods 3 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods 4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods 5 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods Immediate, no debouncing, detected active at least on one Slow Clock edge. • LPDBC: Low-power Debouncer Period 344 Value Name 0 DISABLE 1 2_RTCOUT0 WKUP0/1 in active state for at least 2 RTCOUTx clock periods 2 3_RTCOUT0 WKUP0/1 in active state for at least 3 RTCOUTx clock periods 3 4_RTCOUT0 WKUP0/1 in active state for at least 4 RTCOUTx clock periods 4 5_RTCOUT0 WKUP0/1 in active state for at least 5 RTCOUTx clock periods 5 6_RTCOUT0 WKUP0/1 in active state for at least 6 RTCOUTx clock periods 6 7_RTCOUT0 WKUP0/1 in active state for at least 7 RTCOUTx clock periods 7 8_RTCOUT0 WKUP0/1 in active state for at least 8 RTCOUTx clock periods SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Description Disable the low-power debouncers. 18.5.7 Supply Controller Wake-up Inputs Register Name: SUPC_WUIR Address: 0x400E1420 Access: Read/Write 31 WKUPT15 30 WKUPT14 29 WKUPT13 28 WKUPT12 27 WKUPT11 26 WKUPT10 25 WKUPT9 24 WKUPT8 23 WKUPT7 22 WKUPT6 21 WKUPT5 20 WKUPT4 19 WKUPT3 18 WKUPT2 17 WKUPT1 16 WKUPT0 15 WKUPEN15 14 WKUPEN14 13 WKUPEN13 12 WKUPEN12 11 WKUPEN11 10 WKUPEN10 9 WKUPEN9 8 WKUPEN8 7 WKUPEN7 6 WKUPEN6 5 WKUPEN5 4 WKUPEN4 3 WKUPEN3 2 WKUPEN2 1 WKUPEN1 0 WKUPEN0 This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_MR). • WKUPEN0 - WKUPENx: Wake-up Input Enable 0 to x 0 (DISABLE): The corresponding wake-up input has no wake-up effect. 1 (ENABLE): The corresponding wake-up input is enabled for a wake-up of the core power supply. • WKUPT0 - WKUPTx: Wake-up Input Type 0 to x 0 (LOW): A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. 1 (HIGH): A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 345 18.5.8 Supply Controller Status Register Name: SUPC_SR Address: 0x400E1424 Access: Read-only 31 WKUPIS15 30 WKUPIS14 29 WKUPIS13 28 WKUPIS12 27 WKUPIS11 26 WKUPIS10 25 WKUPIS9 24 WKUPIS8 23 WKUPIS7 22 WKUPIS6 21 WKUPIS5 20 WKUPIS4 19 WKUPIS3 18 WKUPIS2 17 WKUPIS1 16 WKUPIS0 15 – 14 LPDBCS1 13 LPDBCS0 12 – 11 – 10 – 9 – 8 – 7 OSCSEL 6 SMOS 5 SMS 4 SMRSTS 3 BODRSTS 2 SMWS 1 WKUPS 0 – Note: Because of the asynchronism between the Slow Clock (SLCK) and the System Clock (MCK), the status register flag reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR. This register is located in the VDDIO domain. • WKUPS: WKUP Wake-up Status (cleared on read) 0 (NO): No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. • SMWS: Supply Monitor Detection Wake-up Status (cleared on read) 0 (NO): No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. • BODRSTS: Brownout Detector Reset Status (cleared on read) 0 (NO): No core brownout rising edge event has been detected since the last read of the SUPC_SR. 1 (PRESENT): At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detection cell. The rising edge event occurs only when there is a voltage transition below the threshold. • SMRSTS: Supply Monitor Reset Status (cleared on read) 0 (NO): No supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 (PRESENT): At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. • SMS: Supply Monitor Status (cleared on read) 0 (NO): No supply monitor detection since the last read of SUPC_SR. 1 (PRESENT): At least one supply monitor detection since the last read of SUPC_SR. • SMOS: Supply Monitor Output Status 0 (HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement. 1 (LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement. 346 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • OSCSEL: 32-kHz Oscillator Selection Status 0 (RC): The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. 1 (CRYST): The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. • LPDBCS0: Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) 0 (NO): No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. • LPDBCS1: Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) 0 (NO): No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. 1 (PRESENT): At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. • WKUPISx: WKUPx Input Status (cleared on read) 0 (DIS): The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 1 (EN): The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 347 18.5.9 System Controller Write Protection Mode Register Name: SYSC_WPMR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII). See Section 18.4.8 ”Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key. Value Name 0x525443 PASSWD 348 Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 19. General Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds 256 bits of General Purpose Backup registers organized as Eight 32-bit registers. It is possible to generate an immediate clear of the content of General Purpose Backup registers 0 to 3 (first half) if a Low-power Debounce event is detected on one of the wakeup pins, WKUP0 or WKUP1. The content of the other General Purpose Backup registers (second half) remains unchanged. The Supply Controller module must be programmed accordingly. In the register SUPC_WUMR in the Supply Controller module, LPDBCCLR, LPDBCEN0 and/or LPDBCEN1 bit must be configured to 1 and LPDBC must be other than 0. If a Tamper event has been detected, it is not possible to write to the General Purpose Backup registers while the LPDBCS0 or LPDBCS1 flags are not cleared in the Supply Controller Status Register (SUPC_SR). 19.2 Embedded Characteristics  256 bits of General Purpose Backup Registers SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 349 19.3 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Offset 0x0 ... 0x1C 350 Register Mapping Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 7 SYS_GPBR7 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Access Reset Read/Write 0x00000000 ... ... Read/Write 0x00000000 19.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0x400E1490 Access: Read/Write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 GPBR_VALUE 23 22 21 20 19 GPBR_VALUE 15 14 13 12 11 GPBR_VALUE 7 6 5 4 3 GPBR_VALUE These registers are reset at first power-up and on each loss of VVDIO. • GPBR_VALUE: Value of GPBR x If a Tamper event has been detected, it is not possible to write GPBR_VALUE as long as the LPDBCS0 or LPDBCS1 flag has not been cleared in the Supply Controller Status Register (SUPC_SR). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 351 20. Enhanced Embedded Flash Controller (EEFC) 20.1 Description The Enhanced Embedded Flash Controller (EEFC) provides the interface of the Flash block with the 32-bit internal bus. Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 20.2 20.3 Embedded Characteristics  Increases Performance in Thumb-2 Mode with 128-bit or 64-bit-wide Memory Interface up to 120 MHz  Code Loop Optimization  256 Lock Bits, Each Protecting a Lock Region  GPNVMx General-purpose GPNVM Bits  One-by-one Lock Bit Programming  Commands Protected by a Keyword  Erase the Entire Flash  Erase by Plane  Erase by Sector  Erase by Page  Provides Unique Identifier  Provides 512-byte User Signature Area  Supports Erasing before Programming  Locking and Unlocking Operations  Supports Read of the Calibration Bits Product Dependencies 20.3.1 Power Management The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no effect on its behavior. 20.3.2 Interrupt Sources The EEFC interrupt line is connected to the interrupt controller. Using the EEFC interrupt requires the interrupt controller to be programmed first. The EEFC interrupt is generated only if the value of bit EEFC_FMR.FRDY is 1. Table 20-1. 352 Peripheral IDs Instance ID EFC0 6 EFC1 7 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 20.4 Functional Description 20.4.1 Embedded Flash Organization The embedded Flash interfaces directly with the internal bus. The embedded Flash is composed of:  One memory plane organized in several pages of the same size for the code  A separate 2 x 512-byte memory area which includes the unique chip identifier  A separate 512-byte memory area for the user signature  Two 128-bit or 64-bit read buffers used for code read optimization  One 128-bit or 64-bit read buffer used for data read optimization  One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 Mbyte address space, so that each word can be written to its final address.  Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with a lock region composed of several pages in the memory plane.  Several bits that may be set and cleared through the EEFC interface, called general-purpose non-volatile memory bits (GPNVM bits) The embedded Flash size, the page size, the organization of lock regions and the definition of GPNVM bits are specific to the device. The EEFC returns a descriptor of the Flash controller after a ‘Get Flash Descriptor’ command has been issued by the application (see Section 20.4.3.1 ”Get Flash Descriptor Command”). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 353 Flash Memory Areas C od e Ar ea Figure 20-1. @FBA+0x010 @FBA+0x000 Write “Stop Unique Identifier” (Flash Command SPUI) U ni qu e Id en tif ie rA re a @FBA+0x3FF Write “Start Unique Identifier” (Flash Command STUI) @FBA+0x010 Unique Identifier @FBA+0x000 Write “Stop User signature” (Flash Command SPUS) Write “Start User Signature” (Flash Command STUS) U se rS ig na tu re Ar ea @FBA+0x1FF 354 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 @FBA+0x000 FBA = Flash Base Address Figure 20-2. Organization of Embedded Flash for Code Memory Plane Start Address Page 0 Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock Bit (n-1) Page (m-1) Start Address + Flash size -1 Page (n*m-1) SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 355 20.4.2 Read Operations An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in Thumb-2 mode by means of the 128- or 64-bit-wide memory interface. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. The read operations can be performed with or without wait states. Wait states must be programmed in the field FWS in the Flash Mode register (EEFC_FMR). Defining FWS as 0 enables the single-cycle access of the embedded Flash. For mre details, refer to the section “Electrical Characteristics” of this datasheet. 20.4.2.1 128- or 64-bit Access Mode By default, the read accesses of the Flash are performed through a 128-bit wide memory interface. It improves system performance especially when two or three wait states are needed. For systems requiring only 1 wait state, or to focus on current consumption rather than performance, the user can select a 64-bit wide memory access via the bit EEFC_FMR.FAM. For more details, refer to the section “Electrical Characteristics” of this datasheet. 20.4.2.2 Code Read Optimization Code read optimization is enabled if the bit EEFC_FMR.SCOD is cleared. A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential code fetch. Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization. The sequential code read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set to 1, these buffers are disabled and the sequential code read is no longer optimized. Another system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize loop code fetch. Refer to Section 20.4.2.3 ”Code Loop Optimization” for more details. Figure 20-3. Code Read Optimization for FWS = 0 Master Clock ARM Request (32-bit) @0 @+4 @ +8 @+12 @+16 @+20 @+24 @+28 @+32 anticipation of @16-31 Flash Access Buffer 0 (128 bits) Buffer 1 (128 bits) Data to ARM XXX Bytes 0–15 Bytes 16–31 XXX Bytes 32–47 Bytes 32–47 Bytes 0–15 XXX Bytes 0–3 Bytes 16–31 Bytes 4–7 Bytes 8–11 Bytes 12–15 Bytes 16–19 Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access. 356 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Bytes 20–23 Bytes 24–27 Bytes 28–31 Figure 20-4. Code Read Optimization for FWS = 3 Master Clock ARM Request (32-bit) @+4 @+8 @+12 @+16 @+20 @+24 @+28 @+32 @+36 @+40 @+44 @+48 @+52 @0 wait 3 cycles before 128-bit data is stable @0/4/8/12 are ready Flash Access anticipation of @32-47 anticipation of @16-31 @16/20/24/28 are ready Bytes 0–15 Bytes 16–31 Buffer 0 (128 bits) Bytes 32–47 Bytes 0–15 Buffer 1 (128 bits) Bytes 32–47 Bytes 16–31 XXX XXX Data to ARM 0–3 Bytes 48–6 4–7 8–11 12–15 16–19 20–23 24–27 28–31 32–35 36–39 40–43 44–47 48–51 Note: When FWS is between 1 and 3, in case of sequential reads, the first access takes (FWS + 1) cycles. The following accesses take only one cycle. 20.4.2.3 Code Loop Optimization Code loop optimization is enabled when the bit EEFC_FMR.CLOE is set to 1. When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken and becomes inefficient. In this case, the loop code read optimization takes over from the sequential code read optimization to prevent the insertion of wait states. The loop code read optimization is enabled by default. In EEFC_FMR, if the bit CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized. When code loop optimization is enabled, if inner loop body instructions L0 to Ln are positioned from the 128-bit Flash memory cell Mb0 to the memory cell Mp1, after recognition of a first backward branch, the first two Flash memory cells Mb0 and Mb1 targeted by this branch are cached for fast access from the processor at the next loop iteration. Then by combining the sequential prefetch (described in Section 20.4.2.2 ”Code Read Optimization”) through the loop body with the fast read access to the loop entry cache, the entire loop can be iterated with no wait state. Figure 20-5 illustrates code loop optimization. Figure 20-5. Code Loop Optimization Backward address jump Flash Memory 128-bit words Mb0 B0 B1 Mb1 Mp0 Mp1 L0 L1 L2 L3 L4 L5 Ln-5 Ln-4 Ln-3 Ln-2 Ln-1 Ln B2 B3 B4 B5 B6 B7 P0 P1 P2 P3 P4 P5 2x128-bit loop entry cache P6 P7 2x128-bit prefetch buffer Mb0 Branch Cache 0 L0 Loop Entry instruction Mp0 Prefetch Buffer 0 Mb1 Branch Cache 1 Ln Loop End instruction Mp1 Prefetch Buffer 1 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 357 20.4.2.4 Data Read Optimization The organization of the Flash in 128 bits or 64 bits is associated with two 128-bit or 64-bit prefetch buffers and one 128-bit or 64-bit data read buffer, thus providing maximum system performance. This buffer is added in order to store the requested data plus all the data contained in the 128-bit or 64-bit aligned data. This speeds up sequential data reads if, for example, FWS is equal to 1 (see Figure 20-6). The data read optimization is enabled by default. If the bit EEFC_FMR.SCOD is set to 1, this buffer is disabled and the data read is no longer optimized. Note: Figure 20-6. No consecutive data read accesses are mandatory to benefit from this optimization. Data Read Optimization for FWS = 1 Master Clock ARM Request (32-bit) @Byte 0 @4 Flash Access XXX @ 12 @ 16 Bytes 0–15 XXX @ 20 @ 24 @ 28 4–7 8–11 @ 36 Bytes 32–47 Bytes 0–15 Bytes 0–3 @ 32 Bytes 16–31 XXX Buffer (128 bits) Data to ARM @8 Bytes 16–31 12–15 16–19 20–23 24–27 28–31 32–35 20.4.3 Flash Commands The EEFC offers a set of commands to manage programming the Flash memory, locking and unlocking lock regions, consecutive programming, locking and full Flash erasing, etc. The commands are listed in the following table. Table 20-2. 358 Set of Commands Command Value Mnemonic Get Flash descriptor 0x00 GETD Write page 0x01 WP Write page and lock 0x02 WPL Erase page and write page 0x03 EWP Erase page and write page then lock 0x04 EWPL Erase all 0x05 EA Erase pages 0x07 EPA Set lock bit 0x08 SLB Clear lock bit 0x09 CLB Get lock bit 0x0A GLB Set GPNVM bit 0x0B SGPB Clear GPNVM bit 0x0C CGPB SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 20-2. Set of Commands (Continued) Command Value Mnemonic Get GPNVM bit 0x0D GGPB Start read unique identifier 0x0E STUI Stop read unique identifier 0x0F SPUI Get CALIB bit 0x10 GCALB Erase sector 0x11 ES Write user signature 0x12 WUS Erase user signature 0x13 EUS Start read user signature 0x14 STUS Stop read user signature 0x15 SPUS In order to execute one of these commands, select the required command using the FCMD field in the Flash Command register (EEFC_FCR). As soon as EEFC_FCR is written, the FRDY flag and the FVALUE field in the Flash Result register (EEFC_FRR) are automatically cleared. Once the current command has completed, the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. (Note that this is true for all commands except for the STUI command. The FRDY flag is not set when the STUI command has completed.) All the commands are protected by the same keyword, which must be written in the eight highest bits of EEFC_FCR. Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the whole memory plane, but the FCMDE flag is set in the Flash Status register (EEFC_FSR). This flag is automatically cleared by a read access to EEFC_FSR. When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the FLOCKE flag is set in EEFC_FSR. This flag is automatically cleared by a read access to EEFC_FSR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 359 Figure 20-7. Command State Chart Read Status: EEFC_FSR No Check if FRDY flag Set Yes Write FCMD and PAGENB in Flash Command Register Read Status: EEFC_FSR No Check if FRDY flag Set Yes Check if FLOCKE flag Set Yes Locking region violation No Check if FCMDE flag Set Yes Bad keyword violation No Command Successful 20.4.3.1 Get Flash Descriptor Command This command provides the system with information on the Flash organization. The system can take full advantage of this information. For instance, a device could be replaced by one with more Flash capacity, and so the software is able to adapt itself to the new configuration. To get the embedded Flash descriptor, the application writes the GETD command in EEFC_FCR. The first word of the descriptor can be read by the software application in EEFC_FRR as soon as the FRDY flag in EEFC_FSR rises. The next reads of EEFC_FRR provide the following word of the descriptor. If extra read operations to EEFC_FRR are done after the last word of the descriptor has been returned, the EEFC_FRR value is 0 until the next valid command. 360 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 20-3. Flash Descriptor Definition Symbol Word Index Description FL_ID 0 Flash interface description FL_SIZE 1 Flash size in bytes FL_PAGE_SIZE 2 Page size in bytes FL_NB_PLANE 3 Number of planes FL_PLANE[0] 4 Number of bytes in the plane FL_NB_LOCK 4 + FL_NB_PLANE Number of lock bits. A bit is associated with a lock region. A lock bit is used to prevent write or erase operations in the lock region. FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region 20.4.3.2 Write Commands Several commands are used to program the Flash. Only 0 values can be programmed using Flash technology; 1 is the erased value. In order to program words in a page, the page must first be erased. Commands are available to erase the full memory plane or a given number of pages. With the EWP and EWPL commands, a page erase is done automatically before a page programming. After programming, the page (the entire lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL or EWPL commands. Data to be programmed in the Flash must be written in an internal latch buffer before writing the programming command in EEFC_FCR. Data can be written at their final destination address, as the latch buffer is mapped into the Flash memory address space and wraps around within this Flash address space. Byte and half-word AHB accesses to the latch buffer are not allowed. Only 32-bit word accesses are supported. 32-bit words must be written continuously, in either ascending or descending order. Writing the latch buffer in a random order is not permitted. This prevents mapping a C-code structure to the latch buffer and accessing the data of the structure in any order. It is instead recommended to fill in a C-code structure in SRAM and copy it in the latch buffer in a continuous order. Write operations in the latch buffer are performed with the number of wait states programmed for reading the Flash. The latch buffer is automatically re-initialized, i.e., written with logical 1, after execution of each programming command. However, after power-up, the latch buffer is not initialized. If only part of the page is to be written with user data, the remaining part must be erased (written with 1). The programming sequence is the following: 1. Write the data to be programmed in the latch buffer. 2. Write the programming command in EEFC_FCR. This automatically clears the bit EEFC_FSR.FRDY. 3. When Flash programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the EEFC is activated. Three errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Lock Error: The page to be programmed belongs to a locked region. A command must be run previously to unlock the corresponding region.  Flash Error: When programming is completed, the WriteVerify test of the Flash memory has failed. Only one page can be programmed at a time. It is possible to program all the bits of a page (full page programming) or only some of the bits of the page (partial page programming). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 361 Depending on the number of bits to be programmed within the page, the EEFC adapts the write operations required to program the Flash. When a ‘Write Page’ (WP) command is issued, the EEFC starts the programming sequence and all the bits written at 0 in the latch buffer are cleared in the Flash memory array. During programming, i.e., until EEFC_FSR.FDRY rises, access to the Flash is not allowed. Full Page Programming To program a full page, all the bits of the page must be erased before writing the latch buffer and issuing the WP command. The latch buffer must be written in ascending order, starting from the first address of the page. See Figure 20-8 "Full Page Programming". Partial Page Programming To program only part of a page using the WP command, the following constraints must be respected:  Data to be programmed must be contained in integer multiples of 64-bit address-aligned words.  64-bit words can be programmed only if all the corresponding bits in the Flash array are erased (at logical value 1). See Figure 20-9 "Partial Page Programming". Programming Bytes Individual bytes can be programmed using the Partial page programming mode. In this case, an area of 64 bits must be reserved for each byte. Refer to Figure 20-10 "Programming Bytes in the Flash". 362 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 20-8. Full Page Programming 32 bits wide 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF 0xX1C FF FF FF FF 0xX14 FF FF FF FF 0xX10 FF FF FF FF FF FF 0xX0C 0xX08 FF FF FE 0xX04 FF FF FF FF 0xX04 FE 0xX00 FF FF FF FF 0xX00 CA FE CA FE CA FE CA FE 0xX1C CA FE CA FE 0xX18 CA FE CA FE 0xX14 CA FE CA FE 0xX10 CA FE CA FE 0xX0C CA FE CA FE CA FE CA CA FE CA address space for Page N Before programming: Unerased page in Flash array 0xX18 0xX08 Step 1: Flash array after page erase DE CA DE CA DE CA DE CA 0xX1C DE CA DE CA 0xX18 DE DE CA CA DE DE CA CA 0xX14 0xX0C DE CA DE CA 0xX0C CA 0xX08 DE CA DE CA 0xX08 DE CA 0xX04 DE CA DE CA 0xX04 DE CA 0xX00 DE CA DE CA 0xX00 DE CA DE CA DE CA DE CA 0xX1C DE CA DE CA 0xX18 DE DE CA CA DE DE CA CA 0xX14 DE CA DE CA DE CA DE DE CA DE CA 0xX10 address space for latch buffer Step 2: Writing a page in the latch buffer 0xX10 address space for Page N Step 3: Page in Flash array after issuing WP command and FRDY=1 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 363 Figure 20-9. Partial Page Programming 32 bits wide 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX1C FF FF FF FF FF FF FF FF 0xX14 FF FF FF FF FF FF FF FF 0xX10 FF FF FF FF FF FF FF FF CA CA FE FE CA CA FE FE 0xX0C FF FF FF FF FF FF FF FF 0xX04 FF FF FF FF FF FF FF FF 0xX00 address space for Page N Step 1: Flash array after page erase 0xX18 0xX08 Step 2: Flash array after programming 64-bit at address 0xX08 (write latch buffer + WP) 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF CA CA FE FE CA CA 364 32 bits wide FE FE FF FF FF FF 0xX1C CA FE CA FE 0xX1C 0xX18 CA FE CA FE 0xX18 FF 0xX14 CA FE CA FE 0xX14 FF FF 0xX10 CA FE CA FE 0xX10 CA CA FE FE 0xX0C CA FE CA FE 0xX0C 0xX08 CA FE CA FE 0xX08 FE FE 0xX04 CA FE CA FE 0xX04 0xX00 CA FE CA FE 0xX00 CA CA Step 3: Flash array after programming Step 4: Flash array after programming a second 64-bit data at address 0xX00 a 128-bit data word at address 0xX10 (write latch buffer + WP) (write latch buffer + WP) SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 20-10. Programming Bytes in the Flash 32 bits wide 4 x 32 bits = 1 Flash word 4 x 32 bits = 1 Flash word 32 bits wide FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0xX1C FF FF FF FF FF FF FF FF address space 0xX14 for Page N 0xX10 FF FF FF FF 0xX14 FF FF FF FF 0xX10 FF FF FF FF 0xX0C xx xx xx xx 0xX0C FF FF FF FF 0xX08 xx xx xx 55 0xX08 xx xx xx xx 0xX04 xx xx xx xx 0xX04 xx xx xx AA 0xX00 xx xx xx AA 0xX00 0xX1C 0xX18 0xX18 Step 1: Flash array after programming first byte (0xAA) Step 2: Flash array after programming second byte (0x55) 64-bit used at address 0xX00 (write latch buffer + WP) 64-bit used at address 0xX08 (write latch buffer + WP) Note: The byte location shown here is for example only, it can be any byte location within a 64-bit word. 20.4.3.3 Erase Commands Erase commands are allowed only on unlocked regions. Depending on the Flash memory, several commands can be used to erase the Flash:  Erase All Memory (EA): All memory is erased. The processor must not fetch code from the Flash memory.  Erase Pages (EPA): 8 or 16 pages are erased in the Flash sector selected. The first page to be erased is specified in the FARG[15:2] field of the EEFC_FCR. The first page number must be a multiple of 8, 16 or 32 depending on the number of pages to erase at the same time.  Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory. EEFC_FCR.FARG must be set with a page number that is in the sector to be erased. If the processor is fetching code from the Flash memory while the EPA or ES command is being executed, the processor accesses are stalled until the EPA command is completed. To avoid stalling the processor, the code can be run out of internal SRAM. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 365 The erase sequence is the following: 1. Erase starts as soon as one of the erase commands and the FARG field are written in EEFC_FCR. ̶ For the EPA command, the two lowest bits of the FARG field define the number of pages to be erased (FARG[1:0]): Table 20-4. EEFC_FCR.FARG Field for EPA Command FARG[1:0] 2. Number of pages to be erased with EPA command 0 4 pages (only valid for small 8 KB sectors) 1 8 pages 2 16 pages 3 32 pages (not valid for small 8 KB sectors) When erasing is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Three errors can be detected in EEFC_FSR after an erasing sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Lock Error: At least one page to be erased belongs to a locked region. The erase command has been refused, no page has been erased. A command must be run previously to unlock the corresponding region.  Flash Error: At the end of the erase period, the EraseVerify test of the Flash memory has failed. 20.4.3.4 Lock Bit Protection Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. The lock sequence is the following: 1. Execute the ‘Set Lock Bit’ command by writing EEFC_FCR.FCMD with the SLB command and EEFC_FCR.FARG with a page number to be protected. 2. When the locking completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SLB command can be checked running a ‘Get Lock Bit’ (GLB) command. Note: The value of the FARG argument passed together with SLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear lock bits previously set. After the lock bits are cleared, the locked region can be erased or programmed. The unlock sequence is the following: 1. Execute the ‘Clear Lock Bit’ command by writing EEFC_FCR.FCMD with the CLB command and EEFC_FCR.FARG with a page number to be unprotected. 2. Note: When the unlock completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. The value of the FARG argument passed together with CLB command must not exceed the higher lock bit index available in the product. Two errors can be detected in EEFC_FSR after a programming sequence:  366 Command Error: A bad keyword has been written in EEFC_FCR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. The status of lock bits can be returned by the EEFC. The ‘Get Lock Bit’ sequence is the following: 1. Execute the ‘Get Lock Bit’ command by writing EEFC_FCR.FCMD with the GLB command. Field EEFC_FCR.FARG is meaningless. 2. Lock bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. For example, if the third bit of the first word read in EEFC_FRR is set, the third lock region is locked. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. Note: 20.4.3.5 Access to the Flash in read is permitted when a ‘Set Lock Bit’, ‘Clear Lock Bit’ or ‘Get Lock Bit’ command is executed. GPNVM Bit GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to the section “Memories” of this datasheet. The ‘Set GPNVM Bit’ sequence is the following: 1. Execute the ‘Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be set. 2. When the GPNVM bit is set, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. 3. The result of the SGPB command can be checked by running a ‘Get GPNVM Bit’ (GGPB) command. Note: The value of the FARG argument passed together with SGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. It is possible to clear GPNVM bits previously set. The ‘Clear GPNVM Bit’ sequence is the following: 1. Execute the ‘Clear GPNVM Bit’ command by writing EEFC_FCR.FCMD with the CGPB command and EEFC_FCR.FARG with the number of GPNVM bits to be cleared. 2. Note: When the clear completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. The value of the FARG argument passed together with CGPB command must not exceed the higher GPNVM index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is detected only if FARG is greater than 8. Two errors can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed. The status of GPNVM bits can be returned by the EEFC. The sequence is the following: SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 367 1. Execute the ‘Get GPNVM Bit’ command by writing EEFC_FCR.FCMD with the GGPB command. Field EEFC_FCR.FARG is meaningless. 2. GPNVM bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. For example, if the third bit of the first word read in EEFC_FRR is set, the third GPNVM bit is active. One error can be detected in EEFC_FSR after a programming sequence:  Command Error: A bad keyword has been written in EEFC_FCR. Note: 20.4.3.6 Access to the Flash in read is permitted when a ‘Set GPNVM Bit’, ‘Clear GPNVM Bit’ or ‘Get GPNVM Bit’ command is executed. Calibration Bit Calibration bits do not interfere with the embedded Flash memory plane. The calibration bits cannot be modified. The status of calibration bits are returned by the EEFC. The sequence is the following: 1. Execute the ‘Get CALIB Bit’ command by writing EEFC_FCR.FCMD with the GCALB command. Field EEFC_FCR.FARG is meaningless. 2. Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful. Extra reads to EEFC_FRR return 0. The 4/8/12 MHz fast RC oscillator is calibrated in production. This calibration can be read through the GCALB command. The following table shows the bit implementation for each frequency. Table 20-5. Calibration Bit Indexes RC Calibration Frequency EEFC_FRR Bits 8 MHz output [28–22] 12 MHz output [38–32] The RC calibration for the 4 MHz is set to ‘1000000’. 20.4.3.7 Security Bit Protection When the security bit is enabled, access to the Flash through the SWD interface or through the Fast Flash Programming interface is forbidden. This ensures the confidentiality of the code programmed in the Flash. The security bit is GPNVM0. Disabling the security bit can only be achieved by asserting the ERASE pin at ‘1’, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted. 20.4.3.8 Unique Identifier Area Each device is programmed with a 128 bits unique identifier area . See Figure 20-1 "Flash Memory Areas". The sequence to read the unique identifier area is the following: 1. Execute the ‘Start Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the STUI command. Field EEFC_FCR.FARG is meaningless. 2. 368 Wait until the bit EEFC_FSR.FRDY falls to read the unique identifier area. The unique identifier field is located in the first 128 bits of the Flash memory mapping. The ‘Start Read Unique Identifier’ command reuses some addresses of the memory plane for code, but the unique identifier area is physically different from the memory plane for code. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 3. To stop reading the unique identifier area, execute the ‘Stop Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the SPUI command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note that during the sequence, the software cannot be fetched from the Flash. 20.4.3.9 User Signature Area Each product contains a user signature area of 512-bytes. It can be used for storage. Read, write and erase of this area is allowed. See Figure 20-1 "Flash Memory Areas". The sequence to read the user signature area is the following: 1. Execute the ‘Start Read User Signature’ command by writing EEFC_FCR.FCMD with the STUS command. Field EEFC_FCR.FARG is meaningless. 2. Wait until the bit EEFC_FSR.FRDY falls to read the user signature area. The user signature area is located in the first 512 bytes of the Flash memory mapping. The ‘Start Read User Signature’ command reuses some addresses of the memory plane but the user signature area is physically different from the memory plane 3. To stop reading the user signature area, execute the ‘Stop Read User Signature’ command by writing EEFC_FCR.FCMD with the SPUS command. Field EEFC_FCR.FARG is meaningless. 4. When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated. Note that during the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual plane. One error can be detected in EEFC_FSR after this sequence:  Command Error: A bad keyword has been written in EEFC_FCR. The sequence to write the user signature area is the following: 1. Write the full page, at any page address, within the internal memory area address space. 2. Execute the ‘Write User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field EEFC_FCR.FARG is meaningless. 3. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the WriteVerify test of the Flash memory has failed. The sequence to erase the user signature area is the following: 1. Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command. Field EEFC_FCR.FARG is meaningless. 2. When programming is completed, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit EEFC_FMR.FRDY, the corresponding interrupt line of the interrupt controller is activated. Two errors can be detected in EEFC_FSR after this sequence:  Command Error: A bad keyword has been written in EEFC_FCR.  Flash Error: At the end of the programming, the EraseVerify test of the Flash memory has failed. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 369 20.5 Enhanced Embedded Flash Controller (EEFC) User Interface The User Interface of the Embedded Flash Controller (EEFC) is integrated within the System Controller with base address 0x400E0A00. Table 20-6. Register Mapping Offset Register Name Access Reset State 0x00 EEFC Flash Mode Register EEFC_FMR Read/Write 0x0400_0000 0x04 EEFC Flash Command Register EEFC_FCR Write-only – 0x08 EEFC Flash Status Register EEFC_FSR Read-only 0x0000_0001 0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0 0x10–0x14 Reserved – – – 0x18–0xE4 Reserved – – – 370 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 20.5.1 EEFC Flash Mode Register Name: EEFC_FMR Address: 0x400E0A00 (0), 0x400E0C00 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – CLOE – FAM 23 22 21 20 19 18 17 16 – – – – – – – SCOD 15 14 13 12 11 10 9 8 – – – – FWS 7 6 5 4 3 2 1 0 – – – – – – – FRDY • FRDY: Flash Ready Interrupt Enable 0: Flash ready does not generate an interrupt. 1: Flash ready (to accept a new command) generates an interrupt. • FWS: Flash Wait State This field defines the number of wait states for read and write operations: FWS = Number of cycles for Read/Write operations - 1 • SCOD: Sequential Code Optimization Disable 0: The sequential code optimization is enabled. 1: The sequential code optimization is disabled. No Flash read should be done during change of this field. • FAM: Flash Access Mode 0: 128-bit access in Read mode only, to enhance access speed. 1: 64-bit access in Read mode only, to enhance power consumption. No Flash read should be done during change of this field. • CLOE: Code Loop Optimization Enable 0: The opcode loop optimization is disabled. 1: The opcode loop optimization is enabled. No Flash read should be done during change of this field. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 371 20.5.2 EEFC Flash Command Register Name: EEFC_FCR Address: 0x400E0A04 (0), 0x400E0C04 (1) Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FKEY 23 22 21 20 FARG 15 14 13 12 FARG 7 6 5 4 FCMD • FCMD: Flash Command Value Name Description 0x00 GETD Get Flash descriptor 0x01 WP Write page 0x02 WPL Write page and lock 0x03 EWP Erase page and write page 0x04 EWPL Erase page and write page then lock 0x05 EA Erase all 0x07 EPA Erase pages 0x08 SLB Set lock bit 0x09 CLB Clear lock bit 0x0A GLB Get lock bit 0x0B SGPB Set GPNVM bit 0x0C CGPB Clear GPNVM bit 0x0D GGPB Get GPNVM bit 0x0E STUI Start read unique identifier 0x0F SPUI Stop read unique identifier 0x10 GCALB Get CALIB bit 0x11 ES Erase sector 0x12 WUS Write user signature 0x13 EUS Erase user signature 0x14 STUS Start read user signature 0x15 SPUS Stop read user signature 372 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • FARG: Flash Command Argument GETD, GLB, GGPB, STUI, SPUI, GCALB, WUS, EUS, STUS, SPUS, EA Commands requiring no argument, including Erase all command FARG is meaningless, must be written with 0 ES Erase sector command FARG must be written with any page number within the sector to be erased FARG[1:0] defines the number of pages to be erased The start page must be written in FARG[15:2]. FARG[1:0] = 0: Four pages to be erased. FARG[15:2] = Page_Number / 4 EPA Erase pages command FARG[1:0] = 1: Eight pages to be erased. FARG[15:3] = Page_Number / 8, FARG[2]=0 FARG[1:0] = 2: Sixteen pages to be erased. FARG[15:4] = Page_Number / 16, FARG[3:2]=0 FARG[1:0] = 3: Thirty-two pages to be erased. FARG[15:5] = Page_Number / 32, FARG[4:2]=0 Refer to Table 20-4 “EEFC_FCR.FARG Field for EPA Command”. WP, WPL, EWP, EWPL Programming commands FARG must be written with the page number to be programmed SLB, CLB Lock bit commands FARG defines the page number to be locked or unlocked SGPB, CGPB GPNVM commands FARG defines the GPNVM number to be programmed • FKEY: Flash Writing Protection Key Value Name 0x5A PASSWD Description The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 373 20.5.3 EEFC Flash Status Register Name: EEFC_FSR Address: 0x400E0A08 (0), 0x400E0C08 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – FLERR FLOCKE FCMDE FRDY • FRDY: Flash Ready Status (cleared when Flash is busy) 0: The EEFC is busy. 1: The EEFC is ready to start a new command. When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR. This flag is automatically cleared when the EEFC is busy. • FCMDE: Flash Command Error Status (cleared on read or by writing EEFC_FCR) 0: No invalid commands and no bad keywords were written in EEFC_FMR. 1: An invalid command and/or a bad keyword was/were written in EEFC_FMR. • FLOCKE: Flash Lock Error Status (cleared on read) 0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR. 1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR. This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written. • FLERR: Flash Error Status (cleared when a programming operation starts) 0: No Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has passed). 1: A Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed). 374 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 20.5.4 EEFC Flash Result Register Name: EEFC_FRR Address: 0x400E0A0C (0), 0x400E0C0C (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FVALUE 23 22 21 20 FVALUE 15 14 13 12 FVALUE 7 6 5 4 FVALUE • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, the next resulting value is accessible at the next register read. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 375 21. Fast Flash Programming Interface (FFPI) 21.1 Description The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. Although the Fast Flash Programming mode is a dedicated mode for high volume programming, this mode is not designed for in-situ programming. 21.2 Embedded Characteristics   376 Programming Mode for High-volume Flash Programming Using Gang Programmer ̶ Offers Read and Write Access to the Flash Memory Plane ̶ Enables Control of Lock Bits and General-purpose NVM Bits ̶ Enables Security Bit Activation ̶ Disabled Once Security Bit is Set Parallel Fast Flash Programming Interface ̶ Provides an 16-bit Parallel Interface to Program the Embedded Flash ̶ Full Handshake Protocol SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 21.3 Parallel Fast Flash Programming 21.3.1 Device Configuration In Fast Flash Programming mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left unconnected. Figure 21-1. 16-bit Parallel Programming Interface VDDIO VDDIO VDDIO TST PGMEN0 PGMEN1 VDDCORE NCMD RDY PGMNCMD PGMRDY NOE PGMNOE NVALID Table 21-1. Signal Name VDDIO VDDPLL GND PGMNVALID MODE[3:0] PGMM[3:0] DATA[15:0] PGMD[15:0] 0 - 50MHz XIN Signal Description List Function Type Active Level Comments Power VDDIO I/O Lines Power Supply Power – – VDDCORE Core Power Supply Power – – VDDPLL PLL Power Supply Power – – GND Ground Ground – – Input – 32 KHz to 50 MHz Clocks Main Clock Input. XIN This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator. Test TST Test Mode Select Input High Must be connected to VDDIO PGMEN0 Test Mode Select Input High Must be connected to VDDIO PGMEN1 Test Mode Select Input High Must be connected to VDDIO PGMEN2 Test Mode Select Input Low Must be connected to GND Input Low Pulled-up input at reset PIO PGMNCMD Valid command available SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 377 Table 21-1. Signal Description List (Continued) Signal Name Type Active Level Output High Pulled-up input at reset Input Low Pulled-up input at reset Output Low Pulled-up input at reset Input – Pulled-up input at reset Input/Output – Pulled-up input at reset Function 0: Device is busy PGMRDY 1: Device is ready for a new command PGMNOE Output Enable (active high) 0: DATA[15:0] is in input mode PGMNVALID 1: DATA[15:0] is in output mode PGMM[3:0] Specifies DATA type (see Table 21-2) PGMD[15:0] Bi-directional data bus Comments 21.3.2 Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 21-2. Mode Coding MODE[3:0] Symbol Data 0000 CMDE Command Register 0001 ADDR0 Address Register LSBs 0010 ADDR1 – 0011 ADDR2 – 0100 ADDR3 Address Register MSBs 0101 DATA Data Register Default IDLE No register When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. Table 21-3. 378 Command Bit Coding DATA[15:0] Symbol Command Executed 0x0011 READ Read Flash 0x0012 WP Write Page Flash 0x0022 WPL Write Page and Lock Flash 0x0032 EWP Erase Page and Write Page 0x0042 EWPL Erase Page and Write Page then Lock 0x0013 EA Erase All 0x0014 SLB Set Lock Bit 0x0024 CLB Clear Lock Bit 0x0015 GLB Get Lock Bit 0x0034 SGPB Set General Purpose NVM bit 0x0044 CGPB Clear General Purpose NVM bit 0x0025 GGPB Get General Purpose NVM bit 0x0054 SSE Set Security Bit SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 21-3. Command Bit Coding (Continued) DATA[15:0] Symbol Command Executed 0x0035 GSE Get Security Bit 0x001F WRAM Write Memory 0x001E GVE Get Version 21.3.3 Entering Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply the supplies as described in Table 21-1. 2. Apply XIN clock within tPOR_RESET if an external clock is available. 3. Wait for tPOR_RESET 4. Start a read or write handshaking. Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake. 21.3.4 Programmer Handshaking An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high. 21.3.4.1 Write Handshaking For details on the write handshaking sequence, refer to Figure 21-2 and Table 21-4. Figure 21-2. Parallel Programming Timing, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[15:0] 1 MODE[3:0] Table 21-4. Write Handshake Step Programmer Action Device Action Data I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latches MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 379 Table 21-4. Write Handshake (Continued) Step Programmer Action Device Action Data I/O 4 Releases MODE and DATA signals Executes command and polls NCMD high Input 5 Sets NCMD signal Executes command and polls NCMD high Input 6 Waits for RDY high Sets RDY Input 21.3.4.2 Read Handshaking For details on the read handshaking sequence, refer to Figure 21-3 and Table 21-5. Figure 21-3. Parallel Programming Timing, Read Sequence NCMD 12 2 3 RDY 13 NOE 9 5 NVALID 11 7 6 4 Adress IN DATA[15:0] Z 8 Data OUT 10 X IN 1 MODE[3:0] Table 21-5. ADDR Read Handshake Step Programmer Action Device Action DATA I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal – Tristate 6 Waits for NVALID low Sets DATA bus in output mode and outputs the flash contents. Output 7 – Clears NVALID signal Output 8 Reads value on DATA Bus Waits for NOE high Output 9 Sets NOE signal 10 Waits for NVALID high Sets DATA bus in input mode X 11 Sets DATA in output mode Sets NVALID signal Input 12 Sets NCMD signal Waits for NCMD high Input 13 Waits for RDY high Sets RDY signal Input 380 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Output 21.3.5 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 21-3. Each command is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash. 21.3.5.1 Flash Read Command This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 21-6. Read Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE READ 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Read handshaking DATA *Memory Address++ 5 Read handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Read handshaking DATA *Memory Address++ n+3 Read handshaking DATA *Memory Address++ ... ... ... ... 21.3.5.2 Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash:  before access to any page other than the current one  when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-7. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE WP or WPL or EWP or EWPL 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking DATA *Memory Address++ 5 Write handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 381 Table 21-7. Write Command (Continued) Step Handshake Sequence MODE[3:0] DATA[15:0] n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++ ... ... ... ... The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 21.3.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 21-8. Full Erase Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE EA 2 Write handshaking DATA 0 21.3.5.4 Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. In the same way, the Clear Lock command (CLB) is used to clear lock bits. Table 21-9. Set and Clear Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE SLB or CLB 2 Write handshaking DATA Bit Mask Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set. Table 21-10. Get Lock Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE GLB Lock Bit Mask Status 2 Read handshaking DATA 0 = Lock bit is cleared 1 = Lock bit is set 382 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 21.3.5.5 Flash General-purpose NVM Commands General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first GP NVM bit is activated. In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The generalpurpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. Table 21-11. Set/Clear GP NVM Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE SGPB or CGPB 2 Write handshaking DATA GP NVM bit pattern value General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is active when bit n of the bit mask is set. Table 21-12. Get GP NVM Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE GGPB GP NVM Bit Mask Status 2 Read handshaking DATA 0 = GP NVM bit is cleared 1 = GP NVM bit is set 21.3.5.6 Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Table 21-13. Set Security Bit Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE SSE 2 Write handshaking DATA 0 Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash. In order to erase the Flash, the user must perform the following: 1. Power-off the chip. 2. Power-on the chip with TST = 0. 3. Assert Erase during a period of more than 220 ms. 4. Power-off the chip. Then it is possible to return to FFPI mode and check that Flash is erased. 21.3.5.7 Memory Write Command This command is used to perform a write access to any memory location. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 383 The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-14. Write Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE WRAM 2 Write handshaking ADDR0 Memory Address LSB 3 Write handshaking ADDR1 Memory Address 4 Write handshaking DATA *Memory Address++ 5 Write handshaking DATA *Memory Address++ ... ... ... ... n Write handshaking ADDR0 Memory Address LSB n+1 Write handshaking ADDR1 Memory Address n+2 Write handshaking DATA *Memory Address++ n+3 Write handshaking DATA *Memory Address++ ... ... ... ... 21.3.5.8 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-15. 384 Get Version Command Step Handshake Sequence MODE[3:0] DATA[15:0] 1 Write handshaking CMDE GVE 2 Read handshaking DATA Version SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 22. Cortex-M Cache Controller (CMCC) 22.1 Description The Cortex-M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a controller, a tag directory, data memory, metadata memory and a configuration interface. 22.2 Embedded Characteristics  Physically addressed and physically tagged  L1 data cache set to 2 Kbytes  L1 cache line size set to 16 Bytes  L1 cache integrates 32-bit bus master interface  Unified direct mapped cache architecture  Unified 4-Way set associative cache architecture  Write through cache operations, read allocate  Round Robin victim selection policy  Event Monitoring, with one programmable 32-bit counter  Configuration registers accessible through Cortex-M Private Peripheral Bus (PPB)  Cache interface includes cache maintenance operations registers SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 385 22.3 Block Diagram Figure 22-1. Block Diagram Cortex-M Memory Interface Bus Cortex-M Interface Cache Controller META INFO RAM RAM Interface Cortex-M PPB Registers Interface DATA RAM TAG RAM Memory Interface System Memory Bus 22.4 Functional Description 22.4.1 Cache Operation On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated with its configuration registers. The configuration interface is memory-mapped in the private peripheral bus. Use the following sequence to enable the cache controller: 1. Verify that the cache controller is disabled by reading the value of the CSTS (Cache Controller Status) bit of the Status register (CMCC_SR). 2. Enable the cache controller by writing a one to the CEN (Cache Enable) bit of the Control register (CMCC_CTRL). 22.4.2 Cache Maintenance If the contents seen by the cache have changed, the user must invalidate the cache entries. This can be done lineby-line or for all cache entries. 386 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 22.4.2.1 Cache Invalidate-by-Line Operation When an invalidate-by-line command is issued, the cache controller resets the valid bit information of the decoded cache line. As the line is no longer valid, the replacement counter points to that line. Use the following sequence to invalidate one line of cache: 1. Disable the cache controller by clearing the CEN bit of CMCC_CTRL. 2. Check the CSTS bit of CMCC_SR to verify that the cache is successfully disabled. 3. Perform an invalidate-by-line by configuring the bits INDEX and WAY in the Maintenance Register 1 (CMCC_MAINT1). 4. Enable the cache controller by writing a one the CEN bit of the CMCC_CTRL. 22.4.2.2 Cache Invalidate All Operation To invalidate all cache entries, write a one to the INVALL bit of the Maintenance Register 0 (CMCC_MAINT0). 22.4.3 Cache Performance Monitoring The Cortex-M cache controller includes a programmable 32-bit monitor counter. The monitor can be configured to count the number of clock cycles, the number of data hits or the number of instruction hits. Use the following sequence to activate the counter: 1. Configure the monitor counter by writing to the MODE field of the Monitor Configuration register (CMCC_MCFG). 2. Enable the counter by writing a one to the MENABLE bit of the Monitor Enable register (CMCC_MEN). 3. If required, clear the counter by writing a one to the SWRST bit of the Monitor Control register (CMCC_MCTRL). 4. Check the value of the monitor counter by reading the EVENT_CNT field of the CMCC_MSR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 387 22.5 Cortex-M Cache Controller (CMCC) User Interface Table 22-1. Register Mapping Offset Register Name Access Reset 0x00 Cache Controller Type Register CMCC_TYPE Read-only – 0x04 Cache Controller Configuration Register CMCC_CFG Read/Write 0x00000000 0x08 Cache Controller Control Register CMCC_CTRL Write-only – 0x0C Cache Controller Status Register CMCC_SR Read-only 0x00000001 0x10–0x1C Reserved – – – 0x20 Cache Controller Maintenance Register 0 CMCC_MAINT0 Write-only – 0x24 Cache Controller Maintenance Register 1 CMCC_MAINT1 Write-only – 0x28 Cache Controller Monitor Configuration Register CMCC_MCFG Read/Write 0x00000000 0x2C Cache Controller Monitor Enable Register CMCC_MEN Read/Write 0x00000000 0x30 Cache Controller Monitor Control Register CMCC_MCTRL Write-only – 0x34 Cache Controller Monitor Status Register CMCC_MSR Read-only 0x00000000 0x38–0xFC Reserved – – – 388 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 22.5.1 Cache Controller Type Register Name: CMCC_TYPE Address: 0x4007C000 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 12 CLSIZE 11 10 9 CSIZE 8 7 LCKDOWN 6 5 4 RRP 3 LRUP 2 RANDP 1 GCLK 0 AP WAYNUM • AP: Access Port Access Allowed 0: Access Port Access is disabled. 1: Access Port Access is enabled. • GCLK: Dynamic Clock Gating Supported 0: Cache controller does not support clock gating. 1: Cache controller uses dynamic clock gating. • RANDP: Random Selection Policy Supported 0: Random victim selection is not supported. 1: Random victim selection is supported. • LRUP: Least Recently Used Policy Supported 0: Least Recently Used Policy is not supported. 1: Least Recently Used Policy is supported. • RRP: Random Selection Policy Supported 0: Random Selection Policy is not supported. 1: Random Selection Policy is supported. • WAYNUM: Number of Ways Value Name Description 0 DMAPPED Direct Mapped Cache 1 ARCH2WAY 2-way set associative 2 ARCH4WAY 4-way set associative 3 ARCH8WAY 8-way set associative SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 389 • LCKDOWN: Lockdown Supported 0: Lockdown is not supported. 1: Lockdown is supported. • CSIZE: Data Cache Size Value Name Description 0 CSIZE_1KB Data cache size is 1 Kbyte 1 CSIZE_2KB Data cache size is 2 Kbytes 2 CSIZE_4KB Data cache size is 4 Kbytes 3 CSIZE_8KB Data cache size is 8 Kbytes • CLSIZE: Cache LIne Size Value Name 0 CLSIZE_1KB Cache line size is 4 bytes 1 CLSIZE_2KB Cache line size is 8 bytes 2 CLSIZE_4KB Cache line size is 16 bytes 3 CLSIZE_8KB Cache line size is 32 bytes 390 Description SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 22.5.2 Cache Controller Configuration Register Name: CMCC_CFG Address: 0x4007C004 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 GCLKDIS • GCLKDIS: Disable Clock Gating 0: Clock gating is activated. 1: Clock gating is disabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 391 22.5.3 Cache Controller Control Register Name: CMCC_CTRL Address: 0x4007C008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CEN • CEN: Cache Controller Enable 0: The cache controller is disabled. 1: The cache controller is enabled. 392 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 22.5.4 Cache Controller Status Register Name: CMCC_SR Address: 0x4007C00C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CSTS • CSTS: Cache Controller Status 0: The cache controller is disabled. 1: The cache controller is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 393 22.5.5 Cache Controller Maintenance Register 0 Name: CMCC_MAINT0 Address: 0x4007C020 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INVALL • INVALL: Cache Controller Invalidate All 0: No effect. 1: All cache entries are invalidated. 394 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 22.5.6 Cache Controller Maintenance Register 1 Name: CMCC_MAINT1 Address: 0x4007C024 Access: Write-only 31 30 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 INDEX 7 6 5 4 3 – 2 – 1 – 0 – WAY INDEX • INDEX: Invalidate Index This field indicates the cache line that is being invalidated. The size of the INDEX field depends on the cache size: For example: – for 2 Kbytes: 5 bits – for 4 Kbytes: 6 bits – for 8 Kbytes: 7 bits • WAY: Invalidate Way Value Name Description 0 WAY0 Way 0 is selection for index invalidation 1 WAY1 Way 1 is selection for index invalidation 2 WAY2 Way 2 is selection for index invalidation 3 WAY3 Way 3 is selection for index invalidation SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 395 22.5.7 Cache Controller Monitor Configuration Register Name: CMCC_MCFG Address: 0x4007C028 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 • MODE: Cache Controller Monitor Counter Mode Value Name 0 CYCLE_COUNT 1 IHIT_COUNT Instruction hit counter 2 DHIT_COUNT Data hit counter 396 Description Cycle counter SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 0 MODE 22.5.8 Cache Controller Monitor Enable Register Name: CMCC_MEN Address: 0x4007C02C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MENABLE • MENABLE: Cache Controller Monitor Enable 0: The monitor counter is disabled. 1: The monitor counter is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 397 22.5.9 Cache Controller Monitor Control Register Name: CMCC_MCTRL Address: 0x4007C030 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST • SWRST: Monitor 0: No effect. 1: Resets the event counter register. 398 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 22.5.10 Cache Controller Monitor Status Register Name: CMCC_MSR Address: 0x4007C034 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EVENT_CNT 23 22 21 20 EVENT_CNT 15 14 13 12 EVENT_CNT 7 6 5 4 EVENT_CNT • EVENT_CNT: Monitor Event Counter SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 399 23. Cyclic Redundancy Check Calculation Unit (CRCCU) 23.1 Description The Cyclic Redundancy Check Calculation Unit (CRCCU) has its own DMA which functions as a Master with the Bus Matrix. Three different polynomials are available: CCITT802.3, CASTAGNOLI and CCITT16. The CRCCU is designed to perform data integrity checks of off-/on-chip memories as a background task without CPU intervention. 23.2 Embedded Characteristics  Data Integrity Check of Off-/On-Chip Memories  Background Task Without CPU Intervention  Performs Cyclic Redundancy Check (CRC) Operation on Programmable Memory Area  Programmable Bus Burden Note: 400 The CRCCU is designed to verify data integrity of off-/on-chip memories, thus the CRC must be generated and verified by the CRCCU. The CRCCU performs the CRC from LSB to MSB. If the CRC has been performed with the same polynomial by another device, a bit-reverse must be done on each byte before using the CRCCU. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 23.3 CRCCU Block Diagram Figure 23-1. Block Diagram Host Interface APB Bus Context FSM TR_CRC TR_ADDR HRDATA AHB Interface HTRANS HSIZE AHB-Layer External Bus Interface Flash AHB SRAM SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 401 23.4 Product Dependencies 23.4.1 Power Management The CRCCU is clocked through the Power Management Controller (PMC), the programmer must first configure the CRCCU in the PMC to enable the CRCCU clock. 23.4.2 Interrupt Source The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU interrupt requires programming the Interrupt Controller before configuring the CRCCU. 402 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 23.5 CRCCU Functional Description 23.5.1 CRC Calculation Unit The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured and activated, this CRC engine performs a checksum computation on a memory area. CRC computation is performed from the LSB to MSB. Three different polynomials are available: CCITT802.3, CASTAGNOLI and CCITT16 (see field description “PTYPE: Primitive Polynomial” in Section 23.7.10 “CRCCU Mode Register” for details). 23.5.2 CRC Calculation Unit Operation The CRCCU has a DMA controller that supports programmable CRC memory checks. When enabled, the DMA channel reads a programmable amount of data and computes CRC on the fly. The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL, which need to be mapped in the internal SRAM. The addresses of these two registers are pointed to by the CRCCU_DSCR. Table 23-1. CRCCU Descriptor Memory Mapping SRAM Memory CRCCU_DSCR+0x0 ----> TR_ADDR CRCCU_DSCR+0x4 ----> TR_CTRL CRCCU_DSCR+0x8 ----> Reserved CRCCU_DSCR+0xC ----> Reserved CRCCU_DSCR+0x10 ----> TR_CRC TR_ADDR defines the start address of memory area targeted for CRC calculation. TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the transfer-completed interrupt enable. To start the CRCCU, set the CRC enable bit (ENABLE) and configure the mode of operation in the CRCCU Mode Register (CRCCU_MR), then configure the Transfer Control Registers and finally, set the DMA enable bit (DMAEN) in the CRCCU DMA Enable Register (CRCCU_DMA_EN). When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in TR_CTRL) located from TR_ADDR start address and computes the checksum. The CRCCU_SR contains the temporary CRC value. The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decremented if its value is different from zero. Once the value of the BTSIZE field is equal to zero, the CRCCU is disabled by hardware. In this case, the relevant CRCCU DMA Status Register bit DMASR is automatically cleared. If the COMPARE field of the CRCCU_MR is set to true, the TR_CRC (Transfer Reference Register) is compared with the last CRC computed. If a mismatch occurs, an error flag is set and an interrupt is raised (if unmasked). The CRCCU accesses the memory by single access (TRWIDTH size) in order not to limit the bandwidth usage of the system, but the DIVIDER field of the CRCCU Mode Register can be used to lower it by dividing the frequency of the single accesses. The CRCCU scrolls the defined memory area using ascending addresses. In order to compute the CRC for a memory size larger than 256 Kbytes or for non-contiguous memory area, it is possible to re-enable the CRCCU on the new memory area and the CRC will be updated accordingly. Use the RESET field of the CRCCU_CR to reset the CRCCU Status Register to its default value (0xFFFFFFFF). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 403 23.6 Transfer Control Registers Memory Mapping Table 23-2. Transfer Control Register Memory Mapping Offset Register Name Access Reset CRCCU_DSCR + 0x0 CRCCU Transfer Address Register TR_ADDR Read/Write 0x00000000 CRCCU_DSCR + 0x4 CRCCU Transfer Control Register TR_CTRL Read/Write 0x00000000 CRCCU_DSCR + 0xC–0x10 Reserved – – – CRCCU_DSCR+0x10 CRCCU Transfer Reference Register TR_CRC Read/Write 0x00000000 Note: These registers are memory mapped. 404 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 23.6.1 Transfer Address Register Name: TR_ADDR Access: Read/Write 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: Transfer Address SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 405 23.6.2 Transfer Control Register Name: TR_CTRL Access: Read/Write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 IEN 19 – 11 26 – 18 – 10 25 24 17 – 9 16 – 8 3 2 1 0 TRWIDTH BTSIZE BTSIZE • BTSIZE: Buffer Transfer Size • TRWIDTH: Transfer Width Register Value Name Description 0 BYTE The data size is 8-bit 1 HALFWORD The data size is 16-bit 2 WORD The data size is 32-bit • IEN: Context Done Interrupt Enable (Active Low) 0: Bit DMAISR of CRCCU_DMA_ISR is set at the end of the current descriptor transfer. 1: Bit DMAISR of CRCCU_DMA_ISR remains cleared. 406 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 23.6.3 Transfer Reference Register Name: TR_CRC Access: Read/Write 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 REFCRC REFCRC 15 14 13 12 7 6 5 4 REFCRC REFCRC • REFCRC: Reference CRC When Compare mode is enabled, the checksum is compared with this field. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 407 23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface Table 23-3. Register Mapping Offset Register 0x000 CRCCU Descriptor Base Register 0x004 Reserved 0x008 CRCCU DMA Enable Register CRCCU_DMA_EN Write-only – 0x00C CRCCU DMA Disable Register CRCCU_DMA_DIS Write-only – 0x010 CRCCU DMA Status Register CRCCU_DMA_SR Read-only 0x014 CRCCU DMA Interrupt Enable Register CRCCU_DMA_IER Write-only – 0x018 CRCCU DMA Interrupt Disable Register CRCCU_DMA_IDR Write-only – 0x001C CRCCU DMA Interrupt Mask Register CRCCU_DMA_IMR Read-only 0x00000000 0x020 CRCCU DMA Interrupt Status Register CRCCU_DMA_ISR Read-only 0x00000000 – – 0x024–0x030 Reserved Name CRCCU_DSCR – Access Read/Write 0x00000000 – – Reset – 0x00000000 0x034 CRCCU Control Register CRCCU_CR Write-only – 0x038 CRCCU Mode Register CRCCU_MR Read/Write 0x00000000 0x03C CRCCU Status Register CRCCU_SR Read-only 0xFFFFFFFF 0x040 CRCCU Interrupt Enable Register CRCCU_IER Write-only – 0x044 CRCCU Interrupt Disable Register CRCCU_IDR Write-only – 0x048 CRCCU Interrupt Mask Register CRCCU_IMR Read-only 0x00000000 0x004C CRCCU Interrupt Status Register CRCCU_ISR Read-only 0x00000000 – – 0x050–0x0FC Reserved 408 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 – 23.7.1 CRCCU Descriptor Base Address Register Name: CRCCU_DSCR Address: 0x40044000 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 3 – 2 – 1 – 8 – 0 – DSCR 23 22 21 20 DSCR 15 14 13 7 – 6 – 5 – 12 DSCR 4 – • DSCR: Descriptor Base Address DSCR needs to be aligned with 512-byte boundaries. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 409 23.7.2 CRCCU DMA Enable Register Name: CRCCU_DMA_EN Address: 0x40044008 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • DMAEN: DMA Enable 0: No effect 1: Enable CRCCU DMA channel 410 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAEN 23.7.3 CRCCU DMA Disable Register Name: CRCCU_DMA_DIS Address: 0x4004400C Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMADIS • DMADIS: DMA Disable 0: No effect 1: Disable CRCCU DMA channel SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 411 23.7.4 CRCCU DMA Status Register Name: CRCCU_DMA_SR Address: 0x40044010 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • DMASR: DMA Status 0: DMA channel disabled 1: DMA channel enabled 412 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMASR 23.7.5 CRCCU DMA Interrupt Enable Register Name: CRCCU_DMA_IER Address: 0x40044014 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIER • DMAIER: Interrupt Enable 0: No effect 1: Enable interrupt SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 413 23.7.6 CRCCU DMA Interrupt Disable Register Name: CRCCU_DMA_IDR Address: 0x40044018 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • DMAIDR: Interrupt Disable 0: No effect 1: Disable interrupt 414 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIDR 23.7.7 CRCCU DMA Interrupt Mask Register Name: CRCCU_DMA_IMR Address: 0x4004401C Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAIMR • DMAIMR: Interrupt Mask 0: Buffer Transfer Completed interrupt disabled 1: Buffer Transfer Completed interrupt enabled SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 415 23.7.8 CRCCU DMA Interrupt Status Register Name: CRCCU_DMA_ISR Address: 0x40044020 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – • DMAISR: Interrupt Status 0: DMA buffer transfer has not yet started or transfer still in progress 1: DMA buffer transfer has terminated. This flag is reset after read. 416 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DMAISR 23.7.9 CRCCU Control Register Name: CRCCU_CR Address: 0x40044034 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RESET • RESET: CRC Computation Reset 0: No effect 1: Sets the CRCCU_SR to 0xFFFFFFFF SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 417 23.7.10 CRCCU Mode Register Name: CRCCU_MR Address: 0x40044038 Access: Read/Write 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 DIVIDER 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 PTYPE 25 – 17 – 9 – 1 COMPARE 24 – 16 – 8 – 0 ENABLE • ENABLE: CRC Enable Always write a 1 to this bit. • COMPARE: CRC Compare If set to one, this bit indicates that the CRCCU DMA will compare the CRC computed on the data stream with the value stored in the TR_CRC reference register. If a mismatch occurs, the ERRISR bit in the CRCCU_ISR is set. • PTYPE: Primitive Polynomial Value Name Description 0 CCITT8023 Polynom 0x04C11DB7 1 CASTAGNOLI Polynom 0x1EDC6F41 2 CCITT16 Polynom 0x1021 • DIVIDER: Request Divider CRCCU DMA performs successive transfers. It is possible to reduce the bandwidth drained by the CRCCU DMA by programming the DIVIDER field. The transfer request frequency is divided by 2^(DIVIDER+1). 418 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 23.7.11 CRCCU Status Register Name: CRCCU_SR Address: 0x4004403C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRC 23 22 21 20 CRC 15 14 13 12 CRC 7 6 5 4 CRC • CRC: Cyclic Redundancy Check Value This register can not be read if the COMPARE bit in the CRCCU_MR is set to true. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 419 23.7.12 CRCCU Interrupt Enable Register Name: CRCCU_IER Address: 0x40044040 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • ERRIER: CRC Error Interrupt Enable 0: No effect 1: Enable interrupt 420 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRIER 23.7.13 CRCCU Interrupt Disable Register Name: CRCCU_IDR Address: 0x40044044 Access: Write-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRIDR • ERRIDR: CRC Error Interrupt Disable 0: No effect 1: Disable interrupt SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 421 23.7.14 CRCCU Interrupt Mask Register Name: CRCCU_IMR Address: 0x40044048 Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – • ERRIMR: CRC Error Interrupt Mask 0: Interrupt disabled 1: Interrupt enabled 422 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRIMR 23.7.15 CRCCU Interrupt Status Register Name: CRCCU_ISR Address: 0x4004404C Access: Read-only 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ERRISR • ERRISR: CRC Error Interrupt Status 0: Interrupt disabled 1: Interrupt enabled SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 423 24. Boot Program 24.1 Description The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different memories of the product. 24.2 Hardware and Software Constraints  SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be used for user's code.  USB Requirements: ̶ External Crystal or External Clock(1) with frequency of: 11.289 MHz 12.000 MHz 16.000 MHz  Note: 18.432 MHz UART0 requirements: None 1. Table 24-1. 24.3 Must be 2500 ppm and 1.2V Square Wave Signal. Pins Driven during Boot Program Execution Peripheral Pin PIO Line UART0 URXD0 PA9 UART0 UTXD0 PA10 Flow Diagram The Boot Program implements the algorithm in Figure 24-1. Figure 24-1. Boot Program Algorithm Flow Diagram No Device Setup No USB Enumeration Successful ? Yes Run SAM-BA Monitor Character # received from UART0? Yes Run SAM-BA Monitor The SAM-BA Boot program seeks to detect a source clock either from the embedded main oscillator with external crystal (main oscillator enabled) or from a supported frequency signal applied to the XIN pin (main oscillator in Bypass mode). If a clock is found from the two possible sources above, the boot program checks to verify that the frequency is one of the supported external frequencies. If the frequency is one of the supported external frequencies, USB activation is allowed, else (no clock or frequency other than one of the supported external frequencies), the internal 12 MHz RC oscillator is used as main clock and USB clock is not allowed due to frequency drift of the 12 MHz RC oscillator. 424 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 24.4 Device Initialization Initialization follows the steps described below: 1. Stack setup 2. Set up the Embedded Flash Controller 3. External Clock detection (crystal or external clock on XIN) 4. If external crystal or clock with supported frequency, allow USB activation 5. Else, does not allow USB activation and use internal 12 MHz RC oscillator 6. Main oscillator frequency detection if no external clock detected 7. Switch Master Clock on Main Oscillator 8. C variable initialization 9. PLLA setup: PLLA is initialized to generate a 48 MHz clock 10. Disable the Watchdog 11. Initialization of UART0 (115200 bauds, 8, N, 1) 12. Initialization of the USB Device Port (in case USB activation allowed) 13. Wait for one of the following events 1. Check if USB device enumeration has occurred 2. Check if characters have been received in UART0 14. Jump to SAM-BA Monitor (see Section 24.5 ”SAM-BA Monitor”) SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 425 24.5 SAM-BA Monitor Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown in Table 24-2. Table 24-2. Commands Available through the SAM-BA Boot Command Argument(s) Example N Set Normal Mode No argument N# T Set Terminal Mode No argument T# O Write a Byte Address, Value# O200001,CA# o Read a Byte Address,# o200001,# H Write a Half Word Address, Value# H200002,CAFE# h Read a Half Word Address,# h200002,# W Write a Word Address, Value# W200000,CAFEDECA# w Read a Word Address,# w200000,# S Send a File Address,# S200000,# R Receive a File Address, NbOfBytes# R200000,1234# G Go Address# G200200# V Display Version No argument V#   Mode commands: ̶ Normal mode configures SAM-BA Monitor to send/receive data in binary format, ̶ Terminal mode configures SAM-BA Monitor to send/receive data in ascii format. Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. ̶ ̶ ̶    ̶ Address: Address in hexadecimal ̶ Output: The byte, halfword or word read in hexadecimal following by ‘>’ Send a file (S): Send a file to a specified address ̶ Address: Address in hexadecimal ̶ Output: ‘>’. There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. Receive a file (R): Receive data into a file from a specified address ̶ ̶  Value: Byte, halfword or word to write in hexadecimal. Output: ‘>’. ̶  Address: Address in hexadecimal. Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. Note: Address: Address in hexadecimal NbOfBytes: Number of bytes in hexadecimal to receive Output: ‘>’ Go (G): Jump to a specified address and execute the code ̶ Address: Address to jump in hexadecimal ̶ Output: ‘>’ Get Version (V): Return the SAM-BA boot version ̶ 426 Action Output: ‘>’ SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 24.5.1 UART0 Serial Port Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. See Section 24.2 ”Hardware and Software Constraints”. 24.5.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: ̶ = 01 hex ̶ = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) ̶ = 1’s complement of the blk#. ̶ = 2 bytes CRC16 Figure 24-2 shows a transmission using this protocol. Figure 24-2. Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 24.5.3 USB Device Port The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ® , beginning with Windows 98 SE. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID (VID) is Atmel’s vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 427 For more details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the USB Implementers Forum on www.usb.org. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the application note “USB Basic Application”, Atmel literature number 6123, for more details. 24.5.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 24-3. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value. GET_STATUS Returns status for the specified recipient. SET_FEATURE Set or Enable a specific feature. CLEAR_FEATURE Clear or Disable a specific feature. The device also handles some class requests defined in the CDC class. Table 24-4. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 24.5.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 428 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 24.5.4 In Application Programming (IAP) Feature The IAP feature is a function located in ROM that can be called by any software application. When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping while the FRDY bit is not set in the EEFC_FSR). Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code running in Flash. The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008). This function takes two arguments in parameter: the EFC number and the command to be sent to the EEFC. This function returns the value of the EEFC_FSR. IAP software code example: (unsigned int) (*IAP_Function)(unsigned long); void main (void){ unsigned unsigned unsigned unsigned long long long long FlashSectorNum = 200; // flash_cmd = 0; flash_status = 0; EFCIndex = 0; // 0:EEFC0, 1: EEFC1 /* Initialize the function pointer (retrieve function address from NMI vector) */ IAP_Function = ((unsigned long) (*)(unsigned long)) 0x00800008; /* Send your data to the sector here */ /* build the command to send to EEFC */ flash_cmd = (0x5A 1 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 36.6.1.3 Sampling Clock Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in Synchronous mode, the selected clock is simply divided by the field CD in the US_BRGR. SelectedClock BaudRate = -------------------------------------CD In Synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the system clock. In Synchronous mode master (USCLKS = 0 or 1, CLKO set to 1), the receive part limits the SCK maximum frequency tofperipheral clock/3 in USART mode, or fperipheral clock/6 in SPI mode. When either the external clock SCK or the internal clock divided (peripheral clock/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. When the peripheral clock is selected, the baud rate generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 785 36.6.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where:  B is the bit rate  Di is the bit-rate adjustment factor  Fi is the clock frequency division factor  f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 36-5. Table 36-5. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 36-6. Table 36-6. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 36-7 shows the resulting Fi/Di ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 36-7. Possible Values for the Fi/Di Ratio Fi/Di 372 558 744 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 If the USART is configured in ISO7816 mode, the clock selected by the USCLKS field in US_MR is first divided by the value programmed in the field CD in the US_BRGR. The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 36-4 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. 786 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 36-4. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 36.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the US_CR. However, the transmitter registers can be programmed before being enabled. The receiver and the transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the US_CR. The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in the US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding register (US_THR). If a timeguard is programmed, it is handled normally. 36.6.3 Synchronous and Asynchronous Modes 36.6.3.1 Transmitter Operations The transmitter performs the same in both Synchronous and Asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in US_MR. Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in the US_MR configures which data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in the US_MR. The 1.5 stop bit is supported in Asynchronous mode only. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 787 Figure 36-5. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding register (US_THR). The transmitter reports two status bits in the Channel Status register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 36-6. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 36.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN bit in the US_MR to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 36-7 illustrates this coding scheme. Figure 36-7. NRZ to Manchester Encoding NRZ encoded data 1 0 1 1 0 0 0 1 Manchester encoded Txd data The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a 788 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 36-8 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to 1, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. Figure 36-8. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA SFD DATA SFD DATA SFD DATA 8-bit width "ALL_ONE" Preamble Manchester encoded data Txd 8-bit width "ALL_ZERO" Preamble Manchester encoded data Txd 8-bit width "ZERO_ONE" Preamble Manchester encoded data Txd 8-bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT bit in the US_MR. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 36-9 illustrates these patterns. If the start frame delimiter, also known as the start bit, is one bit, (ONEBIT = 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONE BIT to 0), a sequence of three bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC bit in the US_MR is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC bit in US_MR must be set to 1. In this case, the MODSYNC bit in the US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR. The USART character format is modified and includes sync information. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 789 Figure 36-9. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. Figure 36-10. Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error 36.6.3.3 Synchro. Jump Tolerance Sync Jump Synchro. Error Asynchronous Receiver If the USART is programmed in Asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the baud rate clock, depending on the OVER bit in the US_MR. The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16 (OVER = 0), a start is detected at the eighth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration corresponding to 16 oversampling clock cycles. If the oversampling is 8 (OVER = 1), a start bit is detected at the fourth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration corresponding to 8 oversampling clock cycles. 790 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 The number of data bits, first bit sent and Parity mode are selected by the same fields and bits as the transmitter, i.e., respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 36-11 and Figure 36-12 illustrate start detection and character reception when USART operates in Asynchronous mode. Figure 36-11. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 7 0 1 Start Rejection Figure 36-12. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 36.6.3.4 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Manchester Decoder When the MAN bit in the US_MR is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL bit in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 36-8 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 791 to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 3613. The sample pulse rejection mechanism applies. Figure 36-13. Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver resynchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 36-14 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in the US_CSR is raised. It is cleared by writing a 1 to the RSTSTA in the US_CR. See Figure 36-15 for an example of Manchester error detection during data phase. Figure 36-14. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Manchester encoded data Preamble Mismatch invalid pattern SFD Txd DATA Preamble Length is set to 8 Figure 36-15. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded 792 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in Unipolar mode, the first bit of the frame has to be a zero-to-one transition. 36.6.3.5 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 36-16. Figure 36-16. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line Manchester decoder USART Receiver Manchester encoder USART Emitter ASK/FSK downstream transmitter Downstream Receiver PA RF filter Mod VCO control The USART peripheral is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 36-17 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 36-18. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to Receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 793 Figure 36-17. ASK Modulator Output 1 0 0 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd ASK Modulator Output Uptstream Frequency F0 Figure 36-18. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 36.6.3.6 Synchronous Receiver In Synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high-speed transfer capability. Configuration fields and bits are the same as in Asynchronous mode. Figure 36-19 illustrates a character reception in Synchronous mode. Figure 36-19. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 36.6.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the RXRDY bit in US_CSR rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in the US_CR. 794 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 36-20. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 36.6.3.8 Parity The USART supports five Parity modes that are selected by writing to the PAR field in the US_MR. The PAR field also enables the Multidrop mode, see Section 36.6.3.9 ”Multidrop Mode”. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 36-8 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits set to 1 in the character value, the parity bit is set to 1 when the parity is odd, or configured to 0 when the parity is even. Table 36-8. Parity Bit Examples Character Hexadecimal Binary Parity Bit Parity Mode A 0x41 0100 0001 1 Odd A 0x41 0100 0001 0 Even A 0x41 0100 0001 1 Mark A 0x41 0100 0001 0 Space A 0x41 0100 0001 None None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the US_CSR. The PARE bit can be cleared by writing a 1 to the RSTSTA bit the US_CR. Figure 36-21 illustrates the parity bit status setting and clearing. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 795 Figure 36-21. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE Parity Error Detect Time Flags Report Time RXRDY 36.6.3.9 Multidrop Mode If the value 0x6 or 0x07 is written to the PAR field in the US_MR, the USART runs in Multidrop mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in Multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when a 1 is written to the SENTA bit in the US_CR. To handle parity error, the PARE bit is cleared when a 1 is written to the RSTSTA bit in the US_CR. The transmitter sends an address byte (parity bit set) when SENDA is written to in the US_CR. In this case, the next byte written to the US_THR is transmitted as an address. Any character written in the US_THR without having written the command SENDA is transmitted normally with the parity at 0. 36.6.3.10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard register (US_TTGR). When this field is written to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 36-22, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 796 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 36-22. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 36-9 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. Table 36-9. 36.6.3.11 Maximum Timeguard Length Depending on Baud Rate Baud Rate (bit/s) Bit Time (µs) Timeguard (ms) 1,200 833 212.50 9,600 104 26.56 14,400 69.4 17.71 19,200 52.1 13.28 28,800 34.7 8.85 38,400 26 6.63 56,000 17.9 4.55 57,600 17.4 4.43 115,200 8.7 2.21 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the US_CSR rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out register (US_RTOR). If the TO field is written to 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in the US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in US_CSR rises. Then, the user can either:  Stop the counter clock until a new character is received. This is performed by writing a 1 to the STTTO (Start Time-out) bit in the US_CR. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received.  Obtain an interrupt while no character is received. This is performed by writing a 1 to the RETTO (Reload and Start Time-out) bit in the US_CR. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 797 If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 36-23 shows the block diagram of the Receiver Time-out feature. Figure 36-23. Receiver Time-out Block Diagram TO Baud Rate Clock 1 D Clock Q 16-bit Time-out Counter 16-bit Value = STTTO Character Received RETTO Load Clear TIMEOUT 0 Table 36-10 gives the maximum time-out period for some standard baud rates. Table 36-10. 36.6.3.12 Maximum Time-out Period Baud Rate (bit/s) Bit Time (µs) Time-out (ms) 600 1,667 109,225 1,200 833 54,613 2,400 417 27,306 4,800 208 13,653 9,600 104 6,827 14,400 69 4,551 19,200 52 3,413 28,800 35 2,276 38,400 26 1,704 56,000 18 1,170 57,600 17 1,138 200,000 5 328 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of US_CSR. The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing a 1 to the RSTSTA bit in the US_CR. 798 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 36-24. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 36.6.3.13 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing a 1 to the STTBRK bit in the US_CR. This can be performed at any time, either while the transmitter is empty (no character in either the Shift register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing a 1 to the STPBRK bit in the US_CR. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e., the STTBRK and STPBRK commands are processed only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with both STTBRK and STPBRK bits to 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 36-25 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 799 Figure 36-25. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 36.6.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing a 1 to the RSTSTA bit in the US_CR. An end of receive break is detected by a high level for at least 2/16 of a bit period in Asynchronous operating mode or one sample at high level in Synchronous operating mode. The end of break detection also asserts the RXBRK bit. 36.6.3.15 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 36-26. Figure 36-26. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in US_MR to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard Synchronous or Asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 36-27 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled or if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer in the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. 800 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 36-27. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 36-28 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processed, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 36-28. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 36.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in US_MR to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 36.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see Section 36-2 ”Baud Rate Generator”). The USART connects to a smart card as shown in Figure 36-29. The TXD line becomes bidirectional and the baud rate generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 36-29. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to Section 36.7.3 ”USART Mode Register” and “PAR: Parity Type” . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 801 The USART cannot operate concurrently in both Receiver and Transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. 36.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 36-30. If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 3631. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding register (US_RHR). It appropriately sets the PARE bit in the Status register (US_SR) so that the software can handle the error. Figure 36-30. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 36-31. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in US_MR. If INACK is to 1, no error signal is driven on the I/O line even if a parity bit is detected. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding register, as if no error occurred and the RXRDY bit does rise. 802 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the US_MR at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION and the last repeated character is not acknowledged, the ITER bit is set in US_CSR. If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITER bit in US_CSR can be cleared by writing a 1 to the RSTIT bit in the US_CR. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the US_MR. The maximum number of NACKs transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, no error signal is driven on the I/O line and the ITER bit in the US_CSR is set. 36.6.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the US_CSR. 36.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 36-32. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 kbit/s to 115.2 kbit/s. The IrDA mode is enabled by setting the USART_MODE field in US_MR to the value 0x8. The IrDA Filter register (US_IF) is used to configure the demodulator filter. The USART transmitter and receiver operate in a normal Asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 36-32. Connection to IrDA Transceivers USART IrDA Transceivers Receiver Demodulator Transmitter Modulator RXD RX TX TXD The receiver and the transmitter must be enabled or disabled depending on the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done:  Disable TX and Enable RX  Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pullup (better for power consumption). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 803  36.6.5.1 Receive data IrDA Modulation For baud rates up to and including 115.2 kbit/s, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 36-11. Table 36-11. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 kbit/s 78.13 µs 9.6 kbit/s 19.53 µs 19.2 kbit/s 9.77 µs 38.4 kbit/s 4.88 µs 57.6 kbit/s 3.26 µs 115.2 kbit/s 1.63 µs Figure 36-33 shows an example of character transmission. Figure 36-33. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 0 1 1 0 0 1 1 0 1 TXD Bit Period 36.6.5.2 3/16 Bit Period IrDA Baud Rate Table 36-12 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 36-12. IrDA Baud Rate Error Peripheral Clock 804 Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3,686,400 115,200 2 0.00% 1.63 20,000,000 115,200 11 1.38% 1.63 32,768,000 115,200 18 1.25% 1.63 40,000,000 115,200 22 1.38% 1.63 3,686,400 57,600 4 0.00% 3.26 20,000,000 57,600 22 1.38% 3.26 32,768,000 57,600 36 1.25% 3.26 40,000,000 57,600 43 0.93% 3.26 3,686,400 38,400 6 0.00% 4.88 20,000,000 38,400 33 1.38% 4.88 32,768,000 38,400 53 0.63% 4.88 40,000,000 38,400 65 0.16% 4.88 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 36-12. IrDA Baud Rate Error (Continued) Peripheral Clock 36.6.5.3 Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3,686,400 19,200 12 0.00% 9.77 20,000,000 19,200 65 0.16% 9.77 32,768,000 19,200 107 0.31% 9.77 40,000,000 19,200 130 0.16% 9.77 3,686,400 9,600 24 0.00% 19.53 20,000,000 9,600 130 0.16% 19.53 32,768,000 9,600 213 0.16% 19.53 40,000,000 9,600 260 0.16% 19.53 3,686,400 2,400 96 0.00% 78.13 20,000,000 2,400 521 0.03% 78.13 32,768,000 2,400 853 0.04% 78.13 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the peripheral clock speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 36-34 illustrates the operations of the IrDA demodulator. Figure 36-34. IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 5 4 3 Pulse Rejected 2 6 6 5 4 3 2 1 0 Pulse Accepted The programmed value in the US_IF register must always meet the following criteria: tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to make sure IrDA communications operate correctly. 36.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in Asynchronous or Synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to an RS485 bus is shown in Figure 36-35. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 805 Figure 36-35. Typical Connection to a RS485 Bus USART RXD Differential Bus TXD RTS The USART is set in RS485 mode by writing the value 0x1 to the USART_MODE field in US_MR. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 36-36 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 36-36. Example of RTS Drive with Timeguard TG = 4 1 Baud Rate Clock TXD Start D0 Bit RTS Write US_THR TXRDY TXEMPTY 806 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit 36.6.7 Modem Mode The USART features Modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in Modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in Modem mode is performed by writing the USART_MODE field in US_MR to the value 0x3. While operating in Modem mode, the USART behaves as though in Asynchronous mode and all the parameter configurations are available. Table 36-13 gives the correspondence of the USART signals with modem connection standards. Table 36-13. Circuit References USART Pin V24 CCITT Direction TXD 2 103 From terminal to modem RTS 4 105 From terminal to modem DTR 20 108.2 From terminal to modem RXD 3 104 From modem to terminal CTS 5 106 From terminal to modem DSR 6 107 From terminal to modem DCD 8 109 From terminal to modem RI 22 125 From terminal to modem The control of the DTR output pin is performed by writing a 1 to the DTRDIS and DTREN bits respectively in US_CR. The disable command forces the corresponding pin to its inactive level, i.e., high. The enable command forces the corresponding pin to its active level, i.e., low. The RTS output pin is automatically controlled in this mode. The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in US_CSR are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 807 36.6.8 SPI Mode The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one master may simultaneously shift data into multiple slaves. (Multiple master protocol is the opposite of single master protocol, where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address only one SPI slave because it can generate only one NSS signal. The SPI system consists of two data lines and two control lines:  Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the slave.  Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.  Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.  Slave Select (NSS): This control line allows the master to select or deselect the slave. 36.6.8.1 Modes of Operation The USART can operate in SPI Master mode or in SPI Slave mode. Operation in SPI Master mode is programmed by writing 0xE to the USART_MODE field in US_MR. In this case the SPI lines must be connected as described below:  The MOSI line is driven by the output pin TXD  The MISO line drives the input pin RXD  The SCK line is driven by the output pin SCK  The NSS line is driven by the output pin RTS Operation in SPI Slave mode is programmed by writing to 0xF the USART_MODE field in US_MR. In this case the SPI lines must be connected as described below:  The MOSI line drives the input pin RXD  The MISO line is driven by the output pin TXD  The SCK line drives the input pin SCK  The NSS line drives the input pin CTS In order to avoid unpredictable behavior, any change of the SPI mode must be followed by a software reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (See Section 36.6.8.4). 36.6.8.2 Baud Rate In SPI mode, the baud rate generator operates in the same way as in USART Synchronous mode. See Section 36.6.1.3 ”Baud Rate in Synchronous Mode or SPI Mode”. However, there are some restrictions: In SPI Master mode: 808  The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to 1 in the US_MR, in order to generate correctly the serial clock on the SCK pin.  To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior or equal to 6. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15  If the divided peripheral clock is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the SCK pin, this value can be odd if the peripheral clock is selected. In SPI Slave mode: 36.6.8.3  The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the US_MR. Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART SCK pin.  To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least 6 times lower than the system clock. Data Transfer Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the US_MR. The nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI mode (Master or Slave). Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the US_MR. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 36-14. SPI Bus Protocol Mode SPI Bus Protocol Mode CPOL CPHA 0 0 1 1 0 0 2 1 1 3 1 0 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 809 Figure 36-37. SPI Transfer Format (CPHA = 1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master -> RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB 7 8 NSS SPI Master -> RTS SPI Slave -> CTS Figure 36-38. SPI Transfer Format (CPHA = 0, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 5 6 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 36.6.8.4 Receiver and Transmitter Control See Section 36.6.2 ”Receiver and Transmitter Control” 36.6.8.5 Character Transmission The characters are sent by writing in the Transmit Holding register (US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI Master mode. In the USART Mode Register (SPI_MODE) (USART_MR), the value configured on the bit WRDBT can prevent any character 810 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 transmission (even if US_THR has been written) while the receiver side is not ready (character not read). When WRDBT equals 0, the character is transmitted whatever the receiver status. If WRDBT is set to 1, the transmitter waits for the Receive Holding register (US_RHR) to be read before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side. The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave mode and if a character must be sent while the US_THR is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in US_CR. In SPI Master mode, the slave select line (NSS) is asserted at low level one tbit (tbit being the nominal time required to transmit a bit) before the transmission of the MSB bit and released at high level one tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of three tbit always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing a 1 to the RTSEN bit in the US_CR. The slave select line (NSS) can be released at high level only by writing a 1 to the RTSDIS bit in the US_CR (for example, when all data have been transferred to the slave device). In SPI Slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least one tbit before the first serial clock cycle corresponding to the MSB bit. 36.6.8.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and the RXRDY bit in the Status register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in the US_CR. To ensure correct behavior of the receiver in SPI Slave mode, the master device sending the frame must ensure a minimum delay of one tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least one tbit before the first serial clock cycle corresponding to the MSB bit. 36.6.8.7 Receiver Timeout Because the receiver baud rate clock is active only during data transfers in SPI mode, a receiver timeout is impossible in this mode, whatever the time-out value is (field TO) in the US_RTOR. 36.6.9 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In Loopback mode, the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 36.6.9.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 811 Figure 36-39. Normal Mode Configuration RXD Receiver TXD Transmitter 36.6.9.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 36-40. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 36-40. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 36.6.9.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 36-41. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 36-41. Local Loopback Mode Configuration RXD Receiver 1 Transmitter 36.6.9.4 TXD Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 36-42. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 36-42. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 812 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.6.10 Register Write Protection To prevent any single software error from corrupting USART behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the USART Write Protection Mode Register (US_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the USART Write Protection Status Register (US_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the US_WPSR. The following registers can be write-protected:  USART Mode Register  USART Baud Rate Generator Register  USART Receiver Time-out Register  USART Transmitter Timeguard Register  USART FI DI RATIO Register  USART IrDA Filter Register  USART Manchester Configuration Register SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 813 36.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 36-15. Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read/Write 0x0 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only – 0x0010 Interrupt Mask Register US_IMR Read-only 0x0 0x0014 Channel Status Register US_CSR Read-only 0x0 0x0018 Receive Holding Register US_RHR Read-only 0x0 0x001C Transmit Holding Register US_THR Write-only – 0x0020 Baud Rate Generator Register US_BRGR Read/Write 0x0 0x0024 Receiver Time-out Register US_RTOR Read/Write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read/Write 0x0 Reserved – – – 0x0040 FI DI Ratio Register US_FIDI Read/Write 0x174 0x0044 Number of Errors Register US_NER Read-only 0x0 0x0048 Reserved – – – 0x004C IrDA Filter Register US_IF Read/Write 0x0 0x0050 Manchester Configuration Register US_MAN Read/Write 0x30011004 0x0054–0x005C Reserved – – – 0x0060–0x00E0 Reserved – – – 0x00E4 Write Protection Mode Register US_WPMR Read/Write 0x0 0x00E8 Write Protection Status Register US_WPSR Read-only 0x0 0x00EC–0x00FC Reserved – – – 0x0100–0x0128 Reserved for PDC Registers – – – 0x002C–0x003C 814 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.1 USART Control Register Name: US_CR Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see Section 36.7.2 ”USART Control Register (SPI_MODE)”. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 815 • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Clear TIMEOUT Flag and Start Time-out After Next Character Received 0: No effect. 1: Starts waiting for a character before enabling the time-out counter. Immediately disables a time-out period in progress. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITER in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Start Time-out Immediately 0: No effect 1: Immediately restarts time-out period. • DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR to 0. • DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. • RTSEN: Request to Send Pin Control 0: No effect. 1: Drives RTS pin to 0 if US_MR.USART_MODE field = 0. • RTSDIS: Request to Send Pin Control 0: No effect. 1: Drives RTS pin to 1 if US_MR.USART_MODE field = 0. 816 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0x40024000 (0), 0x40028000 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits OVRE, UNRE in US_CSR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 817 • FCS: Force SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect. 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI slave devices supporting the CSAAT mode (Chip Select Active After Transfer). • RCS: Release SPI Chip Select Applicable if USART operates in SPI master mode (USART_MODE = 0xE): 0: No effect. 1: Releases the Slave Select Line NSS (RTS pin). 818 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.3 USART Mode Register Name: US_MR Address: 0x40024004 (0), 0x40028004 (1) Access: Read/Write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. For SPI configuration, see Section 36.7.4 ”USART Mode Register (SPI_MODE)”. • USART_MODE: USART Mode of Operation Value Name Description 0x0 NORMAL Normal mode 0x1 RS485 0x2 HW_HANDSHAKING 0x3 MODEM 0x4 IS07816_T_0 IS07816 Protocol: T = 0 0x6 IS07816_T_1 IS07816 Protocol: T = 1 0x8 IRDA 0xE SPI_MASTER SPI master 0xF SPI_SLAVE SPI Slave RS485 Hardware Handshaking Modem IrDA The PDC transfers are supported in all USART modes of operation. • USCLKS: Clock Selection Value Name Description 0 MCK Peripheral clock is selected 1 DIV Peripheral clock divided (DIV=8) is selected 2 — 3 SCK Reserved Serial clock (SCK) is selected SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 819 • CHRL: Character Length Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous mode. 1: USART operates in Synchronous mode. • PAR: Parity Type Value Name Description 0 EVEN Even parity 1 ODD Odd parity 2 SPACE Parity forced to 0 (Space) 3 MARK Parity forced to 1 (Mark) 4 NO 6 MULTIDROP No parity Multidrop mode • NBSTOP: Number of Stop Bits Value Name Description 0 1_BIT 1 stop bit 1 1_5_BIT 2 2_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 2 stop bits • CHMODE: Channel Mode Value Name Description 0 NORMAL Normal mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK • MSBF: Bit Order 0: Least significant bit is sent/received first. 1: Most significant bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length 1: 9-bit character length 820 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16 × Oversampling 1: 8 × Oversampling • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITER is asserted. Note: MAX_ITERATION field must be set to 0 if DSNACK is cleared. • INVDATA: Inverted Data 0: The data field transmitted on TXD line is the same as the one written in US_THR or the content read in US_RHR is the same as RXD line. Normal mode of operation. 1: The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted mode of operation, useful for contactless card application. To be used with configuration bit MSBF. • VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on MODSYNC value. 1: The sync field is updated when a character is written into US_THR. • MAX_ITERATION: Maximum Number of Automatic Iteration 0–7: Defines the maximum number of iterations in mode ISO7816, protocol T = 0. • FILTER: Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). • MAN: Manchester Encoder/Decoder Enable 0: Manchester encoder/decoder are disabled. 1: Manchester encoder/decoder are enabled. • MODSYNC: Manchester Synchronization Mode 0:The Manchester start bit is a 0 to 1 transition 1: The Manchester start bit is a 1 to 0 transition. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 821 • ONEBIT: Start Frame Delimiter Selector 0: Start frame delimiter is COMMAND or DATA SYNC. 1: Start frame delimiter is one bit. 822 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0x40024004 (0), 0x40028004 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 – 18 CLKO 17 – 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 6 5 4 3 2 1 0 7 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • USART_MODE: USART Mode of Operation Value Name Description 0xE SPI_MASTER SPI master 0xF SPI_SLAVE SPI Slave • USCLKS: Clock Selection Value Name Description 0 MCK Peripheral clock is selected 1 DIV Peripheral clock divided (DIV=8) is selected 3 SCK Serial Clock SLK is selected • CHRL: Character Length Value Name Description 3 8_BIT Character length is 8 bits • CPHA: SPI Clock Phase – Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF): 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: SPI Clock Polarity Applicable if USART operates in SPI mode (slave or master, USART_MODE = 0xE or 0xF): 0: The inactive state value of SPCK is logic level zero. 1: The inactive state value of SPCK is logic level one. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 823 CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • WRDBT: Wait Read Data Before Transfer 0: The character transmission starts as soon as a character is written into US_THR (assuming TXRDY was set). 1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receive Holding Register has been read). 824 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.5 USART Interrupt Enable Register Name: US_IER Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 36.7.6 ”USART Interrupt Enable Register (SPI_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable (available in all USART modes of operation) • ENDTX: End of Transmit Buffer Interrupt Enable (available in all USART modes of operation) • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITER: Max number of Repetitions Reached Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation) • RXBUFF: Receive Buffer Full Interrupt Enable (available in all USART modes of operation) • NACK: Non Acknowledge Interrupt Enable • RIIC: Ring Indicator Input Change Enable SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 825 • DSRIC: Data Set Ready Input Change Enable • DCDIC: Data Carrier Detect Input Change Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable 826 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0x40024008 (0), 0x40028008 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • OVRE: Overrun Error Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • UNRE: SPI Underrun Error Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 827 36.7.7 USART Interrupt Disable Register Name: US_IDR Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 36.7.8 ”USART Interrupt Disable Register (SPI_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation) • ENDTX: End of Transmit Buffer Interrupt Disable (available in all USART modes of operation) • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITER: Max Number of Repetitions Reached Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation) • RXBUFF: Receive Buffer Full Interrupt Disable (available in all USART modes of operation) • NACK: Non Acknowledge Interrupt Disable • RIIC: Ring Indicator Input Change Disable 828 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • DSRIC: Data Set Ready Input Change Disable • DCDIC: Data Carrier Detect Input Change Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 829 36.7.8 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0x4002400C (0), 0x4002800C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • ENDRX: End of Receive Buffer Transfer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • OVRE: Overrun Error Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • UNRE: SPI Underrun Error Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable 830 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.9 USART Interrupt Mask Register Name: US_IMR Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 36.7.10 ”USART Interrupt Mask Register (SPI_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask (available in all USART modes of operation) • ENDTX: End of Transmit Buffer Interrupt Mask (available in all USART modes of operation) • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITER: Max Number of Repetitions Reached Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation) • RXBUFF: Receive Buffer Full Interrupt Mask (available in all USART modes of operation) • NACK: Non Acknowledge Interrupt Mask • RIIC: Ring Indicator Input Change Mask SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 831 • DSRIC: Data Set Ready Input Change Mask • DCDIC: Data Carrier Detect Input Change Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask 832 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.10 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0x40024010 (0), 0x40028010 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • OVRE: Overrun Error Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • UNRE: SPI Underrun Error Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 833 36.7.11 USART Channel Status Register Name: US_CSR Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see Section 36.7.12 ”USART Channel Status Register (SPI_MODE)”. • RXRDY: Receiver Ready (cleared by reading US_RHR) 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready (cleared by writing US_THR) 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the trTable 36-15 “Register Mapping”ansmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 0: No break received or end of break detected since the last RSTSTA. 1: Break received or end of break detected since the last RSTSTA. • ENDRX: End of RX Buffer (cleared by writing US_RCR or US_RNCR) 0: The Receive Counter Register has not reached 0 since the last write in US_RCR or US_RNCR(1). 1: The Receive Counter Register has reached 0 since the last write in US_RCR or US_RNCR(1). • ENDTX: End of TX Buffer (cleared by writing US_TCR or US_TNCR) 0: The Transmit Counter Register has not reached 0 since the last write in US_TCR or US_TNCR(1). 1: The Transmit Counter Register has reached 0 since the last write in US_TCR or US_TNCR(1). • OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. 834 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • FRAME: Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty (cleared by writing US_THR) 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 0: Maximum number of repetitions has not been reached since the last RSTIT. 1: Maximum number of repetitions has been reached since the last RSTIT. • TXBUFE: TX Buffer Empty (cleared by writing US_TCR or US_TNCR) 0: US_TCR or US_TNCR have a value other than 0(1). 1: Both US_TCR and US_TNCR have a value of 0(1). • RXBUFF: RX Buffer Full (cleared by writing US_RCR or US_RNCR) 0: US_RCR or US_RNCR have a value other than 0(1). 1: Both US_RCR and US_RNCR have a value of 0(1). Note: 1. US_RCR, US_RNCR, US_TCR and US_TNCR are PDC registers. • NACK: Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 0: Non acknowledge has not been detected since the last RSTNACK. 1: At least one non acknowledge has been detected since the last RSTNACK. • RIIC: Ring Indicator Input Change Flag (cleared on read) 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. • DSRIC: Data Set Ready Input Change Flag (cleared on read) 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. • DCDIC: Data Carrier Detect Input Change Flag (cleared on read) 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 835 • CTSIC: Clear to Send Input Change Flag (cleared on read) 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. • RI: Image of RI Input 0: RI input is driven low. 1: RI input is driven high. • DSR: Image of DSR Input 0: DSR input is driven low. 1: DSR input is driven high. • DCD: Image of DCD Input 0: DCD input is driven low. 1: DCD input is driven high. • CTS: Image of CTS Input 0: CTS input is driven low. 1: CTS input is driven high. • MANERR: Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. 836 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.12 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0x40024014 (0), 0x40028014 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 TXBUFE 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 ENDTX 3 ENDRX 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. • RXRDY: Receiver Ready (cleared by reading US_RHR) 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready (cleared by writing US_THR) 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • ENDRX: End of RX Buffer (cleared by writing US_RCR or US_RNCR) 0: The Receive Counter Register has not reached 0 since the last write in US_RCR or US_RNCR(1). 1: The Receive Counter Register has reached 0 since the last write in US_RCR or US_RNCR(1). • ENDTX: End of TX Buffer (cleared by writing US_TCR or US_TNCR) 0: The Transmit Counter Register has not reached 0 since the last write in US_TCR or US_TNCR(1). 1: The Transmit Counter Register has reached 0 since the last write in US_TCR or US_TNCR(1). • OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty (cleared by writing US_THR) 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 837 • UNRE: Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No SPI underrun error has occurred since the last RSTSTA. 1: At least one SPI underrun error has occurred since the last RSTSTA. • TXBUFE: TX Buffer Empty (cleared by writing US_TCR or US_TNCR) 0: US_TCR or US_TNCR have a value other than 0(1). 1: Both US_TCR and US_TNCR have a value of 0(1). • RXBUFF: RX Buffer Full (cleared by writing US_RCR or US_RNCR) 0: US_RCR or US_RNCR have a value other than 0(1). 1: Both US_RCR and US_RNCR have a value of 0(1). Note: 838 1. US_RCR, US_RNCR, US_TCR and US_TNCR are PDC registers. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.13 USART Receive Holding Register Name: US_RHR Address: 0x40024018 (0), 0x40028018 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last character received is a data. 1: Last character received is a command. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 839 36.7.14 USART Transmit Holding Register Name: US_THR Address: 0x4002401C (0), 0x4002801C (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be Transmitted 0: The next character sent is encoded as a data. Start frame delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start frame delimiter is COMMAND SYNC. 840 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.15 USART Baud Rate Generator Register Name: US_BRGR Address: 0x40024020 (0), 0x40028020 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 CD OVER = 0 OVER = 1 0 1 to 65535 SYNC = 1 or USART_MODE = SPI (Master or Slave) USART_MODE = ISO7816 Baud Rate Clock Disabled CD = Selected Clock / (16 × Baud Rate) CD = Selected Clock / (8 × Baud Rate) CD = Selected Clock / Baud Rate CD = Selected Clock / (FI_DI_RATIO × Baud Rate) • FP: Fractional Part 0: Fractional divider is disabled. 1–7: Baud rate resolution, defined by FP × 1/8. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 841 36.7.16 USART Receiver Time-out Register Name: US_RTOR Address: 0x40024024 (0), 0x40028024 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • TO: Time-out Value 0: The receiver time-out is disabled. 1–65535: The receiver time-out is enabled and TO is Time-out Delay / Bit Period. 842 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.17 USART Transmitter Timeguard Register Name: US_TTGR Address: 0x40024028 (0), 0x40028028 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • TG: Timeguard Value 0: The transmitter timeguard is disabled. 1–255: The transmitter timeguard is enabled and TG is Timeguard Delay / Bit Period. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 843 36.7.18 USART FI DI RATIO Register Name: US_FIDI Address: 0x40024040 (0), 0x40028040 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the baud rate generator generates no signal. 1–2: Do not use. 3–2047: If ISO7816 mode is selected, the baud rate is the clock provided on SCK divided by FI_DI_RATIO. 844 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.19 USART Number of Errors Register Name: US_NER Address: 0x40024044 (0), 0x40028044 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE = 0x4 or 0x6 in the USART Mode Register. • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 845 36.7.20 USART IrDA Filter Register Name: US_IF Address: 0x4002404C (0), 0x4002804C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE = 0x8 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • IRDA_FILTER: IrDA Filter The IRDA_FILTER value must be defined to meet the following criteria: tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs 846 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.21 USART Manchester Configuration Register Name: US_MAN Address: 0x40024050 (0), 0x40028050 (1) Access: Read/Write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 17 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • TX_PL: Transmitter Preamble Length 0: The transmitter preamble pattern generation is disabled 1–15: The preamble length is TX_PL × Bit Period • TX_PP: Transmitter Preamble Pattern The following values assume that TX_MPOL field is not set: Value Name Description 0 ALL_ONE The preamble is composed of ‘1’s 1 ALL_ZERO The preamble is composed of ‘0’s 2 ZERO_ONE The preamble is composed of ‘01’s 3 ONE_ZERO The preamble is composed of ‘10’s • TX_MPOL: Transmitter Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. • RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1–15: The detected preamble length is RX_PL × Bit Period SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 847 • RX_PP: Receiver Preamble Pattern detected The following values assume that RX_MPOL field is not set: Value Name Description 00 ALL_ONE The preamble is composed of ‘1’s 01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s • RX_MPOL: Receiver Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. • ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register. • DRIFT: Drift Compensation 0: The USART cannot recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. 848 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 36.7.22 USART Write Protection Mode Register Name: US_WPMR Address: 0x400240E4 (0), 0x400280E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). See Section 36.6.10 ”Register Write Protection” for the list of registers that can be write-protected. • WPKEY: Write Protection Key Value Name 0x555341 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 849 36.7.23 USART Write Protection Status Register Name: US_WPSR Address: 0x400240E8 (0), 0x400280E8 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the US_WPSR. 1: A write protection violation has occurred since the last read of the US_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. 850 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37. Timer Counter (TC) 37.1 Description A Timer Counter (TC) module includes three identical TC channels. The number of implemented TC modules is device-specific. Each TC channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The TC embeds a quadrature decoder (QDEC) connected in front of the timers and driven by TIOA0, TIOB0 and TIOB1 inputs. When enabled, the QDEC performs the input lines filtering, decoding of quadrature signals and connects to the timers/counters in order to read the position and speed of the motor through the user interface. The TC block has two global registers which act upon all TC channels: 37.2  Block Control Register (TC_BCR)—allows channels to be started simultaneously with the same instruction  Block Mode Register (TC_BMR)—defines the external clock inputs for each channel, allowing them to be chained Embedded Characteristics  Total number of TC channels: 6  TC channel size: 16-bit  Wide range of functions including:  ̶ Frequency measurement ̶ Event counting ̶ Interval measurement ̶ Pulse generation ̶ Delay timing ̶ Pulse Width Modulation ̶ Up/down capabilities ̶ Quadrature decoder ̶ 2-bit gray up/down count for stepper motor Each channel is user-configurable and contains: ̶ Three external clock inputs ̶ Five Internal clock inputs ̶ Two multi-purpose input/output signals acting as trigger event  Internal interrupt signal  Compare event fault generation for PWM  Register Write Protection SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 851 37.3 Block Diagram Table 37-1. Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 SLCK Note: Figure 37-1. 1. When SLCK is selected for Peripheral Clock (CSS = 0 in PMC Master Clock Register), SLCK input is equivalent to Peripheral Clock. Timer Counter Block Diagram Parallel I/O Controller TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIOA1 TIOA2 TIMER_CLOCK3 TCLK1 TIMER_CLOCK4 XC0 Timer/Counter Channel 0 XC1 TIOA TIOA0 TIOB0 TIOA0 TIOB TCLK2 TIOB0 XC2 TIMER_CLOCK5 TC0XC0S SYNC TCLK0 TCLK1 TCLK2 INT0 TCLK0 TCLK1 XC0 TIOA0 XC1 TIOA2 XC2 Timer/Counter Channel 1 TIOA TIOA1 TIOB1 TIOA1 TIOB TCLK2 TIOB1 SYNC TC1XC1S TCLK0 XC0 TCLK1 XC1 Timer/Counter Channel 2 INT1 TIOA TIOA2 TIOB2 TIOA2 TIOB TCLK2 XC2 TIOB2 TIOA0 TIOA1 SYNC TC2XC2S INT2 FAULT Timer Counter PWM Note: The QDEC connections are detailed in Figure 37-15. 852 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Interrupt Controller Table 37-2. Signal Description Block/Channel Signal Name Description XC0, XC1, XC2 Channel Signal External Clock Inputs TIOA Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT Interrupt Signal Output (internal signal) SYNC 37.4 Synchronization Input Signal (from configuration register) Pin List Table 37-3. Pin List Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O 37.5 Product Dependencies 37.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 37-4. I/O Lines Instance Signal I/O Line Peripheral TC0 TCLK0 PA4 B TC0 TCLK1 PA28 B TC0 TCLK2 PA29 B TC0 TIOA0 PA0 B TC0 TIOA1 PA15 B TC0 TIOA2 PA26 B TC0 TIOB0 PA1 B TC0 TIOB1 PA16 B TC0 TIOB2 PA27 B TC1 TCLK3 PC25 B TC1 TCLK4 PC28 B TC1 TCLK5 PC31 B TC1 TIOA3 PC23 B TC1 TIOA4 PC26 B TC1 TIOA5 PC29 B SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 853 Table 37-4. I/O Lines TC1 TIOB3 PC24 B TC1 TIOB4 PC27 B TC1 TIOB5 PC30 B 37.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock of each channel. 37.5.3 Interrupt Sources The TC has an interrupt line per channel connected to the interrupt controller. Handling the TC interrupt requires programming the interrupt controller before configuring the TC. Table 37-5. Peripheral IDs Instance ID TC0 23 TC1 24 37.5.4 Fault Output The TC has the FAULT output internally connected to the fault input of PWM. Refer to Section 37.6.16 “Fault Mode” and to the implementation of the Pulse Width Modulation (PWM) in this product. 37.6 Functional Description 37.6.1 Description All channels of the Timer Counter are independent and identical in operation except when the QDEC is enabled. The registers for channel programming are listed in Table 37-6 “Register Mapping”. 37.6.2 16-bit Counter Each 16-bit channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 216-1 and passes to zero, an overflow occurs and the COVFS bit in the TC Status Register (TC_SR) is set. The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock. 37.6.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC Block Mode Register (TC_BMR). See Figure 37-2. Each channel can independently select an internal or external clock source for its counter:  External clock signals(1): XC0, XC1 or XC2  Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, SLCK This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR). 854 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the TC_CMR defines this signal (none, XC0, XC1, XC2). See Figure 37-3. Note: 1. Figure 37-2. In all cases, if an external clock is used, the duration of each of its levels must be longer than the peripheral clock period. The external clock frequency must be at least 2.5 times lower than the peripheral clock. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 TIOB0 XC2 = TCLK2 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA1 XC0 = TCLK0 TIOA0 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 855 Figure 37-3. Clock Selection TCCLKS CLKI TIMER_CLOCK1 Synchronous Edge Detection TIMER_CLOCK2 TIMER_CLOCK3 Selected Clock TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 Peripheral Clock BURST 1 37.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 37-4. 856  The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC Channel Control Register (TC_CCR). In Capture mode it can be disabled by an RB load event if LDBDIS is set to 1 in the TC_CMR. In Waveform mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the TC_CCR can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the TC_SR.  The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture mode (LDBSTOP = 1 in TC_CMR) or an RC compare event in Waveform mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands are effective only if the clock is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 37-4. Clock Control Selected Clock Trigger CLKSTA Q Q S CLKEN CLKDIS S R R Counter Clock Stop Event Disable Event 37.6.5 Operating Modes Each channel can operate independently in two different modes:  Capture mode provides measurement on signals.  Waveform mode provides wave generation. The TC operating mode is programmed with the WAVE bit in the TC_CMR. In Capture mode, TIOA and TIOB are configured as inputs. In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 37.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. The following triggers are common to both modes:  Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.  SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.  Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in the TC_CMR. The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting bit ENETRG in the TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the peripheral clock period in order to be detected. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 857 37.6.7 Capture Mode Capture mode is entered by clearing the WAVE bit in the TC_CMR. Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 37-5 shows the configuration of the TC channel when programmed in Capture mode. 37.6.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. They can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA field in the TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB field defines the TIOA selected edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS bit) in the TC_SR. In this case, the old value is overwritten. 37.6.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in the TC_CMR selects TIOA or TIOB input signal as an external trigger . The External Trigger Edge Selection parameter (ETRGEDG field in TC_CMR) defines the edge (rising, falling, or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 858 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 MTIOA MTIOB 1 ABETRG CLKI If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel BURST Peripheral Clock Synchronous Edge Detection S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS LDRBS INT Figure 37-5. Capture Mode LOVRS CPCS ETRGS LDRAS TC1_IMR Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 SAM4S Series [DATASHEET] 859 37.6.10 Waveform Mode Waveform mode is entered by setting the TC_CMRx.WAVE bit. In Waveform mode, the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 37-6 shows the configuration of the TC channel when programmed in Waveform operating mode. 37.6.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR, the behavior of TC_CV varies. With any selection, TC_RA, TC_RB and TC_RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 860 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG Peripheral Clock Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS TIOB MTIOB TIOA MTIOA Figure 37-6. Waveform Mode Output Controller CPCS CPBS COVFS TC1_SR ETRGS TC1_IMR Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 SAM4S Series [DATASHEET] 861 37.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 216-1. Once 216-1 has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 37-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 37-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 37-7. WAVSEL = 00 without Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 37-8. WAVSEL = 00 with Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples TIOB TIOA 862 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Time 37.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 37-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 37-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 37-9. WAVSEL = 10 without Trigger Counter Value 2n-1 (n = counter size) Counter cleared by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 37-10. WAVSEL = 10 with Trigger Counter Value 2n-1 (n = counter size) Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 863 37.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 216-1 . Once 216-1 is reached, the value of TC_CV is decremented to 0, then re-incremented to 216-1 and so on. See Figure 37-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 37-11. WAVSEL = 01 without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 37-12. WAVSEL = 01 with Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Waveform Examples TIOB TIOA 864 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Time 37.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 37-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 37-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 37-13. WAVSEL = 11 without Trigger Counter Value 2n-1 (n = counter size) Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 37-14. WAVSEL = 11 with Trigger Counter Value 2n-1 (n = counter size) RC RB Counter decremented by compare match with RC Counter decremented by trigger Counter incremented by trigger RA Waveform Examples Time TIOB TIOA SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 865 37.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in the TC_CMR. As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 866 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.6.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 37.6.14 Quadrature Decoder 37.6.14.1 Description The quadrature decoder (QDEC) is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of channel 0 and 1. Channel 2 can be used as a time base in case of speed measurement requirements (refer to Figure 37-15). When writing a 0 to bit QDEN of the TC_BMR, the QDEC is bypassed and the IO pins are directly routed to the timer counter function. See TIOA0 and TIOB0 are to be driven by the two dedicated quadrature signals from a rotary sensor mounted on the shaft of the off-chip motor. A third signal from the rotary sensor can be processed through pin TIOB1 and is typically dedicated to be driven by an index signal if it is provided by the sensor. This signal is not required to decode the quadrature signals PHA, PHB. Field TCCLKS of TC_CMRx must be configured to select XC0 input (i.e., 0x101). Field TC0XC0S has no effect as soon as the QDEC is enabled. Either speed or position/revolution can be measured. Position channel 0 accumulates the edges of PHA, PHB input signals giving a high accuracy on motor position whereas channel 1 accumulates the index pulses of the sensor, therefore the number of rotations. Concatenation of both values provides a high level of precision on motion system position. In Speed mode, position cannot be measured but revolution can be measured. Inputs from the rotary sensor can be filtered prior to down-stream processing. Accommodation of input polarity, phase definition and other factors are configurable. Interruptions can be generated on different events. A compare function (using TC_RC) is available on channel 0 (speed/position) or channel 1 (rotation) and can generate an interrupt by means of the CPCS flag in the TC_SRx. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 867 Figure 37-15. Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA Timer/Counter Channel 0 TIOA0 QDEN PHEdges 1 TIOB 1 XC0 TIOB0 TIOA0 PHA TIOB0 PHB TIOB1 IDX XC0 Speed/Position QDEN Index 1 TIOB TIOB1 1 XC0 Timer/Counter Channel 1 XC0 Rotation Direction Timer/Counter Channel 2 Speed Time Base 37.6.14.2 Input Pre-processing Input pre-processing consists of capabilities to take into account rotary sensor factors such as polarities and phase definition followed by configurable digital filtering. Each input can be negated and swapping PHA, PHB is also configurable. The MAXFILT field in the TC_BMR is used to configure a minimum duration for which the pulse is stated as valid. When the filter is active, pulses with a duration lower than MAXFILT +1 × tperipheral clock ns are not passed to downstream logic. 868 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 37-16. Input Stage Input Pre-Processing MAXFILT SWAP 1 PHA Filter TIOA0 MAXFILT > 0 1 PHedge Direction and Edge Detection INVA 1 PHB Filter TIOB0 1 DIR 1 IDX INVB 1 1 IDX Filter TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interference. Or, simply if vibration occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the beginning of one of the reflective or magnetic bars on the rotary sensor disk is aligned with the light or magnetic (Hall) receiver cell of the rotary sensor. Any vibration can make the PHA, PHB signals toggle for a short duration. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 869 Figure 37-17. Filtering Examples MAXFILT = 2 Peripheral Clock particulate contamination PHA,B Filter Out Optical/Magnetic disk strips PHA PHB motor shaft stopped in such a position that rotary sensor cell is aligned with an edge of the disk rotation stop PHA PHB Edge area due to system vibration PHB Resulting PHA, PHB electrical waveforms PHA stop mechanical shock on system PHB vibration PHA, PHB electrical waveforms after filtering PHA PHB 870 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.6.14.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the two quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag. Any change in rotation direction is reported in the TC_QISR and can generate an interrupt. The direction change condition is reported as soon as two consecutive edges on a phase signal have sampled the same value on the other phase signal and there is an edge on the other signal. The two consecutive edges of one phase signal sampling the same value on other phase signal is not sufficient to declare a direction change, for the reason that particulate contamination may mask one or more reflective bars on the optical or magnetic disk of the sensor. Refer to Figure 37-18 for waveforms. Figure 37-18. Rotation Change Detection Direction Change under normal conditions PHA change condition Report Time PHB DIR DIRCHG No direction change due to particulate contamination masking a reflective bar missing pulse PHA same phase PHB DIR spurious change condition (if detected in a simple way) DIRCHG The direction change detection is disabled when QDTRANS is set in the TC_BMR. In this case, the DIR flag report must not be used. A quadrature error is also reported by the QDEC via the QERR flag in the TC_QISR. This error is reported if the time difference between two edges on PHA, PHB is lower than a predefined value. This predefined value is SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 871 configurable and corresponds to (MAXFILT + 1) × tperipheral clock ns. After being filtered there is no reason to have two edges closer than (MAXFILT + 1) × tperipheral clock ns under normal mode of operation. Figure 37-19. Quadrature Error Detection MAXFILT = 2 Peripheral Clock Abnormally formatted optical disk strips (theoretical view) PHA PHB strip edge inaccurary due to disk etching/printing process PHA PHB resulting PHA, PHB electrical waveforms PHA Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time. PHB duration < MAXFILT QERR MAXFILT must be tuned according to several factors such as the peripheral clock frequency, type of rotary sensor and rotation speed to be achieved. 37.6.14.4 Position and Rotation Measurement When the POSEN bit is set in the TC_BMR, the motor axis position is processed on channel 0 (by means of the PHA, PHB edge detections) and the number of motor revolutions are recorded on channel 1 if the IDX signal is provided on the TIOB1 input. The position measurement can be read in the TC_CV0 register and the rotation measurement can be read in the TC_CV1 register. Channel 0 and 1 must be configured in Capture mode (TC_CMR0.WAVE = 0). ‘Rising edge’ must be selected as the External Trigger Edge (TC_CMR.ETRGEDG = 0x01) and ‘TIOA’ must be selected as the External Trigger (TC_CMR.ABETRG = 0x1). In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0 register. Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word. The timer/counter channel 0 is cleared for each increment of IDX count value. 872 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels 0 and 1. The direction status is reported on TC_QISR. 37.6.14.5 Speed Measurement When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0. A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in Waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOA output. This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set. Channel 0 must be configured in Capture mode (WAVE = 0 in TC_CMR0). The ABETRG bit of TC_CMR0 must be configured at 1 to select TIOA as a trigger for this channel. EDGTRG must be set to 0x01, to clear the counter on a rising edge of the TIOA signal and field LDRA must be set accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a consequence, at the end of each time base period the differentiation required for the speed calculation is performed. The process must be started by configuring bits CLKEN and SWTRG in the TC_CCR. The speed can be read on field RA in TC_RA0. Channel 1 can still be used to count the number of revolutions of the motor. 37.6.15 2-bit Gray Up/Down Counter for Stepper Motor Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA, TIOB outputs by means of the GCEN bit in TC_SMMRx. Up or Down count can be defined by writing bit DOWN in TC_SMMRx. It is mandatory to configure the channel in Waveform mode in the TC_CMR. The period of the counters can be programmed in TC_RCx. Figure 37-20. 2-bit Gray Up/Down Counter WAVEx = GCENx =1 TIOAx TC_RCx TIOBx DOWNx 37.6.16 Fault Mode At any time, the TC_RCx registers can be used to perform a comparison on the respective current channel counter value (TC_CVx) with the value of TC_RCx register. The CPCSx flags can be set accordingly and an interrupt can be generated. This interrupt is processed but requires an unpredictable amount of time to be achieve the required action. It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 and/or CPCS from TC_SR1. Each source can be independently enabled/disabled in the TC_FMR. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 873 This can be useful to detect an overflow on speed and/or position when QDEC is processed and to act immediately by using the FAULT output. Figure 37-21. Fault Output Generation AND TC_SR0 flag CPCS OR TC_FMR / ENCF0 AND FAULT (to PWM input) TC_SR1 flag CPCS TC_FMR / ENCF1 37.6.17 Register Write Protection To prevent any single software error from corrupting TC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the TC Write Protection Mode Register (TC_WPMR). The Timer Counter clock of the first channel must be enabled to access TC_WPMR. The following registers can be write-protected: 874  TC Block Mode Register  TC Channel Mode Register: Capture Mode  TC Channel Mode Register: Waveform Mode  TC Fault Mode Register  TC Stepper Motor Mode Register  TC Register A  TC Register B  TC Register C SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7 Timer Counter (TC) User Interface Table 37-6. Register Mapping Offset(1) Register Name Access Reset 0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only – 0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read/Write 0 0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR Read/Write 0 0x00 + channel * 0x40 + 0x0C Reserved – – – 0x00 + channel * 0x40 + 0x10 Counter Value TC_CV 0x00 + channel * 0x40 + 0x14 Register A TC_RA Read-only Read/Write 0 (2) 0 (2) 0 0x00 + channel * 0x40 + 0x18 Register B TC_RB 0x00 + channel * 0x40 + 0x1C Register C TC_RC Read/Write 0 0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0 0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only – 0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only – 0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0 0xC0 Block Control Register TC_BCR Write-only – 0xC4 Block Mode Register TC_BMR Read/Write 0 0xC8 QDEC Interrupt Enable Register TC_QIER Write-only – 0xCC QDEC Interrupt Disable Register TC_QIDR Write-only – 0xD0 QDEC Interrupt Mask Register TC_QIMR Read-only 0 0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0 0xD8 Fault Mode Register TC_FMR Read/Write 0 0xE4 Write Protection Mode Register TC_WPMR Read/Write 0 Reserved – – – 0xE8–0xFC Notes: Read/Write 1. Channel index ranges from 0 to 2. 2. Read-only if TC_CMRx.WAVE = 0 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 875 37.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1], 0x40014080 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN • CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0: No effect. 1: Disables the clock. • SWTRG: Software Trigger Command 0: No effect. 1: A software trigger is performed: the counter is reset and the clock is started. 876 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..2] (CAPTURE_MODE) Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1], 0x40014084 (1)[2] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 18 17 24 – 23 – 22 – 21 – 20 – 19 15 WAVE 14 CPCTRG 13 – 12 – 11 – 10 ABETRG 9 7 LDBDIS 6 LDBSTOP 5 4 3 CLKI 2 1 TCCLKS 16 LDRB BURST LDRA 8 ETRGEDG 0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • TCCLKS: Clock Selection Value Name Description 0 TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 1 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 4 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 5 XC0 Clock selected: XC0 6 XC1 Clock selected: XC1 7 XC2 Clock selected: XC2 • CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0: Counter clock is not stopped when RB loading occurs. 1: Counter clock is stopped when RB loading occurs. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 877 • LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. • WAVE: Waveform Mode 0: Capture mode is enabled. 1: Capture mode is disabled (Waveform mode is enabled). • LDRA: RA Loading Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge of TIOA 2 FALLING Falling edge of TIOA 3 EDGE Each edge of TIOA • LDRB: RB Loading Edge Selection 878 Value Name Description 0 NONE None 1 RISING Rising edge of TIOA 2 FALLING Falling edge of TIOA 3 EDGE Each edge of TIOA SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..2] (WAVEFORM_MODE) Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1], 0x40014084 (1)[2] Access: Read/Write 31 30 29 BSWTRG 23 28 27 BEEVT 22 21 ASWTRG 20 14 13 7 CPCDIS 6 CPCSTOP WAVSEL 25 24 BCPB 19 AEEVT 15 WAVE 26 BCPC 18 17 16 ACPC 12 ENETRG 11 4 3 CLKI 5 BURST ACPA 10 9 EEVT 8 EEVTEDG 2 1 TCCLKS 0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • TCCLKS: Clock Selection Value Name Description 0 TIMER_CLOCK1 Clock selected: internal MCK/2 clock signal (from PMC) 1 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 2 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 3 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 4 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 5 XC0 Clock selected: XC0 6 XC1 Clock selected: XC1 7 XC2 Clock selected: XC2 • CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0: Counter clock is not stopped when counter reaches RC. 1: Counter clock is stopped when counter reaches RC. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 879 • CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event. Value Note: Name Description 0 TIOB (1) TIOB Direction TIOB Input 1 XC0 XC0 Output 2 XC1 XC1 Output 3 XC2 XC2 Output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • ENETRG: External Event Trigger Enable 0: The external event has no effect on the counter and its clock. 1: The external event resets the counter and starts the counter clock. Note: Whatever the value programmed in ENETRG, the selected external event only controls the TIOA output and TIOB if not used as input (trigger event input or other input used). • WAVSEL: Waveform Selection Value Name Description 0 UP UP mode without automatic trigger on RC Compare 1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 2 UP_RC UP mode with automatic trigger on RC Compare 3 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare • WAVE: Waveform Mode 0: Waveform mode is disabled (Capture mode is enabled). 1: Waveform mode is enabled. • ACPA: RA Compare Effect on TIOA 880 Value Name Description 0 NONE None SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPB: RB Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPC: RC Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 881 • BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB 882 Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.4 TC Stepper Motor Mode Register Name: TC_SMMRx [x=0..2] Address: 0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1], 0x40014088 (1)[2] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 DOWN 0 GCEN This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • GCEN: Gray Count Enable 0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x. 1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter. • DOWN: Down Count 0: Up counter. 1: Down counter. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 883 37.7.5 TC Counter Value Register Name: TC_CVx [x=0..2] Address: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1], 0x40014090 (1)[2] Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time. IMPORTANT: For 16-bit channels, CV field size is limited to register bits 15:0. 884 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.6 TC Register A Name: TC_RAx [x=0..2] Address: 0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1], 0x40014094 (1)[2] Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • RA: Register A RA contains the Register A value in real time. IMPORTANT: For 16-bit channels, RA field size is limited to register bits 15:0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 885 37.7.7 TC Register B Name: TC_RBx [x=0..2] Address: 0x40010018 (0)[0], 0x40010058 (0)[1], 0x40010098 (0)[2], 0x40014018 (1)[0], 0x40014058 (1)[1], 0x40014098 (1)[2] Access: Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RB 23 22 21 20 RB 15 14 13 12 RB 7 6 5 4 RB This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • RB: Register B RB contains the Register B value in real time. IMPORTANT: For 16-bit channels, RB field size is limited to register bits 15:0. 886 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.8 TC Register C Name: TC_RCx [x=0..2] Address: 0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[2], 0x4001401C (1)[0], 0x4001405C (1)[1], 0x4001409C (1)[2] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • RC: Register C RC contains the Register C value in real time. IMPORTANT: For 16-bit channels, RC field size is limited to register bits 15:0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 887 37.7.9 TC Status Register Name: TC_SRx [x=0..2] Address: 0x40010020 (0)[0], 0x40010060 (0)[1], 0x400100A0 (0)[2], 0x40014020 (1)[0], 0x40014060 (1)[1], 0x400140A0 (1)[2] Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 MTIOB 17 MTIOA 16 CLKSTA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow Status (cleared on read) 0: No counter overflow has occurred since the last read of the Status Register. 1: A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status (cleared on read) 0: Load overrun has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1. 1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if TC_CMRx.WAVE = 0. • CPAS: RA Compare Status (cleared on read) 0: RA Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0. 1: RA Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1. • CPBS: RB Compare Status (cleared on read) 0: RB Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0. 1: RB Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1. • CPCS: RC Compare Status (cleared on read) 0: RC Compare has not occurred since the last read of the Status Register. 1: RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status (cleared on read) 0: RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1. 1: RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0. • LDRBS: RB Loading Status (cleared on read) 0: RB Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1. 1: RB Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0. 888 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • ETRGS: External Trigger Status (cleared on read) 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If TC_CMRx.WAVE = 0, this means that TIOA pin is low. If TC_CMRx.WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If TC_CMRx.WAVE = 0, this means that TIOA pin is high. If TC_CMRx.WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0: TIOB is low. If TC_CMRx.WAVE = 0, this means that TIOB pin is low. If TC_CMRx.WAVE = 1, this means that TIOB is driven low. 1: TIOB is high. If TC_CMRx.WAVE = 0, this means that TIOB pin is high. If TC_CMRx.WAVE = 1, this means that TIOB is driven high. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 889 37.7.10 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1], 0x400140A4 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0: No effect. 1: Enables the Load Overrun Interrupt. • CPAS: RA Compare 0: No effect. 1: Enables the RA Compare Interrupt. • CPBS: RB Compare 0: No effect. 1: Enables the RB Compare Interrupt. • CPCS: RC Compare 0: No effect. 1: Enables the RC Compare Interrupt. • LDRAS: RA Loading 0: No effect. 1: Enables the RA Load Interrupt. • LDRBS: RB Loading 0: No effect. 1: Enables the RB Load Interrupt. 890 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • ETRGS: External Trigger 0: No effect. 1: Enables the External Trigger Interrupt. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 891 37.7.11 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1], 0x400140A8 (1)[2] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0: No effect. 1: Disables the Load Overrun Interrupt (if TC_CMRx.WAVE = 0). • CPAS: RA Compare 0: No effect. 1: Disables the RA Compare Interrupt (if TC_CMRx.WAVE = 1). • CPBS: RB Compare 0: No effect. 1: Disables the RB Compare Interrupt (if TC_CMRx.WAVE = 1). • CPCS: RC Compare 0: No effect. 1: Disables the RC Compare Interrupt. • LDRAS: RA Loading 0: No effect. 1: Disables the RA Load Interrupt (if TC_CMRx.WAVE = 0). • LDRBS: RB Loading 0: No effect. 1: Disables the RB Load Interrupt (if TC_CMRx.WAVE = 0). 892 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • ETRGS: External Trigger 0: No effect. 1: Disables the External Trigger Interrupt. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 893 37.7.12 TC Interrupt Mask Register Name: TC_IMRx [x=0..2] Address: 0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1], 0x400140AC (1)[2] Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS • COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0: The Load Overrun Interrupt is disabled. 1: The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0: The RA Compare Interrupt is disabled. 1: The RA Compare Interrupt is enabled. • CPBS: RB Compare 0: The RB Compare Interrupt is disabled. 1: The RB Compare Interrupt is enabled. • CPCS: RC Compare 0: The RC Compare Interrupt is disabled. 1: The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0: The Load RA Interrupt is disabled. 1: The Load RA Interrupt is enabled. • LDRBS: RB Loading 0: The Load RB Interrupt is disabled. 1: The Load RB Interrupt is enabled. 894 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 • ETRGS: External Trigger 0: The External Trigger Interrupt is disabled. 1: The External Trigger Interrupt is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 895 37.7.13 TC Block Control Register Name: TC_BCR Address: 0x400100C0 (0), 0x400140C0 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 896 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.14 TC Block Mode Register Name: TC_BMR Address: 0x400100C4 (0), 0x400140C4 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 23 22 21 20 19 – 18 – 17 IDXPHB 16 SWAP 12 EDGPHA 11 QDTRANS 10 SPEEDEN 9 POSEN 8 QDEN 4 3 2 1 0 MAXFILT 15 INVIDX 14 INVB 13 INVA 7 – 6 – 5 TC2XC2S 24 MAXFILT TC1XC1S TC0XC0S This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • TC0XC0S: External Clock Signal 0 Selection Value Name Description 0 TCLK0 Signal connected to XC0: TCLK0 1 – Reserved 2 TIOA1 Signal connected to XC0: TIOA1 3 TIOA2 Signal connected to XC0: TIOA2 • TC1XC1S: External Clock Signal 1 Selection Value Name Description 0 TCLK1 Signal connected to XC1: TCLK1 1 – Reserved 2 TIOA0 Signal connected to XC1: TIOA0 3 TIOA2 Signal connected to XC1: TIOA2 • TC2XC2S: External Clock Signal 2 Selection Value Name Description 0 TCLK2 Signal connected to XC2: TCLK2 1 – Reserved 2 TIOA0 Signal connected to XC2: TIOA0 3 TIOA1 Signal connected to XC2: TIOA1 • QDEN: Quadrature Decoder Enabled 0: Disabled. 1: Enables the QDEC (filter, edge detection and quadrature decoding). Quadrature decoding (direction change) can be disabled using QDTRANS bit. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 897 One of the POSEN or SPEEDEN bits must be also enabled. • POSEN: Position Enabled 0: Disable position. 1: Enables the position measure on channel 0 and 1. • SPEEDEN: Speed Enabled 0: Disabled. 1: Enables the speed measure on channel 0, the time base being provided by channel 2. • QDTRANS: Quadrature Decoding Transparent 0: Full quadrature decoding logic is active (direction change detected). 1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed. • EDGPHA: Edge on PHA Count Mode 0: Edges are detected on PHA only. 1: Edges are detected on both PHA and PHB. • INVA: Inverted PHA 0: PHA (TIOA0) is directly driving the QDEC. 1: PHA is inverted before driving the QDEC. • INVB: Inverted PHB 0: PHB (TIOB0) is directly driving the QDEC. 1: PHB is inverted before driving the QDEC. • INVIDX: Inverted Index 0: IDX (TIOA1) is directly driving the QDEC. 1: IDX is inverted before driving the QDEC. • SWAP: Swap PHA and PHB 0: No swap between PHA and PHB. 1: Swap PHA and PHB internally, prior to driving the QDEC. • IDXPHB: Index Pin is PHB Pin 0: IDX pin of the rotary sensor must drive TIOA1. 1: IDX pin of the rotary sensor must drive TIOB0. • MAXFILT: Maximum Filter 1–63: Defines the filtering capabilities. Pulses with a period shorter than MAXFILT+1 peripheral clock cycles are discarded. 898 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.15 TC QDEC Interrupt Enable Register Name: TC_QIER Address: 0x400100C8 (0), 0x400140C8 (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No effect. 1: Enables the interrupt when a rising edge occurs on IDX input. • DIRCHG: Direction Change 0: No effect. 1: Enables the interrupt when a change on rotation direction is detected. • QERR: Quadrature Error 0: No effect. 1: Enables the interrupt when a quadrature error occurs on PHA, PHB. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 899 37.7.16 TC QDEC Interrupt Disable Register Name: TC_QIDR Address: 0x400100CC (0), 0x400140CC (1) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No effect. 1: Disables the interrupt when a rising edge occurs on IDX input. • DIRCHG: Direction Change 0: No effect. 1: Disables the interrupt when a change on rotation direction is detected. • QERR: Quadrature Error 0: No effect. 1: Disables the interrupt when a quadrature error occurs on PHA, PHB. 900 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.17 TC QDEC Interrupt Mask Register Name: TC_QIMR Address: 0x400100D0 (0), 0x400140D0 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: The interrupt on IDX input is disabled. 1: The interrupt on IDX input is enabled. • DIRCHG: Direction Change 0: The interrupt on rotation direction change is disabled. 1: The interrupt on rotation direction change is enabled. • QERR: Quadrature Error 0: The interrupt on quadrature error is disabled. 1: The interrupt on quadrature error is enabled. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 901 37.7.18 TC QDEC Interrupt Status Register Name: TC_QISR Address: 0x400100D4 (0), 0x400140D4 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 DIR 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX • IDX: Index 0: No Index input change since the last read of TC_QISR. 1: The IDX input has changed since the last read of TC_QISR. • DIRCHG: Direction Change 0: No change on rotation direction since the last read of TC_QISR. 1: The rotation direction changed since the last read of TC_QISR. • QERR: Quadrature Error 0: No quadrature error since the last read of TC_QISR. 1: A quadrature error occurred since the last read of TC_QISR. • DIR: Direction Returns an image of the actual rotation direction. 902 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 37.7.19 TC Fault Mode Register Name: TC_FMR Address: 0x400100D8 (0), 0x400140D8 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 ENCF1 0 ENCF0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • ENCF0: Enable Compare Fault Channel 0 0: Disables the FAULT output source (CPCS flag) from channel 0. 1: Enables the FAULT output source (CPCS flag) from channel 0. • ENCF1: Enable Compare Fault Channel 1 0: Disables the FAULT output source (CPCS flag) from channel 1. 1: Enables the FAULT output source (CPCS flag) from channel 1. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 903 37.7.20 TC Write Protection Mode Register Name: TC_WPMR Address: 0x400100E4 (0), 0x400140E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). The Timer Counter clock of the first channel must be enabled to access this register. See Section 37.6.17 “Register Write Protection” for a list of registers that can be write-protected and Timer Counter clock conditions. • WPKEY: Write Protection Key Value 0x54494D 904 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 38. High Speed Multimedia Card Interface (HSMCI) 38.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1. The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The HSMCI supports stream, block and multi block data read and write, and is compatible with the Peripheral DMA Controller (PDC) Channels, minimizing processor intervention for large buffer transfers. The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences between SD and High Speed MultiMedia Cards are the initialization process and the bus topology. HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable. 38.2 Embedded Characteristics  Compatible with MultiMedia Card Specification Version 4.3  Compatible with SD Memory Card Specification Version 2.0  Compatible with SDIO Specification Version 2.0  Compatible with CE-ATA Specification 1.1  Cards Clock Rate Up to Master Clock Divided by 2  Boot Operation Mode Support  High Speed Mode Support  Embedded Power Management to Slow Down Clock Rate When Not Used  Supports 1 Multiplexed Slot(s) ̶ Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card  Support for Stream, Block and Multi-block Data Read and Write  Supports Connection to Peripheral DMA Controller (PDC) ̶ Minimizes Processor Intervention for Large Buffer Transfers  Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access  Support for CE-ATA Completion Signal Disable Command  Protection Against Unexpected Modification On-the-Fly of the Configuration Registers SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 905 38.3 Block Diagram Figure 38-1. Block Diagram (4-bit configuration) APB Bridge PDC APB MCCK(1) MCCDA(1) PMC MCK MCDA0(1) HSMCI Interface PIO MCDA1(1) MCDA2(1) MCDA3(1) Interrupt Control HSMCI Interrupt Note: 906 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 38.4 Application Block Diagram Figure 38-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 10 11 1213 8 SDCard MMC 38.5 Pin Name List Table 38-1. I/O Lines Description for 4-bit Configuration (1) Pin Name Pin Description Type(2) Comments MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP Notes: DAT[0..3] of an MMC DAT[0..3] of an SD Card/SDIO 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. 2. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 907 38.6 Product Dependencies 38.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 38-2. I/O Lines Instance Signal I/O Line Peripheral HSMCI MCCDA PA28 C HSMCI MCCK PA29 C HSMCI MCDA0 PA30 C HSMCI MCDA1 PA31 C HSMCI MCDA2 PA26 C HSMCI MCDA3 PA27 C 38.6.2 Power Management The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the HSMCI clock. 38.6.3 Interrupt Sources The HSMCI has an interrupt line connected to the interrupt controller. Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI. Table 38-3. 38.7 Peripheral IDs Instance ID HSMCI 18 Bus Topology Figure 38-3. High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 10 11 1213 8 MMC 908 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 38-4. Bus Topology Description HSMCI Pin Name(2) (Slot z) I/O/PP Data MCDz3 CMD I/O/PP/OD Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data 0 MCDz0 8 DAT[1] I/O/PP Data 1 MCDz1 9 DAT[2] I/O/PP Data 2 MCDz2 10 DAT[4] I/O/PP Data 4 MCDz4 11 DAT[5] I/O/PP Data 5 MCDz5 12 DAT[6] I/O/PP Data 6 MCDz6 13 DAT[7] I/O/PP Data 7 MCDz7 Pin Number Name Type 1 DAT[3] 2 Notes: 1. 2. Figure 38-4. (1) I: Input, O: Output, PP: Push/Pull, OD: Open Drain. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 10 11 9 10 11 9 10 11 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 909 Figure 38-5. SD Memory Card Bus Topology 1 2 3 4 56 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 38-5. Table 38-5. SD Memory Card Bus Signals Description HSMCI Pin Name(2) (Slot z) I/O/PP Card detect/ Data line Bit 3 MCDz3 CMD PP Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data line Bit 0 MCDz0 8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1 9 DAT[2] I/O/PP Data line Bit 2 MCDz2 Pin Number Name Type 1 CD/DAT[3] 2 1. 2. Figure 38-6. I: input, O: output, PP: Push Pull, OD: Open Drain. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Notes: (1) Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 910 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 38.8 High Speed MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol. Each message is represented by one of the following tokens:  Command—A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.  Response—A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.  Data—Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System Specification. See also Table 38-6 on page 912. High Speed MultiMedia Card bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock HSMCI clock. Two types of data transfer commands are defined:  Sequential commands—These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.  Block-oriented commands—These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a predefined block count (see Section 38.8.2 “Data Transfer Operation”). The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations. 38.8.1 Command - Response Operation After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR. The PWSEN bit saves power by dividing the HSMCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command Register (HSMCI_CMDR). The HSMCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC NID Cycles E Z ****** Response Z S T CID Content High Impedance State Z Z Z SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 911 The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 38-6 and Table 38-7. Table 38-6. ALL_SEND_CID Command Description CMD Index Type Argument Response Abbreviation Command Description CMD2 bcr(1) [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: 1. Table 38-7. bcr means broadcast command with response. Fields and Values for HSMCI_CMDR Field Value CMDNB (command number) 2 (CMD2) RSPTYP (response type) 2 (R2: 136 bits response) SPCMD (special command) 0 (not a special command) OPCMD (open drain command) 1 MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles) TRCMD (transfer command) 0 (No transfer) TRDIR (transfer direction) X (available only in transfer command) TRTYP (transfer type) X (available only in transfer command) IOSPCMD (SDIO special command) 0 (not a special command) The HSMCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps:  Fill the argument register (HSMCI_ARGR) with the command argument.  Set the command register (HSMCI_CMDR) (see Table 38-7). The command is sent immediately after writing the command register. While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a new command shall not be sent. The NOTBUSY flag in the Status Register (HSMCI_SR) is asserted when the card releases the busy indication. If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the HSMCI Interrupt Enable Register (HSMCI_IER) allows using an interrupt method. 912 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 38-7. Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? RETURN ERROR(1) Read response if required Does the command involve a busy indication? No RETURN OK Read HSMCI_SR 0 NOTBUSY 1 RETURN OK Note: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed MultiMedia Card specification). SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 913 38.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in HSMCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the HSMCI Mode Register (HSMCI_MR) or in the HSMCI Block Register (HSMCI_BLKR). This field determines the size of the data block. Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time):  Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received.  Multiple block read (or write) with predefined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with predefined block count, the host must correctly program the HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the HSMCI_BLKR defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 38.8.3 Read Operation The following flowchart (Figure 38-8) shows how to read a single block with or without use of PDC facilities. In this example, a polling method is used to wait for the end of read. Similarly, the user can configure the HSMCI Interrupt Enable Register (HSMCI_IER) to trigger an interrupt at the end of read. 914 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Figure 38-8. Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) No Yes Read with PDC Reset the PDCMODE bit HSMCI_MR &= ~PDCMODE Set the block length (in bytes) HSMCI_BLKR |= (BlockLength ‘TXTDIS’, ‘RXDIS’ --> ‘RXTDIS’), added commands 6-9 in Section 34.8.7.1 “Data Transmit with the PDC” on page 724 and and commands 4 and 12 in Section 34.8.7.2 “Data Receive with the PDC” on page 724. Updated Figure 34-27 “Master Performs a General Call”. Corrected TWI_THR to Write-only access in Table 34-7 ”Register Mapping” and Section 34.11.11 “TWI Transmit Holding Register” Added Section 34.10.6 “Using the Peripheral DMA Controller (PDC) in Slave Mode” Section 34.11.6 “TWI Status Register”, updated the description of “NACK: Not Acknowledged (clear on read)”, used in master mode Section 35. “Universal Asynchronous Receiver Transmitter (UART)” Corrected the offset for PDC registers in Section 35.6 “Universal Asynchronous Receiver Transmitter (UART) User Interface”. Section 36. “Universal Synchronous Asynchronous Receiver Transceiver (USART)” Table 36-2 ”I/O Line Description”: corrected RXD type from Input to I/O. Added a paragraph on IRDA_FILTER programming criteria in Section 36.7.5.3 “IrDA Demodulator” and in the corresponding bitfield description in Section 36.8.20 “USART IrDA FILTER Register”. Corrected Figure 36-22 “Parity Error” for stop bit value. Replaced 33400 baudrate with 38400 in Table 36-10, “Maximum Timeguard Length Depending on Baud Rate,” on page 792, Table 36-11, “Maximum Time-out Period,” on page 793. Section 36.7.10 “Register Write Protection”: Changed section title and re-worked content. Section 36.8.22 “USART Write Protection Mode Register” and Section 36.8.23 “USART Write Protection Status Register”: Changed register names and modified bit and field descriptions. In Section 36.7.3.4 “Manchester Decoder”, updated information on RXIDLEV bit in 4th paragraph. Section 36.8.3 “USART Mode Register”: in table describing ‘PAR Parity Type’ field, added value ‘5’ and description. Section 36.8.18 “USART FI DI RATIO Register”: modified FI_DI_RATIO field from 16 bits to 11 bits. In Section 36.8.21 “USART Manchester Configuration Register” added RXIDLEV as bit 31 and added bit description. Section 37. “Timer Counter (TC)” TIOA1 replaced with TIOB1 in Section 37.1 “Description”and added a note for ENETRG description in Section 37.7.3 “TC Channel Mode Register: Waveform Mode”. Erroneous description of TCCLKS table, rows 0 to 4 reworked in Section 37.7.2 “TC Channel Mode Register: Capture Mode” and Section 37.7.3 “TC Channel Mode Register: Waveform Mode” Section 37.7.14 “TC Block Mode Register”: corrected TC2XC2S field configuration values: value 2 is TIOA0 (was TIOA1); value 3 is TIOA1 (was TIOA2) Section 37.6.2 “16-bit Counter”, Section 37.6.11.1 “WAVSEL = 00”, Figure 37-9 “WAVSEL = 10 without Trigger”, Figure 37-10 “WAVSEL = 10 with Trigger”, Section 37.6.11.3 “WAVSEL = 01”, and Figure 37-14 “WAVSEL = 11 with Trigger”: replaced “0xFFFF” with “2n-1” in first paragraph (with “n” representing counter size) SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1249 Table 49-6. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 38. “High Speed MultiMedia Card Interface (HSMCI)” Changed PDCFBYTE to FBYTE in Section 9.6 “WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation using DMA Controller” and in Section 9.8 “READ_SINGLE_BLOCK/READ_MULTIPLE_BLOCK Operation using DMA Controller”. Section 38.13 “Register Write Protection”: changed title (was “Write Protection Registers”); revised content In Section 38.14.2 “HSMCI Mode Register”, PDCMODE bit description, corrected reference to MCI Mode Register to HSMCI Status Register. In Section 38.14.7 “HSMCI Block Register”, BLKLEN bit description, removed sentence on its accessibility in HSMCI Mode Register. Section 38.14.17 “HSMCI Write Protection Mode Register”: modified register name (was HSMCI Write Protect Mode Register); replaced list of protectable registers with cross-reference to section “Register Write Protection” Section 38.14.18 “HSMCI Write Protection Status Register”: modified register name (was HSMCI Write Protect Status Register) and updated description Section 40. “USB Device Port (UDP)” Section 40.2 “Embedded Characteristics”: replaced bullet “Integrated Pull-up on DP” with “Integrated Pull-up on DPP”, added bullet “Integrated Pull-down on DDM” Section 40.6.3.6 “Entering in Suspend State”: replaced “must drain less than 500uA” with “must drain no more than 2.5 mA” Section 40.6.3 “Controlling Device States”: replaced “may not consume more than 500 µA” with “must not consume more than 2.5 mA” Table 40-6 ”Register Mapping”: corrected reset values for for UDP-FDR0..Y. Updated note (1). Section 40.4.2 “Power Management”: added detail on fast RC. Changed register names:  Section 40.7.10 old: UDP Endpoint Control and Status Register (Control, Bulk Interrupt Endpoints), new: “UDP Endpoint Control and Status Register (CONTROL_BULK)”  Section 40.7.11 old: UDP Endpoint Control and Status Register (Isochronous Endpoints), new: “UDP Endpoint Control and Status Register (ISOCHRONOUS)”. Section 41. “Analog Comparator Controller (ACC)” Section 41.1 “Description” Updated section for clarity. Figure 41-1 “Analog Comparator Controller Block Diagram”: Updated for clarity. Section 41.6 “Functional Description”, Section 41.6.2 “Analog Settings” and Section 41.6.4 “Fault Mode”: Updated for clarity. Replaced section “Write Protection System” with Section 41.6.5 “Register Write Protection”. Updated Section 41.7.8 “ACC Write Protection Mode Register” and Section 41.7.9 “ACC Write Protection Status Register”. Bit 0 name in Section 41.7.9 “ACC Write Protection Status Register” changed from WPROTERR to WPVS. Section 42. “Analog-to-Digital Converter (ADC)” Section 42.1 “Description”: Added sentence: The last channel is internally connected by a temperature sensor. Section 42.2 “Embedded Characteristics”: updated section with new characteristics Section 42.6.3 “Conversion Resolution”: Modified content to limit information on 12-bit resolution. Section 42.6.14 “Register Write Protection”: Reworked content. Section 42.7.3 “ADC Channel Sequence 1 Register” and Section 42.7.4 “ADC Channel Sequence 2 Register”: modified max channel number to 15. Section 42.7.12 “ADC Interrupt Status Register”: updated ‘ENDRX’ and ‘RXBUFF’ bit descriptions. Section 42.7.15 “ADC Compare Window Register”: updated ‘LOWTHRES’ and ‘HIGHTHRES’ field descriptions. Section 42.7.20 “ADC Write Protection Mode Register” and Section 42.7.21 “ADC Write Protection Status Register”: Modified register names (from Write Protect to Write Protection). Reworked field descriptions. 1250 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 49-6. Doc. Date SAM4S Datasheet Rev. 11100F 29-Jan-14 Revision History (Continued) Changes Section 43. “Digital-to-Analog Converter Controller (DACC)” Section 43.7.7 “DACC Interrupt Enable Register”, Section 43.7.8 “DACC Interrupt Disable Register” and Section 43.7.9 “DACC Interrupt Mask Register”: modified bit descriptions. Rework of all “refresh” related paragraphs, Section 43.7.3 “DACC Channel Enable Register” and Section 43.6.7 “DACC Timings”. Modified description for ”REFRESH: Automatic Refresh Period” field in Section 43.7.2 “DACC Mode Register”. Re-worked Section 43.6.8 “Register Write Protection” and associated registers and bit/field descriptions in Section 43.7.12 “DACC Write Protection Mode Register” and Section 43.7.13 “DACC Write Protection Status Register”. Section 44. “Electrical Characteristics” Added Section 44.2 “Recommended Operating Conditions”. Section 44.4 “Power Consumption”: Added power consumption values for SAM4S4/SAM4S2. Updated Section 44.4.1 “Backup Mode Current Consumption”. Removed Supply Ripple Voltage parameter from Table 44-30, “3 to 20 MHz Crystal Oscillator Characteristics” Table 44-32 ”XIN Clock Electrical Characteristics (In Bypass Mode)”: Added CPARASTANDBY AND RPARASTANDBY parameters. Updated and re-worked Section 44.8 “12-bit ADC Characteristics”: Updated Section 44.9 “12-bit DAC Characteristics”. Removed Max Voltage Ripple parameter from Table 44-55, “Analog Power Supply Characteristics”. Added Refresh Time to Table 44-56, “Channel Conversion Time and DAC Clock”. In Section 44.12 “AC Characteristics” modified  Table 44-64, “SPI Timings”.  Table 44-65, “SSC Timings”  Table 44-66, “SMC Read Signals - NRD Controlled (READ_MODE = 1)”  Table 44-68, “SMC Write Signals - NWE Controlled (WRITE_MODE = 1)”  Table 44-69, “SMC Write Signals - NCS Controlled (WRITE_MODE = 0)”  Table 44-70, “USART SPI Timings” Table 44-71 ”Two-wire Serial Bus Requirements”: Added parameter tBUF Section 44.12.9 “Embedded Flash Characteristics”: modified Table 44-72, “Embedded Flash Wait State at 105°C”. Table 44-73, “AC Flash Characteristics”: Full Chip Erase: Added values for 256 Kbytes and 128 Kbytes. Added new parameter Page Program Time. Section 45. “Mechanical Characteristics” Table 45-20 ”64-ball WLCSP Package Dimensions (in mm)” Added body size for SAM4S4 for WLCSP64 package. Figure 45-8 ”48-lead LQFP Package Drawing” and corresponding characteristics added. Figure 45-9 ”48-lead QFN Package Drawing” and corresponding characteristics added. Section 48. “Errata” Added Section 48.3 “Errata SAM4S4/S2 Rev. A Parts”. Section 47. “Ordering Information” Added information on carrier type availability. Updated Table 47-1 ”Ordering Codes for SAM4S Devices”. Added new ordering codes for SAM4S4 and SAM4S2 devices. SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1251 Table 49-7. SAM4S Datasheet Rev. 11100E 24-Jul-13 Revision History Doc. Rev. 11100E Comments Change Request Ref. Introduction Added WLCSP64 package in Section “Features”, Table 1-1, “Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices”, added Figure 4-6 and Table 4-5, “SAM4S16/S8 64-ball WLCSP Pinout”. 8620 Updated Section 5.6 “Low-power Modes”. Added information on WFE. 9073 Added 2nd paragraph in Section 6.1 “General Purpose I/O Lines”. 8992 RTC Added new bullet “Safety/security features” in Section 16.2 “Embedded Characteristics”. 8544 Last sentence added in Section 16.5.3 “Alarm”. 8900 Added note in Section 16.5.3 “Alarm”, Section 16.6.5 “RTC Time Alarm Register” and Section 16.6.6 “RTC Calendar Alarm Register”. 9027 Replaced values for temperature range with a generic term in Section 16.5.7 “RTC Accurate Clock Calibration”. 9033 Block diagram centered for readability in Section 16.3 “Block Diagram”. rfo PMC Section 28.4.2 “Slow Clock Crystal Oscillator”, replaced “...in MOSCSEL bit of CKGR_MOR,...” with “...in XTALSEL bit of SUPC_CR,...” in the last phrase of the 3d paragraph. 9069 Section 28.4.2 “Slow Clock Crystal Oscillator”, added references on the OSCSEL bit of PMC_SR in the 3d paragraph. rfo Register names in Clock Generator: Replaced “PLL_MCKR” with “PMC_MCKR” and “PLL_SR” with “PMC_SR” 8970 in Section 28.5.6 “Software Sequence to Detect the Presence of Fast Crystal” In Section 28.6.1 “Divider and Phase Lock Loop Programming”, 3rd bullet, replaced PMC_IER with PMC_SR. 8963 Deleted previous 4th bullet (was useless sentence “Disable and then enable the PLL...”). In Figure 28-3 and Section 28.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator” paragraph 5, replaced MOSCXTCNT with MOSCXTST. Added code example in step 1. of Section 29.14 “Programming Sequence”. Corrected reset value of CKGR_MOR register in Table 29-3, “Register Mapping”. Corrected value of PLLA(B)COUNT field description in Section 29.17.9 “PMC Clock Generator PLLA Register” and Section 29.17.10 “PMC Clock Generator PLLB Register”. Added a note in Section 29.17.8 “PMC Clock Generator Main Clock Frequency Register” and reworked a paragraph in Section 28.5.2 “Fast RC Oscillator Clock Frequency Adjustment” 8447 8564 8853 Electrical Characteristics rfo Changed 85°C temperatures with 105°C in the whole chapter. Added read/write characteristics temperature information on Flash in Note (3), Table 44-3, “DC Characteristics” and Note (1), Table 44-73, “AC Flash Characteristics”. Modified Section 44.4.1 “Backup Mode Current Consumption” and Table 44-9 to Table 44-23 with up-to-date current consumption values. rfo Updated Section 44.4.2.1 “Sleep Mode”. Added Section 44.4.3.1 “SAM4S4/2 Active Power Consumption”. rfo In Section 44.4.4 “Peripheral Power Consumption in Active Mode”, updated Table 44-24, “Typical Power Consumption on VDDCORE (VDDIO = 3.3V, TA = 25°C)” rfo Mechanical Characteristics 1252 Added Figure 45-6 and associated package dimensions and soldering tables for WLCSP64 package. 8620 Soldering tables updated in Section 45. “Mechanical Characteristics”. rfo SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 49-7. SAM4S Datasheet Rev. 11100E 24-Jul-13 Revision History (Continued) Change Request Ref. Doc. Rev. 11100E Comments Ordering Information New ordering codes (105 °C, reel conditioning, WLCSP package) added in Table 47-1, “Ordering Codes for SAM4S Devices”. 8620, rfo Errata Added Section Issue: “Watchdog Not Stopped in Wait Mode” and Section Issue: “Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected”. 9075 Backpage ARMConnected® logo and corresponding text deleted. Table 49-8. rfo SAM4S Datasheet Rev. 11100D 15-Apr-13 Revision History Change Request Ref. Doc. Rev. 11100D Comments Introduction Deleted sleep mode for fast start-up in Section 5.8 “Fast Start-up”. 8763 Added 32 kHz trimming features in Section “Features”. rfo Notes added in Section 8.1.3.1 “Flash Overview”, below Figure 8-3. Electrical Characteristics In Table 43-26, added 2 lines describing CPARASTANDBY and RPARASTANDBY parameters. 8614 In Table 43-62, Endurance line, deleted “Write/erase... @ 25°C” and 100k value. 8850 In Table 43-62, added Write Page Mode values. 8860 Errata Deleted former Chapter 45 “SAM4S Series Errata” (was only a cross-reference to Engineering Samples Erratas), added a new detailed Section 48. “Errata”. 8645 Backpage ARMPowered® logo replaced with ARMConnected® logo, corresponding text updated. rfo SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1253 Table 49-9. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History Doc. Rev. 11100C Comments Change Request Ref. Introduction In Section 2. “Block Diagram”, USB linked to Peripheral Bridge instead of AHB Bus Matrix in Figure 2-3, Figure 8386 2-4, Figure 3. and Figure 2-2. Reference to the LPM bit removed in the whole datasheet. 8392 Flash rails mentioned in Section 5.1 “Power Supplies”. 8406 Section 9. “Real Time Event Management” created. 8439 WKUP[15:0] pins added on each block diagram in Section 2. “Block Diagram” and in Table 3-1, “Signal Description List”. 8459 All diagrams updated with Real Time Events in Section 2. “Block Diagram”. 8484 JTAG and PA7 pins details added in Section 6.2.1 “Serial Wire JTAG Debug Port (SWJ-DP) Pins”. 8547 CORTEX Section 12.8.3 “Nested Vectored Interrupt Controller (NVIC) User Interface”, offset information for NVIC register 8211 mapping updated in Table 12-31 ”Nested Vectored Interrupt Controller (NVIC) Register Mapping”. Section 12.9.1 “System Control Block (SCB) User Interface”, deleted lines with MMFSR, BFSR, UFSR and updated the note in Table 12-32, “System Control Block (SCB) Register Mapping”. Table 12-34 ”System Timer (SYST) Register Mapping”: table name updated (SysTick changed to SYST). Harmonized instructions code fonts in Section 12.6 “Cortex-M4 Instruction Set”. Fixed various typos. 8343 RTT RTC 1Hz calibrated clock feature added in Section 15.1 “Description”, Section 15.4 “Functional Description” and in RTT_MR register, see Section 15.5.1 “Real-time Timer Mode Register”. RTC New bullet “Safety/security features” added in Section 16.2 “Embedded Characteristics”. 8544 WDT Note added in Section 17.5.3 “Watchdog Timer Status Register”. 8128 SUPC Offsets updated and SYSC_WPMR in Table 18-1 ”System Controller Registers”. Section 18.4.9 “System Controller Write Protection Mode Register” added. 8253 Force Wake Up Pin removed from Section 18.1 “Embedded Characteristics”. 8263 In Section 18.3.3 “Core Voltage Regulator Control/Backup Low-power Mode”, removed informations related to 8363, 8407 WFE and WFI, deleted reference to 1.8V for voltage regulator. Figure 18-1 Block Diagram updated. 8515 EEFC 1254 In Section 20.5.2 “EEFC Flash Command Register”, table added in FCMD bitfield, details added in table in FARG bitfield. 8352 Note concerning bit number limitation added in Section 20.4.3.5 “GPNVM Bit”. 8390 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 49-9. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History (Continued) Change Request Ref. Doc. Rev. 11100C Comments CMCC Updated access condition from Write-only to Read-only in Section 22.5.4 “Cache Controller Status Register” and Section 22.5.10 “Cache Controller Monitor Status Register”. Index bitfield size increased from 4 to 5 bits in Section 22.5.6 “Cache Controller Maintenance Register 1”, bitfield description completed. 8373 “0xXX - 0xFC” offset replaced with “0x38 - 0xFC” in the last row in Table 22-1 ”Register Mapping”. In Figure 22- rfo 1, replaced “Cortex MPPB” with “APB Interface” in Block Diagram. CRCCU TRWIDTH bitfield description table completed in Section 23.6.2 “Transfer Control Register”. 8303 Updated Section 23.1 “Description” and Section 23.5.2 “CRC Calculation Unit Operation”. rfo PDC Offset data for Register Mapping updated in Table 27-1 ”Register Mapping”. 7976 “ABP bridge” changed to “APB bridge” in Section 27.1 “Description”. rfo PMC Section 28.5.6 “Software Sequence to Detect the Presence of Fast Crystal” added. 8371 Updated CKGR_MOR register reset value to 0x0000_0008 in Section 29.17 “Power Management Controller (PMC) User Interface”. 8448 CHIPID Section 30.3.1 “Chip ID Register”, in ARCH bitfield description table, rows sharing SAM3/SAM4 names reconfigured with standalone rows for each name. Section 30.3.1 “Chip ID Register”, in ARCH bitfield description table, various devices added or removed. 7730 7977, 8034, 8383 Section 30.3.1 “Chip ID Register”, in SRAMSIZ bitfield description table, replaced 1K/1Kbyte with 192K/192Kbyte for value1. 8036 In Section 30.2 “Embedded Characteristics”, updated Table 30-1 ”SAM4S Chip ID Registers”. rfo PIO DSIZE bit description updated in Section 31.7.49 “PIO Parallel Capture Mode Register”. 7705 Section 31.4.2 “External Interrupt Lines” added. Section 31.4.4 “Interrupt Generation” updated. rfo SSC Removed Table 30-4 in Section 32.7.1.1 “Clock Divider”. 7303 Last line (PDC register) updated in Table 32-5 ”Register Mapping”. 7971 Reworked tables and bitfield descriptions in Section 32.9.3 “SSC Receive Clock Mode Register”, Section 32.9.4 “SSC Receive Frame Mode Register”, Section 32.9.5 “SSC Transmit Clock Mode Register”, Section 32.9.6 “SSC Transmit Frame Mode Register”. 8466 SPI In Section 33.2 “Embedded Characteristics”, added the 2 first bullets, deleted the previous last bullet. 8544 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1255 Table 49-9. SAM4S Datasheet Rev. 11100C 09-Jan-13 Revision History (Continued) Doc. Rev. 11100C Comments Change Request Ref. TWI NVIC and AIC changed to Interrupt Controller. Section 33.10.4.5 “PDC” removed. “This bit is only used in Master mode” removed from bitfields ENDRX, ENDTX, RXBUFF, and TXBUFE in Section 34.11.6 “TWI Status Register”. Figure 34-23 updated: SVREAD = 1 and first occurrence of RXRDY = 1. 7844 7884 Removed “20” at the end of the 1st paragraph in Section 34.1 “Description”. 7921 Table 34-7 ”Register Mapping”, replaced “0x100 - 0x124” with “0x100 - 0x128” and “Reserved for the PDC” with 7973 “Reserved for PDC registers” in the PDC line. Section 34.10.6 “Using the Peripheral DMA Controller (PDC) in Slave Mode” reworked. rfo UART Table 35-3 ”Register Mapping”, PDC registers info for register mapping updated. 7967 USART Section 36.7.1 “Baud Rate Generator”, replaced “or 6” with “or 6 times lower” in the last phrase. rfo HSMCI Phrase “not only for Write operations now” removed from NOTBUSY bitfield descriptionI in Section 38.14.12 “HSMCI Status Register”. 8394 replaced BCNT bitfield table with the corresponding description and updated Warning note in BCNT bitfield description in Section 38.14.7 “HSMCI Block Register”. 8431 In Section 38.6.3 “Interrupt”, replaced references to NVIC/AIC with “interrupt controller”. rfo PWM Typo corrected in line Timer0 in Table 39-4 ”Fault Inputs”. 8438 Replaced ‘Main OSC’ with ‘Main OSC (PMC)’ in Table 39-4 ”Fault Inputs”. rfo UDP Pull-up’ and ‘pull-down’ spelling harmonized in the whole chapter. 7867 Added UDP_CSRx (ISOENDPT) alternate register in Section 40.7.11 “UDP Endpoint Control and Status Register (ISOCHRONOUS)”. 8414 ADC Removed “...and EOC bit corresponding to the last converted channel” from the last phrase of the third paragraph in Section 42.6.4 “Conversion Results”. 8357 TRANSFER value set to 2 in TRANSFER bitfield description in Section 42.7.2 “ADC Mode Register”. 8462 Text amended in Section 42.1 “Description”. rfo SLEEP and FWUP bitfield description texts in tables updated in Section 42.7.2 “ADC Mode Register”. Electrical Characteristics Whole chapter reworked to add SAM4SD32/SD16/SA16 data, various values added or updated. rfo, 8435 Clext values changed in Table 44-30. 8391 Configurations A and B updated in Section 44.4.1 “Backup Mode Current Consumption”. 8422 Mechanical Characteristics QFN64 package drawing and table updated in Figure 45-5. 1256 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 8529 . Table 49-10. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History Change Request Ref. Doc. Rev. 11100B Comments Introduction 48 pins packages (SAM4S16A and SAM4S8A devices) removed. 8100 Write Protected Registers added in “Description” on page 1. 8213 Note related to EWP and EWPL commands added in Section 8.1.3.1 “Flash Overview” on page 38. 8225 References to WFE instructions replaced by relevant bits precise descriptions. 8275 Dual bank and cache memory mentioned in “Description” on page 1 and “Configuration Summary” on page 4. rfo Flash and SRAM memory sizes updated in “Description” on page 1 and “Configuration Summary” on page 4. 1 µA instead of 3 in “Description” on page 1, Section 5.3 on page 27 and Section 5.6.1 on page 30. Table titles and sub-section titles updated with new devices. New block diagram added in Figure 2-2 on page 6. VFBGA100 package added: Figure 4-3 on page 17 and Table 4-3 on page 20 added. Reference to CortexM3 deleted and VDDIO value added in Section 5.6.1 “Backup Mode” on page 30. Entering Wait Mode process updated and current changed from 15 to 32 µA in Section 5.6.2 on page 30. Added paragraph detailing mode selection with FLPM value in Section 5.6.3 on page 31. Values added and notes updated in Table 5-1 on page 32. Third paragraph frequency values updated in Section 6.1 on page 34. SRAM upper address changed to 0x20400000, and EFC1 added in Figure 7-1 on page 37. Note added in Section 8.1.3.1 “Flash Overview” on page 38. New devices features added in Section 8.1.1 “Internal SRAM” on page 38, Section 8.1.3.1 “Flash Overview” on page 38, Section 8.1.3.4 “Lock Regions” on page 42, Section 8.1.3.5 “Security Bit” on page 42, Section 8.1.3.11 “GPNVM Bits” on page 43. EEFC replaced by EEFC0 and EEFC1 in Table 11-1 on page 48. ‘Cortex M-4’ changed for ‘Cortex-M4’ in block diagrams: Figure 2-3 on page 7 and Figure 2-4 on page 8. rfo Section 5.6.4 “Low-power Mode Summary Table”, updated the list of potential wake up sources for Sleep Mode rfo in Table 5-1 on page 32. Added references to S16 in the flash size description in Section 8.1.3.1 “Flash Overview”. rfo Section 2. “Block Diagram”, replaced “Time Counter B” by “Time Counter A” in Figure 2-3 on page 7. rfo Fixed the section structure for Section 5.6.3 “Sleep Mode”. rfo CORTEX FPU related instructions deleted in Table 12-13 on page 87. 8252 Fonts style corrected for instructions code in the whole chapter. rfo Updated Figure 12-9 on page 97. rfo RSTC Updated for dual core. 8306 EXTRST field description updated in Section 14.5.1 “Reset Controller Control Register” on page 283. 8340 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1257 Table 49-10. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History (Continued) Doc. Rev. 11100B Comments Change Request Ref. RTC In Section 16.6.2 “RTC Mode Register” on page 303, formulas associated with conditions HIGHPPM = 1 and HIGHPPM = 0 have been swapped, text has been clarified. 7950 In Section 16.5.7 “RTC Accurate Clock Calibration” on page 299, paragraph describing RTC clock calibration circuitry correction updated with mention of crystal drift. 7952 SUPC References to WFE instructions deleted in Section 18.3.3 “Core Voltage Regulator Control/Backup Low-power rfo Mode” on page 328. Supply monitor threshold values modified in Section 18.3.4 “Supply Monitor” on page 328. SMTH bit table replaced by a cross-reference to Electrical characteristics in Section 18.4.4 “Supply Controller Supply Monitor Mode Register” on page 338. Typo in Section 18.4.8 “Supply Controller Status Register” on page 343 is now fixed. 8024 “half” replaced with “first half” in Section 18.4.6 “Supply Controller Wake-up Mode Register” on page 340 and in 8067 Section 18.4.7.2 “Low Power Debouncer Inputs” on page 295. Figure 18-4 on page 331 modified. Push-to-Break figure example Figure 18-6 on page 333 added, title of Figure 18-5 on page 333 modified. 8064, 8082 “square waveform ..” changed to “duty cycle ..” in Section 18.4.7.2 “Low Power Debouncer Inputs” on page 295. 8082 Switching time of slow crystal oscillator updated in Section 18.3.2 “Slow Clock Generator” on page 328. 8266 8226 EEFC Added GPNVM command line in Section • “FARG: Flash Command Argument” on page 368. 8076 Unique identifier address changed in Section 20.4.3.8 “Unique Identifier” on page 363. 8274 User Signature address changed in Section 20.4.3.9 “User Signature” on page 363. Changed the System Controller base address from 0x400E0800 to 0x400E0A00 in Section 20.5 “Enhanced Embedded Flash Controller (EEFC) User Interface” on page 365. rfo FFPI All references, tables, figures related to 48-bit devices cleared in this whole chapter. rfo CMCC New chapter. CRCCU 7803 Typos: CCIT802 corrected to CCITT802, CCIT16 corrected to CCITT16 in Section 23.5.1 “CRC Calculation Unit” on page 399 and Section 23.7.10 “CRCCU Mode Register” on page 414. TRC_RC corrected to TR_CRC in Section 23.7.10 “CRCCU Mode Register” on page 414. SMC 1258 “turned out” changed to “switched to output mode” in Section 26.8.4 “Write Mode” on page 450. 7925 Removed DBW which is not required for 8-bit only in Section 26.15.4 “SMC MODE Register” on page 476. 8307 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Table 49-10. SAM4S Datasheet Rev. 11100B 31-Jul-12 Revision History (Continued) Change Request Ref. Doc. Rev. 11100B Comments PMC Added a note in Section 29.17.7 “PMC Clock Generator Main Oscillator Register” on page 528. 7848 Max MULA/MULB value changed from 2047 to 62 in Section 29.17.9 “PMC Clock Generator PLLA Register” on 8064 page 531 and Section 29.17.10 “PMC Clock Generator PLLB Register” on page 532. Step 5 in Section 28.2.13 “Programming Sequence” on page 463: Master Clock option added in CSS field. 8170 Third paragraph added in Section 28.2.12 “Main Crystal Clock Failure Detector” on page 462. WAITMODE bit added in Section 29.17.7 “PMC Clock Generator Main Oscillator Register” on page 528. 8208 CHIPID Table 30-1 on page 552 modified. rfo TC Changed TIOA1 in TIOB1 in Section 37.6.14.1 “Description” on page 860 and Section 37.6.14.4 “Position and 8101 Rotation Measurement” on page 865. PWM Font size enlarged in Figure 39-14 on page 964. 7910 “CMPS” replaced with “CMPM” in whole document. 8021 ADC EOCAL pin and description added in Section 42.7.12 “ADC Interrupt Status Register” on page 1106. rfo PDC register row added in Section 42.7 “Analog-to-Digital Converter (ADC) User Interface” on page 1092. 7969 Added comment in Section 42.7.15 “ADC Compare Window Register” on page 1109. 8045 Features added in Section 42.2 “Embedded Characteristics” on page 1077. 8088 Comments added, and removed “offset” in Section 42.6.11 “Automatic Calibration” on page 1090. 8133 Electrical Characteristics Whole chapter updated. In tables, values updated, and missing values added. 8085, 8245 Comment for flash erasing added in Section 44.12.9 “Embedded Flash Characteristics” on page 1199. 8223 Updated conditions for VLINE-TR and VLOAD-TR in Table 44-4 on page 1143. rfo Removed the “ADVREF Current” row from Table 43-30 on page 1059. rfo Updated the “Offset Error” parameter description in Table 43-32 on page 1061. Updated the TACCURACY parameter description in Table 44-6 on page 1144. Updated the temperature sensor description in Section 44.11 “Temperature Sensor” on page 1180 and the slope accuracy parameter data in Table 44-60 on page 1180. rfo Mechanical Characteristics 48 pins packages (SAM4S16A and SAM4S8A devices) removed. 8100 100-ball VFBGA package drawing added in Figure 45-3 on page 1203. rfo Ordering Information Table 47-1 on page 1216 completed with new devices and reordered. rfo Errata rfo Removed the Flash Memory section. Removed the Errata section and added references for two separate errata documents in Section 47. “Ordering rfo Information” on page 1216. Specified the preliminary status of the datasheet. rfo SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1259 Table 49-11. SAM4S Datasheet Rev. 11100A 28-Oct-11 Revision History Doc. Rev. 11100A Comments First issue. 1260 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 Change Request Ref. Table of Contents Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Safety Features Highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 4.2 4.3 5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 6. 100-lead Packages and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 64-lead Packages and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 48-lead Packages and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Powering Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 29 30 30 33 33 Input/Output Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 6.2 6.3 6.4 6.5 6.6 General Purpose I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anti-tamper Pins/Low-power Tamper Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 37 37 37 37 7. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 8.2 9. Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 External Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Real Time Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 9.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Real Time Event Mapping List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10. System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 10.2 System Controller and Peripheral Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power-on-Reset, Brownout and Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.1 11.2 Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Peripheral Signal Multiplexing on I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1261 12. ARM Cortex-M4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Cortex-M4 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Cortex-M4 Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 System Control Block (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 System Timer (SysTick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 13. Debug and Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 13.1 13.2 13.3 13.4 13.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 267 268 269 270 14. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.1 14.2 14.3 14.4 14.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 275 275 276 281 15. Real-time Timer (RTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 15.1 15.2 15.3 15.4 15.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 285 285 286 288 16. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 16.1 16.2 16.3 16.4 16.5 16.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 293 294 294 294 302 17. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 17.1 17.2 17.3 17.4 17.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 319 320 321 323 18. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 18.1 1262 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 18.2 18.3 18.4 18.5 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 329 330 339 19. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 19.1 19.2 19.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 General Purpose Backup Registers (GPBR) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 20. Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 20.1 20.2 20.3 20.4 20.5 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enhanced Embedded Flash Controller (EEFC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 352 352 353 370 21. Fast Flash Programming Interface (FFPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 21.1 21.2 21.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Parallel Fast Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 22. Cortex-M Cache Controller (CMCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 22.1 22.2 22.3 22.4 22.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cortex-M Cache Controller (CMCC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 385 386 386 388 23. Cyclic Redundancy Check Calculation Unit (CRCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 23.1 23.2 23.3 23.4 23.5 23.6 23.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 CRCCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 CRCCU Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 Transfer Control Registers Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface . . . . . . . . . . . . . . . . . . . . . . 408 24. Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 24.1 24.2 24.3 24.4 24.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware and Software Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 424 424 425 426 25. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 25.1 25.2 25.3 25.4 25.5 25.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master/Slave Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Bus Granting Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 430 431 431 432 433 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1263 25.7 25.8 Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Bus Matrix (MATRIX) (MATRIX) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 26. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 26.10 26.11 26.12 26.13 26.14 26.15 26.16 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection to External Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Read and Write Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambling/Unscrambling Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 443 444 444 445 446 446 448 450 459 459 464 468 474 476 479 27. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 27.1 27.2 27.3 27.4 27.5 27.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral DMA Controller Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral DMA Controller (PDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 490 491 492 493 495 28. Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 28.1 28.2 28.3 28.4 28.5 28.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divider and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 506 507 508 509 513 29. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 29.9 29.10 29.11 29.12 29.13 29.14 1264 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SysTick Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Free-Running Processor Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Clock Output Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup from Embedded Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Clock Failure Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 515 515 516 516 517 517 517 518 518 518 518 520 520 522 29.15 Clock Switching Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 29.16 Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 29.17 Power Management Controller (PMC) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 30. Chip Identifier (CHIPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 30.1 30.2 30.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 31. Parallel Input/Output Controller (PIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 31.1 31.2 31.3 31.4 31.5 31.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 32. Synchronous Serial Controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 32.1 32.2 32.3 32.4 32.5 32.6 32.7 32.8 32.9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 SSC Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 Synchronous Serial Controller (SSC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 33. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 33.1 33.2 33.3 33.4 33.5 33.6 33.7 33.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 687 688 688 689 689 691 704 34. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 34.1 34.2 34.3 34.4 34.5 34.6 34.7 34.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-wire Interface (TWI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 719 720 720 720 721 721 746 35. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . 761 35.1 35.2 35.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1265 35.4 35.5 35.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . . . . . . . . . . . . . . . . . . 768 36. Universal Synchronous Asynchronous Receiver Transceiver (USART) . . . . . . . . . 779 36.1 36.2 36.3 36.4 36.5 36.6 36.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface . . . . . . . . . 814 37. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 37.1 37.2 37.3 37.4 37.5 37.6 37.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter (TC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 851 852 853 853 854 875 38. High Speed Multimedia Card Interface (HSMCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 38.1 38.2 38.3 38.4 38.5 38.6 38.7 38.8 38.9 38.10 38.11 38.12 38.13 38.14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed MultiMedia Card Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD/SDIO Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Boot Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Transfer Done Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed MultiMedia Card Interface (HSMCI) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . 905 905 906 907 907 908 908 911 918 919 920 921 923 924 39. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 39.1 39.2 39.3 39.4 39.5 39.6 39.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulation Controller (PWM) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 953 954 954 954 957 980 40. USB Device Port (UDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 40.1 40.2 40.3 40.4 1266 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1028 1028 1029 1030 40.5 40.6 40.7 Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032 USB Device Port (UDP) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 41. Analog Comparator Controller (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 41.1 41.2 41.3 41.4 41.5 41.6 41.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Comparator Controller (ACC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 1069 1069 1070 1070 1071 1072 42. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 42.1 42.2 42.3 42.4 42.5 42.6 42.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital (ADC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 1084 1085 1085 1086 1087 1097 43. Digital-to-Analog Converter Controller (DACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121 43.1 43.2 43.3 43.4 43.5 43.6 43.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-to-Analog Converter Controller (DACC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121 1121 1122 1122 1122 1124 1126 44. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142 44.1 44.2 44.3 44.4 44.5 44.6 44.7 44.8 44.9 44.10 44.11 44.12 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLLA, PLLB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-bit DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142 1142 1143 1149 1163 1169 1170 1172 1181 1183 1183 1184 45. Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204 45.1 45.2 45.3 45.4 45.5 45.6 100-lead LQFP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100-ball TFBGA Mechanical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100-ball VFBGA Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-lead LQFP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-lead QFN Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-ball WLCSP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204 1205 1206 1208 1210 1211 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 1267 45.7 45.8 45.9 45.10 48-lead LQFP Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-lead QFN Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214 1216 1217 1217 46. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218 47. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 48. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 48.1 48.2 48.3 48.4 Errata SAM4SD32/SD16/SA16/S16/S8 Rev. A Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errata SAM4SD32/SD16/SA16/S16/S8 Rev. B Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errata SAM4S4/S2 Rev. A Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errata SAM4S4/S2 Rev. B Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 1226 1229 1231 49. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261 1268 SAM4S Series [DATASHEET] Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15 ARM Connected Logo XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15. 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