ATSAMA5D31A-CFUR

ARM-based Embedded MPU SAMA5D3 Series DATASHEET Description The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM® Cortex®-A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its lowpower consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are five SAMA5D3 devices in this series. Table 1-1 “SAMA5D3 Device Differences” shows the differences in the embedded features. All other features are available on all derivatives; this includes the three USB ports as well as the encryption engine and secure boot features. 11121C–ATARM–15-Oct-13 1. Features  Core  ARM® Cortex®-A5 Processor with ARM v7-A Thumb2® Instruction Set  32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)  Fully Integrated MMU and Floating Point Unit (VFPv4)      CPU Frequency up to 536 MHz Memories  One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on 8-bit NAND Flash, SDCard, eMMC, serial DataFlash®, selectable Order  One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed  High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 with datapath scrambling  Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to 24-bit Error Correcting Code (PMECC) System running up to 166 MHz  Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock  Boot Mode Select Option, Remap Command  Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator  Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator  One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed  39 DMA Channels including two 8-channel 64-bit Central DMA Controllers  64-bit Advanced Interrupt Controller  Three Programmable External Clock Signals  Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer Low Power Management  Shut Down Controller  Battery Backup Registers  Clock Generator and Power Management Controller  Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Peripherals  LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion  ITU-R BT. 601/656 Image Sensor Interface  Three HS/FS/LS USB Ports with On-Chip Transceivers  One Device Controller  One Host Controller with Integrated Root Hub (3 Downstream Ports)  One 10/100/1000 Mbps Gigabit Ethernet MAC Controller (GMAC) with IEEE1588 support  One 10/100 Mbps Ethernet MAC Controller (EMAC)  Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B  Softmodem Interface  Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0)  Two Master/Slave Serial Peripheral Interfaces  Two Synchronous Serial Controllers  Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS  Four USARTs, two UARTs, one DBGU  Two Three-channel 32-bit Timer/Counters  One 4-channel 16-bit PWM Controller SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 2    Safety  Power-on Reset Cells  Independent Watchdog  Main Crystal Clock Failure Detection  Write Protection Registers  SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)  Memory Management Unit Security  TRNG: True Random Number Generator  Encryption Engine    One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function  AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications  TDES: Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications Atmel® Secure Boot Solution I/O  Five 32-bit Parallel Input/Output Controllers  160 I/Os  Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input  Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering  Slew Rate Control on High Speed I/Os  Impedance Control on DDR I/Os Package  324-ball LFBGA, 15 x 15 x 1.4 mm, pitch 0.8 mm  324-ball TFBGA, 12 x 12 x 1.2 mm, pitch 0.5 mm Table 1-1. SAMA5D3 Device Differences Peripherals SAMA5D31 SAMA5D33 SAMA5D34 SAMA5D35 SAMA5D36 CAN0, CAN1 — — X X X EMAC X — — X X GMAC — X X X X HSMCI2 X — X X X LCDC X X X — X TC1 — — — X X UART0, UART1 X — — X X SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 3 2. Block Diagram SysC FIQ IRQ HS Trans HS Trans In-Circuit Emulator Cortex-A5 ICache 32 KB PLLA PLLUTMI Osc12 MHz VFP WDT DCache 32 KB MMU BIU PMC HS EHCI USB HOST HS USB Device DMA DMA EMAC 10/100 DDR_DQM[3..0] DDR_DQS[3..0] DDR_DQSN[3..0] DDR_CS DDR_CLK,DDR_CLKN DDR_CKE DDR_RAS, DDR_CAS DDR_WE DDR_BA[2..0] LCD ISI DMA DMA DMA DMA DDR2 LPDDR2 512 MB EBI PIT 4 GPBR RC OSC 32K VDDBU GMAC 10/100/1000 I/D 12 MHZ RC Osc XIN32 XOUT32 SHDN WKUP DDR_VREF DDR_A0-DDR_A13 DDR_D0-DDR_D31 PIO PA PC PB DBGU PCK0-PCK2 XIN XOUT HS Trans AIC PIO DRXD DTXD JTAG / SWD DH S DH DP SD /HH M/ SD HH PA G1 SD 25 MA GT CK -G X GT CK 12 5 X GC EN GRX CKO -G C GRRS, TX K X G E GR ER CO R - L GT X0- GRX X GR D GM 0-G X7 V D TX7 ER C, G M ET EFC DI O X K EC EN R ER SD V, X E T 0- E E R X R X EM 0-ET X1 ER DC X1 ,E LC MD LCD-D D_ AT0 IO LC V -L D_ SY CD LC PC NC _ D_ K , L DA DE , LC CD T23 N, D_ _H LC D S IS I_D D_ ISP YN C PW IS OI_P IS M I _ C IS I_H K D11 SY NC , IS I_V SY NC DD R_ CA LP DD R_ CA LN BMS HH S HH DPC SD H H MC HH SDP SD B MB VB G TST NT RS T TD I TD O TM TC S/SW K/S D WC IO LK JTA GS EL Figure 2-1. SAMA5D3 Block Diagram NAND Flash Controller MCL/SLC ECC (4 KB SRAM) Multi-Layer Matrix SHDC RTC POR RSTC NRST POR TRNG PIOB PIOD SRAM0 64 KB ROM 160 KB SRAM1 64 KB 8-CH DMA0 8-CH DMA1 Peripheral (1) Bridges SHA AES TDES Reduced Static Memory Controller DMA PIO PIOA PIOC D0-D15 A21/NANDALE A22/NANDCLE NRD/NANDOE NWE/NWR0/NANDWE NCS3/NANDCS NANDRDY A0/NBS0 A1-A20 A23-A25 NWR1/NBS1 NCS0,NCS1,NCS2 NWAIT PIOE DMA CAN0 CAN1 TWI0 TWI1 TWI2 DMA USART0 USART1 USART2 USART3 DMA UART0 UART1 DMA SPI0 SPI1 DMA DMA SSC0 SSC1 MCI0/MCI1/MCI2 SD/SDIO eMMC DMA TC0, TC1 TC2, TC3 TC4, TC5 4-CH PWM Real-time Events DMA 12-CH 12-bit ADC TouchScreen SMD P DIB DI N CA RX NT 0-C X0 A -C NR A X TW NT 1 TW D0 X1 CK -TW 0TW D2 CK CT 2 S RT 03 SCS03 RDK03 X TX 0-3 UR D0 DX -3 0 U NP TX -U CS D0 RD X 1, NP -UT 1 XD CS 1 2, NP C NP S3 CS SP 0 C M K O M SI TK ISO 0 TF -TK TD 0-T 1 F 0 RD -T 1 0 D RF -RD1 0 1 RK -RF 0 1 M -RK CI 1 M 0_C CI D M 1_ A CI C D 2 M _C A C D M I0_ A CI C M MC 1_CK CI I K M 0_D 2_C CI A K M 1_D [7..0 CI A ] 2 [ TI _D 3..0 O A ] TI A0 [3.. O -T 0] B TC 0 IO -T A PW LK0 IOB5 M -TC 5 LK PW H0 5 PW ML PW M 0-P MH FI W 3 0- M PW L3 M TS FI AD 3 TR AD IG 0U AD L 1 AD UR 2 AD LL GP 3 AD A LR 5- D4 G P TS PAD I AD 11 VR EF BN PIO CA SPI0_, SPI1_ Note: 1. Peripheral Bridge 0 (APB0) connects HSMCI0, SPI0, USART0, USART1, TWI0, TWI1, UART0, SSC0, SMD. Peripheral Bridge 1 (APB1) connects HSMCI1, HSMCI2, ADC, SSC1, UART1, USART2, USART3, TWI2, DBGU, SPI1, SHA, AES, TDES. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 4 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Input — Output — Input — Clocks, Oscillators and PLLs XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output Output — VBG Bias Voltage Reference for USB Analog — PCK0–PCK2 Programmable Clock Output Output — Output — Input — Shutdown, Wake-up Logic SHDN Shut-Down Control WKUP Wake-Up Input ICE and JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input — TDI Test Data In Input — TDO Test Data Out Output — TMS/SWDIO Test Mode Select/Serial Wire Input/Output I/O — JTAGSEL JTAG Selection Input — I/O Low Reset/Test NRST Microcontroller Reset TST Test Mode Select Input — NTRST Test Reset Signal Input — BMS Boot Mode Select Input — Debug Unit - DBGU DRXD Debug Receive Data Input — DTXD Debug Transmit Data Output — Advanced Interrupt Controller - AIC IRQ External Interrupt Input Input — FIQ Fast Interrupt Input Input — PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0–PAxx Parallel IO Controller A I/O — PB0–PBxx Parallel IO Controller B I/O — PC0–PCxx Parallel IO Controller C I/O — PD0–PDxx Parallel IO Controller D I/O — PE0–PExx Parallel IO Controller E I/O — External Bus Interface - EBI SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 5 Table 3-1. Signal Description List (Continued) Signal Name Function D0–D15 Data Bus A0–A25 Address Bus NWAIT External Wait Signal Type Active Level I/O — Output — Input Low Static Memory Controller - HSMC NCS0–NCS3 Chip Select Lines Output Low NWR0–NWR1 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS1 Byte Mask Signal Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low DDR2/LPDDR Controller DDR_VREF Reference Voltage Input — DDR_CALP Positive Calibration Reference Input — DDR_CALN Negative Calibration Reference Input — DDR_CK, DDR_CKN DDR2 differential clock Output — DDR_CKE DDR2 Clock Enable Output High DDR_CS DDR2 Controller Chip Select Output Low DDR_BA[2..0] Bank Select Output Low DDR_WE DDR2 Write Enable Output Low DDR_RAS, DDR_CAS Row and Column Signal Output Low DDR_A[13..0] DDR2 Address Bus Output — DDR_D[31..0] DDR2 Data Bus I/O — DQS[3..0] Differential Data Strobe I/O — DQSN[3..0] DQSN must be connected to DDR_VREF for DDR2 memories I/O — DQM[3..0] Write Data Mask Output — High Speed Multimedia Card Interface - HSMCI0–2 MCI0_CK, MCI1_CK, MCI2_CK Multimedia Card Clock I/O — MCI0_CDA, MCI1_CDA, MCI2_CDA Multimedia Card Command I/O — MCI0_DA[7..0] Multimedia Card 0 Data I/O — MCI1_DA[3..0] Multimedia Card 1 Data I/O — MCI2_DA[3..0) Multimedia Card 2 Data I/O — SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 6 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level I/O — Universal Synchronous Asynchronous Receiver Transmitter - USART0–3 SCKx USARTx Serial Clock TXDx USARTx Transmit Data Output — RXDx USARTx Receive Data Input — RTSx USARTx Request To Send Output — CTSx USARTx Clear To Send Input — Universal Asynchronous Receiver Transmitter - UARTx [1..0] UTXDx UARTx Transmit Data Output — URXDx UARTx Receive Data Input — Synchronous Serial Controller - SSCx [1..0] TDx SSC Transmit Data Output — RDx SSC Receive Data Input — TKx SSC Transmit Clock I/O — RKx SSC Receive Clock I/O — TFx SSC Transmit Frame Sync I/O — RFx SSC Receive Frame Sync I/O — Input — Timer/Counter - TCx [5..0] TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A I/O — TIOBx TC Channel x I/O Line B I/O — Serial Peripheral Interface - SPIx [1..0] SPIx_MISO Master In Slave Out I/O — SPIx_MOSI Master Out Slave In I/O — SPIx_SPCK SPI Serial Clock I/O — SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS[3..1] SPI Peripheral Chip Select Output Low Two-Wire Interface - TWIx [2..0] TWDx Two-wire Serial Data I/O — TWCKx Two-wire Serial Clock I/O — Input — Output — CAN controller - CANx CANRXx CAN input CANTXx CAN output Soft Modem - SMD DIBN Soft Modem Signal I/O — DIBP Soft Modem Signal I/O — Output — Pulse Width Modulation Controller - PWMC PWMH[3..0] PWM Waveform Output High SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 7 Table 3-1. Signal Description List (Continued) Signal Name Function PWML[3..0] PWM Waveform Output Low PWMFIx PWM Fault Input Type Active Level Output — Input — USB Host High Speed Port - UHPHS HHSDPA USB Host Port A High Speed Data + Analog — HHSDMA USB Host Port A High Speed Data - Analog — HHSDPB USB Host Port B High Speed Data + Analog — HHSDMB USB Host Port B High Speed Data - Analog — HHSDPC USB Host Port C High Speed Data + Analog — HHSDMC USB Host Port C High Speed Data - Analog — USB Device High Speed Port - UDPHS DHSDP USB Device High Speed Data + Analog — DHSDM USB Device High Speed Data - Analog — GIgabit Ethernet 10/100/1000 - GMAC GTXCK Transmit Clock or Reference Clock Input — G125CK 125 MHz input Clock Input — G125CKO 125 MHz output Clock Output — GTXEN Transmit Enable Output — GTX[7..0] Transmit Data Output — GTXER Transmit Coding Error Output — GRXCK Receive Clock Input — GRXDV Receive Data Valid Input — GRX[7..0] Receive Data Input — GRXER Receive Error Input — GCRS Carrier Sense and Data Valid Input — GCOL Collision Detect Input — GMDC Management Data Clock Output — GMDIO Management Data Input/Output I/O — Input — RMII Ethernet 10/100 - EMAC EREFCK Transmit Clock or Reference Clock ETXEN Transmit Enable Output — ETX[1..0] Transmit Data Output — ECRSDV Carrier Sense/Data Valid Input — ERX[1..0] Receive Data Input — ERXER Receive Error Input — EMDC Management Data Clock Output — EMDIO Management Data Input/Output I/O — LCD Controller - LCDC SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 8 Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level LCDDAT[23..0] LCD Data Bus Output — LCDVSYNC LCD Vertical Synchronization Output — LCDHSYNC LCD Horizontal Synchronization Output — LCDPCK LCD pixel Clock Output — LCDDEN LCD Data Enable Output — LCDPWM LCDPWM for Contrast Control Output — LCDDISP LCD Display ON/OFF Output — Image Sensor Interface - ISI ISI_D[11..0] Image Sensor Data Input — ISI_HSYNC Image Sensor Horizontal Synchro input — ISI_VSYNC Image Sensor Vertical Synchro input — ISI_PCK Image Sensor Data clock input — Touch Screen Analog-to-Digital Converter - ADC AD0UL Upper Left Touch Panel Analog — AD1UR Upper Right Touch Panel Analog — AD2LL Lower Left Touch Panel Analog — AD3LR Lower Right Touch Panel Analog — AD4PI Panel Input Analog — AD5–AD11 7 Analog Inputs Analog — ADTRG ADC Trigger Input — ADVREF ADC Reference Analog — SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 9 4. Package and Pinout The SAMA5D3 product is available in two packages: 4.1  324-ball LFBGA (15 x 15 x 1.4 mm, pitch 0.8 mm)  324-ball TFBGA (12 x 12 x 1.2 mm, pitch 0.5 mm) 324-ball LFBGA Package (15 x 15 x 1.4 mm, pitch 0.8 mm) Figure 4-1 shows the ball map of the 324-ball LFBGA package. Figure 4-1. 324-ball LFBGA Ball Map Bottom VIEW V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 10 4.2 324-ball LFBGA Package Pinout Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST E3 VDDIOP0 GPIO PA0 I/O — — LCDDAT0 O — — — — PIO, I, PU, ST F5 VDDIOP0 GPIO PA1 I/O — — LCDDAT1 O — — — — PIO, I, PU, ST D2 VDDIOP0 GPIO PA2 I/O — — LCDDAT2 O — — — — PIO, I, PU, ST Pin F4 VDDIOP0 GPIO PA3 I/O — — LCDDAT3 O — — — — PIO, I, PU, ST D1 VDDIOP0 GPIO PA4 I/O — — LCDDAT4 O — — — — PIO, I, PU, ST J10 VDDIOP0 GPIO PA5 I/O — — LCDDAT5 O — — — — PIO, I, PU, ST G4 VDDIOP0 GPIO PA6 I/O — — LCDDAT6 O — — — — PIO, I, PU, ST J9 VDDIOP0 GPIO PA7 I/O — — LCDDAT7 O — — — — PIO, I, PU, ST F3 VDDIOP0 GPIO PA8 I/O — — LCDDAT8 O — — — — PIO, I, PU, ST J8 VDDIOP0 GPIO PA9 I/O — — LCDDAT9 O — — — — PIO, I, PU, ST E2 VDDIOP0 GPIO PA10 I/O — — LCDDAT10 O — — — — PIO, I, PU, ST K8 VDDIOP0 GPIO PA11 I/O — — LCDDAT11 O — — — — PIO, I, PU, ST F2 VDDIOP0 GPIO PA12 I/O — — LCDDAT12 O — — — — PIO, I, PU, ST G6 VDDIOP0 GPIO PA13 I/O — — LCDDAT13 O — — — — PIO, I, PU, ST PIO, I, PU, ST E1 VDDIOP0 GPIO PA14 I/O — — LCDDAT14 O — — — — H5 VDDIOP0 GPIO PA15 I/O — — LCDDAT15 O — — — — PIO, I, PU, ST H3 VDDIOP0 GPIO PA16 I/O — — LCDDAT16 O — — ISI_D0 I PIO, I, PU, ST H6 VDDIOP0 GPIO PA17 I/O — — LCDDAT17 O — — ISI_D1 I PIO, I, PU, ST H4 VDDIOP0 GPIO PA18 I/O — — LCDDAT18 O TWD2 I/O ISI_D2 I PIO, I, PU, ST H7 VDDIOP0 GPIO PA19 I/O — — LCDDAT19 O TWCK2 O ISI_D3 I PIO, I, PU, ST H2 VDDIOP0 GPIO PA20 I/O — — LCDDAT20 O PWMH0 O ISI_D4 I PIO, I, PU, ST J6 VDDIOP0 GPIO PA21 I/O — — LCDDAT21 O PWML0 O ISI_D5 I PIO, I, PU, ST G2 VDDIOP0 GPIO PA22 I/O — — LCDDAT22 O PWMH1 O ISI_D6 I PIO, I, PU, ST J5 VDDIOP0 GPIO PA23 I/O — — LCDDAT23 O PWML1 O ISI_D7 I PIO, I, PU, ST F1 VDDIOP0 GPIO PA24 I/O — — LCDPWM O — — — — PIO, I, PU, ST J4 VDDIOP0 GPIO PA25 I/O — — LCDDISP O — — — — PIO, I, PU, ST G3 VDDIOP0 GPIO PA26 I/O — — LCDVSYNC O — — — — PIO, I, PU, ST J3 VDDIOP0 GPIO PA27 I/O — — LCDHSYNC O — — — — PIO, I, PU, ST G1 VDDIOP0 GPIO_CLK2 PA28 I/O — — LCDPCK O — — — — PIO, I, PU, ST K4 VDDIOP0 GPIO PA29 I/O — — LCDDEN O — — — — PIO, I, PU, ST H1 VDDIOP0 GPIO PA30 I/O — — TWD0 I/O URXD1 I ISI_VSYNC I PIO, I, PU, ST K3 VDDIOP0 GPIO PA31 I/O — — TWCK0 O UTXD1 O ISI_HSYNC I PIO, I, PU, ST T2 VDDIOP1 GMAC PB0 I/O — — GTX0 O PWMH0 O — — PIO, I, PU, ST N7 VDDIOP1 GMAC PB1 I/O — — GTX1 O PWML0 O — — PIO, I, PU, ST T3 VDDIOP1 GMAC PB2 I/O — — GTX2 O TK1 I/O — — PIO, I, PU, ST N6 VDDIOP1 GMAC PB3 I/O — — GTX3 O TF1 I/O — — PIO, I, PU, ST P5 VDDIOP1 GMAC PB4 I/O — — GRX0 I PWMH1 O — — PIO, I, PU, ST T4 VDDIOP1 GMAC PB5 I/O — — GRX1 I PWML1 O — — PIO, I, PU, ST R4 VDDIOP1 GMAC PB6 I/O — — GRX2 I TD1 O — — PIO, I, PU, ST U1 VDDIOP1 GMAC PB7 I/O — — GRX3 I RK1 I — — PIO, I, PU, ST R5 VDDIOP1 GMAC PB8 I/O — — GTXCK I PWMH2 O — — PIO, I, PU, ST P3 VDDIOP1 GMAC PB9 I/O — — GTXEN O PWML2 O — — PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 11 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate Pin Power Rail I/O Type Signal Dir Signal R6 VDDIOP1 GMAC PB10 I/O — V3 VDDIOP1 GMAC PB11 I/O — P6 VDDIOP1 GMAC PB12 I/O — V1 VDDIOP1 GMAC PB13 I/O R7 VDDIOP1 GMAC PB14 I/O Dir PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST O RF1 I/O — — PIO, I, PU, ST I RD1 I — — PIO, I, PU, ST I PWMH3 O — — PIO, I, PU, ST I PWML3 O — — PIO, I, PU, ST I CANRX1 I — — PIO, I, PU, ST Signal Dir — GTXER — GRXCK — GRXDV — — GRXER — — GCRS U3 VDDIOP1 GMAC PB15 I/O — — GCOL I CANTX1 O — — PIO, I, PU, ST P7 VDDIOP1 GMAC PB16 I/O — — GMDC O — — — — PIO, I, PU, ST V2 VDDIOP1 GMAC PB17 I/O — — GMDIO I/O — — — — PIO, I, PU, ST V5 VDDIOP1 GMAC PB18 I/O — — G125CK I — — — — PIO, I, PU, ST T6 VDDIOP1 GMAC PB19 I/O — — MCI1_CDA I/O GTX4 O — — PIO, I, PU, ST N8 VDDIOP1 GMAC PB20 I/O — — MCI1_DA0 I/O GTX5 O — — PIO, I, PU, ST U4 VDDIOP1 GMAC PB21 I/O — — MCI1_DA1 I/O GTX6 O — — PIO, I, PU, ST M7 VDDIOP1 GMAC PB22 I/O — — MCI1_DA2 I/O GTX7 O — — PIO, I, PU, ST U5 VDDIOP1 GMAC PB23 I/O — — MCI1_DA3 I/O GRX4 I — — PIO, I, PU, ST M8 VDDIOP1 GMAC PB24 I/O — — MCI1_CK I/O GRX5 I — — PIO, I, PU, ST T5 VDDIOP1 GMAC PB25 I/O — — SCK1 I/O GRX6 I — — PIO, I, PU, ST N9 VDDIOP1 GMAC PB26 I/O — — CTS1 I GRX7 I — — PIO, I, PU, ST V4 VDDIOP1 GPIO PB27 I/O — — RTS1 O G125CKO O — — PIO, I, PU, ST M9 VDDIOP1 GPIO PB28 I/O — — RXD1 I — — — — PIO, I, PU, ST P8 VDDIOP1 GPIO PB29 I/O — — TXD1 O — — — — PIO, I, PU, ST M10 VDDIOP0 GPIO PB30 I/O — — DRXD I — — — — PIO, I, PU, ST R9 VDDIOP0 GPIO PB31 I/O — — DTXD O — — — — PIO, I, PU, ST D8 VDDIOP0 GPIO PC0 I/O — — ETX0 O TIOA3 I/O — — PIO, I, PU, ST A4 VDDIOP0 GPIO PC1 I/O — — ETX1 O TIOB3 I/O — — PIO, I, PU, ST E8 VDDIOP0 GPIO PC2 I/O — — ERX0 I TCLK3 I — — PIO, I, PU, ST A3 VDDIOP0 GPIO PC3 I/O — — ERX1 I TIOA4 I/O — — PIO, I, PU, ST PIO, I, PU, ST A2 VDDIOP0 GPIO PC4 I/O — — ETXEN O TIOB4 I/O — — F8 VDDIOP0 GPIO PC5 I/O — — ECRSDV I TCLK4 I — — PIO, I, PU, ST B3 VDDIOP0 GPIO PC6 I/O — — ERXER I TIOA5 I/O — — PIO, I, PU, ST G8 VDDIOP0 GPIO PC7 I/O — — EREFCK I TIOB5 I/O — — PIO, I, PU, ST B4 VDDIOP0 GPIO PC8 I/O — — EMDC O TCLK5 I — — PIO, I, PU, ST F7 VDDIOP0 GPIO PC9 I/O — — EMDIO I/O — — — — PIO, I, PU, ST A1 VDDIOP0 GPIO PC10 I/O — — MCI2_CDA I/O — — LCDDAT20 O PIO, I, PU, ST D7 VDDIOP0 GPIO PC11 I/O — — MCI2_DA0 I/O — — LCDDAT19 O PIO, I, PU, ST C6 VDDIOP0 GPIO PC12 I/O — — MCI2_DA1 I/O TIOA1 I/O LCDDAT18 O PIO, I, PU, ST E7 VDDIOP0 GPIO PC13 I/O — — MCI2_DA2 I/O TIOB1 I/O LCDDAT17 O PIO, I, PU, ST B2 VDDIOP0 GPIO PC14 I/O — — MCI2_DA3 I/O TCLK1 I LCDDAT16 O PIO, I, PU, ST F6 VDDIOP0 MCI_CLK PC15 I/O — — MCI2_CK I/O PCK2 O LCDDAT21 O PIO, I, PU, ST B1 VDDIOP0 GPIO PC16 I/O — — TK0 I/O — — — — PIO, I, PU, ST E6 VDDIOP0 GPIO PC17 I/O — — TF0 I/O — — — — PIO, I, PU, ST PIO, I, PU, ST C3 VDDIOP0 GPIO PC18 I/O — — TD0 O — — — — D6 VDDIOP0 GPIO PC19 I/O — — RK0 I/O — — — — PIO, I, PU, ST C4 VDDIOP0 GPIO PC20 I/O — — RF0 I/O — — — — PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 12 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST D5 VDDIOP0 GPIO PC21 I/O — — RD0 I — — — — PIO, I, PU, ST C2 VDDIOP0 GPIO PC22 I/O — — SPI1_MISO I/O — — — — PIO, I, PU, ST G9 VDDIOP0 GPIO PC23 I/O — — SPI1_MOSI I/O — — — — PIO, I, PU, ST C1 VDDIOP0 GPIO_CLK PC24 I/O — — SPI1_SPCK I/O — — — — PIO, I, PU, ST H10 VDDIOP0 GPIO PC25 I/O — — SPI1_NPCS0 I/O — — — — PIO, I, PU, ST H9 VDDIOP0 GPIO PC26 I/O — — SPI1_NPCS1 O TWD1 I/O ISI_D11 I PIO, I, PU, ST D4 VDDIOP0 GPIO PC27 I/O — — SPI1_NPCS2 O TWCK1 O ISI_D10 I PIO, I, PU, ST PIO, I, PU, ST H8 VDDIOP0 GPIO PC28 I/O — — SPI1_NPCS3 O PWMFI0 I ISI_D9 I G5 VDDIOP0 GPIO PC29 I/O — — URXD0 I PWMFI2 I ISI_D8 I PIO, I, PU, ST D3 VDDIOP0 GPIO PC30 I/O — — UTXD0 O — — ISI_PCK O PIO, I, PU, ST E4 VDDIOP0 GPIO PC31 I/O — — FIQ I PWMFI1 I — — PIO, I, PU, ST K5 VDDIOP1 GPIO PD0 I/O — — MCI0_CDA I/O — — — — PIO, I, PU, ST P1 VDDIOP1 GPIO PD1 I/O — — MCI0_DA0 I/O — — — — PIO, I, PU, ST K6 VDDIOP1 GPIO PD2 I/O — — MCI0_DA1 I/O — — — — PIO, I, PU, ST R1 VDDIOP1 GPIO PD3 I/O — — MCI0_DA2 I/O — — — — PIO, I, PU, ST L7 VDDIOP1 GPIO PD4 I/O — — MCI0_DA3 I/O — — — — PIO, I, PU, ST P2 VDDIOP1 GPIO PD5 I/O — — MCI0_DA4 I/O TIOA0 I/O PWMH2 O PIO, I, PU, ST L8 VDDIOP1 GPIO PD6 I/O — — MCI0_DA5 I/O TIOB0 I/O PWML2 O PIO, I, PU, ST R2 VDDIOP1 GPIO PD7 I/O — — MCI0_DA6 I/O TCLK0 I PWMH3 O PIO, I, PU, ST PIO, I, PU, ST K7 VDDIOP1 GPIO PD8 I/O — — MCI0_DA7 I/O — — PWML3 O U2 VDDIOP1 MCI_CLK PD9 I/O — — MCI0_CK I/O — — — — PIO, I, PU, ST K9 VDDIOP1 GPIO PD10 I/O — — SPI0_MISO I/O — — — — PIO, I, PU, ST M5 VDDIOP1 GPIO PD11 I/O — — SPI0_MOSI I/O — — — — PIO, I, PU, ST K10 VDDIOP1 GPIO_CLK PD12 I/O — — SPI0_SPCK I/O — — — — PIO, I, PU, ST N4 VDDIOP1 GPIO PD13 I/O — — SPI0_NPCS0 I/O — — — — PIO, I, PU, ST L9 VDDIOP1 GPIO PD14 I/O — — SCK0 I/O SPI0_NPCS1 O CANRX0 I PIO, I, PU, ST N3 VDDIOP1 GPIO PD15 I/O — — CTS0 I SPI0_NPCS2 O CANTX0 O PIO, I, PU, ST L10 VDDIOP1 GPIO PD16 I/O — — RTS0 O SPI0_NPCS3 O PWMFI3 I PIO, I, PU, ST N5 VDDIOP1 GPIO PD17 I/O — — RXD0 I — — — — PIO, I, PU, ST M6 VDDIOP1 GPIO PD18 I/O — — TXD0 O — — — — PIO, I, PU, ST T1 VDDIOP1 GPIO PD19 I/O — — ADTRG I — — — — PIO, I, PU, ST N2 VDDANA GPIO_ANA PD20 I/O — — AD0 I — — — — PIO, I, PU, ST M3 VDDANA GPIO_ANA PD21 I/O — — AD1 I — — — — PIO, I, PU, ST M2 VDDANA GPIO_ANA PD22 I/O — — AD2 I — — — — PIO, I, PU, ST L3 VDDANA GPIO_ANA PD23 I/O — — AD3 I — — — — PIO, I, PU, ST M1 VDDANA GPIO_ANA PD24 I/O — — AD4 I — — — — PIO, I, PU, ST N1 VDDANA GPIO_ANA PD25 I/O — — AD5 I — — — — PIO, I, PU, ST L1 VDDANA GPIO_ANA PD26 I/O — — AD6 I — — — — PIO, I, PU, ST L2 VDDANA GPIO_ANA PD27 I/O — — AD7 I — — — — PIO, I, PU, ST K1 VDDANA GPIO_ANA PD28 I/O — — AD8 I — — — — PIO, I, PU, ST K2 VDDANA GPIO_ANA PD29 I/O — — AD9 I — — — — PIO, I, PU, ST J1 VDDANA GPIO_ANA PD30 I/O — — AD10 I PCK0 O — — PIO, I, PU, ST J2 VDDANA GPIO_ANA PD31 I/O — — AD11 I PCK1 O — — PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 13 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST A,I, PD, ST P13 VDDIOM EBI PE0 I/O — — A0/NBS0 O — — — — R14 VDDIOM EBI PE1 I/O — — A1 O — — — — A,I, PD, ST R13 VDDIOM EBI PE2 I/O — — A2 O — — — — A,I, PD, ST V18 VDDIOM EBI PE3 I/O — — A3 O — — — — A,I, PD, ST P14 VDDIOM EBI PE4 I/O — — A4 O — — — — A,I, PD, ST U18 VDDIOM EBI PE5 I/O — — A5 O — — — — A,I, PD, ST T18 VDDIOM EBI PE6 I/O — — A6 O — — — — A,I, PD, ST R15 VDDIOM EBI PE7 I/O — — A7 O — — — — A,I, PD, ST P17 VDDIOM EBI PE8 I/O — — A8 O — — — — A,I, PD, ST P15 VDDIOM EBI PE9 I/O — — A9 O — — — — A,I, PD, ST P18 VDDIOM EBI PE10 I/O — — A10 O — — — — A,I, PD, ST R16 VDDIOM EBI PE11 I/O — — A11 O — — — — A,I, PD, ST N16 VDDIOM EBI PE12 I/O — — A12 O — — — — A,I, PD, ST R17 VDDIOM EBI PE13 I/O — — A13 O — — — — A,I, PD, ST A,I, PD, ST N17 VDDIOM EBI PE14 I/O — — A14 O — — — — R18 VDDIOM EBI PE15 I/O — — A15 O SCK3 I/O — — A,I, PD, ST N18 VDDIOM EBI PE16 I/O — — A16 O CTS3 I — — A,I, PD, ST P16 VDDIOM EBI PE17 I/O — — A17 O RTS3 O — — A,I, PD, ST M18 VDDIOM EBI PE18 I/O — — A18 O RXD3 I — — A,I, PD, ST N15 VDDIOM EBI PE19 I/O — — A19 O TXD3 O — — A,I, PD, ST M15 VDDIOM EBI PE20 I/O — — A20 O SCK2 I/O — — A,I, PD, ST N14 VDDIOM EBI PE21 I/O — — A21/NANDALE O — — — — A,I, PD, ST M17 VDDIOM EBI PE22 I/O — — A22/NANDCLE O — — — — A,I, PD, ST M13 VDDIOM EBI PE23 I/O — — A23 O CTS2 I — — A,I, PD, ST M16 VDDIOM EBI PE24 I/O — — A24 O RTS2 O — — A,I, PD, ST N12 VDDIOM EBI PE25 I/O — — A25 O RXD2 I — — A,I, PD, ST M14 VDDIOM EBI PE26 I/O — — NCS0 O TXD2 O — — A,I, PD, ST M12 VDDIOM EBI PE27 I/O — — NCS1 O TIOA2 I/O LCDDAT22 O PIO,I, PD, ST L13 VDDIOM EBI PE28 I/O — — NCS2 O TIOB2 I/O LCDDAT23 O PIO, I, PD, ST L15 VDDIOM EBI PE29 I/O — — NWR1/NBS1 O TCLK2 I — — PIO, I, PD, ST L14 VDDIOM EBI PE30 I/O — — NWAIT I — — — — PIO, I, PD, ST L16 VDDIOM EBI PE31 I/O — — IRQ I PWML1 O — — PIO,I, PD, ST U15 VDDBU SYSC TST I — — — — — — — — I, PD, U9 VDDIOP0 SYSC BMS I — — — — — — — — I U8 VDDIOP0 CLOCK XIN I — — — — — — — — I V8 VDDIOP0 CLOCK XOUT O — — — — — — — — O U16 VDDBU CLOCK XIN32 I — — — — — — — — I V16 VDDBU CLOCK XOUT32 O — — — — — — — — O T12 VDDBU SYSC SHDN O — — — — — — — — O T10 VDDBU SYSC WKUP I — — — — — — — — I, ST V9 VDDIOP0 RSTJTAG NRST I/O — — — — — — — — I, PU, ST P11 VDDIOP0 RSTJTAG NTRST I — — — — — — — — I, PU, ST R8 VDDIOP0 RSTJTAG TDI I — — — — — — — — I, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 14 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate Pin Power Rail I/O Type Signal Dir Signal M11 VDDIOP0 RSTJTAG TDO O N10 VDDIOP0 RSTJTAG TMS I P9 VDDIOP0 RSTJTAG TCK I SWCLK PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Signal, Dir, PU, PD, HiZ, ST Dir Signal Dir Signal Dir Signal Dir — — — — — — — — O SWDIO I/O — — — — — — I, ST I — — — — — — I, ST T9 VDDBU SYSC JTAGSEL I — — — — — — — — I, PD V6 VDDIOP0 DIB DIBP O — — — — — — — — O, PU U6 VDDIOP0 DIB DIBN O — — — — — — — — O, PU K12 VDDIOM EBI D0 I/O — — — — — — — — I, PD I, PD K15 VDDIOM EBI D1 I/O — — — — — — — — K14 VDDIOM EBI D2 I/O — — — — — — — — I, PD K16 VDDIOM EBI D3 I/O — — — — — — — — I, PD K13 VDDIOM EBI D4 I/O — — — — — — — — I, PD K17 VDDIOM EBI D5 I/O — — — — — — — — I, PD J12 VDDIOM EBI D6 I/O — — — — — — — — I, PD K18 VDDIOM EBI D7 I/O — — — — — — — — I, PD J14 VDDIOM EBI D8 I/O — — — — — — — — I, PD J16 VDDIOM EBI D9 I/O — — — — — — — — I, PD J13 VDDIOM EBI D10 I/O — — — — — — — — I, PD J17 VDDIOM EBI D11 I/O — — — — — — — — I, PD J15 VDDIOM EBI D12 I/O — — — — — — — — I, PD I, PD J18 VDDIOM EBI D13 I/O — — — — — — — — H16 VDDIOM EBI D14 I/O — — — — — — — — I, PD H18 VDDIOM EBI D15 I/O — — — — — — — — I, PD L12 VDDIOM EBI NCS3/NANDCS O — — — — — — — — O, PU L18 VDDIOM EBI NANDRDY I — — — — — — — — I, PU L17 VDDIOM EBI NRD/NANDOE O — — — — — — — — O, PU K11 VDDIOM EBI NWE/NANDWE O — — — — — — — — O, PU C13 VDDIODDR Reference voltage DDR_VREF I — — — — — — — — I B10 VDDIODDR DDR_IO DDR_A0 O — — — — — — — — O C11 VDDIODDR DDR_IO DDR_A1 O — — — — — — — — O A9 VDDIODDR DDR_IO DDR_A2 O — — — — — — — — O D11 VDDIODDR DDR_IO DDR_A3 O — — — — — — — — O B9 VDDIODDR DDR_IO DDR_A4 O — — — — — — — — O E10 VDDIODDR DDR_IO DDR_A5 O — — — — — — — — O D10 VDDIODDR DDR_IO DDR_A6 O — — — — — — — — O A8 VDDIODDR DDR_IO DDR_A7 O — — — — — — — — O C10 VDDIODDR DDR_IO DDR_A8 O — — — — — — — — O O B8 VDDIODDR DDR_IO DDR_A9 O — — — — — — — — F11 VDDIODDR DDR_IO DDR_A10 O — — — — — — — — O A7 VDDIODDR DDR_IO DDR_A11 O — — — — — — — — O D9 VDDIODDR DDR_IO DDR_A12 O — — — — — — — — O A6 VDDIODDR DDR_IO DDR_A13 O — — — — — — — — O H12 VDDIODDR DDR_IO DDR_D0 I/O — — — — — — — — HiZ H17 VDDIODDR DDR_IO DDR_D1 I/O — — — — — — — — HiZ SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 15 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST H13 VDDIODDR DDR_IO DDR_D2 I/O — — — — — — — — HiZ G17 VDDIODDR DDR_IO DDR_D3 I/O — — — — — — — — HiZ G16 VDDIODDR DDR_IO DDR_D4 I/O — — — — — — — — HiZ H15 VDDIODDR DDR_IO DDR_D5 I/O — — — — — — — — HiZ F17 VDDIODDR DDR_IO DDR_D6 I/O — — — — — — — — HiZ G15 VDDIODDR DDR_IO DDR_D7 I/O — — — — — — — — HiZ F16 VDDIODDR DDR_IO DDR_D8 I/O — — — — — — — — HiZ E17 VDDIODDR DDR_IO DDR_D9 I/O — — — — — — — — HiZ G14 VDDIODDR DDR_IO DDR_D10 I/O — — — — — — — — HiZ E16 VDDIODDR DDR_IO DDR_D11 I/O — — — — — — — — HiZ D17 VDDIODDR DDR_IO DDR_D12 I/O — — — — — — — — HiZ C18 VDDIODDR DDR_IO DDR_D13 I/O — — — — — — — — HiZ D16 VDDIODDR DDR_IO DDR_D14 I/O — — — — — — — — HiZ C17 VDDIODDR DDR_IO DDR_D15 I/O — — — — — — — — HiZ B16 VDDIODDR DDR_IO DDR_D16 I/O — — — — — — — — HiZ B18 VDDIODDR DDR_IO DDR_D17 I/O — — — — — — — — HiZ C15 VDDIODDR DDR_IO DDR_D18 I/O — — — — — — — — HiZ A18 VDDIODDR DDR_IO DDR_D19 I/O — — — — — — — — HiZ C16 VDDIODDR DDR_IO DDR_D20 I/O — — — — — — — — HiZ C14 VDDIODDR DDR_IO DDR_D21 I/O — — — — — — — — HiZ D15 VDDIODDR DDR_IO DDR_D22 I/O — — — — — — — — HiZ B14 VDDIODDR DDR_IO DDR_D23 I/O — — — — — — — — HiZ A15 VDDIODDR DDR_IO DDR_D24 I/O — — — — — — — — HiZ A14 VDDIODDR DDR_IO DDR_D25 I/O — — — — — — — — HiZ E12 VDDIODDR DDR_IO DDR_D26 I/O — — — — — — — — HiZ A11 VDDIODDR DDR_IO DDR_D27 I/O — — — — — — — — HiZ B11 VDDIODDR DDR_IO DDR_D28 I/O — — — — — — — — HiZ F12 VDDIODDR DDR_IO DDR_D29 I/O — — — — — — — — HiZ A10 VDDIODDR DDR_IO DDR_D30 I/O — — — — — — — — HiZ E11 VDDIODDR DDR_IO DDR_D31 I/O — — — — — — — — HiZ G12 VDDIODDR DDR_IO DDR_DQM0 O — — — — — — — — O E15 VDDIODDR DDR_IO DDR_DQM1 O — — — — — — — — O B15 VDDIODDR DDR_IO DDR_DQM2 O — — — — — — — — O D12 VDDIODDR DDR_IO DDR_DQM3 O — — — — — — — — O E18 VDDIODDR DDR_IO DDR_DQS0 I/O — — — — — — — — I, PD G18 VDDIODDR DDR_IO DDR_DQS1 I/O — — — — — — — — I, PD B17 VDDIODDR DDR_IO DDR_DQS2 I/O — — — — — — — — I, PD B13 VDDIODDR DDR_IO DDR_DQS3 I/O — — — — — — — — I, PD D18 VDDIODDR DDR_IO DDR_DQSN0 I/O — — — — — — — — I, PU F18 VDDIODDR DDR_IO DDR_DQSN1 I/O — — — — — — — — I, PU A17 VDDIODDR DDR_IO DDR_DQSN2 I/O — — — — — — — — I, PU A13 VDDIODDR DDR_IO DDR_DQSN3 I/O — — — — — — — — I, PU C8 VDDIODDR DDR_IO DDR_CS O — — — — — — — — O SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 16 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Pin Power Rail I/O Type B12 VDDIODDR A12 VDDIODDR B7 VDDIODDR C12 E13 Alternate PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST Signal Dir Signal Dir DDR_IO DDR_CLK O — — — — — — — — O DDR_IO DDR_CLKN O — — — — — — — — O DDR_IO DDR_CKE O — — — — — — — — O VDDIODDR DDR_IO DDR_CALN I — — — — — — — — O VDDIODDR DDR_IO DDR_CALP I — — — — — — — — O G11 VDDIODDR DDR_IO DDR_RAS O — — — — — — — — O A5 VDDIODDR DDR_IO DDR_CAS O — — — — — — — — O B5 VDDIODDR DDR_IO DDR_WE O — — — — — — — — O E9 VDDIODDR DDR_IO DDR_BA0 O — — — — — — — — O B6 VDDIODDR DDR_IO DDR_BA1 O — — — — — — — — O F9 VDDIODDR DDR_IO DDR_BA2 O — — — — — — — — O R11 VBG VBG VBG I — — — — — — — — I U14 VDDUTMII USBHS HHSDPC I/O — — — — — — — — O, PD V14 VDDUTMII USBHS HHSDMC I/O — — — — — — — — O, PD U12 VDDUTMII USBHS HHSDPB I/O — — — — — — — — O, PD V12 VDDUTMII USBHS HHSDMB I/O — — — — — — — — O, PD U10 VDDUTMII USBHS HHSDPA I/O DHSDP — — — — — — — O, PD V10 VDDUTMII USBHS HHSDMA I/O DHSDM — — — — — — — O, PD V15 VDDBU power supply VDDBU I — — — — — — — — I T13 GNDBU ground GNDBU I — — — — — — — — I C5, C7, D14, T15, T7, U17, V7 VDDCORE power supply VDDCORE I — — — — — — — — I A16, C9, N13, T14, T8, V17 GNDCORE ground GNDCORE I — — — — — — — — I D13, F14, G10, G13, H11 VDDIODDR power supply VDDIODDR I — — — — — — — — I E14, F10, F13, F15, H14 GNDIODDR ground GNDIODDR I — — — — — — — — I P12, T16 VDDIOM power supply VDDIOM I — — — — — — — — I J11, T17 GNDIOM ground GNDIOM I — — — — — — — — I G7, V11 VDDIOP0 power supply VDDIOP0 I — — — — — — — — I L11, M4 VDDIOP1 power supply VDDIOP1 I — — — — — — — — I E5, J7, N11, U7 GNDIOP Ground GNDIOP I — — — — — — — — I V13 VDDUTMIC Power supply VDDUTMIC I — — — — — — — — I SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 17 Table 4-1. SAMA5D3 Pinout for 324-ball LFBGA Package (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST U13 VDDUTMII Power supply VDDUTMII I — — — — — — — — I R12 GNDUTMI Ground GNDUTMI I — — — — — — — — I R10 VDDPLLA Power supply VDDPLLA I — — — — — — — — I P10 GNDPLL Ground GNDPLL I — — — — — — — — I U11 VDDOSC Power supply VDDOSC I — — — — — — — — I T11 GNDOSC Ground GNDOSC I — — — — — — — — I L6 VDDANA Power supply VDDANA I — — — — — — — — I L4 GNDANA Ground GNDANA I — — — — — — — — I L5 VDDANA Power supply ADVREF I — — — — — — — — I R3 VDDFUSE Power supply VDDFUSE I — — — — — — — — I P4 GNDFUSE Ground GNDFUSE I — — — — — — — — I SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 18 4.3 324-ball TFBGA Package (12 x 12 x 1.2 mm, pitch 0.5 mm) Figure 4-2 shows the ball map of the 324-ball TFBGA package. Figure 4-2. 324-ball TFBGA Ball Map SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 19 4.4 324-ball TFBGA Package Pinout Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package Primary Pin Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST PIO, I, PU, ST D2 VDDIOP0 GPIO PA0 I/O — — LCDDAT0 O — — — — G4 VDDIOP0 GPIO PA1 I/O — — LCDDAT1 O — — — — PIO, I, PU, ST C2 VDDIOP0 GPIO PA2 I/O — — LCDDAT2 O — — — — PIO, I, PU, ST F3 VDDIOP0 GPIO PA3 I/O — — LCDDAT3 O — — — — PIO, I, PU, ST F2 VDDIOP0 GPIO PA4 I/O — — LCDDAT4 O — — — — PIO, I, PU, ST G3 VDDIOP0 GPIO PA5 I/O — — LCDDAT5 O — — — — PIO, I, PU, ST B1 VDDIOP0 GPIO PA6 I/O — — LCDDAT6 O — — — — PIO, I, PU, ST G2 VDDIOP0 GPIO PA7 I/O — — LCDDAT7 O — — — — PIO, I, PU, ST C1 VDDIOP0 GPIO PA8 I/O — — LCDDAT8 O — — — — PIO, I, PU, ST H3 VDDIOP0 GPIO PA9 I/O — — LCDDAT9 O — — — — PIO, I, PU, ST D1 VDDIOP0 GPIO PA10 I/O — — LCDDAT10 O — — — — PIO, I, PU, ST H4 VDDIOP0 GPIO PA11 I/O — — LCDDAT11 O — — — — PIO, I, PU, ST E2 VDDIOP0 GPIO PA12 I/O — — LCDDAT12 O — — — — PIO, I, PU, ST K9 VDDIOP0 GPIO PA13 I/O — — LCDDAT13 O — — — — PIO, I, PU, ST H2 VDDIOP0 GPIO PA14 I/O — — LCDDAT14 O — — — — PIO, I, PU, ST K4 VDDIOP0 GPIO PA15 I/O — — LCDDAT15 O — — — — PIO, I, PU, ST G1 VDDIOP0 GPIO PA16 I/O — — LCDDAT16 O — — ISI_D0 I PIO, I, PU, ST K10 VDDIOP0 GPIO PA17 I/O — — LCDDAT17 O — — ISI_D1 I PIO, I, PU, ST F1 VDDIOP0 GPIO PA18 I/O — — LCDDAT18 O TWD2 I/O ISI_D2 I PIO, I, PU, ST J4 VDDIOP0 GPIO PA19 I/O — — LCDDAT19 O TWCK2 O ISI_D3 I PIO, I, PU, ST J3 VDDIOP0 GPIO PA20 I/O — — LCDDAT20 O PWMH0 O ISI_D4 I PIO, I, PU, ST K2 VDDIOP0 GPIO PA21 I/O — — LCDDAT21 O PWML0 O ISI_D5 I PIO, I, PU, ST J2 VDDIOP0 GPIO PA22 I/O — — LCDDAT22 O PWMH1 O ISI_D6 I PIO, I, PU, ST L9 VDDIOP0 GPIO PA23 I/O — — LCDDAT23 O PWML1 O ISI_D7 I PIO, I, PU, ST H1 VDDIOP0 GPIO PA24 I/O — — LCDPWM O — — — — PIO, I, PU, ST K3 VDDIOP0 GPIO PA25 I/O — — LCDDISP O — — — — PIO, I, PU, ST PIO, I, PU, ST J1 VDDIOP0 GPIO PA26 I/O — — LCDVSYNC O — — — — L10 VDDIOP0 GPIO PA27 I/O — — LCDHSYNC O — — — — PIO, I, PU, ST K1 VDDIOP0 GPIO_CLK2 PA28 I/O — — LCDPCK O — — — — PIO, I, PU, ST L3 VDDIOP0 GPIO PA29 I/O — — LCDDEN O — — — — PIO, I, PU, ST L2 VDDIOP0 GPIO PA30 I/O — — TWD0 I/O URXD1 I ISI_VSYNC I PIO, I, PU, ST L4 VDDIOP0 GPIO PA31 I/O — — TWCK0 O UTXD1 O ISI_HSYNC I PIO, I, PU, ST AA1 VDDIOP1 GMAC PB0 I/O — — GTX0 O PWMH0 O — — PIO, I, PU, ST W3 VDDIOP1 GMAC PB1 I/O — — GTX1 O PWML0 O — — PIO, I, PU, ST Y2 VDDIOP1 GMAC PB2 I/O — — GTX2 O TK1 I/O — — PIO, I, PU, ST Y3 VDDIOP1 GMAC PB3 I/O — — GTX3 O TF1 I/O — — PIO, I, PU, ST AA2 VDDIOP1 GMAC PB4 I/O — — GRX0 I PWMH1 O — — PIO, I, PU, ST W5 VDDIOP1 GMAC PB5 I/O — — GRX1 I PWML1 O — — PIO, I, PU, ST W7 VDDIOP1 GMAC PB6 I/O — — GRX2 I TD1 O — — PIO, I, PU, ST AB2 VDDIOP1 GMAC PB7 I/O — — GRX3 I RK1 I — — PIO, I, PU, ST AB1 VDDIOP1 GMAC PB8 I/O — — GTXCK I PWMH2 O — — PIO, I, PU, ST AA3 VDDIOP1 GMAC PB9 I/O — — GTXEN O PWML2 O — — PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 20 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST W6 VDDIOP1 GMAC PB10 I/O — — GTXER O RF1 I/O — — PIO, I, PU, ST AB3 VDDIOP1 GMAC PB11 I/O — — GRXCK I RD1 I — — PIO, I, PU, ST Y5 VDDIOP1 GMAC PB12 I/O — — GRXDV I PWMH3 O — — PIO, I, PU, ST Y4 VDDIOP1 GMAC PB13 I/O — — GRXER I PWML3 O — — PIO, I, PU, ST W8 VDDIOP1 GMAC PB14 I/O — — GCRS I CANRX1 I — — PIO, I, PU, ST AA5 VDDIOP1 GMAC PB15 I/O — — GCOL I CANTX1 O — — PIO, I, PU, ST AA4 VDDIOP1 GMAC PB16 I/O — — GMDC O — — — — PIO, I, PU, ST Y7 VDDIOP1 GMAC PB17 I/O — — GMDIO I/O — — — — PIO, I, PU, ST AB4 VDDIOP1 GMAC PB18 I/O — — G125CK I — — — — PIO, I, PU, ST Y6 VDDIOP1 GMAC PB19 I/O — — MCI1_CDA I/O GTX4 O — — PIO, I, PU, ST Y8 VDDIOP1 GMAC PB20 I/O — — MCI1_DA0 I/O GTX5 O — — PIO, I, PU, ST AA6 VDDIOP1 GMAC PB21 I/O — — MCI1_DA1 I/O GTX6 O — — PIO, I, PU, ST W9 VDDIOP1 GMAC PB22 I/O — — MCI1_DA2 I/O GTX7 O — — PIO, I, PU, ST AB6 VDDIOP1 GMAC PB23 I/O — — MCI1_DA3 I/O GRX4 I — — PIO, I, PU, ST AB5 VDDIOP1 GMAC PB24 I/O — — MCI1_CK I/O GRX5 I — — PIO, I, PU, ST AB7 VDDIOP1 GMAC PB25 I/O — — SCK1 I/O GRX6 I — — PIO, I, PU, ST AA7 VDDIOP1 GMAC PB26 I/O — — CTS1 I GRX7 I — — PIO, I, PU, ST AB8 VDDIOP1 GPIO PB27 I/O — — RTS1 O G125CKO O — — PIO, I, PU, ST AA8 VDDIOP1 GPIO PB28 I/O — — RXD1 I — — — — PIO, I, PU, ST Y9 VDDIOP1 GPIO PB29 I/O — — TXD1 O — — — — PIO, I, PU, ST W10 VDDIOP0 GPIO PB30 I/O — — DRXD I — — — — PIO, I, PU, ST Y12 VDDIOP0 GPIO PB31 I/O — — DTXD O — — — — PIO, I, PU, ST D10 VDDIOP0 GPIO PC0 I/O — — ETX0 O TIOA3 I/O — — PIO, I, PU, ST B8 VDDIOP0 GPIO PC1 I/O — — ETX1 O TIOB3 I/O — — PIO, I, PU, ST D9 VDDIOP0 GPIO PC2 I/O — — ERX0 I TCLK3 I — — PIO, I, PU, ST C8 VDDIOP0 GPIO PC3 I/O — — ERX1 I TIOA4 I/O — — PIO, I, PU, ST PIO, I, PU, ST B7 VDDIOP0 GPIO PC4 I/O — — ETXEN O TIOB4 I/O — — D8 VDDIOP0 GPIO PC5 I/O — — ECRSDV I TCLK4 I — — PIO, I, PU, ST A6 VDDIOP0 GPIO PC6 I/O — — ERXER I TIOA5 I/O — — PIO, I, PU, ST A7 VDDIOP0 GPIO PC7 I/O — — EREFCK I TIOB5 I/O — — PIO, I, PU, ST B6 VDDIOP0 GPIO PC8 I/O — — EMDC O TCLK5 I — — PIO, I, PU, ST D7 VDDIOP0 GPIO PC9 I/O — — EMDIO I/O — — — — PIO, I, PU, ST A5 VDDIOP0 GPIO PC10 I/O — — MCI2_CDA I/O — — LCDDAT20 O PIO, I, PU, ST C7 VDDIOP0 GPIO PC11 I/O — — MCI2_DA0 I/O — — LCDDAT19 O PIO, I, PU, ST B5 VDDIOP0 GPIO PC12 I/O — — MCI2_DA1 I/O TIOA1 I/O LCDDAT18 O PIO, I, PU, ST C6 VDDIOP0 GPIO PC13 I/O — — MCI2_DA2 I/O TIOB1 I/O LCDDAT17 O PIO, I, PU, ST B4 VDDIOP0 GPIO PC14 I/O — — MCI2_DA3 I/O TCLK1 I LCDDAT16 O PIO, I, PU, ST A4 VDDIOP0 MCI_CLK PC15 I/O — — MCI2_CK I/O PCK2 O LCDDAT21 O PIO, I, PU, ST A3 VDDIOP0 GPIO PC16 I/O — — TK0 I/O — — — — PIO, I, PU, ST C5 VDDIOP0 GPIO PC17 I/O — — TF0 I/O — — — — PIO, I, PU, ST PIO, I, PU, ST C4 VDDIOP0 GPIO PC18 I/O — — TD0 O — — — — D6 VDDIOP0 GPIO PC19 I/O — — RK0 I/O — — — — PIO, I, PU, ST B3 VDDIOP0 GPIO PC20 I/O — — RF0 I/O — — — — PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 21 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST D5 VDDIOP0 GPIO PC21 I/O — — RD0 I — — — — PIO, I, PU, ST C3 VDDIOP0 GPIO PC22 I/O — — SPI1_MISO I/O — — — — PIO, I, PU, ST B2 VDDIOP0 GPIO PC23 I/O — — SPI1_MOSI I/O — — — — PIO, I, PU, ST A2 VDDIOP0 GPIO_CLK PC24 I/O — — SPI1_SPCK I/O — — — — PIO, I, PU, ST A1 VDDIOP0 GPIO PC25 I/O — — SPI1_NPCS0 I/O — — — — PIO, I, PU, ST D3 VDDIOP0 GPIO PC26 I/O — — SPI1_NPCS1 O TWD1 I/O ISI_D11 I PIO, I, PU, ST D4 VDDIOP0 GPIO PC27 I/O — — SPI1_NPCS2 O TWCK1 O ISI_D10 I PIO, I, PU, ST E4 VDDIOP0 GPIO PC28 I/O — — SPI1_NPCS3 O PWMFI0 I ISI_D9 I PIO, I, PU, ST E3 VDDIOP0 GPIO PC29 I/O — — URXD0 I PWMFI2 I ISI_D8 I PIO, I, PU, ST E1 VDDIOP0 GPIO PC30 I/O — — UTXD0 O — — ISI_PCK O PIO, I, PU, ST F4 VDDIOP0 GPIO PC31 I/O — — FIQ I PWMFI1 I — — PIO, I, PU, ST M10 VDDIOP1 GPIO PD0 I/O — — MCI0_CDA I/O — — — — PIO, I, PU, ST T1 VDDIOP1 GPIO PD1 I/O — — MCI0_DA0 I/O — — — — PIO, I, PU, ST R4 VDDIOP1 GPIO PD2 I/O — — MCI0_DA1 I/O — — — — PIO, I, PU, ST U1 VDDIOP1 GPIO PD3 I/O — — MCI0_DA2 I/O — — — — PIO, I, PU, ST M9 VDDIOP1 GPIO PD4 I/O — — MCI0_DA3 I/O — — — — PIO, I, PU, ST V1 VDDIOP1 GPIO PD5 I/O — — MCI0_DA4 I/O TIOA0 I/O PWMH2 O PIO, I, PU, ST N10 VDDIOP1 GPIO PD6 I/O — — MCI0_DA5 I/O TIOB0 I/O PWML2 O PIO, I, PU, ST W1 VDDIOP1 GPIO PD7 I/O — — MCI0_DA6 I/O TCLK0 I PWMH3 O PIO, I, PU, ST PIO, I, PU, ST R3 VDDIOP1 GPIO PD8 I/O — — MCI0_DA7 I/O — — PWML3 O Y1 VDDIOP1 MCI_CLK PD9 I/O — — MCI0_CK I/O — — — — PIO, I, PU, ST T3 VDDIOP1 GPIO PD10 I/O — — SPI0_MISO I/O — — — — PIO, I, PU, ST T2 VDDIOP1 GPIO PD11 I/O — — SPI0_MOSI I/O — — — — PIO, I, PU, ST N9 VDDIOP1 GPIO_CLK PD12 I/O — — SPI0_SPCK I/O — — — — PIO, I, PU, ST U2 VDDIOP1 GPIO PD13 I/O — — SPI0_NPCS0 I/O — — — — PIO, I, PU, ST T4 VDDIOP1 GPIO PD14 I/O — — SCK0 I/O SPI0_NPCS1 O CANRX0 I PIO, I, PU, ST V2 VDDIOP1 GPIO PD15 I/O — — CTS0 I SPI0_NPCS2 O CANTX0 O PIO, I, PU, ST U3 VDDIOP1 GPIO PD16 I/O — — RTS0 O SPI0_NPCS3 O PWMFI3 I PIO, I, PU, ST V3 VDDIOP1 GPIO PD17 I/O — — RXD0 I — — — — PIO, I, PU, ST U4 VDDIOP1 GPIO PD18 I/O — — TXD0 O — — — — PIO, I, PU, ST W2 VDDIOP1 GPIO PD19 I/O — — ADTRG I — — — — PIO, I, PU, ST P3 VDDANA GPIO_ANA PD20 I/O — — AD0 I — — — — PIO, I, PU, ST R2 VDDANA GPIO_ANA PD21 I/O — — AD1 I — — — — PIO, I, PU, ST PIO, I, PU, ST P2 VDDANA GPIO_ANA PD22 I/O — — AD2 I — — — — R1 VDDANA GPIO_ANA PD23 I/O — — AD3 I — — — — PIO, I, PU, ST P1 VDDANA GPIO_ANA PD24 I/O — — AD4 I — — — — PIO, I, PU, ST N3 VDDANA GPIO_ANA PD25 I/O — — AD5 I — — — — PIO, I, PU, ST N1 VDDANA GPIO_ANA PD26 I/O — — AD6 I — — — — PIO, I, PU, ST N2 VDDANA GPIO_ANA PD27 I/O — — AD7 I — — — — PIO, I, PU, ST M2 VDDANA GPIO_ANA PD28 I/O — — AD8 I — — — — PIO, I, PU, ST M1 VDDANA GPIO_ANA PD29 I/O — — AD9 I — — — — PIO, I, PU, ST M3 VDDANA GPIO_ANA PD30 I/O — — AD10 I PCK0 O — — PIO, I, PU, ST L1 VDDANA GPIO_ANA PD31 I/O — — AD11 I PCK1 O — — PIO, I, PU, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 22 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST W17 VDDIOM EBI PE0 I/O — — A0/NBS0 O — — — — A,I, PD, ST Y18 VDDIOM EBI PE1 I/O — — A1 O — — — — A,I, PD, ST W18 VDDIOM EBI PE2 I/O — — A2 O — — — — A,I, PD, ST AA21 VDDIOM EBI PE3 I/O — — A3 O — — — — A,I, PD, ST Y16 VDDIOM EBI PE4 I/O — — A4 O — — — — A,I, PD, ST Pin Y20 VDDIOM EBI PE5 I/O — — A5 O — — — — A,I, PD, ST W19 VDDIOM EBI PE6 I/O — — A6 O — — — — A,I, PD, ST Y22 VDDIOM EBI PE7 I/O — — A7 O — — — — A,I, PD, ST Y21 VDDIOM EBI PE8 I/O — — A8 O — — — — A,I, PD, ST W22 VDDIOM EBI PE9 I/O — — A9 O — — — — A,I, PD, ST V19 VDDIOM EBI PE10 I/O — — A10 O — — — — A,I, PD, ST W20 VDDIOM EBI PE11 I/O — — A11 O — — — — A,I, PD, ST W21 VDDIOM EBI PE12 I/O — — A12 O — — — — A,I, PD, ST T19 VDDIOM EBI PE13 I/O — — A13 O — — — — A,I, PD, ST A,I, PD, ST V22 VDDIOM EBI PE14 I/O — — A14 O — — — — V20 VDDIOM EBI PE15 I/O — — A15 O SCK3 I/O — — A,I, PD, ST V21 VDDIOM EBI PE16 I/O — — A16 O CTS3 I — — A,I, PD, ST T20 VDDIOM EBI PE17 I/O — — A17 O RTS3 O — — A,I, PD, ST U20 VDDIOM EBI PE18 I/O — — A18 O RXD3 I — — A,I, PD, ST U21 VDDIOM EBI PE19 I/O — — A19 O TXD3 O — — A,I, PD, ST U22 VDDIOM EBI PE20 I/O — — A20 O SCK2 I/O — — A,I, PD, ST R19 VDDIOM EBI PE21 I/O — — A21/NANDALE O — — — — A,I, PD, ST R20 VDDIOM EBI PE22 I/O — — A22/NANDCLE O — — — — A,I, PD, ST T21 VDDIOM EBI PE23 I/O — — A23 O CTS2 I — — A,I, PD, ST T22 VDDIOM EBI PE24 I/O — — A24 O RTS2 O — — A,I, PD, ST P19 VDDIOM EBI PE25 I/O — — A25 O RXD2 I — — A,I, PD, ST R22 VDDIOM EBI PE26 I/O — — NCS0 O TXD2 O — — A,I, PD, ST R21 VDDIOM EBI PE27 I/O — — NCS1 O TIOA2 I/O LCDDAT22 O PIO,I, PD, ST P20 VDDIOM EBI PE28 I/O — — NCS2 O TIOB2 I/O LCDDAT23 O PIO, I, PD, ST P21 VDDIOM EBI PE29 I/O — — NWR1/NBS1 O TCLK2 I — — PIO, I, PD, ST N19 VDDIOM EBI PE30 I/O — — NWAIT I — — — — PIO, I, PD, ST N21 VDDIOM EBI PE31 I/O — — IRQ I PWML1 O — — PIO,I, PD, ST Y15 VDDBU SYSC TST I — — — — — — — — I, PD, — — — — I — — — — — — I — — — — O AB14 VDDIOP0 SYSC BMS I — — AB11 VDDIOP0 CLOCK XIN I — — AA11 VDDIOP0 CLOCK XOUT O — — AB19 VDDBU CLOCK XIN32 I — — AA19 VDDBU CLOCK XOUT32 O — — W16 VDDBU SYSC SHDN O — — AB16 VDDBU SYSC WKUP I — — — — — — — — — — I — — — — O — — — — O — — — — I, ST Y13 VDDIOP0 RSTJTAG NRST I/O — — — — — — — — I, PU, ST AA14 VDDIOP0 RSTJTAG NTRST I — — — — — — — — I, PU, ST W13 VDDIOP0 RSTJTAG TDI I — — — — — — — — I, ST SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 23 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Alternate Power Rail I/O Type Signal Dir Signal PIO Peripheral A PIO Peripheral B PIO Peripheral C Dir Signal Dir Signal Dir Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST W11 VDDIOP0 RSTJTAG TDO O — — — — — — — — O W12 VDDIOP0 RSTJTAG TMS I SWDIO I/O — — — — — — I, ST Y14 VDDIOP0 RSTJTAG TCK I SWCLK I — — — — — — I, ST AA16 VDDBU SYSC JTAGSEL I — — — — — — — — I, PD AA9 VDDIOP0 DIB DIBP O — — — — — — — — O, PU AB9 VDDIOP0 DIB DIBN O — — — — — — — — O, PU M19 VDDIOM EBI D0 I/O — — — — — — — — I, PD I, PD M22 VDDIOM EBI D1 I/O — — — — — — — — M20 VDDIOM EBI D2 I/O — — — — — — — — I, PD L22 VDDIOM EBI D3 I/O — — — — — — — — I, PD L20 VDDIOM EBI D4 I/O — — — — — — — — I, PD L21 VDDIOM EBI D5 I/O — — — — — — — — I, PD K21 VDDIOM EBI D6 I/O — — — — — — — — I, PD H22 VDDIOM EBI D7 I/O — — — — — — — — I, PD L19 VDDIOM EBI D8 I/O — — — — — — — — I, PD J22 VDDIOM EBI D9 I/O — — — — — — — — I, PD K19 VDDIOM EBI D10 I/O — — — — — — — — I, PD J21 VDDIOM EBI D11 I/O — — — — — — — — I, PD K22 VDDIOM EBI D12 I/O — — — — — — — — I, PD H20 VDDIOM EBI D13 I/O — — — — — — — — I, PD K20 VDDIOM EBI D14 I/O — — — — — — — — I, PD J20 VDDIOM EBI D15 I/O — — — — — — — — I, PD N20 VDDIOM EBI NCS3/NANDCS O — — — — — — — — O, PU M21 VDDIOM EBI NANDRDY I — — — — — — — — I, PU N22 VDDIOM EBI NRD/NANDOE O — — — — — — — — O, PU P22 VDDIOM EBI NWE/NANDWE O — — — — — — — — O, PU J13, J14 VDDIODDR Reference voltage DDR_VREF I — — — — — — — — I B13 VDDIODDR DDR_IO DDR_A0 O — — — — — — — — O C14 VDDIODDR DDR_IO DDR_A1 O — — — — — — — — O B16 VDDIODDR DDR_IO DDR_A2 O — — — — — — — — O C13 VDDIODDR DDR_IO DDR_A3 O — — — — — — — — O A14 VDDIODDR DDR_IO DDR_A4 O — — — — — — — — O D13 VDDIODDR DDR_IO DDR_A5 O — — — — — — — — O C12 VDDIODDR DDR_IO DDR_A6 O — — — — — — — — O B12 VDDIODDR DDR_IO DDR_A7 O — — — — — — — — O D12 VDDIODDR DDR_IO DDR_A8 O — — — — — — — — O A13 VDDIODDR DDR_IO DDR_A9 O — — — — — — — — O C11 VDDIODDR DDR_IO DDR_A10 O — — — — — — — — O B11 VDDIODDR DDR_IO DDR_A11 O — — — — — — — — O A12 VDDIODDR DDR_IO DDR_A12 O — — — — — — — — O A11 VDDIODDR DDR_IO DDR_A13 O — — — — — — — — O J19 VDDIODDR DDR_IO DDR_D0 I/O — — — — — — — — HiZ H21 VDDIODDR DDR_IO DDR_D1 I/O — — — — — — — — HiZ SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 24 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST F20 VDDIODDR DDR_IO DDR_D2 I/O — — — — — — — — HiZ G20 VDDIODDR DDR_IO DDR_D3 I/O — — — — — — — — HiZ F21 VDDIODDR DDR_IO DDR_D4 I/O — — — — — — — — HiZ H19 VDDIODDR DDR_IO DDR_D5 I/O — — — — — — — — HiZ G21 VDDIODDR DDR_IO DDR_D6 I/O — — — — — — — — HiZ D21 VDDIODDR DDR_IO DDR_D7 I/O — — — — — — — — HiZ G19 VDDIODDR DDR_IO DDR_D8 I/O — — — — — — — — HiZ D20 VDDIODDR DDR_IO DDR_D9 I/O — — — — — — — — HiZ C22 VDDIODDR DDR_IO DDR_D10 I/O — — — — — — — — HiZ C20 VDDIODDR DDR_IO DDR_D11 I/O — — — — — — — — HiZ B21 VDDIODDR DDR_IO DDR_D12 I/O — — — — — — — — HiZ C21 VDDIODDR DDR_IO DDR_D13 I/O — — — — — — — — HiZ D19 VDDIODDR DDR_IO DDR_D14 I/O — — — — — — — — HiZ F19 VDDIODDR DDR_IO DDR_D15 I/O — — — — — — — — HiZ B20 VDDIODDR DDR_IO DDR_D16 I/O — — — — — — — — HiZ E21 VDDIODDR DDR_IO DDR_D17 I/O — — — — — — — — HiZ E19 VDDIODDR DDR_IO DDR_D18 I/O — — — — — — — — HiZ C17 VDDIODDR DDR_IO DDR_D19 I/O — — — — — — — — HiZ D18 VDDIODDR DDR_IO DDR_D20 I/O — — — — — — — — HiZ HiZ A18 VDDIODDR DDR_IO DDR_D21 I/O — — — — — — — — C19 VDDIODDR DDR_IO DDR_D22 I/O — — — — — — — — HiZ C18 VDDIODDR DDR_IO DDR_D23 I/O — — — — — — — — HiZ C16 VDDIODDR DDR_IO DDR_D24 I/O — — — — — — — — HiZ A21 VDDIODDR DDR_IO DDR_D25 I/O — — — — — — — — HiZ D15 VDDIODDR DDR_IO DDR_D26 I/O — — — — — — — — HiZ A20 VDDIODDR DDR_IO DDR_D27 I/O — — — — — — — — HiZ B14 VDDIODDR DDR_IO DDR_D28 I/O — — — — — — — — HiZ A22 VDDIODDR DDR_IO DDR_D29 I/O — — — — — — — — HiZ A16 VDDIODDR DDR_IO DDR_D30 I/O — — — — — — — — HiZ D14 VDDIODDR DDR_IO DDR_D31 I/O — — — — — — — — HiZ E20 VDDIODDR DDR_IO DDR_DQM0 O — — — — — — — — O B22 VDDIODDR DDR_IO DDR_DQM1 O — — — — — — — — O B18 VDDIODDR DDR_IO DDR_DQM2 O — — — — — — — — O C15 VDDIODDR DDR_IO DDR_DQM3 O — — — — — — — — O G22 VDDIODDR DDR_IO DDR_DQS0 I/O — — — — — — — — I, PD E22 VDDIODDR DDR_IO DDR_DQS1 I/O — — — — — — — — I, PD A19 VDDIODDR DDR_IO DDR_DQS2 I/O — — — — — — — — I, PD B17 VDDIODDR DDR_IO DDR_DQS3 I/O — — — — — — — — I, PD F22 VDDIODDR DDR_IO DDR_DQSN0 I/O — — — — — — — — I, PU D22 VDDIODDR DDR_IO DDR_DQSN1 I/O — — — — — — — — I, PU B19 VDDIODDR DDR_IO DDR_DQSN2 I/O — — — — — — — — I, PU A17 VDDIODDR DDR_IO DDR_DQSN3 I/O — — — — — — — — I, PU C9 VDDIODDR DDR_IO DDR_CS O — — — — — — — — O SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 25 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Signal Alternate Power Rail I/O Type Dir Signal D17 VDDIODDR DDR_IO DDR_CLK O D16 VDDIODDR DDR_IO DDR_CLKN O A9 VDDIODDR DDR_IO DDR_CKE O — PIO Peripheral A PIO Peripheral B PIO Peripheral C Dir Reset State Signal, Dir, PU, PD, HiZ, ST Dir Signal Dir Signal Dir Signal — — — — — — — — O — — — — — — — — O — — — — — — — O A15 VDDIODDR DDR_IO DDR_CALN I — — — — — — — — O B15 VDDIODDR DDR_IO DDR_CALP I — — — — — — — — O B10 VDDIODDR DDR_IO DDR_RAS O — — — — — — — — O B9 VDDIODDR DDR_IO DDR_CAS O — — — — — — — — O A8 VDDIODDR DDR_IO DDR_WE O — — — — — — — — O D11 VDDIODDR DDR_IO DDR_BA0 O — — — — — — — — O A10 VDDIODDR DDR_IO DDR_BA1 O — — — — — — — — O C10 VDDIODDR DDR_IO DDR_BA2 O — — — — — — — — O P12 VBG VBG VBG I — — — — — — — — I AA17 VDDUTMII USBHS HHSDPC I/O — — — — — — — — O, PD AB17 VDDUTMII USBHS HHSDMC I/O — — — — — — — — O, PD O, PD AA15 VDDUTMII USBHS HHSDPB I/O — — — — — — — — AB15 VDDUTMII USBHS HHSDMB I/O — — — — — — — — O, PD AA13 VDDUTMII USBHS HHSDPA I/O DHSDP — — — — — — — O, PD AB13 VDDUTMII USBHS HHSDMA I/O DHSDM — — — — — — — O, PD N13 VDDBU Power supply VDDBU I — — — — — — — — I N12 GNDBU Ground GNDBU I — — — — — — — — I Y17, Y19, AA20, AA22, AB20, AB22 VDDCORE Power supply VDDCORE I — — — — — — — — I Y10, Y11, AA10, AA12, AB10, AB12 GNDCORE Ground GNDCORE I — — — — — — — — I J12, K12, K13, K14, L12 VDDIODDR Power supply VDDIODDR I — — — — — — — — I L13, L14, M12, M13, N11 GNDIODDR Ground GNDIODDR I — — — — — — — — I M14, U19 VDDIOM Power supply VDDIOM I — — — — — — — — I N14, P14 GNDIOM Ground GNDIOM I — — — — — — — — I J9, J10 VDDIOP0 Power supply VDDIOP0 I — — — — — — — — I P9, P10 VDDIOP1 Power supply VDDIOP1 I — — — — — — — — I J11, K11, L11, M11 GNDIOP Ground GNDIOP I — — — — — — — — I AB18 VDDUTMIC Power supply VDDUTMIC I — — — — — — — — I AA18 VDDUTMII Power supply VDDUTMII I — — — — — — — — I SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 26 Table 4-2. SAMA5D3 Pinout for 324-ball TFBGA Package (Continued) Primary Pin Power Rail I/O Type Signal Alternate Dir Signal Dir PIO Peripheral A Signal Dir PIO Peripheral B Signal Dir PIO Peripheral C Signal Dir Reset State Signal, Dir, PU, PD, HiZ, ST P13 GNDUTMI Ground GNDUTMI I — — — — — — — — I W14 VDDPLLA Power supply VDDPLLA I — — — — — — — — I W15 GNDPLL Ground GNDPLL I — — — — — — — — I AB21 VDDOSC Power supply VDDOSC I — — — — — — — — I P11 GNDOSC Ground GNDOSC I — — — — — — — — I M4 VDDANA Power supply VDDANA I — — — — — — — — I P4 GNDANA Ground GNDANA I — — — — — — — — I I N4 VDDANA Power supply ADVREF I — — — — — — — — W4 VDDFUSE Power supply VDDFUSE I — — — — — — — — I V4 GNDFUSE Ground GNDFUSE I — — — — — — — — I SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 27 4.5 Input/Output Description Table 4-3. SAMA5 I/O Types Description I/O Type Voltage Range Analog Pull-up Pull-up Typ. Value (Ohm) Pull-down Pull-down Typ. Value (Ohm) Schmitt Trigger GPIO 1.65–3.6V — Switchable 100K Switchable 100K Switchable GPIO_CLK 1.65–3.6V — Switchable 100K Switchable 100K Switchable GPIO_CLK2 1.65–3.6V — Switchable 100K Switchable 100K Switchable GPIO_ANA 3.0–3.6V I Switchable 100K — — Switchable EBI 1.65–1.95V, 3.0–3.6V — Switchable 100K Switchable 100K — RSTJTAG 3.0–3.6V — Reset State 100K Reset State 100K Reset State SYSC 1.65–3.6V — — — Reset State 15K Reset State USBHS 3.0–3.6V I/O — — — — — CLOCK 1.65–3.6V I/O — — — — — DIB 3.0–3.6V I/O — — — — — When “Reset State” is indicated, the configuration is defined by the “Reset State” column of the Pin Description table (see Table 4-1 on page 11). Table 4-4. SAMA5 I/O Type Assignation and Frequency I/O Type Max I/O Frequency (MHz) Load (pF) Fan-out Drive Control Signal Name GPIO 33 40 — High/Medium/Low All PIO lines except the lines indicated further on in this table MCI_CLK 52 20 — High/Medium/Low MCI0CK, MCI1CK, MCI2CK GPIO_CLK 66 20 — High/Medium/Low SPI0CK, SPI1CK, ETXCLK, ERXCLK GPIO_CLK2 75 20 — High/Medium/Low LCDDOTCK GPIO_ANA 25 20 Fixed to Medium ADx EBI 66 50 — DDR_IO 166 20 — High/Medium/Low All DDR signals RST 3 10 — Fixed to Low NRST, NTRST, BMS JTAG 10 10 — Fixed to Medium TCK, TDI, TMS, TDO SYSC 0.25 10 — No WKUP, SHDN, JTAGSEL, TST, SHDN VBG 0.25 10 — No VBG USBHS 480 20 — No HHSDPC, HHSDPB, HHSDPA/DHSDP, HHSDMC, HHSDMB, HHSDMA/DHSDM CLOCK 50 50 — No XIN, XOUT, XIN32, XOUT32 GMAC 125 15 — High/Medium/Low Gigabit Ethernet I/Os 16 mA, 40 mA (peak) High/Medium/Low 1.8V/3.3V All EBI signals SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 28 5. Power Considerations 5.1 Power Supplies Table 5-1 defines the power supply rails and the estimated power consumption at typical voltage. Table 5-1. SAMA5D3 Power supplies Name Voltage Range, Nominal Associated Ground Powers VDDCORE 1.1–1.32V, 1.2V The core, including the processor, the embedded memories and the peripherals VDDIODDR VDDIOM 1.7–1.9V, 1.8V 1.14–1.30, 1.2V 1.65–1.95V, 1.8V 3.0–3.6V, 3.3V GNDCORE GNDIODDR LPDDR/DDR2 Interface I/O lines LPDDR2 Interface I/O lines GNDIOM NAND and HSMC Interface I/O lines VDDIOP0 1.65–3.6V GNDIOP Peripheral I/O lines VDDIOP1 1.65–3.6V GNDIOP Peripheral I/O lines VDDBU 1.65–3.6V GNDBU The Slow Clock Oscillator, the internal 32 kHz RC Oscillator and a part of the System Controller The USB device and host UTMI+ core VDDUTMIC 1.1–1.32V, 1.2V GNDUTMI VDDUTMII 3.0–3.6V, 3.3V GNDUTMI The USB device and host UTMI+ interface VDDPLLA 1.1–1.32V, 1.2V GNDPLL The PLLA cell VDDOSC 1.65–3.6V GNDOSC Main Oscillator Cell and PLL UTMI. If PLL UTMI is used the range is to be 3.0V to 3.6V. VDDANA 3.0–3.6V, 3.3V GNDANA The Analog-to-Digital Converter VDDFUSE 2.25–2.75V, 2.5V GNDFUSE The UTMI PLL Fuse box for programming. 5.2 It can be tied to ground with a 100 Ω resistor for fuse reading only. Power-up Consideration The user must first activate VDDIOP and VDDIOM, then VDDPLL and VDDCORE with the constraint that VDDPLL is established no later than 1 ms after VDDCORE. The VDDCORE and VDDBU power supplies rising time must be defined according to the Core and Backup Power-OnReset characteristics to ensure VDDCORE or VDDBU has reached VIH after the POR reset time. Please refer to the “Core Power Supply POR Characteristics” and “Backup Power Supply POR Characteristics” sections of the product datasheet for power-up constraints. 5.3 Power-down Consideration The user must remove VDDPLL first, then VDDCORE, and at last VDDIOP and VDDIOM, to ensure a reliable operation of the device. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 29 6. Memories Figure 6-1. Memory Mapping Internal Memory Mapping Addressl Memory Space 0x0000 0000 Notes: (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP 0x0000 0000 Internal Memories ROM 0x0020 0000 256 MBytes NFC SRAM 0x0FFF FFFF 0x1000 0000 0x0030 0000 EBI Chip Select 0 256 MBytes 0x1FFF FFFF 0x2000 0000 0xF000 4000 DDRCS Peripheral Mapping 0x0031 0000 HSMCI0 0x0040 0000 SPI0 0x0050 0000 SRAM0 0xF000 0000 0xF000 8000 SSC0 UDPH SRAM 0x0060 0000 UHP OHCI 0xF000 C000 512 MBytes SRAM1 SMD CAN0 0xF001 0000 0x0070 0000 UHP EHCI 0x0080 0000 TC0, TC1, TC2 TWI0 EBI Chip Select 1 0xF001 8000 256 MBytes DAP 0x00A0 0000 Undefined (Abort) TWI1 0xF001 C000 0x4FFF FFFF 0x5000 0000 AXI Matrix 0x0090 0000 0xF001 4000 0x3FFF FFFF 0x4000 0000 0x0FFF FFFF USART0 EBI Chip Select 2 0xF002 0000 USART1 256 MBytes 0xF002 4000 0x5FFF FFFF 0x6000 0000 UART0 EBI Chip Select 3 0xF002 8000 256 MBytes GMAC System Controller Mapping 0xF002 C000 PWMC 0x6FFF FFFF 0x7000 0000 0xFFFF C000 0xF003 0000 NFC Command Registers 256 MBytes LCDC 0xF003 4000 Reserved 0xF003 8000 SFR 0xF003 C000 0xFFFF E400 FUSE Reserved 0xFFFF E600 HSMCI1 0xFFFF E800 HSMCI2 0xFFFF EA00 SPI1 0xFFFF EC00 SSC1 0xFFFF EE00 CAN1 0xFFFF F000 TC3, TC4, TC5 0xFFFF F200 TSADC 0xFFFF F400 0xF800 0000 DMAC0 0xF800 4000 DMAC1 0xF800 8000 MPDDRC 0xF800 C000 0xF801 0000 0xF801 4000 0xF801 8000 Undefined (Abort) MATRIX DBGU AIC PIOA 0xF801 C000 PIOB TWI2 0xFFFF F600 USART2 0xFFFF F800 0xF802 0000 PIOC 0xF802 4000 PIOD USART3 0xFFFF FA00 0xF802 8000 UART1 0xF802 C000 EMAC 0xF803 0000 UDPHS 0xF803 8000 0xFFFF FE10 0xFFFF FE20 0xFFFF FE30 AES 256 MBytes PMC 0xFFFF FE00 SHDC SHA Internal Peripherals PIOE 0xFFFF FC00 RSTC 0xF803 4000 0xEFFF FFFF 0xF000 0000 0xF803 C000 Reserved PITC 0xFFFF FE40 WDT TDES 0xF804 0000 0xFFFF FE50 0xFFFF FE54 0xFFFF FE60 Reserved 0xFFFF FE70 0xFFFF FEB0 0xFFFF C000 SYSC SCKC_CR BSC TRNG 0xF804 4000 0xFFFF FFFF HSMC 0xFFFF D000 ISI 0x7FFF FFFF 0xFFFF FFFF (1) Boot Memory 0x0010 0000 GPBR Reserved RTCC 0xFFFF FEE0 0xFFFF FFFF Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 30 6.1 Embedded Memories 6.1.1 Internal SRAM The SAMA5D3 product embeds a total of 128 Kbytes high-speed SRAM0 and SRAM1. After Remap the SRAM is accessible at address 0 but also at address 0x00300000. Only the ARM core has access to the SRAM at address 0. The others masters (DMA, peripherals, etc.) always access the SRAM at address 0x00300000. SRAM0 and SRAM1 can be accessed in parallel to improve the overall bandwidth of the system. 6.1.2 Internal ROM The SAMA5D3 product embeds one 160-Kbyte internal ROM containing a standard and a secure bootloader. The secure bootloader is described in a separate document, under NDA. The standard bootloader supports booting from:  8-bit NAND Flash with ECC management  SPI Serial Flash  SDCARD  EMMC  TWI EEPROM The boot sequence can be selected using the boot order facility (Boot Select Control Register). The internal ROM embeds Galois field tables that are used to compute NandFlash ECC. Please refer to Figure 12-9 “Galois Field Table Mapping” in the “Boot Strategies” section of this datasheet. 6.1.3 Boot Strategies For standard boot strategies, please refer to the “Boot Strategies” section of this datasheet. For secure boot strategies, please refer to the Application Note “Secure Boot on SAMA5D3 Series” (NDA required). 6.2 External Memory The SAMA5D3 features interfaces to offer connexion to a wide range of external memories or to parallel peripherals. 6.2.1 6.2.2 DDR2/LPDDR/LPDDR2 Interface  32-bit external interface  512 Mbytes address space on CS1  Supports DDR2, LPDDR and LPDDR2 memories  Drive level control  I/O impedance control embedded  Supports 4-banks and 8-banks and up to 512 Mbytes  Multi-port Static Memories and NAND Flash The static memory controller is dedicated to interfacing external memory devices: The static memory controller is able to drive up to four chip selects. NCS3 is dedicated to the NAND Flash control.  Asynchronous SRAM-like memories and parallel peripherals  NAND Flash (8-bit MLC and SLC) The HSMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 31 In order to improve overall system performance the DATA phase of the transfer can be DMA assisted. The static memory embeds a NAND Flash Error Correcting Code controller with the features as follows:  Algorithm based on BCH codes  Supports also SLC 1-bit (BCH 2-bit), SLC 4-bit (BCH 4-bit)  Programmable Error Correcting Capability:  2-bit, 4-bit, 8-bit and 16-bit errors for 512 bytes/sector (4 Kbyte page)  24-bit error for 1024 bytes/sector (8 Kbyte page)  Programmable sector size: 512 bytes or 1024 bytes  Programmable number of sector per page: 1, 2, 4 or 8 blocks of data per page  Programmable spare area size  Supports spare area ECC protection  Supports 8 Kbyte page size using 1024 bytes/sector and 4 Kbyte page size using 512 bytes/sector  Error detection is interrupt driven  Provides hardware acceleration for error location  Finds roots of error-locator polynomial  Programmable number of roots SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 32 7. Real-time Event Management The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 7.1 Embedded Characteristics Peripherals generate event triggers which are directly routed to event managers such as ADC, for example, to start measurement/conversion without processor intervention. 7.2 Real-time Event Mapping List Table 7-1. Real-time Event Mapping List Event Generator Event Manager PMC Pulse Width Modulation (PWM) Analog-to-Digital Converter (ADC) PWM Function Safety / Puts the PWM Outputs in Safe Mode (Main Crystal Clock Failure Detection) Safety / Puts the PWM Outputs in Safe Mode (Overspeed, Overcurrent detection, etc.) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 33 8. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories. The System Controller’s peripherals are all mapped within the highest 16 KB of address space, between addresses 0xFFFF D000 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 8-1 on page 35 shows the System Controller block diagram. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 34 Figure 8-1. SAMA5D3 System Controller Block Diagram VDDCORE Powered System Controller nirq irq_vect irq fiq periph_irq[2..42] pit_irq wdt_irq dbgu_irq nfiq fiq_vect Advanced Interrupt Controller Cortex-A5 pmc_irq por_ntrst ntrst proc_nreset rstc_irq PCK MCK periph_nreset Debug Unit dbgu_irq dbgu_txd dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset debug Periodic Interval Timer pit_irq Watchdog Timer wdt_irq jtag_nreset Boundary Scan TAP Controller MCK periph_nreset Bus Matrix wdt_fault WDRPROC NRST por_ntrst jtag_nreset VDDCORE POR Reset Controller periph_nreset proc_nreset backup_nreset VDDBU VDDBU POR VDDBU Powered UPLLCK UHP48M UHP12M SLCK SLCK backup_nreset Real-Time Clock rtc_irq periph_nreset rtc_alarm periph_irq[32] USB High Speed Host Port SLCK SHDN WKUP backup_nreset rtc_alarm UPLLCK Shut-Down Controller periph_nreset XIN32 XOUT32 SLOW CLOCK OSC 32 kHz RC OSC XIN USB High Speed Device Port periph_irq[33] SCKC_CR 12 MHz RC OSC XOUT 4 General-purpose Backup Registers SLCK int MAINCK 12 MHz MAIN OSC SMDCK UPLL UPLLCK PLLA PLLACK Power Management Controller periph_clk[2..49] pck[0-1] UHP48M UHP12M PCK MCK DDR sysclk LCD Pixel clock pmc_irq idle SMDCK = periph_clk[11] SMDCK periph_nreset SMD Software Modem periph_irq[11] periph_clk[2..49] periph_nreset periph_nreset periph_nreset periph_clk[5.9] dbgu_rxd PA0-PA31 PIO Controllers PB0-PB31 periph_irq[5..9] irq fiq dbgu_txd Embedded Peripherals periph_irq[2..49] in out enable PC0-PC31 PD0-PD31 PE0-PE31 Fuse Box SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 35 8.1 Chip Identification  Chip ID: 0x8A5C07C2  Extended ID: Table 8-1. 8.2 Chip Identification of SAMA5D3 Devices Device Extended ID SAMA5D31 0x00444300 SAMA5D33 0x00414300 SAMA5D34 0x00414301 SAMA5D35 0x00584300 SAMA5D36 0x00004301  Boundary JTAG ID: 0x05B3103F  Cortex-A5 JTAG IDCODE: 0x4BA00477  Cortex-A5 Serial Wire IDCODE: 0x2BA01477 Backup Section The SAMA5D3 features a Backup Section that embeds:  RC Oscillator  Slow Clock Oscillator  SCKR register  Real-time Clock (RTC)  Shutdown Controller  4 Backup registers  Part of the Reset Controller (RSTC)  Boot Select Control Register This section is powered by the VDDBU rail. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 36 9. Peripherals 9.1 Peripheral Mapping As shown in Section 6. “Memories” the peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFF7 8000 and 0xFFFC FFFF. Each user peripheral is allocated 16 Kbytes of address space. 9.2 Peripheral Identifiers Table 9-1. Peripheral Identifiers Instance Interrupt ID Name Description External Wired-OR Clock Type 0 AIC Advanced Interrupt Controller FIQ — SYS_CLK 1 SYS System Controller Interrupt — PMC, RSTC, RTC SYS_CLK 2 DBGU Debug Unit Interrupt — — PCLOCK 3 PIT Periodic Interval Timer Interrupt — — SYS_CLK 4 WDT Watchdog timer Interrupt — — SYS_CLK 5 HSMC Multi-bit ECC Interrupt — — HCLOCK 6 PIOA Parallel I/O Controller A — — PCLOCK 7 PIOB Parallel I/O Controller B — — PCLOCK 8 PIOC Parallel I/O Controller C — — PCLOCK 9 PIOD Parallel I/O Controller D — — PCLOCK 10 PIOE Parallel I/O Controller E — — PCLOCK 11 SMD SMD Soft Modem — — HCLOCK 12 USART0 USART 0 — — PCLOCK 13 USART1 USART 1 — — PCLOCK 14 USART2 USART 2 — — PCLOCK 15 USART3 USART 3 — — PCLOCK 16 UART0 UART 0 — — PCLOCK 17 UART1 UART 1 — — PCLOCK 18 TWI0 Two-Wire Interface 0 — — PCLOCK 19 TWI1 Two-Wire Interface 1 — — PCLOCK 20 TWI2 Two-Wire Interface 2 — — PCLOCK 21 HSMCI0 High Speed Multimedia Card Interface 0 — — PCLOCK 22 HSMCI1 High Speed Multimedia Card Interface 1 — — PCLOCK 23 HSMCI2 High Speed Multimedia Card Interface 2 — — PCLOCK 24 SPI0 Serial Peripheral Interface 0 — — PCLOCK 25 SPI1 Serial Peripheral Interface 1 — — PCLOCK 26 TC0 Timer Counter 0 (ch. 0, 1, 2) — — PCLOCK 27 TC1 Timer Counter 1 (ch. 3, 4, 5) — — PCLOCK SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 37 Table 9-1. Peripheral Identifiers (Continued) Instance Interrupt ID Name Description External Wired-OR Clock Type 28 PWM Pulse Width Modulation Controller — — PCLOCK 29 ADC Touch Screen ADC Controller — — PCLOCK 30 DMAC0 DMA Controller 0 — — HCLOCK 31 DMAC1 DMA Controller 1 — — HCLOCK 32 UHPHS USB Host High Speed — — HCLOCK 33 UDPHS USB Device High Speed — — HCLOCK 34 GMAC Gigabit Ethernet MAC — — HCLOCK + PCLOCK 35 EMAC Ethernet MAC — — HCLOCK + PCLOCK 36 LCDC LCD Controller — — HCLOCK 37 ISI Image Sensor Interface — — HCLOCK 38 SSC0 Synchronous Serial Controller 0 — — PCLOCK 39 SSC1 Synchronous Serial Controller 1 — — PCLOCK 40 CAN0 CAN Controller 0 — — PCLOCK 41 CAN1 CAN Controller 1 — — PCLOCK 42 SHA Secure Hash Algorithm — — PCLOCK 43 AES Advanced Encryption Standard — — PCLOCK 44 TDES Triple Data Encryption Standard — — PCLOCK 45 TRNG True Random Number Generator — — PCLOCK 46 ARM Performance Monitor Unit — — PROC_CLOCK 47 AIC Advanced Interrupt Controller IRQ — SYS_CLK 48 FUSE Fuse Controller — — PCLOCK 49 MPDDRC MPDDR controller — — HCLOCK 50-63 Reserved — — — — SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 38 9.3 Peripheral Signal Multiplexing on I/O Lines The SAMA5D3 product features five PIO controllers (PIOA, PIOB, PIOC, PIOD and PIOE) which multiplex the I/O lines of the peripheral set. Each PIO Controller controls 32 lines. Each line can be assigned to one of three peripheral functions: A, B or C. The multiplexing tables (Table 4-1 “SAMA5D3 Pinout for 324-ball LFBGA Package” and Table 4-2 “SAMA5D3 Pinout for 324ball TFBGA Package”) define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO controllers. Note that some output-only peripheral functions might be duplicated within the tables. The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 9.4 Peripheral Clock Type The SAMA5D3 Series embeds peripherals with five different clock types:  HCLOCK: AHB Clock, managed with the PMC_SCER, PMC_SCDR and PMC_SCSR registers of PMC System Clock  PCLOCK: APB Clock, managed with the PMC_PCER, PMC_PCDR, PMC_PCSR and PMC_PCR registers of Peripheral Clock  HCLOCK+PCLOCK: Both clock types coexist. The clock is managed with the PMC_PCER, PMC_PCDR, PMC_PCSR and PMC_PCR registers of Peripheral Clock  SYS_CLOCK: This clock cannot be disabled.  PROC_CLOCK: The clock related to Processor Clock (PCK) and managed with the PMC_SCDR and PMC_SCSR registers of PMC System Clock Please refer to Table 9-1 “Peripheral Identifiers” for details. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 39 10. ARM Cortex-A5 Processor 10.1 Description The ARM Cortex-A5 processor is a high-performance, low-power, ARM macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A5 processor implements the ARMv7 architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java™ byte codes in Jazelle® state. The Floating-Point Unit (FPU) supports the ARMv7 VFPv4-D16 architecture without Advanced SIMD extensions (NEON). It is tightly integrated to the Cortex-A5 processor pipeline. It provides trapless execution and is optimized for scalar operation. It can generate an Undefined instruction exception on vector instructions that enables the programmer to emulate vector capability in software. The design can include the FPU only, in which case the Media Processing Engine (MPE) is not included. See the Cortex-A5 Floating-Point Unit Technical Reference Manual. 10.1.1 Power Management The Cortex-A5 design supports the following main levels of power management:  Run Mode  Standby Mode 10.1.1.1 Run Mode Run mode is the normal mode of operation where all of the processor functionality is available. Everything, including core logic and embedded RAM arrays, is clocked and powered up. 10.1.1.2 Standby Mode Standby mode disables most of the clocks of the processor, while keeping it powered up. This reduces the power drawn to the static leakage current, plus a small clock power overhead required to enable the processor to wake up from Standby mode. The transition from Standby mode to Run mode is caused by one of the following: 10.2  the arrival of an interrupt, either masked or unmasked  the arrival of an event, if standby mode was initiated by a Wait for Event (WFE) instruction  a debug request, when either debug is enabled or disabled  a reset. Embedded Characteristics  In-order pipeline with dynamic branch prediction  ARM, Thumb, and ThumbEE instruction set support  Harvard level 1 memory system with a Memory Management Unit (MMU)  32 Kbytes Data Cache  32 Kbytes Instruction Cache  64-bit AXI master interface  ARM v7 debug architecture  VFPv4-D16 FPU with trapless execution  Jazelle hardware acceleration SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 40 10.3 Block Diagram Figure 10-1. Cortex-A5 Processor Top-level Diagram '&   &   '    "#$%   $                  & #      !   & #                !        ! )%     ! $(!   10.4 Programmer Model 10.4.1 Processor Operating Modes The following operation modes are present in all states:  User mode (USR) is the usual ARM program execution state. It is used for executing most application programs.  Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process.  Interrupt (IRQ) mode is used for general-purpose interrupt handling.  Supervisor mode (SVC) is a protected mode for the operating system.  Abort mode (ABT) is entered after a data or instruction prefetch abort.  System mode (SYS) is a privileged user mode for the operating system.  Undefined mode (UND) is entered when an undefined instruction exception occurs. Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 10.4.2 Processor Operating States The processor has the following instruction set states controlled by the T bit and J bit in the CPSR.  ARM state: The processor executes 32-bit, word-aligned ARM instructions. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 41  Thumb state: The processor executes 16-bit and 32-bit, halfword-aligned Thumb instructions.  ThumbEE state: The processor executes a variant of the Thumb instruction set designed as a target for dynamically generated code. This is code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation.  Jazelle state: The processor executes variable length, byte-aligned Java bytecodes. The J bit and the T bit determine the instruction set used by the processor. Table 10-1 shows the encoding of these bits. Table 10-1. CPSR J and T Bit Encoding J T Instruction Set State 0 0 ARM 0 1 Thumb 1 0 Jazelle 1 1 ThumbEE Changing between ARM and Thumb states does not affect the processor mode or the register contents. See the ARM Architecture Reference Manual for information on entering and exiting ThumbEE state. 10.4.2.1 Switching State It is possible to change the instruction set state of the processor between:  ARM state and Thumb state using the BX and BLX instructions.  Thumb state and ThumbEE state using the ENTERX and LEAVEX instructions.  ARM and Jazelle state using the BXJ instruction.  Thumb and Jazelle state using the BXJ instruction. See the ARM Architecture Reference Manual for more information about changing instruction set state. 10.4.3 Cortex-A5 Registers This view provides 16 ARM core registers, R0 to R15, that include the Stack Pointer (SP), Link Register (LR), and Program Counter (PC). These registers are selected from a total set of either 31 or 33 registers, depending on whether or not the Security Extensions are implemented. The current execution mode determines the selected set of registers, as shown in Table 10-2. This shows that the arrangement of the registers provides duplicate copies of some registers, with the current register selected by the execution mode. This arrangement is described as banking of the registers, and the duplicated copies of registers are referred to as banked registers. Table 10-2. Cortex-A5 Modes and Registers Layout User and System Monitor Supervisor Abort Undefined Interrupt Fast Interrupt R0 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R6 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 42 Table 10-2. Cortex-A5 Modes and Registers Layout (Continued) User and System Monitor Supervisor Abort Undefined Interrupt Fast Interrupt R7 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12 R12_FIQ R13 R13_MON R13_SVC R13_ABT R13_UND R13_IRQ R13_FIQ R14 R14_MON R14_SVC R14_ABT R14_UND R14_IRQ R14_FIQ PC PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR CPSR SPSR_MON SPSR_SVC SPSR_ABT SPSR_UND SPSR_IRQ SPSR_FIQ Mode-specific banked registers The core contains one CPSR, and six SPSRs for exception handlers to use. The program status registers:  hold information about the most recently performed ALU operation  control the enabling and disabling of interrupts  set the processor operation mode Figure 10-2. Status Register Format 31 30 29 28 27 N Z C V Q 24 23 20 19 IT J Reserved [1:0] 16 15 GE[3:0] 10 9 8 7 6 5 4 IT[7:2] E A I F T 0 Mode  N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags  Q: cumulative saturation flag  IT: If-Then execution state bits for the Thumb IT (If-Then) instruction  J: Jazelle bit, see the description of the T bit  GE: Greater than or Equal flags, for SIMD instructions  E: Endianness execution state bit. Controls the load and store endianness for data accesses. This bit is ignored by instruction fetches.  E = 0: Little endian operation  E = 1: Big endian operation  A: Asynchronous abort disable bit. Used to mask asynchronous aborts.  I: Interrupt disable bit. Used to mask IRQ interrupts.  F: Fast interrupt disable bit. Used to mask FIQ interrupts.  T: Thumb execution state bit. This bit and the J execution state bit, bit [24], determine the instruction set state of the processor, ARM, Thumb, Jazelle, or ThumbEE. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 43  Mode: five bits to encode the current processor mode. The effect of setting M[4:0] to a reserved value is UNPREDICTABLE. Table 10-3. Processor Mode vs. Mode Field Mode M[4:0] USR 10000 FIQ 10001 IRQ 10010 SVC 10011 ABT 10111 UND 11011 SYS 11111 Reserved Other 10.4.3.1 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:  Cortex A5  Caches (ICache, DCache and write buffer)  MMU  Security  Other system options To control these features, CP15 provides 16 additional registers. See Table 10-4. Table 10-4. CP15 Registers Register Name Read/Write (1) 0 ID Code Read/Unpredictable 0 Cache type(1) Read/Unpredictable 1 (1) Control Read/Write (1) Read/Write 1 Security 2 Translation Table Base Read/Write 3 Domain Access Control Read/Write 4 Reserved None (1) 5 Data fault Status Read/Write 5 Instruction fault status Read/Write 6 Fault Address Read/Write 7 Cache and MMU Operations 8 TLB operations (1) Read/Write Unpredictable/Write (1) 9 Cache lockdown 10 TLB lockdown Read/Write 11 Reserved None 12 Interrupts management Read/Write 13 (1) Read/Write FCSE PID Read/Write SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 44 Table 10-4. CP15 Registers (Continued) Register Note: Name Read/Write 13 Context ID(1) Read/Write 14 Reserved None 15 Test configuration Read/Write 1. This register provides access to more than one register. The register accessed depends on the value of the CRm field or Opcode_2 field. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 45 10.4.4 CP 15 Register Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions such as CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR/MRC instructions bit pattern is shown below: 31 30 29 28 27 1 26 1 21 20 L 19 18 13 12 11 1 5 4 1 3 cond 23 22 opcode_1 15 14 Rd 7 6 opcode_2 25 1 24 0 17 16 10 1 9 1 8 1 2 1 0 CRn CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • L: Instruction Bit 0: MCR instruction 1: MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 46 10.4.5 Addresses in the Cortex-A5 processor The Cortex-A5 processor operates using virtual addresses (VAs). The Memory Management Unit (MMU) translates these VAs into the physical addresses (PAs) used to access the memory system. Translation tables hold the mappings between VAs and PAs. See the ARM Architecture Reference Manual for more information. When the Cortex-A5 processor is executing in Non-secure state, the processor performs translation table look-ups using the Non-secure versions of the Translation Table Base Registers. In this situation, any VA can only translate into a Nonsecure PA. When it is in Secure state, the Cortex-A5 processor performs translation table look-ups using the Secure versions of the Translation Table Base Registers. In this situation, the security state of any VA is determined by the NS bit of the translation table descriptors for that address. Following is an example of the address manipulation that occurs when the Cortex-A5 processor requests an instruction: 1. The Cortex-A5 processor issues the VA of the instruction as Secure or Non-secure VA accesses according to the state the processor is in. 2. The instruction cache is indexed by the bits of the VA. The MMU performs the translation table look-up in parallel with the cache access. If the processor is in the Secure state it uses the Secure translation tables, otherwise it uses the Non-secure translation tables. 3. If the protection check carried out by the MMU on the VA does not abort and the PA tag is in the instruction cache, the instruction data is returned to the processor. 4. If there is a cache miss, the MMU passes the PA to the AXI bus interface to perform an external access. The external access is always Non-secure when the core is in the Non-secure state. In the Secure state, the external access is Secure or Non-secure according to the NS attribute value in the selected translation table entry. In Secure state, both L1 and L2 translation table walk accesses are marked as Secure, even if the first level descriptor is marked as NS. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 47 10.5 Memory Management Unit 10.5.1 About the MMU The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also controls accesses to and from external memory. The ARM v7 Virtual Memory System Architecture (VMSA) features include the following:  Page table entries that support:  16-Mbyte supersections. The processor supports supersections that consist of 16-Mbyte blocks of memory.  1-Mbyte sections  64-Kbyte large pages  4-Kbyte small pages  16 access domains  Global and application-specific identifiers to remove the requirement for context switch TLB flushes.  Extended permissions checking capability. TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated with the core. This coprocessor provides a standard mechanism for configuring the L1 memory system. See the ARM Architecture Reference Manual for a full architectural description of the ARMv7 VMSA. 10.5.2 Memory Management System The Cortex-A5 processor supports the ARM v7 VMSA The translation of a Virtual Address (VA) used by the instruction set architecture to a Physical Address (PA) used in the memory system and the management of the associated attributes and permissions is carried out using a two-level MMU. The first level MMU uses a Harvard design with separate micro TLB structures in the PFU for instruction fetches (IuTLB) and in the DPU for data read and write requests (DuTLB). A miss in the micro TLB results in a request to the main unified TLB shared between the data and instruction sides of the memory system. The TLB consists of a 128-entry two-way set-associative RAM based structure. The TLB page-walk mechanism supports page descriptors held in the L1 data cache. The caching of page descriptors is configured globally for each translation table base register, TTBRx, in the system coprocessor, CP15. The TLB contains a hitmap cache of the page types which have already been stored in the TLB. 10.5.2.1 Memory types Although various different memory types can be specified in the page tables, the Cortex-A5 processor does not implement all possible combinations:  Write-through caches are not supported. Any memory marked as write-through is treated as Non-cacheable.  The outer shareable attribute is not supported. Anything marked as outer shareable is treated in the same way as inner shareable.  Write-back no write-allocate is not supported. It is treated as write-back write-allocate. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 48 Table 10-5 shows the treatment of each different memory type in the Cortex-A5 processor in addition to the architectural requirements. Table 10-5. Treatment of Memory Attributes Memory Type Attribute Shareability Other attributes Notes — — — Non-shareable — — Shareable — — Non-cacheable Does not access L1 caches Write-through cacheable Treated as non-cacheable Write-back cacheable, write allocate Can dynamically switch to no write allocate, if more than three full cache lines are written in succession Write-back cacheable, no write allocate Treated as non-shareable write-back cacheable, write allocate Non-cacheable — Write-through cacheable Treated as inner shareable non-cacheable Write-back cacheable, write allocate Treated as inner shareable non-cacheable unless the SMP bit in the Auxiliary Control Register is set (ACTLR[6] = b1). If this bit is set the area is treated as write-back cacheable write allocate. Strongly Ordered Device Non-shareable Inner shareable Normal Write-back cacheable, no write allocate Non-cacheable Treated as inner shareable non-cacheable Write-through cacheable Outer shareable Write-back cacheable, write allocate Write-back cacheable, no write allocate Treated as inner shareable non-cacheable unless the SMP bit in the Auxiliary Control Register is set (ACTLR[6] = b1). If this bit is set the area is treated as write-back cacheable write allocate. 10.5.3 TLB Organization TLB Organization is described in the sections that follow:  Micro TLB  Main TLB 10.5.3.1 Micro TLB The first level of caching for the page table information is a micro TLB of 10 entries that is implemented on each of the instruction and data sides. These blocks provide a lookup of the virtual addresses in a single cycle. The micro TLB returns the physical address to the cache for the address comparison, and also checks the access permissions to signal either a Prefetch Abort or a Data Abort. All main TLB related maintenance operations affect both the instruction and data micro TLBs, causing them to be flushed. In the same way, any change of the following registers causes the micro TLBs to be flushed:  Context ID Register (CONTEXTIDR)  Domain Access Control Register (DACR)  Primary Region Remap Register (PRRR)  Normal Memory Remap Register (NMRR)  Translation Table Base Registers (TTBR0 and TTBR1) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 49 10.5.3.2 Main TLB Misses from the instruction and data micro TLBs are handled by a unified main TLB. Accesses to the main TLB take a variable number of cycles, according to competing requests from each of the micro TLBs and other implementationdependent factors. The main TLB is 128-entry two-way set-associative. TLB match process Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory properties. Each is marked as being associated with a particular application space (ASID), or as global for all application spaces. The CONTEXTIDR determines the currently selected application space. A TLB entry matches when these conditions are true:  its virtual address matches that of the requested address  its Non-secure TLB ID (NSTID) matches the Secure or Non-secure state of the MMU request  its ASID matches the current ASID in the CONTEXTIDR or is global The operating system must ensure that, at most, one TLB entry matches at any time. The TLB can store entries based on the following block sizes: Supersections Describe 16-Mbyte blocks of memory. Sections Describe 1-Mbyte blocks of memory. Large pages Describe 64-Kbyte blocks of memory. Small pages Describe 4-Kbyte blocks of memory Supersections, sections and large pages are supported to permit mapping of a large region of memory while using only a single entry in the TLB. If no mapping for an address is found within the TLB, then the translation table is automatically read by hardware and a mapping is placed in the TLB. 10.5.4 Memory Access Sequence When the processor generates a memory access, the MMU: 1. Performs a lookup for the requested virtual address and current ASID and security state in the relevant instruction or data micro TLB. 2. If there is a miss in the micro TLB, performs a lookup for the requested virtual address and current ASID and security state in the main TLB. 3. If there is a miss in main TLB, performs a hardware translation table walk. The MMU can be configured to perform hardware translation table walks in cacheable regions by setting the IRGN bits in Translation Table Base Register 0 and Translation Table Base Register 1. If the encoding of the IRGN bits is write-back, an L1 data cache lookup is performed and data is read from the data cache. If the encoding of the IRGN bits is writethrough or non-cacheable, an access to external memory is performed. For more information refer to: Cortex-A5 Technical Reference Manual. The MMU might not find a global mapping, or a mapping for the currently selected ASID, with a matching Non-secure TLB ID (NSTID) for the virtual address in the TLB. In this case, the hardware does a translation table walk if the translation table walk is enabled by the PD0 or PD1 bit in the Translation Table Base Control Register. If translation table walks are disabled, the processor returns a Section Translation fault. For more information refer to: Cortex-A5 Technical Reference Manual. If the TLB finds a matching entry, it uses the information in the entry as follows: 1. The access permission bits and the domain determine if the access is enabled. If the matching entry does not pass the permission checks, the MMU signals a memory abort. See the ARM Architecture Reference Manual for a SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 50 description of access permission bits, abort types and priorities, and for a description of the Instruction Fault Status Register (IFSR) and Data Fault Status Register (DFSR). 2. The memory region attributes specified in both the TLB entry and the CP15 c10 remap registers determine if the access is  Secure or Non-secure  Shared or not  Normal memory, Device, or Strongly-ordered For more information refer to: Cortex-A5 Technical Reference Manual, Memory region remap. 3. The TLB translates the virtual address to a physical address for the memory access. 10.5.5 Interaction with Memory System The MMU can be enabled or disabled as described in the ARM Architecture Reference Manual. 10.5.6 External Aborts External memory errors are defined as those that occur in the memory system rather than those that are detected by the MMU. External memory errors are expected to be extremely rare. External aborts are caused by errors flagged by the AXI interfaces when the request goes external to the Cortex-A5 processor. External aborts can be configured to trap to Monitor mode by setting the EA bit in the Secure Configuration Register. For more information refer to: Cortex-A5 Technical Reference Manual. 10.5.6.1 External Aborts on Data Write Externally generated errors during a data write can be asynchronous. This means that the r14_abt on entry into the abort handler on such an abort might not hold the address of the instruction that caused the exception. The DFAR is Unpredictable when an asynchronous abort occurs. Externally generated errors during data read are always synchronous. The address captured in the DFAR matches the address which generated the external abort. 10.5.6.2 Synchronous and Asynchronous Aborts Chapter 4, System Control in the Cortex-A5 Technical Reference Manual describes synchronous and asynchronous aborts, their priorities, and the IFSR and DFSR. To determine a fault type, read the DFSR for a data abort or the IFSR for an instruction abort. The processor supports an Auxiliary Fault Status Register for software compatibility reasons only. The processor does not modify this register because of any generated abort. 10.5.7 MMU Software Accessible Registers The system control coprocessor registers, CP15, in conjunction with page table descriptors stored in memory, control the MMU. Access all the registers with instructions of the form: MRC p15, 0, , , , MCR p15, 0, , , , CRn is the system control coprocessor register. Unless specified otherwise, CRm and Opcode_2 Should Be Zero. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 51 11. SAMA5D3 Series Debug and Test 11.1 Description The device features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. A 2-pin debug port Serial Wire Debug (SWD). SWD replaces the 5-pin JTAG port and provides an easy and risk free alternative to JTAG as the two signals SWDIO and SWCLK are overlaid on the TMS and TCK pins, allowing for bi-modal devices that provide the other JTAG signals. These extra JTAG pins can be switched to other uses when in SWD mode. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 11.2 Embedded Characteristics    Cortex-A5 Real-time In-circuit Emulator  Two real-time Watchpoint Units  Two Independent Registers: Debug Control Register and Debug Status Register  Test Access Port Accessible through JTAG Protocol  Debug Communications Channel  Serial Wire Debug Debug Unit  Two-pin UART  Debug Communication Channel Interrupt Handling  Chip ID Register IEEE1149.1 JTAG Boundary-scan on All Digital Pins. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 52 Block Diagram Figure 11-1. Debug and Test Block Diagram TMS / SWDIO TCK / SWCLK TDI NTRST SWD/ICE/JTAG SELECT Boundary Port JTAGSEL TDO SWD DEBUG PORT ICE/JTAG DEBUG PORT POR Reset and Test TST Cortex-A5 DTXD DMA DBGU PIO 11.3 DRXD SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 53 11.4 Application Examples 11.4.1 Debug Environment Figure 11-2 on page 54 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 11-2. Application Debug and Trace Environment Example Host Debugger PC ICE/JTAG Interface ICE/JTAG Connector SAM device RS232 Connector Terminal SAM-based Application Board SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 54 11.4.2 Test Environment Figure 11-3 on page 55 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 11-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Chip n SAM device Chip 2 Chip 1 SAM-based Application Board In Test SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 55 11.5 Debug and Test Pin Description Table 11-1. Debug and Test Pin List Pin Name Function Type Active Level Input/Output Low Input High Low Reset/Test NRST Microcontroller Reset TST Test Mode Select ICE and JTAG NTRST Test Reset Signal Input TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Input JTAGSEL JTAG Selection Input Output SWD SWCLK Serial Debug Clock SWDIO Serial Debug IO Input Input/Output Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 56 11.6 Functional Description 11.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 11.6.2 EmbeddedICE The Cortex-A5 EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface.The internal state of the Cortex-A5 is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the Cortex-A5 registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the Cortex-A5 processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document: ARM IHI 0031A_ARM_debug_interface_v5.pdf 11.6.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel Cortex-A5-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. 11.6.4 Chip Access Using JTAG Connection In some cases, the JTAG connection is not allowed on this chip (JMem, SAM-BA, etc.) due to the Secure ROM Code implementation. By default, the SAMA5D3 devices boot in Standard mode and not in Secure mode. When the Secure ROM Code starts, it disables the JTAG access for the whole boot sequence. If the Secure ROM Code does not find any program in the external memory, it enables the USB connection and waits for a dedicated command to switch the chip into Secure mode. If any other character is received, the Secure ROM Code starts the Standard SAM-BA Monitor, locks access to the ROM memory, and enables the JTAG. Then you can access to the chip using the JTAG connection. If the Secure ROM Code finds a bootable program, it disables automatically ROM access and enables JTAG just before launching the program. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 57 The procedure to enable JTAG access is as follows:  Connect your computer to the board with JTAG and USB (J20 USB-A)  Power on the chip  Open a terminal console (TeraTerm or HyperTerminal, etc.) on your computer and connect to the USB CDC Serial COM port related to the J20 connector on the board  Send the '#' character. You will see then the prompt '>' character sent by the device (indicating that the Standard SAM-BA Monitor is running)  Use the Standard SAM-BA Monitor to connect to the chip with JTAG Note that you don't need to follow this sequence in order to connect the Standard SAM-BA Monitor with USB. 11.6.5 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. For further details on the Debug Unit, see the Debug Unit section. 11.6.6 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 58 11.7 The Boundary JTAG ID Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B31 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B3_103F. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 59 11.8 The Cortex-A5 DP Identification Code Register IDCODE The Identification Code Register is always present on all DP implementations. It provides identification information about the ARM Debug Interface. 11.8.1 JTAG Debug Port (JTAG-DP) It is accessed using its own scan chain, the JTAG-DP Device ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 9 8 PART NUMBER 15 14 13 12 11 10 PART NUMBER 7 6 DESIGNER 5 4 3 2 1 DESIGNER 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0xBA00 • DESIGNER[11:1] Set to 0x23B. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. Cortex-A5 JTAG-DP IDCODE value is 0x0BA0_0477 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 60 11.8.2 Serial Wire Debug Port (SW-DP) It is at address 0x0 on read operations when the APnDP bit = 0. Access to the Identification Code Register is not affected by the value of the CTRLSEL bit in the Select Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 9 8 PART NUMBER 15 14 13 12 11 10 PART NUMBER 7 6 DESIGNER 5 4 3 2 1 DESIGNER 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0xBA01 • DESIGNER[11:1] Set to 0x23B. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. Cortex-A5 SW-DP IDCODE is 0x0BA0_1477 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 61 12. Standard Boot Strategies The system always boots from the ROM memory at address 0x0. The ROM Code is a boot program contained in the embedded ROM. It is also called “First level bootloader”. This microcontroller can be configured to run a Standard Boot Mode or a Secure Boot Mode. More information on how the Secure Boot Mode can be enabled, and how the chip operates in this mode, is provided in the application note “Secure Boot on SAMAD3 Series”, literature number 11165A. Please refer to the Atmel web site at www.atmel.com. By default, the chip starts in Standard Boot Mode. Note: JTAG access is disabled during the execution of ROM Code Sequence. It is re-enabled when jumping into SRAM when a valid code has been found on an external NVM, in the same time the ROM memory is hidden. If no valid boot has been found on an external NVM, the ROM Code enables the USB connection and waits for a special command to set the chip in Secure mode. If any other character is received, the ROM Code starts the Standard SAM-BA Monitor, locks access to the ROM memory and re-enables the JTAG. The user can choose to boot from an external NOR Flash memory with the help of the BMS pin. The sampling of the BMS pin is done by hardware at reset, and the result is available in the BMS_EBI bit of the SFR_EBICFG register. The first steps of the ROM Code program is to check the state of this pin by reading this register. If BMS signal is tied to 0, BMS_BIT is read at 1 The ROM Code allows execution of the code contained into the memory connected to Chip Select 0 of the External Bus Interface. To achieve that, the following sequence is preformed by the ROM Code:  The main clock is the on-chip 12 MHz RC oscillator  The Static Memory Controller is configured with timing allowing code execution inCS0 external memory at 12 MHz  AXI matrix is configured to remap EBI CS0 address at 0x0  0x0 is loaded in the Program Counter register The user software in the external memory must perform the next operation in order to complete the clocks and SMC timings configuration to run at a higher clock frequency:  Enable the 32768 Hz oscillator if best accuracy is needed  Reprogram the SMC setup, cycle, hold, mode timing registers for EBI CS0, to adapt them to the new clock  Program the PMC (Main Oscillator Enable or Bypass mode)  Program and Start the PLL  Switch the system clock to the new value If BMS signal is tied to 1, BMS_BIT is read at 0 The ROM Code standard sequence is executed as follows:  Basic chip initialization: crystal or external clock frequency detection  Attempt to retrieve a valid code from external non-volatile memories (NVM)  Execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 62 12.1 Flow Diagram The ROM Code implements the algorithm shown in Figure 12-1. Figure 12-1. ROM Code Algorithm Flow Diagram Chip Setup Valid boot code found in one NVM Yes Copy and run it in internal SRAM No SAM-BA Monitor 12.2 Chip Setup At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz fast RC oscillator. Initialization follows the steps described below: 1. Stack Setup for ARM supervisor mode 2. Main Oscillator Detection: The Main Clock is switched to the 32 kHz RC oscillator to allow external clock frequency to be measured. Then the Main Oscillator is enabled and set in the bypass mode. If the MOSCSELS bit rises, an external clock is connected, and the next step is Main Clock Selection (3). If not, the bypass mode is cleared to attempt external quartz detection. This detection is successful when the MOSCXTS and MOSCSELS bits rise, else the internal 12 MHz fast RC oscillator is used as the Main Clock. 3. Main Clock Selection: The Master Clock source is switched from the Slow Clock to the Main Oscillator without prescaler. The PMC Status Register is polled to wait for MCK Ready. PCK and MCK are now the Main Clock. 4. C Variable Initialization: Non zero-initialized data is initialized in the RAM (copy from ROM to RAM). Zero-initialized data is set to 0 in the RAM. 5. PLLA Initialization: PLLA is configured to get a PCK at 96 MHz and an MCK at 48 MHz. If an external clock or crystal frequency running at 12 MHz is found, then the PLLA is configured to allow communication on the USB link for the SAM-BA Monitor; else the Main Clock is switched to the internal 12 MHz fast RC oscillator, but USB will not be activated. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 63 12.3 NVM Boot 12.3.1 NVM Boot Sequence The boot sequence on external memory devices can be controlled using the Boot Sequence Configuration Register (BSC_CR). The user can then choose to bypass some steps shown in Figure 12-2 “NVM Bootloader Sequence Diagram” according to the BOOT value in the BSC_CR. Table 12-1. Values of the Boot Sequence Configuration Register BOOT Value SPI0 NPCS0 SD Card / eMMC (MCI0) SD Card / eMMC (MCI1) 8-bit NAND Flash SPI0 NPCS1 TWI EEPROM SAM-BA Monitor 0 Y Y Y Y Y Y Y 1 Y — Y Y Y Y Y 2 Y — — Y Y Y Y 3 Y — — — Y Y Y 4 Y — — — Y Y Y 5 — — — — — — Y 6 — — — — — — Y 7 — — — — — — Y SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 64 Figure 12-2. NVM Bootloader Sequence Diagram Device Setup SPI0 CS0 Flash Boot Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from SD Card to SRAM Run SD Card Bootloader Yes Copy from NAND Flash to SRAM Run NAND Flash Bootloader Yes Copy from SPI Flash to SRAM Run SPI Flash Bootloader Yes Copy from TWI EEPROM to SRAM Run TWI EEPROM Bootloader No SD Card Boot No NAND Flash Boot No SPI0 CS1 Flash Boot No TWI EEPROM Boot No SAM-BA Monitor SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 65 12.3.2 NVM Bootloader Program Description Figure 12-3. NVM Bootloader Program Diagram Start Initialize NVM Initialization OK ? No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the PC to 0 to jump to the downloaded application End SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 66 The NVM bootloader program first initializes the PIOs related to the NVM device. Then it configures the right peripheral depending on the NVM and tries to access this memory. If the initialization fails, it restores the reset values for the PIO and the peripheral, and then tries to fulfill the same operations on the next NVM of the sequence. If the initialization is successful, the NVM bootloader program reads the beginning of the NVM and determines if the NVM contains a valid code. If the NVM does not contain a valid code, the NVM bootloader program restores the reset value for the peripherals and then tries to fulfill the same operations on the next NVM of the sequence. If a valid code is found, this code is loaded from the NVM into the internal SRAM and executed by branching at address 0x0000_0000 after remap. This code may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. Figure 12-4. Remap Action after Download Completion 0x0000_0000 0x0000_0000 REMAP Internal ROM Internal SRAM 0x0010_0000 0x0010_0000 Internal ROM Internal ROM 0x0030_0000 0x0030_0000 Internal SRAM Internal SRAM 12.3.3 Valid Code Detection There are two kinds of valid code detection. 12.3.3.1 ARM Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM instructions for either branch or load PC with PC relative addressing. Figure 12-5. LDR Opcode 31 1 28 27 1 1 0 0 24 23 1 I P U 20 19 1 W 0 16 15 Rn 12 11 Rd 0 Offset Figure 12-6. B Opcode 31 1 28 27 1 1 0 1 24 23 0 1 0 0 Offset (24 bits) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 67 Unconditional instruction: 0xE for bits 31 to 28. Load PC with the PC relative addressing instruction:  Rn = Rd = PC = 0xF  I==0 (12-bit immediate value)  P==1 (pre-indexed)  U offset added (U==1) or subtracted (U==0)  W==1 The sixth vector, at the offset 0x14, contains the size of the image to download. The user must replace this vector with the user’s own vector. This procedure is described below. Figure 12-7. Structure of the ARM Vector 6 31 0 Size of the code to download in bytes The value has to be smaller than 64 Kbytes. Example An example of valid vectors: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B0x20 B0x04 B_main B0x0c B0x10 B0x14’ Read commands: Read a byte (o), a halfword (h) or a word (w) from the target  Address: Address in hexadecimal  Output: The byte, halfword or word read in hexadecimal followed by ‘>’ Send a file (S): Send a file to a specified address  Address: Address in hexadecimal  Output: ‘>’ There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. Receive a file (R): Receive data into a file from a specified address  Address: Address in hexadecimal  NbOfBytes: Number of bytes in hexadecimal to receive  Output: ‘>’ Go (G): Jump to a specified address and execute the code  Address: Address to jump in hexadecimal  Output: ‘>’ once returned from the program execution. If the executed program does not handle the link register at its entry and does not return, the prompt will not be displayed Get Version (V): Return the Boot Program version  Output: version, date and time of ROM code followed by ‘>’ 12.4.2 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115,200 Baud, 8 bits of data, no parity, 1 stop bit. 12.4.2.1 Supported External Crystal/External Clocks The SAM-BA Monitor supports a frequency of 12, 16, 24 or 48 MHz to allow DBGU communication for both external crystal and external clock. 12.4.2.2 Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory in order to work. The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC16 to guarantee detection of maximum bit errors. Xmodem protocol with CRC is supported by successful transmission reports provided both by a sender and by a receiver. Each transfer block is as follows: in which:  = 01 hex  = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)  = 1’s complement of the blk#.  = 2 bytes CRC16 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 75 Figure 12-11 shows a transmission using this protocol. Figure 12-11.Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 12.4.3 USB Device Port 12.4.3.1 Supported External Crystal / External Clocks The SAM-BA Monitor supports a frequency of 12, 16, 24 or 48 MHz to allow USB communication for both external crystal and external clock. 12.4.3.2 USB Class The device uses the USB Communication Device Class (CDC) drivers to take advantage of the installed PC Serial Communication software to talk over the USB. The CDC class is implemented in all releases of Windows®, from Windows 98SE® to Windows 7®. The CDC document, available at www.usb.org, describes how to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is the Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, INF files contain the correspondence between vendor ID and product ID. 12.4.3.3 Enumeration Process The USB protocol is a master/slave protocol. The host starts the enumeration, sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 12-5. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value SET_ADDRESS Sets the device address for all future device access SET_CONFIGURATION Sets the device configuration GET_CONFIGURATION Returns the current device configuration value GET_STATUS Returns status for the specified recipient SET_FEATURE Used to set or enable a specific feature CLEAR_FEATURE Used to clear or disable a specific feature SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 76 The device also handles some class requests defined in the CDC class. Table 12-6. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits SET_CONTROL_LINE_STATE RS-232 signal used to indicate to the DCE device that the DTE device is now present Unhandled requests are STALLed. 12.4.3.4 Communication Endpoints Endpoint 0 is used for the enumeration process. Endpoint 1 (64-byte Bulk OUT) and endpoint 2 (64-byte Bulk IN) are used as communication endpoints. SAM-BA Boot commands are sent by the host through Endpoint 1. If required, the message is split into several data payloads by the host driver. If the command requires a response, the host sends IN transactions to pick up the response. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 77 13. Boot Sequence Controller (BSC) 13.1 Description The System Controller embeds a Boot Sequence Configuration Register (BSC_CR) to save timeout delays on boot. The boot sequence is programmable through the BSC_CR. The BSC_CR is powered by VDDBU. Any modification of the register value is stored and applied after the next reset. The register defaults to the factory value in case of battery removal. The BSC_CR is programmable with user programs or SAM-BA and is key-protected. 13.2 Embedded Characteristics  13.3 VDDBU powered register Product Dependencies  Product-dependent order SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 78 13.4 Boot Sequence Controller (BSC) Registers User Interface Table 13-1. Register Mapping Offset 0x0 Register Name Boot Sequence Configuration Register BSC_CR Access Reset Read-write – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 79 13.4.1 Boot Sequence Configuration Register Name: BSC_CR Address: 0xFFFFFE54 Access: Read-write Factory Value: 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 – 10 – 9 – 8 – 3 2 1 0 WPKEY 23 22 21 20 WPKEY 15 – 14 – 13 – 12 – 7 6 5 4 BOOT • BOOT: Boot media sequence This value is defined in the product-dependent ROM code. It is only written if WPKEY carries the valid value. • WPKEY: Write Protect Key (Write-only) Value Name 0x6683 PASSWD Description Writing any other value in this field aborts the write operation of the BOOT field. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 80 14. AXI Bus Matrix (AXIMX) 14.1 Description The AXI Bus Matrix (AXIMX) comprises the embedded Advanced EXtensible Interface (AXI) bus protocol which supports separate address/control and data phases, unaligned data transfers using byte strobes, burst-based transactions with only start address issued, separate read and write data channels to enable low-cost DMA, ability to issue multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to provide timing closure. 14.2 Embedded Characteristics  High Performance AXI Network Interconnect  1 AXI Slave Interface  1 AHB-Lite Slave Interface  3 AXI Master Interfaces  1 APB3 Slave Interface  Single-cycle Arbitration  Full Pipelining to prevent Master Stalls  2 Remap States SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 81 14.3 Operation 14.3.1 Remap There are two remap states using bits 0 and 1 in the Remap Register (AXIMX_REMAP)  Bit 1 is used to remap EBI @ addr 0x00000000 for external boot.  Bit 0 is used to remap RAM @ addr 0x00000000 Refer to Section 14.4 ”AXI Matrix (AXIMX) User Interface" and Table 14-1, “Register Mapping”. The number of remap states can be defined using eight bits of the remap register, and a bit in the remap register controls each remap state. Each remap state can be used to control the address decoding for one or more slave interfaces. If a slave interface is affected by two remap states that are both asserted, the remap state with the lowest remap bit number takes precedence. Each slave interface can be configured independently so that a remap state can perform different functions for different masters. A remap state can:  Alias a memory region into two different address ranges  Move an address region  Remove an address region Because of the nature of the distributed register sub-system, the masters receive the updated remap bit states in sequence, and not simultaneously. A slave interface does not update to the latest remap bit setting until:  The address completion handshake accepts any transaction that is pending  Any current lock sequence completes The BRESP from a GPV after a remap update guarantees that the next transaction issued to each slave interface, or the first one after the completion of a locked sequence, uses the updated value. The AXI Matrix uses two remap bits. At powerup, ROM is seen at address 0 After powerup, ahbslave can be moved down to address 0 by means of the remap bits. Figure 14-1 shows the memory map when remap is set to 000, representing no remap, SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 82 Figure 14-1. No Remap 0x00000000 ROM 0x000FFFFF 0x00100000 0x001FFFFF 0x00200000 0x002FFFFF 0x00300000 0x0007FFFFF 0x00800000 0x008FFFFF 0x00900000 0x09FFFFF 0x0A00000 0x001FFFFF 0x01000000 0x01FFFFFF 0x20000000 0x3FFFFFFF 0x40000000 ROM ahbslave ahbslave gpv_0 dap [apb3bridge] reserved ahbslave MPDDR ahbslave 0x7FFFFFFF 0x80000000 0xEFFFFFFF 0xF0000000 reserved ahbslave 0xFFFFFFFF Figure 14-2 shows mapping when remap state is 01 or 11. This state is used for RAM boot. RAM is seen at address 0 through ahbslave. Figure 14-2. Remap state is 01 or 11 0x00000000 ahbslave (RAM) 0x000FFFFF 0x00100000 0x001FFFFF 0x00200000 0x002FFFFF 0x00300000 0x0007FFFFF 0x00800000 ROM ahbslave ahbslave gpv_0 0x008FFFFF 0x00900000 0x09FFFFF 0x0A00000 0x001FFFFF 0x01000000 0x01FFFFFF 0x20000000 0x3FFFFFFF 0x40000000 dap [apb3bridge] reserved ahbslave MPDDR ahbslave 0x7FFFFFFF 0x80000000 0xEFFFFFFF 0xF0000000 0xFFFFFFFF reserved ahbslave Figure 14-3 shows mapping when remap state is 10. This state is used for external boot. EBI is seen at address 0 through ahbslave. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 83 Figure 14-3. Remap State is 10 0x00000000 ahbslave (EBI) 0x000FFFFF 0x00100000 0x001FFFFF 0x00200000 0x002FFFFF 0x00300000 0x0007FFFFF 0x00800000 ROM ahbslave ahbslave gpv_0 0x008FFFFF 0x00900000 0x009FFFFF 0x00A00000 0x001FFFFF 0x01000000 0x01FFFFFF 0x20000000 0x3FFFFFFF 0x40000000 dap[apb3bridge] reserved ahbslave MPDDR ahbslave 0x7FFFFFFF 0x80000000 0xEFFFFFFF 0xF0000000 0xFFFFFFFF reserved ahbslave SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 84 14.4 AXI Matrix (AXIMX) User Interface Table 14-1. Register Mapping Offset Register Name 0x00 Remap Register AXIMX_REMAP 0x04 - 0x43108 Reserved – Access Reset Write-only 0x00000000 – 0x00000000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 85 14.4.1 AXI Matrix Remap Register Name: AXIMX_REMAP Address: 0x00800000 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 – – 1 REMAP1 0 REMAP0 – 23 22 21 20 – 15 14 13 12 – 7 – 6 – 5 – 4 – REMAP0 has higher priority than REMAP1, i.e., if both REMAP0 & REMAP1 are asserted, the matrix is in remap state 0. • REMAP0: Remap State 0 SRAM is seen at address 0x00000000 (through AHB slave interface) instead of ROM. • REMAP1: Remap State 1 HEBI is seen at address 0x00000000 (through AHB slave interface) instead of ROM for external boot. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 86 15. Bus Matrix (MATRIX) 15.1 Description The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 AHB masters to up to 16 AHB slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus. 15.1.1 Matrix Masters The Bus Matrix of the SAMA5D3 product manages 15 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. List of Bus Matrix Masters Master 0 Cortex A5 Master 1, 2, 3 DMA Controller 0 Master 4, 5, 6 DMA Controller 1 Master 7 GMAC DMA Master 8, 9 LCDC DMA Master 10 UHP EHCI DMA Master 11 UHP OHCI DMA Master 12 UDPHS DMA Master 13 EMAC DMA Master 14 ISI DMA 15.1.2 Matrix Slaves The Bus Matrix of the SAMA5 product manages 13 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 15-1. List of Bus Matrix Slaves Slave 0 Internal SRAM0 Slave 1 Internal SRAM1 Slave 2 NFC SRAM Slave 3 Internal ROM Slave 4 Soft Modem (SMD) USB Device High Speed Dual Port RAM (DPR) Slave 5 USB Host OHCI registers USB Host EHCI registers Slave 6 External Bus Interface/NFC Slave 7 DDR2 Port0 Slave 8 DDR2 Port1 Slave 9 DDR2 Port2 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 87 Table 15-1. List of Bus Matrix Slaves Slave 10 DDR2 Port3 Slave 11 Peripheral Bridge 0 Slave 12 Peripheral Bridge 1 15.1.3 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 15-2. SAMA5 Master to Slave Access Masters Slaves 0 1 A5 2 3 DMAC0 4 5 6 7 GMAC DMA DMAC1 8 9 LCDC DMA 10 11 12 13 14 UHPHS EHCI DMA UHPHS OHCI DMA UDPHS DMA EMAC DMA ISI DMA 0 Internal SRAM0 X X X X X X X X 1 Internal SRAM1 X X X X X X X X 2 NFC SRAM X X 3 Internal ROM X X X X X 4 SMD X X X X X X X X X X UDPHS RAM 5 UHP OHCI Reg X UHP EHCI Reg EBI CS0..CS3 X NFC Command Register X 7 DDR2 Port 0 X 8 DDR2 port1 9 DDR2 port2 10 DDR2 port3 11 APB 0 X 12 APB 1 X 6 X X X X X X X X X X X X X X X X X SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 88 15.2 Embedded Characteristics  AMBA Advanced High-performance Bus (AHB Lite) Compliant Interfaces  32-bit or 64-bit Data Bus  APB Compliant User Interface  Configurable Number of Masters (Up to sixteen)  Configurable Number of Slaves (Up to sixteen)  One Decoder for Each Master  Several Possible Boot Memories for Each Master before Remap  One Remap Function for Each Master  Support for Long Bursts of 32, 64, 128 and Up to the 256-beat Word Burst AHB Limit  Enhanced Programmable Mixed Arbitration for Each Slave   Round-Robin  Fixed Priority Programmable Default Master for Each Slave  No Default Master  Last Accessed Default Master  Fixed Default Master  Deterministic Maximum Access Latency for Masters  Zero or One Cycle Arbitration Latency for the First Access of a Burst  Bus Lock Forwarding to Slaves  Master Number Forwarding to Slaves  One Special Function Register for Each Slave (Not dedicated)  Write Protection of User Interface Registers SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 89 15.3 Memory Mapping The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR), that performs remap action for every master independently. The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master independently. 15.4 Special Bus Granting Mechanism The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from masters. This mechanism reduces latency at first access of a burst, or for a single transfer, as long as the slave is free from any other master access. It does not provide any benefit if the slave is continuously accessed by more than one master, since arbitration is pipelined and has no negative effect on the slave bandwidth or access latency. This bus granting mechanism sets a different default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters:  No default master  Last access master  Fixed default master To change from one type of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for every slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Refer to Section 15.10.2 “Bus Matrix Slave Configuration Registers” on page 97. 15.5 No Default Master After the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave bus bandwidth is widely used by one or more masters. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever the number of requesting masters. 15.6 Last Access Master After the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for masters that mainly perform single accesses or short bursts with some Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput whatever is the number of requesting masters. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 90 15.7 Fixed Default Master After the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike the last access master, the fixed default master does not change unless the user modifies it by software (FIXED_DEFMSTR field of the related MATRIX_SCFG). This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-privileged masters will get one latency cycle. This technique is useful for a master that mainly performs single accesses or short bursts with Idle cycles in between. This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, regardless of the number of requesting masters. 15.8 Arbitration The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each slave specifically. The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for each slave: 1. Round-robin Arbitration (default) 2. Fixed Priority Arbitration The resulting algorithm may be complemented by selecting a default master configuration for each slave. When re-arbitration must be done, specific conditions apply. See Section 15.8.1 “Arbitration Scheduling” on page 91. 15.8.1 Arbitration Scheduling Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: When a slave is currently doing a single access. 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. See “Undefined Length Burst Arbitration” on page 91 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. See “Slot Cycle Limit Arbitration” on page 92 15.8.1.1 Undefined Length Burst Arbitration In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be selected from the following Undefined Length Burst Type (ULBT) possibilities: 1. Unlimited: no predetermined end of burst is generated. This value enables 1-kbyte burst lengths. 2. 1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer. 3. 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR transfer. 4. 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR transfer. 5. 16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR transfer. 6. 32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR transfer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 91 7. 64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR transfer. 8. 128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR transfer. The use of undefined length16-beat bursts, or less, is discouraged since this generally decreases significantly the overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. If the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kbyte address boundaries. Unless duly needed, the ULBT should be left at its default value of 0 for power saving. This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG). 15.8.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access cycle. Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled (SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by some Atmel masters. In most cases, this feature is not needed and should be disabled for power saving. Warning: This feature cannot prevent any slave from locking its access indefinitely. 15.8.2 Arbitration Priority Scheme The bus Matrix arbitration scheme is organized in priority pools. Round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority is used between priority pools and in the intermediate priority pools. For each slave, each master is assigned to one of the slave priority pools through the priority registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating master requests, this programmed priority level always takes precedence. After reset, all the masters belong to the lowest priority pool (MxPR = 0) and are therefore granted bus access in a true round-robin order. The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight and deterministic maximum access latency from AHB bus requests. In the worst case, any currently occurring high-priority master request will be granted after the current bus master access has ended and other high priority pool master requests, if any, have been granted once each. The lowest priority pool shares the remaining bus bandwidth between AHB Masters. Intermediate priority pools allow fine priority tuning. Typically, a moderately latency-critical master or a bandwidth-only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master priority. All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be assigned the highest priority pool (round-robin), and remaining masters the lowest priority pool (round-robin), with no master for intermediate fix priority levels. If more than one master requests the slave bus, regardless of the respective masters priorities, no master will be granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only requesting master. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 92 15.8.2.1 Fixed Priority Arbitration Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority pools). Fixed priority arbitration allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the MxPR field for each master in the Priority Registers, MATRIX_PRAS and MATRIX_PRBS. If two or more master requests are active at the same time, the master with the highest priority MxPR number is serviced first. In intermediate priority pools, if two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. 15.8.2.2 Round-Robin Arbitration This algorithm is only used in the highest and lowest priority pools. It allows the Bus Matrix arbiters to properly dispatch requests from different masters to the same slave. If two or more master requests are active at the same time in the priority pool, they are serviced in a round-robin increasing master number order. 15.9 Write Protect Registers To prevent any single software error that may corrupt the Bus Matrix behavior, the entire Bus Matrix address space can be write-protected by setting the WPEN bit in the Bus Matrix Write Protect Mode Register (MATRIX_WPMR). If WPEN is at one and a write access in the Bus Matrix address space is detected, then the WPVS flag in the Bus Matrix Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the Bus Matrix Write Protect Mode Register (MATRIX_WPMR) with the appropriate access key WPKEY. The protected registers are: “Bus Matrix Master Configuration Registers” “Bus Matrix Slave Configuration Registers” “Bus Matrix Priority Registers A For Slaves” “Bus Matrix Priority Registers B For Slaves” “Bus Matrix Master Remap Control Register” SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 93 15.10 Bus Matrix (MATRIX) User Interface Table 15-3. Register Mapping Offset Register Name Access Reset 0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read-write 0x00000001 0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read-write 0x00000000 0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read-write 0x00000000 0x000C Master Configuration Register 3 MATRIX_MCFG3 Read-write 0x00000000 0x0010 Master Configuration Register 4 MATRIX_MCFG4 Read-write 0x00000000 0x0014 Master Configuration Register 5 MATRIX_MCFG5 Read-write 0x00000000 0x0018 Master Configuration Register 6 MATRIX_MCFG6 Read-write 0x00000000 0x001C Master Configuration Register 7 MATRIX_MCFG7 Read-write 0x00000000 0x0020 Master Configuration Register 8 MATRIX_MCFG8 Read-write 0x00000000 0x0024 Master Configuration Register 9 MATRIX_MCFG9 Read-write 0x00000000 0x0028 Master Configuration Register 10 MATRIX_MCFG10 Read-write 0x00000000 0x002C Master Configuration Register 11 MATRIX_MCFG11 Read-write 0x00000000 0x0030 Master Configuration Register 12 MATRIX_MCFG12 Read-write 0x00000000 0x0034 Master Configuration Register 13 MATRIX_MCFG13 Read-write 0x00000000 0x0038 Master Configuration Register 14 MATRIX_MCFG14 Read-write 0x00000000 0x003C Master Configuration Register 15 MATRIX_MCFG15 Read-write 0x00000000 0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read-write 0x000001FF 0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read-write 0x000001FF 0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read-write 0x000001FF 0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read-write 0x000001FF 0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read-write 0x000001FF 0x0054 Slave Configuration Register 5 MATRIX_SCFG5 Read-write 0x000001FF 0x0058 Slave Configuration Register 6 MATRIX_SCFG6 Read-write 0x000001FF 0x005C Slave Configuration Register 7 MATRIX_SCFG7 Read-write 0x000001FF 0x0060 Slave Configuration Register 8 MATRIX_SCFG8 Read-write 0x000001FF 0x0064 Slave Configuration Register 9 MATRIX_SCFG9 Read-write 0x000001FF 0x0068 Slave Configuration Register 10 MATRIX_SCFG10 Read-write 0x000001FF 0x006C Slave Configuration Register 11 MATRIX_SCFG11 Read-write 0x000001FF 0x0070 Slave Configuration Register 12 MATRIX_SCFG12 Read-write 0x000001FF 0x0074 Slave Configuration Register 13 MATRIX_SCFG13 Read-write 0x000001FF 0x0078 Slave Configuration Register 14 MATRIX_SCFG14 Read-write 0x000001FF 0x007C Slave Configuration Register 15 MATRIX_SCFG15 Read-write 0x000001FF 0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read-write 0x33333333(1) 0x0084 Priority Register B for Slave 0 MATRIX_PRBS0 Read-write 0x33333333(1) 0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read-write 0x33333333(1) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 94 Table 15-3. Register Mapping (Continued) Offset Register Name Access Reset 0x008C Priority Register B for Slave 1 MATRIX_PRBS1 Read-write 0x33333333(1) 0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read-write 0x33333333(1) 0x0094 Priority Register B for Slave 2 MATRIX_PRBS2 Read-write 0x33333333(1) 0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read-write 0x33333333(1) 0x009C Priority Register B for Slave 3 MATRIX_PRBS3 Read-write 0x33333333(1) 0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Read-write 0x33333333(1) 0x00A4 Priority Register B for Slave 4 MATRIX_PRBS4 Read-write 0x33333333(1) 0x00A8 Priority Register A for Slave 5 MATRIX_PRAS5 Read-write 0x33333333(1) 0x00AC Priority Register B for Slave 5 MATRIX_PRBS5 Read-write 0x33333333(1) 0x00B0 Priority Register A for Slave 6 MATRIX_PRAS6 Read-write 0x33333333(1) 0x00B4 Priority Register B for Slave 6 MATRIX_PRBS6 Read-write 0x33333333(1) 0x00B8 Priority Register A for Slave 7 MATRIX_PRAS7 Read-write 0x33333333(1) 0x00BC Priority Register B for Slave 7 MATRIX_PRBS7 Read-write 0x33333333(1) 0x00C0 Priority Register A for Slave 8 MATRIX_PRAS8 Read-write 0x33333333(1) 0x00C4 Priority Register B for Slave 8 MATRIX_PRBS8 Read-write 0x33333333(1) 0x00C8 Priority Register A for Slave 9 MATRIX_PRAS9 Read-write 0x33333333(1) 0x00CC Priority Register B for Slave 9 MATRIX_PRBS9 Read-write 0x33333333(1) 0x00D0 Priority Register A for Slave 10 MATRIX_PRAS10 Read-write 0x33333333(1) 0x00D4 Priority Register B for Slave 10 MATRIX_PRBS10 Read-write 0x33333333(1) 0x00D8 Priority Register A for Slave 11 MATRIX_PRAS11 Read-write 0x33333333(1) 0x00DC Priority Register B for Slave 11 MATRIX_PRBS11 Read-write 0x33333333(1) 0x00E0 Priority Register A for Slave 12 MATRIX_PRAS12 Read-write 0x33333333(1) 0x00E4 Priority Register B for Slave 12 MATRIX_PRBS12 Read-write 0x33333333(1) 0x00E8 Priority Register A for Slave 13 MATRIX_PRAS13 Read-write 0x33333333(1) 0x00EC Priority Register B for Slave 13 MATRIX_PRBS13 Read-write 0x33333333(1) 0x00F0 Priority Register A for Slave 14 MATRIX_PRAS14 Read-write 0x33333333(1) 0x00F4 Priority Register B for Slave 14 MATRIX_PRBS14 Read-write 0x33333333(1) 0x00F8 Priority Register A for Slave 15 MATRIX_PRAS15 Read-write 0x33333333(1) 0x00FC Priority Register B for Slave 15 MATRIX_PRBS15 Read-write 0x33333333(1) 0x0100 Master Remap Control Register MATRIX_MRCR Read-write 0x00000000 0x0104 - 0x010C Reserved – – – 0x01A0 - 0x01E0 Reserved – – – 0x01E4 Write Protect Mode Register MATRIX_WPMR Read-write 0x00000000 0x01E8 Write Protect Status Register MATRIX_WPSR Read-only 0x00000000 Notes: 1. Values in the Bus Matrix Priority Registers are product dependent. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 95 15.10.1 Bus Matrix Master Configuration Registers Name: MATRIX_MCFG0...MATRIX_MCFG15 Address: 0xFFFFEC00 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” . • ULBT: Undefined Length Burst Type 0: Unlimited Length Burst No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1 Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 1: Single Access The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 2: 4-beat Burst The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 3: 8-beat Burst The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 4: 16-beat Burst The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 5: 32-beat Burst The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 6: 64-beat Burst The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 7: 128-beat Burst The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Unless duly needed, the ULBT should be left at its default 0 value for power saving. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 96 15.10.2 Bus Matrix Slave Configuration Registers Name: MATRIX_SCFG0...MATRIX_SCFG15 Address: 0xFFFFEC40 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – 15 14 13 12 11 10 9 8 – – – – – – – SLOT_CYCLE 7 6 5 4 3 2 1 0 FIXED_DEFMSTR DEFMSTR_TYPE SLOT_CYCLE This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” . • SLOT_CYCLE: Maximum Bus Grant Duration for Masters When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place to let another master access this slave. If another master is requesting the slave bus, then the current master burst is broken. If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to the ULBT. This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for slave access. This limit must not be too small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. The default maximum value is usually an optimal conservative choice. In most cases, this feature is not needed and should be disabled for power saving. See “Slot Cycle Limit Arbitration” on page 92 for details. • DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having one clock cycle latency when the last master tries to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one clock cycle latency when the fixed master tries to access the slave again. • FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 97 15.10.3 Bus Matrix Priority Registers A For Slaves Name: MATRIX_PRAS0...MATRIX_PRAS15 Address: 0xFFFFEC80 [0], 0xFFFFEC88 [1], 0xFFFFEC90 [2], 0xFFFFEC98 [3], 0xFFFFECA0 [4], 0xFFFFECA8 [5], 0xFFFFECB0 [6], 0xFFFFECB8 [7], 0xFFFFECC0 [8], 0xFFFFECC8 [9], 0xFFFFECD0 [10], 0xFFFFECD8 [11], 0xFFFFECE0 [12], 0xFFFFECE8 [13], 0xFFFFECF0 [14], 0xFFFFECF8 [15] Access: Read-write 31 30 – – 23 22 – – 15 14 – – 7 6 – – 29 28 M7PR 21 20 M5PR 13 12 M3PR 5 4 M1PR 27 26 – – 19 18 – – 11 10 – – 3 2 – – 25 24 M6PR 17 16 M4PR 9 8 M2PR 1 0 M0PR This register can only be written if the WPE bit is cleared in the “Write Protect Mode Register” . • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See “Arbitration Priority Scheme” on page 92 for details. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 98 15.10.4 Bus Matrix Priority Registers B For Slaves Name: MATRIX_PRBS0...MATRIX_PRBS15 Address: 0xFFFFEC84 [0], 0xFFFFEC8C [1], 0xFFFFEC94 [2], 0xFFFFEC9C [3], 0xFFFFECA4 [4], 0xFFFFECAC [5], 0xFFFFECB4 [6], 0xFFFFECBC [7], 0xFFFFECC4 [8], 0xFFFFECCC [9], 0xFFFFECD4 [10], 0xFFFFECDC [11], 0xFFFFECE4 [12], 0xFFFFECEC [13], 0xFFFFECF4 [14], 0xFFFFECFC [15] Access: Read-write 31 30 – – 23 22 – – 15 14 – – 7 6 – – 29 28 M15PR 21 20 M13PR 13 12 M11PR 5 4 M9PR 27 26 – – 19 18 – – 11 10 – – 3 2 – – 25 24 M14PR 17 16 M12PR 9 8 M10PR 1 0 M8PR This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” . • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. All the masters programmed with the same MxPR value for the slave make up a priority pool. Round-robin arbitration is used in the lowest (MxPR = 0) and highest (MxPR = 3) priority pools. Fixed priority is used in intermediate priority pools (MxPR = 1) and (MxPR = 2). See “Arbitration Priority Scheme” on page 92 for details. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 99 15.10.5 Bus Matrix Master Remap Control Register Name: MATRIX_MRCR Address: 0xFFFFED00 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 RCB15 RCB14 RCB13 RCB12 RCB11 RCB10 RCB9 RCB8 7 6 5 4 3 2 1 0 RCB7 RCB6 RCB5 RCB4 RCB3 RCB2 RCB1 RCB0 This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” . • RCB: Remap Command Bit for Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 100 15.10.6 Write Protect Mode Register Name: MATRIX_WPMR Address: 0xFFFFEDE4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN For more details on MATRIX_WPMR, refer to Section 15.9 “Write Protect Registers” on page 93. The protected registers are: “Bus Matrix Master Configuration Registers” “Bus Matrix Slave Configuration Registers” “Bus Matrix Priority Registers A For Slaves” “Bus Matrix Priority Registers B For Slaves” “Bus Matrix Master Remap Control Register” • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII). Protects the entire Bus Matrix address space from address offset 0x000 to 0x1FC. • WPKEY: Write Protect KEY (Write-only) Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 101 15.10.7 Write Protect Status Register Name: MATRIX_WPSR Address: 0xFFFFEDE8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS For more details on MATRIX_WPSR, refer to Section 15.9 “Write Protect Registers” on page 93. • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last write of the MATRIX_WPMR. 1: At least one Write Protect Violation has occurred since the last write of the MATRIX_WPMR. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the register address offset in which a write access has been attempted. Otherwise it reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 102 16. Special Function Registers (SFR) 16.1 Description Special Function Registers (SFR) manage specific aspects of the integrated memory, bridge implementations, processor and other functionality not controlled elsewhere. 16.2 Embedded Characteristics  32-bit Special Function Registers control specific behavior of the product SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 103 16.3 Special Function Registers (SFR) User Interface Table 16-1. Register Mapping Offset Register 0x00–0x04 Reserved 0x08–0x0C Reserved Name Access Reset – – – – – – 0x10 OHCI Interrupt Configuration Register SFR_OHCIICR Read-write 0x0 0x14 OHCI Interrupt Status Register SFR_OHCIISR Read-only – 0x18 Reserved – – – 0x1C Reserved – – – 0x20–0x24 Reserved – – – Read-write 0x0 – – 0x28 Security Configuration Register SFR_SECURE 0x2C Reserved 0x30 UTMI Clock Trimming Register SFR_UTMICKTRIM Read-write 0x00010000 0x40 EBI Configuration Register SFR_EBICFG Read-write – 0x44 Reserved – – – 0x48 Reserved – – – 0x4C–0x50 Reserved – – – 0x54–0x3FFC Reserved – – – – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 104 16.3.1 OHCI Interrupt Configuration Register Name: SFR_OHCIICR Address: 0xF0038010 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 UDPPUDIS – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – APPSTART ARIE – RES2 RES1 RES0 • RESx: USB PORTx RESET 0: Resets USB PORT. 1: Usable USB PORT. • ARIE: OHCI Asynchronous Resume Interrupt Enable 0: Interrupt disabled. 1: Interrupt enabled. • APPSTART: Reserved 0: Must write 0. • UDPPUDIS: USB DEVICE PULL-UP DISABLE 0: USB device Pull-up connection is enabled. 1: USB device Pull-up connection is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 105 16.3.2 OHCI Interrupt Status Register Name: SFR_OHCIISR Address: 0xF0038014 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – RIS2 RIS1 RIS0 • RISx: OHCI Resume Interrupt Status Port x 0: OHCI Port resume not detected. 1: OHCI Port resume detected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 106 16.3.3 APB Bridge Configuration Register Name: SFR_BRIDGE Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – AXI2AHBSEL 7 6 5 4 3 2 1 0 – – – – – – – APBTURBO • APBTURBO: AHB to APB Bridge Mode 0: AHB transaction optimization disabled. 1: AHB transaction optimization enabled. • AXI2AHBSEL: AXI to AHB Bridge for DDR Controller Selection 0 (SINGLE): Uses single port bridge. 1 (DUAL): Uses dual port bridge. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 107 16.3.4 Security Configuration Register Name: SFR_SECURE Address: 0xF0038028 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – FUSE 7 6 5 4 3 2 1 0 – – – – – – – ROM • ROM: Disable Access to ROM Code This bit is writable once only. When the ROM is secured, only reset signal can clear this bit. 0: ROM is enabled. 1: ROM is disabled. • FUSE: Disable Access to Fuse Controller This bit is writable once only. When the Fuse Controller is secured, only reset signal can clear this bit. 0: Fuse Controller is enabled. 1: Fuse Controller is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 108 16.3.5 UTMI Clock Trimming Register Name: SFR_UTMICKTRIM Address: 0xF0038030 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 1 7 6 5 4 3 2 – – – – – – 0 FREQ • FREQ: UTMI Reference Clock Frequency Value Name Description 0 12 12 MHz reference clock 1 16 16 MHz reference clock 2 24 24 MHz reference clock 3 48 48 MHz reference clock SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 109 16.3.6 EBI Configuration Register Name: SFR_EBICFG Address: 0xF0038040 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – BMS 15 14 13 12 11 10 9 – – – SCH1 7 6 5 4 – – – SCH0 PULL1 3 2 PULL0 8 DRIVE1 1 0 DRIVE0 This register controls EBI pins which are not multiplexed with PIO controller lines. DRIVE0, PULL0, SCH0 control EBI Data pins when applicable. DRIVE1, PULL1, SCH1 control other EBI pins when applicable. • DRIVEx: EBI Pins Drive Level Drive level should be programmed depending on target frequency and board characteristics. Refer to pad characteristics to set correct drive level. Value Name Description 0 LOW Low drive level 1 RESERVED Low drive level 2 MEDIUM Medium drive level 3 HIGH High drive level • PULLx: EBI Pins Pull Value Value Name Description 0 UP Pull-up 1 NONE No Pull 2 Reserved No Change (forbidden write value) 3 DOWN Pull-down • SCHx: EBI Pins Schmitt Trigger 0: Schmitt Trigger off. 1: Schmitt Trigger on. • BMS: BMS Sampled Value (Read Only) This bit examines whether boot is on EBI or ROM. 0 (ROM): Boot on ROM. 1 (EBI): Boot on EBI. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 110 17. Advanced Interrupt Controller (AIC) 17.1 Description The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to hundred and twenty-eight interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or high-level or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. 17.2 Embedded Characteristics  Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM® Processor  128 Individually Maskable and Vectored Interrupt Sources     Source 0 is Reserved for the Fast Interrupt Input (FIQ)  Source 1 is Reserved for System Peripheral Interrupts  Source 2 to Source 127, Control up to 126 Embedded Peripheral Interrupts or External Interrupts  Programmable Edge-triggered or Level-sensitive Internal Sources  Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources 8-level Priority Controller  Drives the Normal Interrupt of the Processor  Handles Priority of the Interrupt Sources 1 to 127  Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt Vectoring  Optimizes Interrupt Service Routine Branch and Execution  One 32-bit Vector Register for all Interrupt Sources  Interrupt Vector Register Reads the Corresponding Current Interrupt Vector Protect Mode   Easy Debugging by Preventing Automatic Operations when Protect Models are Enabled Fast Forcing  Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the Processor  General Interrupt Mask  Write Protected Registers  Provides Processor Synchronization on Events Without Triggering an Interrupt SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 111 17.3 Block Diagram Figure 17-1. Block Diagram FIQ AIC ARM Processor IRQ0-IRQn Up to 128 Sources Embedded PeripheralEE Embedded nFIQ nIRQ Peripheral Embedded Peripheral APB 17.4 Application Block Diagram Figure 17-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 17.5 AIC Detailed Block Diagram Figure 17-3. AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller Fast Interrupt Controller External Source Input Stage ARM Processor nFIQ nIRQ IRQ0-IRQn Embedded Peripherals Interrupt Priority Controller Fast Forcing PIOIRQ Internal Source Input Stage Processor Clock Power Management Controller User Interface Wake Up APB SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 112 17.6 I/O Line Description Table 17-1. I/O Line Description Pin Name Pin Description Type FIQ Fast Interrupt Input IRQ0 - IRQn Interrupt 0 - Interrupt n Input 17.7 Product Dependencies 17.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. Table 17-2. I/O Lines Instance Signal I/O Line Peripheral AIC FIQ PC31 A AIC IRQ PE31 A 17.7.2 Power Management The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event. 17.7.3 Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature a FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 127 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 127. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID127. 17.8 Functional Description 17.8.1 Interrupt Source Control 17.8.1.1 Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the AIC_SMR (Source Mode Register) selects the interrupt condition of the interrupt source selected by the INTSEL field of the ”AIC Source Select Register”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 113 Note: Configuration registers such as AIC_SMR, AIC_SSR, return the values corresponding to the interrupt source selected by INTSEL. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes. 17.8.1.2 Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; “AIC Interrupt Enable Command Register” on page 139 and “AIC Interrupt Disable Command Register” on page 140. The interrupt mask of the selected interrupt source can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts. 17.8.1.3 Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in levelsensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization” circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See “Priority Controller” on page 117.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, see Section 17.8.4.5 ”Fast Forcing”). The automatic clear of the interrupt source 0 is performed when AIC_FVR is read. 17.8.1.4 Interrupt Status AIC_IPR registers represent the state of the interrupt lines, whether they are masked or not. The AIC_IMR register permits to define the mask of the interrupt lines. The AIC_ISR register reads the number of the current interrupt (see “Priority Controller” on page 117) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. 17.8.1.5 Internal Interrupt Source Input Stage Figure 17-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear AIC_ISCR FF AIC_ICCR AIC_IDCR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 114 17.8.1.6 External Interrupt Source Input Stage Figure 17-5. External Interrupt Source Input Stage High/Low AIC_SMRi SRCTYPE Level/ Edge AIC_IPR AIC_IMR Source i Fast Interrupt Controller or Priority Controller AIC_IECR Pos./Neg. Edge Detector Set AIC_ISCR FF Clear AIC_IDCR AIC_ICCR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 115 17.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including:  The time the software masks the interrupts.  Occurrence, either at the processor level or at the AIC level.  The execution time of the instruction in progress when the interrupt occurs.  The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 17.8.2.1 External Interrupt Edge Triggered Source Figure 17-6. External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles 17.8.2.2 External Interrupt Level Sensitive Source Figure 17-7. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 116 17.8.2.3 Internal Interrupt Edge Triggered Source Figure 17-8. Internal Interrupt Edge Triggered Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles 17.8.2.4 Internal Interrupt Level Sensitive Source Figure 17-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 17.8.3 Normal Interrupt 17.8.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 127 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 117 indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 17.8.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is reasserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 17.8.3.3 Interrupt Vectoring The interrupt handler address corresponding to the interrupt source selected by the INTSEL field can be stored in the registers AIC_SVR (Source Vector Register). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining the AIC_SVR of the interrupt sources to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 17.8.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits. It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 118 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects:  Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt.  De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ.  Automatically clears the interrupt, if it has been programmed to be edge-triggered.  Pushes the current level and the current interrupt number on to the stack.  Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). 17.8.4 Fast Interrupt 17.8.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 17.8.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR and INTSEL = 0, the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt when INTSEL = 0. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 119 17.8.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored through the AIC_SVR (Source Vector Register). The value written into this register when INTSEL = 0 is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 17.8.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: 3. LDR PC, [PC, # -&F20] The user does not need nested fast interrupts. When nFIQ is asserted, if the bit “F” of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor.The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 4. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 5. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. 17.8.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 120 Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR). The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edgetriggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. Figure 17-10.Fast Forcing Source 0 _ FIQ AIC_IPR Input Stage Automatic Clear AIC_IMR nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 127. AIC_FFSR Source n AIC_IPR Input Stage Priority Manager Automatic Clear nIRQ AIC_IMR Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. 17.8.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences:  If an enabled interrupt with a higher priority than the current one is pending, it is stacked.  If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 121 This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 17.8.6 Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when:  An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time.  An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.)  An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 17.8.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution. 17.8.8 Write Protected Registers To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by setting the WPEN bit in the ”AIC Write Protect Mode Register” (AIC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the ”AIC Write Protect Status Register”(AIC_WPSR) is set and the WPVSRC field indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the ”AIC Write Protect Status Register”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 122 List of the write-protected registers:  ”AIC Source Mode Register”  ”AIC Source Vector Register”  ”AIC Spurious Interrupt Vector Register”  ”AIC Debug Control Register” SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 123 17.9 Advanced Interrupt Controller (AIC) User Interface Table 17-3. Register Mapping Offset Register Name Access Reset 0x00 Source Select Register AIC_SSR Read-write 0x0 0x04 Source Mode Register AIC_SMR Read-write 0x0 0x08 Source Vector Register AIC_SVR Read-write 0x0 0x0C Reserved – – – 0x10 Interrupt Vector Register AIC_IVR Read-only 0x0 0x14 FIQ Interrupt Vector Register AIC_FVR Read-only 0x0 0x18 Interrupt Status Register AIC_ISR Read-only 0x0 0x1C Reserved – – – (2) AIC_IPR0 Read-only 0x0(1) 0x24 (2) Interrupt Pending Register 1 AIC_IPR1 Read-only 0x0(1) 0x28 Interrupt Pending Register 2(2) AIC_IPR2 Read-only 0x0(1) 0x2C Interrupt Pending Register 3(2) AIC_IPR3 Read-only 0x0(1) 0x30 Interrupt Mask Register AIC_IMR Read-only 0x0 0x34 Core Interrupt Status Register AIC_CISR Read-only 0x0 0x38 End of Interrupt Command Register AIC_EOICR Write-only – 0x3C Spurious Interrupt Vector Register AIC_SPU Read-write 0x0 0x40 Interrupt Enable Command Register AIC_IECR Write-only – 0x44 Interrupt Disable Command Register AIC_IDCR Write-only – 0x48 Interrupt Clear Command Register AIC_ICCR Write-only – 0x4C Interrupt Set Command Register AIC_ISCR Write-only – 0x20 Interrupt Pending Register 0 0x50 Fast Forcing Enable Register AIC_FFER Write-only – 0x54 Fast Forcing Disable Register AIC_FFDR Write-only – 0x58 Fast Forcing Status Register AIC_FFSR Read-only 0x0 0x5C Reserved – – – 0x6C Debug Control Register AIC_DCR Read-write 0x0 0xE4 Write Protect Mode Register AIC_WPMR Read-write 0x0 0xE8 Write Protect Status Register AIC_WPSR Read-only 0x0 0xEC - 0xFC Reserved Notes: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID127 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 124 17.9.1 AIC Source Select Register Name: AIC_SSR Address: 0xFFFFF000 Access: Read-write Reset: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 4 3 INTSEL 2 1 0 • INTSEL: Interrupt Line Selection 0-127 = Selects the interrupt line to handle. See Section 17.8.1.1 ”Interrupt Source Mode”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 125 17.9.2 AIC Source Mode Register Name: AIC_SMR Address: 0xFFFFF004 Access: Read-write Reset: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 4 – 3 – 2 1 PRIOR 0 SRCTYPE • PRIOR: Priority Level Programs the priority level of the source selected by INTSEL in except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ. • SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt source selected by INTSEL. Value Name Description 0x0 INT_LEVEL_SENSITIVE 0x1 INT_EDGE_TRIGGERED 0x2 EXT_HIGH_LEVEL 0x3 EXT_POSITIVE_EDGE Value High level Sensitive for internal source Low level Sensitive for external source Positive edge triggered for internal source Negative edge triggered for external source High level Sensitive for internal source High level Sensitive for external source Positive edge triggered for internal source Positive edge triggered for external source Internal Interrupt External Interrupt 0 0 High level sensitive Low level sensitive 0 1 Positive edge triggered Negative edge triggered 1 0 High level sensitive High level sensitive 1 1 Positive edge triggered Positive edge triggered SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 126 17.9.3 AIC Source Vector Register Name: AIC_SVR Address: 0xFFFFF008 Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in this register the address of the corresponding handler for the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 127 17.9.4 AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF010 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 128 17.9.5 AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF014 Access: Read-only Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register when INTSEL = 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 129 17.9.6 AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF018 Access: Read-only Reset: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 4 3 IRQID 2 1 0 • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 130 17.9.7 AIC Interrupt Pending Register 0 Name: AIC_IPR0 Address: 0xFFFFF020 Access: Read-only Reset: 0x0 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 SYS 0 FIQ • FIQ, SYS, PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 131 17.9.8 AIC Interrupt Pending Register 1 Name: AIC_IPR1 Address: 0xFFFFF024 Access: Read-only Reset: 0x0 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 • PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 132 17.9.9 AIC Interrupt Pending Register 2 Name: AIC_IPR2 Address: 0xFFFFF028 Access: Read-only Reset: 0x0 31 PID95 30 PID94 29 PID93 28 PID92 27 PID91 26 PID90 25 PID89 24 PID88 23 PID87 22 PID86 21 PID85 20 PID84 19 PID83 18 PID82 17 PID81 16 PID80 15 PID79 14 PID78 13 PID77 12 PID76 11 PID75 10 PID74 9 PID73 8 PID72 7 PID71 6 PID70 5 PID69 4 PID68 3 PID67 2 PID66 1 PID65 0 PID64 • PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 133 17.9.10 AIC Interrupt Pending Register 3 Name: AIC_IPR3 Address: 0xFFFFF02C Access: Read-only Reset: 0x0 31 PID127 30 PID126 29 PID125 28 PID124 27 PID123 26 PID122 25 PID121 24 PID120 23 PID119 22 PID118 21 PID117 20 PID116 19 PID115 18 PID114 17 PID113 16 PID112 15 PID111 14 PID110 13 PID109 12 PID108 11 PID107 10 PID106 9 PID105 8 PID104 7 PID103 6 PID102 5 PID101 4 PID100 3 PID99 2 PID98 1 PID97 0 PID96 • PIDx: Interrupt Pending 0 = The corresponding interrupt is not pending. 1 = The corresponding interrupt is pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 134 17.9.11 AIC Interrupt Mask Register Name: AIC_IMR Address: 0xFFFFF030 Access: Read-only Reset: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INTM • INTM: Interrupt Mask 0 = The interrupt source selected by INTSEL is disabled. 1 = The interrupt source selected by INTSEL is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 135 17.9.12 AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF034 Access: Read-only Reset: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 NIRQ 0 NFIQ • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 136 17.9.13 AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF038 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 ENDIT • ENDIT: Interrupt Processing Complete Command The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 137 17.9.14 AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF03C Access: Read-write Reset: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR • SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 138 17.9.15 AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF040 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INTEN • INTEN: Interrupt Enable 0 = No effect. 1 = Enables the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 139 17.9.16 AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF044 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INTD • INTD: Interrupt Disable 0 = No effect. 1 = Disables the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 140 17.9.17 AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF048 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INTCLR • INTCLR: Interrupt Clear Clears one the following depending on the setting of the INTSEL bit FIQ, SYS, PID2-PID127 0 = No effect. 1 = Clears the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 141 17.9.18 AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF04C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 INTSET • INTSET: Interrupt Set 0 = No effect. 1 = Sets the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 142 17.9.19 AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF050 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FFEN • FFEN: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 143 17.9.20 AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF054 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FFDIS • FFDIS: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 144 17.9.21 AIC Fast Forcing Status Register Name: AIC_FFSR Address: 0xFFFFF058 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FFS • FFS: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the interrupt source selected by INTSEL. 1 = The Fast Forcing feature is enabled on the interrupt source selected by INTSEL. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 145 17.9.22 AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF06C Access: Read-write Reset: 0x0 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 GMSK 0 PROT • PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 146 17.9.23 AIC Write Protect Mode Register Name: AIC_WPMR Address: 0xFFFFF0E4 Access: Read-write Reset: See Table 17-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414943 (“AIC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414943 (“AIC” in ASCII). Protects the registers: • ”AIC Source Mode Register” • ”AIC Source Vector Register” • ”AIC Spurious Interrupt Vector Register” • ”AIC Debug Control Register” • WPKEY: Write Protect KEY Value 0x414943 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 147 17.9.24 AIC Write Protect Status Register Name: AIC_WPSR Address: 0xFFFFF0E8 Access: Read-only Reset: See Table 17-3 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the AIC_WPSR register. 1 = A Write Protect Violation has occurred since the last read of the AIC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading AIC_WPSR automatically clears all fields. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 148 18. Watchdog Timer (WDT) 18.1 Description The Watchdog Timer (WDT) can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 18.2 Embedded Characteristics  12-bit key-protected programmable counter  Watchdog Clock is independent from Processor Clock  Provides reset or interrupt signals to the system  Counter may be stopped while the processor is in debug state or in idle mode SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 149 18.3 Block Diagram Figure 18-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR reload WDD Current Value 1/128 SLCK = EXTERNAL RESET LENGTH 19.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:  PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.  PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.)  EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the reset controller reports the software status in the field RSTTYP of the RSTC_SR. Other software resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the RSTC_SR. It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 163 Figure 19-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 to 2 cycles Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 19.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:  If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.  If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 164 Figure 19-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 19.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order:  Backup Reset  Wake-up Reset  User Reset  Watchdog Reset  Software Reset Particular cases are listed below:    When in User Reset:  A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.  A software reset is impossible, since the processor reset is being activated. When in Software Reset:  A watchdog event has priority over the current state.  The NRST has no effect. When in Watchdog Reset:  The processor reset is active and so a Software Reset cannot be programmed.  A User Reset cannot be entered. 19.4.6 Reset Controller Status Register The Reset Controller Status Register (RSTC_SR) provides several status fields:  RSTTYP field: This field gives the type of the last reset, as explained in previous sections.  SRCMP bit: This bit indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.  NRSTL bit: This bit gives the level of the NRST pin sampled on each MCK rising edge. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 165  URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 19-9). Reading the RSTC_SR resets the URSTS bit. Figure 19-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 166 19.5 Reset Controller (RSTC) User Interface Table 19-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: Access Reset Back-up Reset RSTC_CR Write-only - - Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read-write - 0x0000_0000 1. The reset value of RSTC_SR either reports a general reset or a wake-up reset depending on last rising power supply. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 167 19.5.1 Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFE00 Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect 1: If KEY is correct, resets the processor • PERRST: Peripheral Reset 0: No effect 1: If KEY is correct, resets the peripherals • EXTRST: External Reset 0: No effect 1: If KEY is correct, asserts the NRST pin and resets the processor and the peripherals • KEY: Write Access Password Value Name 0xA5 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 168 19.5.2 Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFE04 Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. Value Name Description 0 GENERAL_RST Both VDDCORE and VDDBU rising 1 WKUP_RST VDDCORE rising 2 WDT_RST Watchdog fault occurred 3 SOFT_RST Processor reset required by the software 4 USER_RST NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0: No software command is being performed by the reset controller. The reset controller is ready for a software command. 1: A software reset command is being performed by the reset controller. The reset controller is busy. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 169 19.5.3 Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFE08 Access Type: Read-write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 – KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 – 3 – ERSTL 2 – • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows the assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Write Access Password Value Name 0xA5 PASSWD Description Writing any other value in this field aborts the write operation. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 170 20. Shutdown Controller (SHDWC) 20.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 20.2 Embedded Characteristics  20.3 Shutdown and Wake-up Logic  Software Assertion of the SHDW Output Pin  Programmable De-assertion from the WKUP Input Pins Block Diagram Figure 20-1. Shutdown Controller Block Diagram SLCK Shutdown Controller SHDW_MR read SHDW_SR CPTWK0 reset WAKEUP0 SHDW_SR WKMODE0 set WKUP0 read SHDW_SR Wake-up reset RTCWKEN SHDW_MR RTC Alarm RTCWK SHDW_SR set SHDW_CR SHDW 20.4 Shutdown Output Controller SHDN Shutdown I/O Lines Description Table 20-1. I/O Lines Description Name Description Type WKUP0 Wake-up 0 input Input SHDN Shutdown output Output SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 171 20.5 Product Dependencies 20.5.1 Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller. 20.6 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any pushbuttons or signal that wake up the system. The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is passwordprotected and so the value written should contain the correct key for the command to be taken into account. As a result, the system should be powered down. A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR). The transition detector can be programmed to detect either a positive or negative transition or any level change on WKUP0. The detection can also be disabled. Programming is performed by defining WKMODE0. Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR register. If the programmed level change is detected on a pin, a counter starts. When the counter reaches the value programmed in the corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter reaches the corresponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register (SHDW_SR) reports the detection of the programmed events on WKUP0 with a reset after the read of SHDW_SR. The Shutdown Controller can be programmed so as to activate the wake-up using the RTC alarm (the detection of the rising edge of the RTC alarm is synchronized with SLCK). This is done by writing the SHDW_MR register using the RTCWKEN field. When enabled, the detection of RTC alarm is reported in the RTCWK bit of the SHDW_SR Status register. They are reset after the read of SHDW_SR. When using the RTC alarm to wake up the system, the user must ensure that RTC alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flags may be detected and the wake-up will fail. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 172 20.7 Shutdown Controller (SHDWC) User Interface Table 20-2. Register Mapping Offset Register Name Access Reset 0x00 Shutdown Control Register SHDW_CR Write-only – 0x04 Shutdown Mode Register SHDW_MR Read-write 0x0000_0003 0x08 Shutdown Status Register SHDW_SR Read-only 0x0000_0000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 173 20.7.1 Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFE10 Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW • SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. • KEY: Password. Value Name Description 0xA5 PASSWD Writing any other value in this field aborts the write operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 174 20.7.2 Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFE14 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWKEN 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 – 2 – 1 0 CPTWK0 WKMODE0 • WKMODE0: Wake-up Mode 0 Value Name Description 0 NO_DETECTION No detection is performed on the wake-up input 1 RISING_EDGE Low to high transition triggers the detection process 2 FALLING_EDGE High to low level transition triggers the detection process 3 ANY_EDGE Any edge on the wake-up input triggers the detection process • CPTWK0: Debounce Counter on Wake-up 0 Defines the minimum duration of the WKUP1 pin after the occurrence of the selected triggering edge (WKMODE0). The SHDN pin is released if the WKUP0 holds the selected level for (CPTWK * 16 + 1) consecutive Slow Clock cycles after the occurrence of the selected triggering edge on WKUP0. • RTCWKEN: Real-time Clock Wake-up Enable 0 = The RTC Alarm signal has no effect on the Shutdown Controller. 1 = The RTC Alarm signal forces the de-assertion of the SHDN pin. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 175 20.7.3 Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFE18 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RTCWK 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 • WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on WKUP0 input since the last read of SHDW_SR. 1 = At least one wake-up event occurred on WKUP0 input since the last read of SHDW_SR. • RTCWK: Real-time Clock Wake-up 0 = No wake-up alarm from the RTC occurred since the last read of SHDW_SR. 1 = At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 176 21. General-Purpose Backup Registers (GPBR) 21.1 Description The System Controller embeds 4 General-purpose Backup registers. 21.2 Embedded Characteristics  4 32-bit General Purpose Backup Registers SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 177 21.3 General Purpose Backup Registers (GPBR) User Interface Table 21-1. Register Mapping Offset 0x0 ... 0x6C Register Name General Purpose Backup Register 0 SYS_GPBR0 ... ... General Purpose Backup Register 3 SYS_GPBR3 Access Reset Read-write – ... ... Read-write – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 178 21.3.1 General Purpose Backup Register x Name: SYS_GPBRx Address: 0xFFFFFE60 Access: Read-write 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 GPBR_VALUE 23 22 21 20 19 GPBR_VALUE 15 14 13 12 11 GPBR_VALUE 7 6 5 4 3 GPBR_VALUE • GPBR_VALUE: Value of GPBR x SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 179 22. Periodic Interval Timer (PIT) 22.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 22.2 Embedded Characteristics  20-bit Programmable Counter plus 12-bit Interval Counter  Reset-on-read Feature  Both Counters Work on Master Clock/16 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 180 22.3 Block Diagram Figure 22-1. Periodic Interval Timer PIT_MR PIV = PIT_MR PITIEN set 0 PIT_SR PITS pit_irq reset 0 MCK Prescaler 0 0 1 12-bit Adder 1 read PIT_PIVR 20-bit Counter MCK/16 CPIV PIT_PIVR CPIV PIT_PIIR PICNT PICNT SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 181 22.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 22-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 22-2. Enabling/Disabling PIT with PITEN APB cycle APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN CPIV PICNT 0 1 PIV - 1 0 PIV 1 0 1 0 PITS (PIT_SR) APB Interface read PIT_PIVR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 182 22.5 Periodic Interval Timer (PIT) User Interface Table 22-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read-write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 183 22.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFE30 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 184 22.5.2 Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFE34 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 185 22.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFE38 Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 186 22.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFE3C Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 187 23. Real-time Clock (RTC) 23.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. 23.2 Embedded Characteristics  Ultra Low Power Consumption  Full Asynchronous Design  Gregorian Calendar up to 2099  Programmable Periodic Interrupt  Safety/security features:  Valid Time and Date Programmation Check SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 188 23.3 Block Diagram Figure 23-1. RTC Block Diagram Slow Clock: SLCK 32768 Divider Date Entry Control Interrupt Control Bus Interface Bus Interface 23.4 Time RTC Interrup Product Dependencies 23.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 23.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other module interrupts. Only one System Controller interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the interrupt controller to be programmed first. When a System Controller interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading each status register of the System Controller peripherals successively. Table 23-1. Peripheral IDs 23.5 Instance ID RTC 1 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099. 23.5.1 Reference Clock The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal. During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 189 23.5.2 Timing The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 23.5.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition:  If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second.  If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC, MIN, HOUR fields. Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_TIMALR or RTC_CALALR registers. The first access clears the enable corresponding to the field to change (SECEN,MINEN,HOUREn,DATEEN,MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is required to re-enable the field by writing 1 in SECEN,MINEN,HOUREn,DATEEN,MTHEN fields. 23.5.4 Error Checking when Programming Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check if it is in range 19 - 20 ) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8. Second (check BCD and range 00 - 59) Note: If the 12-hour mode is selected by means of the RTC_MR register, a 12-hour value can be programmed and the returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIMR register) to determine the range to be checked. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 190 23.5.5 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate Time and Calendar register. Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control When entering programming mode of the calendar fields, the time fields remain enabled. When entering the programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be updated before entering programming mode. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 191 Figure 23-2. Update Sequence Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR Polling or IRQ (if enabled) ACKUPD =1? No Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in RTC_TIMR/RTC_CALR Clear UPDTIM and/or UPDCAL bit in RTC_CR End SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 192 23.6 Real-time Clock (RTC) User Interface Table 23-2. Register Mapping Offset Register Name Access Reset 0x00 Control Register RTC_CR Read-write 0x0 0x04 Mode Register RTC_MR Read-write 0x0 0x08 Time Register RTC_TIMR Read-write 0x0 0x0C Calendar Register RTC_CALR Read-write 0x01810720 0x10 Time Alarm Register RTC_TIMALR Read-write 0x0 0x14 Calendar Alarm Register RTC_CALALR Read-write 0x01010000 0x18 Status Register RTC_SR Read-only 0x0 0x1C Status Clear Command Register RTC_SCCR Write-only – 0x20 Interrupt Enable Register RTC_IER Write-only – 0x24 Interrupt Disable Register RTC_IDR Write-only – 0x28 Interrupt Mask Register RTC_IMR Read-only 0x0 0x2C Valid Entry Register RTC_VER Read-only 0x0 0x30–0xC4 Reserved Register – – – 0xC8–0xF8 Reserved Register – – – 0xFC Reserved Register – – – Note: If an offset is not listed in the table it must be considered as reserved. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 193 23.6.1 RTC Control Register Name: RTC_CR Address: 0xFFFFFEB0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 – – – – – – 16 CALEVSEL 9 8 TIMEVSEL 7 6 5 4 3 2 1 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register. • UPDCAL: Update Request Calendar Register 0 = No effect. 1 = Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set. • TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL. Value Name Description 0 MINUTE Minute change 1 HOUR Hour change 2 MIDNIGHT Every day at midnight 3 NOON Every day at noon • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL Value Name Description 0 WEEK Week change (every Monday at time 00:00:00) 1 MONTH Month change (every 01 of each month at time 00:00:00) 2 YEAR Year change (every January 1 at time 00:00:00) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 194 23.6.2 RTC Mode Register Name: RTC_MR Address: 0xFFFFFEB4 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 195 23.6.3 RTC Time Register Name: RTC_TIMR Address: 0xFFFFFEB8 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – AMPM 15 14 10 9 8 2 1 0 HOUR 13 12 – 7 11 MIN 6 5 – 4 3 SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0 = AM. 1 = PM. All non-significant bits read zero. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 196 23.6.4 RTC Calendar Register Name: RTC_CALR Address: 0xFFFFFEBC Access: Read-write 31 30 – – 23 22 29 28 27 21 20 19 DAY 15 14 26 25 24 18 17 16 DATE MONTH 13 12 11 10 9 8 3 2 1 0 YEAR 7 6 5 – 4 CENT • CENT: Current Century The range that can be set is 19 - 20 (gregorian) (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • DAY: Current Day in Current Week The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Day in Current Month The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 197 23.6.5 RTC Time Alarm Register Name: RTC_TIMALR Address: 0xFFFFFEC0 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 21 20 19 18 17 16 10 9 8 2 1 0 23 22 HOUREN AMPM 15 14 HOUR 13 12 MINEN 7 6 5 SECEN Note: 11 MIN 4 3 SEC To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_TIMALR register. The first access clears the enable corresponding to the field to change (SECEN,MINEN,HOUREN). If the field is already cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields. • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled. • MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. • MINEN: Minute Alarm Enable 0 = The minute-matching alarm is disabled. 1 = The minute-matching alarm is enabled. • HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled. 1 = The hour-matching alarm is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 198 23.6.6 RTC Calendar Alarm Register Name: RTC_CALALR Address: 0xFFFFFEC4 Access: Read-write 31 30 DATEEN – 29 28 27 26 25 24 18 17 16 DATE 23 22 21 MTHEN – – 15 14 13 12 11 10 9 8 – – – – – – – – Note: 20 19 MONTH 7 6 5 4 3 2 1 0 – – – – – – – – To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_CALALR register. The first access clears the enable corresponding to the field to change (DATEEN,MTHEN). If the field is already cleared, this access is not required. The second access performs the change of the value (DATE,MONTH). The third access is required to re-enable the field by writing 1 in DATEEN, MTHEN fields. • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled. 1 = The date-matching alarm is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 199 23.6.7 RTC Status Register Name: RTC_SR Address: 0xFFFFFEC8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 (FREERUN) = Time and calendar registers cannot be updated. 1 (UPDATE) = Time and calendar registers can be updated. • ALARM: Alarm Flag 0 (NO_ALARMEVENT) = No alarm matching condition occurred. 1 (ALARMEVENT) = An alarm matching condition has occurred. • SEC: Second Event 0 (NO_SECEVENT) = No second event has occurred since the last clear. 1 (SECEVENT) = At least one second event has occurred since the last clear. • TIMEV: Time Event 0 (NO_TIMEVENT) = No time event has occurred since the last clear. 1 (TIMEVENT) = At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). • CALEV: Calendar Event 0 (NO_CALEVENT) = No calendar event has occurred since the last clear. 1 (CALEVENT) = At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 200 23.6.8 RTC Status Clear Command Register Name: RTC_SCCR Address: 0xFFFFFECC Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • ACKCLR: Acknowledge Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • ALRCLR: Alarm Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • SECCLR: Second Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • TIMCLR: Time Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). • CALCLR: Calendar Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 201 23.6.9 RTC Interrupt Enable Register Name: RTC_IER Address: 0xFFFFFED0 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect. 1 = The alarm interrupt is enabled. • SECEN: Second Event Interrupt Enable 0 = No effect. 1 = The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable 0 = No effect. 1 = The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable 0 = No effect. 1 = The selected calendar event interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 202 23.6.10 RTC Interrupt Disable Register Name: RTC_IDR Address: 0xFFFFFED4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect. 1 = The alarm interrupt is disabled. • SECDIS: Second Event Interrupt Disable 0 = No effect. 1 = The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable 0 = No effect. 1 = The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable 0 = No effect. 1 = The selected calendar event interrupt is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 203 23.6.11 RTC Interrupt Mask Register Name: RTC_IMR Address: 0xFFFFFED8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled. • ALR: Alarm Interrupt Mask 0 = The alarm interrupt is disabled. 1 = The alarm interrupt is enabled. • SEC: Second Event Interrupt Mask 0 = The second periodic interrupt is disabled. 1 = The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled. 1 = The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled. 1 = The selected calendar event interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 204 23.6.12 RTC Valid Entry Register Name: RTC_VER Address: 0xFFFFFEDC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – NVCALALR NVTIMALR NVCAL NVTIM • NVTIM: Non-valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed. • NVCAL: Non-valid Calendar 0 = No invalid data has been detected in RTC_CALR (Calendar Register). 1 = RTC_CALR has contained invalid data since it was last programmed. • NVTIMALR: Non-valid Time Alarm 0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 = RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non-valid Calendar Alarm 0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 = RTC_CALALR has contained invalid data since it was last programmed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 205 24. Slow Clock Controller (SCKC) 24.1 Description The System Controller embeds a Slow Clock Controller. The slow clock can be generated either by an external 32768 Hz crystal oscillator or by the on-chip 32 kHz RC oscillator. The 32768 Hz crystal oscillator can be bypassed by setting the OSC32BYP bit to accept an external slow clock on XIN32. The internal 32 kHz RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1, respectively, the RCEN and OSC32EN bits in the System Controller user interface. The OSCSEL command selects the slow clock source. 24.2 Embedded Characteristics  32 kHz RC Oscillator or 32768 Hz Crystal Oscillator Selector  VDDBU Powered SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 206 24.3 Block Diagram Figure 24-1. Block Diagram RCEN On Chip RC OSC Slow Clock SLCK XIN32 XOUT32 Slow Clock Oscillator OSCSEL OSC32EN OSC32BYP RCEN, OSC32EN, OSCSEL and OSC32BYP bits are located in the Slow Clock Controller Configuration Register (SCKC_CR) located at the address 0xFFFFFE50 in the backed-up part of the System Controller and, thus, they are preserved while VDDBU is present. After the VDDBU power-on reset, the default configuration is RCEN = 1, OSC32EN = 0 and OSCSEL = 0, allowing the system to start on the internal 32 kHz RC oscillator. The programmer controls the slow clock switching by software and so must take precautions during the switching phase. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 207 24.3.1 Switch from Internal 32 kHz RC Oscillator to 32768 Hz Crystal Oscillator To switch from the internal 32 kHz RC oscillator to the 32768 Hz crystal oscillator, the programmer must execute the following sequence:  Switch the master clock to a source different from slow clock (PLL or Main Oscillator) through the Power Management Controller.  Enable the 32768 Hz oscillator by writing a 1 to the OSC32EN bit.  Wait 32768 Hz startup time for clock stabilization (software loop).  Switch from internal 32 kHz RC oscillator to 32768 Hz oscillator by writing a 1 to the OSCSEL bit.  Wait 5 slow clock cycles for internal resynchronization.  Disable the 32 kHz RC oscillator by writing a 0 to the RCEN bit. 24.3.2 Bypass the 32768 Hz Oscillator The following steps must be added to bypass the 32768 Hz oscillator:  An external clock must be connected on XIN32.  Enable the bypass path by writing a 1 to the OSC32BYP bit.  Disable the 32768 Hz oscillator by writing a 0 to the OSC32EN bit. 24.3.3 Switch from 32768 Hz Crystal Oscillator to Internal 32 kHz RC Oscillator The same procedure must be followed to switch from the 32768 Hz crystal oscillator to the internal 32 kHz RC oscillator:  Switch the master clock to a source different from slow clock (PLL or Main Oscillator).  Enable the internal 32 kHz RC oscillator for low power by writing a 1 to the RCEN bit.  Wait internal 32 kHz RC startup time for clock stabilization (software loop).  Switch from 32768 Hz oscillator to internal RC by writing a 0 to the OSCSEL bit.  Wait 5 slow clock cycles for internal resynchronization.  Disable the 32768 Hz oscillator by writing a 0 to the OSC32EN bit. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 208 24.4 Slow Clock Controller (SCKC) User Interface Table 24-1. Register Mapping Offset 0x0 Register Name Slow Clock Controller Configuration Register SCKC_CR Access Reset Read/Write 0x0000_0001 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 209 24.4.1 Slow Clock Controller Configuration Register Name: SCKC_CR Address: 0xFFFFFE50 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCSEL 2 OSC32BYP 1 OSC32EN 0 RCEN • RCEN: Internal 32 kHz RC Oscillator 0: 32 kHz RC oscillator is disabled. 1: 32 kHz RC oscillator is enabled. • OSC32EN: 32768 Hz Oscillator 0: 32768 Hz oscillator is disabled. 1: 32768 Hz oscillator is enabled. • OSC32BYP: 32768Hz Oscillator Bypass 0: 32768 Hz oscillator is not bypassed. 1: 32768 Hz oscillator is bypassed, accept an external slow clock on XIN32. • OSCSEL: Slow Clock Selector 0 (RC): Slow clock is internal 32 kHz RC oscillator. 1 (XTAL): Slow clock is 32768 Hz oscillator. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 210 25. Fuse Controller (FUSE) 25.1 Description The Fuse Controller (FUSE) supports software fuse programming through a 32-bit register. Only fuses set to level ‘1’ are programmed. The fast (main) RC oscillator must be enabled at startup to access the fuse matrix. It reads the fuse states on startup and stores them into 32-bit registers. The first 8 Fuse Status registers (FUSE_SRx) can be masked and will read as a value of ‘0’ regardless of the fuse state when masked. 25.2 Embedded Characteristics  Software Fuse Programming  User Write Access for Fuse  Part of Fuse can be Masked After Read  256 FUSE bits:  192 bits are dedicated to Users  3 bits are dedicated to Special Functions  The Fuse Controller can be hidden thanks to a SFR write-once bit. Please refer to the “Special Function Registers (SFR)” section of the SAMA5D3 series datasheet for details. 25.2.1 FUSE Bit Mapping To avoid any malfunctioning, the user must not write the “DO NOT USE (DNU)” FUSE bits. Table 25-1. FUSE Bit Mapping 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 DO NOT USE (DNU) 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 USER_DATA 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 DO NOT USE (DNU) B J W 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 USER_DATA 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 USER_DATA 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 45 44 43 42 41 40 39 38 37 36 35 34 33 32 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USER_DATA 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 USER_DATA 16 15 14 USER_DATA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 211 25.2.2 Special Functions The user is allowed to set special bits as described in the following table. Table 25-2. Special Bits Bit Number Bit Name Function 162 B BMS_SAMPLING_DISABLED - BMS sampling is disabled if set 161 J JTAG_DISABLED - JTAG is disabled if set 160 W FUSE_WRITE_DISABLED - FUSE bit writing is disabled if set SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 212 25.3 Block Diagram Figure 25-1. Fuse Controller Block Diagram Fuse States Fuse States Fuse Cell Fuse Controller Controls Controls SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 213 25.4 Functional Description 25.4.1 Fuse Reading The fuse states are automatically read on CORE startup and are available for reading in the 8 Fuse Status (FUSE_SRx) registers. The fuse states of bits 31 to 0 will be available at FUSE_SR0, the fuse states of bits 63 to 32 will be available at FUSE_SR1 and so on. FUSE_SRx registers can be updated manually by using the RRQ bit of the Fuse Control register (FUSE_CR). RS and WS bits of the Fuse Index register (FUSE_IR) must be at level one before issuing the read request. Figure 25-2. Fuse Read Clock FUSE_SRx outdated up to date RRQ WS RS 25.4.2 Fuse Programming All the fuses, except Atmel reserved fuses, can be written by software. To program fuses, strictly follow the order of the sequence instructions as provided below: 1. Select the word to write, using the WSEL field of the Fuse Index register (FUSE_IR). 2. Write the word to program in the Fuse Data register (FUSE_DR). 3. Check that RS and WS bits of the FUSE_IR are at level one (no read and no write pending). 4. Write the WRQ bit of the Fuse Control register (FUSE_CR) to begin the fuse programming. The KEY field must be written at the same time with a value 0xFB to make the write request valid. Writing the WRQ bit will clear the WS bit. 5. Check the WS bit of FUSE_IR. When WS has a value of ‘1’ the fuse write process is over. Only fuses to be set to level ‘1’ are written. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 214 Figure 25-3. Fuse Write Clock WSEL DATA XX 00 XX 01 Fuse[31:0] Fuse[63:32] WRQ WS RS 25.4.3 Fuse Masking It is possible to mask the first 8 FUSE_SRx registers so that they will be read at a value of ‘0’, regardless of the fuse state. To activate fuse masking on the first 8 FUSE_SRx registers, the MSK bit of the Fuse Mode register (FUSE_MR) must be written to level ‘1’. The MSK bit is write-only. Only a general reset can disable fuse masking. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 215 25.5 Fuse Controller (FUSE) User Interface Table 25-3. Register Mapping Offset Register Name Access Reset 0x00 Fuse Control Register FUSE_CR Write-only – 0x04 Fuse Mode Register FUSE_MR Write-only – 0x08 Fuse Index Register FUSE_IR Read-write 0x00000000 0x0C Fuse Data Register FUSE_DR Read-write – 0x10 Fuse Status Register 0 FUSE_SR0 Read-only 0x00000000 0x14 Fuse Status Register 1 FUSE_SR1 Read-only 0x00000000 ... ... ... FUSE_SR7 Read-only 0x00000000 ... 0x2C ... Fuse Status Register 7 0x30–0xDC Reserved – – – 0xE0–0xFC Reserved – – – Note: 1. Values in the Version Register vary with the version of the IP block implementation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 216 25.5.1 Fuse Control Register Name: FUSE_CR Address: 0xFFFFE400 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 RRQ 0 WRQ KEY 7 – 6 – 5 – 4 – • WRQ: Write Request 0: No effect. 1: Requests the word DATA to be programmed if KEY field value is 0xFB. • RRQ: Read Request 0: No effect. 1: Requests the fuses to be read and FUSE_SRx registers to be updated if KEY field value is 0xFB. • KEY: Key code Value Name 0xFB VALID Description Writing any other value in this field aborts the write operation of the WRQ and RRQ bits. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 217 25.5.2 Fuse Mode Register Name: FUSE_MR Address: 0xFFFFE404 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MSK • MSK: Mask Fuse Status Registers 0: No effect. 1: Masks the first 8 FUSE_SRx registers. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 218 25.5.3 Fuse Index Register Name: FUSE_IR Address: 0xFFFFE408 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 RS 0 WS WSEL 2 – • WS: Write Status 0: Write is pending or no write has been requested since general reset. 1: Write of fuses is done. • RS: Read Status 0: Read is pending or no read has been requested since general reset. 1: Read of fuses is done. • WSEL: Word Selection 0–15: Selects the word to write. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 219 25.5.4 Fuse Data Register Name: FUSE_DR Address: 0xFFFFE40C Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA • DATA: Data to Program Data to program. Only bits with a value of ‘1’ will be programmed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 220 25.5.5 Fuse Status Register Name: FUSE_SRx [x=0..7] Address: 0xFFFFE410 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FUSE 23 22 21 20 FUSE 15 14 13 12 FUSE 7 6 5 4 FUSE • FUSE: Fuse Status Indicates the status of corresponding fuses: 0: Unprogrammed. 1: Programmed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 221 26. Power Management Controller (PMC) 26.1 Clock Generator 26.1.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in Section 26.2.15 “Power Management Controller (PMC) User Interface”. However, the Clock Generator registers are named CKGR_. 26.1.2 Embedded Characteristics The Clock Generator is made up of:  Low-power 32768 Hz Slow Clock Oscillator with bypass mode  Low-power 32 kHz RC Oscillator  8 to 48 MHz Crystal Oscillator or a 24/48 MHz XRCGB Crystal Resonator, which can be bypassed (12 MHz, 24 MHz (preferred) or 48 MHz must be used in case of USB operations)  Fast RC Oscillator, at 12 MHz  480 MHz UTMI PLL providing a clock for the USB High Speed Device Controller  400 to 1000 MHz programmable PLL (input from 8 to 50 MHz), capable of providing the clock MCK to the processor and to the peripherals It provides the following clocks:  SLCK, the Slow Clock, which is the only permanent clock within the system  MAINCK is the output of the Main Clock Oscillator selection: either 8 to 48 MHz Crystal Oscillator or 12 MHz Fast RC Oscillator  PLLACK is the output of the Divider and 400 to 1000 programmable PLL (PLLA)  UPLLCK is the output of the 480 MHz UTMI PLL (UPLL)  SMDCK is the Software Modem Clock The Power Management Controller also provides the following operations on clocks:  Main crystal oscillator clock failure detector  Frequency counter on main clock and an on-the-fly adjustable main RC oscillator frequency SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 222 26.1.3 Block Diagram Figure 26-1. Clock Generator Block Diagram Clock Generator RCEN On Chip 32K RC OSC XIN32 XOUT32 Slow Clock SLCK Slow Clock Oscillator OSCSEL OSC32EN OSC32BYP MOSCRCEN MOSCSEL On Chip 12M RC OSC XIN XOUT 8 to 48 MHz Main Oscillator UPLL UPLLCK PLLA and Divider Status Main Clock MAINCK PLLA Clock PLLACK Control Power Management Controller 26.1.4 Main Clock Selection The main clock can be generated either by an external 8 to 48 MHz crystal, an XRCGB crystal resonator or by the onchip12 MHz Fast RC Oscillator. This allows the processor to start or restart in a few microseconds when 12 MHz Fast RC Oscillator is selected. The 8 to 48 MHz crystal oscillator can be bypassed by setting the MOSCXTBY bit to accept an external main clock on XIN. Figure 26-2. Main Clock Selection MOSCRCEN On Chip 12 MHz RC Oscillator Main Clock XIN XOUT Main Clock Oscillator MOSCSEL SMDCK MOSCXTEN MOSCXTBY SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 223 MOSCRCEN, MOSCXTEN, MOSCSEL and MOSCXTBY bits are located in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). After a VDDBU power on reset, the default configuration is MOSCRCEN = 1, MOSCXTEN = 0 and MOSCSEL = 0, the 12 MHz RC is started as Main clock. 26.1.4.1 Fast Wake-up To speed up the wake-up phase, the user can switch the system clock from 32 kHz RC (SLCK) to 12 MHz RC (Main Clock). This enables the user to perform system configuration (PLL, DDR, etc.) at 12 MHz instead of 32 kHz during the12 MHz Oscillator startup. Figure 26-3. PMC Startup 12 MHz RC External Main clock Main Supply 12 MHz RC Startup Time POR output Crystal Startup Time System starts on 32 kHz RC Wait MOSCRCS = 1 RCEN = 1 User switch on Main Clock OSC32EN = 0 to speed-up the boot OSCSEL = 0 PMC_MCKR =1 MOSCRCEN = 1 System is running at 12 MHz MOSCXTEN = 0 MOSCSEL = 0 External oscillator PMC_MCKR = 0 is started for better accuracy MOSCXTEN = 1 MOSCSEL = 0 Wait MOSCXTS = 1 User switches on external oscillator MOSCSEL = 1 Wait while MOSCSELS = 1 System is runnning on 12 MHz Crystal PLL can be used 26.1.4.2 Switch from Internal 12 MHz Fast RC Oscillator to the 8 to 48 MHz Crystal The programmer controls the main clock switching by software and must take precautions during the switching phase. To switch from internal 12 MHz Fast RC Oscillator to the 8 to 48 MHz crystal, the programmer must execute the following sequence:  Enable the 8 to 48 MHz oscillator by writing a 1 to bit MOSCXTEN.  Wait for 8 to 48 MHz oscillator status MAINRDY is 1.  Switch from internal 12 MHz RC to the 8 to 48 MHz oscillator by writing a 1 to bit MOSCSEL.  If not, the PMC writes a 0 to bit MOSCSEL.  Disable the 12 MHz RC oscillator by writing a 0 to bit MOSCRCEN. 26.1.4.3 Bypass the 8 to 48 MHz Crystal Oscillator The following step must be added to bypass the 8 to 48 MHz crystal oscillator.  An external clock must be connected on XIN.  Enable the bypass path MOSCXTBY bit set to 1.  Disable the 8 to 48 MHz oscillator by writing a 0 to bit MOSCXTEN. 26.1.4.4 Switch from the 8 to 48 MHz Crystal Oscillator to internal 12 MHz Fast RC Oscillator The same procedure must be followed to switch from a 8 to 48 MHz crystal oscillator to the internal 12 MHz Fast RC Oscillator.  Enable the internal 12 MHz RC oscillator for low power by writing a 1 to bit MOSCRCEN. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 224  Wait internal 12 MHz RC startup time for clock stabilization (software loop).  Switch from 8 to 48 MHz oscillator to the internal 12 MHz Fast RC Oscillator by writing a 0 to bit MOSCSEL.  Disable the 8 to 48 MHz oscillator by writing a 0 to bit MOSCXTEN. 26.1.5 Main Clock Figure 26-4. Main Clock Block Diagram MOSCRCEN MOSCRCF MOSCRCS On Chip 12 MHz RC Oscillator MOSCSEL MOSCSELS 1 MAINCK Main Clock MOSCXTEN 0 XIN XOUT 8 to 48 MHz Crystal Oscillator MOSCXTCNT SLCK Slow Clock 8 to 48 MHz Crystal Oscillator Counter MOSCXTS MOSCRCEN MOSCXTEN MOSCSEL Main Clock Frequency Counter MAINF MAINRDY The Main Clock has two sources:  12 MHz Fast RC Oscillator which starts very quickly and is used at startup  8 to 48 MHz Crystal Oscillator, which can be bypassed 26.1.5.1 12 MHz Fast RC Oscillator After reset, the 12 MHz Fast RC Oscillator is enabled and it is selected as the source of MCK. MCK is the default clock selected to start up the system. Please refer to the “DC Characteristics” section of the product electrical characteristics. The software can disable or enable the 12 MHz Fast RC Oscillator with the MOSCRCEN bit in the Clock Generator Main Oscillator Register (CKGR_MOR). When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is automatically cleared, indicating the Main Clock is off. Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER) can trigger an interrupt to the processor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 225 26.1.5.2 12 MHz Fast RC Oscillator Clock Frequency Adjustment It is possible for the user to adjust the main RC oscillator frequency through PMC_OCR. By default, SEL is low, so the RC oscillator is driven with fuse calibration bits which are programmed during the chip production. The user can adjust the trimming of the 12 MHz Fast RC oscillator through the PMC_OCR in order to obtain more accurate frequency (to compensate derating factors such as temperature and voltage). In order to calibrate the 12 MHz oscillator frequency, SEL must be set to 1 and a correct frequency value must be configured in CAL. It is possible to restart, at anytime, a measurement of the main frequency by means of the RCMEAS bit in Main Clock Frequency Register (CKGR_MCFR). Thus, when MAINFRDY flag reads 1, another read access on CKGR_MCFR provides an image of the frequency of the main clock on MAINF field. The software can calculate the error with an expected frequency and correct the CAL field accordingly. This may be used to compensate frequency drift due to derating factors such as temperature and/or voltage. 26.1.5.3 8 to 48 MHz Crystal Oscillator After reset, the 8 to 48 MHz Crystal Oscillator is disabled and it is not selected as the source of MAINCK. The user can select the 8 to 48 MHz crystal oscillator to be the source of MAINCK, as it provides a more accurate frequency. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCXTEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit in PMC_SR is automatically cleared, indicating the Main Clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the oscillator. When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to enable the main oscillator, the MOSCXTS bit in the PMC_SR is cleared and the counter starts counting down on the slow clock divided by 8 from the MOSCXTCNT value. Since the MOSCXTCNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor. 26.1.5.4 Main Clock Oscillator Selection The user can select either the 12 MHz Fast RC Oscillator or the Crystal Oscillator to be the source of Main Clock. The selection is made by writing the MOSCSEL bit in the CKGR_MOR. The switch of the Main Clock source is glitch free, so there is no need to run out of SLCK or PLLACK in order to change the selection. The MOSCSELS bit of the PMC_SR indicates when the switch sequence is done. Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor. 26.1.5.5 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator Both sources must be enabled during the switch operation. Only after completion can the unused oscillator be disabled. If switching to Fast Crystal Oscillator, the clock presence must first be checked according to what is described in Section 26.1.5.6 “Software Sequence to Detect the Presence of Fast Crystal” because the source may not be reliable (crystal failure or bypass on a non-existent clock). 26.1.5.6 Software Sequence to Detect the Presence of Fast Crystal The frequency meter carried on the CKGR_MCFR is operating on the selected main clock and not on the fast crystal clock nor on the fast RC Oscillator clock. Therefore, to check for the presence of the fast crystal clock, it is necessary to switch the main clock on the fast crystal clock. The following software sequence must be followed (during this sequence the Main RC oscillator must be kept enabled (MOSCRCEN = 1)): SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 226 1. MCK must select the slow clock (CSS = 0 in PMC_MCKR). 2. Wait for the MCKRDY flag in the PMC_SR to be 1. 3. The fast crystal must be enabled by programming 1 in the MOSCXTEN field in the CKGR_MOR, with the MOSCXTST field being programmed to the appropriate value (see the electrical characteristics section). 4. Wait for the MOSCXTS flag to be 1 in the PMC_SR to allow the start-up period of the fast crystal oscillator to end. 5. MOSCSEL must be programmed to 1 in the CKGR_MOR to select the fast main crystal oscillator for the main clock. 6. MOSCSEL must be read until its value equals 1. 7. The MOSCSELS status flag must be checked in the PMC_SR. At this point, two cases may occur: either MOSCSELS = 0 or MOSCSELS = 1.  MOSCSELS = 1: There is a valid crystal connected and its frequency can be determined by initiating a frequency measure by programming RCMEAS in the CKGR_MCFR.  MOSCSELS = 0:  There is no fast crystal clock (either no crystal connected or a crystal clock out of specification). A frequency measure can reinforce this status by initiating a frequency measure by programming RCMEAS in the CKGR_MCFR.  The selection of the main clock must be programmed back to the main RC oscillator by writing MOSCSEL to 0 prior to disabling the fast crystal oscillator.  The crystal oscillator can be disabled (MOSCXTEN = 0 in CKGR_MOR). 26.1.5.7 Main Clock Frequency Counter The device features a Main Clock frequency counter that provides the frequency of the Main Clock. The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock in the following cases:  When the 12 MHz Fast RC Oscillator clock is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)  When the Crystal Oscillator is selected as the source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is set)  When the Main Clock Oscillator selection is modified Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the CKGR_MCFR is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the 12 MHz Fast RC Oscillator or the Crystal Oscillator can be determined. 26.1.6 Divider and PLLA Block The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLLA minimum input frequency when programming the divider. Figure 26-5 shows the block diagram of the divider and PLLA block. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 227 Figure 26-5. Divider and PLLA Block Diagram DIVA MAINCK MULA Divider OUTA PLLA PLLACK PLLACOUNT SLCK PLLA Counter LOCKA 26.1.6.1 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIVA and MULA. The factor applied to the source signal frequency is (MULA + 1)/DIVA. When MULA is written to 0, the PLLA is disabled and its power consumption is saved. Re-enabling the PLLA can be performed by writing a value higher than 0 in the MUL field. Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in PMC_SR is automatically cleared. The values written in the PLLACOUNT field in CKGR_PLLAR are loaded in the PLLA counter. The PLLA counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLLA transient time into the PLLACOUNT field. The PLLA clock must be divided by 2 by writing the PLLADIV2 bit in the PMC_MCKR. 26.1.7 UTMI Phase Lock Loop Programming The source clock of the UTMI PLL is the Main OSC output. When the 12 MHz Fast RC Oscillator is selected as the source of the MAINCK, the 12 MHz frequency must also be selected because the UTMI PLL multiplier contains a built-in multiplier of x 40 to obtain the USB High Speed 480 MHz. A 12, 16, 24 or 48 MHz crystal is needed to use the USB. Please refer to the SFR_UTMICKTRIM register to set the value. Figure 26-6. UTMI PLL Block Diagram UPLLEN MAINCK UTMI PLL UPLLCK UPLLCOUNT SLCK UTMI PLL Counter LOCKU Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL counter. The UTMI PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At this time, the LOCKU bit is set SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 228 in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 229 26.2 Power Management Controller (PMC) 26.2.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core. 26.2.2 Embedded Characteristics The Power Management Controller provides the following clocks:  MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently.  Processor Clock (PCK), must be switched off when entering the processor in Sleep Mode.  The USB Device HS Clock (UDPCK)  The Software Modem Clock (SMDCK)  Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, HSMCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet.  Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 230 26.2.3 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which allows the processor clock to be faster than the Master Clock. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 6. The PRES field in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Figure 26-7. Master Clock Controller PMC_MCKR CSS PMC_MCKR PRES SLCK MAINCK PLLACK Master Clock Prescaler MCK UPLLCK To the Processor Clock Controller (PCK) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 231 26.2.4 Block Diagram Figure 26-8. General Clock Block Diagram PLLACK /2 PLLADIV2 1 0 USBS UHP48M USBDIV+1 USB OHCI UHP12M /4 USB EHCI PCK Processor Clock Controller UPLLCK Any Peripheral Interrupt Master Clock Controller (PMC_MCKR) MAINCK SLCK CSS Prescaler /1,/2,/3,/4,...,/64 Divider /1, /2, /3, /4 PRES MDIV MCK PMC_PCR Peripherals Clock Controller ON/OFF Divider EN DIV Periph_clk[..] Programmable Clock Controller (PMC_PCKx) SLCK MAINCK ON/OFF Prescaler /1, /2, /4,... /64 UPLLCK MCK CSS pck[..] PRES 26.2.5 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 232 The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 26.2.6 USB Device and Host Clocks The USB Device and Host High Speed ports (UDPHS and UHPHS) clocks are enabled by corresponding PIDx bits in PMC_PCER. To save power on this peripheral when they are not used, the user can set these bits in the PMC_PCDR. Corresponding PIDx bits in the PMC_PCSR give the status of these clocks. The PMC also provides the clocks UHP48M and UHP12M to the USB Host OHCI. The USB Host OHCI clocks are controlled by the UHP bit in PMC_SCER. To save power on this peripheral when they are not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the status of this clock. The USB host OHCI requires both the 12/48 MHz signal and the Master Clock. The USBDIV field in PMC_USB register is to be programmed to 9 (division by 10) for normal operations. To further reduce power consumption the user can stop UTMI PLL, in this case USB high-speed operations are not possible. Nevertheless, as the USB OHCI Input clock can be selected with USBS bit (PLLA or UTMI PLL) in PMC_USB register, OHCI full-speed operation remains possible. The user must program the USB OHCI Input Clock and the USBDIV divider in the PMC_USB register to generate a 48 MHz and a 12 MHz signal with an accuracy of ± 0.25%. The USB clock input is to be defined according to Main Oscillator via the FREQ field. It is defined in the UTMI Clock Trimming Register located in the SFR section (see the “Special Function Registers (SFR)” section of this datasheet for details). This input clock can be 12, 16, 24, or 48 MHz. 26.2.7 DDR2/LPDDR/LPDDR2 Clock The Power Management Controller controls the clocks of the DDR memory. The DDR clock can be enabled and disabled with the DDRCK bit respectively in the PMC_SCER and PMC_SDER. At reset, the DDR clock is disabled to save power consumption. In case MDIV = 00, (PCK = MCK), DDRCK clock is not available. To save PLLA power consumption, the user can choose UPLLCK as an Input clock for the system. In this case the DDR Controller can drive LPDDR or LPDDR2 at up to 120 MHz. 26.2.8 Software Modem Clock The Power Management Controller controls the clocks of the Software Modem. SMDCK is a division of UPLL or PLLA. 26.2.9 Peripheral Clock Controller The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the clock on the peripherals and select a division factor from MCK. This is done with the help of the Peripheral Control Register (PMC_PCR). In order to save power consumption, the division factor can be 1, 2, 4 or 8. The PMC_PCR is a register that features a command and acts like a mailbox. To write the division factor on a particular peripheral, user needs to write a WRITE command, the peripheral ID and the chosen division factor. To read the current division factor on a particular peripheral, user just needs to write the READ command and the peripheral ID. Code Example to select divider 8 for peripheral 2 and enable its clock: write_register(PMC_PCR,0x01030102) Code Example to read the divider of peripheral 4: SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 233 write_register(PMC_PCR,0x00000004) When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Control registers is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 26.2.10 Programmable Clock Output Controller The PMC controls two signals to be outputs on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock (SLCK), the Master Clock (MAINCK), the PLLACK, the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR. Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed. 26.2.11 Main Crystal Clock Failure Detector The clock failure detector monitors the 8 to 48 MHz Crystal or Ceramic Resonator-based oscillator to identify an eventual defect of this oscillator (for example, if the crystal is unconnected). The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled. However, if the 8 to 48 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the clock failure detector is disabled too. A failure is detected by means of a counter incrementing on the 8 to 48 MHz Crystal oscillator or Ceramic Resonatorbased oscillator clock edge and timing logic clocked on the slow clock RC oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is one slow clock RC oscillator clock period. If, during the high level period of the slow clock RC oscillator, less than eight fast crystal oscillator clock periods have been counted, then a failure is declared. The slow RC oscillator must be enabled. The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator. Then the status register must be read two slow clock cycles after enabling. The clock failure detection must be disabled when the main crystal is disabled. If a failure of the 8 to 48 MHz Crystal or Ceramic Resonator-based oscillator clock is detected, the CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not masked. The interrupt remains active until a read operation in the PMC_SR. The user can know the status of the clock failure detector at any time by reading the CFDS bit in the PMC_SR. If the 8 to 48 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACK or UPLLCK (CSS = 2 or 3), a clock failure detection automatically forces MAINCK to be the source clock for the master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection automatically forces the 4/8/12 MHz Fast RC oscillator to be the source clock for MAINCK. If the Fast RC oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure detection mechanism. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 234 It takes two slow clock RC oscillator cycles to detect and switch from the 8 to 48 MHz Crystal, or Ceramic Resonatorbased oscillator, to the 4/8/12 MHz Fast RC Oscillator if the Master Clock source is Main Clock, or three slow clock RC oscillator cycles if the Master Clock source is PLLACK or UPLLCK. A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock failure is detected. This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Register (PMC_FOCR). The user can know the status of the fault output at any time by reading the FOS bit in the PMC_SR. 26.2.12 Programming Sequence 1. If the fast crystal oscillator is not required, PLL can be directly configured (begin with Step 6. or Step 7.) else the fast crystal oscillator must be started (begin with Step 2.). 2. Enabling the fast crystal oscillator: The fast crystal oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register (CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the user must wait for MOSCXTS field in the PMC_SR to be set. This can be done either by polling MOSCXTS in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (MOSCXTS) has been enabled in the PMC_IER. 3. Switch the MAINCK to the Main Crystal Oscillator by setting MOSCSEL in CKGR_MOR. 4. Wait for the MOSCSELS to be set in PMC_SR to ensure the switchover is complete. 5. Checking the Main Clock Frequency: The Main Clock Frequency can be measured via the Main Clock Frequency Register (CKGR_MCFR). Read the CKGR_MCFR until the MAINFRDY field is set, after which the user can read the MAINF field in CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have been counted during a period of 16 slow clock cycles. If MAINF = 0, switch the MAINCK to the Fast RC Oscillator by clearing MOSCSEL in CKGR_MOR. If MAINF ≠ 0, proceed to Step 6. 6. Setting PLLA and divider (if not required, proceed to Step 7.): All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR. The DIVA field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider and PLLA are turned off. The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 127. If MULA is set to 0, PLLA is turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by (MULA + 1). The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR after the CKGR_PLLAR has been written. Once the CKGR_PLLAR has been written, the user must wait for the LOCKA bit to be set in the PMC_SR. This can be done either by polling LOCKA in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKA) has been enabled in the PMC_IER. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage parameter MULA or DIVA is modified, LOCKA bit goes low to indicate that PLLA is not yet ready. When PLLA is locked, LOCKA is set again. If PLLA and divider are enabled, the PLLA input clock is the main clock. PLLA output clock is PLLA input clock multiplied by 5. Once CKGR_PLLAR has been written, LOCKA bit will be set after eight slow clock cycles. Once CKGR_PLLAR is written, the user has to write ‘3’ in the IPLL_PLLA field of the PLL Charge Pump Current Register (PMC_PLLICPR). The user must perform this step before using the PLLA output clock. The user must wait for the LOCKA bit to be set before using the PLLA output clock. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 235 7. Setting Bias and High-speed PLL (UPLL) for UTMI The UTMI PLL is enabled by setting the UPLLEN field in the CKGR_UCKR. The UTMI Bias must is enabled by setting the BIASEN field in the CKGR_UCKR in the same time. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the PLLCOUNT field in the CKGR_UCKR. Once this register has been correctly configured, the user must wait for LOCKU field in the PMC_SR to be set. This can be done either by polling LOCKU in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (LOCKU) has been enabled in the PMC_IER. 8. Selecting Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR. The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the selected clock source is the main clock. The PRES field is used to define the Processor Clock and Master Clock prescaler. The user can choose between different values (1, 2, 3, 4, 8, 16, 32, 64). Prescaler output is the selected clock source frequency divided by the PRES value. The MDIV field is used to define the Master Clock divider. It is possible to choose between different values (0, 1, 2, 3). The Master Clock output is Processor Clock frequency divided by 1, 2, 3 or 4, depending on the value programmed in MDIV. The PMC PLLA Clock input must be divided by 2 by writing the PLLADIV2 bit. By default, MDIV and PLLLADIV2 are set to 0, which indicates that Processor Clock is equal to the Master Clock. Once the PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR. This can be done either by polling MCKRDY in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (MCKRDY) has been enabled in the PMC_IER. The PMC_MCKR must not be programmed in a single write operation. The programming sequence for PMC_MCKR is as follows:   If a new value for CSS field corresponds to PLL Clock,  Program the PRES field in PMC_MCKR.  Wait for the MCKRDY bit to be set in PMC_SR.  Program the CSS field in PMC_MCKR.  Wait for the MCKRDY bit to be set in PMC_SR. If a new value for CSS field corresponds to Main Clock or Slow Clock,  Program the CSS field in PMC_MCKR.  Wait for the MCKRDY bit to be set in the PMC_SR.  Program the PRES field in PMC_MCKR.  Wait for the MCKRDY bit to be set in PMC_SR. If at some stage parameter CSS or PRES is modified, the MCKRDY bit goes low to indicate that the Master Clock and the Processor Clock are not yet ready. The user must wait for the MCKRDY bit to be set again before using the Master and Processor Clocks. Note: If PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCKA goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock. For further information, see see Section 26.2.13.2 “Clock Switching Waveforms”. Code Example: write_register(PMC_MCKR,0x00000001) wait (MCKRDY=1) write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 236 The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 9. Selecting Programmable Clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR. 3 programmable clocks can be used. The PMC_SCSR indicates which programmable clock is enabled. By default all programmable clocks are disabled. PMC_PCKx registers are used to configure programmable clocks. The CSS field is used to select the programmable clock divider source. Five clock options are available: main clock, slow clock, master clock, PLLACK, UPLLCK. The slow clock is the default clock source. The PRES field is used to control the programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES value is set to 0 which means that PCKx is equal to slow clock. Once the PMC_PCKx register has been configured, The corresponding programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done either by polling PCKRDYx in the PMC_SR or by waiting for the interrupt line to be raised if the associated interrupt source (PCKRDYx) has been enabled in the PMC_IER. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable clock and wait for the PCKRDYx bit to be set. 10. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCERx and PMC_PCDRx. 26.2.13 Clock Switching Details 26.2.13.1 Master Clock Switching Timings Table 26-1 and Table 26-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 26-1. Clock Switching Timings (Worst Case) From To Main Clock SLCK Main Clock – 4 x SLCK + 2.5 x Main Clock SLCK 0.5 x Main Clock + 4.5 x SLCK – 3 x PLL Clock + 5 x SLCK PLL Clock 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK Notes: 1. 2. PLL Clock 3 x PLL Clock + 4 x SLCK + 1 x Main Clock PLL designates either the PLLA or the UPLL Clock. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 237 Table 26-2. Clock Switching Timings between Two PLLs (Worst Case) From To PLLA Clock UPLL Clock PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock UPLL Clock 3 x UPLL Clock + 4 x SLCK + 1.5 x UPLL Clock 2.5 x UPLL Clock + 4 x SLCK + UPLLCOUNT x SLCK 26.2.13.2 Clock Switching Waveforms Figure 26-9. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 238 Figure 26-10.Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 26-11.Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Slow Clock Write CKGR_PLLAR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 239 Figure 26-12.Programmable Clock Output Programming PLL Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR PLL Clock is selected PCKx is enabled PCKx is disabled SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 240 26.2.14 Register Write Protection To prevent any single software error from corrupting PMC behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the PMC Write Protection Mode Register (PMC_WPMR). If a write access to a write-protected register is detected, the WPVS bit in the PMC Write Protection Status Register (PMC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PMC_WPSR. The following registers can be protected:  PMC System Clock Enable Register  PMC System Clock Disable Register  PMC Clock Generator Main Clock Frequency Register  PMC Clock Generator PLLA Register  PMC Master Clock Register  PMC USB Clock Register  PMC Programmable Clock Register  PLL Charge Pump Current Register  PMC Peripheral Clock Enable Register 0  PMC Peripheral Clock Disable Register 1  PMC Oscillator Calibration Register SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 241 26.2.15 Power Management Controller (PMC) User Interface Table 26-3. Register Mapping Offset Register Name Access Reset 0x0000 System Clock Enable Register PMC_SCER Write-only – 0x0004 System Clock Disable Register PMC_SCDR Write-only – 0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0005 0x000C Reserved – – 0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only – 0x0014 Peripheral Clock Disable Register 0 PMC_PCDR0 Write-only – 0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000_0000 0x001C UTMI Clock Register CKGR_UCKR Read/Write 0x1020_0000 0x0020 Main Oscillator Register CKGR_MOR Read/Write 0x0100_0001 0x0024 Main Clock Frequency Register CKGR_MCFR Read/Write 0x0000_0000 0x0028 PLLA Register CKGR_PLLAR Read/Write 0x0000_3F00 0x002C Reserved – – 0x0030 Master Clock Register Read/Write 0x0000_0001 0x0034 Reserved – – 0x0038 USB Clock Register PMC_USB Read/Write 0x0000_0000 0x003C Soft Modem Clock Register PMC_SMD Read/Write 0x0000_0000 0x0040 Programmable Clock 0 Register PMC_PCK0 Read/Write 0x0000_0000 0x0044 Programmable Clock 1 Register PMC_PCK1 Read/Write 0x0000_0000 0x0048 Programmable Clock 2 Register PMC_PCK2 Read/Write 0x0000_0000 – – 0x004C–0x005C – – PMC_MCKR – Reserved – 0x0060 Interrupt Enable Register PMC_IER Write-only – 0x0064 Interrupt Disable Register PMC_IDR Write-only – 0x0068 Status Register PMC_SR Read-only 0x0001_0008 0x006C Interrupt Mask Register PMC_IMR Read-only 0x0000_0000 – – Write-only – – – Read/Write 0x0000_0000 – – 0x0070–0x0074 Reserved 0x0078 Fault Output Clear Register 0x007C Reserved 0x0080 PLL Charge Pump Current Register 0x0084–0x00E0 Reserved – PMC_FOCR – PMC_PLLICPR – 0x00E4 Write ProtectIon Mode Register PMC_WPMR Read/Write 0x0000_0000 0x00E8 Write Protection Status Register PMC_WPSR Read-only 0x0000_0000 – – 0x00EC–0x00FC Reserved – 0x0100 Peripheral Clock Enable Register 1 PMC_PCER1 Write-only – 0x0104 Peripheral Clock Disable Register 1 PMC_PCDR1 Write-only – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 242 Table 26-3. Register Mapping Offset Register Name Access Reset 0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read-only 0x0000_0000 0x010C Peripheral Control Register PMC_PCR Read/Write 0x0000_0000 0x0110 Oscillator Calibration Register PMC_OCR Read/Write 0x0040_4040 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 243 26.2.15.1 PMC System Clock Enable Register Name: PMC_SCER Address: 0xFFFFFC00 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 UHP 5 – 4 SMDCK 3 LCDCK 2 DDRCK 1 – 0 – • DDRCK: DDR Clock Enable 0: No effect. 1: Enables the DDR clock. • LCDCK: LCD2x Clock Enable 0: No effect. 1: Enables the LCD2x clock. • SMDCK: SMD Clock Enable 0: No effect. 1: Enables the soft modem clock. • UHP: USB Host OHCI Clocks Enable 0: No effect. 1: Enables the UHP48M and UHP12M OHCI clocks. • UDP: USB Device Clock Enable 0: No effect. 1: Enables the USB Device clock. • PCKx: Programmable Clock x Output Enable 0: No effect. 1: Enables the corresponding Programmable Clock output. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 244 26.2.15.2 PMC System Clock Disable Register Name: PMC_SCDR Address: 0xFFFFFC04 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 UHP 5 – 4 SMDCK 3 LCDCK 2 DDRCK 1 – 0 PCK • PCK: Processor Clock Disable 0: No effect. 1: Disables the Processor clock. This is used to enter the processor in Idle Mode. • DDRCK: DDR Clock Disable 0: No effect. 1: Disables the DDR clock. • LCDCK: LCD2x Clock Disable 0: No effect. 1: Disables the LCD2x clock. • SMDCK: SMD Clock Disable 0: No effect. 1: Disables the soft modem clock. • UHP: USB Host OHCI Clock Disable 0: No effect. 1: Disables the UHP48M and UHP12M OHCI clocks. • UDP: USB Device Clock Enable 0: No effect. 1: Disables the USB Device clock. • PCKx: Programmable Clock x Output Disable 0: No effect. 1: Disables the corresponding Programmable Clock output. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 245 26.2.15.3 PMC System Clock Status Register Name: PMC_SCSR Address: 0xFFFFFC08 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 PCK2 9 PCK1 8 PCK0 7 UDP 6 UHP 5 – 4 SMDCK 3 LCDCK 2 DDRCK 1 – 0 PCK • PCK: Processor Clock Status 0: The Processor clock is disabled. 1: The Processor clock is enabled. • DDRCK: DDR Clock Status 0: The DDR clock is disabled. 1: The DDR clock is enabled. • LCDCK: LCD2x Clock Status 0: The LCD2x clock is disabled. 1: The LCD2x clock is enabled. • SMDCK: SMD Clock Status 0: The soft modem clock is disabled. 1: The soft modem clock is enabled. • UHP: USB Host Port Clock Status 0: The UHP48M and UHP12M OHCI clocks are disabled. 1: The UHP48M and UHP12M OHCI clocks are enabled. • UDP: USB Device Port Clock Status 0: The USB Device clock is disabled. 1: The USB Device clock is enabled. • PCKx: Programmable Clock x Output Status 0: The corresponding Programmable Clock output is disabled. 1: The corresponding Programmable Clock output is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 246 26.2.15.4 PMC Peripheral Clock Enable Register 0 Name: PMC_PCER0 Address: 0xFFFFFC10 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 – 0 – This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other peripherals can be enabled in PMC_PCER1. Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 247 26.2.15.5 PMC Peripheral Clock Disable Register 0 Name: PMC_PCDR0 Address: 0xFFFFFC14 Access: Write-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 - 0 - This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other peripherals can be disabled in PMC_PCDR1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 248 26.2.15.6 PMC Peripheral Clock Status Register 0 Name: PMC_PCSR0 Address: 0xFFFFFC18 Access: Read-only 31 PID31 30 PID30 29 PID29 28 PID28 27 PID27 26 PID26 25 PID25 24 PID24 23 PID23 22 PID22 21 PID21 20 PID20 19 PID19 18 PID18 17 PID17 16 PID16 15 PID15 14 PID14 13 PID13 12 PID12 11 PID11 10 PID10 9 PID9 8 PID8 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 – 0 – • PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled. Note: PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other peripherals status can be read in PMC_PCSR1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 249 26.2.15.7 PMC UTMI Clock Configuration Register Name: CKGR_UCKR Address: 0xFFFFFC1C Access: Read/Write 31 30 29 28 27 – 26 – 25 – 24 BIASEN 21 20 19 – 18 – 17 – 16 UPLLEN BIASCOUNT 23 22 UPLLCOUNT 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • UPLLEN: UTMI PLL Enable 0: The UTMI PLL is disabled. 1: The UTMI PLL is enabled. When UPLLEN is set, the LOCKU flag is set once the UTMI PLL startup time is achieved. • UPLLCOUNT: UTMI PLL Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the UTMI PLL start-up time. • BIASEN: UTMI BIAS Enable 0: The UTMI BIAS is disabled. 1: The UTMI BIAS is enabled. • BIASCOUNT: UTMI BIAS Start-up Time Specifies the number of Slow Clock cycles for the UTMI BIAS startup time. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 250 26.2.15.8 PMC Clock Generator Main Oscillator Register Name: CKGR_MOR Address: 0xFFFFFC20 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 CFDEN 24 MOSCSEL 19 18 17 16 11 10 9 8 3 MOSCRCEN 2 – 1 MOSCXTBY 0 MOSCXTEN KEY 15 14 13 12 MOSCXTST 7 – 6 5 0 4 Warning: Bit 4,5,6 must always be set to 0 when programming the CKGR_MOR. • MOSCXTEN: Main Crystal Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The Main Crystal Oscillator is disabled. 1: The Main Crystal Oscillator is enabled. MOSCXTBY must be set to 0. When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator startup time is achieved. • MOSCXTBY: Main Crystal Oscillator Bypass 0: No effect. 1: The Main Crystal Oscillator is bypassed. MOSCXTEN must be set to 0. An external clock must be connected on XIN. When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set. Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag. • MOSCRCEN: Main On-Chip RC Oscillator Enable 0: The Main On-Chip RC Oscillator is disabled. 1: The Main On-Chip RC Oscillator is enabled. When MOSCRCEN is set, the MOSCRCS flag is set once the Main On-Chip RC Oscillator startup time is achieved. • MOSCXTST: Main Crystal Oscillator Startup Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time. • KEY: Password Value Name 0x37 PASSWD Description Writing any other value in this field aborts the write operation. • MOSCSEL: Main Oscillator Selection 0: The Main On-Chip RC Oscillator is selected. 1: The Main Crystal Oscillator is selected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 251 • CFDEN: Clock Failure Detector Enable 0: The Clock Failure Detector is disabled. 1: The Clock Failure Detector is enabled. The clock failure detection must be disabled when the main crystal is disabled. The slow RC oscillator must be enabled. The clock failure detection must be enabled only when system clock MCK selects the fast RC oscillator. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 252 26.2.15.9 PMC Clock Generator Main Clock Frequency Register Name: CKGR_MCFR Address: 0xFFFFFC24 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 RCMEAS 19 – 18 – 17 – 16 MAINFRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINFRDY: Main Clock Ready 0: MAINF value is not valid or the Main Oscillator is disabled. 1: The Main Oscillator has been enabled previously and MAINF value is available. Note: To ensure that a correct value is read on the MAINF field, the MAINFRDY flag must be read at 1, then another read access must be performed on the register to obtain a stable value on the MAINF field. • RCMEAS: RC Oscillator Frequency Measure (write-only) 0: No effect. 1: Restarts a measure of the main RC frequency, MAINF will carry the new frequency as soon as a low to high transition occurs on MAINFRDY flag. The measure is performed on the main frequency (i.e., not limited to RC oscillator only) but if the main clock frequency source is the fast crystal oscillator, the restart of the measure is unneeded because of the well known stability of crystal oscillators. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 253 26.2.15.10 PMC Clock Generator PLLA Register Name: CKGR_PLLAR Address: 0xFFFFFC28 Access: Read/Write 31 – 30 – 29 ONE 23 22 21 28 – 27 – 26 – 25 – 20 19 18 17 MULA 15 14 13 24 MULA 16 OUTA 12 11 OUTA 10 9 8 2 1 0 PLLACOUNT 7 6 5 4 3 DIVA Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR. • DIVA: Divider A Value Name Description 0 0 Divider output is 0 1 BYPASS Divider is bypassed 2 - 255 - Divider output is the selected clock divided by DIVA. • PLLACOUNT: PLLA Counter Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. • OUTA: PLLA Clock Frequency Range To be programmed to 0. • MULA: PLLA Multiplier 0: The PLLA is deactivated. 1 up to 127: The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1. • ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the CKGR_PLLAR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 254 26.2.15.11 PMC Master Clock Register Name: PMC_MCKR Address: 0xFFFFFC30 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 PLLADIV2 11 – 10 – 9 8 7 – 6 5 PRES 4 3 – 2 – 1 MDIV 0 CSS • CSS: Master/Processor Clock Source Selection Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLACK is selected 3 UPLL_CLK UPLL Clock is selected • PRES: Master/Processor Clock Prescaler Value Name Description 0 CLOCK Selected clock 1 CLOCK_DIV2 Selected clock divided by 2 2 CLOCK_DIV4 Selected clock divided by 4 3 CLOCK_DIV8 Selected clock divided by 8 4 CLOCK_DIV16 Selected clock divided by 16 5 CLOCK_DIV32 Selected clock divided by 32 6 CLOCK_DIV64 Selected clock divided by 64 7 Reserved Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 255 • MDIV: Master Clock Division Value Name 0 EQ_PCK 1 PCK_DIV2 2 PCK_DIV4 3 PCK_DIV3 Description Master Clock is Prescaler Output Clock divided by 1. Warning: SysClk DDR and DDRCK are not available. Master Clock is Prescaler Output Clock divided by 2. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 4. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. Master Clock is Prescaler Output Clock divided by 3. SysClk DDR is equal to 2 x MCK. DDRCK is equal to MCK. • PLLADIV2: PLLA Divisor by 2 Bit PLLADIV2 must always be set to 1 when MDIV is set to 3. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 256 26.2.15.12 PMC USB Clock Register Name: PMC_USB Address: 0xFFFFFC38 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 – 6 – 5 – 4 – 3 – 1 – 0 USBS USBDIV 2 – • USBS: USB OHCI Input clock selection 0: USB Clock Input is PLLA. 1: USB Clock Input is UPLL. • USBDIV: Divider for USB OHCI Clock. USB Clock is Input clock divided by USBDIV + 1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 257 26.2.15.13 PMC SMD Clock Register Name: PMC_SMD Address: 0xFFFFFC3C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 SMDDIV 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SMDS • SMDS: SMD input clock selection 0: SMD Clock Input is PLLA. 1: SMD Clock Input is UPLL. • SMDDIV: Divider for SMD Clock. SMD Clock is Input clock divided by SMD + 1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 258 26.2.15.14 PMC Programmable Clock Register Name: PMC_PCKx[x = 0..2] Address: 0xFFFFFC40 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 5 PRES 4 3 – 2 1 CSS 0 • CSS: Master Clock Source Selection Value Name Description 0 SLOW_CLK Slow Clock is selected 1 MAIN_CLK Main Clock is selected 2 PLLA_CLK PLLACK is selected 3 UPLL_CLK UPLL Clock is selected 4 MCK_CLK Master Clock is selected • PRES: Programmable Clock Prescaler Value Name Description 0 CLOCK Selected clock 1 CLOCK_DIV2 Selected clock divided by 2 2 CLOCK_DIV4 Selected clock divided by 4 3 CLOCK_DIV8 Selected clock divided by 8 4 CLOCK_DIV16 Selected clock divided by 16 5 CLOCK_DIV32 Selected clock divided by 32 6 CLOCK_DIV64 Selected clock divided by 64 7 Reserved Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 259 26.2.15.15 PMC Interrupt Enable Register Name: PMC_IER Address: 0xFFFFFC60 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 CFDEV 17 – 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 – 6 LOCKU 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS • MOSCXTS: Main Crystal Oscillator Status Interrupt Enable • LOCKA: PLLA Lock Interrupt Enable • MCKRDY: Master Clock Ready Interrupt Enable • LOCKU: UTMI PLL Lock Interrupt Enable • PCKRDYx: Programmable Clock Ready x Interrupt Enable • MOSCSELS: Main Oscillator Selection Status Interrupt Enable • CFDEV: Clock Failure Detector Event Interrupt Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 260 26.2.15.16 PMC Interrupt Disable Register Name: PMC_IDR Address: 0xFFFFFC64 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 CFDEV 17 – 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 – 6 LOCKU 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS • MOSCXTS: Main Crystal Oscillator Status Interrupt Disable • LOCKA: PLLA Lock Interrupt Disable • MCKRDY: Master Clock Ready Interrupt Disable • LOCKU: UTMI PLL Lock Interrupt Enable • PCKRDYx: Programmable Clock Ready x Interrupt Disable • MOSCSELS: Main Oscillator Selection Status Interrupt Disable • CFDEV: Clock Failure Detector Event Interrupt Disable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 261 26.2.15.17 PMC Status Register Name: PMC_SR Address: 0xFFFFFC68 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 FOS 19 CFDS 18 CFDEV 17 – 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 OSCSELS 6 LOCKU 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS • MOSCXTS: Main XTAL Oscillator Status 0: Main XTAL oscillator is not stabilized. 1: Main XTAL oscillator is stabilized. • LOCKA: PLLA Lock Status 0: PLLA is not locked. 1: PLLA is locked. • MCKRDY: Master Clock Status 0: Master Clock is not ready. 1: Master Clock is ready. • LOCKU: UPLL Clock Status 0: UPLL Clock is not ready. 1: UPLL Clock is ready. • OSCSELS: Slow Clock Oscillator Selection 0: Internal slow clock RC oscillator is selected. 1: External slow clock 32 kHz oscillator is selected. • PCKRDYx: Programmable Clock Ready Status 0: Programmable Clock x is not ready. 1: Programmable Clock x is ready. • MOSCSELS: Main Oscillator Selection Status 0: Selection is in progress. 1: Selection is done. • CFDEV: Clock Failure Detector Event 0: No clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 262 1: At least one clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR. • CFDS: Clock Failure Detector Status 0: A clock failure of the fast crystal oscillator clock is not detected. 1: A clock failure of the fast crystal oscillator clock is detected. • FOS: Clock Failure Detector Fault Output Status 0: The fault output of the clock failure detector is inactive. 1: The fault output of the clock failure detector is active. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 263 26.2.15.18 PMC Interrupt Mask Register Name: PMC_IMR Address: 0xFFFFFC6C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 CFDEV 17 – 16 MOSCSELS 15 – 14 – 13 – 12 – 11 – 10 PCKRDY2 9 PCKRDY1 8 PCKRDY0 7 – 6 – 5 – 4 – 3 MCKRDY 2 – 1 LOCKA 0 MOSCXTS • MOSCXTS: Main Crystal Oscillator Status Interrupt Mask • LOCKA: PLLA Lock Interrupt Mask • MCKRDY: Master Clock Ready Interrupt Mask • PCKRDYx: Programmable Clock Ready x Interrupt Mask • MOSCSELS: Main Oscillator Selection Status Interrupt Mask • CFDEV: Clock Failure Detector Event Interrupt Mask SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 264 26.2.15.19 PMC Fault Output Clear Register Name: PMC_FOCR Address: 0xFFFFFC78 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FOCLR • FOCLR: Fault Output Clear Clears the clock failure detector fault output. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 265 26.2.15.20 PLL Charge Pump Current Register Name: PMC_PLLICPR Address: 0xFFFFFC80 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 24 23 – 22 – 21 – 20 – 19 – 18 – 17 15 – 14 – 13 – 12 – 11 – 10 9 IPLL_PLLA 8 7 – 6 – 5 – 4 – 3 – 2 – 1 0 IVCO_PLLU 16 ICP_PLLU ICP_PLLA • ICP_PLLA: Charge Pump Current PLLA To optimize clock performance, this field must be programmed as specified in “PLL A Characteristics” in the Electrical Characteristics section of the product datasheet. • IPLL_PLLA: Engineering Configuration PLLA Should be written to 3. • ICP_PLLU: Charge Pump Current PLL UTMI Should be written to 0. • IVCO_PLLU: Voltage Control Output Current PLL UTMI Should be written to 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 266 26.2.15.21 PMC Write Protection Mode Register Name: PMC_WPMR Address: 0xFFFFFCE4 Access: Read/Write Reset: See Table 26-3 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 — 6 — 5 — 4 — • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII). See Section 26.2.14 “Register Write Protection” for the list of registers which can be protected. • WPKEY: Write Protect Key Value Name 0x504D43 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 267 26.2.15.22 PMC Write Protection Status Register Name: PMC_WPSR Address: 0xFFFFFCE8 Access: Read-only Reset: See Table 26-3 31 — 30 — 29 — 28 — 23 22 21 20 27 — 26 — 25 — 24 — 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 — 6 — 5 — 4 — • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the PMC_WPSR. 1: A Write Protect Violation has occurred since the last read of the PMC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 268 26.2.15.23 PMC Peripheral Clock Enable Register 1 Name: PMC_PCER1 Address: 0xFFFFFD00 Access: Write-only 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock. Notes: 1. PID32 to PID63 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. 2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 269 26.2.15.24 PMC Peripheral Clock Disable Register 1 Name: PMC_PCDR1 Address: 0xFFFFFD04 Access: Write-only 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock. Note: PID32 to PID63 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 270 26.2.15.25 PMC Peripheral Clock Status Register 1 Name: PMC_PCSR1 Address: 0xFFFFFD08 Access: Read-only 31 PID63 30 PID62 29 PID61 28 PID60 27 PID59 26 PID58 25 PID57 24 PID56 23 PID55 22 PID54 21 PID53 20 PID52 19 PID51 18 PID50 17 PID49 16 PID48 15 PID47 14 PID46 13 PID45 12 PID44 11 PID43 10 PID42 9 PID41 8 PID40 7 PID39 6 PID38 5 PID37 4 PID36 3 PID35 2 PID34 1 PID33 0 PID32 • PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled. 1: The corresponding peripheral clock is enabled. Note: PID32 to PID63 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 271 26.2.15.26 PMC Peripheral Control Register Name: PMC_PCR Address: 0xFFFFFD0C Access: Read/Write 31 — 30 — 29 — 28 EN 27 — 26 — 25 — 24 — 23 — 22 — 21 — 20 — 19 — 18 — 17 15 — 14 — 13 — 12 CMD 11 — 10 — 9 — 8 — 7 — 6 — 5 4 3 2 1 0 16 DIV PID • PID: Peripheral ID Peripheral ID selection from PID2 to the maximum PID number. This refers to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Only the following peripherals can be configured with divided clock (DIV > 0): ADC, SSCx, CANx, USARTx, UARTx, TWIx, SPIx, and TCx.” Among the PIDs supporting the divided clock, some require a DIV value configuration matching the maximum peripheral frequency (refer to table “Maximum Values for each Peripheral” in the “Electrical Characteristics” section of datasheet). • CMD: Command 0: Read mode 1: Write mode • DIV: Divisor value Value Name Description 0 PERIPH_DIV_MCK Peripheral clock is MCK 1 PERIPH_DIV2_MCK Peripheral clock is MCK/2 2 PERIPH_DIV4_MCK Peripheral clock is MCK/4 3 PERIPH_DIV8_MCK Peripheral clock is MCK/8 • EN: Enable 0: Selected Peripheral clock is disabled 1: Selected Peripheral clock is enabled SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 272 26.2.15.27 PMC Oscillator Calibration Register Name: PMC_OCR Address: 0xFFFFFD10 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SEL 6 5 4 3 CAL 2 1 0 This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register. • CAL: 12 MHz RC Oscillator Calibration bits Calibration bits applied to the RC Oscillator when SEL is set. • SEL: Selection of RC Oscillator Calibration bits 0: Factory determined value. 1: Value written by user in CAL field of this register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 273 27. Parallel Input/Output Controller (PIO) 27.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of the product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. Each I/O line of the PIO Controller features:  An input change interrupt enabling level change detection on any I/O line.  Additional Interrupt modes enabling rising edge, falling edge, low-level or high-level detection on any I/O line.  A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle.  A debouncing filter providing rejection of unwanted pulses from key or push button operations.  Multi-drive capability similar to an open drain I/O line.  Control of the pull-up and pull-down of the I/O line.  Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 27.2 Embedded Characteristics  Up to 32 Programmable I/O Lines  Fully Programmable through Set/Clear Registers  Multiplexing of Four Peripheral Functions per I/O Line  For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)  Input Change Interrupt  Programmable Glitch Filter  Programmable Debouncing Filter  Multi-drive Option Enables Driving in Open Drain  Programmable Pull-Up on Each I/O Line  Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time  Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low-Level or High-Level  Lock of the Configuration by the Connected Peripheral  Synchronous Output, Provides Set and Clear of Several I/O Lines in a Single Write  Write Protect Registers  Programmable Schmitt Trigger Inputs  Programmable I/O Drive SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 274 27.3 Block Diagram Figure 27-1. Block Diagram PIO Controller Interrupt Controller PIO Interrupt PIO Clock PMC Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 27-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 275 27.4 Product Dependencies 27.4.1 Pin Multiplexing Each pin is configurable, depending on the product, as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. 27.4.2 External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. 27.4.3 Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering. Note that the input change interrupt, the interrupt modes on a programmable event and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 27.4.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. Using the PIO Controller requires the Interrupt Controller to be programmed first. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 276 27.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 27-3. In this description each signal shown represents one of up to 32 possible indexes. Figure 27-3. I/O Line Control Logic PIO_OER[0] VDD PIO_OSR[0] PIO_PUER[0] PIO_ODR[0] PIO_PUSR[0] PIO_PUDR[0] 1 Peripheral A Output Enable 00 01 10 11 Peripheral B Output Enable Peripheral C Output Enable Peripheral D Output Enable 0 0 PIO_PER[0] PIO_ABCDSR1[0] PIO_PDR[0] 00 01 10 11 Peripheral B Output Peripheral C Output Peripheral D Output 1 PIO_PSR[0] PIO_ABCDSR2[0] Peripheral A Output Integrated Pull-Up Resistor PIO_MDER[0] PIO_MDSR[0] 0 PIO_MDDR[0] 0 PIO_SODR[0] 1 PIO_ODSR[0] Pad PIO_CODR[0] 1 PIO_PPDER[0] Integrated Pull-Down Resistor PIO_PPDSR[0] PIO_PPDDR[0] GND Peripheral A Input Peripheral B Input Peripheral C Input Peripheral D Input PIO_PDSR[0] PIO_ISR[0] 0 D PIO Clock 0 Slow Clock PIO_SCDR Clock Divider 1 Programmable Glitch or Debouncing Filter Q DFF D Q DFF EVENT DETECTOR (Up to 32 possible inputs) PIO Interrupt 1 Resynchronization Stage PIO_IER[0] PIO_IMR[0] PIO_IFER[0] PIO_IDR[0] PIO_IFSR[0] PIO_IFSCER[0] PIO_IFSCSR[0] PIO_IFSCDR[0] PIO_IFDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 277 27.5.1 Pull-up and Pull-down Resistor Control Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor can be enabled or disabled by writing to the Pull-up Enable register (PIO_PUER) or Pull-up Disable register (PIO_PUDR), respectively. Writing to these registers results in setting or clearing the corresponding bit in the Pull-up Status register (PIO_PUSR). Reading a one in PIO_PUSR means the pull-up is disabled and reading a zero means the pull-up is enabled. The pull-down resistor can be enabled or disabled by writing the Pull-down Enable register (PIO_PPDER) or the Pull-down Disable register (PIO_PPDDR), respectively. Writing in these registers results in setting or clearing the corresponding bit in the Pull-down Status register (PIO_PPDSR). Reading a one in PIO_PPDSR means the pull-up is disabled and reading a zero means the pull-down is enabled. Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of PIO_PPDER for the relevant I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. In this case, the write of PIO_PUER for the relevant I/O line is discarded. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are disabled, i.e. PIO_PPDSR resets at the value 0xFFFFFFFF. 27.5.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the Enable register (PIO_PER) and the Disable register (PIO_PDR). The Status register (PIO_PSR) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of zero indicates that the pin is controlled by the corresponding on-chip peripheral selected in the ABCD Select registers (PIO_ABCDSR1 and PIO_ABCDSR2). A value of one indicates the pin is controlled by the PIO Controller. If a pin is used as a general-purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns a one for the corresponding bit. After reset, the I/O lines are controlled by the PIO Controller, i.e. PIO_PSR resets at one. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset, or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level and depends on the multiplexing of the device. 27.5.3 Peripheral A or B or C or D Selection The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by writing PIO_ABCDSR1 and PIO_ABCDSR2. For each pin:  The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral A is selected.  The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral B is selected.  The corresponding bit at level zero in PIO_ABCDSR1 and the corresponding bit at level one in PIO_ABCDSR2 means peripheral C is selected.  The corresponding bit at level one in PIO_ABCDSR1 and the corresponding bit at level zero in PIO_ABCDSR2 means peripheral D is selected. Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always connected to the pin input. Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in PIO_ABCDSR1 and PIO_ABCDSR2 in addition to a write in PIO_PDR. After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are zero, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 278 27.5.4 Output Control When the I/O line is assigned to a peripheral function, i.e., the corresponding bit in PIO_PSR is at zero, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and PIO_ABCDSR2 determines whether the pin is driven or not. When the I/O line is controlled by the PIO Controller, the pin can be configured to be driven. This is done by writing the Output Enable register (PIO_OER) and Output Disable register (PIO_ODR). The results of these write operations are detected in the Output Status register (PIO_OSR). When a bit in this register is at zero, the corresponding I/O line is used as an input only. When the bit is at one, the corresponding I/O line is driven by the PIO Controller. The level driven on an I/O line can be determined by writing in the Set Output Data register (PIO_SODR) and the Clear Output Data register (PIO_CODR). These write operations, respectively, set and clear the Output Data Status register (PIO_ODSR), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO Controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR affects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 27.5.5 Synchronous Data Output Clearing one or more PIO line(s) and setting another one or more PIO line(s) synchronously cannot be done by using PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different registers. To overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR. Only bits unmasked by the Output Write Status register (PIO_OWSR) are written. The mask bits in PIO_OWSR are set by writing to the Output Write Enable register (PIO_OWER) and cleared by writing to the Output Write Disable register (PIO_OWDR). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 27.5.6 Multi-Drive Control (Open Drain) Each I/O can be independently programmed in open drain by using the multi-drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The multi-drive feature is controlled by the Multi-driver Enable register (PIO_MDER) and the Multi-driver Disable register (PIO_MDDR). The multi-drive can be selected whether the I/O line is controlled by the PIO Controller or assigned to a peripheral function. The Multi-driver Status register (PIO_MDSR) indicates the pins that are configured to support external drivers. After reset, the multi-drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 27.5.7 Output Line Timings Figure 27-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 27-4 also shows when the feedback in the Pin Data Status register (PIO_PDSR) is available. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 279 Figure 27-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 27.5.8 Inputs The level on each I/O line can be read through PIO_PDSR. This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input, or driven by the PIO Controller, or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 27.5.9 Input Glitch and Debouncing Filters Optional input glitch and debouncing filters are independently programmable on each I/O line. The glitch filter can filter a glitch with a duration of less than 1/2 master clock (MCK) and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. The selection between glitch filtering or debounce filtering is done by writing in the PIO Input Filter Slow Clock Disable register (PIO_IFSCDR) and the PIO Input Filter Slow Clock Enable register (PIO_IFSCER). Writing PIO_IFSCDR and PIO_IFSCER, respectively, sets and clears bits in the Input Filter Slow Clock Status register (PIO_IFSCSR). The current selection status can be checked by reading the register PIO_IFSCSR.  If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 master clock period.  If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 programmable divided slow clock period. For the debouncing filter, the period of the divided slow clock is performed by writing in the DIV field of the Slow Clock Divider register (PIO_SCDR. Tdiv_slclk = ((DIV+1)*2).Tslow_clock When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents MCK or divided slow clock depending on PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a duration of one selected clock (MCK or divided slow clock) cycle or more is accepted. For pulse durations between 1/2 selected clock cycle and one selected clock cycle, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible, it must exceed one selected clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle. The filters also introduce some latencies, illustrated in Figure 27-5 and Figure 27-6. The glitch filters are controlled by the Input Filter Enable register (PIO_IFER), the Input Filter Disable register (PIO_IFDR) and the Input Filter Status register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 280 When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters require that the PIO Controller clock is enabled. Figure 27-5. Input Glitch Filter Timing PIO_IFCSR = 0 MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles 1 cycle up to 2.5 cycles PIO_PDSR if PIO_IFSR = 1 up to 2 cycles Figure 27-6. Input Debouncing Filter Timing PIO_IFCSR = 1 Divided Slow Clock Pin Level up to 2 cycles Tmck up to 2 cycles Tmck PIO_PDSR if PIO_IFSR = 0 1 cycle Tdiv_slclk PIO_PDSR if PIO_IFSR = 1 1 cycle Tdiv_slclk up to 1.5 cycles Tdiv_slclk up to 1.5 cycles Tdiv_slclk up to 2 cycles Tmck up to 2 cycles Tmck 27.5.10 Input Edge/Level Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The Input Edge/Level interrupt is controlled by writing the Interrupt Enable register (PIO_IER) and the Interrupt Disable register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and clearing the corresponding bit in the Interrupt Mask register (PIO_IMR). As input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change interrupt is available regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. By default, the interrupt can be generated at any time an edge is detected on the input. Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable register (PIO_AIMER) and Additional Interrupt Modes Disable register (PIO_AIMDR). The current state of this selection can be read through the Additional Interrupt Modes Mask register (PIO_AIMMR). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 281 These additional modes are:  Rising edge detection  Falling edge detection  Low-level detection  High-level detection In order to select an additional interrupt mode:  The type of event detection (edge or level) must be selected by writing in the Edge Select register (PIO_ESR) and Level Select register (PIO_LSR) which , respectively, the edge and level detection. The current status of this selection is accessible through the Edge/Level Status register (PIO_ELSR).  The polarity of the event detection (rising/falling edge or high/low-level) must be selected by writing in the Falling Edge /Low-Level Select register (PIO_FELLSR) and Rising Edge/High-Level Select register (PIO_REHLSR) which allow to select falling or rising edge (if edge is selected in PIO_ELSR) edge or high- or low-level detection (if level is selected in PIO_ELSR). The current status of this selection is accessible through the Fall/Rise - Low/High Status register (PIO_FRLHSR). When an input edge or level is detected on an I/O line, the corresponding bit in the Interrupt Status register (PIO_ISR) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt signals of the 32 channels are ORed-wired together to generate a single interrupt signal to the interrupt controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “level”, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed. Figure 27-7. Event Detector on Input Lines (Figure Represents Line 0) Event Detector Rising Edge Detector 1 Falling Edge Detector 0 0 PIO_REHLSR[0] 1 PIO_FRLHSR[0] PIO_FELLSR[0] Resynchronized input on line 0 Event detection on line 0 1 0 High Level Detector 1 Low Level Detector 0 PIO_LSR[0] PIO_ELSR[0] PIO_ESR[0] PIO_AIMER[0] PIO_AIMMR[0] PIO_AIMDR[0] Edge Detector SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 282 27.5.10.1 Example If generating an interrupt is required on the lines below, the configuration required is described in Section 27.5.10.2 ”Interrupt Mode Configuration”, Section 27.5.10.3 ”Edge or Level Detection Configuration” and Section 27.5.10.4 ”Falling/Rising Edge or Low/High-Level Detection Configuration”:  Rising edge on PIO line 0  Falling edge on PIO line 1  Rising edge on PIO line 2  Low-level on PIO line 3  High-level on PIO line 4  High-level on PIO line 5  Falling edge on PIO line 6  Rising edge on PIO line 7  Any edge on the other lines the configuration required is described below. 27.5.10.2 Interrupt Mode Configuration All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER. Then the additional interrupt mode is enabled for lines 0 to 7 by writing 32’h0000_00FF in PIO_AIMER. 27.5.10.3 Edge or Level Detection Configuration Lines 3, 4 and 5 are configured in level detection by writing 32’h0000_0038 in PIO_LSR. The other lines are configured in edge detection by default, if they have not been previously configured. Otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32’h0000_00C7 in PIO_ESR. 27.5.10.4 Falling/Rising Edge or Low/High-Level Detection Configuration Lines 0, 2, 4, 5 and 7 are configured in rising edge or high-level detection by writing 32’h0000_00B5 in PIO_REHLSR. The other lines are configured in falling edge or low-level detection by default if they have not been previously configured. Otherwise, lines 1, 3 and 6 must be configured in falling edge/low-level detection by writing 32’h0000_004A in PIO_FELLSR. Figure 27-8. Input Change Interrupt Timings When No Additional Interrupt Modes MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 27.5.11 I/O Lines Lock When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become locked by the action of this peripheral via an input of the PIO Controller. When an I/O line is locked, the write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER, PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which I/O line is locked by SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 283 reading the PIO Lock Status register (PIO_LOCKSR). Once an I/O line is locked, the only way to unlock it is to apply a hardware reset to the PIO Controller. 27.5.12 Programmable I/O Drive It is possible to configure the I/O drive for pads PA0 to PA31. For any details, refer to the product electrical characteristics. 27.5.13 Programmable Schmitt Trigger It is possible to configure each input for the Schmitt trigger. By default the Schmitt trigger is active. Disabling the Schmitt trigger is requested when using the QTouch™ Library. 27.5.14 Register Write Protection To prevent any single software error from corrupting PIO behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the “PIO Write Protection Mode Register” (PIO_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the “PIO Write Protection Status Register” (PIO_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the PIO_WPSR. The following registers can be write-protected: 27.6  “PIO Enable Register” on page 289  “PIO Disable Register” on page 290  “PIO Output Enable Register” on page 292  “PIO Output Disable Register” on page 293  “PIO Input Filter Enable Register” on page 295  “PIO Input Filter Disable Register” on page 296  “PIO Multi-driver Enable Register” on page 306  “PIO Multi-driver Disable Register” on page 307  “PIO Pull-Up Disable Register” on page 309  “PIO Pull-Up Enable Register” on page 310  “PIO Peripheral ABCD Select Register 1” on page 312  “PIO Peripheral ABCD Select Register 2” on page 313  “PIO Output Write Enable Register” on page 321  “PIO Output Write Disable Register” on page 322  “PIO Pad Pull-Down Disable Register” on page 318  “PIO Pad Pull-Down Status Register” on page 320 I/O Lines Programming Example The programming example shown in Table 27-1 is used to obtain the following configuration.  4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor  Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor, no pulldown resistor  Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts  Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter  I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor  I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 284  I/O line 24 to 27 assigned to peripheral C with Input Change Interrupt, no pull-up resistor and no pull-down resistor  I/O line 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor Table 27-1. Programming Example Register Value to be Written PIO_PER 0x0000_FFFF PIO_PDR 0xFFFF_0000 PIO_OER 0x0000_00FF PIO_ODR 0xFFFF_FF00 PIO_IFER 0x0000_0F00 PIO_IFDR 0xFFFF_F0FF PIO_SODR 0x0000_0000 PIO_CODR 0x0FFF_FFFF PIO_IER 0x0F00_0F00 PIO_IDR 0xF0FF_F0FF PIO_MDER 0x0000_000F PIO_MDDR 0xFFFF_FFF0 PIO_PUDR 0xFFF0_00F0 PIO_PUER 0x000F_FF0F PIO_PPDDR 0xFF0F_FFFF PIO_PPDER 0x00F0_0000 PIO_ABCDSR1 0xF0F0_0000 PIO_ABCDSR2 0xFF00_0000 PIO_OWER 0x0000_000F PIO_OWDR 0x0FFF_ FFF0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 285 27.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is notmultiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns one systematically. Table 27-2. Register Mapping Offset Register Name Access Reset 0x0000 PIO Enable Register PIO_PER Write-only – 0x0004 PIO Disable Register PIO_PDR Write-only – Read-only (1) – – 0x0008 PIO Status Register PIO_PSR 0x000C Reserved 0x0010 Output Enable Register PIO_OER Write-only – 0x0014 Output Disable Register PIO_ODR Write-only – 0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000 0x001C Reserved – – 0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only – 0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only – 0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000 0x002C Reserved – – 0x0030 Set Output Data Register PIO_SODR Write-only – 0x0034 Clear Output Data Register PIO_CODR Write-only 0x0038 Output Data Status Register PIO_ODSR Read-only or(2) Read/Write – 0x003C Pin Data Status Register PIO_PDSR Read-only (3) 0x0040 Interrupt Enable Register PIO_IER Write-only – 0x0044 Interrupt Disable Register PIO_IDR Write-only – – – – 0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000 0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000 0x0050 Multi-driver Enable Register PIO_MDER Write-only – 0x0054 Multi-driver Disable Register PIO_MDDR Write-only – 0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000 0x005C Reserved – – 0x0060 Pull-up Disable Register PIO_PUDR Write-only – 0x0064 Pull-up Enable Register PIO_PUER Write-only – Read-only (1) – – 0x0068 Pad Pull-up Status Register 0x006C Reserved – PIO_PUSR – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 286 Table 27-2. Register Mapping (Continued) Offset Register Name Access Reset 0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read/Write 0x00000000 0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read/Write 0x00000000 0x0078 to 0x007C Reserved – – – 0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-only – 0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only – 0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000 0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read/Write 0x00000000 0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only – 0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only – Read-only (1) – – 0x0098 Pad Pull-down Status Register PIO_PPDSR 0x009C Reserved 0x00A0 Output Write Enable PIO_OWER Write-only – 0x00A4 Output Write Disable PIO_OWDR Write-only – 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 – 0x00AC Reserved – – 0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER – Write-only – 0x00B4 Additional Interrupt Modes Disable Register PIO_AIMDR Write-only – 0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000 0x00BC Reserved – – 0x00C0 Edge Select Register PIO_ESR Write-only – 0x00C4 Level Select Register PIO_LSR Write-only – 0x00C8 Edge/Level Status Register PIO_ELSR Read-only 0x00000000 – 0x00CC Reserved – – 0x00D0 Falling Edge/Low-Level Select Register PIO_FELLSR – Write-only – 0x00D4 Rising Edge/ High-Level Select Register PIO_REHLSR Write-only – 0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000 0x00DC Reserved – – 0x00E0 Lock Status PIO_LOCKSR Read-only 0x00000000 0x00E4 Write Protection Mode Register PIO_WPMR Read/Write 0x0 0x00E8 Write Protection Status Register PIO_WPSR Read-only 0x0 0x00EC to 0x00F8 Reserved – – – 0x0100 Schmitt Trigger Register PIO_SCHMITT Read/Write 0x00000000 0x01040x010C Reserved – – – 0x0110 Reserved – – – 0x0114 Reserved – – – – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 287 Table 27-2. Register Mapping (Continued) Offset Register Name Access Reset 0x0118 I/O Drive Register 1 PIO_DRIVER1 Read/Write 0x00000000 0x011C I/O Drive Register 2 PIO_DRIVER2 Read/Write 0x00000000 0x0120 to 0x014C Reserved – – – Notes: 1. Reset value depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. If an offset is not listed in the table it must be considered as reserved. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 288 27.7.1 PIO Enable Register Name: PIO_PER Address: 0xFFFFF200 (PIOA), 0xFFFFF400 (PIOB), 0xFFFFF600 (PIOC), 0xFFFFF800 (PIOD), 0xFFFFFA00 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 289 27.7.2 PIO Disable Register Name: PIO_PDR Address: 0xFFFFF204 (PIOA), 0xFFFFF404 (PIOB), 0xFFFFF604 (PIOC), 0xFFFFF804 (PIOD), 0xFFFFFA04 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 290 27.7.3 PIO Status Register Name: PIO_PSR Address: 0xFFFFF208 (PIOA), 0xFFFFF408 (PIOB), 0xFFFFF608 (PIOC), 0xFFFFF808 (PIOD), 0xFFFFFA08 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active). 1: PIO is active on the corresponding I/O line (peripheral is inactive). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 291 27.7.4 PIO Output Enable Register Name: PIO_OER Address: 0xFFFFF210 (PIOA), 0xFFFFF410 (PIOB), 0xFFFFF610 (PIOC), 0xFFFFF810 (PIOD), 0xFFFFFA10 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 292 27.7.5 PIO Output Disable Register Name: PIO_ODR Address: 0xFFFFF214 (PIOA), 0xFFFFF414 (PIOB), 0xFFFFF614 (PIOC), 0xFFFFF814 (PIOD), 0xFFFFFA14 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Output Disable 0: No effect. 1: Disables the output on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 293 27.7.6 PIO Output Status Register Name: PIO_OSR Address: 0xFFFFF218 (PIOA), 0xFFFFF418 (PIOB), 0xFFFFF618 (PIOC), 0xFFFFF818 (PIOD), 0xFFFFFA18 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 294 27.7.7 PIO Input Filter Enable Register Name: PIO_IFER Address: 0xFFFFF220 (PIOA), 0xFFFFF420 (PIOB), 0xFFFFF620 (PIOC), 0xFFFFF820 (PIOD), 0xFFFFFA20 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 295 27.7.8 PIO Input Filter Disable Register Name: PIO_IFDR Address: 0xFFFFF224 (PIOA), 0xFFFFF424 (PIOB), 0xFFFFF624 (PIOC), 0xFFFFF824 (PIOD), 0xFFFFFA24 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 296 27.7.9 PIO Input Filter Status Register Name: PIO_IFSR Address: 0xFFFFF228 (PIOA), 0xFFFFF428 (PIOB), 0xFFFFF628 (PIOC), 0xFFFFF828 (PIOD), 0xFFFFFA28 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 297 27.7.10 PIO Set Output Data Register Name: PIO_SODR Address: 0xFFFFF230 (PIOA), 0xFFFFF430 (PIOB), 0xFFFFF630 (PIOC), 0xFFFFF830 (PIOD), 0xFFFFFA30 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 298 27.7.11 PIO Clear Output Data Register Name: PIO_CODR Address: 0xFFFFF234 (PIOA), 0xFFFFF434 (PIOB), 0xFFFFF634 (PIOC), 0xFFFFF834 (PIOD), 0xFFFFFA34 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Clear Output Data 0: No effect. 1: Clears the data to be driven on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 299 27.7.12 PIO Output Data Status Register Name: PIO_ODSR Address: 0xFFFFF238 (PIOA), 0xFFFFF438 (PIOB), 0xFFFFF638 (PIOC), 0xFFFFF838 (PIOD), 0xFFFFFA38 (PIOE) Access: Read-only or Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 300 27.7.13 PIO Pin Data Status Register Name: PIO_PDSR Address: 0xFFFFF23C (PIOA), 0xFFFFF43C (PIOB), 0xFFFFF63C (PIOC), 0xFFFFF83C (PIOD), 0xFFFFFA3C (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 301 27.7.14 PIO Interrupt Enable Register Name: PIO_IER Address: 0xFFFFF240 (PIOA), 0xFFFFF440 (PIOB), 0xFFFFF640 (PIOC), 0xFFFFF840 (PIOD), 0xFFFFFA40 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Enable 0: No effect. 1: Enables the Input Change interrupt on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 302 27.7.15 PIO Interrupt Disable Register Name: PIO_IDR Address: 0xFFFFF244 (PIOA), 0xFFFFF444 (PIOB), 0xFFFFF644 (PIOC), 0xFFFFF844 (PIOD), 0xFFFFFA44 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0: No effect. 1: Disables the Input Change interrupt on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 303 27.7.16 PIO Interrupt Mask Register Name: PIO_IMR Address: 0xFFFFF248 (PIOA), 0xFFFFF448 (PIOB), 0xFFFFF648 (PIOC), 0xFFFFF848 (PIOD), 0xFFFFFA48 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Mask 0: Input Change interrupt is disabled on the I/O line. 1: Input Change interrupt is enabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 304 27.7.17 PIO Interrupt Status Register Name: PIO_ISR Address: 0xFFFFF24C (PIOA), 0xFFFFF44C (PIOB), 0xFFFFF64C (PIOC), 0xFFFFF84C (PIOD), 0xFFFFFA4C (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Status 0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 305 27.7.18 PIO Multi-driver Enable Register Name: PIO_MDER Address: 0xFFFFF250 (PIOA), 0xFFFFF450 (PIOB), 0xFFFFF650 (PIOC), 0xFFFFF850 (PIOD), 0xFFFFFA50 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Multi-Drive Enable 0: No effect. 1: Enables multi-drive on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 306 27.7.19 PIO Multi-driver Disable Register Name: PIO_MDDR Address: 0xFFFFF254 (PIOA), 0xFFFFF454 (PIOB), 0xFFFFF654 (PIOC), 0xFFFFF854 (PIOD), 0xFFFFFA54 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Multi-Drive Disable 0: No effect. 1: Disables multi-drive on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 307 27.7.20 PIO Multi-driver Status Register Name: PIO_MDSR Address: 0xFFFFF258 (PIOA), 0xFFFFF458 (PIOB), 0xFFFFF658 (PIOC), 0xFFFFF858 (PIOD), 0xFFFFFA58 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi-Drive Status 0: The multi-drive is disabled on the I/O line. The pin is driven at high- and low-level. 1: The multi-drive is enabled on the I/O line. The pin is driven at low-level only. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 308 27.7.21 PIO Pull-Up Disable Register Name: PIO_PUDR Address: 0xFFFFF260 (PIOA), 0xFFFFF460 (PIOB), 0xFFFFF660 (PIOC), 0xFFFFF860 (PIOD), 0xFFFFFA60 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Pull-Up Disable 0: No effect. 1: Disables the pull-up resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 309 27.7.22 PIO Pull-Up Enable Register Name: PIO_PUER Address: 0xFFFFF264 (PIOA), 0xFFFFF464 (PIOB), 0xFFFFF664 (PIOC), 0xFFFFF864 (PIOD), 0xFFFFFA64 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Pull-Up Enable 0: No effect. 1: Enables the pull-up resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 310 27.7.23 PIO Pull-Up Status Register Name: PIO_PUSR Address: 0xFFFFF268 (PIOA), 0xFFFFF468 (PIOB), 0xFFFFF668 (PIOC), 0xFFFFF868 (PIOD), 0xFFFFFA68 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull-Up Status 0: Pull-up resistor is enabled on the I/O line. 1: Pull-up resistor is disabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 311 27.7.24 PIO Peripheral ABCD Select Register 1 Name: PIO_ABCDSR1 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Peripheral Select If the same bit is set to 0 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral B function. If the same bit is set to 1 in PIO_ABCDSR2: 0: Assigns the I/O line to the Peripheral C function. 1: Assigns the I/O line to the Peripheral D function. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 312 27.7.25 PIO Peripheral ABCD Select Register 2 Name: PIO_ABCDSR2 Access: Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Peripheral Select. If the same bit is set to 0 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral A function. 1: Assigns the I/O line to the Peripheral C function. If the same bit is set to 1 in PIO_ABCDSR1: 0: Assigns the I/O line to the Peripheral B function. 1: Assigns the I/O line to the Peripheral D function. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 313 27.7.26 PIO Input Filter Slow Clock Disable Register Name: PIO_IFSCDR Address: 0xFFFFF280 (PIOA), 0xFFFFF480 (PIOB), 0xFFFFF680 (PIOC), 0xFFFFF880 (PIOD), 0xFFFFFA80 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Clock Glitch Filtering Select 0: No effect. 1: The glitch filter is able to filter glitches with a duration < Tmck/2. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 314 27.7.27 PIO Input Filter Slow Clock Enable Register Name: PIO_IFSCER Address: 0xFFFFF284 (PIOA), 0xFFFFF484 (PIOB), 0xFFFFF684 (PIOC), 0xFFFFF884 (PIOD), 0xFFFFFA84 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Debouncing Filtering Select 0: No effect. 1: The debouncing filter is able to filter pulses with a duration < Tdiv_slclk/2. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 315 27.7.28 PIO Input Filter Slow Clock Status Register Name: PIO_IFSCSR Address: 0xFFFFF288 (PIOA), 0xFFFFF488 (PIOB), 0xFFFFF688 (PIOC), 0xFFFFF888 (PIOD), 0xFFFFFA88 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Glitch or Debouncing Filter Selection Status 0: The glitch filter is able to filter glitches with a duration < Tmck2. 1: The debouncing filter is able to filter pulses with a duration < Tdiv_slclk/2. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 316 27.7.29 PIO Slow Clock Divider Debouncing Register Name: PIO_SCDR Address: 0xFFFFF28C (PIOA), 0xFFFFF48C (PIOB), 0xFFFFF68C (PIOC), 0xFFFFF88C (PIOD), 0xFFFFFA8C (PIOE) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – 7 6 2 1 0 DIV 5 4 3 DIV • DIV: Slow Clock Divider Selection for Debouncing Tdiv_slclk = 2*(DIV+1)*Tslow_clock. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 317 27.7.30 PIO Pad Pull-Down Disable Register Name: PIO_PPDDR Address: 0xFFFFF290 (PIOA), 0xFFFFF490 (PIOB), 0xFFFFF690 (PIOC), 0xFFFFF890 (PIOD), 0xFFFFFA90 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Pull-Down Disable 0: No effect. 1: Disables the pull-down resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 318 27.7.31 PIO Pad Pull-Down Enable Register Name: PIO_PPDER Address: 0xFFFFF294 (PIOA), 0xFFFFF494 (PIOB), 0xFFFFF694 (PIOC), 0xFFFFF894 (PIOD), 0xFFFFFA94 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Pull-Down Enable 0: No effect. 1: Enables the pull-down resistor on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 319 27.7.32 PIO Pad Pull-Down Status Register Name: PIO_PPDSR Address: 0xFFFFF298 (PIOA), 0xFFFFF498 (PIOB), 0xFFFFF698 (PIOC), 0xFFFFF898 (PIOD), 0xFFFFFA98 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Pull-Down Status 0: Pull-down resistor is enabled on the I/O line. 1: Pull-down resistor is disabled on the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 320 27.7.33 PIO Output Write Enable Register Name: PIO_OWER Address: 0xFFFFF2A0 (PIOA), 0xFFFFF4A0 (PIOB), 0xFFFFF6A0 (PIOC), 0xFFFFF8A0 (PIOD), 0xFFFFFAA0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Output Write Enable 0: No effect. 1: Enables writing PIO_ODSR for the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 321 27.7.34 PIO Output Write Disable Register Name: PIO_OWDR Address: 0xFFFFF2A4 (PIOA), 0xFFFFF4A4 (PIOB), 0xFFFFF6A4 (PIOC), 0xFFFFF8A4 (PIOD), 0xFFFFFAA4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 This register can only be written if the WPEN bit is cleared in “PIO Write Protection Mode Register” . • P0-P31: Output Write Disable 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 322 27.7.35 PIO Output Write Status Register Name: PIO_OWSR Address: 0xFFFFF2A8 (PIOA), 0xFFFFF4A8 (PIOB), 0xFFFFF6A8 (PIOC), 0xFFFFF8A8 (PIOD), 0xFFFFFAA8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 323 27.7.36 PIO Additional Interrupt Modes Enable Register Name: PIO_AIMER Address: 0xFFFFF2B0 (PIOA), 0xFFFFF4B0 (PIOB), 0xFFFFF6B0 (PIOC), 0xFFFFF8B0 (PIOD), 0xFFFFFAB0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Enable 0: No effect. 1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 324 27.7.37 PIO Additional Interrupt Modes Disable Register Name: PIO_AIMDR Address: 0xFFFFF2B4 (PIOA), 0xFFFFF4B4 (PIOB), 0xFFFFF6B4 (PIOC), 0xFFFFF8B4 (PIOD), 0xFFFFFAB4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Additional Interrupt Modes Disable 0: No effect. 1: The interrupt mode is set to the default interrupt mode (both-edge detection). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 325 27.7.38 PIO Additional Interrupt Modes Mask Register Name: PIO_AIMMR Address: 0xFFFFF2B8 (PIOA), 0xFFFFF4B8 (PIOB), 0xFFFFF6B8 (PIOC), 0xFFFFF8B8 (PIOD), 0xFFFFFAB8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral CD Status 0: The interrupt source is a both-edge detection event. 1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 326 27.7.39 PIO Edge Select Register Name: PIO_ESR Address: 0xFFFFF2C0 (PIOA), 0xFFFFF4C0 (PIOB), 0xFFFFF6C0 (PIOC), 0xFFFFF8C0 (PIOD), 0xFFFFFAC0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge Interrupt Selection 0: No effect. 1: The interrupt source is an edge-detection event. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 327 27.7.40 PIO Level Select Register Name: PIO_LSR Address: 0xFFFFF2C4 (PIOA), 0xFFFFF4C4 (PIOB), 0xFFFFF6C4 (PIOC), 0xFFFFF8C4 (PIOD), 0xFFFFFAC4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Level Interrupt Selection 0: No effect. 1: The interrupt source is a level-detection event. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 328 27.7.41 PIO Edge/Level Status Register Name: PIO_ELSR Address: 0xFFFFF2C8 (PIOA), 0xFFFFF4C8 (PIOB), 0xFFFFF6C8 (PIOC), 0xFFFFF8C8 (PIOD), 0xFFFFFAC8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge/Level Interrupt Source Selection 0: The interrupt source is an edge-detection event. 1: The interrupt source is a level-detection event. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 329 27.7.42 PIO Falling Edge/Low-Level Select Register Name: PIO_FELLSR Address: 0xFFFFF2D0 (PIOA), 0xFFFFF4D0 (PIOB), 0xFFFFF6D0 (PIOC), 0xFFFFF8D0 (PIOD), 0xFFFFFAD0 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Falling Edge/Low-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a falling edge detection or low-level detection event, depending on PIO_ELSR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 330 27.7.43 PIO Rising Edge/High-Level Select Register Name: PIO_REHLSR Address: 0xFFFFF2D4 (PIOA), 0xFFFFF4D4 (PIOB), 0xFFFFF6D4 (PIOC), 0xFFFFF8D4 (PIOD), 0xFFFFFAD4 (PIOE) Access: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Rising Edge /High-Level Interrupt Selection 0: No effect. 1: The interrupt source is set to a rising edge detection or high-level detection event, depending on PIO_ELSR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 331 27.7.44 PIO Fall/Rise - Low/High Status Register Name: PIO_FRLHSR Address: 0xFFFFF2D8 (PIOA), 0xFFFFF4D8 (PIOB), 0xFFFFF6D8 (PIOC), 0xFFFFF8D8 (PIOD), 0xFFFFFAD8 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Edge /Level Interrupt Source Selection 0: The interrupt source is a falling edge detection (if PIO_ELSR = 0) or low-level detection event (if PIO_ELSR = 1). 1: The interrupt source is a rising edge detection (if PIO_ELSR = 0) or high-level detection event (if PIO_ELSR = 1). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 332 27.7.45 PIO Lock Status Register Name: PIO_LOCKSR Address: 0xFFFFF2E0 (PIOA), 0xFFFFF4E0 (PIOB), 0xFFFFF6E0 (PIOC), 0xFFFFF8E0 (PIOD), 0xFFFFFAE0 (PIOE) Access: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Lock Status 0: The I/O line is not locked. 1: The I/O line is locked. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 333 27.7.46 PIO Write Protection Mode Register Name: PIO_WPMR Address: 0xFFFFF2E4 (PIOA), 0xFFFFF4E4 (PIOB), 0xFFFFF6E4 (PIOC), 0xFFFFF8E4 (PIOD), 0xFFFFFAE4 (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 5 – – 4 – – – For more information on write-protecting registers, refer to Section 27.5.14 ”Register Write Protection”. • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x50494F (“PIO” in ASCII). See Section 27.5.14 ”Register Write Protection” for the list of registers that can be protected. • WPKEY: Write Protection Key. Value Name 0x50494F PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 334 27.7.47 PIO Write Protection Status Register Name: PIO_WPSR Address: 0xFFFFF2E8 (PIOA), 0xFFFFF4E8 (PIOB), 0xFFFFF6E8 (PIOC), 0xFFFFF8E8 (PIOD), 0xFFFFFAE8 (PIOE) Access: Read-only Reset: See Table 27-2 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 – WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – – – • WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the PIO_WPSR register. 1: A write protection violation has occurred since the last read of the PIO_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 335 27.7.48 PIO Schmitt Trigger Register Name: PIO_SCHMITT Address: 0xFFFFF300 (PIOA), 0xFFFFF500 (PIOB), 0xFFFFF700 (PIOC), 0xFFFFF900 (PIOD), 0xFFFFFB00 (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 28 27 26 25 24 SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24 23 22 21 20 19 18 17 16 SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16 15 14 13 12 11 10 9 8 SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8 7 6 5 4 3 2 1 0 SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0 • SCHMITTx [x=0..31]: Schmitt Trigger Control 0: Schmitt trigger is enabled. 1: Schmitt trigger is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 336 27.7.49 PIO I/O Drive Register 1 Name: PIO_DRIVER1 Address: 0xFFFFF318 (PIOA), 0xFFFFF518 (PIOB), 0xFFFFF718 (PIOC), 0xFFFFF918 (PIOD), 0xFFFFFB18 (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 LINE15 23 22 21 LINE11 15 28 14 20 13 19 6 12 5 18 11 17 9 8 LINE4 2 LINE1 16 LINE8 10 3 24 LINE12 LINE5 4 LINE2 25 LINE9 LINE6 LINE3 26 LINE13 LINE10 LINE7 7 27 LINE14 1 0 LINE0 • LINEx [x=0..15]: Drive of PIO Line x Value Name Description 0 LO_DRIVE Low drive 1 LO_DRIVE Low drive 2 ME_DRIVE Medium drive 3 HI_DRIVE High drive SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 337 27.7.50 PIO I/O Drive Register 2 Name: PIO_DRIVER2 Address: 0xFFFFF31C (PIOA), 0xFFFFF51C (PIOB), 0xFFFFF71C (PIOC), 0xFFFFF91C (PIOD), 0xFFFFFB1C (PIOE) Access: Read/Write Reset: See Table 27-2 31 30 29 LINE31 23 22 21 LINE27 15 27 14 20 13 19 6 12 5 18 11 17 9 8 LINE20 2 LINE17 16 LINE24 10 3 24 LINE28 LINE21 4 LINE18 25 LINE25 LINE22 LINE19 26 LINE29 LINE26 LINE23 7 28 LINE30 1 0 LINE16 • LINEx [x=16..31]: Drive of PIO line x Value Name Description 0 LO_DRIVE Low drive 1 LO_DRIVE Low drive 2 ME_DRIVE Medium drive 3 HI_DRIVE High drive SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 338 28. External Memories The product features:  Multiport DDR Controller (MPDDRC)  External Bus Interface (EBI) that embeds a NAND Flash controller and a Static Memory Controller (HSMC) Figure 28-1. External Memory Controllers MPDDRC Port 3 Port 2 Port 1 Port 0 LPDDR DDR2 LPDDR2-S4 Device EBI NAND Flash Controller NAND Flash Device Static Memory Controller Static Memory Device Bus Matrix  MPDDRC is a standalone multi-port DDRSDR controller. It supports only DDR2, LPDDR, and LPDDR2-S4 devices. Its user interface is located at 0xFFFFEA00.  HSMC supports Static Memories and MLC/SLC NAND Flashes. It embeds Multi-Bit ECC. Its user interface is located at 0xFFFFC000. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 339 28.1 MPDDRC Multi-port DDRSDR Controller 28.1.1 Description The DDR2 Controller is dedicated to 8-port DDR2/LPDDR/LPDDR2 support. Data transfers are performed through a 32bit data bus on one chip select. The Controller operates with 1.8V Power Supply for DDR2 and LP-DDR, 1.2V Power Supply for LP-DDR2. 28.1.2 Embedded Characteristics 28.1.2.1 DDR2/LPDDR/LPDDR2 Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Minimizes Transaction Latency.  Supports AHB Transfers:  DWord, Word, Half Word, Byte Access.  Supports Low-Power DDR2-SDRAM-S4, DDR2-SDRAM, Low-Power DDR1-SDRAM  Numerous Configurations Supported   2K, 4K, 8K, 16K Row Address Memory Parts  DDR2 with Four or Eight Internal Banks (DDR2_SDRAM/Low-Power DDR2-SDRAM)  DDR2/LPDDR with 32-bit Data Path  One Chip Select for DDR2/LPDDR Device (512 Mbytes Address Space) Programming Facilities  Multibank Ping-pong Access (Up to 4 or 8 Banks Opened at Same Time = Reduces Average Latency of Transactions)  Timing Parameters Specified by Software  Automatic Refresh Operation, Refresh Rate is Programmable  Automatic Update of DS, TCR and PASR Parameters (Low-power DDR-SDRAM Devices)  Energy-saving Capabilities  Power-up Initialization by Software  CAS Latency of 2, 3, 4, 5, 6 supported  Reset function supported (DDR2)  Auto Precharge Command Not Used  On Die Termination not supported  OCD mode not supported  Self-refresh, Power-down, Active Power-down and Deep Power-down Modes Supported SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 340 28.1.3 MPDDR Controller Block Diagram Figure 28-2. Organization of the MPDDRC MPDDRC DDR_A0-DDR_A13 DDR_D0-DDR_D31 DDR_CS Bus Matrix DDR_CKE DDR_RAS, DDR_CAS DDR2 LPDDR LPDDR2-S4 Controller AHB DDR_CLK,#DDR_CLK DDR_DQS[3:0] DDR_DQSN[3:0] DDR_DQM[3:0] DDR_WE DDR_BA[2:0] Address Decoders DDR_CALP DDR_CALN DDR_VREF User Interface APB SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 341 28.1.4 I/O Lines Description Table 28-1. DDR2 I/O Lines Description Name Function Type Active Level DDR2/LPDDR Controller VDDIODDR Power Supply of memory interface Input DDR_VREF Reference Voltage for DDR2 operations, typically 0.9V Input DDR_CALP Pad positive calibration reference for LP-DDR2 Input DDR_CALN Pad negative calibration reference for LP-DDR2 Input DDR_D0 - DDR_D31 Data Bus DDR_A0 - DDR_A13 Address Bus Output DDR_DQM0 - DDR_DQM3 Data Mask Output DDR_DQS0 - DDR_DQS3 Data Strobe Output DDR_DQSN0 DDR_DQSN3 Negative Data Strobe Output DDR_CS Chip Select Output DDR_CLK - DDR_CLK# DDR2 Differential Clock Output DDR_CKE Clock enable Output High DDR_RAS Row signal Output Low DDR_CAS Column signal Output Low DDR_WE Write enable Output Low DDR_BA0 - DDR_BA2 Bank Select Output I/O Low In LPDDR2 mode, DQS and DQSN are connected to the LPDDR2 memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 342 28.1.5 Product Dependencies The pins used for interfacing the DDR2 memory are not multiplexed with the PIO lines. Table 28-2. DDR2 I/O Lines Usage vs Operating Modes Signal Name DDR2 Mode LPDDR2 Mode LPDDR DDR_VREF VDDIODDR/2 VDDIODDR/2 VDDIODDR/2 DDR_CALP GND via 200Ω resistor GND via 240Ω resistor GND via 200Ω resistor DDR_CALN VDDIODDR via 200Ω resistor VDDIODDR via 240Ω resistor VDDIODDR via 200Ω resistor DDR_CK, DDR_CKN CLK and CLKN CLK and CLKN CLK and CLKN DDR_CKE CLKE CLKE CLKE DDR_CS CS CS CS DDR_BA[2..0] BA[2..0] BA[2..0] BA[2..0] DDR_WE WE CA2 WE DDR_RAS - DDR_CAS RAS, CAS CA0, CA1 RAS, CAS DDR_A[13..0] A[13:0] CAx, with x>2 A[13:0] DDR_D[31..0] D[31:0] D[31:0] D[31:0] DQS[3..0], DQSN[3..0] DQS[3:0] DQSN connected to DDR_VREF DQS[3:0] DQSN[3:0] DQS[3:0] DQSN connected to DDR_VREF DQM[3..0] DQM[3..0] DQM[3..0] DQM[3..0] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 343 28.1.6 Implementation Example The following hardware configuration is given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 28.1.6.1 2x16-bit DDR2 Hardware Configuration Figure 28-3. 2x16-bit DDR2 Hardware Configuration Software Configuration The following configuration has to be performed:  Initialize the DDR2 Controller depending on the DDR2 device and system bus frequency. The DDR2 initialization sequence is described in the sub-section “DDR2 Device Initialization” of the DDRSDRC section. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 344 28.1.6.2 2x16-bit LPDDR2 Hardware Configuration Figure 28-4. 2x16-bit LPDDR2 Hardware Configuration CAx LPDDR2 signals are to be connected as indicated in Table 28-3: Table 28-3. CAx LP-DDR2 Signal Connection DDR Controller Signal LP-DDR2 Signal RAS CA0 CAS CA1 WE CA2 DDR_A0 CA3 DDR_A1 CA4 DDR_A2 CA5 DDR_A3 CA6 DDR_A4 CA7 DDR_A5 CA8 DDR_A6 CA9 Higher addresses Higher CAs Software Configuration The following configuration has to be performed:  Initialize the DDR2 Controller depending on the LPDDR2 device and system bus frequency. The DDR2 initialization sequence is described in the sub-section “LPDDR2 Device Initialization” of the DDRSDRC section. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 345 28.2 External Bus Interface (EBI) 28.2.1 Description The External Bus Interface is designed to ensure the successful data transfer between several external devices and the ARM processor-based device. The External Bus Interface of the device consists of a Static Memory Controller (HSMC). This HSMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. The HSMC generates the signals that control the access to external memory devices or peripheral devices. It has 4 Chip Selects and a 26-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The HSMC can manage wait requests from external devices to extend the current access. The HSMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The HSMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. The HSMC includes programmable hardware error correcting code with one-bit error correction capability and supports two-bit error detection. In order to improve the overall system performance, the DATA phase of the transfer can be DMAassisted. The External Data Bus can be scrambled/unscrambled by means of user keys. The full description is available in the HSMC section. 28.2.1.1 External Bus Interface (EBI)  Integrates Two External Memory Controllers:  Static Memory Controller  SLC/MLC Nand Flash Controller  Additional logic for NAND Flash  Optional 16-bit External Data Bus  Up to 26-bit Address Bus (up to 64 MBytes linear per chip select)  Up to 4 chip selects, Configurable Assignment  NAND Flash chip select is programmable: 28.2.1.2 Static Memory Controller (HSMC)  64-MByte Address Space per Chip Select  8- or 16-bit Data Bus  Word, Halfword, Byte Transfers  Byte Write or Byte Select Lines  Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select  Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select  Programmable Data Float Time per Chip Select  External Data Bus Scrambling/Unscrambling Function  External Wait Request  Automatic Switch to Slow Clock Mode  NAND Flash Controller Supporting NAND Flash with Multiplexed Data/Address Buses  Supports SLC and MLC NAND Flash Technology  Programmable Timing on a per Chip Select Basis SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 346 28.2.1.3 NAND Flash Controller (NFC)  Programmable Flash Data Width 8 bits or 16 bits.  Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path.  Supports 1-bit Correction for a Page of 512, 1024, 2048 and 4096 Bytes with 8- or 16-bit Data Path.  Supports 1-bit Correction per 512 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path.  Supports 1-bit Correction per 256 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path.  Multibit Error Correcting Code (ECC)  ECC Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem (BCH) codes.  Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bits of errors per block.  Programmable block size: 512 Bytes or 1024 Bytes.  Programmable number of block per page: 1, 2, 4 or 8 blocks of data per page.  Programmable spare area size.  Supports spare area ECC protection.  Supports 8 kBytes page size using 1024 Bytes/block and 4 kBytes page size using 512 Bytes/block.  Multibit Error detection is interrupt driven.  Provides hardware acceleration for determining roots of polynomials defined over a finite field  Programmable finite Field GF(2^13) or GF(2^14)  Finds roots of error-locator polynomial.  Programmable finite Field GF(2^13) or GF(2^14)  Finds roots of error-locator polynomial. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 347 28.2.2 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 28.2.2.1 8-bit NAND Flash Hardware Configuration Software Configuration The following configuration has to be performed:  Select the NAND Flash Chip Select by setting the field CSID in NFCADDR_CMD register.  Configure the NFC and HSMC according to the used NAND Flash.  Enable the NFC with NFCEN bit in HSMC_CTRL register in HSMC User interface.  Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bits A21 and A22 during accesses.  Configure a PIO line as an input to manage the Ready/Busy signal.  Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 348 28.2.2.2 16-bit NAND Flash Hardware Configuration Software Configuration The software configuration is the same as for an 8-bit NAND Flash except for the data bus width programmed in the mode register of the Static Memory Controller. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 349 28.2.2.3 NOR Flash on NCS0 Hardware Configuration D[0..15] A[1..22] U1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 NRST NWE 3V3 NCS0 NRD 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 12 11 14 13 26 28 RESET WE WP VPP CE OE DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AT49BV6416 3V3 VCCQ 47 VCC 37 VSS VSS 46 27 C2 100NF C1 100NF TSOP48 PACKAGE Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 350 29. Multi-port DDR-SDRAM Controller (MPDDRC) 29.1 Description The Multi-port DDR-SDRAM Controller (MPDDRC) is a multi-port memory controller. It comprises four slave AHB interfaces. All simultaneous accesses (four independent AHB ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to DDR-SDRAM protocol. The MPDDRC extends the memory capabilities of a chip by providing the interface to the external 16-bit or 32-bit DDRSDRAM device. The page size support ranges from 2048 to 16384 and the number of columns from 256 to 4096. It supports dword (64-bits), word (32-bit), half-word (16-bit), and byte (8-bit) accesses. The MPDDRC supports a read or write burst length of eight locations. This enables the command and address bus to anticipate the next command, thus reducing latency imposed by the DDR-SDRAM protocol and improving the DDRSDRAM bandwidth. Moreover, MPDDRC keeps track of the active row in each bank, thus maximizing DDR-SDRAM performance, e.g., the application may be placed in one bank and data in other banks. To optimize performance, avoid accessing different rows in the same bank. The MPDDRC supports CAS latency of 2, 3 and optimizes the read access depending on the frequency. Self-refresh, power-down and deep power-down modes minimize the consumption of the DDR-SDRAM device. OCD (Off-chip Driver) and ODT (On-die Termination) modes are not supported. 29.2 Embedded Characteristics  Four advanced high performance bus (AHB) interfaces, management of all accesses maximizes memory bandwidth and minimizes transaction latency  Bus transfer: word, half word, byte access  Bus transfer: dword, word, half word, byte access  Supports low-power DDR2-SDRAM-S4 (LPDDR2), DDR2-SDRAM, low-power DDR1-SDRAM (LPDDR1)  Numerous configurations supported    2K, 4K, 8K, 16K row address memory parts  DDR-SDRAM with four or eight internal banks (DDR2-SDRAM/ low-power DDR2-SDRAM-S4)  DDR-SDRAM with 16-bit data path for system oriented word access  DDR-SDRAM with 32-bit data path for system oriented dword access  One chip select for SDRAM device (512-Mbyte address space)  One chip select for SDRAM device (256-Mbyte address space) Programming Facilities  Multibank ping-pong access (up to four or eight banks opened at the same time = reduced average latency of transactions)  Timing parameters specified by software  Automatic refresh operation, refresh rate is programmable  Automatic update of DS, TCR and PASR parameters (low-power DDR-SDRAM devices) Energy-saving capabilities  Self-refresh, Power-down, active power-down and deep power-down modes supported  DDR-SDRAM power-up initialization by software  CAS latency of 2,3 supported  Reset function supported (DDR2-SDRAM)  Auto-refresh per bank supported (low-power DDR2-SDRAM-S4)  Automatic adjust refresh rate (low-power DDR2-SDRAM-S4)  Auto-precharge command not used  OCD (Off-chip Driver) mode, ODT (On-die Termination) are not supported SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 351  29.3 Dynamic Scrambling with user key (no impact on bandwidth) MPDDRC Module Diagram Figure 29-1. MPDDRC Module Diagram AHB MPDDR Controller DDR Controller AHB Slave Interface 0 Input Stage Power Management clk/nclk AHB Slave Interface 1 ras, cas, we, cke Input Stage Output Stage AHB Slave Interface 2 Input Stage Memory Controller Finite State Machine SDRAM Signal Management Addr, DQM DDR-Devices DQS Arbiter Data odt AHB Slave Interface 3 Input Stage Asynchronous Timing Refresh Management Interconnect Matrix APB Interface APB MPDDRC is partitioned in two blocks (see Figure 29-1):  the Interconnect Matrix block that manages concurrent accesses on the AHB bus between four AHB masters and integrates an arbiter  the DDR controller that translates AHB requests (read/write) in the DDR-SDRAM protocol SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 352 29.4 Product Dependencies, Initialization Sequence 29.4.1 Low-power DDR1-SDRAM Initialization The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are initialized by the following sequence: 1. Program the memory device type in the MPDDRC Memory Device Register (MPDDRC_MD). 2. Program the features of the low-power DDR1-SDRAM device in the MPDDRC Configuration Register (number of columns, rows, banks, CAS latency and output drive strength) and in the MPDDRC Timing Parameter 0 Register/MPDDRC Timing Parameter 1 Register (asynchronous timing (TRC, TRAS, etc.)). 3. Program Temperature Compensated Self-refresh (TCR), Partial Array Self-refresh (PASR) and Drive Strength (DS) parameters in the MPDDRC Low-power Register. 4. A minimum pause of 200 µs is provided to precede any signal toggle. 5. A NOP command is issued to the low-power DDR1-SDRAM. Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command. The clocks which drive the low-power DDR1-SDRAM device are now enabled. 6. A NOP command is issued to the low-power DDR1-SDRAM. Program the NOP command in the MPDDRC_MR. The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command. A calibration request is now made to the I/O pad. 7. An All Banks Precharge command is issued to the low-power DDR1-SDRAM. Program All Banks Precharge command in the MPDDRC_MR. The application must write a two to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command. 8. Two auto-refresh (CBR) cycles are provided. Program the Auto Refresh command (CBR) in the MPDDRC_MR. The application must write a four to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR1-SDRAM location twice to acknowledge these commands. 9. An Extended Mode Register set (EMRS) cycle is issued to program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS). The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 Mbits SDRAM (12 rows, 9 columns, 4 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00800000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 4 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x08000000. Note: This address is given as an example only. The real address depends on implementation in the product. 10. A Mode Register set (MRS) cycle is issued to program parameters of the DDR1-SDRAM devices, in particular CAS latency and burst length. The application must write a three to the MODE field in the MPDDRC_MR and perform a write access to the low-power DDR1-SDRAM to acknowledge this command. The write address must be chosen so that signals BA[1:0] are set to 0. For example, the SDRAM write access should be done at the address: BASE_ADDRESS_DDR. 11. The application must enter Normal mode, write a zero to the MODE field in the MPDDRC_MR and perform a write access at any location in the low-power DDR1-SDRAM to acknowledge this command. 12. Perform a write access to any low-power DDR1-SDRAM address. 13. Write the refresh rate into the COUNT field in the MPDDRC Refresh Timer Register (MPDDRC_RTR): refresh rate = delay between refresh cycles. The low-power DDR1-SDRAM device requires a refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, MPDDRC_RTR must be set with (15.625 * 100 MHz) = 1562 i.e., 0x061A or (7.81 * 100 MHz) = 781 i.e., 0x030D. After initialization, the low-power DDR1-SDRAM device is fully functional. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 353 29.4.2 DDR2-SDRAM Initialization The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence: 1. Program the memory device type in the MPDDRC Memory Device Register. 2. Program features of the DDR2-SDRAM device in the MPDDRC Configuration Register (number of columns, rows, banks, CAS latency and output driver impedance control) and in the MPDDRC Timing Parameter 0 Register/MPDDRC Timing Parameter 1 Register (asynchronous timing (TRC, TRAS, etc.). 3. A NOP command is issued to the DDR2-SDRAM. Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. The clocks which drive the DDR2-SDRAM device are now enabled. 4. A minimum pause of 200 µs is provided to precede any signal toggle. 5. A NOP command is issued to the DDR2-SDRAM. Program the NOP command in the MPDDRC_MR. The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. CKE is now driven high. 6. An All Banks Precharge command is issued to the DDR2-SDRAM. Program All Banks Precharge command in the MPDDRC_MR. The application must write a two to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. 7. An Extended Mode Register set (EMRS2) cycle is issued to choose between commercial or high temperature operations. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and signal BA[0] is set to 0. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00800000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x08000000. Note: This address is given as an example only. The real address depends on implementation in the product. 8. An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode Register to 0. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 1 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00C00000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x0C000000. 9. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL and to program D.I.C. (Output Driver Impedance Control). The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00400000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x04000000. 10. An additional 200 cycles of clock are required for locking DLL 11. Write a one to the DLL bit (enable DLL reset) in the MPDDRC Configuration Register (MPDDRC_CR). 12. A Mode Register set (MRS) cycle is issued to reset DLL. The application must write a three to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signals BA[1:0] are set to 0. For example, the SDRAM write access should be done at the address: BASE_ADDRESS_DDR. 13. An All Banks Precharge command is issued to the DDR2-SDRAM. Program the All Banks Precharge command in the MPDDRC_MR. The application must write a two to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2-SDRAM address to acknowledge this command. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 354 14. Two auto-refresh (CBR) cycles are provided. Program the Auto Refresh command (CBR) in the MPDDRC_MR. The application must write a four to the MODE field in the MPDDRC_MR. Perform a write access to any DDR2SDRAM location twice to acknowledge these commands. 15. Write a zero to the DLL bit (disable DLL reset) in the MPDDRC_CR. 16. A Mode Register set (MRS) cycle is issued to program parameters of the DDR2-SDRAM device, in particular CAS latency and burst length, and to disable DLL reset. The application must write a three to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signals BA[1:0] are set to 0. For example, with a 16-bit 128 Mbits SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address: BASE_ADDRESS_DDR. 17. Write a seven to the OCD field (default OCD calibration) in the MPDDRC_CR. 18. An Extended Mode Register set (EMRS1) cycle is issued to the default OCD value. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks), the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00400000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x04000000. 19. Write a zero to the OCD field (exit OCD calibration mode) in the MPDDRC_CR. 20. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The application must write a five to the MODE field in the MPDDRC_MR and perform a write access to the DDR2-SDRAM to acknowledge this command. The write address must be chosen so that signal BA[1] is set to 0 and signal BA[0] is set to 1. For example, with a 16-bit 128 Mbits DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x00400000. For example, with a 32-bit 1 Gbit SDRAM (14 rows, 10 columns, 8 banks), the SDRAM write access should be done at the address: BASE_ADDRESS_DDR + 0x04000000. 21. A Normal mode command is provided. Program the normal mode in the MPDDRC_MR and perform a write access to any DDR2-SDRAM address to acknowledge this command. 22. Perform a write access to any DDR2-SDRAM address. 23. Write the refresh rate into the COUNT field in the MPDDRC Refresh Timer Register (MPDDRC_RTR): refresh rate = delay between refresh cycles. The DDR2-SDRAM device requires a refresh every 15.625 µs or 7.81 µs. With a 133 MHz frequency, the COUNT field in the MPDDRC_RTR must be set with (15.625 * 133 MHz) = 2079 i.e., 0x081F or (7.81 * 133 MHz) = 1039 i.e., 0x040F. After initialization, the DDR2-SDRAM devices are fully functional. 29.4.3 Low-power DDR2-SDRAM Initialization The initialization sequence is generated by software. The low-power DDR2-SDRAM devices are initialized by the following sequence: 1. Program the memory device type in the MPDDRC Memory Device Register. 2. Program features of the low-power DDR2-SDRAM device into and in the MPDDRC Configuration Register (number of columns, rows, banks, CAS latency and output drive strength) and in the MPDDRC Timing Parameter 0 Register/MPDDRC Timing Parameter 0 Register (asynchronous timing, TRC, TRAS, etc.). 3. A NOP command is issued to the low-power DDR2-SDRAM. Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR). The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The clocks which drive the Low-power DDR2-SDRAM devices are now enabled. 4. A minimum pause of 100 ns must be observed to precede any signal toggle. 5. A NOP command is issued to the low-power DDR2-SDRAM. Program the NOP command in the MPDDRC_MR. The application must write a one to the MODE field in the MPDDRC_MR. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. CKE is now driven high. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 355 6. A minimum pause of 200 µs must be satisfied before a Reset command. 7. A Reset command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a 63 to the MRS field. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Reset command is now issued. 8. A minimum pause of 1 µs must be satisfied before any commands. 9. A Mode Register Read command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and must write a zero to the MRS field. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Read command is now issued. 10. A minimum pause of 10 µs must be satisfied before any commands. 11. A Calibration command is issued to the low-power DDR2-SDRAM. Program the type of calibration in the MPDDRC Configuration Register (MPDDRC_CR): set the ZQ field to the RESET value. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a 10 to the MRS field. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The ZQ Calibration command is now issued. Program the type of calibration in the MPDDRC_CR: set the ZQ field to the SHORT value. 12. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a one to the MRS field. The Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular burst length. Perform a write access to any low-power DDR2SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 13. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a two to the MRS field. The Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular CAS latency. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 14. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR, configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a three to the MRS field. The Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular Drive Strength and Slew Rate. Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 15. A Mode Register Write command is issued to the low-power DDR2-SDRAM. In the MPDDRC_MR configure the MODE field to the LPDDR2_CMD value and configure the MRS field. The application must write a seven to the MODE field and a 16 to the MRS field. Mode Register Write command cycle is issued to program parameters of the low-power DDR2-SDRAM device, in particular Partial Array Self Refresh (PASR). Perform a write access to any low-power DDR2-SDRAM address to acknowledge this command. The Mode Register Write command is now issued. 16. Write the refresh rate into the COUNT field in the MPDDRC Refresh Timer Register (MPDDRC_RTR): refresh rate = delay between refresh cycles. The low-power DDR2-SDRAM device requires a refresh every 7.81 µs. With a 133 MHz frequency, the COUNT field in the MPDDRC_RTR must be set with (7.81 * 133 MHz) = 1039 i.e., 0x040F. After initialization, the low-power DDR2-SDRAM devices are fully functional. 29.5 Functional Description 29.5.1 DDR-SDRAM Controller Write Cycle The MPDDRC provides burst access or single access in normal mode (MODE = 0). Whatever the access type, the MPDDRC keeps track of the active row in each bank, thus maximizing performance. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 356 The DDR-SDRAM device is programmed with a burst length (bl) equal to 8. This determines the length of a sequential data input by the write command that is set to 8. The latency from write command to data input is fixed to 1 in case of the DDR1-SDRAM devices, and it is fixed to 2 in case of DDR2-SDRAM depending on the programmed latency. To initiate a single access, the MPDDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a write command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a write command. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) command. As the burst length is fixed to 8, in case of single access, it has to stop the burst, otherwise seven invalid values may be written. In case of the DDR-SDRAM device, the burst stop command is not supported for the burst write operation. Thus, in order to interrupt the write operation, the DM (data mask) input signal must be set to 1 to mask invalid data (see Figure 29-2 on page 357 and Figure 29-4 on page 358), and DQS must continue to toggle. To initiate a burst access, the MPDDRC controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the DDR-SDRAM device is carried out. If the next access is a write non-sequential access, then an automatic access break is inserted, the MPDDRC generates a precharge command, activates the new row and initiates a write command. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) commands. For the definition of timing parameters, please refer to Section 29.8.4 “MPDDRC Timing Parameter 0 Register”. Write accesses to the DDR-SDRAM device are burst oriented and the burst length is programmed to 8. It determines the maximum number of column locations that can be accessed for a given write command. When the write command is issued, eight columns are selected. All accesses for that burst take place within these eight columns, thus the burst wraps within these eight columns if a boundary is reached. These eight columns are selected by addr[13:3]. addr[2:0] is used to select the starting location within the block. In case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the DDRSDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next access is at 0x00. Since the boundary is reached, the burst is wrapped. The MPDDRC takes this feature of the DDR-SDRAM device into account. In case of a transfer starting at address 0x04/0x08/0x0C or starting at address 0x10/0x14/0x18/0x1C, two write commands are issued to avoid wrapping when the boundary is reached. The last write command is subject to DM input logic level. If DM is registered high, the corresponding data input is ignored and the write access is not done. This avoids additional writing. Figure 29-2. Single Write Access, Row Closed, DDR-SDRAM Devices SDCLK Row a A[12:0] COMMAND BA[1:0] NOP PRCHG NOP ACT col a NOP WRITE NOP 00 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da t RP = 2 3 Db t RCD = 2 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 357 Figure 29-3. Single Write Access, Row Closed, DDR2-SDRAM Devices SDCLK Row a A[12:0] COMMAND NOP PRCHG NOP col a ACT NOP WRITE NOP 00 BA[1:0] DQS[1:0] DM[1:0] 3 D[15:0] 0 Da t RP = 2 3 Db t RCD = 2 Figure 29-4. Burst Write Access, Row Closed, DDR-SDRAM Devices SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da t RP = 2 Db Dc Dd 3 De Df Dg Dh t RCD = 2 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 358 Figure 29-5. Burst Write Access, Row Closed, DDR2-SDRAM Devices SDCLK A[12:0] Row a COMMAND BA[1:0] NOP PRCHG NOP col a ACT NOP WRITE NOP 0 DQS[1:0] DM[1:0] 3 0 D [15:0] Da t RP = 2 Db Dc Dd 3 De Df Dg Dh t RCD = 2 A write command can be followed by a read command. To avoid breaking the current write burst, tWTR/tWRD (bl/2 + 2 = 6 cycles) should be met. See Figure 29-6 on page 359. Figure 29-6. Write Command Followed by a Read Command without Burst Write Interrupt, DDR-SDRAM Devices SDCLK A[12:0] col a COMMAND BA[1:0] NOP col a WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] D[15:0] 3 0 Da 3 Db Dc Dd De Df Dg Dh Da Db t WRD = bl/2 + 2 = 8/2 + 2 = 6 t WR =1 In case of a single write access, write operation should be interrupted by a read access but DM must be input 1 cycle prior to the read command to avoid writing invalid data. See Figure 29-7 on page 360. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 359 Figure 29-7. SINGLE Write Access followed by a Read Access, DDR-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] col a Row a NOP PRCHG NOP ACT NOP WRITE NOP READ BST NOP 0 DQS[1:0] DM[1:0] 3 0 D[15:0] 3 Da Db Db Da Data masked Figure 29-8. SINGLE Write Access followed by a Read Access, DDR2-SDRAM Devices SDCLK A[12:0] Row a COMMAND NOP PRCHG NOP BA[1:0] col a ACT NOP WRITE NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] 0 Da 3 Da Db Db Data masked t WTR 29.5.2 DDR-SDRAM Controller Read Cycle The MPDDRC provides burst access or single access in normal mode (mode = 0). Whatever the access type, the MPDDRC keeps track of the active row in each bank, thus maximizing performance of the MPDDRC. The DDR-SDRAM devices are programmed with a burst length equal to 8 which determines the length of a sequential data output by the read command that is set to 8. The latency from read command to data output is equal to 2, 3. This value is programmed during the initialization phase (see Section 29.4 “Product Dependencies, Initialization Sequence”). To initiate a single access, the MPDDRC checks if the page access is already open. If row/bank addresses match with the previous row/bank addresses, the controller generates a read command. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/read (tRCD) command. After a read command, additional wait states are generated to comply with CAS latency. The MPDDRC supports a CAS latency of two to three (2 to 3 clocks delay). As the burst length is fixed to 8, in case of a single access or a burst access inferior to 8 data requests, it has to stop the burst, otherwise an additional seven or X values could be read. The Burst Stop command (BST) is used to stop output during a burst read. If the DDR2-SDRAM Burst Stop command is not supported by the JEDEC standard, in a single read access, an additional seven unwanted data will be read. To initiate a burst access, the MPDDRC checks the transfer type signal. If the next accesses are sequential read accesses, reading to the SDRAM device is carried out. If the next access is a read non-sequential access, then an SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 360 automatic page break can be inserted. If the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. If page access is already open, a read command is generated. To comply with DDR-SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/read (tRCD) commands. The MPDDRC supports a CAS latency of two to three (2 to 3 clocks delay). During this delay, the controller uses internal signals to anticipate the next access and improve the performance of the controller. Depending on the latency, the MPDDRC anticipates two to three read accesses. In case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and depending on the latency, the MPDDRC anticipates two to three read accesses. For the definition of timing parameters, refer to Section 29.8.3 “MPDDRC Configuration Register”. Read accesses to the DDR-SDRAM are burst oriented and the burst length is programmed to 8. The burst length determines the maximum number of column locations that can be accessed for a given read command. When the read command is issued, eight columns are selected. All accesses for that burst take place within these eight columns, meaning that the burst wraps within these eight columns if the boundary is reached. These eight columns are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block. In case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the 16-byte boundary of the DDRSDRAM device. For example, when a transfer (INCR4) starts at address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next access is 0x00. Since the boundary is reached, the burst wraps. The MPDDRC takes into account this feature of the SDRAM device. In case of the DDR-SDRAM device, transfers start at address 0x04/0x08/0x0C. Two read commands are issued to avoid wrapping when the boundary is reached. The last read command may generate additional reading (1 read cmd = 4 DDR words). To avoid additional reading, it is possible to use the burst stop command to truncate the read burst and to decrease power consumption. The DDR2-SDRAM devices do not support the burst stop command. Figure 29-9. Single Read Access, Row Closed, Latency = 2, DDR-SDRAM Devices SDCLK A[12:0] COMMAND Row a NOP BA[1:0] 0 DM[3:0] 3 PRCHG NOP ACT col a NOP D[31:0] READ BST NOP DaDb t RP t RCD Latency = 2 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 361 Figure 29-10.Single Read Access, Row Closed, Latency = 3, DDR2-SDRAM Devices SDCLK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP Row a Col a ACT NOP READ 0 DQS[1] DQS[0] DM[1:0] 3 D[15:0] Da t RP t RCD Db Latency = 3 Figure 29-11.Burst Read Access, Latency = 2, DDR-SDRAM Devices SDCLKN SDCLK A[12:0] COMMAND BA[1:0] Col a NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Dc Db Dd De Df Dg Dh Latency = 2 Figure 29-12.Burst Read Access, Latency = 3, DDR2-SDRAM Devices SDCLKN SDCLK A[12:0] COMMAND BA[1:0] Col a NOP READ NOP 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Dc Dd De Df Dg Dh Latency = 3 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 362 29.5.2.1 All Banks Auto Refresh The All Banks Auto Refresh command performs a refresh operation on all banks. An auto refresh command is used to refresh the MPDDRC. Refresh addresses are generated internally by the DDR-SDRAM device and incremented after each auto-refresh automatically. The MPDDRC generates these auto-refresh commands periodically. A timer is loaded in the MPDDRC_RTR with the value that indicates the number of clock cycles between refresh cycles (see Section 29.8.2 “MPDDRC Refresh Timer Register”). When the MPDDRC initiates a refresh of the DDR-SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the DDR-SDRAM device, the slave indicates that the device is busy. A refresh request does not interrupt a burst transfer in progress. This feature is activated by setting Per-bank Refresh bit (REF_PB) to 0 in the MPDDRC_RTR (see Section 29.8.2 “MPDDRC Refresh Timer Register”). 29.5.2.2 Per-bank Auto Refresh The low-power DDR2-SDRAM embeds a new Per-bank Refresh command which performs a refresh operation on the bank scheduled by the bank counter in the memory device. The Per-bank Refresh command is executed in a fixed sequence order of round-robin type: “0-1-2-3-4-5-6-7-0-1-...”. The bank counter is automatically cleared upon issuing a RESET command or when exiting from self-refresh mode, in order to ensure the synchronism between SDRAM memory device and the MPDDRC controller. The bank addressing for the Per-bank Refresh count is the same as established in the Single-bank Precharge command. This feature is activated by setting the Per-bank Refresh bit (REF_PB) to 1 in the MPDDRC_RTR (see Section 29.8.2 “MPDDRC Refresh Timer Register”). This feature masks the latency due to the refresh procedure. The target bank is inaccessible during the Per-bank Refresh cycle period (tRFCpb), however other banks within the device are accessible and may be addressed during the “Per-bank Refresh” cycle. During the REFpb operation, any bank other than the one being refreshed can be maintained in active state or accessed by a read or a write command. When the “Per-bank Refresh” cycle is completed, the affected bank will be in idle state. 29.5.2.3 Adjust Auto Refresh Rate The low-power DDR2-SDRAM embeds an internal register, Mode Register 19 (Refresh Mode). The content of this register allows to adjust the interval of auto-refresh operations according to temperature variation. This feature is activated by setting the Adjust Refresh bit [ADJ_REF] to 1 in the MPDDRC_RTR (see Section 29.8.2 “MPDDRC Refresh Timer Register”). When this feature is enabled, a mode register read command (MRR) is performed every 16 * tREFI (average time between REFRESH commands). Depending on the read value, the auto refresh interval will be modified. In case of high temperature, the interval is reduced and in case of low temperature, the interval is increased. 29.5.3 Power Management 29.5.3.1 Self-refresh Mode This mode is activated by writing a one to the Low-power Command bit (LPCB) in the MPDDRC_LPR register. Self-refresh mode is used in power-down mode, i.e., when no access to the DDR-SDRAM device is possible. In this case, power consumption is very low. In self-refresh mode, the DDR-SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto refresh cycles. During self-refresh period CKE is driven low. As soon as the DDR-SDRAM device is selected, the MPDDRC provides a sequence of commands and exits self-refresh mode. The MPDDRC re-enables self-refresh mode as soon as the DDR-SDRAM device is not selected. It is possible to define when self-refresh mode is to be enabled by configuring the TIMEOUT field in the MPDDRC_LPR register: 0: Self-refresh mode is enabled as soon as the DDR-SDRAM device is not selected. 1: Self-refresh mode is enabled 64 clock cycles after completion of the last access. 2: Self-refresh mode is enabled 128 clock cycles after completion of the last access. This controller also interfaces the low-power DDR-SDRAM. To optimize power consumption, the Low Power DDR SDRAM provides programmable self-refresh options comprised of Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array). Disabled banks are not refreshed in self-refresh mode. This feature permits to reduce the self-refresh current. In case of low-power DDR1-SDRAM, the Extended Mode register controls this feature. It includes Temperature Compensated Selfrefresh (TSCR) and Partial Array Self-refresh (PASR) parameters and the drive strength (DS) (see Section 29.8.7 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 363 “MPDDRC Low-power Register”). In case of low-power DDR2-SDRAM, the mode registers 16 and 17 control this feature, including PASR Bank Mask (BK_MASK) and PASR Segment Mask (SEG_MASK) parameters and drives strength (DS) (see Section 29.8.8 “MPDDRC Low-power DDR2 Low-power Register” on page 388). These parameters are set during the initialization phase. After initialization, as soon as the PASR/DS/TCSR fields or BK_MASK/SEG_MASK/DS are modified, the memory device Extended Mode Register or Mode Registers 3/16/17 are automatically accessed. Thus if MPDDRC does not share an external bus with another controller, PASR/DS/TCSR and BK_MASK/SEG_MASK/DS bits are updated before entering self-refresh mode or during a refresh command. If MPDDRC does share an external bus with another controller, PASR/DS/TCSR and BK_MASK/SEG_MASK/DS bits are also updated during a pending read or write access. This type of update is a function of the UPD_MR bit (see Section 29.8.7 “MPDDRC Low-power Register”). The low-power DDR1-SDRAM must remain in self-refresh mode during the minimum of TRFC periods (see Section 29.8.5 “MPDDRC Timing Parameter 1 Register”), and may remain in self-refresh mode for an indefinite period. The DDR2-SDRAM must remain in self-refresh mode during the minimum of tCKE periods (see the memory device datasheet), and may remain in self-refresh mode for an indefinite period. The low-power DDR2-SDRAM must remain in self-refresh mode for the minimum of tCKESR periods (see the memory device datasheet) and may remain in self-refresh mode for an indefinite period. Figure 29-13.Self-refresh Mode Entry, Time-out = 0 SDCK A[12:0] NOP READ COMMAND BST NOP PRCHG NOP ARFSH NOP CKE BA[1:0] 0 DQS[0:1] DM[1:0] 3 D[15:0] Da Db t RP Enter Self-refresh Mode Figure 29-14.Self-refresh Mode Entry, Time-out = 1 or 2 SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP ARFSH NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] D[15:0] 3 Da Db 64 or 128 Wait states t RP Enter Self-refresh Mode SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 364 Figure 29-15.Self-refresh Mode Exit SDCLK A[12:0] COMMAND NOP VALID NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Exit Self-refresh Mode Clock must be stable before exiting self-refresh mode t XNRD / t XSRD t XSR (DDR device) (Low-power DDR device) 29.5.3.2 Power-down Mode This mode is activated by writing a 10 to the Low-power Command bit (LPCB). Power-down mode is used when no access to the DDR-SDRAM device is possible. In this mode, power consumption is greater than in self-refresh mode. This state is similar to normal mode (no low-power mode/no self-refresh mode), but the CKE pin is low and the input and output buffers are deactivated as soon the DDR-SDRAM device is no longer accessible. In contrast to self-refresh mode, the DDR-SDRAM device cannot remain in low-power mode longer than one refresh period (64 ms). As no auto-refresh operations are performed in this mode, the MPDDRC carries out the refresh operation. For DDR1-SDRAM, in order to exit low-power mode, a NOP command is required. For the low-power DDR1SDRAM devices, a NOP command must be generated for a minimum period defined in the TXP field of the MPDDRC Timing Parameter 1 Register. In addition, low-power DDR-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum period corresponding to tCKE (see the memory device datasheet). The exit procedure is faster than in self-refresh mode. See Figure 29-16 on page 366. The MPDDRC returns to powerdown mode as soon as the DDR-SDRAM device is not selected. It is possible to define when power-down mode is enabled by configuring the TIMEOUT field in the MPDDRC_LPR register: 0: Power-down mode is enabled as soon as the DDR-SDRAM device is not selected. 1: Power-down mode is enabled 64 clock cycles after completion of the last access. 2: Power-down mode is enabled 128 clock cycles after completion of the last access. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 365 Figure 29-16.Power-down Entry/Exit, Time-out = 0 SDCK A[12:0] COMMAND READ BST NOP READ CKE BA[1:0] 0 DQS[1:0] DM[1:0] 3 D[15:0] Da Db Exit Power-down Mode Enter Power-down Mode 29.5.3.3 Deep Power-down Mode The deep power-down mode is a feature of low-power DDR-SDRAM. When this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. Deep power-down mode is activated by writing a three to the Low-power Command bit (LPCB). When this mode is enabled, the MPDDRC leaves normal mode (mode = 0) and the controller is frozen. Before enabling this mode, the user must assume there is no access in progress. To exit deep power-down mode, the Low-power Command bit (LPCB) must be written to zero and the initialization sequence must be generated by software. See Section 29.4.1 “Low-power DDR1-SDRAM Initialization” or Section 29.4.3 “Low-power DDR2-SDRAM Initialization”. Figure 29-17.Deep Power-down Mode Entry SDCLK A[12:0] COMMAND NOP READ BST NOP PRCHG NOP DEEPOWER NOP CKE BA[1:0] 0 DQS[1:0] DM[1:0] D[15:0] 3 Da Db t RP Enter Deep Power-down Mode 29.5.3.4 Change Frequency During Power-down Mode with Low-power DDR2-SDRAM Devices To change frequency, power-down mode must be activated by writing a two to the Low-power Command bit (LPCB) and a one to the Change Frequency Command bit (CHG_FR) in the MPDDRC Low-power Register. Once the low-power DDR2-SDRAM is in precharge power-down mode, the clock frequency may change. The device input clock frequency changes only within minimum and maximum operating frequencies as specified by low-power DDR2-SDRAM providers. Once the input clock frequency is changed, new stable clocks must be provided to the device before exiting from the precharge power-down mode. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 366 Depending on the new clock frequency, the user can change the CAS latency in the user interface. (See “CAS: CAS Latency” on page 378.) It is recommended to check that no access is in progress. Once the controller detects a change of latency during the change frequency procedure, a Load Mode Register command is performed. During a change frequency procedure, the Change Frequency Command bit (CHG_FR) is set to 0 automatically. 29.5.3.5 Reset Mode The reset mode is a feature of DDR2-SDRAM. This mode is activated by writing a three to the Low-power Command bit (LPCB) and a one to the Clock Frozen Command bit (CLK_FR) in the MPDDRC Low-power Register. When this mode is enabled, the MPDDRC leaves normal mode (mode = 0) and the controller is frozen. Before enabling this mode, the user must assume there is no access in progress. To exit reset mode, the Low-power Command bit (LPCB) must be written to zero, the Clock Frozen Command bit (CLK_FR) must be written to zero and the initialization sequence must be generated by software. (See Section 29.4.2 “DDR2-SDRAM Initialization”). 29.5.4 Multi-port Functionality The DDR-SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing system performance. An access to DDR-SDRAM is performed if banks and rows are open (or active). To activate a row in a particular bank, the last open row must be deactivated and a new row must be open. Two DDR-SDRAM commands must be performed to open a bank: Precharge command and Activate command with respect to tRP timing. Before performing a read or write command, tRCD timing must be checked. This operation generates a significant bandwidth loss (see Figure 29-18.). Figure 29-18.tRP and tRCD Timings SDCK A[12:0] COMMAND BA[1:0] NOP PRCHG NOP ACT NOP READ BST NOP 0 DQS[1:0] DM1:0] 3 D[15:0] Da t RP t RCD Db Latency = 2 4 cycles before performing a read command SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 367 The multi-port controller is designed to mask these timings and thus improve the bandwidth of the system. The MPDDRC is a multi-port controller whereby four masters can simultaneously reach the controller. This feature improves the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus anticipate the commands that follow, Precharge command and Activate command in bank X during the current access in bank Y. This masks tRP and tRCD timings (see Figure 29-19). In the best case, all accesses are done as if the banks and rows were already open. The best condition is met when the four masters work in different banks. In the case of four simultaneous read accesses, when the four or eight banks and associated rows are open, the controller reads with a continuous flow and masks the CAS latency for each access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (CAS latency) before the end of the current access. The arbitration scheme must be changed since the round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus a master with a high priority arises before the end of the current access, then this master will not be serviced. Figure 29-19.Anticipate Precharge/Activate Command in Bank 2 during Read Access in Bank 1 SDCK A[12:0] COMMAND BA[1:0] NOP 0 READ PRECH 1 NOP ACT READ 2 NOP 1 DQS[1:0] DM1:0] 3 D[15:0] Da Db Dc Dd De Df Dg Dh Di Dj Dk Dl t RP Anticipate command, Precharge/Active Bank 2 Read Access in Bank 1 The arbitration mechanism reduces latency when a conflict occurs, that is when two or more masters try to access the DDR-SDRAM device at the same time. The arbitration type is round-robin arbitration. This algorithm dispatches requests from different masters to the DDRSDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput for the DDR-SDRAM device, arbitration must only take place during the following cycles: 1. Idle cycles: when no master is connected to the DDR-SDRAM device. 2. Single cycles: when a slave is currently performing a single access. 3. End of Burst cycles: when the current cycle is the last cycle of a burst transfer. 4. 29.6  For bursts of defined length, predicted end of burst matches the size of the transfer.  For bursts of undefined length, predicted end of burst is generated at the end of each four-beat boundary inside the INCR transfer. Anticipated Access: when an anticipated read access is done while the current access is not complete, the arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme. Scrambling/Unscrambling Function The external data bus can be scrambled in order to prevent intellectual property data located in off-chip memories from being easily recovered by analyzing data at the package pin level of either the microcontroller or the memory device. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 368 The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling method depends on two user-configurable key registers, MPDDRC_KEY1 in the “MPDDRC OCMS KEY1 Register” and MPDDRC_KEY2 in the “MPDDRC OCMS KEY2 Register” . These key registers are only accessible in write mode. The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. The scrambling/unscrambling function can be enabled or disabled by programming the “MPDDRC OCMS Register” . 29.7 Software Interface/SDRAM Organization, Address Mapping The DDR-SDRAM address space is organized into banks, rows and columns. The MPDDRC maps different memory types depending on values set in the MPDDRC Configuration Register (see Section 29.8.3 “MPDDRC Configuration Register”). The tables that follow illustrate the relation between CPU addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths. The MPDDRC supports address mapping in linear mode. Sequential mode is a method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. Interleaved mode is a method for address mapping where banks alternate at each SDRAM end page of the current bank. The MPDDRC makes the DDR-SDRAM device access protocol transparent to the user. The tables that follow illustrate the DDR-SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated. 29.7.1 DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width Table 29-1. Sequential Mapping for DDR-SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 Bk[1:0] 15 14 13 12 11 10 9 8 7 Row[10:0] Bk[1:0] 4 3 2 1 M0 M0 Column[10:0] Row[10:0] 0 M0 Column[9:0] Row[10:0] Bk[1:0] 5 Column[8:0] Row[10:0] Bk[1:0] 6 M0 Column[11:0] Table 29-2. Interleaved Mapping for DDR-SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[10:0] Row[10:0] 10 Bk[1:0] Row[10:0] Row[10:0] 11 Bk[1:0] Bk[1:0] Bk[1:0] 9 8 7 6 5 4 3 2 Column[8:0] Column[9:0] Column[10:0] 1 0 M0 M0 M0 M0 Column[11:0] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 369 Table 29-3. Sequential Mapping for DDR-SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 7 Row[11:0] Bk[1:0] 4 3 2 1 M0 M0 Column[10:0] Row[11:0] 0 M0 Column[9:0] Row[11:0] Bk[1:0] 5 Column[8:0] Row[11:0] Bk[1:0] 6 M0 Column[11:0] Table 29-4. Interleaved Mapping for DDR-SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[11:0] 11 10 9 8 7 Bk[1:0] Row[11:0] 4 3 2 1 M0 M0 Column[10:0] Bk[1:0] 0 M0 Column[9:0] Bk[1:0] Row[11:0] 5 Column[8:0] Bk[1:0] Row[11:0] 6 M0 Column[11:0] Table 29-5. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 7 Row[12:0] Bk[1:0] 4 3 2 1 M0 M0 Column[10:0] Row[12:0] 0 M0 Column[9:0] Row[12:0] Bk[1:0] 5 Column[8:0] Row[12:0] Bk[1:0] 6 M0 Column[11:0] Table 29-6. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[12:0] 11 10 9 8 7 Bk[1:0] Row[12:0] 4 3 2 1 M0 M0 Column[10:0] Bk[1:0] 0 M0 Column[9:0] Bk[1:0] Row[12:0] 5 Column[8:0] Bk[1:0] Row[12:0] 6 M0 Column[11:0] Table 29-7. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows, 512/1024/2048 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 Bk[1:0] Bk[1:0] Bk[1:0] 17 16 Row[13:0] Row[13:0] Row[13:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Column[8:0] Column[9:0] Column[10:0] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1 0 M0 M0 M0 370 Table 29-8. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows, 512/1024/2048 Columns, 4 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 Row[13:0] 11 10 9 8 7 Bk[1:0] Row[13:0] 5 4 3 2 1 M0 Column[9:0] Bk[1:0] 0 M0 Column[8:0] Bk[1:0] Row[13:0] 6 M0 Column[10:0] Table 29-9. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 19 Bk[2:0] 18 17 16 15 14 13 12 11 10 9 8 7 Row[12:0] 6 5 4 3 2 1 0 M0 Column[9:0] Table 29-10. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[12:0] 12 11 10 9 8 7 Bk[2:0] 6 5 4 3 2 1 0 M0 Column[9:0] Table 29-11. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 19 Bk[2:0] 18 17 16 15 14 13 12 11 10 9 8 7 Row[13:0] 6 5 4 3 2 1 0 M0 Column[9:0] Table 29-12. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows,1024/ Columns, 8 banks CPU Address Line 27 26 25 24 23 22 21 20 Row[13:0] 19 18 17 16 15 14 13 12 Bk[2:0] 11 10 9 8 7 6 5 4 3 2 Column[9:0] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1 0 M0 371 29.7.2 DDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width Table 29-13. Sequential Mapping DDR-SDRAM Configuration Mapping: 2K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 Bk[1:0] 16 15 14 13 12 11 10 9 8 Row[10:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[10:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[10:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-14. Interleaved Mapping DDR-SDRAM Configuration Mapping: 2K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[10:0] 12 11 10 9 8 Bk[1:0] Row[10:0] 6 5 4 3 2 Column[8:0] Bk[1:0] Row[10:0] 7 0 M[1:0] Column[9:0] Bk[1:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-15. Sequential Mapping DDR-SDRAM Configuration Mapping: 4K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 17 16 15 14 13 12 11 10 9 8 Row[11:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[11:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[11:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-16. Interleaved Mapping DDR-SDRAM Configuration Mapping: 4K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[11:0] 12 11 10 9 8 Bk[1:0] Row[11:0] 6 5 4 3 2 Column[8:0] Bk[1:0] Row[11:0] 7 0 M[1:0] Column[9:0] Bk[1:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-17. Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 Bk[1:0] 17 16 15 14 13 12 11 10 9 8 Row[12:0] Bk[1:0] 6 5 4 3 2 Column[8:0] Row[12:0] Bk[1:0] 7 0 M[1:0] Column[9:0] Row[12:0] 1 M[1:0] Column[10:0] M[1:0] Table 29-18. Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows /512/1024/2048 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Row[13:0] Row[13:0] Row[13:0] 12 11 Bk[1:0] Bk[1:0] Bk[1:0] 10 9 8 7 6 5 4 3 2 Column[8:0] Column[9:0] Column[10:0] 1 0 M[1:0] M[1:0] M[1:0] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 372 Table 29-19. Sequential Mapping DDR-SDRAM Configuration Mapping: 8K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 Bk[2:0] 19 18 17 16 15 14 13 12 11 10 9 8 Row[12:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-20. Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 Row[12:0] 13 12 11 10 9 8 Bk[2:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-21. Sequential Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 Bk[1:0] 19 18 17 16 15 14 13 12 11 10 9 8 Row[13:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-22. Interleaved Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 4 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 Row[13:0] 13 12 11 10 9 8 Bk[1:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-23. Sequential Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 Bk[2:0] 19 18 17 16 15 14 13 12 11 10 9 8 Row[13:0] 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Table 29-24. Interleaved Mapping DDR-SDRAM Configuration Mapping: 16K Rows /1024 Columns, 8 banks CPU Address Line 28 27 26 25 24 23 22 21 20 19 18 17 16 Row[13:0] 15 14 13 Bk[2:0] 12 11 10 9 8 7 6 5 4 3 2 Column[9:0] 1 0 M[1:0] Notes: 1. M[1:0] is the byte address inside a 32-bit word. 2. Bk[2] = BA2, Bk[1] = BA1, Bk[0] = BA0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 373 29.8 AHB Multi-port DDR-SDRAM Controller (MPDDRC) User Interface The User Interface is connected to the APB bus. The MPDDRC is programmed using the registers listed in Table 29-25. Table 29-25. Register Mapping Offset Register Name Access Reset 0x00 MPDDRC Mode Register MPDDRC_MR Read/Write 0x00000000 0x04 MPDDRC Refresh Timer Register MPDDRC_RTR Read/Write 0x00000000 0x08 MPDDRC Configuration Register MPDDRC_CR Read/Write 0x024 0x0C MPDDRC Timing Parameter 0 Register MPDDRC_TPR0 Read/Write 0x20227225 0x10 MPDDRC Timing Parameter 1 Register MPDDRC_TPR1 Read/Write 0x3C80808 0x14 MPDDRC Timing Parameter 2 Register MPDDRC_TPR2 Read/Write 0x00042062 0x18 Reserved – – 0x1C MPDDRC Low-power Register MPDDRC_LPR Read/Write 0x0 0x20 MPDDRC Memory Device Register MPDDRC_MD Read/Write 0x10 0x24 MPDDRC High Speed Register MPDDRC_HS Read/Write 0x00000000 0x28 MPDDRC LPDDR2 Low-power Register MPDDRC_LPDDR2_LPR Read/Write 0x00000000 0x2C MPDDRC LPDDR2 Calibration and MR4 Register MPDDRC_LPDDR2_CAL_MR4 Read/Write 0x00000000 0x30 MPDDRC LPDDR2 Timing Calibration Register MPDDRC_LPDDR2_TIM_CAL Read/Write 0x040 0x34 MPDDRC IO Calibration MPDDRC_IO_CALIBR Read/Write 0x00870002 0x38 MPDDRC OCMS Register MPDDRC_OCMS Read/Write 0x00000000 0x3C MPDDRC OCMS KEY1 Register MPDDRC_OCMS_KEY1 Write-only 0x00000000 0x40 MPDDRC OCMS KEY2 Register MPDDRC_OCMS_KEY2 Write-only 0x00000000 0x44–0x70 Reserved – – – 0x74 MPDDRC DLL Master Offset Register MPDDRC_DLL_MO Read/Write 0x-(1) 0x78 MPDDRC DLL Slave Offset Register MPDDRC_DLL_SOF Read/Write 0x-(1) 0x7C MPDDRC DLL Status Master Register MPDDRC_DLL_MS Read-only 0x00000000 0x80 MPDDRC DLL Status Slave 0 Register MPDDRC_DLL_SS0 Read-only 0x00000000 0x84 MPDDRC DLL Status Slave 1 Register MPDDRC_DLL_SS1 Read-only 0x00000000 0x88 MPDDRC DLL Status Slave 2 Register MPDDRC_DLL_SS2 Read-only 0x00000000 0x8C MPDDRC DLL Status Slave 3 Register MPDDRC_DLL_SS3 Read-only 0x00000000 0x94xE0 Reserved – – – 0xE4 MPDDRC Write Protect Control Register MPDDRC_WPMR Read/Write 0x00000000 0xE8 MPDDRC Write Protect Status Register MPDDRC_WPSR Read-only 0x00000000 0x158–0x1CC Reserved – – – 0x1DC–0x1F8 Reserved – – – Note: – 1. Values in the DLL Master Offset Register and in the DLL Slave Offset Register vary with the product implementation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 374 29.8.1 MPDDRC Mode Register Name: MPDDRC_MR Address: 0xFFFFEA00 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 2 1 0 MRS 7 6 5 4 3 – – – – – MODE • MODE: MPDDRC Command Mode This field defines the command issued by the MPDDRC when the SDRAM device is accessed. This register is used to initialize the SDRAM device and to activate deep power-down mode. Value Name Description 0 NORMAL_CMD Normal Mode. Any access to the MPDDRC is decoded normally. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 1 NOP_CMD The MPDDRC issues a NOP command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDR-SDRAM. 2 PRCGALL_CMD 3 LMR_CMD 4 RFSH_CMD 5 The MPDDRC issues the All Banks Precharge command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. The MPDDRC issues a Load Mode Register command when the DDR-SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the DDRSDRAM. The MPDDRC issues an Auto-Refresh command when the DDR-SDRAM device is accessed regardless of the cycle. Previously, an All Banks Precharge command must be issued. To activate this mode, the command must be followed by a write to the DDR-SDRAM. The MPDDRC issues an Extended Load Mode Register command when the SDRAM device is accessed EXT_LMR_CMD regardless of the cycle. To activate this mode, the command must be followed by a write to the DDRSDRAM. The write in the DDR-SDRAM must be done in the appropriate bank. 6 DEEP_CMD 7 LPDDR2_CMD Deep power mode: Access to deep power-down mode The MPDDRC issues an LPDDR2 Mode Register command when the low-power DDR2-SDRAM device is accessed regardless of the cycle. To activate this mode, the Mode Register command must be followed by a write to the low-power DDR2-SDRAM. • MRS: Mode Register Select LPDDR2 Configure this 8-bit field to program all mode registers included in the low-power DDR2-SDRAM device. This field is unique to the low-power DDR2-SDRAM devices. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 375 29.8.2 MPDDRC Refresh Timer Register Name: MPDDRC_RTR Address: 0xFFFFEA04 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – REF_PB ADJ_REF 11 10 9 8 1 0 MR4_VALUE 15 14 13 12 – – – – 7 6 5 4 COUNT 3 2 COUNT • COUNT: MPDDRC Refresh Timer Count This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh sequence is initiated. The SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the MPDDRC clock frequency (MCK: Master Clock) and the number of rows in the device. For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of the COUNT field is configured: ((64 x 10)/8192) x 100 x 106 = 781 or 0x030D. 3 The low-power DDR2-SDRAM devices support Per Bank Refresh operation. In this configuration, average time between refresh command is 0.975 µs. The value of the COUNT field is configured depending on this value. For example, the value of a 100 MHz Master clock refresh timer is 98 or 0x0062. • ADJ_REF: Adjust Refresh Rate Reset value is 0. 0: Adjust refresh rate is not enabled. 1: Adjust refresh rate is enabled. This mode is unique to the low-power DDR2-SDRAM devices. • REF_PB: Refresh Per Bank Reset value is 0. 0: Refresh all banks during auto-refresh operation. 1: Refresh the scheduled bank by the bank counter in the memory interface. This mode is unique to the low-power DDR2-SDRAM devices. • MR4_VALUE: Content of MR4 Register Reset value is 3. This field (read-only) gives the content of MR4 register. This field is updated when MRR command is generated and Adjust Refresh Rate bit is enabled. Update is done when read value is different from MR4_VALUE. LP-DDR2 JEDEC memory standards impose derating LP-DDR2 AC timings (tRCD, tRC, tRAS, tRP and tRRD) when the value of MR4 is equal to 6. If the application needs to work in extreme conditions, the derating value must be added to AC timings before the power up sequence. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 376 This mode is unique to the low-power DDR2-SDRAM devices. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 377 29.8.3 MPDDRC Configuration Register Name: MPDDRC_CR Address: 0xFFFFEA08 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 19 18 17 16 – ENRDM DQMS 23 22 21 20 UNAL DECOD NDQS NB 15 14 13 12 – 11 OCD 7 6 5 DLL 10 ZQ 4 3 CAS 2 NR 9 8 DIS_DLL DIC_DS 1 0 NC • NC: Number of Column Bits Reset value is 9 column bits. Value Name Description 0 9_COL_BITS 9 bit to define the column number, up to 512 column 1 10_COL_BITS 10 bit to define the column number, up to 1024 columns 2 11_COL_BITS 11 bit to define the column number, up to 2048 columns 3 12_COL_BITS 12 bit to define the column number, up to 4096 columns • NR: Number of Row Bits Reset value is 12 row bits. Value Name 0 11_ROW_BITS Description 11 bit to define the row number, up to 2048 rows 1 12_ROW_BITS 12 bit to define the row number, up to 4096 rows 2 13_ROW_BITS 13 bit to define the row number, up to 8192 rows 3 14_ROW_BITS 14 bit to define the row number, up to 16384 rows • CAS: CAS Latency Reset value is 2 cycles. Value Name Description 2 DDR_CAS2 LPDDR1 CAS Latency 2 3 DDR_CAS3 DDR2/LPDDR2/LPDDR1 CAS Latency 3 • DLL: Reset DLL Reset value is 0. This bit defines the value of Reset DLL. 0 (RESET_DISABLED): Disable DLL reset. 1 (RESET_ENABLED): Enable DLL reset. This value is used during the power-up sequence. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 378 This bit is found only in the DDR2-SDRAM devices. • DIC_DS: Output Driver Impedance Control (Drive Strength) Reset value is 0. This bit name is described as “DS” in some memory datasheets. It defines the output drive strength. This value is used during the power-up sequence. Value Name Description 0 DDR2_NORMALSTRENGTH Normal driver strength 1 DDR2_WEAKSTRENGTH Weak driver strength This bit is found only in the DDR2-SDRAM devices. • DIS_DLL: DISABLE DLL Reset value is 0. 0: Enable DLL. 1: Disable DLL. This value is used during the power-up sequence. It is only found in the DDR2-SDRAM devices. • ZQ: ZQ Calibration Reset value is 0. Value Name Description 0 INIT 1 LONG Long calibration Calibration command after initialization 2 SHORT Short calibration 3 RESET ZQ Reset This parameter is used to calibrate DRAM On resistance (Ron) values over PVT. This field is found only in the low-power DDR2-SDRAM devices. • OCD: Off-chip Driver Reset value is 7. Note: SDRAM Controller supports only two values for OCD (default calibration and exit from calibration). These values MUST always be programmed during the initialization sequence. The default calibration must be programmed first, after which the exit calibration and maintain settings must be programmed. This field is found only in the DDR2-SDRAM devices. Value Name 0 DDR2_EXITCALIB 7 DDR2_DEFAULT_CALI B Description Exit from OCD calibration mode and maintain settings OCD calibration default • DQMS: Mask Data is Shared Reset value is 0. 0 (NOT_SHARED): DQM is not shared with another controller. 1 (SHARED): DQM is shared with another controller. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 379 • ENRDM: Enable Read Measure Reset value is 0. 0 (OFF): DQS/DDR_DATA phase error correction is disabled. 1 (ON): DQS/DDR_DATA phase error correction is enabled. • NB: Number of Banks Reset value is 4 banks. If LC_LPDDR1 is set to 1, NB is not relevant. Value Name Description 0 4_BANKS 4 banks memory devices 1 8_BANKS 8 banks. Only possible when using the DDR2-SDRAM and low-power DDR2-SDRAM devices. • NDQS: Not DQS Reset value is 1; not DQS is disabled. 0: (ENABLED) Not DQS is enabled. 1: (DISABLED) Not DQS is disabled. This field is found only in the DDR2-SDRAM devices. • DECOD: Type of Decoding Reset value is 0. Value Name Description 0 SEQUENTIAL Method for address mapping where banks alternate at each last DDR-SDRAM page of the current bank. 1 INTERLEAVED Method for address mapping where banks alternate at each SDRAM end page of the current bank. • UNAL: Support Unaligned Access Reset value is 0; unaligned access is not supported. 0 (UNSUPPORTED): Unaligned access is not supported. 1 (SUPPORTED): Unaligned access is supported. This mode is enabled with masters which have an AXI interface. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 380 29.8.4 MPDDRC Timing Parameter 0 Register Name: MPDDRC_TPR0 Address: 0xFFFFEA0C Access: Read/Write Reset: See Table 29-25 31 30 29 28 TMRD 23 22 27 26 21 20 19 14 18 13 6 17 16 9 8 1 0 TRP 12 11 10 TRC 7 24 TWTR TRRD 15 25 RDC_WRRD TWR 5 TRCD 4 3 2 TRAS • TRAS: Active to Precharge Delay Reset value is 5 SDCK(1) clock cycles. This field defines the delay between an Activate command and a Precharge command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. • TRCD: Row to Column Delay Reset value is 2 SDCK(1) clock cycles. This field defines the delay between an Activate command and a Read/Write command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. • TWR: Write Recovery Delay Reset value is 2 SDCK(1) clock cycles. This field defines the Write Recovery Time in number of SDCK(1) clock cycles. The number of cycles is between 1 and 15. • TRC: Row Cycle Delay Reset value is 7 SDCK(1) clock cycles. This field defines the delay between an Activate command and Refresh command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15 • TRP: Row Precharge Delay Reset value is 2 SDCK(1) clock cycles. This field defines the delay between a Precharge command and another command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. • TRRD: Active BankA to Active BankB Reset value is 2 SDCK(1) clock cycles. This field defines the delay between an Activate command in BankA and an Activate command in BankB in number of SDCK(1) clock cycles. The number of cycles is between 1 and 15. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 381 • TWTR: Internal Write to Read Delay Reset value is 0. This field defines the internal Write to Read command time in number of SDCK(1) clock cycles. The number of cycles is between 1 and 7. • RDC_WRRD: Reduce Write to Read Delay Reset value is 0. This field reduces the delay between write to read access for the low-power DDR-SDRAM devices with a latency equal to 2. To use this feature, the TWTR field must be equal to 0. Note that some devices do not support this feature. • TMRD: Load Mode Register Command to Activate or Refresh Command Reset value is 2 SDCK(1) clock cycles. This field defines the delay between a Load mode register command and an Activate or Refresh command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. For low-power DDR2-SDRAM, this field is equivalent to TMRW timing. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 382 29.8.5 MPDDRC Timing Parameter 1 Register Name: MPDDRC_TPR1 Address: 0xFFFFEA10 Access: Read/Write Reset: See Table 29-25 31 30 29 28 – – – – 23 22 21 20 27 26 25 24 TXP 19 18 17 16 11 10 9 8 2 1 0 TXSRD 15 14 13 12 TXSNR 7 6 5 – – – 4 3 TRFC • TRFC: Row Cycle Delay Reset value is 8 SDCK(1) clock cycles. This field defines the delay between a Refresh command or a Refresh and Activate command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 31. In case of low-power DDR2-SDRAM, this field is equivalent to tRFCab timing. If the user enables the function “Refresh Per Bank” (see “REF_PB: Refresh Per Bank” on page 376), this field is equivalent to tRFCpb. • TXSNR: Exit Self-refresh Delay to Non Read Command Reset value is 8 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Non Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 255. This field is used by the DDR-SDRAM devices. In case of low-power DDR-SDRAM, this field is equivalent to tXSR timing. • TXSRD: Exit Self-refresh Delay to Read Command Reset value is 200 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 255. This field is found only in the DDR2-SDRAM devices . • TXP: Exit Power-down Delay to First Command Reset value is 3 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Valid command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 383 29.8.6 MPDDRC Timing Parameter 2 Register Name: MPDDRC_TPR2 Address: 0xFFFFEA14 Access: Read/Write Reset: See Table 29-25 31 30 – – 23 22 29 28 27 26 21 20 19 18 25 24 17 16 9 8 1 0 TFAW 15 14 13 12 11 10 TRTP 7 6 5 TRPA 4 3 2 TXARDS TXARD • TXARD: Exit Active Power Down Delay to Read Command in Mode “Fast Exit” Reset value is 2 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM devices. • TXARDS: Exit Active Power Down Delay to Read Command in Mode “Slow Exit” Reset value is 6 SDCK(1) clock cycles. This field defines the delay between CKE set high and a Read command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM devices. • TRPA: Row Precharge All Delay Reset value is 0 SDCK(1) clock cycles. This field defines the delay between a Precharge All Banks command and another command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM devices. • TRTP: Read to Precharge Reset value is 2 SDCK(1) clock cycles. This field defines the delay between Read command and a Precharge command in number of SDCK(1) clock cycles. The number of cycles is between 0 and 7. • TFAW: Four Active Windows Reset value is 4 SDCK(1) clock cycles. DDR2 devices with eight banks (1 Gbit or larger) have an additional requirement concerning tFAW timing. This requires that no more than four Activate commands may be issued in any given tFAW (MIN) period. The number of cycles is between 0 and 15. This field is found only in the DDR2-SDRAM and LPDDR2-SDRAM devices. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 384 29.8.7 MPDDRC Low-power Register Name: MPDDRC_LPR Address: 0xFFFFEA1C Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – APDE 15 14 11 10 9 8 – – 7 6 – UPD_MR 13 12 TIMEOUT 5 – 4 PASR DS 3 2 LPDDR2_PWOFF CLK_FR 1 0 LPCB • LPCB: Low-power Command Bit Reset value is 0. Value Name Description 0 NOLOWPOWER Low-power feature is inhibited. No power-down, self-refresh and deep-power modes are issued to the DDR-SDRAM device. 1 SELFREFRESH The MPDDRC issues a self-refresh command to the DDR-SDRAM device, the clock(s) is/are deactivated and the CKE signal is set low. The DDR-SDRAM device leaves the self-refresh mode when accessed and reenters it after the access. 2 POWERDOWN The MPDDRC issues a Power-down command to the DDR-SDRAM device after each access, the CKE signal is set low. The DDR-SDRAM device leaves the power-down mode when accessed and reenters it after the access. 3 DEEPPOWERDOWN The MPDDRC issues a Deep Power-down command to the low-power DDR-SDRAM device. • CLK_FR: Clock Frozen Command Bit Reset value is 0. This field sets the clock low during power-down mode. Some DDR-SDRAM devices do not support freezing the clock during power-down mode. Refer to the device datasheet for details. 0 (DISABLED): Clock(s) is/are not frozen. 1 (ENABLED): Clock(s) is/are frozen. • LPDDR2_PWOFF: LPDDR2 Power Off Bit Reset value is 0. LPDDR2 power off sequence must be controlled to preserve the LPDDR2 device. The power failure is handled at system level (IRQ or FIQ) and the LPDDR2 power off sequence is applied using the LPDDR2_PWOFF bit. LPDDR2_PWOFF bit is used to impose CKE low before a power off sequence. Uncontrolled power off sequence can be applied only up to 400 times in the life of a LPDDR2 device. 1 (ENABLED): A power off sequence is applied to the LPDDR2 device. CKE is forced low. 0 (DISABLED): No power off sequence applied to LPDDR2. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 385 • PASR: Partial Array Self-refresh Reset value is 0. This field is unique to low-power DDR1-SDRAM. It is used to specify whether only one-quarter, one-half or all banks of the DDRSDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. The values of this field are dependant on the low-power DDR-SDRAM devices. After the initialization sequence, as soon as the PASR field is modified, the Extended Mode Register in the external device memory is accessed automatically and PASR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. • DS: Drive Strength Reset value is 0. This field is unique to low-power DDR-SDRAM. It selects the driver strength of the DDR- SDRAM output. After the initialization sequence, as soon as the DS field is modified, the Extended Mode Register is accessed automatically and DS bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. • TIMEOUT: Time Between Last Transfer and Low Power Mode Reset value is 0. This field defines when low-power mode is activated. Value Name Description 0 NONE SDRAM low-power mode is activated immediately after the end of the last transfer. 1 DELAY_64_CLK SDRAM low-power mode is activated 64 clock cycles after the end of the last transfer. 2 DELAY_128_CLK SDRAM low-power mode is activated 128 clock cycles after the end of the last transfer. • APDE: Active Power Down Exit Time Reset value is 1. This mode is unique to the DDR2-SDRAM devices. This mode manages the active power-down mode which determines performance versus power saving. Value Name Description 0 DDR2_FAST_EXIT Fast Exit from Power Down. The DDR2-SDRAM devices only. 1 DDR2_SLOW_EXIT Slow Exit from Power Down. The DDR2-SDRAM devices only. After the initialization sequence, as soon as the APDE field is modified, the Extended Mode Register (located in the memory of the external device) is accessed automatically and APDE bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access • UPD_MR: Update Load Mode Register and Extended Mode Register Reset value is 0. This bit is used to enable or disable automatic update of the Load Mode Register and Extended Mode Register. This update is function of DDRSDRC integration in a system. DDRSDRC can either share or not, an external bus with another controller. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 386 Value Name Description 0 NO_UPDATE 1 UPDATE_SHAREDBUS DDRSDRC shares an external bus. Automatic update is done during a refresh command and a pending read or write access in the SDRAM device. 2 UPDATE_NOSHAREDBUS DDRSDRC does not share an external bus. Automatic update is done before entering in selfrefresh mode. Update of Load Mode and Extended Mode registers is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 387 29.8.8 MPDDRC Low-power DDR2 Low-power Register Name: MPDDRC_LPDDR2_LPR Address: 0xFFFFEA28 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 DS 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 SEG_MASK 15 14 13 12 SEG_MASK 7 6 5 4 BK_MASK_PASR • BK_MASK_PASR: Bank Mask Bit/PASR Partial Array Self-Refresh (the low-power DDR2-SDRAM-S4 devices only) Reset value is 0. After the initialization sequence, as soon as the BK_MASK_PASR field is modified, Mode Register 16 is accessed automatically and BK_MASK_PASR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. 0: Refresh is enabled (= unmasked). 1: Refresh is disabled (= masked). This mode is unique to the low-power DDR2-SDRAM-S4 devices. In self-refresh mode, each bank of LPDDR2 can be independently configured whether a self-refresh operation is taking place or not. After the initialization sequence, as soon as the BK_MASK_PASR field is modified, the Extended Mode Register is accessed automatically and BK_MASK_PASR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. • SEG_MASK: Segment Mask Bit Reset value is 0. After the initialization sequence, as soon as the SEG_MASK field is modified, Mode Register 17 is accessed automatically and SEG_MASK bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. 0: Segment is refreshed (= unmasked). 1: Segment is not refreshed (= masked). This mode is unique to the low-power DDR2-SDRAM-S4 devices. The number of Segment Mask bits differs with the density. For 1 Gbit density, 8 segments are used. In self-refresh mode, when the Segment Mask bit is configured, the refresh operation is masked in the segment. • DS: Drive strength Reset value is 0. After the initialization sequence, as soon as the DS field is modified, Mode Register 3 is accessed automatically and DS bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 388 This field is unique to low-power DDR2-SDRAM. It selects the driver strength of DDR2-SDRAM I/O. • SR: Slew Rate Reset value is 0. After the initialization sequence, as soon as the SR field is modified, Mode Register 3 is accessed automatically and SR bits are updated. Depending on the UPD_MR bit, update is done before entering self-refresh mode or during a refresh command and a pending read or write access This field is unique to low-power DDR2-SDRAM. It selects the slew rate of low-power DDR2-SDRAM I/O. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 389 29.8.9 MPDDRC Low-power DDR2 Calibration and MR4 Register Name: MPDDRC_LPDDR2_CAL_MR4 Address: 0xFFFFEA2C Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MR4_READ 23 22 21 20 MR4_READ 15 14 13 12 COUNT_CAL 7 6 5 4 COUNT_CAL • COUNT_CAL: LPDDR2 Calibration Timer Count This 16-bit field is loaded into a timer which generates the calibration pulse. Each time the calibration pulse is generated, a ZQCS calibration sequence is initiated. The ZQCS Calibration command is used to calibrate DRAM Ron values over PVT. One method for calculating the interval between ZQCS commands gives the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application. The interval could be defined by the following formula: ZQCorrection/((TSens x Tdriftrate) + (VSens x Vdriftrate)) Where TSens = max(dRONdTM) and VSens = max(dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 0.75%/C, VSens = 0.2%/mV, Tdriftrate = 1C/sec and Vdriftrate = 15 mV/s, then the interval between ZQCS commands is calculated as: 1.5/((0.75 x 1) + (0.2 x 15)) = 0.4s In this example, the LPDDR2-SDRAM devices require a calibration every 0.4s. The value to be loaded depends on average time between REFRESH commands, tREF. For example, for an LPDDR2-SDRAM with the time between refresh of 7.8 µs, the value of the Calibration Timer Count field is programmed: (0.4/7.8 x 10-6) = 0xC852. • MR4_READ: Mode Register 4 Read Interval MR4_READ defines the time period between MR4 reads (for LPDDR2-SDRAM). The formula is (MR4_READ+1) * tREF. The value to be loaded depends on the average time between REFRESH commands, tREF. For example, for an LPDDR2-SDRAM with the time between refresh of 7.8 µs, if the MR4_READ value is 2, the time period between MR4 reads is 23.4 µs. The LPDDR2-SDRAM devices feature a temperature sensor whose status can be read from MR4 register. This sensor can be used to determine an appropriate refresh rate. Temperature sensor data may be read from MR4 register using the Mode Register Read protocol. The Adjust Refresh Rate bit (ADJ_REF) in the Refresh Timer Register (MPDDRC_RTR) must be written to a one to activate these reads. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 390 29.8.10 MPDDRC Low-power DDR2 Timing Calibration Register Name: MPDDRC_LPDDR2_TIM_CAL Address: 0xFFFFEA30 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ZQCS • ZQCS: ZQ Calibration Short Reset value is 6 SDCK(1) clock cycles This field defines the delay between ZQ Calibration command and any Valid commands in number of SDCK(1) clock cycles. The number of cycles is between 0 and 255. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 391 29.8.11 MPDDRC I/O Calibration Register Name: MPDDRC_IO_CALIBR Address: 0xFFFFEA34 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 9 8 CALCODEN CALCODEP 15 14 13 12 11 – – – – – 7 6 5 4 3 – – – – – 10 TZQIO 2 1 0 RDIV • RDIV: Resistor Divider, Output Driver Impedance Reset value is 2. This corresponds to 40 ohms. With the LPDDR2-SDRAM device, the RDIV field must be equal to the DS (Drive Strength) field (see “DS: Drive Strength” on page 386). RDIV is used with the external precision resistor RZQ to define the output driver impedance. The value of RZQ is either 240 ohms (LPDDR2 mode) or 200 ohms (the DDR2/LPDDR1 device). Value Name 1 RZQ_34 2 RZQ_40_RZQ_33_3 3 RZQ_48_RZQ_40 Description LPDDR2 RZQ = 34.3 ohms, DDR2/LPDDR1: Not applicable LPDDR2:RZQ = 40 ohms, DDR2/LPDDR1: RZQ = 33.3 ohms LPDDR2:RZQ = 48 ohms, DDR2/LPDDR1: RZQ = 40 ohms 4 RZQ_60_RZQ_50 6 RZQ_80_RZQ_66_7 LPDDR2: RZQ = 80 ohms, DDR2/LPDDR1: RZQ = 66.7 ohms LPDDR2:RZQ = 60 ohms, DDR2/LPDDR1: RZQ = 50 ohms 7 RZQ_120_RZQ_100 LPDDR2:RZQ = 120 ohms, DDR2/LPDDR1: RZQ = 100 ohms • TZQIO: IO Calibration This field defines the delay between an IO Calibration command and any valid commands in number of SDCK(1) clock cycles. The number of cycles is between 0 and 7. The TZQIO configuration code must be correctly set depending on the clock frequency using the following formula: TZQIO = (DDRCLK * 20 ns) + 1. • CALCODEP: Number of Transistor P This register is read-only. Reset value is 7. This value gives the number of transistor P to perform the calibration. • CALCODEN: Number of Transistor N This register is read-only. Reset value is 8. This value gives the number of transistor N to perform the calibration. Note: 1. SDCK is the clock that drives the SDRAM device. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 392 29.8.12 MPDDRC OCMS Register Name: MPDDRC_OCMS Address: 0xFFFFEA38 Access: Read/Write Reset: See Table 29-25 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SCR_EN • SCR_EN: Scrambling Enable 0: Disables “Off-chip” scrambling for SDRAM access. 1: Enables “Off-chip” scrambling for SDRAM access. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 393 29.8.13 MPDDRC OCMS KEY1 Register Name: MPDDRC_OCMS_KEY1 Address: 0xFFFFEA3C Access: Write once Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1 23 22 21 20 KEY1 15 14 13 12 KEY1 7 6 5 4 KEY1 • KEY1: Off-chip Memory Scrambling (OCMS) Key Part 1 When Off-chip Memory Scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 394 29.8.14 MPDDRC OCMS KEY2 Register Name: MPDDRC_OCMS_KEY2 Address: 0xFFFFEA40 Access: Write once Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2 23 22 21 20 KEY2 15 14 13 12 KEY2 7 6 5 4 KEY2 • KEY2: Off-chip Memory Scrambling (OCMS) Key Part 2 When Off-chip Memory Scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 395 29.8.15 MPDDRC Memory Device Register Name: MPDDRC_MD Address: 0xFFFFEA20 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – DBW – MD • MD: Memory Device Indicates the type of memory used. Reset value is that for the DDR-SDRAM device. Value Name 3 LPDDR_SDRAM 6 DDR2_SDRAM 7 LPDDR2_SDRAM Description Low-power DDR1-SDRAM DDR2-SDRAM Low-power DDR2-SDRAM • DBW: Data Bus Width Reset value is 16 bits. 0 (DBW_32_BITS): Data bus width is 32 bits. 1 (DBW_16_BITS): Data bus width is 16 bits.(1) Note: 1. Only 32-bit value is used. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 396 29.8.16 DDRSDRC High Speed Register Name: MPDDRC_HS Address: 0xFFFFEA24 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – DIS_ANTICIP_READ – – • DIS_ANTICIP_READ: Disable Anticip Read Access This field allows DDR read access optimization with the multi-port. As this feature is based on the “bank open policy”, the software must map different buffers in different DDR banks to take advantage of that feature. 0: Anticip_read access is enabled (default). 1: Anticip_read access is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 397 29.8.17 MPDDRC Write Protect Mode Register Name: MPDDRC_WPMR Address: 0xFFFFEAE4 Access: Read/Write Reset: See Table 29-25 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protection Enable 0: Disables the Write Protection if WPKEY corresponds to 0x444452 (“DDR” in ASCII). 1: Enables the Write Protection if WPKEY corresponds to 0x444452 (“DDR” in ASCII). • WPKEY: Write Protection KEY Value Name 0x444452 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 398 29.8.18 MPDDRC Write Protect Status Register Name: MPDDRC_WPSR Address: 0xFFFFEAE8 Access: Read-only Reset: See Table 29-25 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protection Enable 0: No Write Protection Violation occurred since the last read of this register (MPDDRC_WPSR). 1: A Write Protection Violation occurred since the last read of this register (MPDDRC_WPSR). If this violation is an unauthorized attempt to write a control register, the associated violation is reported into the WPVSRC field. • WPVSRC: Write Protection Violation Source When WPVS is active, it indicates the register (through address or code) that should have been written if Write Protection had not been previously enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 399 29.8.19 MPDDRC DLL Master Offset Register Name: MPDDRC_DLL_MO Address: 0xFFFFEA74 Access: Read/Write Reset: See Table 29-25 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 SELOFF 15 – 14 – 13 – 12 11 10 CLK90OFF 9 8 7 – 6 – 5 – 4 – 3 2 1 0 MOFF • MOFF: DLL Master Delay Line Offset The value stored by this field is unsigned. When this field is written, the programmable Master delay line offset is written. When this field is read: – If SELOFF = 0: the hard-coded Master delay line offset is read. – If SELOFF = 1: the programmable Master delay line offset is read. • CLK90OFF: DLL CLK90 Delay Line Offset The value stored by this field is signed. When this field is written, the programmable CLK90 delay line offset is written. When this field is read: – If SELOFF = 0: the hard-coded CLK90 delay line offset is read. – If SELOFF = 1: the programmable CLK90 delay line offset is read. • SELOFF: DLL Offset Selection 0: The hard-coded Master/Slave x/CLK90 delay line offsets are selected. 1: The programmable Master/Slave x/CLK90 delay line offsets are selected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 400 29.8.20 MPDDRC DLL Slave Offset Register Name: MPDDRC_DLL_SOF Address: 0xFFFFEA78 Access: Read/Write Reset: See Table 29-25 31 – 30 – 29 – 28 27 26 S3OFF 25 24 23 – 22 – 21 – 20 19 18 S2OFF 17 16 15 – 14 – 13 – 12 11 10 S1OFF 9 8 7 – 6 – 5 – 4 3 2 S0OFF 1 0 • SxOFF: DLL Slave x Delay Line Offset ([x = 0..3]) The value stored by this field is signed. When this field is written, the programmable Slave x delay line offset is written. When this field is read: – If MPDDRC_DLL MOR.SELOFF = 0: the hard-coded Slave x delay line offset is read. – If MPDDRC_DLL MOR.SELOFF = 1: the programmable Slave x delay line offset is read. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 401 29.8.21 MPDDRC DLL Master Status Register Name: MPDDRC_DLL_MS Address: 0xFFFFEA7C Access: Read-only Reset: See Table 29-25 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 MDOVF 1 MDDEC 0 MDINC MDVAL 7 – 6 – 5 – 4 – • MDINC: DLL Master Delay Increment 0: The DLL is not incrementing the Master delay counter. 1: The DLL is incrementing the Master delay counter. • MDDEC: DLL Master Delay Decrement 0: The DLL is not decrementing the Master delay counter. 1: The DLL is decrementing the Master delay counter. • MDOVF: DLL Master Delay Overflow Flag 0: The Master delay counter has not reached its maximum value, or the Master is not locked yet 1: The Master delay counter has reached its maximum value, the Master delay counter increment is stopped and the DLL forces the Master lock. If this flag is set, it means the MPDDRC clock frequency is too low compared to Master delay line number of elements. • MDVAL: DLL Master Delay Value Value of the Master delay counter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 402 29.8.22 MPDDRC DLL Status Slave x Register Name: MPDDRC_DLL_SSx Address: 0xFFFFEA80 Access: Read-only Reset: See Table 29-25 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 SDERF 1 SDCUDF 0 SDCOVF SDCVAL 15 14 13 12 SDVAL 7 – 6 – 5 – 4 – • SDCOVF: DLL Slave x Delay Correction Overflow Flag 0: Due to the correction, the Slave x delay counter has not reached its maximum value, or the Slave x is not locked yet. 1: Due to the correction, the Slave x delay counter has reached its maximum value, the correction is not optimal because it has not been entirely applied. • SDCUDF: DLL Slave x Delay Correction Underflow Flag 0: Due to the correction, the Slave x delay counter has not reached its minimum value, or the Slave x is not locked yet. 1: Due to the correction, the Slave x delay counter has reached its minimum value, the correction is not optimal because it has not been entirely applied. • SDERF: DLL Slave x Delay Correction Error Flag 0: The DLL has succeeded in computing the Slave x delay correction, or the Slave x is not locked yet. 1: The DLL has not succeeded in computing the Slave x delay correction. • SDVAL: DLL Slave x Delay Value Value of the Slave x delay counter. • SDCVAL: DLL Slave x Delay Correction Value Value of the correction applied to the Slave x delay. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 403 30. Static Memory Controller (SMC) 30.1 Description This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash. The SMC generates the signals that control the access to external memory devices or peripheral devices. It has 4 Chip Selects and a 26-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. The SMC includes programmable hardware error correcting code with one-bit error correction capability and supports two-bit error detection. In order to improve the overall system performance, the DATA phase of the transfer can be DMAassisted. The External Data Bus can be scrambled/unscrambled by means of user keys. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 404 30.2 Embedded Characteristics  64-Mbyte Address Space per Chip Select  8- or 16-bit Data Bus  Word, Halfword, Byte Transfers  Byte Write or Byte Select Lines  Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select  Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select  Programmable Data Float Time per Chip Select  External Data Bus Scrambling/Unscrambling Function  External Wait Request  Automatic Switch to Slow Clock Mode  Hardware Configurable Number of Chip Selects from 1 to 4  Programmable Timing on a per Chip Select Basis  NAND Flash Controller Supporting NAND Flash with Multiplexed Data/Address Buses  Supports SLC and MLC NAND Flash Technology  Supports NAND Flash Devices with 8-bit Data Path  Multibit Error Correcting Code (ECC)  ECC Algorithm Based on Binary Shortened Bose, Chaudhuri and Hocquenghem (BCH) Codes  Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 Bits of Errors per Block  Programmable Block Size: 512 Bytes or 1024 Bytes  Programmable Number of Block per Page: 1, 2, 4 or 8 Blocks of Data per Page  Programmable Spare Area Size up to 512 bytes  Supports Spare Area ECC Protection  Supports 8 Kbytes Page Size Using 1024 Bytes/block and 4 Kbytes Page Size Using 512 Bytes/block  MultibIt Error Detection Is Interrupt Driven  Provides Hardware Acceleration for Determining Roots of Polynomials Defined over a Finite Field  Programmable Finite Field GF(2^13) or GF(2^14)  Finds Roots of Error-locator Polynomial  Programmable Number of Roots SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 405 30.3 Block Diagram SMC AHB Interface NAND Flash Controller (NFC) AHB Arbiter SMC Scrambler Figure 30-1. Block Diagram D[15:0] A[0]/NBS0 A[20:1] A21/NANDALE A22/NANDCLE A[25:23] NCS[3:0] SMC Interface SRAM AHB Interface SRAM Scrambler ECC User Interface NFC (8 Kbytes) Internal SRAM Control & Status Registers NRD NWR0/NWE NWR1/NBS1 NANDOE NANDWE NANDRDY NWAIT APB Interface SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 406 30.4 I/O Lines Description Table 30-1. I/O Line Description Name Description Type Active Level NCS[3:0] Static Memory Controller Chip Select Lines Output Low NRD Read Signal Output Low NWR0/NWE Write 0/Write Enable Signal Output Low A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low A[25:1] Address Bus Output – D[15:0] Data Bus I/O – NWAIT External Wait Signal Input Low NANDRDY NAND Flash Ready/Busy Input – NANDWE NAND Flash Write Enable Output Low NANDOE NAND Flash Output Enable Output Low NANDALE NAND Flash Address Latch Enable Output – NANDCLE NAND Flash Command Latch Enable Output – 30.5 Multiplexed Signals Table 30-2. Static Memory Controller (SMC) Multiplexed Signals Multiplexed Signals Related Function NWR0 NWE Byte-write or Byte-select access, see Figure 30-4 "Memory Connection for an 8-bit Data Bus" and Figure 30-5 "Memory Connection for a 16-bit Data Bus" A0 NBS0 8-bit or 16-bit data bus, see Section 30.9.1 “Data Bus Width” A22 NANDCLE NAND Flash Command Latch Enable A21 NANDALE NAND Flash Address Latch Enable NWR1 NBS1 Byte-write or Byte-select access, see Figure 30-4 and Figure 30-5 A1 – 8-/16-bit data bus, see Section 30.9.1 “Data Bus Width” Byte-write or Byte-select access, see Figure 30-4 and Figure 30-5 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 407 30.6 Application Example 30.6.1 Hardware Interface Figure 30-2. SMC Connections to Static Memory Devices D0-D15 A0/NBS0 NWR0/NWE NWR1/NBS1 A1 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NWR0/NWE NCS0 NCS1 NCS2 NCS3 A2 - A18 A0 - A16 NRD OE WE D0-D7 CS A0 - A16 NRD 128K x 8 SRAM NWR1/NBS1 A2 - A18 OE WE A2 - A23 Static Memory Controller 30.7 Product Dependencies 30.7.1 I/O Lines The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. 30.7.2 Power Management The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SMC clock. 30.7.3 Interrupt The SMC has an interrupt line connected to the Nested Vector Interrupt Controller (NVIC). Handling the SMC interrupt requires programming the NVIC before configuring the SMC. Table 30-3. Peripheral IDs 30.8 Instance ID SMC 5 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 30-3). A[25:0] is only significant for 8-bit memory; A[25:1] is used for 16-bit memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 408 Figure 30-3. Memory Connections for External Devices NCS[0] - NCS[3] NRD SMC NWE NCS3 A[25:0] NCS2 D[15:0] NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] 8 or 16 30.9 Connection to External Devices 30.9.1 Data Bus Width D[15:0] or D[7:0] A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the field DBW in the SMC Mode Register (HSMC_MODE) for the corresponding chip select. Figure 30-4 shows how to connect a 512K x 8-bit memory on NCS2. Figure 30-5 shows how to connect a 512K x 16-bit memory on NCS2. 30.9.2 Byte Write or Byte Select Access Each chip select with a 16-bit data bus can operate with one of two different types of write access: Byte write or Byte select access. This is controlled by the BAT field of the HSMC_MODE register for the corresponding chip select. Figure 30-4. Memory Connection for an 8-bit Data Bus SMC D[7:0] D[7:0] A[18:2] A[18:2] A1 A1 A0 A0 NWE Write Enable NRD Output Enable NCS[2] Memory Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 409 Figure 30-5. Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC A[0] NBS0 Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Memory Enable 30.9.2.1 Byte Write Access Byte write access supports one write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode.  For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory. 30.9.2.2 Byte Select Access In this mode, read/write operations can be enabled/disabled at Byte level. One Byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write.  For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively Byte0 (lower byte) and Byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device. Figure 30-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[7:0] D[15:8] A[24:2] SMC A1 NWR0 A[23:1] A[0] Write Enable NWR1 NRD NCS[3] Read Enable Memory Enable D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 410 30.9.2.3 Signal Multiplexing Depending on the Byte Access Type (BAT), only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 30-4 shows signal multiplexing depending on the data bus width and the Byte Access Type. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 is unused. When Byte Write option is selected, NBS0 is unused. Table 30-4. SMC Multiplexed Signal Translation Signal Name 16-bit Bus Device Type 8-bit Bus 1 x 16-bit 2 x 8-bit 1 x 8-bit Byte Select Byte Write – NBS0_A0 NBS0 – A0 NWE_NWR0 NWE NWR0 NWE NBS1_NWR1 NBS1 NWR1 – A1 A1 A1 Byte Access Type (BAT) A1 30.10 Standard Read and Write Protocols In the following sections, the Byte Access Type is not considered. Byte select lines (NBS0 to NBS1) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..3] chip select lines. 30.10.1 Read Waveforms The read cycle is shown on Figure 30-7. The read cycle starts with the address setting on the memory address bus, i.e.,: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 411 Figure 30-7. Standard Read Cycle MCK A[25:2] NBS0,NBS1, A0, A1 NRD NCS D[15:0] NRD_SETUP NCS_RD_SETUP NRD_PULSE NCS_RD_PULSE NRD_HOLD NCS_RD_HOLD NRD_CYCLE 30.10.1.1 NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing: 1. NRD_SETUP: The NRD setup time is defined as the setup of address before the NRD falling edge. 2. NRD_PULSE: The NRD pulse length is the time between NRD falling edge and NRD rising edge. 3. NRD_HOLD: The NRD hold time is defined as the hold time of address after the NRD rising edge. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 412 30.10.1.2 NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: The NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: The NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCS_RD_HOLD: The NCS hold time is defined as the hold time of address after the NCS rising edge. 30.10.1.3 Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, the user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 30.10.2 Read Mode As NCS and NRD waveforms are defined independently of one another, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the HSMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation. 30.10.2.1 Read is Controlled by NRD (READ_MODE = 1) Figure 30-8 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of the Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS. Figure 30-8. READ_MODE = 1: Data is Sampled by SMC before the Rising Edge of NRD MCK A[25:2] NBS0,NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 413 30.10.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 30-9 shows the typical read cycle. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of the Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD. Figure 30-9. READ_MODE = 0: Data is Sampled by SMC before the Rising Edge of NCS MCK A[25:2] NBS0,NBS1, A0, A1 NRD NCS tPACC D[15:0] Data Sampling SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 414 30.10.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 30-10. The write cycle starts with the address setting on the memory address bus. 30.10.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing: 1. NWE_SETUP: The NWE setup time is defined as the setup of address and data before the NWE falling edge. 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge. 3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3. 30.10.3.2 NCS Waveforms The NCS signal waveforms in write operations are not the same as those applied in read operations, but are separately defined: 1. NCS_WR_SETUP: The NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_WR_PULSE: The NCS pulse length is the time between NCS falling edge and NCS rising edge. 3. NCS_WR_HOLD: The NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 30-10.Write Cycle MCK A[25:2] NBS0, NBS1, A0, A1 NWE NCS NWE_SETUP NCS_WR_SETUP NWE_PULSE NCS_WR_PULSE NWE_HOLD NCS_WR_HOLD NWE_CYCLE 30.10.3.3 Write Cycle The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 415 NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE 30.10.4 Write Mode The WRITE_MODE parameter in the HSMC_MODE register of the corresponding chip select indicates which signal controls the write operation. 30.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1) Figure 30-11 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS. Figure 30-11.WRITE_MODE = 1. The write operation is controlled by NWE MCK A[25:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] 30.10.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 30-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 416 Figure 30-12.WRITE_MODE = 0. The write operation is controlled by NCS MCK A[25:2] NBS0, NBS1, A0, A1 NWE, NWR0, NWR1 NCS D[15:0] 30.10.5 Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one register according to their type:  The HSMC_SETUP register groups the definition of all setup parameters: NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP  The HSMC_PULSE register groups the definition of all pulse parameters: NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE  The HSMC_CYCLE register groups the definition of all cycle parameters: NRD_CYCLE, NWE_CYCLE Table 30-5 shows how the timing parameters are coded and their permitted range. Table 30-5. Coding and Range of Timing Parameters Permitted Range Coded Value Number of Bits Effective Value setup [5:0] 6 128 x setup[5] + setup[4:0] pulse [6:0] cycle [8:0] 7 9 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0] Coded Value Effective Value 0 ≤ setup ≤ 31 0..31 32 ≤ setup ≤ 63 128..(128 + 31) 0 ≤ pulse ≤ 63 0..63 64 ≤ pulse ≤ 127 256..(256 + 63) 0 ≤ cycle ≤ 127 0..127 128 ≤ cycle ≤ 255 256..(256 + 127) 256 ≤ cycle ≤ 383 512..(512 + 127) 384 ≤ cycle ≤ 511 768..(768 + 127) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 417 30.10.6 Reset Values of Timing Parameters Table 30-6 gives the default value of timing parameters at reset. Table 30-6. Reset Values of Timing Parameters Register Reset Value Description HSMC_SETUP – All setup timings are set to 1 HSMC_PULSE – All pulse timings are set to 1 HSMC_CYCLE – The read and write operations last 3 Master Clock cycles and provide one hold cycle WRITE_MODE 1 Write is controlled with NWE READ_MODE 1 Read is controlled with NRD 30.10.7 Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to an unpredictable behavior of the SMC. 30.10.7.1 For Read Operations Null but positive setup and hold of address and NRD and/or NCS cannot be guaranteed at the memory interface because of the propagation delay of these signals through external logic and pads. When positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals. 30.10.7.2 For Write Operations If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See Section 30.12.2 “Early Read Wait State” on page 419. 30.10.7.3 For Read and Write Operations A null value for pulse parameters is forbidden and may lead to an unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 30.11 Scrambling/Unscrambling Function The external data bus D[15:0] can be scrambled in order to prevent intellectual property data located in off-chip memories from being easily recovered by analyzing data at the package pin level of either the microcontroller or the memory device. The scrambling and unscrambling are performed on-the-fly without additional wait states. The scrambling method depends on two user-configurable key registers, HSMC_KEY1 and HSMC_KEY2. These key registers are only accessible in write mode. The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key is lost. The scrambling/unscrambling function can be enabled or disabled by programming the HSMC_OCMS register. One bit is dedicated to enabling/disabling the NAND Flash scrambling, and one bit is dedicated to enabling/disabling the off chip SRAM scrambling. When at least one external SRAM is scrambled, the SMSC field must be set in the HSMC_OCMS register. When multiple chip selects (external SRAM) are handled, it is possible to configure the scrambling function per chip select using the OCMS field in the HSMC_TIMINGS registers. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 418 To scramble the NAND Flash contents, the SRSE field must be set in the HSMC_OCMS register. When the NAND Flash memory content is scrambled, the on-chip SRAM page buffer associated for the transfer is also scrambled. 30.12 Automatic Wait States Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 30.12.1 Chip Select Wait States The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to NWR1, NCS[0..3], and NRD lines. They are all set to 1. Figure 30-13 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2. Figure 30-13.Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, A0,A1 NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[15:0] Read to Write Chip Select Wait State Wait State 30.12.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid:  if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 30-14). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 419  in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 30-15). The write operation must end with an NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.  in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 30-16. Figure 30-14.Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, A0, A1 NWE NRD No hold No setup D[15:0] Write cycle Early Read wait state Read cycle SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 420 Figure 30-15.Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup MCK A[25:2] NBS0, NBS1, A0,A1 NCS NRD No hold No setup D[15:0] Read cycle Write cycle Early Read (WRITE_MODE = 0) wait state (READ_MODE = 0 or READ_MODE = 1) Figure 30-16.Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle MCK A[25:2] NBS0, NBS1, A0, A1 Internal write controlling signal External write controlling signal (NWE) No hold Read setup = 1 NRD D[15:0] Write cycle Early Read Read cycle (WRITE_MODE = 1) wait state (READ_MODE = 0 or READ_MODE = 1) 30.12.3 Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 421 When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State is inserted, even if the change does not concern the current Chip Select. 30.12.3.1 User Procedure To insert a Reload Configuration Wait State, the SMC detects a write access to any HSMC_MODE register of the user interface. If only the timing registers are modified (HSMC_SETUP, HSMC_PULSE, HSMC_CYCLE registers) in the user interface, the user must validate the modification by writing the HSMC_MODE register, even if no change was made on the mode parameters. 30.12.3.2 Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see Section 30.15 “Slow Clock Mode” on page 432). 30.12.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 30-13 on page 419. 30.13 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access:  before starting a read access to a different external memory  before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the HSMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long tDF will not slow down the execution of a program from internal memory. The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the HSMC_MODE register for the corresponding chip select. 30.13.1 READ_MODE Setting READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 30-17 illustrates the Data Float Period in NRD-controlled mode (READ_MODE = 1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 30-18 shows the read operation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 422 Figure 30-17.TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[25:2] NBS0, NBS1, A0, A1 NRD NCS tpacc D[15:0] TDF = 2 clock cycles NRD controlled read operation Figure 30-18.TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, A0,A1 NRD NCS tpacc D[15:0] TDF = 3 clock cycles NCS controlled read operation 30.13.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the HSMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 30-19 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 423 NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled). Figure 30-19.TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK A[25:2] NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[15:0] Read access on NCS0 (NRD controlled) Read to Write Wait State Write access on NCS0 (NWE controlled) 30.13.3 TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, TDF wait states are inserted at the end of the read transfer, so that the data float period ends when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional TDF wait states will be inserted. Figure 30-20, Figure 30-21 and Figure 30-22 illustrate the cases:  read access followed by a read access on another chip select,  read access followed by a write access on another chip select,  read access followed by a write access on the same chip select, with no TDF optimization. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 424 Figure 30-20.TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK A[25:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) read1 hold = 1 read2 controlling signal (NRD) read2 setup = 1 TDF_CYCLES = 6 D[15:0] 5 TDF WAIT STATES read2 cycle TDF_MODE = 0 (optimization disabled) read1 cycle TDF_CYCLES = 6 Chip Select Wait State Figure 30-21. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects MCK A[25:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) read1 hold = 1 write2 controlling signal (NWE) write2 setup = 1 TDF_CYCLES = 4 D[15:0] read1 cycle TDF_CYCLES = 4 2 TDF WAIT STATES Read to Write Chip Select Wait State Wait State write2 cycle TDF_MODE = 0 (optimization disabled) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 425 Figure 30-22.TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[15:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 30.14 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the HSMC_MODE register on the corresponding chip select must be set to either ‘10’ (frozen mode) or ‘11’ (ready mode). When the EXNW_MODE is set to ‘00’ (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 30.14.1 Restriction When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Slow Clock Mode (Section 30.15 “Slow Clock Mode” on page 432). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. NWAIT is then examined by the SMC in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on the SMC behavior. 30.14.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after an internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 30-23. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 30-24. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 426 Figure 30-23.Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, A0,A1 FROZEN STATE 4 3 2 1 1 1 1 0 3 2 2 2 2 1 NWE 6 5 4 0 NCS D[15:0] NWAIT Internally synchronized NWAIT signal Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 427 Figure 30-24.Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, A0,A1 FROZEN STATE NCS 4 1 NRD 3 2 2 2 1 0 2 1 0 2 1 0 0 5 5 5 4 3 NWAIT Internally synchronized NWAIT signal Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE = 5, NCS_RD_HOLD = 3 Assertion is ignored 30.14.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 30-25 and Figure 30-26. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 30-26. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 428 Figure 30-25.NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, A0,A1 Wait STATE 4 3 2 1 0 0 0 3 2 1 1 1 NWE 6 5 4 0 NCS D[15:0] NWAIT Internally synchronized NWAIT signal Write cycle EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 429 Figure 30-26.NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, A0,A1 Wait STATE 6 5 4 3 2 1 0 0 6 5 4 3 2 1 1 NCS NRD 0 NWAIT Internally synchronized NWAIT signal Read cycle EXNW_MODE = 11 (Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE = 7 30.14.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 30-27. When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 430 Figure 30-27.NWAIT Latency MCK A[25:2] NBS0, NBS1, A0,A1 WAIT STATE 4 3 2 1 0 0 0 NRD Minimal pulse length NWAIT Internally synchronized NWAIT signal NWAIT latency 2 Resynchronization cycles Read cycle EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 431 30.15 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects. 30.15.1 Slow Clock Mode Waveforms Figure 30-28 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 30-7 indicates the value of read and write parameters in slow clock mode. Figure 30-28. Write/Read Cycles in Slow Clock Mode MCK MCK A[25:2] A[25:2] NBS0, NBS1, A0,A1 NBS0, NBS1, A0,A1 1 NWE NRD 1 1 1 1 NCS NCS NRD_CYCLE = 2 NWE_CYCLE = 3 SLOW CLOCK MODE WRITE Table 30-7. SLOW CLOCK MODE READ Read and Write Timing Parameters in Slow Clock Mode Read Parameters Duration (cycles) Write Parameters Duration (cycles) NRD_SETUP 1 NWE_SETUP 1 NRD_PULSE 1 NWE_PULSE 1 NCS_RD_SETUP 0 NCS_WR_SETUP 0 NCS_RD_PULSE 2 NCS_WR_PULSE 3 NRD_CYCLE 2 NWE_CYCLE 3 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 432 30.15.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters. See Figure 30-29. The external device may not be fast enough to support such timings. Figure 30-30 illustrates the recommended procedure to properly switch from one mode to the other. Figure 30-29.Clock Rate Transition occurs while the SMC is performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, A0, A1 NWE 1 1 1 1 1 1 2 3 2 NCS NWE_CYCLE = 3 SLOW CLOCK MODE WRITE NWE_CYCLE = 7 SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 433 Figure 30-30.Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode Internal signal from PMC MCK A[25:2] NBS0, NBS1, A0, A1 NWE 1 1 1 2 3 2 NCS SLOW CLOCK MODE WRITE IDLE STATE NORMAL MODE WRITE Reload Configuration Wait State 30.16 Register Write Protection To prevent any single software error that may corrupt SMC behavior, selected registers can be write-protected by setting the WPEN bit in the HSMC Write Protection Mode Register (HSMC_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the HSMC Write Protection Status Register (HSMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the HSMC_WPSR. The following registers can be write-protected:  HSMC Setup Register  HSMC Pulse Register  HSMC Cycle Register  HSMC Timings Register  HSMC Mode Register 30.17 NAND Flash Controller Operations 30.17.1 NFC Overview The NAND Flash Controller (NFC) handles all the command, address and data sequences of the NAND low level protocol. An SRAM is used as an internal read/write buffer when data is transferred from or to the NAND. 30.17.2 NFC Control Registers NAND Flash Read and NAND Flash Program operations can be performed through the NFC Command Registers. In order to minimize CPU intervention and latency, commands are posted in a command buffer. This buffer provides zero wait state latency. The detailed description of the command encoding scheme is explained below. The NFC handles an automatic transfer between the external NAND Flash and the chip via the NFC SRAM. It is done via NFC Command Registers. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 434 The NFC Command Registers are very efficient to use. When writing to these registers:  the address of the register (NFCADDR_CMD) is the command used  the data of the register (NFCDATA_ADDT) is the address to be sent to the NAND Flash So, in one single access the command is sent and immediately executed by the NFC. Two commands can even be programmed within a single access (CMD1, CMD2) depending on the VCMD2 value. The NFC can send up to five address cycles. Figure 30-31 below shows a typical NAND Flash Page Read Command of a NAND Flash Memory and correspondence with NFC Address Command Register. Figure 30-31.NFC/NAND Flash Access Example 00h Col. Add1 Col. Add2 30h Row Address Column Address CMD1 Row Add1 Row Add2 Row Add3 ADD cycles (0 to 5) Depends on ACYCLE value CMD2 If VCMD2 = 1 For more details refer to Section 30.17.2.2 “NFC Address Command” on page 436. Reading the NFC command register (to any address) will give the status of the NFC. This is especially useful to know if the NFC is busy, for example. 30.17.2.1 Building NFC Address Command Example The base address is made of HOST_ADDR address. Page read operation example: // Build the Address Command (NFCADDR_CMD) AddressCommand = (HOST_ADDR | NFCCMD=1 | // NFC Command Enable NFCWR=0 |// NFC Read Data from NAND Flash DATAEN=1 | // NFC Data phase Enable. CSID=1 | // Chip Select ID = 1 ACYCLE= 5 | // Number of address cycle. VCMD2=1 | // CMD2 is sent after Address Cycles CMD2=0x30 | // CMD2 = 30h CMD1=0x0) // CMD1 = Read Command = 00h // Set the Address for Cycle 0 HSMC_ADDR = Col. Add1 // Write command with the Address Command built above *AddressCommand = (Col. Add2 |// ADDR_CYCLE1 Row Add1 | // ADDR_CYCLE2 Row Add2 |// ADDR_CYCLE3 Row Add3 )// ADDR_CYCLE4 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 435 30.17.2.2 NFC Address Command Name: NFCADDR_CMD Access: Read/Write Reset: 0x00000000 31 – 23 30 – 29 – 28 – 27 – 26 NFCWR 25 DATAEN 22 21 20 ACYCLE 19 18 VCMD2 17 12 11 10 9 CSID 15 14 13 6 5 16 CMD2 CMD2 7 24 CSID 8 CMD1 4 3 2 CMD1 1 – 0 – • CMD1: Command Register Value for Cycle 1 If NFCCMD is set, when a read or write access occurs, the NFC sends this command. • CMD2: Command Register Value for Cycle 2 If NFCCMD and VCMD2 field are set to one, the NFC sends this command after CMD1. • VCMD2: Valid Cycle 2 Command When set to true, the CMD2 field is issued after the address cycle. • ACYCLE: Number of Address required for the current command When ACYCLE field is different from zero, ACYCLE Address cycles are performed after Command Cycle 1. The maximum number of cycles is 5. • CSID: Chip Select Identifier Chip select used • DATAEN: NFC data phase enable When set to true, the NFC will automatically read or write data after the command. • NFCWR: NFC Write Enable 0: NFC reads data from the NAND Flash. 1: NFC writes data into the NAND Flash. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 436 30.17.2.3 NFC Data Address Name: NFCDATA_ADDT Access: Write-only Reset: 0x00000000 31 30 29 28 27 ADDR_CYCLE4 26 25 24 23 22 21 20 19 ADDR_CYCLE3 18 17 16 15 14 13 12 11 ADDR_CYCLE2 10 9 8 7 6 5 4 3 ADDR_CYCLE1 2 1 0 • ADDR_CYCLE1: NAND Flash Array Address Cycle 1 When less than five address cycles are used, ADDR_CYCLE1 is the first byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE1 is the second byte written to NAND Flash. • ADDR_CYCLE2: NAND Flash Array Address Cycle 2 When less than five address cycles are used, ADDR_CYCLE2 is the second byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE2 is the third byte written to the NAND Flash. • ADDR_CYCLE3: NAND Flash Array Address Cycle 3 When less than five address cycles are used, ADDR_CYCLE3 is the third byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE3 is the fourth byte written to the NAND Flash. • ADDR_CYCLE4: NAND Flash Array Address Cycle 4 When less than five address cycles are used, ADDR_CYCLE4 is the fourth byte written to the NAND Flash. When five address cycles are used, ADDR_CYCLE4 is the fifth byte written to the NAND Flash. Note: If five address cycles are used, the first address cycle is ADDR_CYCLE0. Refer to HSMC_ADDR register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 437 30.17.2.4 NFC DATA Status Name: NFCDATA_STATUS Access: Read-only Reset: 0x00000000 31 – 23 30 – 29 – 28 – 27 NFCBUSY 26 NFCWR 25 DATAEN 22 21 20 ACYCLE 19 18 VCMD2 17 12 11 10 9 CSID 15 14 13 6 5 16 CMD2 CMD2 7 24 CSID 8 CMD1 4 3 CMD1 2 1 – 0 – • CMD1: Command Register Value for Cycle 1 When a Read or Write Access occurs, the Physical Memory Interface drives the IO bus with CMD1 field during the Command Latch cycle 1. • CMD2: Command Register Value for Cycle 2 When VCMD2 field is set to true, the Physical Memory Interface drives the IO bus with CMD2 field during the Command Latch cycle 2. • VCMD2: Valid Cycle 2 Command When set to true, the CMD2 field is issued after addressing cycle. • ACYCLE: Number of Address required for the current command When ACYCLE field is different from zero, ACYCLE Address cycles are performed after Command Cycle 1. • CSID: Chip Select Identifier Chip select used • DATAEN: NFC Data phase enable When set to true, the NFC data phase is enabled. • NFCWR: NFC Write Enable 0: NFC is in read mode. 1: NFC is in write mode. • NFCBUSY: NFC Busy Status Flag If set to true, it indicates that the NFC is busy. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 438 30.17.3 NFC Initialization Prior to any Command and Data Transfer, the SMC User Interface must be configured to meet the device timing requirements.  Write enable Configuration Use NWE_SETUP, NWE_PULSE and NWE_CYCLE to define the write enable waveform according to the device datasheet. Use TADL field in the HSMC_TIMINGS register to configure the timing between the last address latch cycle and the first rising edge of WEN for data input. Figure 30-32.Write Enable Timing Configuration mck wen t WEN_SETUP t WEN_PULSE t WEN_HOLD t WEN_CYCLES Figure 30-33.Write Enable Timing for NAND Flash Device Data Input Mode mck ale wen t ADL  Read Enable Configuration Use NRD_SETUP, NRD_PULSE and NRD_CYCLE to define the read enable waveform according to the device datasheet. Use TAR field in the HSMC_TIMINGS register to configure the timings between the address latch enable falling edge to read the enable falling edge. Use TCLR field in the HSMC_TIMINGS register to configure the timings between the command latch enable falling edge to read the enable falling edge. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 439 Figure 30-34.Read Enable Timing Configuration Working with NAND Flash Device mck cen ale cle ren tCLR tAR  tREN_SETUP tREN_PULSE tREH tREN_CYCLE Ready/Busy Signal Timing configuration working with a NAND Flash device Use TWB field in HSMC_TIMINGS register to configure the maximum elapsed time between the rising edge of the wen signal and the falling edge of the rbn signal. Use TRR field in the HSMC_TIMINGS register to program the number of clock cycles between the rising edge of the rbn signal and the falling edge of the ren signal. Figure 30-35.Ready/Busy Timing Configuration mck rbn ren wen tWB busy tRR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 440 30.17.3.1 NAND Flash Controller Timing Engine When the NFC Command register is written, the NFC issues a NAND Flash Command and optionally performs a data transfer between the NFC SRAM and the NAND Flash device. The NAND Flash Controller Timing Engine guarantees valid NAND Flash timings, depending on the set of parameters decoded from the address bus. These timings are defined in the HSMC_TIMINGS register. For information on the timing used depending on the command, see Figure 30-36. Figure 30-36.NAND Flash Controller Timing Engine Timing Check Engine NFCEN = 1 NFCWR = 1 TADL = 1 Wait TADL NFCEN = 1 NFCWR = 0 TWB ! = 0 Wait TWB NFCEN = 0 VCMD2 = 1 TCLR ! = 0 Wait TCLR !NFCEN = 1 VCMD2 = 0 ACYCLE! = 0 NFCWR = 1 TADL ! = 0 Wait TADL !NFCEN = 1 VCMD2 = 0 ACYCLE! = 0 NFCWR = 0 TAR ! = 0 Wait TAR !NFCEN = 1 VCMD2 = 0 ACYCLE! = 0 TCLR ! = 0 Wait TCLR See the NFC Address Command register description and the HSMC Timings Register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 441 30.17.4 NFC SRAM 30.17.4.1 NFC SRAM Mapping If the NFC is used to read and write Data from and to the NAND Flash, the configuration depends on the page size, the relevant field is PAGESIZE in HSMC_CFG register. See Table 30-8 to Table 30-12 for detailed mapping. The NFC SRAM size is 8 Kbytes. The NFC can handle the NAND Flash with a page size of 8 Kbytes or of a lower size (such as 2 Kbytes for example). In case of a 4-Kbyte or lower page size, the NFC SRAM can be split into two banks. The field BANK in the HSMC_BANK register is used to select where NAND flash data are written or read. For 8 Kbytes page size this field is not relevant. Note that a “ping-pong” mode (write or read to a bank while the NFC writes or reads to another bank) is accessible with the NFC (using two different banks). If the NFC is not used, the NFC SRAM can be used for a general purpose by the application. Table 30-8. NFC SRAM Bank Mapping for 512 bytes Offset Use Access 0x00000000–0x000001FF Main Area Bank 0 Read/Write 0x00000200–0x000003FF Spare Area Bank 0 Read/Write 0x00001200–0x000013FF Main Area Bank 1 Read/Write 0x00001400–0x000015FF Spare Area Bank 1 Read/Write Table 30-9. NFC SRAM Bank Mapping for 1 Kbyte Offset Use Access 0x00000000–0x000003FF Main Area Bank 0 Read/Write 0x00000400–0x000005FF Spare Area Bank 0 Read/Write 0x00001200–0x000015FF Main Area Bank 1 Read/Write 0x00001600–0x000017FF Spare Area Bank 1 Read/Write Table 30-10. NFC SRAM Bank Mapping for 2 Kbytes Offset Use Access 0x00000000–0x000007FF Main Area Bank 0 Read/Write 0x00000800–0x000009FF Spare Area Bank 0 Read/Write 0x00001200–0x000019FF Main Area Bank 1 Read/Write 0x00001A00–0x00001BFF Spare Area Bank 1 Read/Write Table 30-11. NFC SRAM Bank Mapping for 4 Kbytes Offset Use Access 0x00000000–0x00000FFF Main Area Bank 0 Read/Write 0x00001000–0x000011FF Spare Area Bank 0 Read/Write 0x00001200–0x000021FF Main Area Bank 1 Read/Write 0x00002200–0x000023FF Spare Area Bank 1 Read/Write SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 442 Table 30-12. NFC SRAM Bank Mapping for 8 Kbytes, only one bank is available Offset Use Access 0x00000000–0x00001FFF Main Area Bank 0 Read/Write 0x00002000–0x000023FF Spare Area Bank 0 Read/Write 30.17.4.2 NFC SRAM Access Prioritization Algorithm When the NAND Flash Controller (NFC) is reading from or writing to an NFC SRAM bank, the other bank is available. If an NFC SRAM access occurs when the NFC performs a read or write operation in the same bank, then the access is discarded. The write operation is not performed. The read operation returns undefined data. If this situation is encountered, the AWB status flag located in the NFC Status Register is raised and indicates that a shared resource access violation has occurred. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 443 30.17.5 NAND Flash Operations This section describes the software operations needed to issue commands to the NAND Flash device and to perform data transfers using the NFC. 30.17.5.1 Page Read Figure 30-37.Page Read Flow Chart Configure the device writing in the User Interface Using NFC Write the NFC Command registers Enable XFRDONE interrupt (SMC_IER) Wait for Interrupt Copy data from NFC SRAM to application memory (via DMA for example) Check Error Correcting Codes Note that, instead of using the interrupt, one can poll the NFCBUSY flag. For more information on the NFC Control Register, see Section 30.17.2.2 “NFC Address Command”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 444 30.17.5.2 Program Page Figure 30-38.Program Page Flow Chart Configure the device writing in the User interface Write data in the NFC SRAM (CPU or DMA) Enable XFRDONE Write the Command Register through the AHB interface Wait for interrupt Write ECC Wait for Ready/Busy interrupt Writing the ECC cannot be done using the NFC; it needs to be done “manually”. Note that, instead of using the interrupt, one can poll the NFCBUSY flag. For more information on the NFC Control Register, see Section 30.17.2.2 “NFC Address Command”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 445 30.18 PMECC Controller Functional Description The Programmable Multibit Error Correcting Code (PMECC) controller is a programmable binary BCH (Bose, Chaudhuri and Hocquenghem) encoder/decoder. This controller can be used to generate redundancy information for both SLC and MLC NAND devices. It supports redundancy for correction of 2, 4, 8, 12, or 24 errors per sector of data. The sector size is programmable and can be set to 512 bytes or 1024 bytes. The PMECC module generates redundancy at encoding time, when a NAND write page operation is performed. The redundancy is appended to the page and written in the spare area. This operation is performed by the processor. It moves the content of the PMECCX registers into the NAND flash memory. The number of registers depends on the selected error correction capability (see Table 30-13 on page 448). This operation shall be executed for each sector. At decoding time, the PMECC module generates the remainders of the received codeword by the minimal polynomials. When all remainders for a given sector are set to zero, no error occurred. When the remainders are different from zero, the codeword is corrupted and further processing is required. The PMECC module generates an interrupt indicating that an error occurred. The processor must read the PMECC Interrupt Status Register (HSMC_PMECCISR). This register indicates which sector is corrupted. The processor must execute the following decoding steps to find the error location within a sector: 1. Syndrome computation. 2. Finding the error location polynomial. 3. Finding the roots of the error location polynomial. All decoding steps involve finite field computation. It means that a library of finite field arithmetic must be available to perform addition, multiplication and inversion. These arithmetic operations can be performed through the use of a memory mapped look-up table, or direct software implementation. The software implementation presented is based on look-up tables. Two tables named gf_log and gf_antilog are used. If alpha is the primitive element of the field, then a power of alpha is in the field. Assuming that beta = alpha ^ index, then beta belongs to the field, and gf_log(beta) = gf_log(alpha ^ index) = index. The gf_antilog table provides exponent inverse of the element; if beta = alpha ^ index, then gf_antilog(index) = beta. The first step consists in the syndrome computation. The PMECC module computes the remainders and the software must substitute the power of the primitive element. The procedure implementation is given in Section 30.19.1 “Remainder Substitution Procedure” on page 452. The second step is the most software intensive. It is the Berlekamp’s iterative algorithm for finding the error-location polynomial. The procedure implementation is given in Section 30.19.2 “Find the Error Location Polynomial Sigma(x)” on page 453. The Last step is finding the root of the error location polynomial. This step can be very software intensive. Indeed there is no straightforward method of finding the roots, except evaluating each element of the field in the error location polynomial. However, a hardware accelerator can be used to find the roots of the polynomial. The PMERRLOC module provides this kind of hardware acceleration. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 446 Figure 30-39.Software Hardware Multibit Error Correction Dataflow NAND Flash PROGRAM PAGE Operation Software NAND Flash READ PAGE Operation Hardware Accelerator Configure PMECC : error correction capability sector size/page size NAND write field set to true spare area desired layout Move the NAND Page to external Memory whether using DMA or Processor Software Hardware Accelerator Configure PMECC : error correction capability sector size/page size NAND write field set to false spare area desired layout PMECC computes redundancy as the data is written into external memory Move the NAND Page from external Memory whether using DMA or Processor PMECC computes polynomial remainders as the data is read from external memory PMECC modules indicate if at least one error is detected. Copy redundancy from PMECC user interface to user-defined spare area using DMA or Processor. If a sector is corrupted use the substitute() function to determine the syndromes. When the table of syndromes is completed, use the get_sigma() function to get the error location polynomial. Find the error positions finding the roots of the error location polynomial And correct the bits. This step can be hardware-assisted using the PMERRLOC module. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 447 30.18.1 MLC/SLC Write Page Operation Using PMECC When an MLC write page operation is performed, the PMECC controller is configured with the NANDWR field of the PMECCFG register set to one. When the NAND spare area contains file system information and redundancy (PMECCx), the spare area is error protected, then the SPAREEN bit of the PMECCFG register is set to one. When the NAND spare area contains only redundancy information, the SPAREEN bit is set to zero. When the write page operation is terminated, the user writes the redundancy in the NAND spare area. This operation can be done with DMA assistance. Table 30-13. Relevant Redundancy Registers BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 0 PMECC0 PMECC0 1 PMECC0, PMECC1 PMECC0, PMECC1 2 PMECC0, PMECC1, PMECC2, PMECC3 PMECC0, PMECC1, PMECC2, PMECC3 3 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6 4 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9 PMECC0, PMECC1, PMECC2, PMECC3, PMECC4, PMECC5, PMECC6, PMECC7, PMECC8, PMECC9, PMECC10 Table 30-14. Number of Relevant ECC Bytes per Sector, Copied from LSByte to MSByte BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 0 4 bytes 4 bytes 1 7 bytes 7 bytes 2 13 bytes 14 bytes 3 20 bytes 21 bytes 4 39 bytes 42 bytes 30.18.1.1 SLC/MLC Write Operation with Spare Enable Bit Set When the SPAREEN field of the PMECCFG register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. This mode is entered by writing 1 in the DATA field of the PMECCTRL register. When the encoding process is over, the redundancy shall be written to the spare area in user mode. The USER field of the PMECCTRL register must be set to one. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 448 Figure 30-40.NAND Write Operation with Spare Encoding Write NAND operation with SPAREEN set to one pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 sparesize Sector 3 Spare 512 or 1024 bytes ecc_area start_addr end_addr ECC computation enable signal 30.18.1.2 SLC/MLC Write Operation with Spare Disable When the SPAREEN field of PMECCFG is set to zero, the spare area is not encoded with the stream of data. This mode is entered by writing 1 to the DATA field of the PMECCTRL register. Figure 30-41.NAND Write Operation Write NAND operation with SPAREEN set to zero pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 Sector 3 512 or 1024 bytes ECC computation enable signal 30.18.2 MLC/SLC Read Page Operation Using PMECC Table 30-15. Relevant Remainder Registers BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 0 PMECCREM0 PMECCREM0 1 PMECCREM0, PMECCREM1 PMECCREM0, PMECCREM1 2 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3 3 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 449 Table 30-15. Relevant Remainder Registers (Continued) BCH_ERR Field Sector Size Set to 512 Bytes Sector Size Set to 1024 Bytes 4 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7, PMECCREM8, PMECCREM9, PMECCREM10, PMECCREM11 PMECCREM0, PMECCREM1, PMECCREM2, PMECCREM3, PMECCREM4, PMECCREM5, PMECCREM6, PMECCREM7, PMECCREM8, PMECCREM9, PMECCREM10, PMECCREM11 30.18.2.1 MLC/SLC Read Operation with Spare Decoding When the spare area is protected, it contains valid data. As the redundancy may be included in the middle of the information stream, the user shall program the start address and the end address of the ECC area. The controller will automatically skip the ECC area. This mode is entered writing 1 in the DATA field of the PMECCTRL register. When the page has been fully retrieved from the NAND, the ECC area shall be read using the user mode, writing 1 to the USER field of the PMECCTRL register. Figure 30-42.Read Operation with Spare Decoding Read NAND operation with SPAREEN set to One and AUTO set to Zero pagesize = n * sectorsize Sector 0 Sector 1 Sector 2 sparesize Sector 3 Spare 512 or 1024 bytes ecc_area start_addr end_addr Remainder computation enable signal 30.18.2.2 MLC/SLC Read Operation If the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. This mode is entered writing 1 in the DATA field of the PMECCTRL register. When AUTO field is set to one, the ECC is retrieved automatically; otherwise, the ECC must be read using the user mode. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 450 Figure 30-43.Read Operation Read NAND operation with SPAREEN set to Zero and AUTO set to One pagesize = n * sectorsize Sector 0 Sector 1 sparesize Sector 2 Sector 3 Spare 512 or 1024 bytes ecc_area ECC_BLK2 ECC_BLK1 ECC_BLK0 ECC_BLK3 end_addr start_addr Remainder computation enable signal 30.18.2.3 MLC/SLC User Read ECC Area This mode allows a manual retrieve of the ECC. It is entered writing 1 in the USER field of the PMECCTRL register. Figure 30-44.Read User Mode ecc_area_size ECC ecc_area addr = 0 end_addr Remainder computation enable signal SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 451 30.18.2.4 MLC Controller Working with NAND Flash Controller Table 30-16. MLC Controller Configuration when the Host Controller is Used NFC Transfer Type PMECC RSPARE WSPARE SPAREEN AUTO User Mode Program Page main area is protected, spare is not protected, spare is written manually 0 0 0 0 Not used Program Page main area is protected, spare is protected, spare is written by NFC 0 1 1 0 Not used Read Page main area is protected, spare is not protected, spare is not retrieved by NFC 0 0 0 0 Used Read Page main area is protected, spare is not protected, spare is retrieved by NFC 1 0 0 1 Not used Read Page main area is protected, spare is protected, spare is retrieved by NFC 1 0 1 0 Used 30.19 Software Implementation 30.19.1 Remainder Substitution Procedure The substitute function evaluates the remainder polynomial, with different values of the field primitive element. The addition arithmetic operation is performed with the exclusive OR. The multiplication arithmetic operation is performed through the gf_log and gf_antilog look-up tables. The REM2NP1 and REMN2NP3 fields of the PMECCREMN registers contain only odd remainders. Each bit indicates whether the coefficient of the remainder polynomial is set to zero or not. NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. si[] is a table that holds the current syndrome value. An element of that table belongs to the field. This is also a shared variable for the next step of the decoding operation. oo[] is a table that contains the degree of the remainders. int { int int for { substitute() i; j; (i = 1; i < 2 * NB_ERROR_MAX; i++) si[i] = 0; } for (i = 1; i < 2*NB_ERROR; i++) { for (j = 0; j < oo[i]; j++) { SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 452 if (REM2NPX[i][j]) { si[i] = gf_antilog[(i * j)%NB_FIELD_ELEMENTS] ^ si[i]; } } } return 0; } 30.19.2 Find the Error Location Polynomial Sigma(x) The sample code below gives a Berlekamp iterative procedure for finding the value of the error location polynomial. The input of the procedure is the si[] table defined in the remainder substitution procedure. The output of the procedure is the error location polynomial named smu (sigma mu). The polynomial coefficients belong to the field. The smu[NB_ERROR+1][] is a table that contains all these coefficients. NB_ERROR_MAX defines the maximum value of the error correcting capability. NB_ERROR defines the error correcting capability selected at encoding/decoding time. NB_FIELD_ELEMENTS defines the number of elements in the field. int get_sigma() { int i; int j; int k; /* mu */ int mu[NB_ERROR_MAX+2]; /* sigma ro */ int sro[2*NB_ERROR_MAX+1]; /* discrepancy */ int dmu[NB_ERROR_MAX+2]; /* delta order */ int delta[NB_ERROR_MAX+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* First Row */ /* */ /* Mu */ mu[0] = -1; /* Actually -1/2 */ /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ delta[0] = (mu[0] * 2 - lmu[0]) >> 1; /* */ /* Second Row */ /* */ /* Mu */ SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 453 mu[1] = 0; /* Sigma(x) set to 1 */ for (i = 0; i < (2*NB_ERROR_MAX+1); i++) smu[1][i] = 0; smu[1][0] = 1; /* discrepancy set to Syndrome 1 */ dmu[1] = si[1]; /* polynom order set to 0 */ lmu[1] = 0; /* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i XMEMSIZE ) otherwise 32.6.9.3 Vertical Scaler The YMEMSIZE field of the LCDC_HEOCFG4 register indicates the vertical size minus one of the image in the system memory. The YSIZE field of the LCDC_HEOCFG3 register contains the vertical size minus one of the window. The SCALEN field of the LCDC_HEOCFG13 register is set to one. The scaling factor is programmed in the YFACTOR field of the LCDC_HEOCFG13 register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 590 8 × 256 × YMEMSIZE – 256 × YPHIDEF YFACTOR 1st = floor  --------------------------------------------------------------------------------------------------------   YSIZE YFACTOR 1st = YFACTOR 1st + 1 YFACTOR 1st × YSIZE + 256 × YPHIDEF YMEMSIZE max = floor  ----------------------------------------------------------------------------------------------------------   2048 YFACTOR = YFACTOR 1st – 1 YFACTOR = YFACTOR 1st  when ( YMEMSIZEmax > YMEMSIZE ) otherwise 32.6.10 Hardware Cursor The LCD module integrates a hardware cursor database. This layer features only a minimal set of color among 1, 2, 4 and 8 bpp palletized and 16 bpp to 32 bpp true color. The cursor size is limited to 128 x 128 pixels. 32.6.11 Color Combine Unit 32.6.11.1 Window Overlay The LCD module provides hardware support for multiple “overlay plane” that can be used to display windows on top of the image without destroying the image located below. The overlay image can use any color depth. Using the overlay alleviates the need to re-render the occluded portion of the image. When pixels are combined together through the alpha blending unit, a new color is created. This new pixel is called an iterated pixel and is passed to the next blending stage. Then, this pixel may be combined again with another pixel. The VIDPRI field located in the LCDC_HEOCFG12 register configures the video priority algorithm used to display the layers. When VIDPRI field is set to zero, the OVR1 layer is located above the HEO layer. When VIDPRI field is set to one, OVR1 is located below the HEO layer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 591 Figure 32-9. Overlay Example with Two Different Video Prioritization Algorithms HEO width OVR1 width Base width Base height o0(x,y) HEO o1(x,y) HEO height Overlay1 OVR1 OVR1 height HCC Base Image Video Prioritization Algorithm 1 : HCC > OVR1 > HEO > BASE Base Image HEO HCC Overlay1 OVR1 Video Prioritization Algorithm 2 : HCC > HEO > OVR1 > BASE 32.6.11.2 Base Layer, with Window Overlay Optimization When the base layer is combined with at least one active overlay, the whole base layer frame is retrieved from the memory though it is not visible. A set of registers is used to disable the Base DMA when this condition is met. These registers are listed below:  LCDC_CFG5: DISCXPOS field discard area horizontal position  LCDC_CFG5: DISCYPOS field discard area vertical position  LCDC_CFG6: DISCXSIZE field discard area horizontal size  LCDC_CFG6: DISCYSIZE field discard area vertical size  LCDC_CFG4: DISCEN field discard area enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 592 Figure 32-10.Base Layer Discard Area Base width Base height Base Image discxsize Base width Base height {discxpos, discypos} Overlay1 discysize Discarded Area Base Image HEO width Base width Base height HEO Video HEO height Base Image SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 593 32.6.11.3 Overlay Blending The blending function requires two pixels (one iterated from the previous blending stage and one from the current overlay color) and a set of blending configuration parameters. These parameters define the color operation. Figure 32-11.Alpha Blender Function iter[n-1] GA OVR From LAEN Shadow REVALPHA Registers ITER ITER2BL CRKEY INV DMA GAEN RGBKEY RGBMASK OVRDEF la ovr blending function iter[n] Figure 32-12.Alpha Blender Database la ovr iter[n-1] OVR ITER OVRDEF GA "0" "0" GAEN 0 0 0 DMA LAEN "0" 0 0 Alpha * ovr + (1 - Alpha) * iter[n-1] REVALPHA ovr RGBKEY RGBMASK CRKEY ovr iter[n-1] 0 MATCH LOGIC 0 Inverted INV 0 iter[n] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 594 32.6.11.4 Global Alpha Blender Figure 32-13.Global Alpha Blender base ovr1la ovr1 iter[n-1] la ovr2la ovr2 heola heo hcrla hcr ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] iter[n-1] la ovr blending function iter[n] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 595 32.6.11.5 Window Blending Figure 32-14.256-level Alpha Blending Base Image OVR1 25 % HEO 75 % Video Prioritization Algorithm 1 : OVR1 > HEO > BASE 32.6.11.6 Color Keying Color keying involves a method of bit-block image transfer (Blit). This entails blitting one image onto another where not all the pixels are copied. Blitting usually involves two bitmaps, a source bitmap and a destination bitmap. A raster operation (ROP) is performed to define whether the iterated color or the overlay color is to be visible or not. Source Color Keying If the masked overlay color matches the color key then the iterated color is selected, Source Color Keying is activated using the following configuration.  Select the Overlay to Blit  Set DSTKEY field to zero  Activate Color Keying setting CRKEY field to 1  Program Color Key writing RKEY, GKEY and BKEY fields  Program Color Mask writing RKEY, GKEY and BKEY fields When the Mask register is set to zero, the comparison is disabled and the raster operation is activated. Destination Color Keying If the iterated masked color matches the color key then the overlay color is selected, Destination Color Keying is activated using the following configuration:  Select the Overlay to Blit  Set DSTKEY field to one  Activate Color Keying setting CRKEY field to 1  Program Color Key writing RKEY, GKEY and BKEY fields  Program Color Mask writing RKEY, GKEY and BKEY fields When the Mask register is set to zero, the comparison is disabled and the raster operation is activated. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 596 32.6.12 LCDC PWM Controller This block generates the LCD contrast control signal (LCD_PWM) to make possible the control of the display's contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be converted to an analog voltage with a simple passive filter. The PWM module has a free-running counter whose value is compared against a compare register (PWMCVAL field of the LCDC_LCDCFG6 register). If the value in the counter is less than that in the register, the output brings the value of the polarity (PWMPOL field) bit in the PWM control register: LCDC_LCDCFG6. Otherwise, the opposite value is output. Thus, a periodic waveform with a pulse width proportional to the value in the compare register is generated. Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM counter cycles. Thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) × VDD can be obtained (for the positive polarity case, or between (1/256) × VDD and VDD for the negative polarity case). Other voltage values can be obtained by adding active external circuitry. For PWM mode, the counter frequency can be adjusted to four different values using the PWMPS field of the LCDC_LCDCFG6 register. The PWM module can be fed with the slow clock or the system clock, depending on the CLKPWMSEL field of the LCDC_CFG0 register. 32.6.13 Post Processing Controller The output stream of pixels can be either displayed on the screen or written to the memory using the Post Processing Controller (PPC). When the PPC is used, the screen display is disabled, but synchronization signals remain active (if enabled). The stream of pixel can be written in RGB mode or encoded in YCbCr 422 mode. A programmable color space conversion stage is available. ·· Y CSCYR CSCYG CSCYB R Yoff U = CSCUR CSCUG CSCUB • G + Uoff V CSCVR CSCVG CSCUB B Voff 32.6.14 LCD Overall Performance 32.6.14.1 Color Lookup Table (CLUT) Table 32-48. CLUT Pixel Performance CLUT MODE Pixels/Cycle ROTATION SCALING 1 bpp 64 Not supported Supported 2 bpp 32 Not supported Supported 3 bpp 16 Not supported Supported 4 bpp 8 Not supported Supported SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 597 32.6.14.2 RGB Mode Fetch Performance Table 32-49. RGB Mode Performance Pixels/Cycle Rotation Peak Random Memory Access (pixels/cycle) RGB Mode SCALING Burst Mode or Rotation Optimization Available Memory Burst Mode Rotation Optimization(1) Normal Mode 12 bpp 4 1 0.2 Supported 16 bpp 4 1 0.2 Supported 18 bpp 2 1 0.2 Supported 18 bpp RGB PACKED 2.666 Not supported 0.2 Supported 19 bpp 2 1 0.2 Supported 19 bpp PACKED 2.666 Not Supported 0.2 Supported 24 bpp 2 1 0.2 Supported 24 bpp PACKED 2.666 Not Supported 0.2 Supported 25 bpp 2 1 0.2 Supported 32 bpp 2 1 0.2 Supported Note: 1. Rotation optimization = AHB lock asserted on consecutive single access. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 598 32.6.14.3 YUV Mode Fetch Performance Table 32-50. Single Stream for 0 Wait State Memory Pixels/Cycle Rotation Peak Random Memory Access (pixels/cycle) YUV Mode SCALING burst mode or rotation optimization is available memory burst mode Rotation Optimization Normal Mode 32 bpp AYUV 2 1 0.2 Supported 16 bpp 422 4 Not Supported Not Supported Supported Note: rotation optimization = AHB lock asserted on consecutive single access Table 32-51. Multiple Stream for 0 Wait State Memory Comp/Cycle Rotation Peak Random Memory Access (pixels/cycle) YUV Mode SCALING burst mode or rotation optimization is available memory burst mode Rotation Optimization Normal Mode 16 bpp 422 semiplanar 8 Y, 4 UV 1 Y, 1 UV (2 streams) 0.2 Y 0.2 UV (2 streams) 16 bpp 422 planar 8 Y, 8 U, 8 V 1 Y, 1 U, 1 V (3 streams) 0.2 Y, 0.2 U, 0.2 V (3 streams) Supported 12 bpp 4:2:0 semiplanar 8 Y, 4 UV 1 Y, 1 UV (2 streams) 0.2 Y 0.2 UV (2 streams) 12 bpp 4:2:0 planar 8 Y, 8 U, 8 V 1 Y, 1 U, 1 V (3 streams) 0.2 Y, 0.2 U, 0.2 V (3 streams) Supported Note: Supported Supported In order to provide more bandwidth, when multiple streams are used to transfer Y, UV, U or V components, two AHB interfaces are recommended or multiple AXI ID are required. Table 32-52. YUV Planar Overall Performance 1 AHB Interface for 0 Wait State Memory Pix/Cycle YUV Mode Rotation Peak Random Memory Access (pixels/cycle) SCALING burst mode or rotation optimization is available memory burst mode Rotation Optimization Normal Mode 16 bpp 422 semiplanar 4 0.66 0.132 Supported 16 bpp 422 planar 4 0.5 0.1 Supported 12 bpp 4:2:0 semiplanar 5.32 0.8 0.16 Supported 12 bpp 4:2:0 planar 5.32 0.66 0.132 Supported In order to provide more bandwidth, when multiple streams are used to transfer Y, UV, U or V components, two AHB interfaces are recommended or multiple AXI ID are required. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 599 32.6.15 Input FIFO The LCD module includes one input FIFO per overlay. These input FIFOs are used to buffer the AHB burst and serialize the stream of pixels. 32.6.16 Output FIFO The LCD module includes one output FIFO that stores the blended pixel. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 600 32.6.17 Output Timing Generation 32.6.17.1 Active Display Timing Mode Figure 32-15.Active Display Timing LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] HSW VSW VBP HBP LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] HSW HBP HFP PPL HSW HBP LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_BIAS_DEN LCD_DAT[23:0] PPL HFP HSW VFP SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 601 Figure 32-16.Vertical Synchronization Timing (part 1) VSPDLYS = 0 VSPDLYE = 0 VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VSPSU = 0 VBP HBP VBP HBP VBP HBP VBP HBP VBP HBP VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 0 VSPDLYE = 1 VSW VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 1 VSW VSPSU = 0 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VSPSU = 1 VSPHO = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSW SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 602 Figure 32-17.Vertical Synchronization Timing (part 2) VSPDLYS = 1 VSPDLYE = 0 VSPSU = 0 VSPHO = 1 VSPSU = 1 VSPHO = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSPDLYS = 1 VSPDLYE = 0 VSW VBP HBP VBP HBP LCD_PCLK LCD_VSYNC LCD_HSYNC HSW VSW SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 603 Figure 32-18.DISP Signal Timing Diagram VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC lcd display off LCD_DISP lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 0 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display off lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display off lcd display on VSPDLYE = 0 VSPHO = 0 DISPPOL = 0 DISPDLY = 1 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DISP lcd display on lcd display off SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 604 32.6.18 Output Format 32.6.18.1 Active Mode Output Pin Assignment Table 32-53. Active Mode Output with 24 bits Bus Interface Configuration Pin ID TFT 24 bits TFT 18 bits TFT 16 bits TFT 12 bits LCD_DAT[23] R[7] – – – LCD_DAT[22] R[6] – – – LCD_DAT[21] R[5] – – – LCD_DAT[20] R[4] – – – LCD_DAT[19] R[3] – – – LCD_DAT[18] R[2] – – – LCD_DAT[17] R[1] R[5] – – LCD_DAT[16] R[0] R[4] – – LCD_DAT[15] G[7] R[3] R[4] – LCD_DAT[14] G[6] R[2] R[3] – LCD_DAT[13] G[5] R[1] R[2] – LCD_DAT[12] G[4] R[0] R[1] – LCD_DAT[11] G[3] G[5] R[0] R[3] LCD_DAT[10] G[2] G[4] G[5] R[2] LCD_DAT[9] G[1] G[3] G[4] R[1] LCD_DAT[8] G[0] G[2] G[3] R[0] LCD_DAT[7] B[7] G[1] G[2] G[3] LCD_DAT[6] B[6] G[0] G[1] G[2] LCD_DAT[5] B[5] B[5] G[0] G[1] LCD_DAT[4] B[4] B[4] B[4] G[0] LCD_DAT[3] B[3] B[3] B[3] B[3] LCD_DAT[2] B[2] B[2] B[2] B[2] LCD_DAT[1] B[1] B[1] B[1] B[1] LCD_DAT[0] B[0] B[0] B[0] B[0] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 605 32.7 LCD Controller (LCDC) User Interface Table 32-54. Register Mapping Offset Register Name Access Reset 0x00000000 LCD Controller Configuration Register 0 LCDC_LCDCFG0 Read-write 0x00000000 0x00000004 LCD Controller Configuration Register 1 LCDC_LCDCFG1 Read-write 0x00000000 0x00000008 LCD Controller Configuration Register 2 LCDC_LCDCFG2 Read-write 0x00000000 0x0000000C LCD Controller Configuration Register 3 LCDC_LCDCFG3 Read-write 0x00000000 0x00000010 LCD Controller Configuration Register 4 LCDC_LCDCFG4 Read-write 0x00000000 0x00000014 LCD Controller Configuration Register 5 LCDC_LCDCFG5 Read-write 0x00000000 0x00000018 LCD Controller Configuration Register 6 LCDC_LCDCFG6 Read-write 0x00000000 0x0000001C Reserved – – – 0x00000020 LCD Controller Enable Register LCDC_LCDEN Write-only – 0x00000024 LCD Controller Disable Register LCDC_LCDDIS Write-only – 0x00000028 LCD Controller Status Register LCDC_LCDSR Read-only 0x00000000 0x0000002C LCD Controller Interrupt Enable Register LCDC_LCDIER Write-only – 0x00000030 LCD Controller Interrupt Disable Register LCDC_LCDIDR Write-only – 0x00000034 LCD Controller Interrupt Mask Register LCDC_LCDIMR Read-only 0x00000000 0x00000038 LCD Controller Interrupt Status Register LCDC_LCDISR Read-only 0x00000000 0x0000003C LCD Controller Attribute Register LCDC_ATTR Write-only – 0x00000040 Base Layer Channel Enable Register LCDC_BASECHER Write-only 0x00000000 0x00000044 Base Layer Channel Disable Register LCDC_BASECHDR Write-only 0x00000000 0x00000048 Base Layer Channel Status Register LCDC_BASECHSR Read-only 0x00000000 0x0000004C Base Layer Interrupt Enable Register LCDC_BASEIER Write-only 0x00000000 0x00000050 Base Layer Interrupt Disabled Register LCDC_BASEIDR Write-only 0x00000000 0x00000054 Base Layer Interrupt Mask Register LCDC_BASEIMR Read-only 0x00000000 0x00000058 Base Layer Interrupt status Register LCDC_BASEISR Read-only 0x00000000 0x0000005C Base DMA Head Register LCDC_BASEHEAD Read-write 0x00000000 0x00000060 Base DMA Address Register LCDC_BASEADDR Read-write 0x00000000 0x00000064 Base DMA Control Register LCDC_BASECTRL Read-write 0x00000000 0x00000068 Base DMA Next Register LCDC_BASENEXT Read-write 0x00000000 0x0000006C Base Configuration register 0 LCDC_BASECFG0 Read-write 0x00000000 0x00000070 Base Configuration register 1 LCDC_BASECFG1 Read-write 0x00000000 0x00000074 Base Configuration register 2 LCDC_BASECFG2 Read-write 0x00000000 0x00000078 Base Configuration register 3 LCDC_BASECFG3 Read-write 0x00000000 0x0000007C Base Configuration register 4 LCDC_BASECFG4 Read-write 0x00000000 0x00000080 Base Configuration register 5 LCDC_BASECFG5 Read-write 0x00000000 0x00000084 Base Configuration register 6 LCDC_BASECFG6 Read-write 0x00000000 0x88-0x13C Reserved – – – 0x00000140 Overlay 1 Channel Enable Register LCDC_OVRCHER1 Write-only 0x00000000 0x00000144 Overlay 1 Channel Disable Register LCDC_OVRCHDR1 Write-only 0x00000000 0x00000148 Overlay 1 Channel Status Register LCDC_OVRCHSR1 Read-only 0x00000000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 606 Table 32-54. Register Mapping (Continued) Offset Register Name Access Reset 0x0000014C Overlay 1 Interrupt Enable Register LCDC_OVRIER1 Write-only 0x00000000 0x00000150 Overlay 1 Interrupt Disable Register LCDC_OVRIDR1 Write-only 0x00000000 0x00000154 Overlay 1 Interrupt Mask Register LCDC_OVRIMR1 Read-only 0x00000000 0x00000158 Overlay 1 Interrupt Status Register LCDC_OVRISR1 Read-only 0x00000000 0x0000015C Overlay 1 DMA Head Register LCDC_OVRHEAD1 Read-write 0x00000000 0x00000160 Overlay 1 DMA Address Register LCDC_OVRADDR1 Read-write 0x00000000 0x00000164 Overlay 1 DMA Control Register LCDC_OVRCTRL1 Read-write 0x00000000 0x00000168 Overlay 1 DMA Next Register LCDC_OVRNEXT1 Read-write 0x00000000 0x0000016C Overlay 1 Configuration 0 Register LCDC_OVR1CFG0 Read-write 0x00000000 0x00000170 Overlay 1 Configuration 1 Register LCDC_OVR1CFG1 Read-write 0x00000000 0x00000174 Overlay 1 Configuration 2 Register LCDC_OVR1CFG2 Read-write 0x00000000 0x00000178 Overlay 1 Configuration 3 Register LCDC_OVR1CFG3 Read-write 0x00000000 0x0000017C Overlay 1 Configuration 4 Register LCDC_OVR1CFG4 Read-write 0x00000000 0x00000180 Overlay 1 Configuration 5 Register LCDC_OVR1CFG5 Read-write 0x00000000 0x00000184 Overlay 1 Configuration 6 Register LCDC_OVR1CFG6 Read-write 0x00000000 0x00000188 Overlay 1 Configuration 7 Register LCDC_OVR1CFG7 Read-write 0x00000000 0x0000018C Overlay 1 Configuration 8Register LCDC_OVR1CFG8 Read-write 0x00000000 0x00000190 Overlay 1 Configuration 9 Register LCDC_OVR1CFG9 Read-write 0x00000000 0x194-0x23C Reserved – – – 0x00000240 Overlay 2 Channel Enable Register LCDC_OVRCHER2 Write-only 0x00000000 0x00000244 Overlay 2 Channel Disable Register LCDC_OVRCHDR2 Write-only 0x00000000 0x00000248 Overlay 2 Channel Status Register LCDC_OVRCHSR2 Read-only 0x00000000 0x0000024C Overlay 2 Interrupt Enable Register LCDC_OVRIER2 Write-only 0x00000000 0x00000250 Overlay 2 Interrupt Disable Register LCDC_OVRIDR2 Write-only 0x00000000 0x00000254 Overlay 2 Interrupt Mask Register LCDC_OVRIMR2 Read-only 0x00000000 0x00000258 Overlay 2 Interrupt status Register LCDC_OVRISR2 Read-only 0x00000000 0x0000025C Overlay 2 DMA Head Register LCDC_OVRHEAD2 Read-write 0x00000000 0x00000260 Overlay 2 DMA Address Register LCDC_OVRADDR2 Read-write 0x00000000 0x00000264 Overlay 2 DMA Control Register LCDC_OVRCTRL2 Read-write 0x00000000 0x00000268 Overlay 2 DMA Next Register LCDC_OVRNEXT2 Read-write 0x00000000 0x0000026C Overlay 2 Configuration 0 Register LCDC_OVR2CFG0 Read-write 0x00000000 0x00000270 Overlay 2 Configuration 1 Register LCDC_OVR2CFG1 Read-write 0x00000000 0x00000274 Overlay 2 Configuration 2 Register LCDC_OVR2CFG2 Read-write 0x00000000 0x00000278 Overlay 2 Configuration 3 Register LCDC_OVR2CFG3 Read-write 0x00000000 0x0000027C Overlay 2 Configuration 4 Register LCDC_OVR2CFG4 Read-write 0x00000000 0x00000280 Overlay 2 Configuration 5 Register LCDC_OVR2CFG5 Read-write 0x00000000 0x00000284 Overlay 2 Configuration 6 Register LCDC_OVR2CFG6 Read-write 0x00000000 0x00000288 Overlay 2 Configuration 7 Register LCDC_OVR2CFG7 Read-write 0x00000000 0x0000028C Overlay 2 Configuration 8 Register LCDC_OVR2CFG8 Read-write 0x00000000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 607 Table 32-54. Register Mapping (Continued) Offset 0x00000290 0x294-33C Register Overlay 2 Configuration 9 Register Reserved Name Access Reset LCDC_OVR2CFG9 Read-write 0x00000000 – – – 0x00000340 High-End Overlay Channel Enable Register LCDC_HEOCHER Write-only 0x00000000 0x00000344 High-End Overlay Channel Disable Register LCDC_HEOCHDR Write-only 0x00000000 0x00000348 High-End Overlay Channel Status Register LCDC_HEOCHSR Read-only 0x00000000 0x0000034C High-End Overlay Interrupt Enable Register LCDC_HEOIER Write-only 0x00000000 0x00000350 High-End Overlay Interrupt Disable Register LCDC_HEOIDR Write-only 0x00000000 0x00000354 High-End Overlay Interrupt Mask Register LCDC_HEOIMR Read-only 0x00000000 0x00000358 High-End Overlay Interrupt Status Register LCDC_HEOISR Read-only 0x00000000 0x0000035C High-End Overlay DMA Head Register LCDC_HEOHEAD Read-write 0x00000000 0x00000360 High-End Overlay DMA Address Register LCDC_HEOADDR Read-write 0x00000000 0x00000364 High-End Overlay DMA Control Register LCDC_HEOCTRL Read-write 0x00000000 0x00000368 High-End Overlay DMA Next Register LCDC_HEONEXT Read-write 0x00000000 0x0000036C High-End Overlay U DMA Head Register LCDC_HEOUHEAD Read-write 0x00000000 0x00000370 High-End Overlay U DMA Address Register LCDC_HEOUADDR Read-write 0x00000000 0x00000374 High-End Overlay U DMA control Register LCDC_HEOUCTRL Read-write 0x00000000 0x00000378 High-End Overlay U DMA Next Register LCDC_HEOUNEXT Read-write 0x00000000 0x0000037C High-End Overlay V DMA Head Register LCDC_HEOVHEAD Read-write 0x00000000 0x00000380 High-End Overlay V DMA Address Register LCDC_HEOVADDR Read-write 0x00000000 0x00000384 High-End Overlay V DMA control Register LCDC_HEOVCTRL Read-write 0x00000000 0x00000388 High-End Overlay VDMA Next Register LCDC_HEOVNEXT Read-write 0x00000000 0x0000038C High-End Overlay Configuration Register 0 LCDC_HEOCFG0 Read-write 0x00000000 0x00000390 High-End Overlay Configuration Register 1 LCDC_HEOCFG1 Read-write 0x00000000 0x00000394 High-End Overlay Configuration Register 2 LCDC_HEOCFG2 Read-write 0x00000000 0x00000398 High-End Overlay Configuration Register 3 LCDC_HEOCFG3 Read-write 0x00000000 0x0000039C High-End Overlay Configuration Register 4 LCDC_HEOCFG4 Read-write 0x00000000 0x000003A0 High-End Overlay Configuration Register 5 LCDC_HEOCFG5 Read-write 0x00000000 0x000003A4 High-End Overlay Configuration Register 6 LCDC_HEOCFG6 Read-write 0x00000000 0x000003A8 High-End Overlay Configuration Register 7 LCDC_HEOCFG7 Read-write 0x00000000 0x000003AC High-End Overlay Configuration Register 8 LCDC_HEOCFG8 Read-write 0x00000000 0x000003B0 High-End Overlay Configuration Register 9 LCDC_HEOCFG9 Read-write 0x00000000 0x000003B4 High-End Overlay Configuration Register 10 LCDC_HEOCFG10 Read-write 0x00000000 0x000003B8 High-End Overlay Configuration Register 11 LCDC_HEOCFG11 Read-write 0x00000000 0x000003BC High-End Overlay Configuration Register 12 LCDC_HEOCFG12 Read-write 0x00000000 0x000003C0 High-End Overlay Configuration Register 13 LCDC_HEOCFG13 Read-write 0x00000000 0x000003C4 High-End Overlay Configuration Register 14 LCDC_HEOCFG14 Read-write 0x00000000 0x000003C8 High-End Overlay Configuration Register 15 LCDC_HEOCFG15 Read-write 0x00000000 0x000003CC High-End Overlay Configuration Register 16 LCDC_HEOCFG16 Read-write 0x00000000 0x000003D0 High-End Overlay Configuration Register 17 LCDC_HEOCFG17 Read-write 0x00000000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 608 Table 32-54. Register Mapping (Continued) Offset Register Name Access Reset 0x000003D4 High-End Overlay Configuration Register 18 LCDC_HEOCFG18 Read-write 0x00000000 0x000003D8 High-End Overlay Configuration Register 19 LCDC_HEOCFG19 Read-write 0x00000000 0x000003DC High-End Overlay Configuration Register 20 LCDC_HEOCFG20 Read-write 0x00000000 0x000003E0 High-End Overlay Configuration Register 21 LCDC_HEOCFG21 Read-write 0x00000000 0x000003E4 High-End Overlay Configuration Register 22 LCDC_HEOCFG22 Read-write 0x00000000 0x000003E8 High-End Overlay Configuration Register 23 LCDC_HEOCFG23 Read-write 0x00000000 0x000003EC High-End Overlay Configuration Register 24 LCDC_HEOCFG24 Read-write 0x00000000 0x000003F0 High-End Overlay Configuration Register 25 LCDC_HEOCFG25 Read-write 0x00000000 0x000003F4 High-End Overlay Configuration Register 26 LCDC_HEOCFG26 Read-write 0x00000000 0x000003F8 High-End Overlay Configuration Register 27 LCDC_HEOCFG27 Read-write 0x00000000 0x000003FC High-End Overlay Configuration Register 28 LCDC_HEOCFG28 Read-write 0x00000000 0x00000400 High-End Overlay Configuration Register 29 LCDC_HEOCFG29 Read-write 0x00000000 0x00000404 High-End Overlay Configuration Register 30 LCDC_HEOCFG30 Read-write 0x00000000 0x00000408 High-End Overlay Configuration Register 31 LCDC_HEOCFG31 Read-write 0x00000000 0x0000040C High-End Overlay Configuration Register 32 LCDC_HEOCFG32 Read-write 0x00000000 0x00000410 High-End Overlay Configuration Register 33 LCDC_HEOCFG33 Read-write 0x00000000 0x00000414 High-End Overlay Configuration Register 34 LCDC_HEOCFG34 Read-write 0x00000000 0x00000418 High-End Overlay Configuration Register 35 LCDC_HEOCFG35 Read-write 0x00000000 0x0000041C High-End Overlay Configuration Register 36 LCDC_HEOCFG36 Read-write 0x00000000 0x00000420 High-End Overlay Configuration Register 37 LCDC_HEOCFG37 Read-write 0x00000000 0x00000424 High-End Overlay Configuration Register 38 LCDC_HEOCFG38 Read-write 0x00000000 0x00000428 High-End Overlay Configuration Register 39 LCDC_HEOCFG39 Read-write 0x00000000 0x0000042C High-End Overlay Configuration Register 40 LCDC_HEOCFG40 Read-write 0x00000000 0x00000430 High-End Overlay Configuration Register 41 LCDC_HEOCFG41 Read-write 0x00000000 0x434-0x43C Reserved – – – 0x00000440 Hardware Cursor Channel Enable Register LCDC_HCRCHER Write-only 0x00000000 0x00000444 Hardware Cursor Channel disable Register LCDC_HCRCHDR Write-only 0x00000000 0x00000448 Hardware Cursor Channel Status Register LCDC_HCRCHSR Read-only 0x00000000 0x0000044C Hardware Cursor Interrupt Enable Register LCDC_HCRIER Write-only 0x00000000 0x00000450 Hardware Cursor Interrupt Disable Register LCDC_HCRIDR Write-only 0x00000000 0x00000454 Hardware Cursor Interrupt Mask Register LCDC_HCRIMR Read-only 0x00000000 0x00000458 Hardware Cursor Interrupt Status Register LCDC_HCRISR Read-only 0x00000000 0x0000045C Hardware Cursor DMA Head Register LCDC_HCRHEAD Read-write 0x00000000 0x00000460 Hardware cursor DMA Address Register LCDC_HCRADDR Read-write 0x00000000 0x00000464 Hardware Cursor DMA Control Register LCDC_HCRCTRL Read-write 0x00000000 0x00000468 Hardware Cursor DMA NExt Register LCDC_HCRNEXT Read-write 0x00000000 0x0000046C Hardware Cursor Configuration 0 Register LCDC_HCRCFG0 Read-write 0x00000000 0x00000470 Hardware Cursor Configuration 1 Register LCDC_HCRCFG1 Read-write 0x00000000 0x00000474 Hardware Cursor Configuration 2 Register LCDC_HCRCFG2 Read-write 0x00000000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 609 Table 32-54. Register Mapping (Continued) Offset Register Name Access Reset 0x00000478 Hardware Cursor Configuration 3 Register LCDC_HCRCFG3 Read-write 0x00000000 0x0000047C Hardware Cursor Configuration 4 Register LCDC_HCRCFG4 Read-write 0x00000000 0x00000480 Reserved – – – 0x00000484 Hardware Cursor Configuration 6 Register LCDC_HCRCFG6 Read-write 0x00000000 0x00000488 Hardware Cursor Configuration 7 Register LCDC_HCRCFG7 Read-write 0x00000000 0x0000048C Hardware Cursor Configuration 8 Register LCDC_HCRCFG8 Read-write 0x00000000 0x00000490 Hardware Cursor Configuration 9 Register LCDC_HCRCFG9 Read-write 0x00000000 0x494-0x53C Reserved – – – 0x00000540 Post Processing Channel Enable Register LCDC_PPCHER Write-only 0x00000000 0x00000544 Post Processing Channel Disable Register LCDC_PPCHDR Write-only 0x00000000 0x00000548 Post Processing Channel Status Register LCDC_PPCHSR Read-only 0x00000000 0x0000054C Post Processing Interrupt Enable Register LCDC_PPIER Write-only 0x00000000 0x00000550 Post Processing Interrupt Disable Register LCDC_PPIDR Write-only 0x00000000 0x00000554 Post Processing Interrupt Mask Register LCDC_PPIMR Read-only 0x00000000 0x00000558 Post Processing Interrupt Status Register LCDC_PPISR Read-only 0x00000000 0x0000055C Post Processing Head Register LCDC_PPHEAD Read-write 0x00000000 0x00000560 Post Processing Address Register LCDC_PPADDR Read-write 0x00000000 0x00000564 Post Processing Control Register LCDC_PPCTRL Read-write 0x00000000 0x00000568 Post Processing Next Register LCDC_PPNEXT Read-write 0x00000000 0x0000056C Post Processing Configuration Register 0 LCDC_PPCFG0 Read-write 0x00000000 0x00000570 Post Processing Configuration Register 1 LCDC_PPCFG1 Read-write 0x00000000 0x00000574 Post Processing Configuration Register 2 LCDC_PPCFG2 Read-write 0x00000000 0x00000578 Post Processing Configuration Register 3 LCDC_PPCFG3 Read-write 0x00000000 0x0000057C Post Processing Configuration Register 4 LCDC_PPCFG4 Read-write 0x00000000 0x00000580 Post Processing Configuration Register 5 LCDC_PPCFG5 Read-write 0x00000000 0x584-0x5FC Reserved – – – LCDC_BASECLUT0 Read-write 0x00000000 ... ... ... LCDC_BASECLUT255 Read-write 0x00000000 LCDC_OVR1CLUT0 Read-write 0x00000000 ... ... ... LCDC_OVR1CLUT255 Read-write 0x00000000 LCDC_OVR2CLUT0 Read-write 0x00000000 ... ... ... LCDC_OVR2CLUT255 Read-write 0x00000000 LCDC_HEOCLUT0 Read-write 0x00000000 ... ... ... LCDC_HEOCLUT255 Read-write 0x00000000 LCDC_HCRCLUT0 Read-write 0x00000000 0x600 ... Base CLUT Register 0 ... 0x8FC Base CLUT Register 255 0xA00 Overlay 1 CLUT Register 0 ... ... 0xDFC Overlay 1 CLUT Register 255 0xE00 Overlay 2 CLUT Register 0 ... ... 0x11FC Overlay 2 CLUT Register 255 0x1200 High End Overlay CLUT Register 0 ... ... 0x15FC High End Overlay CLUT Register 255 0x1600 Hardware Cursor CLUT Register 0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 610 Table 32-54. Register Mapping (Continued) Offset Register ... 0x19FC ... Hardware Cursor CLUT Register 255 0x1A00-0x1FE4 Reserved Note: Name Access Reset ... ... ... LCDC_HCRCLUT255 Read-write 0x00000000 – – – 1. The CLUT registers are located in the RAM. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 611 32.7.1 LCD Controller Configuration Register 0 Name: LCDC_LCDCFG0 Address: 0xF0030000 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 – 7 – 14 – 6 – 13 CGDISPP 5 – 28 – 20 27 – 19 CLKDIV 12 11 CGDISHCR CGDISHEO 4 3 – CLKPWMSEL 26 – 18 25 – 17 24 – 16 10 CGDISOVR2 2 CLKSEL 9 CGDISOVR1 1 – 8 CGDISBASE 0 CLKPOL • CLKPOL: LCD Controller Clock Polarity 0: Data/Control signals are launched on the rising edge of the Pixel Clock. 1: Data/Control signals are launched on the falling edge of the Pixel Clock. • CLKSEL: LCD Controller Clock Source Selection 0: The Asynchronous output stage of the LCD controller is fed by the System Clock. 1: The Asynchronous output state of the LCD controller is fed by the 2x System Clock. • CLKPWMSEL: LCD Controller PWM Clock Source Selection 0: The slow clock is selected and feeds the PWM module. 1: The system clock is selected and feeds the PWM module. • CGDISBASE: Clock Gating Disable Control for the Base Layer 0: Automatic Clock Gating is enabled for the Base Layer. 1: Clock is running continuously. • CGDISOVR1: Clock Gating Disable Control for the Overlay 1 Layer 0: Automatic Clock Gating is enabled for the Overlay 1 Layer. 1: Clock is running continuously. • CGDISOVR2: Clock Gating Disable Control for the Overlay 2 Layer 0: Automatic Clock Gating is enabled for the Overlay 2 Layer. 1: Clock is running continuously. • CGDISHEO: Clock Gating Disable Control for the High End Overlay 0: Automatic Clock Gating is enabled for the High End Overlay Layer. 1: Clock is running continuously. • CGDISHCR: Clock Gating Disable Control for the Hardware Cursor Layer 0: Automatic Clock Gating is enabled for the Hardware Cursor Layer. 1: Clock is running continuously. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 612 • CGDISPP: Clock Gating Disable Control for the Post Processing Layer 0: Automatic Clock Gating is enabled for the Post Processing Layer. 1: Clock is running continuously. • CLKDIV: LCD Controller Clock Divider 8-bit width clock divider for pixel clock LCD_PCLK. pixel_clock = selected_clock / (CLKDIV+2) where selected_clock is equal to system_clock when CLKSEL field is set to 0 and system_clock2x when CLKSEL is set to 1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 613 32.7.2 LCD Controller Configuration Register 1 Name: LCDC_LCDCFG1 Address: 0xF0030004 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VSPW HSPW • HSPW: Horizontal Synchronization Pulse Width Width of the LCD_HSYNC pulse, given in pixel clock cycles. Width is (HSPW+1) LCD_PCLK cycles. • VSPW: Vertical Synchronization Pulse Width Width of the LCD_VSYNC pulse, given in number of lines. Width is (VSPW+1) lines. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 614 32.7.3 LCD Controller Configuration Register 2 Name: LCDC_LCDCFG2 Address: 0xF0030008 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 28 – 20 27 – 19 13 – 5 12 – 4 11 – 3 26 – 18 25 – 17 24 – 16 10 – 2 9 – 1 8 – 0 VBPW VFPW • VFPW: Vertical Front Porch Width This field indicates the number of lines at the end of the Frame. The blanking interval is equal to (VFPW+1) lines. • VBPW: Vertical Back Porch Width This field indicates the number of lines at the beginning of the Frame. The blanking interval is equal to VBPW lines. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 615 32.7.4 LCD Controller Configuration Register 3 Name: LCDC_LCDCFG3 Address: 0xF003000C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 14 – 6 13 – 5 12 – 4 27 – 19 26 – 18 25 – 17 24 HBPW 16 11 – 3 10 – 2 9 – 1 8 HFPW 0 HBPW HFPW • HFPW: Horizontal Front Porch Width Number of pixel clock cycles inserted at the end of the active line. The interval is equal to (HFPW+1) LCD_PCLK cycles. • HBPW: Horizontal Back Porch Width Number of pixel clock cycles inserted at the beginning of the line. The interval is equal to (HBPW+1) LCD_PCLK cycles. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 616 32.7.5 LCD Controller Configuration Register 4 Name: LCDC_LCDCFG4 Address: 0xF0030010 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 RPF 17 24 9 PPL 1 8 16 RPF 15 – 7 14 – 6 13 – 5 12 – 4 2 0 PPL • RPF: Number of Active Row Per Frame Number of active lines in the frame. The frame height is equal to (RPF+1) lines. • PPL: Number of Pixels Per Line Number of pixel in the frame. The number of active pixels in the frame is equal to (PPL+1) pixels. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 617 32.7.6 LCD Controller Configuration Register 5 Name: LCDC_LCDCFG5 Address: 0xF0030014 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 DISPDLY 30 – 22 – 14 – 6 DITHER 29 – 21 – 13 VSPHO 5 – 28 – 20 27 – 19 12 VSPSU 4 DISPPOL 11 – 3 VSPDLYE 26 – 18 GUARDTIME 10 PP 2 VSPDLYS 25 – 17 24 – 16 9 8 MODE 1 VSPOL 0 HSPOL • HSPOL: Horizontal Synchronization Pulse Polarity 0: Active High 1: Active Low • VSPOL: Vertical Synchronization Pulse Polarity 0: Active High 1: Active Low • VSPDLYS: Vertical Synchronization Pulse Start 0: The first active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. 1: The first active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. • VSPDLYE: Vertical Synchronization Pulse End 0: The second active edge of the Vertical synchronization pulse is synchronous with the second edge of the horizontal pulse. 1: The second active edge of the Vertical synchronization pulse is synchronous with the first edge of the horizontal pulse. • DISPPOL: Display Signal Polarity 0: Active High 1: Active Low • DITHER: LCD Controller Dithering 0: Dithering logical unit is disabled. 1: Dithering logical unit is activated. • DISPDLY: LCD Controller Display Power Signal Synchronization 0: The LCD_DISP signal is asserted synchronously with the second active edge of the horizontal pulse. 1: The LCD_DISP signal is asserted asynchronously with both edges of the horizontal pulse. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 618 • MODE: LCD Controller Output Mode Value Name Description 0 OUTPUT_12BPP LCD output mode is set to 12 bits per pixel 1 OUTPUT_16BPP LCD output mode is set to 16 bits per pixel 2 OUTPUT_18BPP LCD output mode is set to 18 bits per pixel 3 OUTPUT_24BPP LCD output mode is set to 24 bits per pixel • PP: Post Processing Enable 0: The Blended pixel is pushed into the output FIFO. 1: The Blended pixel is written back to memory, the post processing stage is enabled. • VSPSU: LCD Controller Vertical synchronization Pulse Setup Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. 1: The vertical synchronization pulse is asserted one pixel clock cycle before the horizontal pulse. • VSPHO: LCD Controller Vertical synchronization Pulse Hold Configuration 0: The vertical synchronization pulse is asserted synchronously with horizontal pulse edge. 1: The vertical synchronization pulse is held active one pixel clock cycle after the horizontal pulse. • GUARDTIME: LCD DISPLAY Guard Time Number of frames inserted during start up before LCD_DISP assertion. Number of frames inserted after LCD_DISP reset. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 619 32.7.7 LCD Controller Configuration Register 6 Name: LCDC_LCDCFG6 Address: 0xF0030018 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 7 – 6 – 5 – 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 PWMCVAL 4 3 PWMPOL – 2 1 PWMPS 0 • PWMPS: PWM Clock Prescaler 3-bit value. Selects the configuration of the counter prescaler module. The PWMPS field decoding is listed below. Value Name Description 000 DIV_1 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK 001 DIV_2 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/2 010 DIV_4 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/4 011 DIV_8 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/8 100 DIV_16 The counter advances at a rate of fCOUNTER = fPWM_SELECTED_CLOCK/16 101 DIV_32 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/32 110 DIV_64 The counter advances at a of rate fCOUNTER = fPWM_SELECTED_CLOCK/64 • PWMPOL: LCD Controller PWM Signal Polarity This bit defines the polarity of the PWM output signal. If set to one, the output pulses are high level (the output will be high whenever the value in the counter is less than the value CVAL) If set to zero, the output pulses are low level. • PWMCVAL: LCD Controller PWM Compare Value PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 620 32.7.8 LCD Controller Enable Register Name: LCDC_LCDEN Address: 0xF0030020 Access: Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 PWMEN 26 – 18 – 10 – 2 DISPEN 25 – 17 – 9 – 1 SYNCEN 24 – 16 – 8 – 0 CLKEN • CLKEN: LCD Controller Pixel Clock Enable 0: Writing this field to zero has no effect. 1: When set to one the pixel clock logical unit is activated. • SYNCEN: LCD Controller Horizontal and Vertical Synchronization Enable 0: Writing this field to zero has no effect. 1: When set to one, both horizontal and vertical synchronization (LCD_VSYNC and LCD_HSYNC) signals are generated. • DISPEN: LCD Controller DISP Signal Enable 0: Writing this field to zero has no effect. 1: When set to one, LCD_DISP signal is generated. • PWMEN: LCD Controller Pulse Width Modulation Enable 0: Writing this field to zero has no effect. 1: When set to one, the pwm is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 621 32.7.9 LCD Controller Disable Register Name: LCDC_LCDDIS Address: 0xF0030024 Access: Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 PWMRST 3 PWMDIS 26 – 18 – 10 DISPRST 2 DISPDIS 25 – 17 – 9 SYNCRST 1 SYNCDIS 24 – 16 – 8 CLKRST 0 CLKDIS • CLKDIS: LCD Controller Pixel Clock Disable 0: No effect. 1: Disables the pixel clock. • SYNCDIS: LCD Controller Horizontal and Vertical Synchronization Disable 0: No effect. 1: Disables the synchronization signals after the end of the frame. • DISPDIS: LCD Controller DISP Signal Disable 0: No effect 1: Disables the DISP signal. • PWMDIS: LCD Controller Pulse Width Modulation Disable 0: No effect 1: Disables the pulse width modulation signal. • CLKRST: LCD Controller Clock Reset 0: No effect. 1: Resets the pixel clock generator module. The pixel clock duty cycle may be violated. • SYNCRST: LCD Controller Horizontal and Vertical Synchronization Reset 0: No effect. 1: Resets the timing engine. Both Horizontal and vertical pulse width are violated. • DISPRST: LCD Controller DISP Signal Reset 0: No effect. 1: Resets the DISP signal. • PWMRST: LCD Controller PWM Reset 0: No effect. 1: Resets the PWM module, the duty cycle may be violated. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 622 32.7.10 LCD Controller Status Register Name: LCDC_LCDSR Address: 0xF0030028 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 SIPSTS 27 – 19 – 11 – 3 PWMSTS 26 – 18 – 10 – 2 DISPSTS 25 – 17 – 9 – 1 LCDSTS 24 – 16 – 8 – 0 CLKSTS • CLKSTS: Clock Status 0: Pixel Clock is disabled. 1: Pixel Clock is running. • LCDSTS: LCD Controller Synchronization status 0: Timing Engine is disabled. 1: Timing Engine is running. • DISPSTS: LCD Controller DISP Signal Status 0: DISP is disabled. 1: DISP signal is activated. • PWMSTS: LCD Controller PWM Signal Status 0: PWM is disabled. 1: PWM signal is activated. • SIPSTS: Synchronization In Progress 0: Clock domain synchronization is terminated. 1: Synchronization is in progress. Access to the registers LCDC_LCDCCFG[0..6], LCDC_LCDEN and LCDC_LCDDIS has no effect. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 623 32.7.11 LCD Controller Interrupt Enable Register Name: LCDC_LCDIER Address: 0xF003002C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 PPIE 5 – 28 – 20 – 12 HCRIE 4 FIFOERRIE 27 – 19 – 11 HEOIE 3 – 26 – 18 – 10 OVR2IE 2 DISPIE 25 – 17 – 9 OVR1IE 1 DISIE 24 – 16 – 8 BASEIE 0 SOFIE • SOFIE: Start of Frame Interrupt Enable Register 0: No effect 1: Enables the interrupt. • DISIE: LCD Disable Interrupt Enable Register 0: No effect 1: Enables the interrupt. • DISPIE: Power UP/Down Sequence Terminated Interrupt Enable Register 0: No effect 1: Enables the interrupt. • FIFOERRIE: Output FIFO Error Interrupt Enable Register 0: No effect 1: Enables the interrupt. • BASEIE: Base Layer Interrupt Enable Register 0: No effect 1: Enables the interrupt. • OVR1IE: Overlay 1 Interrupt Enable Register 0: No effect 1: Enables the interrupt. • OVR2IE: Overlay 2 Interrupt Enable Register 0: No effect 1: Enables the interrupt. • HEOIE: High End Overlay Interrupt Enable Register 0: No effect 1: Enables the interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 624 • HCRIE: Hardware Cursor Interrupt Enable Register 0: No effect 1: Enables the interrupt. • PPIE: Post Processing Interrupt Enable Register 0: No effect 1: Enables the interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 625 32.7.12 LCD Controller Interrupt Disable Register Name: LCDC_LCDIDR Address: 0xF0030030 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 PPID 5 – 28 – 20 – 12 HCRID 4 FIFOERRID 27 – 19 – 11 HEOID 3 – 26 – 18 – 10 OVR2ID 2 DISPID 25 – 17 – 9 OVR1ID 1 DISID 24 – 16 – 8 BASEID 0 SOFID • SOFID: Start of Frame Interrupt Disable Register 0: No effect 1: Disables the interrupt. • DISID: LCD Disable Interrupt Disable Register 0: No effect 1: Disables the interrupt. • DISPID: Power UP/Down Sequence Terminated Interrupt Disable Register 0: No effect 1: Disables the interrupt. • FIFOERRID: Output FIFO Error Interrupt Disable Register 0: No effect 1: Disables the interrupt. • BASEID: Base Layer Interrupt Disable Register 0: No effect 1: Disables the interrupt. • OVR1ID: Overlay 1 Interrupt Disable Register 0: No effect 1: Disables the interrupt. • OVR2ID: Overlay 2 Interrupt Disable Register 0: No effect 1: Disables the interrupt. • HEOID: High End Overlay Interrupt Disable Register 0: No effect 1: Disables the interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 626 • HCRID: Hardware Cursor Interrupt Disable Register 0: No effect 1: Disables the interrupt. • PPID: Post Processing Interrupt Disable Register 0: No effect 1: Disables the interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 627 32.7.13 LCD Controller Interrupt Mask Register Name: LCDC_LCDIMR Address: 0xF0030034 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 PPIM 5 – 28 – 20 – 12 HCRIM 4 FIFOERRIM 27 – 19 – 11 HEOIM 3 – 26 – 18 – 10 OVR2IM 2 DISPIM 25 – 17 – 9 OVR1IM 1 DISIM 24 – 16 – 8 BASEIM 0 SOFIM • SOFIM: Start of Frame Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DISIM: LCD Disable Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DISPIM: Power UP/Down Sequence Terminated Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • FIFOERRIM: Output FIFO Error Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • BASEIM: Base Layer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • OVR1IM: Overlay 1 Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • OVR2IM: Overlay 2 Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • HEOIM: High End Overlay Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 628 • HCRIM: Hardware Cursor Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • PPIM: Post Processing Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 629 32.7.14 LCD Controller Interrupt Status Register Name: LCDC_LCDISR Address: 0xF0030038 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 PP 5 – 28 – 20 – 12 HCR 4 FIFOERR 27 – 19 – 11 HEO 3 – 26 – 18 – 10 OVR2 2 DISP 25 – 17 – 9 OVR1 1 DIS 24 – 16 – 8 BASE 0 SOF • SOF: Start of Frame Interrupt Status Register When set to one, this flag indicates that a start of frame event has been detected. This flag is reset after a read operation. • DIS: LCD Disable Interrupt Status Register When set to one, this flag indicates that the horizontal and vertical timing generator has been successfully disabled. This flag is reset after a read operation. • DISP: Power-up/Power-down Sequence Terminated Interrupt Status Register When set to one, this flag indicates whether the power-up sequence or power-down sequence has terminated. This flag is reset after a read operation. • FIFOERR: Output FIFO Error When set to one, this flag indicates that an underflow occurs in the output FIFO. This flag is reset after a read operation. • BASE: Base Layer Raw Interrupt Status Register When set to one, this flag indicates that a base layer interrupt is pending. This flag is reset as soon as the BASEISR register is read. • OVR1: Overlay 1 Raw Interrupt Status Register When set to one, this flag indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the OVR1ISR register is read. • OVR2: Overlay 2 Raw Interrupt Status Register When set to one this flag indicates that an Overlay 1 layer interrupt is pending. This flag is reset as soon as the OVR1ISR register is read. • HEO: High End Overlay Raw Interrupt Status Register When set to one, this flag indicates that a Hi End layer interrupt is pending. This flag is reset as soon as the HEOISR register is read. • HCR: Hardware Cursor Raw Interrupt Status Register When set to one, this flag indicates that a Hardware Cursor layer interrupt is pending. This flag is reset as soon as the HCRISR register is read. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 630 • PP: Post Processing Raw Interrupt Status Register When set to one, this flag indicates that Post Processing interrupt is pending. This flag is reset as soon as the PPISR register is read. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 631 32.7.15 LCD Controller Attribute Register Name: LCDC_ATTR Address: 0xF003003C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 PPA2Q 5 PP 28 – 20 – 12 HCRA2Q 4 HCR 27 – 19 – 11 HEOA2Q 3 HEO 26 – 18 – 10 OVR2A2Q 2 OVR2 25 – 17 – 9 OVR1A2Q 1 OVR1 24 – 16 – 8 BASEA2Q 0 BASE • BASE: Base Layer Update Attribute Register 0: No effect 1: Update the BASE window attributes. • OVR1: Overlay 1 Update Attribute Register 0: No effect 1: Update the OVR1 window attribute • OVR2: Overlay 2 Update Attribute Register 0: No effect 1: Update the OVR2 window attribute • HEO: High-End Overlay Update Attribute Register 0: No effect 1: Update the HEO window attribute • HCR: Hardware Cursor Update Attribute Register 0: No effect 1: Update the BCH window attribute • PP: Post-Processing Update Attribute Register 0: No effect 1: Update the PP window attribute • BASEA2Q: Base Layer Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the BASEHEAD register to the descriptor list. • OVR1A2Q: Overlay 1 Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the OVR1HEAD register to the descriptor list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 632 • OVR2A2Q: Overlay 2 Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the OVR2HEAD register to the descriptor list. • HEOA2Q: High-End Overlay Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the HEOHEAD register to the descriptor list. • HCRA2Q: Hardware Cursor Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the HCRHEAD register to the descriptor list. • PPA2Q: Post-Processing Update Attribute Register 0: No effect 1: Add the descriptor pointed out by the PPHEAD register to the descriptor list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 633 32.7.16 Base Layer Channel Enable Register Name: LCDC_BASECHER Address: 0xF0030040 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. • A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 634 32.7.17 Base Layer Channel Disable Register Name: LCDC_BASECHDR Address: 0xF0030044 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. • CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 635 32.7.18 Base Layer Channel Status Register Name: LCDC_BASECHSR Address: 0xF0030048 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. • UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. • A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 636 32.7.19 Base Layer Interrupt Enable Register Name: LCDC_BASEIER Address: 0xF003004C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 637 32.7.20 Base Layer Interrupt Disable Register Name: LCDC_BASEIDR Address: 0xF0030050 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DONE: End of List Interrupt Disable Register 0: No effect. 1: interrupt source is disabled. • OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 638 32.7.21 Base Layer Interrupt Mask Register Name: LCDC_BASEIMR Address: 0xF0030054 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 639 32.7.22 Base Layer Interrupt Status Register Name: LCDC_BASEISR Address: 0xF0030058 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. • DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • DONE: End of List Detected When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. • OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 640 32.7.23 Base Layer Head Register Name: LCDC_BASEHEAD Address: 0xF003005C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 641 32.7.24 Base Layer Address Register Name: LCDC_BASEADDR Address: 0xF0030060 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer Start Address Frame buffer base address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 642 32.7.25 Base Layer Control Register Name: LCDC_BASECTRL Address: 0xF0030064 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. • DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 643 32.7.26 Base Layer Next Register Name: LCDC_BASENEXT Address: 0xF0030068 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 644 32.7.27 Base Layer Configuration 0 Register Name: LCDC_BASECFG0 Address: 0xF003006C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 SIF • SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. • BLEN: AHB Burst Length Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. • DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 645 32.7.28 Base Layer Configuration 1 Register Name: LCDC_BASECFG1 Address: 0xF0030070 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 20 – 12 5 4 – RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color lookup table is selected. • RGBMODE: RGB Input Mode Selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 • CLUTMODE: Color Lookup Table Input Mode Selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 646 32.7.29 Base Layer Configuration 2 Register Name: LCDC_BASECFG2 Address: 0xF0030074 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 647 32.7.30 Base Layer Configuration 3 Register Name: LCDC_BASECFG3 Address: 0xF0030078 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Base DMA channel is disabled. • GDEF: Green Default Default Green color when the Base DMA channel is disabled. • BDEF: Blue Default Default Blue color when the Base DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 648 32.7.31 Base Layer Configuration 4 Register Name: LCDC_BASECFG4 Address: 0xF003007C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 DISCEN 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 REP 1 – 24 – 16 – 8 DMA 0 – • DMA: Use DMA Data Path 0: The default color is used on the Base Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. • DISCEN: Discard Area Enable 0: The whole frame is retrieved from memory. 1:When set to one the DMA channel discards the area located at screen coordinate {DISCXPOS, DISCYPOS}. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 649 32.7.32 Base Layer Configuration 5 Register Name: LCDC_BASECFG5 Address: 0xF0030080 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 10 3 2 18 25 DISCYPOS 17 24 9 DISCXPOS 1 8 16 DISCYPOS 15 – 7 14 – 6 13 – 5 12 – 4 0 DISCXPOS • DISCXPOS: Discard Area horizontal coordinate Horizontal Position of the Discard Area. • DISCYPOS: Discard Area Vertical coordinate Vertical Position of the Discard Area. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 650 32.7.33 Base Layer Configuration 6 Register Name: LCDC_BASECFG6 Address: 0xF0030084 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 10 3 2 18 25 DISCYSIZE 17 24 9 DISCXSIZE 1 8 16 DISCYSIZE 15 – 7 14 – 6 13 – 5 12 – 4 0 DISCXSIZE • DISCXSIZE: Discard Area Horizontal Size Discard Horizontal size in pixels. The Discard size is set to (DISCXSIZE+1) pixels in horizontal. • DISCYSIZE: Discard Area Vertical Size Discard Vertical size in pixels. The Discard size is set to (DISCYSIZE+1) pixels in vertical. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 651 32.7.34 Overlay 1 Layer Channel Enable Register Name: LCDC_OVRCHER1 Address: 0xF0030140 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates window attributes (size, alpha-blending, etc.) on the next start of frame. • A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 652 32.7.35 Overlay 1 Layer Channel Disable Register Name: LCDC_OVRCHDR1 Address: 0xF0030144 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. • CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 653 32.7.36 Overlay 1 Layer Channel Status Register Name: LCDC_OVRCHSR1 Address: 0xF0030148 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. • UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. • A2QSR: Add to Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 654 32.7.37 Overlay 1 Layer Interrupt Enable Register Name: LCDC_OVRIER1 Address: 0xF003014C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 655 32.7.38 Overlay 1 Layer Interrupt Disable Register Name: LCDC_OVRIDR1 Address: 0xF0030150 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 656 32.7.39 Overlay 1 Layer Interrupt Mask Register Name: LCDC_OVRIMR1 Address: 0xF0030154 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 657 32.7.40 Overlay 1 Layer Interrupt Status Register Name: LCDC_OVRISR1 Address: 0xF0030158 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. • DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • DONE: End of List Detected Register When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. • OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 658 32.7.41 Overlay 1 Layer Head Register Name: LCDC_OVRHEAD1 Address: 0xF003015C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 659 32.7.42 Overlay 1 Layer Address Register Name: LCDC_OVRADDR1 Address: 0xF0030160 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer Overlay 1 Address Overlay 1 frame buffer base address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 660 32.7.43 Overlay 1 Layer Control Register Name: LCDC_OVRCTRL1 Address: 0xF0030164 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. • DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 661 32.7.44 Overlay 1 Layer Next Register Name: LCDC_OVRNEXT1 Address: 0xF0030168 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 662 32.7.45 Overlay 1 Layer Configuration 0 Register Name: LCDC_OVR1CFG0 Address: 0xF003016C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 LOCKDIS 5 28 – 20 – 12 ROTDIS 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 SIF • SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. • BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. • DLBO: Defined Length Burst Only for Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). • ROTDIS: Hardware Rotation Optimization Disable 0: Rotation optimization is enabled. 1: Rotation optimization is disabled. • LOCKDIS: Hardware Rotation Lock Disable 0: AHB lock signal is asserted when a rotation is performed. 1: AHB lock signal is cleared when a rotation is performed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 663 32.7.46 Overlay 1 Layer Configuration 1 Register Name: LCDC_OVR1CFG1 Address: 0xF0030170 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 – RGBMODE 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color lookup table is selected. • RGBMODE: RGB Input Mode Selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 • CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 664 32.7.47 Overlay 1 Layer Configuration 2 Register Name: LCDC_OVR1CFG2 Address: 0xF0030174 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XPOS • XPOS: Horizontal Window Position Overlay 1 Horizontal window position. • YPOS: Vertical Window Position Overlay 1 Vertical window position. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 665 32.7.48 Overlay 1 Layer Configuration 3 Register Name: LCDC_OVR1CFG3 Address: 0xF0030178 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XSIZE • XSIZE: Horizontal Window Size Overlay 1 window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE ≤ PPL • YSIZE: Vertical Window Size Overlay 1 window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE ≤ RPF SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 666 32.7.49 Overlay 1 Layer Configuration 4 Register Name: LCDC_OVR1CFG4 Address: 0xF003017C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 667 32.7.50 Overlay 1 Layer Configuration 5 Register Name: LCDC_OVR1CFG5 Address: 0xF0030180 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE • PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 668 32.7.51 Overlay 1 Layer Configuration 6 Register Name: LCDC_OVR1CFG6 Address: 0xF0030184 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Overlay 1 DMA channel is disabled. • GDEF: Green Default Default Green color when the Overlay 1 DMA channel is disabled. • BDEF: Blue Default Default Blue color when the Overlay 1 DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 669 32.7.52 Overlay 1 Layer Configuration 7 Register Name: LCDC_OVR1CFG7 Address: 0xF0030188 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY • RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. • GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. • BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 670 32.7.53 Overlay 1 Layer Configuration 8 Register Name: LCDC_OVR1CFG8 Address: 0xF003018C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK • RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. • GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. • BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 671 32.7.54 Overlay1 Layer Configuration 9 Register Name: LCDC_OVR1CFG9 Address: 0xF0030190 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 OVR 14 – 6 LAEN 13 – 5 GAEN 12 – 4 REVALPHA 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA • CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. • INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. • ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. • ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. • REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. • GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. • LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. • OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 672 • DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. • DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. • GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 673 32.7.55 Overlay 2 Layer Channel Enable Register Name: LCDC_OVRCHER2 Address: 0xF0030240 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. • A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 674 32.7.56 Overlay 2 Layer Channel Disable Register Name: LCDC_OVRCHDR2 Address: 0xF0030244 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. • CHRST: Channel Reset Register When set to one this field disables the layer at the end of the current frame. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 675 32.7.57 Overlay 2 Layer Channel Status Register Name: LCDC_OVRCHSR2 Address: 0xF0030248 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. • UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will update on the next Frame. • A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 676 32.7.58 Overlay 2 Layer Interrupt Enable Register Name: LCDC_OVRIER2 Address: 0xF003024C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 677 32.7.59 Overlay 2 Layer Interrupt Disable Register Name: LCDC_OVRIDR2 Address: 0xF0030250 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 678 32.7.60 Overlay 2 Layer Interrupt Mask Register Name: LCDC_OVRIMR2 Address: 0xF0030254 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 679 32.7.61 Overlay 2 Layer Interrupt Status Register Name: LCDC_OVRISR2 Address: 0xF0030258 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. • DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • ADD: Head Descriptor Loaded Interrupt Disable Register When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • DONE: End Of List Interrupt Disable Register When set to one this flag indicates that a End of List condition has occurred. This flag is reset after a read operation. • OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 680 32.7.62 Overlay 2 Layer Head Register Name: LCDC_OVRHEAD2 Address: 0xF003025C Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 681 32.7.63 Overlay 2 Layer Address Register Name: LCDC_OVRADDR2 Address: 0xF0030260 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer Overlay 2 Address Overlay 2 frame buffer base address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 682 32.7.64 Overlay 2 Layer Control Register Name: LCDC_OVRCTRL2 Address: 0xF0030264 Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. • DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 683 32.7.65 Overlay 2 Layer Next Register Name: LCDC_OVRNEXT2 Address: 0xF0030268 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 684 32.7.66 Overlay 2 Layer Configuration 0 Register Name: LCDC_OVR2CFG0 Address: 0xF003026C Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 LOCKDIS 5 28 – 20 – 12 ROTDIS 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 – • BLEN: AHB Burst Length Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. • DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for 2 and 3 beats burst. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). • ROTDIS: Hardware Rotation Optimization Disable 0: Rotation optimization is enabled. 1: Rotation optimization is disabled. • LOCKDIS: Hardware Rotation Lock Disable 0: AHB lock signal is asserted when a rotation is performed. 1: AHB lock signal is cleared when a rotation is performed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 685 32.7.67 Overlay 2 Layer Configuration 1 Register Name: LCDC_OVR2CFG1 Address: 0xF0030270 Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected 1: Color lookup table is selected • RGBMODE: RGB Input Mode Selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 • CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 686 32.7.68 Overlay 2 Layer Configuration 2 Register Name: LCDC_OVR2CFG2 Address: 0xF0030274 Access: Read-Write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XPOS • XPOS: Horizontal Window Position Overlay 2 Horizontal window position. • YPOS: Vertical Window Position Overlay 2 Vertical window position. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 687 32.7.69 Overlay 2 Layer Configuration 3 Register Name: LCDC_OVR2CFG3 Address: 0xF0030278 Access: Read-Write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XSIZE • XSIZE: Horizontal Window Size Overlay 2 window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE ≤ PPL • YSIZE: Vertical Window Size Overlay 2 window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE ≤ RPF SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 688 32.7.70 Overlay 2 Layer Configuration 4 Register Name: LCDC_OVR2CFG4 Address: 0xF003027C Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 689 32.7.71 Overlay 2 Layer Configuration 5 Register Name: LCDC_OVR2CFG5 Address: 0xF0030280 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE • PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 690 32.7.72 Overlay 2 Layer Configuration 6 Register Name: LCDC_OVR2CFG6 Address: 0xF0030284 Access: Read-Write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Overlay 1 DMA channel is disabled. • GDEF: Green Default Default Green color when the Overlay 1 DMA channel is disabled. • BDEF: Blue Default Default Blue color when the Overlay 1 DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 691 32.7.73 Overlay 2 Layer Configuration 7 Register Name: LCDC_OVR2CFG7 Address: 0xF0030288 Access: Read-Write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY • RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. • GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. • BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 692 32.7.74 Overlay 2 Layer Configuration 8 Register Name: LCDC_OVR2CFG8 Address: 0xF003028C Access: Read-Write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK • RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. • GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. • BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 693 32.7.75 Overlay 2 Layer Configuration 9 Register Name: LCDC_OVR2CFG9 Address: 0xF0030290 Access: Read-Write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 OVR 14 – 6 LAEN 13 – 5 GAEN 12 – 4 REVALPHA 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA • CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. • INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. • ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. • ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. • REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. • GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. • LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. • OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 694 • DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. • DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. • GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 695 32.7.76 High End Overlay Layer Channel Enable Register Name: LCDC_HEOCHER Address: 0xF0030340 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. • A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 696 32.7.77 High End Overlay Layer Channel Disable Register Name: LCDC_HEOCHDR Address: 0xF0030344 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. • CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 697 32.7.78 High End Overlay Layer Channel Status Register Name: LCDC_HEOCHSR Address: 0xF0030348 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. • UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. • A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 698 32.7.79 High End Overlay Layer Interrupt Enable Register Name: LCDC_HEOIER Address: 0xF003034C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • UDMA: End of DMA Transfer for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • UDSCR: Descriptor Loaded for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • UADD: Head Descriptor Loaded for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 699 • UDONE: End of List for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • UOVR: Overflow for U or UV Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • VDMA: End of DMA for V Chrominance Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • VDSCR: Descriptor Loaded for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • VADD: Head Descriptor Loaded for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • VDONE: End of List for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • VOVR: Overflow for V Chrominance Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 700 32.7.80 High End Overlay Layer Interrupt Disable Register Name: LCDC_HEOIDR Address: 0xF0030350 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • UDMA: End of DMA Transfer for U or UV Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • UDSCR: Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • UADD: Head Descriptor Loaded for U or UV Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 701 • UDONE: End of List Interrupt for U or UV Chrominance Component Disable Register 0: No effect. 1: Interrupt source is disabled. • UOVR: Overflow Interrupt for U or UV Chrominance Component Disable Register 0: No effect. 1: Interrupt source is disabled. • VDMA: End of DMA Transfer for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • VDSCR: Descriptor Loaded for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • VADD: Head Descriptor Loaded for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • VDONE: End of List for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • VOVR: Overflow for V Chrominance Component Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 702 32.7.81 High End Overlay Layer Interrupt Mask Register Name: LCDC_HEOIMR Address: 0xF0030354 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • UDMA: End of DMA Transfer for U or UV Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • UDSCR: Descriptor Loaded for U or UV Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • UADD: Head Descriptor Loaded for U or UV Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 703 • UDONE: End of List for U or UV Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • UOVR: Overflow for U Chrominance Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • VDMA: End of DMA Transfer for V Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • VDSCR: Descriptor Loaded for V Chrominance Component Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • VADD: Head Descriptor Loaded for V Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • VDONE: End of List for V Chrominance Component Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • VOVR: Overflow for V Chrominance Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 704 32.7.82 High End Overlay Layer Interrupt Status Register Name: LCDC_HEOISR Address: 0xF0030358 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 VOVR 14 UOVR 6 OVR 29 – 21 VDONE 13 UDONE 5 DONE 28 – 20 VADD 12 UADD 4 ADD 27 – 19 VDSCR 11 UDSCR 3 DSCR 26 – 18 VDMA 10 UDMA 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. • DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • DONE: End of List Detected When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. • OVR: Overflow Detected When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. • UDMA: End of DMA Transfer for U component When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. • UDSCR: DMA Descriptor Loaded for U component When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • UADD: Head Descriptor Loaded for U component When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • UDONE: End of List Detected for U component When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. • UOVR: Overflow Detected for U component When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. • VDMA: End of DMA Transfer for V component When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 705 • VDSCR: DMA Descriptor Loaded for V component When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • VADD: Head Descriptor Loaded for V component When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • VDONE: End of List Detected for V component When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. • VOVR: Overflow Detected for V component When set to one this flag indicates that an overflow occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 706 32.7.83 High End Overlay Layer Head Register Name: LCDC_HEOHEAD Address: 0xF003035C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 707 32.7.84 High End Overlay Layer Address Register Name: LCDC_HEOADDR Address: 0xF0030360 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer start Address Frame Buffer Base Address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 708 32.7.85 High End Overlay Layer Control Register Name: LCDC_HEOCTRL Address: 0xF0030364 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. • DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 709 32.7.86 High End Overlay Layer Next Register Name: LCDC_HEONEXT Address: 0xF0030368 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 710 32.7.87 High End Overlay Layer U-UV Head Register Name: LCDC_HEOUHEAD Address: 0xF003036C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UHEAD UHEAD 15 14 13 12 7 6 5 4 UHEAD UHEAD • UHEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 711 32.7.88 High End Overlay Layer U-UV Address Register Name: LCDC_HEOUADDR Address: 0xF0030370 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UADDR UADDR 15 14 13 12 7 6 5 4 UADDR UADDR • UADDR: DMA Transfer Start Address for U or UV Chrominance U or UV frame buffer address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 712 32.7.89 High End Overlay Layer U-UV Control Register Name: LCDC_HEOUCTRL Address: 0xF0030374 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 UDONEIEN 28 – 20 – 12 – 4 UADDIEN 27 – 19 – 11 – 3 UDSCRIEN 26 – 18 – 10 – 2 UDMAIEN 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 UDFETCH • UDFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • UDMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • UDSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • UADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • UDONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 713 32.7.90 High End Overlay Layer U-UV Next Register Name: LCDC_HEOUNEXT Address: 0xF0030378 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UNEXT UNEXT 15 14 13 12 7 6 5 4 UNEXT UNEXT • UNEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 714 32.7.91 High End Overlay Layer V Head Register Name: LCDC_HEOVHEAD Address: 0xF003037C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VHEAD VHEAD 15 14 13 12 7 6 5 4 VHEAD VHEAD • VHEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 715 32.7.92 High End Overlay Layer V Address Register Name: LCDC_HEOVADDR Address: 0xF0030380 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VADDR VADDR 15 14 13 12 7 6 5 4 VADDR VADDR • VADDR: DMA Transfer Start Address for V Chrominance Frame Buffer Base Address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 716 32.7.93 High End Overlay Layer V Control Register Name: LCDC_HEOVCTRL Address: 0xF0030384 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 VDONEIEN 28 – 20 – 12 – 4 VADDIEN 27 – 19 – 11 – 3 VDSCRIEN 26 – 18 – 10 – 2 VDMAIEN 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 VDFETCH • VDFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • VDMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • VDSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • VADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • VDONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 717 32.7.94 High End Overlay Layer V Next Register Name: LCDC_HEOVNEXT Address: 0xF0030388 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VNEXT VNEXT 15 14 13 12 7 6 5 4 VNEXT VNEXT • VNEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 718 32.7.95 High End Overlay Layer Configuration 0 Register Name: LCDC_HEOCFG0 Address: 0xF003038C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 LOCKDIS 5 BLENUV 28 – 20 – 12 ROTDIS 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 SIF • SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. • BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. • BLENUV: AHB Burst Length for U-V channel Value Name Description 0 AHB_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB_INCR16 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 719 • DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). • ROTDIS: Hardware Rotation Optimization Disable 0: Rotation optimization is enabled. 1: Rotation optimization is disabled. • LOCKDIS: Hardware Rotation Lock Disable 0: AHB lock signal is asserted when a rotation is performed. 1: AHB lock signal is cleared when a rotation is performed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 720 32.7.96 High End Overlay Layer Configuration 1 Register Name: LCDC_HEOCFG1 Address: 0xF0030390 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 – 20 DSCALEOPT 12 5 4 YUVMODE RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 24 – – 17 16 YUV422SWP YUV422ROT 9 8 CLUTMODE 1 0 YUVEN CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color Lookup table is selected. • YUVEN: YUV Color Space Enable 0: Color space is RGB 1: Color Space is YUV • RGBMODE: RGB input mode selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 721 • CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel • YUVMODE: YUV input mode selection Value Name Description 0 32BPP_AYCBCR 32 bpp AYCbCr 444 1 16BPP_YCBCR_MODE0 16 bpp Cr(n)Y(n+1)Cb(n)Y(n) 422 2 16BPP_YCBCR_MODE1 16 bpp Y(n+1)Cr(n)Y(n)Cb(n) 422 3 16BPP_YCBCR_MODE2 16 bpp Cb(n)Y(+1)Cr(n)Y(n) 422 4 16BPP_YCBCR_MODE3 16 bpp Y(n+1)Cb(n)Y(n)Cr(n) 422 5 16BPP_YCBCR_SEMIPLANAR 16 bpp Semiplanar 422 YCbCr 6 16BPP_YCBCR_PLANAR 16 bpp Planar 422 YCbCr 7 12BPP_YCBCR_SEMIPLANAR 12 bpp Semiplanar 420 YCbCr 8 12BPP_YCBCR_PLANAR 12 bpp Planar 420 YCbCr • YUV422ROT: YUV 4:2:2 Rotation When set to one, this bit indicates that the Chroma Upsampling kernel is configured to use the 4:2:2 Rotation Algorithm. This field is relevant only when a rotation angle of 90 degrees or 270 degrees is used. • YUV422SWP: YUV 4:2:2 SWAP When set to one, the Y component of the YUV 4:2:2 packed data stream are swapped. • DSCALEOPT: Down Scaling Bandwidth Optimization 0: Scaler Optimization is disabled. 1: Scaler Optimization is enabled, only relevant pixels are retrieved from memory to fill the scaler filter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 722 32.7.97 High End Overlay Layer Configuration 2 Register Name: LCDC_HEOCFG2 Address: 0xF0030394 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XPOS • XPOS: Horizontal Window Position High End Overlay Horizontal window position. • YPOS: Vertical Window Position High End Overlay Vertical window position. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 723 32.7.98 High End Overlay Layer Configuration 3 Register Name: LCDC_HEOCFG3 Address: 0xF0030398 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XSIZE • XSIZE: Horizontal Window Size High End Overlay window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE ≤ PPL • YSIZE: Vertical Window Size High End Overlay window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE ≤ RPF SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 724 32.7.99 High End Overlay Layer Configuration 4 Register Name: LCDC_HEOCFG4 Address: 0xF003039C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YMEMSIZE 17 24 9 XMEMSIZE 1 8 16 YMEMSIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XMEMSIZE • XMEMSIZE: Horizontal image Size in Memory High End Overlay image width in pixels. The image width is set to (XMEMSIZE+1). • YMEMSIZE: Vertical image Size in Memory High End Overlay image height in pixels. The image height is set to (YMEMSIZE+1). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 725 32.7.100High End Overlay Layer Configuration 5 Register Name: LCDC_HEOCFG5 Address: 0xF00303A0 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 726 32.7.101High End Overlay Layer Configuration 6 Register Name: LCDC_HEOCFG6 Address: 0xF00303A4 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PSTRIDE PSTRIDE 15 14 13 12 7 6 5 4 PSTRIDE PSTRIDE • PSTRIDE: Pixel Stride PSTRIDE represents the memory offset, in bytes, between two pixels of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 727 32.7.102High End Overlay Layer Configuration 7 Register Name: LCDC_HEOCFG7 Address: 0xF00303A8 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UVXSTRIDE UVXSTRIDE 15 14 13 12 7 6 5 4 UVXSTRIDE UVXSTRIDE • UVXSTRIDE: UV Horizontal Stride UVXSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 728 32.7.103High End Overlay Layer Configuration 8 Register Name: LCDC_HEOCFG8 Address: 0xF00303AC Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 UVPSTRIDE UVPSTRIDE 15 14 13 12 7 6 5 4 UVPSTRIDE UVPSTRIDE • UVPSTRIDE: UV Pixel Stride UVPSTRIDE represents the memory offset, in bytes, between two pixels of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 729 32.7.104High End Overlay Layer Configuration 9 Register Name: LCDC_HEOCFG9 Address: 0xF00303B0 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the High End Overlay DMA channel is disabled. • GDEF: Green Default Default Green color when the High End Overlay DMA channel is disabled. • BDEF: Blue Default Default Blue color when the High End Overlay DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 730 32.7.105High End Overlay Layer Configuration 10 Register Name: LCDC_HEOCFG10 Address: 0xF00303B4 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY • RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. • GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. • BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 731 32.7.106High End Overlay Layer Configuration 11 Register Name: LCDC_HEOCFG11 Address: 0xF00303B8 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK • RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. • GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. • BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 732 32.7.107High End Overlay Layer Configuration 12 Register Name: LCDC_HEOCFG12 Address: 0xF00303BC Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 OVR 14 – 6 LAEN 13 – 5 GAEN 12 VIDPRI 4 REVALPHA 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA • CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. • INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. • ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. • ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. • REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. • GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. • LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. • OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 733 • DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. • DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. • VIDPRI: Video Priority 0: OVR1 layer is above HEO layer. 1: OVR1 layer is below HEO layer. • GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 734 32.7.108High End Overlay Layer Configuration 13 Register Name: LCDC_HEOCFG13 Address: 0xF00303C0 Access: Read-write Reset: 0x00000000 31 SCALEN 23 30 – 22 29 28 27 26 25 24 21 20 19 18 17 16 10 9 8 2 1 0 YFACTOR YFACTOR 15 – 7 14 – 6 13 12 11 5 4 3 XFACTOR XFACTOR • SCALEN: Hardware Scaler Enable 0: Scaler is disabled 1: Scaler is enabled. • YFACTOR: Vertical Scaling Factor Scaler Vertical Factor. • XFACTOR: Horizontal Scaling Factor Scaler Horizontal Factor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 735 32.7.109High End Overlay Layer Configuration 14 Register Name: LCDC_HEOCFG14 Address: 0xF00303C4 Access: Read-write Reset: 0x00000000 31 – 23 15 30 CSCYOFF 22 CSCRV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCRV 18 CSCRU 13 12 11 10 9 4 3 2 1 CSCRU 7 6 5 CSCRY 0 CSCRY • CSCRY: Color Space Conversion Y coefficient for Red Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCRU: Color Space Conversion U coefficient for Red Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCRV: Color Space Conversion V coefficient for Red Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCYOFF: Color Space Conversion Offset 0: Offset is set to 0 1: Offset is set to 16 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 736 32.7.110High End Overlay Layer Configuration 15 Register Name: LCDC_HEOCFG15 Address: 0xF00303C8 Access: Read-write Reset: 0x00000000 31 – 23 15 30 CSCUOFF 22 CSCGV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCGV 18 CSCGU 13 12 11 10 9 4 3 2 1 CSCGU 7 6 5 CSCGY 0 CSCGY • CSCGY: Color Space Conversion Y coefficient for Green Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCGU: Color Space Conversion U coefficient for Green Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCGV: Color Space Conversion V coefficient for Green Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCUOFF: Color Space Conversion Offset 0: Offset is set to 0 1: Offset is set to 128 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 737 32.7.111High End Overlay Layer Configuration 16 Register Name: LCDC_HEOCFG16 Address: 0xF00303CC Access: Read-write Reset: 0x00000000 31 – 23 15 30 CSCVOFF 22 CSCBV 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCBV 18 CSCBU 13 12 11 10 9 4 3 2 1 CSCBU 7 6 5 CSCBY 0 CSCBY • CSCBY: Color Space Conversion Y coefficient for Blue Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCBU: Color Space Conversion U coefficient for Blue Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCBV: Color Space Conversion V coefficient for Blue Component 1:2:7 format Color Space Conversion coefficient format is 1 sign bit, 2 magnitude bits and 7 fractional bits. • CSCVOFF: Color Space Conversion Offset 0: Offset is set to 0 1: Offset is set to 128 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 738 32.7.112High End Overlay Layer Configuration 17 Register Name: LCDC_HEOCFG17 Address: 0xF00303D0 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI0COEFF3 20 19 XPHI0COEFF2 12 11 XPHI0COEFF1 4 3 XPHI0COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI0COEFF0: Horizontal Coefficient for phase 0 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI0COEFF1: Horizontal Coefficient for phase 0 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI0COEFF2: Horizontal Coefficient for phase 0 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI0COEFF3: Horizontal Coefficient for phase 0 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 739 32.7.113High End Overlay Layer Configuration 18 Register Name: LCDC_HEOCFG18 Address: 0xF00303D4 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI0COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI0COEFF4: Horizontal Coefficient for phase 0 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 740 32.7.114High End Overlay Layer Configuration 19 Register Name: LCDC_HEOCFG19 Address: 0xF00303D8 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI1COEFF3 20 19 XPHI1COEFF2 12 11 XPHI1COEFF1 4 3 XPHI1COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI1COEFF0: Horizontal Coefficient for phase 1 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI1COEFF1: Horizontal Coefficient for phase 1 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI1COEFF2: Horizontal Coefficient for phase 1 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI1COEFF3: Horizontal Coefficient for phase 1 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 741 32.7.115High End Overlay Layer Configuration 20 Register Name: LCDC_HEOCFG20 Address: 0xF00303DC Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI1COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI1COEFF4: Horizontal Coefficient for phase 1 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 742 32.7.116High End Overlay Layer Configuration 21 Register Name: LCDC_HEOCFG21 Address: 0xF00303E0 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI2COEFF3 20 19 XPHI2COEFF2 12 11 XPHI2COEFF1 4 3 XPHI2COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI2COEFF0: Horizontal Coefficient for phase 2 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI2COEFF1: Horizontal Coefficient for phase 2 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI2COEFF2: Horizontal Coefficient for phase 2 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI2COEFF3: Horizontal Coefficient for phase 2 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 743 32.7.117High End Overlay Layer Configuration 22 Register Name: LCDC_HEOCFG22 Address: 0xF00303E4 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI2COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI2COEFF4: Horizontal Coefficient for phase 2 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 744 32.7.118High End Overlay Layer Configuration 23 Register Name: LCDC_HEOCFG23 Address: 0xF00303E8 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI3COEFF3 20 19 XPHI3COEFF2 12 11 XPHI3COEFF1 4 3 XPHI3COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI3COEFF0: Horizontal Coefficient for phase 3 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI3COEFF1: Horizontal Coefficient for phase 3 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI3COEFF2: Horizontal Coefficient for phase 3 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI3COEFF3: Horizontal Coefficient for phase 3 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 745 32.7.119High End Overlay Layer Configuration 24 Register Name: LCDC_HEOCFG24 Address: 0xF00303EC Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI3COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI3COEFF4: Horizontal Coefficient for phase 3 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 746 32.7.120High End Overlay Layer Configuration 25 Register Name: LCDC_HEOCFG25 Address: 0xF00303F0 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI4COEFF3 20 19 XPHI4COEFF2 12 11 XPHI4COEFF1 4 3 XPHI4COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI4COEFF0: Horizontal Coefficient for phase 4 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI4COEFF1: Horizontal Coefficient for phase 4 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI4COEFF2: Horizontal Coefficient for phase 4 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI4COEFF3: Horizontal Coefficient for phase 4 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 747 32.7.121High End Overlay Layer Configuration 26 Register Name: LCDC_HEOCFG26 Address: 0xF00303F4 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI4COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI4COEFF4: Horizontal Coefficient for phase 4 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 748 32.7.122High End Overlay Layer Configuration 27 Register Name: LCDC_HEOCFG27 Address: 0xF00303F8 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI5COEFF3 20 19 XPHI5COEFF2 12 11 XPHI5COEFF1 4 3 XPHI5COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI5COEFF0: Horizontal Coefficient for phase 5 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI5COEFF1: Horizontal Coefficient for phase 5 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI5COEFF2: Horizontal Coefficient for phase 5 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI5COEFF3: Horizontal Coefficient for phase 5 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 749 32.7.123High End Overlay Layer Configuration 28 Register Name: LCDC_HEOCFG28 Address: 0xF00303FC Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI5COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI5COEFF4: Horizontal Coefficient for phase 5 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 750 32.7.124High End Overlay Layer Configuration 29 Register Name: LCDC_HEOCFG29 Address: 0xF0030400 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI6COEFF3 20 19 XPHI6COEFF2 12 11 XPHI6COEFF1 4 3 XPHI6COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI6COEFF0: Horizontal Coefficient for phase 6 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI6COEFF1: Horizontal Coefficient for phase 6 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI6COEFF2: Horizontal Coefficient for phase 6 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI6COEFF3: Horizontal Coefficient for phase 6 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 751 32.7.125High End Overlay Layer Configuration 30 Register Name: LCDC_HEOCFG30 Address: 0xF0030404 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI6COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI6COEFF4: Horizontal Coefficient for phase 6 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 752 32.7.126High End Overlay Layer Configuration 31 Register Name: LCDC_HEOCFG31 Address: 0xF0030408 Access: Read-write Reset: 0x00000000 31 30 29 23 22 21 15 14 13 7 6 5 28 27 XPHI7COEFF3 20 19 XPHI7COEFF2 12 11 XPHI7COEFF1 4 3 XPHI7COEFF0 26 25 24 18 17 16 10 9 8 2 1 0 • XPHI7COEFF0: Horizontal Coefficient for phase 7 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI7COEFF1: Horizontal Coefficient for phase 7 tap 1 Coefficient format is 1 sign bit and 7 fractional bits. • XPHI7COEFF2: Horizontal Coefficient for phase 7 tap 2 Coefficient format is 1 magnitude bit and 7 fractional bits. • XPHI7COEFF3: Horizontal Coefficient for phase 7 tap 3 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 753 32.7.127High End Overlay Layer Configuration 32 Register Name: LCDC_HEOCFG32 Address: 0xF003040C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 27 – – 20 19 – – 12 11 – – 4 3 XPHI7COEFF4 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • XPHI7COEFF4: Horizontal Coefficient for phase 7 tap 4 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 754 32.7.128High End Overlay Layer Configuration 33 Register Name: LCDC_HEOCFG33 Address: 0xF0030410 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI0COEFF2 12 11 YPHI0COEFF1 4 3 YPHI0COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI0COEFF0: Vertical Coefficient for phase 0 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI0COEFF1: Vertical Coefficient for phase 0 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI0COEFF2: Vertical Coefficient for phase 0 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 755 32.7.129High End Overlay Layer Configuration 34 Register Name: LCDC_HEOCFG34 Address: 0xF0030414 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI1COEFF2 12 11 YPHI1COEFF1 4 3 YPHI1COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI1COEFF0: Vertical Coefficient for phase 1 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI1COEFF1: Vertical Coefficient for phase 1 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI1COEFF2: Vertical Coefficient for phase 1 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 756 32.7.130High End Overlay Layer Configuration 35 Register Name: LCDC_HEOCFG35 Address: 0xF0030418 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI2COEFF2 12 11 YPHI2COEFF1 4 3 YPHI2COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI2COEFF0: Vertical Coefficient for phase 2 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI2COEFF1: Vertical Coefficient for phase 2 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI2COEFF2: Vertical Coefficient for phase 2 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 757 32.7.131High End Overlay Layer Configuration 36 Register Name: LCDC_HEOCFG36 Address: 0xF003041C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI3COEFF2 12 11 YPHI3COEFF1 4 3 YPHI3COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI3COEFF0: Vertical Coefficient for phase 3 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI3COEFF1: Vertical Coefficient for phase 3 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI3COEFF2: Vertical Coefficient for phase 3 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 758 32.7.132High End Overlay Layer Configuration 37 Register Name: LCDC_HEOCFG37 Address: 0xF0030420 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI4COEFF2 12 11 YPHI4COEFF1 4 3 YPHI4COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI4COEFF0: Vertical Coefficient for phase 4 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI4COEFF1: Vertical Coefficient for phase 4 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI4COEFF2: Vertical Coefficient for phase 4 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 759 32.7.133High End Overlay Layer Configuration 38 Register Name: LCDC_HEOCFG38 Address: 0xF0030424 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI5COEFF2 12 11 YPHI5COEFF1 4 3 YPHI5COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI5COEFF0: Vertical Coefficient for phase 5 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI5COEFF1: Vertical Coefficient for phase 5 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI5COEFF2: Vertical Coefficient for phase 5 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 760 32.7.134High End Overlay Layer Configuration 39 Register Name: LCDC_HEOCFG39 Address: 0xF0030428 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI6COEFF2 12 11 YPHI6COEFF1 4 3 YPHI6COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI6COEFF0: Vertical Coefficient for phase 6 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI6COEFF1: Vertical Coefficient for phase 6 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI6COEFF2: Vertical Coefficient for phase 6 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 761 32.7.135High End Overlay Layer Configuration 40 Register Name: LCDC_HEOCFG40 Address: 0xF003042C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 15 14 13 7 6 5 28 27 – – 20 19 YPHI7COEFF2 12 11 YPHI7COEFF1 4 3 YPHI7COEFF0 26 – 18 25 – 17 24 – 16 10 9 8 2 1 0 • YPHI7COEFF0: Vertical Coefficient for phase 7 tap 0 Coefficient format is 1 sign bit and 7 fractional bits. • YPHI7COEFF1: Vertical Coefficient for phase 7 tap 1 Coefficient format is 1 magnitude bit and 7 fractional bits. • YPHI7COEFF2: Vertical Coefficient for phase 7 tap 2 Coefficient format is 1 sign bit and 7 fractional bits. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 762 32.7.136High End Overlay Layer Configuration 41 Register Name: LCDC_HEOCFG41 Address: 0xF0030430 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 10 – 2 25 – 17 YPHIDEF 9 – 1 XPHIDEF 24 – 16 8 – 0 • XPHIDEF: Horizontal Filter Phase Offset XPHIDEF defines the index of the first coefficient set used when the horizontal resampling operation is started. • YPHIDEF: Vertical Filter Phase Offset XPHIDEF defines the index of the first coefficient set used when the vertical resampling operation is started. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 763 32.7.137Hardware Cursor Layer Channel Enable Register Name: LCDC_HCRCHER Address: 0xF0030440 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. • A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 764 32.7.138Hardware Cursor Layer Channel Disable Register Name: LCDC_HCRCHDR Address: 0xF0030444 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. The frame is completed. • CHRST: Channel Reset Register When set to one this field resets the layer immediately. The frame is aborted. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 765 32.7.139Hardware Cursor Layer Channel Status Register Name: LCDC_HCRCHSR Address: 0xF0030448 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. • UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will be updated on the next frame. • A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 766 32.7.140Hardware Cursor Layer Interrupt Enable Register Name: LCDC_HCRIER Address: 0xF003044C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 767 32.7.141Hardware Cursor Layer Interrupt Disable Register Name: LCDC_HCRIDR Address: 0xF0030450 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • OVR: Overflow Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 768 32.7.142Hardware Cursor Layer Interrupt Mask Register Name: LCDC_HCRIMR Address: 0xF0030454 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • OVR: Overflow Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 769 32.7.143Hardware Cursor Layer Interrupt Status Register Name: LCDC_HCRISR Address: 0xF0030458 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 OVR 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. • DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • DONE: End of List Detected When set to one this flag indicates that an End of List condition has occurred. This flag is reset after a read operation. • OVR: Overflow Detected When set to one this flag indicates that an Overflow has occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 770 32.7.144Hardware Cursor Layer Head Register Name: LCDC_HCRHEAD Address: 0xF003045C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 771 32.7.145Hardware Cursor Layer Address Register Name: LCDC_HCRADDR Address: 0xF0030460 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer start address Frame buffer start address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 772 32.7.146Hardware Cursor Layer Control Register Name: LCDC_HCRCTRL Address: 0xF0030464 Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 LFETCH 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • LFETCH: Lookup Table Fetch Enable 0: Lookup Table DMA fetch is disabled. 1: Lookup Table DMA fetch is enabled. • DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 773 32.7.147Hardware Cursor Layer Next Register Name: LCDC_HCRNEXT Address: 0xF0030468 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 774 32.7.148Hardware Cursor Layer Configuration 0 Register Name: LCDC_HCRCFG0 Address: 0xF003046C Access: Read-write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 SIF • SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. • BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. • DLBO: Defined Length Burst Only for Channel Bus Transaction. 0: Undefined length INCR burst is used for a burst of 2 and 3 beats. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 775 32.7.149Hardware Cursor Layer Configuration 1 Register Name: LCDC_HCRCFG1 Address: 0xF0030470 Access: Read-write Reset: 0x00000000 31 – 23 – 15 30 – 22 – 14 7 6 29 – 21 – 13 28 – 20 – 12 5 4 – RGBMODE 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 24 – 16 – 8 CLUTMODE 1 – 0 CLUTEN • CLUTEN: Color Lookup Table Enable 0: RGB mode is selected. 1: Color Lookup table is selected. • RGBMODE: RGB input mode selection Value Name Description 0 12BPP_RGB_444 12 bpp RGB 444 1 16BPP_ARGB_4444 16 bpp ARGB 4444 2 16BPP_RGBA_4444 16 bpp RGBA 4444 3 16BPP_RGB_565 16 bpp RGB 565 4 16BPP_TRGB_1555 16 bpp TRGB 1555 5 18BPP_RGB_666 18 bpp RGB 666 6 18BPP_RGB_666PACKED 18 bpp RGB 666 PACKED 7 19BPP_TRGB_1666 19 bpp TRGB 1666 8 19BPP_TRGB_PACKED 19 bpp TRGB 1666 PACKED 9 24BPP_RGB_888 24 bpp RGB 888 10 24BPP_RGB_888_PACKED 24 bpp RGB 888 PACKED 11 25BPP_TRGB_1888 25 bpp TRGB 1888 12 32BPP_ARGB_8888 32 bpp ARGB 8888 13 32BPP_RGBA_8888 32 bpp RGBA 8888 • CLUTMODE: Color Lookup table input mode selection Value Name Description 0 CLUT_1BPP color lookup table mode set to 1 bit per pixel 1 CLUT_2BPP color lookup table mode set to 2 bits per pixel 2 CLUT_4BPP color lookup table mode set to 4 bits per pixel 3 CLUT_8BPP color lookup table mode set to 8 bits per pixel SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 776 32.7.150Hardware Cursor Layer Configuration 2 Register Name: LCDC_HCRCFG2 Address: 0xF0030474 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YPOS 17 24 9 XPOS 1 8 16 YPOS 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XPOS • XPOS: Horizontal Window Position Hardware Cursor Horizontal window position. • YPOS: Vertical Window Position Hardware Cursor Vertical window position. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 777 32.7.151Hardware Cursor Layer Configuration 3 Register Name: LCDC_HCRCFG3 Address: 0xF0030478 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 11 – 3 10 18 25 YSIZE 17 24 9 XSIZE 1 8 16 YSIZE 15 – 7 14 – 6 13 – 5 12 – 4 2 0 XSIZE • XSIZE: Horizontal Window Size Hardware cursor width is limited to 128 pixels Hardware Cursor window width in pixels. The window width is set to (XSIZE+1). The following constraint must be met: XPOS + XSIZE ≤ PPL • YSIZE: Vertical Window Size Hardware cursor height is limited to 128 pixels Hardware Cursor window height in pixels. The window height is set to (YSIZE+1). The following constrain must be met: YPOS + YSIZE ≤ RPF SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 778 32.7.152Hardware Cursor Layer Configuration 4 Register Name: LCDC_HCRCFG4 Address: 0xF003047C Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 779 32.7.153Hardware Cursor Layer Configuration 6 Register Name: LCDC_HCRCFG6 Address: 0xF0030484 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RDEF GDEF BDEF • RDEF: Red Default Default Red color when the Hardware Cursor DMA channel is disabled. • GDEF: Green Default Default Green color when the Hardware Cursor DMA channel is disabled. • BDEF: Blue Default • Default Blue color when the Hardware Cursor DMA channel is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 780 32.7.154Hardware Cursor Layer Configuration 7 Register Name: LCDC_HCRCFG7 Address: 0xF0030488 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RKEY GKEY BKEY • RKEY: Red Color Component Chroma Key Reference Red chroma key used to match the Red color of the current overlay. • GKEY: Green Color Component Chroma Key Reference Green chroma key used to match the Green color of the current overlay. • BKEY: Blue Color Component Chroma Key Reference Blue chroma key used to match the Blue color of the current overlay. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 781 32.7.155Hardware Cursor Layer Configuration 8 Register Name: LCDC_HCRCFG8 Address: 0xF003048C Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RMASK GMASK BMASK • RMASK: Red Color Component Chroma Key Mask Red Mask used when the compare function is used. If a bit is set then this bit is compared. • GMASK: Green Color Component Chroma Key Mask Green Mask used when the compare function is used. If a bit is set then this bit is compared. • BMASK: Blue Color Component Chroma Key Mask Blue Mask used when the compare function is used. If a bit is set then this bit is compared. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 782 32.7.156Hardware Cursor Layer Configuration 9 Register Name: LCDC_HCRCFG9 Address: 0xF0030490 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 OVR 14 – 6 LAEN 13 – 5 GAEN 12 – 4 REVALPHA 27 – 19 26 – 18 25 – 17 24 – 16 11 – 3 ITER 10 DSTKEY 2 ITER2BL 9 REP 1 INV 8 DMA 0 CRKEY GA • CRKEY: Blender Chroma Key Enable 0: Chroma key matching is disabled. 1: Chroma key matching is enabled. • INV: Blender Inverted Blender Output Enable 0: Iterated pixel is the blended pixel. 1: Iterated pixel is the inverted pixel. • ITER2BL: Blender Iterated Color Enable 0: Final adder stage operand is set to 0. 1: Final adder stage operand is set to the iterated pixel value. • ITER: Blender Use Iterated Color 0: Pixel difference is set to 0. 1: Pixel difference is set to the iterated pixel value. • REVALPHA: Blender Reverse Alpha 0: Pixel difference is multiplied by alpha. 1: Pixel difference is multiplied by 1 - alpha. • GAEN: Blender Global Alpha Enable 0: Global alpha blending coefficient is disabled. 1: Global alpha blending coefficient is enabled. • LAEN: Blender Local Alpha Enable 0: Local alpha blending coefficient is disabled. 1: Local alpha blending coefficient is enabled. • OVR: Blender Overlay Layer Enable 0: Overlay pixel color is set to the default overlay pixel color. 1: Overlay pixel color is set to the DMA channel pixel color. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 783 • DMA: Blender DMA Layer Enable 0: The default color is used on the Overlay 1 Layer. 1: The DMA channel retrieves the pixels stream from the memory. • REP: Use Replication logic to expand RGB color to 24 bits 0: When the selected pixel depth is less than 24 bpp the pixel is shifted and least significant bits are set to 0. 1: When the selected pixel depth is less than 24 bpp the pixel is shifted and the least significant bit replicates the msb. • DSTKEY: Destination Chroma Keying 0: Source Chroma keying is enabled. 1: Destination Chroma keying is used. • GA: Blender Global Alpha Global alpha blender for the current layer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 784 32.7.157Post Processing Layer Channel Enable Register Name: LCDC_PPCHER Address: 0xF0030540 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QEN 25 – 17 – 9 – 1 UPDATEEN 24 – 16 – 8 – 0 CHEN • CHEN: Channel Enable Register 0: No effect. 1: Enables the DMA channel. • UPDATEEN: Update Overlay Attributes Enable Register 0: No effect. 1: Updates windows attributes on the next start of frame. • A2QEN: Add to Queue Enable Register When set to one, it indicates that a valid descriptor has been written to memory, its memory location should be written to the DMA head pointer. The A2QSR status bit is set to one, and it is reset by hardware as soon as the descriptor pointed out by the DMA head pointer is added to the list. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 785 32.7.158Post Processing Layer Channel Disable Register Name: LCDC_PPCHDR Address: 0xF0030544 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 CHRST 0 CHDIS • CHDIS: Channel Disable Register When set to one this field disables the layer at the end of the current frame. • CHRST: Channel Reset Register When set to one this field disables the layer at the end of the current frame. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 786 32.7.159Post Processing Layer Channel Status Register Name: LCDC_PPCHSR Address: 0xF0030548 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 A2QSR 25 – 17 – 9 – 1 UPDATESR 24 – 16 – 8 – 0 CHSR • CHSR: Channel Status Register When set to one this field disables the layer at the end of the current frame. • UPDATESR: Update Overlay Attributes In Progress When set to one this bit indicates that the overlay attributes will update on the next Frame. • A2QSR: Add To Queue Pending Register When set to one this bit indicates that the head pointer is still pending. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 787 32.7.160Post Processing Layer Interrupt Enable Register Name: LCDC_PPIER Address: 0xF003054C Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. • DONE: End of List Interrupt Enable Register 0: No effect. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 788 32.7.161Post Processing Layer Interrupt Disable Register Name: LCDC_PPIDR Address: 0xF0030550 Access: Write-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DSCR: Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • ADD: Head Descriptor Loaded Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. • DONE: End of List Interrupt Disable Register 0: No effect. 1: Interrupt source is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 789 32.7.162Post Processing Layer Interrupt Mask Register Name: LCDC_PPIMR Address: 0xF0030554 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DSCR: Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • ADD: Head Descriptor Loaded Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. • DONE: End of List Interrupt Mask Register 0: Interrupt source is disabled. 1: Interrupt source is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 790 32.7.163Post Processing Layer Interrupt Status Register Name: LCDC_PPISR Address: 0xF0030558 Access: Read-only Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONE 28 – 20 – 12 – 4 ADD 27 – 19 – 11 – 3 DSCR 26 – 18 – 10 – 2 DMA 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – • DMA: End of DMA Transfer When set to one this flag indicates that an End of Transfer has been detected. This flag is reset after a read operation. • DSCR: DMA Descriptor Loaded When set to one this flag indicates that a descriptor has been loaded successfully. This flag is reset after a read operation. • ADD: Head Descriptor Loaded When set to one this flag indicates that the descriptor pointed to by the head register has been loaded successfully. This flag is reset after a read operation. • DONE: End Of List Detected When set to one this flag indicates that a End of List condition has occurred. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 791 32.7.164Post Processing Layer Head Register Name: LCDC_PPHEAD Address: 0xF003055C Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – HEAD HEAD 15 14 13 12 7 6 5 4 HEAD HEAD • HEAD: DMA Head Pointer The Head Pointer points to a new descriptor. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 792 32.7.165Post Processing Layer Address Register Name: LCDC_PPADDR Address: 0xF0030560 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR ADDR 15 14 13 12 7 6 5 4 ADDR ADDR • ADDR: DMA Transfer start address Post Processing Destination frame buffer address. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 793 32.7.166Post Processing Layer Control Register Name: LCDC_PPCTRL Address: 0xF0030564 Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 DONEIEN 28 – 20 – 12 – 4 ADDIEN 27 – 19 – 11 – 3 DSCRIEN 26 – 18 – 10 – 2 DMAIEN 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 DFETCH • DFETCH: Transfer Descriptor Fetch Enable 0: Transfer Descriptor fetch is disabled. 1: Transfer Descriptor fetch is enabled. • DMAIEN: End of DMA Transfer Interrupt Enable 0: DMA transfer completed interrupt is enabled. 1: DMA transfer completed interrupt is disabled. • DSCRIEN: Descriptor Loaded Interrupt Enable 0: Transfer descriptor loaded interrupt is enabled. 1: Transfer descriptor loaded interrupt is disabled. • ADDIEN: Add Head Descriptor to Queue Interrupt Enable 0: Transfer descriptor added to queue interrupt is enabled. 1: Transfer descriptor added to queue interrupt is enabled. • DONEIEN: End of List Interrupt Enable 0: End of list interrupt is disabled. 1: End of list interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 794 32.7.167Post Processing Layer Next Register Name: LCDC_PPNEXT Address: 0xF0030568 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NEXT NEXT 15 14 13 12 7 6 5 4 NEXT NEXT • NEXT: DMA Descriptor Next Address The transfer descriptor address must be aligned on a 64-bit boundary. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 795 32.7.168Post Processing Layer Configuration 0 Register Name: LCDC_PPCFG0 Address: 0xF003056C Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 BLEN 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 DLBO 0 SIF • SIF: Source Interface 0: Base Layer data is retrieved through AHB interface 0. 1: Base Layer data is retrieved through AHB interface 1. • BLEN: AHB Burst Length Value Name Description 0 AHB_BLEN_SINGLE AHB Access is started as soon as there is enough space in the FIFO to store one data. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. 1 AHB_BLEN_INCR4 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 4 data. An AHB INCR4 Burst is used. SINGLE, INCR and INCR4 bursts are used. INCR is used for a burst of 2 and 3 beats. 2 AHB_BLEN_INCR8 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 8 data. An AHB INCR8 Burst is used. SINGLE, INCR, INCR4 and INCR8 bursts are used. INCR is used for a burst of 2 and 3 beats. 3 AHB Access is started as soon as there is enough space in the FIFO to store a total amount of 16 data. AHB_BLEN_INCR16 An AHB INCR16 Burst is used. SINGLE, INCR, INCR4, INCR8 and INCR16 bursts are used. INCR is used for a burst of 2 and 3 beats. • DLBO: Defined Length Burst Only For Channel Bus Transaction. 0: Undefined length INCR burst is used for 2 and 3 beats burst. 1: Only Defined Length burst is used (SINGLE, INCR4, INCR8 and INCR16). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 796 32.7.169Post Processing Layer Configuration 1 Register Name: LCDC_PPCFG1 Address: 0xF0030570 Access: Read-Write Reset: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 ITUBT601 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 25 – 17 – 9 – 1 PPMODE 24 – 16 – 8 – 0 • PPMODE: Post Processing Output Format selection Table 32-55. PPMODE selection Value Name Description 0 PPMODE_RGB_16BPP RGB 16 bpp 1 PPMODE_RGB_24BPP_PACKED RGB 24 bpp PACKED 2 PPMODE_RGB_24BPP_UNPACKED RGB 24 bpp UNPACKED 3 PPMODE_YCBCR_422_MODE0 YCbCr 422 16 bpp (Mode 0) 4 PPMODE_YCBCR_422_MODE1 YCbCr 422 16 bpp (Mode 1) 5 PPMODE_YCBCR_422_MODE2 YCbCr 422 16 bpp (Mode 2) 6 PPMODE_YCBCR_422_MODE3 YCbCr 422 16 bpp (Mode 3) • ITUBT601: Color Space Conversion Luminance 0: Luminance and chrominance range is [0;255] 1: Luminance values are clamped to [16;235] range. Chrominance values are clamped to [16;240] range. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 797 32.7.170Post Processing Layer Configuration 2 Register Name: LCDC_PPCFG2 Address: 0xF0030574 Access: Read-Write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XSTRIDE XSTRIDE 15 14 13 12 7 6 5 4 XSTRIDE XSTRIDE • XSTRIDE: Horizontal Stride XSTRIDE represents the memory offset, in bytes, between two rows of the image memory. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 798 32.7.171Post Processing Layer Configuration 3 Register Name: LCDC_PPCFG3 Address: 0xF0030578 Access: Read-Write Reset: 0x00000000 31 – 23 15 30 CSCYOFF 22 CSCYB 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCYB 18 CSCYG 13 12 11 10 9 4 3 2 1 CSCYG 7 6 5 CSCYR 0 CSCYR • CSCYR: Color Space Conversion R coefficient for Luminance component, signed format, step set to 1/1024 Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCYG: Color Space Conversion G coefficient for Luminance component, signed format, step set to 1/512 Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCYB: Color Space Conversion B coefficient for Luminance component, signed format, step set to 1/1024 Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCYOFF: Color Space Conversion Luminance Offset 0: The Yoff parameter value is set to 0. 1: The Yoff parameter value is set to 16. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 799 32.7.172Post Processing Layer Configuration 4 Register Name: LCDC_PPCFG4 Address: 0xF003057C Access: Read-Write Reset: 0x00000000 31 – 23 15 30 CSCUOFF 22 CSCUB 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCUB 18 CSCUG 13 12 11 10 9 4 3 2 1 CSCUG 7 6 5 CSCUR 0 CSCUR • CSCUR: Color Space Conversion R coefficient for Chrominance B component, signed format. (step 1/1024) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCUG: Color Space Conversion G coefficient for Chrominance B component, signed format. (step 1/512) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCUB: Color Space Conversion B coefficient for Chrominance B component, signed format. (step 1/512) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCUOFF: Color Space Conversion Chrominance B Offset 0: The Cboff parameter value is set to 0. 1: The Cboff parameter value is set to 128. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 800 32.7.173Post Processing Layer Configuration 5 Register Name: LCDC_PPCFG5 Address: 0xF0030580 Access: Read-Write Reset: 0x00000000 31 – 23 15 30 CSCVOFF 22 CSCVB 14 29 28 27 21 20 19 26 25 24 17 16 8 CSCVB 18 CSCVG 13 12 11 10 9 4 3 2 1 CSCVG 7 6 5 CSCVR 0 CSCVR • CSCVR: Color Space Conversion R coefficient for Chrominance R component, signed format. (step 1/1024) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCVG: Color Space Conversion G coefficient for Chrominance R component, signed format. (step 1/512) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCVB: Color Space Conversion B coefficient for Chrominance R component, signed format. (step 1/1024) Color Space Conversion coefficient format is 1 sign bit, 9 fractional bits. • CSCVOFF: Color Space Conversion Chrominance R Offset 0: The Croff parameter value is set to 0. 1: The Croff parameter value is set to 128. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 801 32.7.174Base CLUT Register x Register Name: LCDC_BASECLUTx [x=0..255] Address: 0xF0030600 Access: Read-write Reset: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 15 14 13 12 7 6 5 4 27 – 19 26 – 18 25 – 17 24 – 16 11 10 9 8 3 2 1 0 RCLUT GCLUT BCLUT • BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. • RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 802 32.7.175Overlay 1 CLUT Register x Register Name: LCDC_OVR1CLUTx [x=0..255] Address: 0xF0030A00 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT • BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. • RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. • ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 803 32.7.176Overlay 2 CLUT Register x Register Name: LCDC_OVR2CLUTx [x=0..255] Address: 0xF0030E00 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT • BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. • RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. • ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 804 32.7.177High End Overlay CLUT Register x Register Name: LCDC_HEOCLUTx [x=0..255] Address: 0xF0031200 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT • BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. • RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. • ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 805 32.7.178Hardware Cursor CLUT Register x Register Name: LCDC_HCRCLUTx [x=0..255] Address: 0xF0031600 Access: Read-write Reset: 0x00000000 31 30 29 28 23 22 21 20 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ACLUT RCLUT 15 14 13 12 7 6 5 4 GCLUT BCLUT • BCLUT: Blue Color entry This field indicates the 8-bit width Blue color of the color lookup table. • GCLUT: Green Color entry This field indicates the 8-bit width Green color of the color lookup table. • RCLUT: Red Color entry This field indicates the 8-bit width Red color of the color lookup table. • ACLUT: Alpha Color entry This field indicates the 8-bit width Alpha channel of the color lookup table. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 806 33. Image Sensor Interface (ISI) 33.1 Description The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller. Internal FIFOs on the preview and codec paths are used to store the incoming data. The RGB output on the preview path is compatible with the LCD controller. This module outputs the data in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD display resolution (See Table 33-3 on page 810). Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. It supports two modes of synchronization:  The hardware with ISI_VSYNC and ISI_HSYNC signals  The International Telecommunication Union Recommendation ITU-R BT.656-4 Start-of-Active-Video (SAV) and End-of-Active-Video (EAV) synchronization sequence. Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Table 33-1. I/O Description Signal Direction Description ISI_VSYNC IN Vertical Synchronization ISI_HSYNC IN Horizontal Synchronization ISI_DATA[11..0] IN Sensor Pixel Data ISI_MCK OUT ISI_PCK IN Master Clock Provided to the Image Sensor Pixel Clock Provided by the Image Sensor Figure 33-1. ISI Connection Example Image Sensor Image Sensor Interface data[11..0] 33.2 ISI_DATA[11..0] CLK ISI_MCK PCLK ISI_PCK VSYNC ISI_VSYNC HSYNC ISI_HSYNC Embedded Characteristics  ITU-R BT. 601/656 8-bit Mode External Interface Support  Supports up to 12-bit Grayscale CMOS Sensors  Support for ITU-R BT.656-4 SAV and EAV Synchronization  Vertical and Horizontal Resolutions up to 2048*2048  Preview Path SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 807 33.3  Up to 2048*2048 in Grayscale Mode  Up to 640*480 in RGB Mode  32 Bytes FIFO on Codec Path  32 Bytes FIFO on Preview Path  Support for Packed Data Formatting for YCbCr 4:2:2 Formats  Preview Scaler to Generate Smaller Size image  Programmable Frame Capture Rate  VGA, QVGA, CIF, QCIF Formats Supported for LCD Preview  Custom Formats with Horizontal and Vertical Preview Size as Multiples of 16 Also Supported for LCD Preview Block Diagram Timing Signals Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) CMOS sensor Pixel input up to 12 bit YCbCr 4:2:2 8:8:8 RGB 5:6:5 CMOS sensor pixel clock input 33.4 Config Registers Camera Interrupt Controller Camera Interrupt Request Line From Rx buffers Pixel Clock Domain Preview path Frame Rate Clipping + Color Conversion YCC to RGB Pixel Sampling Module Clipping + Color Conversion RGB to YCC codec_on 2-D Image Scaler Pixel Formatter Packed Formatter APB Interface APB Clock Domain AHB Clock Domain Rx Direct Display FIFO Rx Direct Capture FIFO Core Video Arbiter Camera AHB Master Interface Scatter Mode Support AHB bus Hsync/Len Vsync/Fen APB bus Figure 33-2. Image Sensor Interface Block Diagram Codec path Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream. The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event. For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. When the preview DMA channel is configured and enabled, the preview path is activated and an ‘RGB frame’ is moved to memory. The preview path frame rate is configured with the FRATE field of the ISI_CFG1 register. When the codec DMA channel is configured and enabled, the codec path is activated and a ‘YCbCr 4:2:2 frame’ is captured as soon as the ISI_CDC bit of the ISI Control Register (ISI_CR) is set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 808 When the FULL bit of the ISI_CFG1 register is set, both preview DMA channel and codec DMA channel can operate simultaneously. When a zero is written to the FULL bit of the ISI_CFG1 register, a hardware scheduler checks the FRATE field. If its value is zero, a preview frame is skipped and a codec frame is moved to memory instead. If its value is other than zero, at least one free frame slot is available. The scheduler postpones the codec frame to that free available frame slot. The data stream may be sent on both preview path and codec path if the value of bit ISI_CDC in the ISI_CR is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required. In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CFG2 register. The codec datapath is not available when grayscale image is selected. A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. 33.4.1 Data Timing The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are shown in Figure 33-3 and Figure 33-4. In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the ISI_CR . The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface. There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. Figure 33-3. HSYNC and VSYNC Synchronization Frame ISI_VSYNC 1 line ISI_HSYNC ISI_PCK DATA[7..0] Y Cb Y Cr Y Cb Y Cr Y Cb Y Y Cr Cr Figure 33-4. SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cb FF 00 00 EAV 9D 33.4.2 Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 809 All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table 33-2. Data Ordering in YCbCr Mode Mode Byte 0 Byte 1 Byte 2 Byte 3 Default Cb(i) Y(i) Cr(i) Y(i+1) Mode 1 Cr(i) Y(i) Cb(i) Y(i+1) Mode 2 Y(i) Cb(i) Y(i+1) Cr(i) Mode 3 Y(i) Cr(i) Y(i+1) Cb(i) Table 33-3. RGB Format in Default Mode, RGB_CFG = 00, No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 R7(i) R6(i) R5(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 G7(i) G6(i) G5(i) G4(i) G3(i) G2(i) G1(i) G0(i) Byte 2 B7(i) B6(i) B5(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 3 R7(i+1) R6(i+1) R5(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) Byte 0 R4(i) R3(i) R2(i) R1(i) R0(i) G5(i) G4(i) G3(i) Byte 1 G2(i) G1(i) G0(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 2 R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) G5(i+1) G4(i+1) G3(i+1) Byte 3 G2(i+1) G1(i+1) G0(i+1) B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) RGB 8:8:8 RGB 5:6:5 Table 33-4. RGB Format, RGB_CFG = 10 (Mode 2), No Swap Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 G2(i) G1(i) G0(i) R4(i) R3(i) R2(i) R1(i) R0(i) Byte 1 B4(i) B3(i) B2(i) B1(i) B0(i) G5(i) G4(i) G3(i) Byte 2 G2(i+1) G1(i+1) G0(i+1) R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) Byte 3 B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) G5(i+1) G4(i+1) G3(i+1) RGB 5:6:5 Table 33-5. RGB Format in Default Mode, RGB_CFG = 00, Swap Activated Mode Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 R0(i) R1(i) R2(i) R3(i) R4(i) R5(i) R6(i) R7(i) Byte 1 G0(i) G1(i) G2(i) G3(i) G4(i) G5(i) G6(i) G7(i) Byte 2 B0(i) B1(i) B2(i) B3(i) B4(i) B5(i) B6(i) B7(i) Byte 3 R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) R5(i+1) R6(i+1) R7(i+1) Byte 0 G3(i) G4(i) G5(i) R0(i) R1(i) R2(i) R3(i) R4(i) Byte 1 B0(i) B1(i) B2(i) B3(i) B4(i) G0(i) G1(i) G2(i) Byte 2 G3(i+1) G4(i+1) G5(i+1) R0(i+1) R1(i+1) R2(i+1) R3(i+1) R4(i+1) Byte 3 B0(i+1) B1(i+1) B2(i+1) B3(i+1) B4(i+1) G0(i+1) G1(i+1) G2(i+1) RGB 8:8:8 RGB 5:6:5 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 810 The RGB 5:6:5 input format is processed to be displayed as RGB 5:6:5 format, compliant with the 16-bit mode of the LCD controller. 33.4.3 Clocks The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Management Controller (APMC) through a Programmable Clock output or by an external oscillator connected to the sensor. None of the sensors embed a power management controller, so providing the clock by the APMC is a simple and efficient way to control power consumption of the system. Care must be taken when programming the system clock. The ISI has two clock domains, the sensor master clock and the pixel clock provided by sensor. The two clock domains are not synchronized, but the sensor master clock must be faster than the pixel clock. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 811 33.4.4 Preview Path 33.4.4.1 Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16; values 0 to 15 are forbidden. Table 33-6. Decimation Factor Decimation Value 0–15 16 17 18 19 ... 124 125 126 127 Decimation Factor — 1 1.063 1.125 1.188 ... 7.750 7.813 7.875 7.938 Table 33-7. Decimation and Scaler Offset Values OUTPUT VGA 640*480 QVGA 320*240 CIF 352*288 QCIF 176*144 INPUT 352*288 640*480 800*600 1280*1024 1600*1200 2048*1536 F — 16 20 32 40 51 F 16 32 40 64 80 102 F 16 26 33 56 66 85 F 32 53 66 113 133 170 Example: Input 1280*1024 Output = 640*480 Hratio = 1280/640 = 2 Vratio = 1024/480 = 2.1333 The decimation factor is 2 so 32/16. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 812 Figure 33-5. Resize Examples 32/16 decimation 1280 640 1024 480 1280 56/16 decimation 352 1024 288 33.4.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: C0 0 C1 Y – Y off R G = C 0 – C 2 – C 3 × C b – C boff B C0 C4 0 C r – C roff Example of programmable value to convert YCrCb to RGB:  R = 1,164 ⋅ ( Y – 16 ) + 1,596 ⋅ ( C r – 128 )   G = 1,164 ⋅ ( Y – 16 ) – 0,813 ⋅ ( C r – 128 ) – 0,392 ⋅ ( C b – 128 )   B = 1,164 ⋅ ( Y – 16 ) + 2,107 ⋅ ( C b – 128 ) An example of programmable value to convert from YUV to RGB:  R = Y + 1,596 ⋅ V   G = Y – 0,394 ⋅ U – 0,436 ⋅ V   B = Y + 2,032 ⋅ U SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 813 33.4.4.3 Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:6:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel. When grayscale mode is enabled, two memory formats are supported. One mode supports two pixels per word, and the other mode supports one pixel per word. Table 33-8. Grayscale Memory Mapping Configuration for 12-bit Data GS_MODE DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] 0 P_0[11:4] P_0[3:0], 0000 P_1[11:4] P_1[3:0], 0000 1 P_0[11:4] P_0[3:0], 0000 0 0 33.4.4.4 FIFO and DMA Features Both preview and Codec datapaths contain FIFOs. These asynchronous buffers are used to safely transfer formatted pixels from the pixel clock domain to the AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on the FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of three words. The first one defines the current frame buffer address (named DMA_X_ADDR register), the second defines control information (named DMA_X_CTRL register) and the third defines the next descriptor address (named DMA_X_DSCR). DMA transfer mode with linked list support is available for both codec and preview datapath. The data to be transferred described by an FBD requires several burst accesses. In the following example, the use of two ping-pong frame buffers is described. Example The first FBD, stored at address 0x00030000, defines the location of the first frame buffer. This address is programmed in the ISI user interface DMA_P_DSCR. To enable the descriptor fetch operation, the value 0x00000001 must be written to the DMA_P_CTRL register. LLI_0 and LLI_1 are the two descriptors of the linked list. Destination address: frame buffer ID0 0x02A000 (LLI_0.DMA_P_ADDR) Transfer 0 Control Information, fetch and writeback: 0x00000003 (LLI_0.DMA_P_CTRL) Next FBD address: 0x00030010 (LLI_0.DMA_P_DSCR) Second FBD, stored at address 0x00030010, defines the location of the second frame buffer. Destination address: frame buffer ID1 0x0003A000 (LLI_1.DMA_P_ADDR Transfer 1 Control information fetch and writeback: 0x00000003 (LLI_1.DMA_P_CTRL) Next FBD address: 0x00030000, wrapping to first FBD (LLI_1.DMA_P_DSCR) Using this technique, several frame buffers can be configured through the linked list. Figure 33-6 illustrates a typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 814 Figure 33-6. Three Frame Buffers Application and Memory Mapping Codec Done Codec Request frame n-1 frame n frame n+1 frame n+2 frame n+3 frame n+4 Memory Space Frame Buffer 3 Frame Buffer 0 LCD Frame Buffer 1 ISI config Space 4:2:2 Image Full ROI 33.4.5 Codec Path 33.4.5.1 Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y Cr = C0 C1 C2 Cb –C6 –C7 C8 C3 –C4 –C5 Y off R × G + Cr off B Cb off An example of coefficients is given below:  Y = 0,257 ⋅ R + 0,504 ⋅ G + 0,098 ⋅ B + 16  C = 0,439 ⋅ R – 0,368 ⋅ G – 0,071 ⋅ B + 128  r   C b = – 0,148 ⋅ R – 0,291 ⋅ G + 0,439 ⋅ B + 128 33.4.5.2 Memory Interface Dedicated FIFOs are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported. 33.4.5.3 DMA Features Like preview datapath, codec datapath DMA mode uses linked list operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 815 33.5 Image Sensor Interface (ISI) User Interface Table 33-9. Register Mapping Offset Register Name Access Reset Value 0x00 ISI Configuration 1 Register ISI_CFG1 Read-write 0x00000000 0x04 ISI Configuration 2 Register ISI_CFG2 Read-write 0x00000000 0x08 ISI Preview Size Register ISI_PSIZE Read-write 0x00000000 0x0C ISI Preview Decimation Factor Register ISI_PDECF Read-write 0x00000010 0x10 ISI Color Space Conversion YCrCb To RGB Set 0 Register ISI_Y2R_SET0 Read-write 0x6832CC95 0x14 ISI Color Space Conversion YCrCb To RGB Set 1 Register ISI_Y2R_SET1 Read-write 0x00007102 0x18 ISI Color Space Conversion RGB To YCrCb Set 0 Register ISI_R2Y_SET0 Read-write 0x01324145 0x1C ISI Color Space Conversion RGB To YCrCb Set 1 Register ISI_R2Y_SET1 Read-write 0x01245E38 0x20 ISI Color Space Conversion RGB To YCrCb Set 2 Register ISI_R2Y_SET2 Read-write 0x01384A4B 0x24 ISI Control Register ISI_CR Write-only 0x00000000 0x28 ISI Status Register ISI_SR Read-only 0x00000000 0x2C ISI Interrupt Enable Register ISI_IER Write-only 0x00000000 0x30 ISI Interrupt Disable Register ISI_IDR Write-only 0x00000000 0x34 ISI Interrupt Mask Register ISI_IMR Read-only 0x00000000 0x38 DMA Channel Enable Register ISI_DMA_CHER Write-only 0x00000000 0x3C DMA Channel Disable Register ISI_DMA_CHDR Write-only 0x00000000 0x40 DMA Channel Status Register ISI_DMA_CHSR Read-only 0x00000000 0x44 DMA Preview Base Address Register ISI_DMA_P_ADDR Read-write 0x00000000 0x48 DMA Preview Control Register ISI_DMA_P_CTRL Read-write 0x00000000 0x4C DMA Preview Descriptor Address Register ISI_DMA_P_DSCR Read-write 0x00000000 0x50 DMA Codec Base Address Register ISI_DMA_C_ADDR Read-write 0x00000000 0x54 DMA Codec Control Register ISI_DMA_C_CTRL Read-write 0x00000000 0x58 DMA Codec Descriptor Address Register ISI_DMA_C_DSCR Read-write 0x00000000 0x5C–0xE0 Reserved – – – 0xE4 Write Protection Control Register ISI_WPCR Read-write 0x00000000 0xE8 Write Protection Status Register ISI_WPSR Read-only 0x00000000 0xEC–0xF8 Reserved – – – 0xFC Reserved – – – Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 816 33.5.1 ISI Configuration 1 Register Name: ISI_CFG1 Address: 0xF0034000 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 SFD 23 22 21 20 SLD 15 – 14 7 CRC_SYNC 6 EMB_SYNC 13 12 FULL 11 DISCR 10 9 FRATE 8 5 – 4 PIXCLK_POL 3 VSYNC_POL 2 HSYNC_POL 1 – 0 – THMASK • HSYNC_POL: Horizontal Synchronization Polarity 0: HSYNC active high 1: HSYNC active low • VSYNC_POL: Vertical Synchronization Polarity 0: VSYNC active high 1: VSYNC active low • PIXCLK_POL: Pixel Clock Polarity 0: Data is sampled on rising edge of pixel clock. 1: Data is sampled on falling edge of pixel clock. • EMB_SYNC: Embedded Synchronization 0: Synchronization by HSYNC, VSYNC 1: Synchronization by embedded synchronization sequence SAV/EAV • CRC_SYNC: Embedded Synchronization Correction 0: No CRC correction is performed on embedded synchronization. 1: CRC correction is performed. If the correction is not possible, the current frame is discarded and the CRC_ERR bit is set in the status register. • FRATE: Frame Rate [0..7] 0: All the frames are captured, else one frame every FRATE + 1 is captured. • DISCR: Disable Codec Request 0: Codec datapath DMA interface requires a request to restart. 1: Codec datapath DMA automatically restarts. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 817 • FULL: Full Mode is Allowed 0: The codec frame is transferred to memory when an available frame slot is detected. 1: Both preview and codec DMA channels are operating simultaneously. • THMASK: Threshold Mask Value Name Description 0 BEATS_4 Only 4 beats AHB burst allowed 1 BEATS_8 Only 4 and 8 beats AHB burst allowed 2 BEATS_16 4, 8 and 16 beats AHB burst allowed • SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. • SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 818 33.5.2 ISI Configuration 2 Register Name: ISI_CFG2 Address: 0xF0034004 Access: Read-write Reset: 0x00000000 31 30 29 RGB_CFG 23 28 YCC_SWAP 22 21 20 27 – 26 25 IM_HSIZE 24 19 18 17 16 IM_HSIZE 15 COL_SPACE 14 RGB_SWAP 13 GRAYSCALE 12 RGB_MODE 11 GS_MODE 10 9 IM_VSIZE 8 7 6 5 4 3 2 1 0 IM_VSIZE • IM_VSIZE: Vertical Size of the Image Sensor [0..2047] Vertical size = IM_VSIZE + 1 • GS_MODE: Grayscale Pixel Format Mode 0: 2 pixels per word 1: 1 pixel per word • RGB_MODE: RGB Input Mode 0: RGB 8:8:8 24 bits 1: RGB 5:6:5 16 bits • GRAYSCALE: Grayscale Mode Format Enable 0: Grayscale mode is disabled. 1: Input image is assumed to be grayscale coded. • RGB_SWAP: RGB Format Swap Mode 0: D7 -> R7 1: D0 -> R7 The RGB_SWAP has no effect when the grayscale mode is enabled. • COL_SPACE: Color Space for the Image Data 0: YCbCr 1: RGB • IM_HSIZE: Horizontal Size of the Image Sensor [0..2047] Horizontal size = IM_HSIZE + 1 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 819 • YCC_SWAP: YCrCb Format Swap Mode Defines the YCC image data Value Name Description Byte 0 Cb(i) 0 DEFAULT Byte 1 Y(i) Byte 2 Cr(i) Byte 3 Y(i+1) Byte 0 Cr(i) 1 MODE1 Byte 1 Y(i) Byte 2 Cb(i) Byte 3 Y(i+1) Byte 0 Y(i) 2 MODE2 Byte 1 Cb(i) Byte 2 Y(i+1) Byte 3 Cr(i) Byte 0 Y(i) 3 MODE3 Byte 1 Cr(i) Byte 2 Y(i+1) Byte 3 Cb(i) • RGB_CFG: RGB Pixel Mapping Configuration Defines RGB pattern when RGB_MODE is set to 1 Value Name Description Byte 0 R/G(MSB) 0 DEFAULT Byte 1 G(LSB)/B Byte 2 R/G(MSB) Byte 3 G(LSB)/B Byte 0 B/G(MSB) 1 MODE1 Byte 1 G(LSB)/R Byte 2 B/G(MSB) Byte 3 G(LSB)/R Byte 0 G(LSB)/R 2 MODE2 Byte 1 B/G(MSB) Byte 2 G(LSB)/R Byte 3 B/G(MSB) Byte 0 G(LSB)/B 3 MODE3 Byte 1 R/G(MSB) Byte 2 G(LSB)/B Byte 3 R/G(MSB) If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 820 33.5.3 ISI Preview Size Register Name: ISI_PSIZE Address: 0xF0034008 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 19 18 17 11 – 10 – 9 3 2 1 24 PREV_HSIZE 16 PREV_HSIZE 15 – 14 – 13 – 12 – 7 6 5 4 8 PREV_VSIZE 0 PREV_VSIZE • PREV_VSIZE: Vertical Size for the Preview Path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode) • PREV_HSIZE: Horizontal Size for the Preview Path Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 821 33.5.4 ISI Preview Decimation Factor Register Name: ISI_PDECF Address: 0xF003400C Access: Read-write Reset: 0x00000010 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 DEC_FACTOR • DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 822 33.5.5 ISI Color Space Conversion YCrCb to RGB Set 0 Register Name: ISI_Y2R_SET0 Address: 0xF0034010 Access: Read-write Reset: 0x6832CC95 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/128, ranges from 0 to 1.9921875. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, ranges from 0 to 1.9921875. • C2: Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/128, ranges from 0 to 1.9921875. • C3: Color Space Conversion Matrix Coefficient C3 C3 element default step is 1/128, ranges from 0 to 1.9921875. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 823 33.5.6 ISI Color Space Conversion YCrCb to RGB Set 1 Register Name: ISI_Y2R_SET1 Address: 0xF0034014 Access: Read-write Reset: 0x00007102 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 Cboff 13 Croff 12 Yoff 11 – 10 – 9 – 8 C4 7 6 5 4 3 2 1 0 C4 • C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. • Yoff: Color Space Conversion Luminance Default Offset 0: No offset 1: Offset = 128 • Croff: Color Space Conversion Red Chrominance Default Offset 0: No offset 1: Offset = 16 • Cboff: Color Space Conversion Blue Chrominance Default Offset 0: No offset 1: Offset = 16 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 824 33.5.7 ISI Color Space Conversion RGB to YCrCb Set 0 Register Name: ISI_R2Y_SET0 Address: 0xF0034018 Access: Read-write Reset: 0x01324145 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Roff 23 – 22 21 20 19 C2 18 17 16 15 – 14 13 12 11 C1 10 9 8 7 – 6 5 4 3 C0 2 1 0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. • C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875. • C2: Color Space Conversion Matrix Coefficient C2 C2 element default step is 1/512, from 0 to 0.2480468875. • Roff: Color Space Conversion Red Component Offset 0: No offset 1: Offset = 16 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 825 33.5.8 ISI Color Space Conversion RGB to YCrCb Set 1 Register Name: ISI_R2Y_SET1 Address: 0xF003401C Access: Read-write Reset: 0x01245E38 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Goff 23 – 22 21 20 19 C5 18 17 16 15 – 14 13 12 11 C4 10 9 8 7 – 6 5 4 3 C3 2 1 0 • C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. • C4: Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375. • C5: Color Space Conversion Matrix Coefficient C5 C1 element default step is 1/512, ranges from 0 to 0.2480468875. • Goff: Color Space Conversion Green Component Offset 0: No offset 1: Offset = 128 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 826 33.5.9 ISI Color Space Conversion RGB to YCrCb Set 2 Register Name: ISI_R2Y_SET2 Address: 0xF0034020 Access: Read-write Reset: 0x01384A4B 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 Boff 23 – 22 21 20 19 C8 18 17 16 15 – 14 13 12 11 C7 10 9 8 7 – 6 5 4 3 C6 2 1 0 • C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. • C7: Color Space Conversion Matrix Coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375. • C8: Color Space Conversion Matrix Coefficient C8 C8 element default step is 1/128, ranges from 0 to 0.9921875. • Boff: Color Space Conversion Blue Component Offset 0: No offset 1: Offset = 128 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 827 33.5.10 ISI Control Register Name: ISI_CR Address: 0xF0034024 Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 ISI_CDC 7 – 6 – 5 – 4 – 3 – 2 ISI_SRST 1 ISI_DIS 0 ISI_EN • ISI_EN: ISI Module Enable Request Write a one to this bit to enable the module. Software must poll ENABLE bit in the ISI_SR to verify that the command has successfully completed. • ISI_DIS: ISI Module Disable Request Write a one to this bit to disable the module. If both ISI_EN and ISI_DIS are asserted at the same time, the disable request is not taken into account. Software must poll DIS_DONE bit in the ISI_SR to verify that the command has successfully completed. • ISI_SRST: ISI Software Reset Request Write a one to this bit to request a software reset of the module. Software must poll SRST bit in the ISI_SR to verify that the software request command has terminated. • ISI_CDC: ISI Codec Request Write a one to this bit to enable the codec datapath and capture a full resolution frame. A new request cannot be taken into account while CDC_PND bit is active in the ISI_SR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 828 33.5.11 ISI Status Register Name: ISI_SR Address: 0xF0034028 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 SIP 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 CDC_PND 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 ENABLE • ENABLE: Module Enable This bit is a status bit. 0: Module is disabled 1: Module is enabled • DIS_DONE: Module Disable Request has Terminated 0: Indicates that the request is not completed (if a request was issued). 1: Disable request has completed. This flag is reset after a read operation. • SRST: Module Software Reset Request has Terminated 0: Indicates that the request is not completed (if a request was issued). 1: Software reset request has completed. This flag is reset after a read operation. • CDC_PND: Pending Codec Request This bit is a status bit. 0: Indicates that no Codec request is pending 1: Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is postponed to the next frame. • VSYNC: Vertical Synchronization 0: Indicates that the vertical synchronization has not been detected since the last read of the status register. 1: Indicates that a vertical synchronization has been detected since the last read of the status register. • PXFR_DONE: Preview DMA Transfer has Terminated When set, this bit indicates that the DATA transfer on the preview channel has completed. This flag is reset after a read operation. 0: Preview transfer done not detected. 1: Preview transfer done detected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 829 • CXFR_DONE: Codec DMA Transfer has Terminated When set, this bit indicates that the DATA transfer on the codec channel has completed. This flag is reset after a read operation. 0: Codec transfer done not detected. 1: Codec transfer done detected. • SIP: Synchronization in Progress This is a status bit. When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the clock domain synchronization. 0: The clock domain synchronization process is terminated. 1: This bit is set when the clock domain synchronization operation occurs. No modification of the channel status is allowed when this bit is set, to guarantee data integrity. • P_OVR: Preview Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation. • C_OVR: Codec Datapath Overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. This flag is reset after a read operation. • CRC_ERR: CRC Synchronization Error 0: No CRC error in the embedded synchronization frame (SAV/EAV) 1: Embedded Synchronization Correction is enabled (CRC_SYNC bit is set) in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one. This flag is reset after a read operation. • FR_OVR: Frame Rate Overrun 0: No frame overrun 1: Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs. This flag is reset after a read operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 830 33.5.12 ISI Interrupt Enable Register Name: ISI_IER Address: 0xF003402C Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 – 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 – • DIS_DONE: Disable Done Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • SRST: Software Reset Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • VSYNC: Vertical Synchronization Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • PXFR_DONE: Preview DMA Transfer Done Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • CXFR_DONE: Codec DMA Transfer Done Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • P_OVR: Preview Datapath Overflow Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • C_OVR: Codec Datapath Overflow Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 831 • CRC_ERR: Embedded Synchronization CRC Error Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. • FR_OVR: Frame Rate Overflow Interrupt Enable 0: No effect 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 832 33.5.13 ISI Interrupt Disable Register Name: ISI_IDR Address: 0xF0034030 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 – 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 – • DIS_DONE: Disable Done Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • SRST: Software Reset Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • VSYNC: Vertical Synchronization Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • PXFR_DONE: Preview DMA Transfer Done Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • CXFR_DONE: Codec DMA Transfer Done Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • P_OVR: Preview Datapath Overflow Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • C_OVR: Codec Datapath Overflow Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 833 • CRC_ERR: Embedded Synchronization CRC Error Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. • FR_OVR: Frame Rate Overflow Interrupt Disable 0: No effect 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 834 33.5.14 ISI Interrupt Mask Register Name: ISI_IMR Address: 0xF0034034 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 FR_OVR 26 CRC_ERR 25 C_OVR 24 P_OVR 23 – 22 – 21 – 20 – 19 – 18 – 17 CXFR_DONE 16 PXFR_DONE 15 – 14 – 13 – 12 – 11 – 10 VSYNC 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SRST 1 DIS_DONE 0 – • DIS_DONE: Module Disable Operation Completed 0: The disable completed interrupt is disabled. 1: The disable completed interrupt is enabled. • SRST: Software Reset Completed 0: The software reset completed interrupt is disabled. 1: The software reset completed interrupt is enabled. • VSYNC: Vertical Synchronization 0: The vertical synchronization interrupt is enabled. 1: The vertical synchronization interrupt is disabled. • PXFR_DONE: Preview DMA Transfer Interrupt 0: The Preview DMA transfer completed interrupt is enabled 1: The Preview DMA transfer completed interrupt is disabled • CXFR_DONE: Codec DMA Transfer Interrupt 0: The Codec DMA transfer completed interrupt is enabled 1: The Codec DMA transfer completed interrupt • P_OVR: FIFO Preview Overflow 0: The preview FIFO overflow interrupt is disabled. 1: The preview FIFO overflow interrupt is enabled. • C_OVR: FIFO Codec Overflow 0: The codec FIFO overflow interrupt is disabled. 1: The codec FIFO overflow interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 835 • CRC_ERR: CRC Synchronization Error 0: The CRC error interrupt is disabled. 1: The CRC error interrupt is enabled. • FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 836 33.5.15 DMA Channel Enable Register Name: ISI_DMA_CHER Address: 0xF0034038 Access: Write-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_EN 0 P_CH_EN • P_CH_EN: Preview Channel Enable Write a one to this bit to enable the preview DMA channel. • C_CH_EN: Codec Channel Enable Write a one to this bit to enable the codec DMA channel. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 837 33.5.16 DMA Channel Disable Register Name: ISI_DMA_CHDR Address: 0xF003403C Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_DIS 0 P_CH_DIS • P_CH_DIS: Preview Channel Disable Request 0: No effect 1: Disables the channel. Poll P_CH_S in DMA_CHSR to verify that the preview channel status has been successfully modified. • C_CH_DIS: Codec Channel Disable Request 0: No effect 1: Disables the channel. Poll C_CH_S in DMA_CHSR to verify that the codec channel status has been successfully modified. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 838 33.5.17 DMA Channel Status Register Name: ISI_DMA_CHSR Address: 0xF0034040 Access: Read-only Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 C_CH_S 0 P_CH_S • P_CH_S: Preview DMA Channel Status 0: Indicates that the Preview DMA channel is disabled 1: Indicates that the Preview DMA channel is enabled • C_CH_S: Code DMA Channel Status 0: Indicates that the Codec DMA channel is disabled 1: Indicates that the Codec DMA channel is enabled SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 839 33.5.18 DMA Preview Base Address Register Name: ISI_DMA_P_ADDR Address: 0xF0034044 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_ADDR 23 22 21 20 P_ADDR 15 14 13 12 P_ADDR 7 6 5 4 P_ADDR • P_ADDR: Preview Image Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 840 33.5.19 DMA Preview Control Register Name: ISI_DMA_P_CTRL Address: 0xF0034048 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 P_DONE 2 P_IEN 1 P_WB 0 P_FETCH • P_FETCH: Descriptor Fetch Control Bit 0: Preview channel fetch operation is disabled. 1: Preview channel fetch operation is enabled. • P_WB: Descriptor Writeback Control Bit 0: Preview channel writeback operation is disabled. 1: Preview channel writeback operation is enabled. • P_IEN: Transfer Done Flag Control 0: Preview transfer done flag generation is enabled. 1: Preview transfer done flag generation is disabled. • P_DONE: Preview Transfer Done This bit is only updated in the memory. 0: The transfer related to this descriptor has not been performed. 1: The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when writeback operation is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 841 33.5.20 DMA Preview Descriptor Address Register Name: ISI_DMA_P_DSCR Address: 0xF003404C Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – P_DSCR 23 22 21 20 P_DSCR 15 14 13 12 P_DSCR 7 6 5 4 P_DSCR • P_DSCR: Preview Descriptor Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 842 33.5.21 DMA Codec Base Address Register Name: ISI_DMA_C_ADDR Address: 0xF0034050 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_ADDR 23 22 21 20 C_ADDR 15 14 13 12 C_ADDR 7 6 5 4 C_ADDR • C_ADDR: Codec Image Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 843 33.5.22 DMA Codec Control Register Name: ISI_DMA_C_CTRL Address: 0xF0034054 Access: Read-write Reset: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 C_DONE 2 C_IEN 1 C_WB 0 C_FETCH • C_FETCH: Descriptor Fetch Control Bit 0: Codec channel fetch operation is disabled. 1: Codec channel fetch operation is enabled. • C_WB: Descriptor Writeback Control Bit 0: Codec channel writeback operation is disabled. 1: Codec channel writeback operation is enabled. • C_IEN: Transfer Done Flag Control 0: Codec transfer done flag generation is enabled. 1: Codec transfer done flag generation is disabled. • C_DONE: Codec Transfer Done This bit is only updated in the memory. 0: The transfer related to this descriptor has not been performed. 1: The transfer related to this descriptor has completed. This bit is updated in memory at the end of the transfer, when. writeback operation is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 844 33.5.23 DMA Codec Descriptor Address Register Name: ISI_DMA_C_DSCR Address: 0xF0034058 Access: Read-write Reset: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – C_DSCR 23 22 21 20 C_DSCR 15 14 13 12 C_DSCR 7 6 5 4 C_DSCR • C_DSCR: Codec Descriptor Base Address This address is word aligned. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 845 33.5.24 ISI Write Protection Control Register Name: ISI_WPCR Address: 0xF00340E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x495349 (“ISI” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x495349 (“ISI” in ASCII). • WPKEY: Write Protection Key Password Value Name 0x495349 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 846 33.5.25 ISI Write Protection Status Register Name: ISI_WPSR Address: 0xF00340E8 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – • WPVS: Write Protection Violation Status Value Description 0 No Write Protection Violation occurred since the last read of this register (WP_SR). 1 Write Protection detected unauthorized attempt to write a control register had occurred (since the last read). • WPVSRC: Write Protection Violation Source Value Description 0 No Write Protection Violation occurred since the last read of this register (WP_SR). 1 Write access in ISI_CFG1 while Write Protection was enabled (since the last read). 2 Write access in ISI_CFG2 while Write Protection was enabled (since the last read). 3 Write access in ISI_PSIZE while Write Protection was enabled (since the last read). 4 Write access in ISI_PDECF while Write Protection was enabled (since the last read). 5 Write access in ISI_Y2R_SET0 while Write Protection was enabled (since the last read). 6 Write access in ISI_Y2R_SET1 while Write Protection was enabled (since the last read). 7 Write access in ISI_R2Y_SET0 while Write Protection was enabled (since the last read). 8 Write access in ISI_R2Y_SET1 while Write Protection was enabled (since the last read). 9 Write access in ISI_R2Y_SET2 while Write Protection was enabled (since the last read). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 847 34. USB High Speed Device Port (UDPHS) 34.1 Description The USB High Speed Device Port (UDPHS) is compliant with the Universal Serial Bus (USB), rev 2.0 High Speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one, two or three banks of a Dual-port RAM used to store the current data payload. If two or three banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 848 34.2 34.3 Embedded Characteristics  1 Device High Speed  1 UTMI transceiver shared between Host and Device  USB v2.0 High Speed Compliant, 480 Mbit/s  16 Endpoints up to 1024 bytes  Embedded Dual-port RAM for Endpoints  Suspend/Resume Logic (Command of UTMI)  Up to Three Memory Banks for Endpoints (Not for Control Endpoint)  8 KBytes of DPRAM Block Diagram Figure 34-1. Block Diagram APB Interface APB bus ctrl status DHSDP DHSDM AHB1 AHB bus Rd/Wr/Ready DMA AHB0 AHB bus UTMI USB2.0 CORE DFSDP DP DFSDM DM AHB Switch Local AHB Slave interface EPT Alloc 32 bits DPRAM System Clock Domain 16/8 bits USB Clock Domain PMC SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 849 34.4 Typical Connection Figure 34-2. Board Schematic PIO (VBUS DETECT) 15k Ω (1) "B" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 2 3 4 DHSDM/DFSDM Shell = Shield (1) 22k Ω CRPB CRPB:1µF to 10µF DHSDP/DFSDP 5K62 ± 1%Ω VBG 10 pF GNDUTMI Note: 34.5 The values shown on the 22 kΩ and 15 kΩ resistors are only valid with 3V3 supplied PIOs. Product Dependencies 34.5.1 Power Management The UDPHS is not continuously clocked. For using the UDPHS, the programmer must first enable the UDPHS Clock in the Power Management Controller Peripheral Clock Enable Register (PMC_PCER). Then enable the PLL in the PMC UTMI Clock Configuration Register (CKGR_UCKR). Finally, enable BIAS in CKGR_UCKR. However, if the application does not require UDPHS operations, the UDPHS clock can be stopped when not needed and restarted later. 34.5.2 Interrupt The UDPHS interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the UDPHS Table 34-1. Peripheral IDs Instance ID UDPHS 33 interrupt requires the Interrupt Controller to be programmed first. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 850 34.6 Functional Description 34.6.1 UTMI transceivers Sharing The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL register. Figure 34-3. USB Selection others Transceivers HS Transceiver EN_UDPHS 0 Others Ports 1 PA HS USB Host HS EHCI FS OHCI DMA HS USB Device DMA 34.6.2 USB V2.0 High Speed Device Port Introduction The USB V2.0 High Speed Device Port provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB Device through a set of communication flows. 34.6.3 USB V2.0 High Speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device. A device provides several logical communication pipes with the host. To each logical pipe is associated an endpoint. Transfer through a pipe belongs to one of the four transfer types:  Control Transfers: Used to configure a device at attach time and can be used for other device-specific purposes, including control of other pipes on the device.  Bulk Data Transfers: Generated or consumed in relatively large burst quantities and have wide dynamic latitude in transmission constraints.  Interrupt Data Transfers: Used for timely but reliable delivery of data, for example, characters or coordinates with human-perceptible echo or feedback response characteristics.  Isochronous Data Transfers: Occupy a prenegotiated amount of USB bandwidth with a prenegotiated delivery latency. (Also called streaming real time transfers.) As indicated below, transfers are sequential events carried out on the USB bus. Endpoints must be configured according to the transfer type they handle. Table 34-2. USB Communication Flow Transfer Direction Bandwidth Endpoint Size Error Detection Retrying Bidirectional Not guaranteed 8, 16, 32, 64 Yes Automatic Isochronous Unidirectional Guaranteed 8-1024 Yes No Interrupt Unidirectional Not guaranteed 8-1024 Yes Yes Bulk Unidirectional Not guaranteed 8-512 Yes Yes Control SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 851 34.6.4 USB Transfer Event Definitions A transfer is composed of one or several transactions as shown in the following table. Table 34-3. USB Transfer Events Transfer Direction Type Transaction • Setup transaction → Data IN transactions → Status OUT transaction CONTROL (bidirectional) • Setup transaction → Data OUT transactions → Status IN transaction Control Transfer (1) • Setup transaction → Status IN transaction • Data IN transaction → Data IN transaction Bulk IN Transfer IN (device toward host) • Data IN transaction → Data IN transaction Interrupt IN Transfer Isochronous IN Transfer OUT (host toward device) (2) • Data IN transaction → Data IN transaction Bulk OUT Transfer • Data OUT transaction → Data OUT transaction Interrupt OUT Transfer • Data OUT transaction → Data OUT transaction Isochronous OUT Transfer (2) • Data OUT transaction → Data OUT transaction Notes: 1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake. 2. Isochronous transfers must use endpoints configured with two or three banks. An endpoint handles all transactions related to the type of transfer for which it has been configured. Table 34-4. UDPHS Endpoint Description Mnemonic Nb Bank DMA High Band Width Max. Endpoint Size Endpoint Type 0 EPT_0 1 N N 64 Control 1 EPT_1 3 Y Y 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 2 EPT_2 3 Y Y 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 3 EPT_3 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 4 EPT_4 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 5 EPT_5 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 6 EPT_6 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 7 EPT_7 2 Y N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 8 EPT_8 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 9 EPT_9 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 10 EPT_10 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 11 EPT_11 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 12 EPT_12 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 13 EPT_13 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 14 EPT_14 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt 15 EPT_15 2 N N 1024 Ctrl/Bulk/Iso(34.3)/Interrupt Endpoint # Note: 1. In Isochronous Mode (Iso), it is preferable that High Band Width capability is available. The size of internal DPRAM is 8 KB. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 852 Suspend and resume are automatically detected by the UDPHS device, which notifies the processor by raising an interrupt. 34.6.5 USB V2.0 High Speed BUS Transactions Each transfer results in one or more transactions over the USB bus. There are five kinds of transactions flowing across the bus in packets: 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction 4. Status IN Transaction 5. Status OUT Transaction Figure 34-4. Control Read and Write Sequences Setup Stage Control Write Setup TX Data Stage Data OUT TX No Data Control Setup TX Data OUT TX Data Stage Setup Stage Control Read Status Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Status IN TX Status Stage Data IN TX Status OUT TX A status IN or OUT transaction is identical to a data IN or OUT transaction. 34.6.6 Endpoint Configuration The endpoint 0 is always a control endpoint, it must be programmed and active in order to be enabled when the End Of Reset interrupt occurs. To configure the endpoints:  Fill the configuration register (UDPHS_EPTCFG) with the endpoint size, direction (IN or OUT), type (CTRL, Bulk, IT, ISO) and the number of banks.  Fill the number of transactions (NB_TRANS) for isochronous endpoints. Note: For control endpoints the direction has no effect.  Verify that the EPT_MAPD flag is set. This flag is set if the endpoint size and the number of banks are correct compared to the FIFO maximum capacity and the maximum number of allowed banks.  Configure control flags of the endpoint and enable it in UDPHS_EPTCTLENBx according to “UDPHS Endpoint Control Disable Register (Isochronous Endpoint)” on page 897. Control endpoints can generate interrupts and use only 1 bank. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 853 All endpoints (except endpoint 0) can be configured either as Bulk, Interrupt or Isochronous. See Table 34-4. UDPHS Endpoint Description. The maximum packet size they can accept corresponds to the maximum endpoint size. Note: The endpoint size of 1024 is reserved for isochronous endpoints. The size of the DPRAM is 8 KB. The DPR is shared by all active endpoints. The memory size required by the active endpoints must not exceed the size of the DPRAM. SIZE_DPRAM = SIZE _EPT0 + NB_BANK_EPT1 x SIZE_EPT1 + NB_BANK_EPT2 x SIZE_EPT2 + NB_BANK_EPT3 x SIZE_EPT3 + NB_BANK_EPT4 x SIZE_EPT4 + NB_BANK_EPT5 x SIZE_EPT5 + NB_BANK_EPT6 x SIZE_EPT6 +... (refer to 34.7.8 UDPHS Endpoint Configuration Register) If a user tries to configure endpoints with a size the sum of which is greater than the DPRAM, then the EPT_MAPD is not set. The application has access to the physical block of DPR reserved for the endpoint through a 64 KB logical address space. The physical block of DPR allocated for the endpoint is remapped all along the 64 KB logical address space. The application can write a 64 KB buffer linearly. Figure 34-5. Logical Address Space for DPR Access DPR 8 to 64 B 1 bank Logical address 8 to 64 B 64 KB EP0 8 to1024 B 64 KB 8 to1024 B 8 to1024 B EP1 ... 64 KB EP2 8 to1024 B 8 to1024 B x banks y banks z banks 8 to1024 B 64 KB EP3 ... Configuration examples of UDPHS_EPTCTLx (UDPHS Endpoint Control Disable Register (Isochronous Endpoint)) for Bulk IN endpoint type follow below.  With DMA  AUTO_VALID: Automatically validate the packet and switch to the next bank.  EPT_ENABL: Enable endpoint. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 854  Without DMA:  TXRDY: An interrupt is generated after each transmission.  EPT_ENABL: Enable endpoint. Configuration examples of Bulk OUT endpoint type follow below.   With DMA  AUTO_VALID: Automatically validate the packet and switch to the next bank.  EPT_ENABL: Enable endpoint. Without DMA  RXRDY_TXKL: An interrupt is sent after a new packet has been stored in the endpoint FIFO.  EPT_ENABL: Enable endpoint. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 855 34.6.7 DPRAM Management Endpoints can only be allocated in ascending order, from the endpoint 0 to the last endpoint to be allocated. The user shall therefore configure them in the same order. The allocation of an endpoint x starts when the Number of Banks field in the UDPHS Endpoint Configuration Register (UDPHS_EPTCFGx.BK_NUMBER) is different from zero. Then, the hardware allocates a memory area in the DPRAM and inserts it between the x-1 and x+1 endpoints. The x+1 endpoint memory window slides up and its data is lost. Note that the following endpoint memory windows (from x+2) do not slide. Disabling an endpoint, by writing a one to the Endpoint Disable bit in the UDPHS Endpoint Control Disable Register (UDPHS_EPTCTLDISx.EPT_DISABL), does not reset its configuration:  The Endpoint Banks (UDPHS_EPTCFGx.BK_NUMBER),  The Endpoint Size (UDPHS_EPTCFGx.EPT_SIZE),  The Endpoint Direction (UDPHS_EPTCFGx.EPT_DIR), and  The Endpoint Type (UDPHS_EPTCFGx.EPT_TYPE). To free its memory, the user shall write a zero to the UDPHS_EPTCFGx.BK_NUMBER field. The x+1 endpoint memory window then slides down and its data is lost. Note that the following endpoint memory windows (from x+2) do not slide. Figure 34-6 on page 856 illustrates the allocation and reorganization of the DPRAM in a typical example. Figure 34-6. Allocation and Reorganization of the DPRAM Free Memory Free Memory Free Memory EPT5 EPT5 EPT5 Free Memory EPT5 Conflict EPT4 EPT4 EPT4 EPT3 EPT3 (always allocated) EPT4 EPT2 EPT2 EPT2 EPT2 EPT1 EPT1 EPT1 EPT1 EPT0 EPT0 EPT0 EPT0 Device: Device: EPT4 Lost Memory Device: Device: UDPHS_EPTCTLENBx.EPT_ENABL = 1 UDPHS_EPTCTLDIS3.EPT_DISABL = 1 UDPHS_EPTCFG3.BK_NUMBER = 0 UDPHS_EPTCFGx.BK_NUMBER 0 Endpoints 0..5 Activated Endpoint 3 Disabled EPT3 (larger size) UDPHS_EPTCTLENB3.EPT_ENABL = 1 UDPHS_EPTCFG3.BK_NUMBER 0 Endpoint 3 Memory Freed Endpoint 3 Activated 1. The endpoints 0 to 5 are enabled, configured and allocated in ascending order. Each endpoint then owns a memory area in the DPRAM. 2. The endpoint 3 is disabled, but its memory is kept allocated by the controller. 3. In order to free its memory, its UDPHS_EPTCFGx.BK_NUMBER field is written to zero. The endpoint 4 memory window slides down, but the endpoint 5 does not move. 4. If the user chooses to reconfigure the endpoint 3 with a larger size, the controller allocates a memory area after the endpoint 2 memory area and automatically slides up the endpoint 4 memory window. The endpoint 5 does not SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 856 move and a memory conflict appears as the memory windows of the endpoints 4 and 5 overlap. The data of these endpoints is potentially lost. Notes: 1. There is no way the data of the endpoint 0 can be lost (except if it is de-allocated) as the memory allocation and de-allocation may affect only higher endpoints. 2. Deactivating then reactivating the same endpoint with the same configuration only modifies temporarily the controller DPRAM pointer and size for this endpoint. Nothing changes in the DPRAM, higher endpoints seem not to have been moved and their data is preserved as far as nothing has been written or received into them while changing the allocation state of the first endpoint. 3. When the user writes a value different from zero to the UDPHS_EPTCFGx.BK_NUMBER field, the Endpoint Mapped bit (UDPHS_EPTCFGx.EPT_MAPD) is set only if the configured size and number of banks are correct as compared to the endpoint maximal allowed values and to the maximal FIFO size (i.e., the DPRAM size). The UDPHS_EPTCFGx.EPT_MAPD value does not consider memory allocation conflicts. 34.6.8 Transfer With DMA USB packets of any length may be transferred when required by the UDPHS device. These transfers always feature sequential addressing. Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance boost with paged memories. These clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur only once instead of several times, during a single big USB packet DMA transfer in case another AHB master addresses the memory. The locked bursts result in up to 128-word single-cycle unbroken AHB bursts for bulk endpoints and 256word single-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then controlled by the lowest programmed USB endpoint size (EPT_SIZE field in the UDPHS_EPTCFGx register) and DMA Size (BUFF_LENGTH field in the UDPHS_DMACONTROLx register). The USB 2.0 device average throughput may be up to nearly 60 Mbyte/s. Its internal slave average access latency decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. If at least 0 wait-state word burst capability is also provided by the external DMA AHB bus slaves, each of both DMA AHB busses need less than 50% bandwidth allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz. The UDPHS DMA Channel Transfer Descriptor is described in “UDPHS DMA Channel Transfer Descriptor” on page 918. Note: In case of debug, be careful to address the DMA to an SRAM address even if a remap is done. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 857 Figure 34-7. Example of DMA Chained List Transfer Descriptor UDPHS Registers (Current Transfer Descriptor) Next Descriptor Address DMA Channel Address Transfer Descriptor UDPHS Next Descriptor DMA Channel Control Next Descriptor Address DMA Channel Address DMA Channel Address Transfer Descriptor DMA Channel Control Next Descriptor Address DMA Channel Control DMA Channel Address DMA Channel Control Null Memory Area Data Buff 1 Data Buff 2 Data Buff 3 34.6.9 Transfer Without DMA Important. If the DMA is not to be used, it is necessary that it be disabled because otherwise it can be enabled by previous versions of software without warning. If this should occur, the DMA can process data before an interrupt without knowledge of the user. The recommended means to disable DMA is as follows: // Reset IP UDPHS AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS; AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS; // With OR without DMA !!! for( i=1; iUDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) { // RESET endpoint canal DMA: // DMA stop channel command AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Disable endpoint AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF; // Reset endpoint config AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0; // Reset DMA channel (Buff count and Control field) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0x02; // NON STOP command // Reset DMA channel 0 (STOP) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Clear DMA channel status (read the register for clear it) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS = AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS; } SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 858 34.6.10 Handling Transactions with USB V2.0 Device Peripheral 34.6.10.1 Setup Transaction The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by the application, the UDPHS accepts the next packets sent over the device endpoint. When a valid setup packet is accepted by the UDPHS:  The UDPHS device automatically acknowledges the setup packet (sends an ACK response)  Payload data is written in the endpoint  Sets the RX_SETUP interrupt  The BYTE_COUNT field in the UDPHS_EPTSTAx register is updated An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read the setup packet in the FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register to acknowledge the setup stage. If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by the device. Then, the device still accepts the setup stage. (See Section 34.6.10.15 “STALL” on page 869). 34.6.10.2 NYET NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the PING protocol. High Speed devices must support an improved NAK mechanism for Bulk OUT and control endpoints (except setup stage). This mechanism allows the device to tell the host whether it has sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via Ping Flow Control). The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are automatically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to force a NAK response by using the NYET_DIS bit). If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this means that the endpoint accepted the data but does not have room for another data payload. The host controller must return to using a PING token until the endpoint indicates it has space available. Figure 34-8. NYET Example with Two Endpoint Banks data 0 ACK t=0 data 1 NYET t = 125 µs Bank 1 E Bank 0 F PING ACK t = 250 µs Bank 1 F Bank 1 F Bank 0 E' Bank 0 E data 0 NYET t = 375 µs Bank 1 F Bank 0 E PING t = 500 µs Bank 1 F Bank 0 F NACK PING t = 625 µs Bank 1 E' Bank 0 F ACK E: empty E': begin to empty F: full Bank 1 E Bank 0 F 34.6.10.3 Data IN 34.6.10.4 Bulk IN or Interrupt IN Data IN packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. There are three ways for an application to transfer a buffer in several packets over the USB:  packet by packet (see 34.6.10.5 below)  64 KB (see 34.6.10.5 below) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 859  DMA (see 34.6.10.6 below) 34.6.10.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host) The application can write one or several banks. A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint. Algorithm Description for Each Packet:  The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write access to the DPR.  The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window.  The application sets TXRDY flag in the UDPHS_EPTSETSTAx register. The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register. Algorithm Description to Fill Several Packets: Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register. The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware.  The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait that at least one bank is free.  The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS.  If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the TXRDY bit in the UDPHS_EPTSETSTAx register. The application is notified that all banks are free, so that it is possible to write another burst of packets by the BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers. This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate. A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register. 34.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer. Example DMA configuration: 1. Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3. Program UDPHS_ DMACONTROLx:  Size of buffer to send: size of the buffer to be sent to the host.  END_B_EN: The endpoint can validate the packet (according to the values programmed in the AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See “UDPHS Endpoint Control Disable Register (Isochronous Endpoint)” on page 897 and Figure 34-13. Autovalid with DMA)  END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0.  CHANN_ENB: Run and stop at end of buffer The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 860 A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field (Load Next Descriptor Now) in UDPHS_DMACONTROLx register. The structure that defines this transfer descriptor must be aligned. Each buffer to be transferred must be described by a DMA Transfer descriptor (see “UDPHS DMA Channel Transfer Descriptor” on page 918). Transfer descriptors are chained. Before executing transfer of the buffer, the UDPHS may fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register. To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped. To do so, INTDIS_DMA and TXRDY may be set in the UDPHS_EPTCTLENBx register. It is also possible for the application to wait for the completion of all transfers. In this case the LDNXT_DSC field in the last transfer descriptor UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1. Then the application can chain a new transfer descriptor. The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be used to stop DMA transfers in case of errors. The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx register). Figure 34-9. Data IN Transfer for Endpoint with One Bank Prevous Data IN TX USB Bus Packets Token IN Microcontroller Loads Data in FIFO Data IN 1 TXRDY Flag (UDPHS_EPTSTAx) Set by firmware ACK Token IN NAK Cleared by hardware Data is Sent on USB Bus Token IN Data IN 2 ACK Set by the firmware Cleared by hardware Interrupt Pending TX_COMPLT Flag (UDPHS_EPTSTAx) Payload in FIFO Set by hardware DPR access by firmware FIFO Content Interrupt Pending Data IN 1 Load in progress Cleared by firmware Cleared by firmware DPR access by hardware Data IN 2 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 861 Figure 34-10.Data IN Transfer for Endpoint with Two Banks Microcontroller Load Data IN Bank 0 USB Bus Packets Microcontroller Load Data IN Bank 1 UDPHS Device Send Bank 0 Token IN Data IN ACK Microcontroller Load Data IN Bank 0 UDPHS Device Send Bank 1 Data IN Token IN ACK Set by Firmware, Cleared by Hardware Data Payload Written switch to next bank in FIFO Bank 0 Virtual TXRDY bank 0 (UDPHS_EPTSTAx) Cleared by Hardware Data Payload Fully Transmitted Virtual TXRDY bank 1 (UDPHS_EPTSTAx) Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending TX_COMPLT Flag (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Set by Hardware Set by Hardware Interrupt Cleared by Firmware Written by Microcontroller Read by USB Device FIFO (DPR) Bank1 Written by Microcontroller Written by Microcontroller Read by UDPHS Device Figure 34-11.Data IN Followed By Status OUT Transfer at the End of a Control Transfer Device Sends the Last Data Payload to Host USB Bus Packets Token IN Data IN Device Sends a Status OUT to Host ACK Token OUT Data OUT (ZLP) ACK Token OUT Data OUT (ZLP) ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Note: Cleared by Firmware A NAK handshake is always generated at the first status stage token. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 862 Figure 34-12.Data OUT Followed by Status IN Transfer Host Sends the Last Data Payload to the Device USB Bus Packets Token OUT Data OUT Device Sends a Status IN to the Host ACK Token IN Data IN ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Cleared by Firmware Set by Hardware TXRDY (UDPHS_EPTSTAx) Set by Firmware Note: Clear by Hardware Before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage). If not certain (non-predictable data stage length), then the software should wait for a NAK-IN interrupt before proceeding to the status stage. This precaution should be taken to avoid collision in the FIFO. Figure 34-13.Autovalid with DMA Bank (system) Write Bank 0 Bank 1 write bank 0 write bank 1 bank 0 is full Bank 1 Bank 0 Bank 1 write bank 0 bank 1 is full bank 0 is full Bank 0 IN data 0 Bank (usb) Bank 0 IN data 1 Bank 1 IN data 0 Bank 0 Bank 1 Virtual TXRDY Bank 0 Virtual TXRDY Bank 1 TXRDY (Virtual 0 & Virtual 1) Note: In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 863 34.6.10.7 Isochronous IN Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate. Isochronous transfer provides periodic, continuous communication between host and device. It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. If the endpoint is not available (TXRDY_TRER = 0), then the device does not answer to the host. An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled, then sent to the CPU. The STALL_SNT command bit is not used for an ISO-IN endpoint. 34.6.10.8 High Bandwidth Isochronous Endpoint Handling: IN Example For high bandwidth isochronous endpoints, the DMA can be programmed with the number of transactions (BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide the required number of packets per microframe, otherwise, the host will notice a sequencing problem. A response should be made to the first token IN recognized inside a microframe under the following conditions:  If at least one bank has been validated, the correct DATAx corresponding to the programmed Number Of Transactions per Microframe (NB_TRANS) should be answered. In case of a subsequent missed or corrupted token IN inside the microframe, the USB 2.0 Core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. If this flush occurs, an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx).  If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end.  If no data bank has been validated at the time when a response should be made for the second transaction of NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx).  If no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx).  If at the end of a microframe no valid token IN has been recognized, no data bank is flushed and no error condition is reported. At the end of a microframe in which at least one data bank has been transmitted, if less than NB_TRANS banks have been validated for that microframe, an error condition is flagged (ERR_TRANS is set in UDPHS_EPTSTAx). Cases of Error (in UDPHS_EPTSTAx)  ERR_FL_ISO: There was no data to transmit inside a microframe, so a ZLP is answered by default.  ERR_FLUSH: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of transactions actually validated (TXRDY_TRER) and likewise with the NB_TRANS programmed.  ERR_TRANS: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of programmed NB_TRANS transactions and the packets not requested were not validated.  ERR_FL_ISO + ERR_FLUSH: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN.  ERR_FL_ISO + ERR_TRANS: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN and the data can be discarded at the microframe end.  ERR_FLUSH + ERR_TRANS: The first token IN has been answered and it was the only one received, a second bank has been validated but not the third, whereas NB_TRANS was waiting for three transactions.  ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second Token IN was not available in time, but the second bank has been validated before the end of the microframe. The third bank has not been validated, but three transactions have been set in NB_TRANS. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 864 34.6.10.9 Data OUT 34.6.10.10 Bulk OUT or Interrupt OUT Like data IN, data OUT packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous OUT transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. 34.6.10.11 Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device) Algorithm Description for Each Packet:  The application enables an interrupt on RXRDY_TXKL.  When an interrupt on RXRDY_TXKL is received, the application knows that UDPHS_EPTSTAx register BYTE_COUNT bytes have been received.  The application reads the BYTE_COUNT bytes from the endpoint.  The application clears RXRDY_TXKL. Note: If the application does not know the size of the transfer, it may not be a good option to use AUTO_VALID. Because if a zero-length-packet is received, the RXRDY_TXKL is automatically cleared by the AUTO_VALID hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the UDPHS_EPTSTAx register. Algorithm to Fill Several Packets:  The application enables the interrupts of BUSY_BANK and AUTO_VALID.  When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available. If the application doesn’t know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL. 34.6.10.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device) To use the DMA setting, the AUTO_VALID field is mandatory. See 34.6.10.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) for more information. DMA Configuration Example: 1. First program UDPHS_DMAADDRESSx with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3. Program the DMA Channelx Control Register:  Size of buffer to be sent.  END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered packet data) at the end of DMA buffer.  END_BUFFIT: Generate an interrupt when BUFF_COUNT in the UDPHS_DMASTATUSx register reaches 0.  END_TR_EN: End of transfer enable, the UDPHS device can put an end to the current DMA transfer, in case of a short packet.  END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.)  CHANN_ENB: Run and stop at end of buffer. For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty). Notes: 1. When a zero-length-packet is received, RXRDY_TXKL bit in UDPHS_EPTSTAx is cleared automatically by AUTO_VALID, and the application knows of the end of buffer by the presence of the END_TR_IT. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 865 2. If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK. No data is written in the endpoint, the RXRDY_TXKL interrupt is generated, and the BYTE_COUNT field in UDPHS_EPTSTAx is null. Figure 34-14.Data OUT Transfer for Endpoint with One Bank Host Sends Data Payload USB Bus Packets Token OUT Data OUT 1 Microcontroller Transfers Data Host Sends the Next Data Payload ACK Token OUT Host Resends the Next Data Payload Data OUT 2 NAK Data OUT 2 Token OUT ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware FIFO (DPR) Content Data OUT 1 Written by UDPHS Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 1 Data OUT 2 Microcontroller Read Written by UDPHS Device Figure 34-15.Data OUT Transfer for an Endpoint with Two Banks Microcontroller reads Data 1 in bank 0, Host sends second data payload Host sends first data payload USB Bus Packets Virtual RXRDY Bank 0 Token OUT Data OUT 1 ACK Token OUT Data OUT 2 Virtual RXRDY Bank 1 ACK Token OUT Data OUT 3 Cleared by Firmware Interrupt pending Set by Hardware, Data payload written in FIFO endpoint bank 0 Microcontroller reads Data 2 in bank 1, Host sends third data payload Set by Hardware Data Payload written in FIFO endpoint bank 1 Cleared by Firmware Interrupt pending RXRDY = (virtual bank 0 | virtual bank 1) (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Data OUT 1 Write by UDPHS Device FIFO (DPR) Bank 1 Data OUT 1 Data OUT 3 Read by Microcontroller Write in progress Data OUT 2 Write by Hardware Data OUT 2 Read by Microcontroller SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 866 34.6.10.13 High Bandwidth Isochronous Endpoint OUT Figure 34-16.Bank Management, Example of Three Transactions per Microframe USB bus Transactions MDATA0 MDATA1 DATA2 t = 52.5 µs (40% of 125 µs) t=0 RXRDY Microcontroller FIFO (DPR) Access MDATA0 Read Bank 1 Read Bank 2 MDATA1 DATA2 USB line t = 125 µs RXRDY Read Bank 3 Read Bank 1 USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe. To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average). NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe. If NB_TRANS > 1 then it is High Bandwidth. Example:    If NB_TRANS = 3, the sequence should be either  MData0  MData0/Data1  MData0/Data1/Data2 If NB_TRANS = 2, the sequence should be either  MData0  MData0/Data1 If NB_TRANS = 1, the sequence should be  Data0 34.6.10.14 Isochronous Endpoint Handling: OUT Example The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three fields as follows:  TOGGLESQ_STA: PID of the data stored in the current bank  CURBK: Number of the bank currently being accessed by the microcontroller.  BUSY_BANK_STA: Number of busy bank This is particularly useful in case of a missing data packet. If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.) If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The ERR_CRC_NTR flag is set in UDPHS_EPTSTAx register. If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in UDPHS_EPTSTAx. If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 867 If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RXRDY_TXKL flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null. The FRCESTALL command bit is unused for an isochonous endpoint. Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and the BYTE_COUNT in UDPHS_EPTSTAx register is updated. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 868 34.6.10.15 STALL STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported.  OUT To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register.  IN Set the FRCESTALL bit in UDPHS_EPTSETSTAx register. Figure 34-17.Stall Handshake Data OUT Transfer USB Bus Packets Data OUT Token OUT Stall PID FRCESTALL Set by Firmware Cleared by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware Figure 34-18.Stall Handshake Data IN Transfer USB Bus Packets Token IN Stall PID FRCESTALL Cleared by Firmware Set by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 869 34.6.11 Speed Identification The high speed reset is managed by the hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated. Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device. 34.6.12 USB V2.0 High Speed Global Interrupt Interrupts are defined in Section 34.7.3 ”UDPHS Interrupt Enable Register” (UDPHS_IEN) and in Section 34.7.4 ”UDPHS Interrupt Status Register” (UDPHS_INTSTA). 34.6.13 Endpoint Interrupts Interrupts are enabled in UDPHS_IEN (see Section 34.7.3 ”UDPHS Interrupt Enable Register”) and individually masked in UDPHS_EPTCTLENBx (see Section 34.7.9 ”UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)”). Table 34-5. Endpoint Interrupt Source Masks SHRT_PCKT Short Packet Interrupt BUSY_BANK Busy Bank Interrupt NAK_OUT NAKOUT Interrupt NAK_IN/ERR_FLUSH NAKIN/Error Flush Interrupt STALL_SNT/ERR_CRC_NTR Stall Sent/CRC error/Number of Transaction Error Interrupt RX_SETUP/ERR_FL_ISO Received SETUP/Error Flow Interrupt TXRDY_TRER TX Packet Read/Transaction Error Interrupt TX_COMPLT Transmitted IN Data Complete Interrupt RXRDY_TXKL Received OUT Data Interrupt ERR_OVFLW Overflow Error Interrupt MDATA_RX MDATA Interrupt DATAX_RX DATAx Interrupt SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 870 Figure 34-19.UDPHS Interrupt Control Interface (UDPHS_IEN) Global IT mask Global IT sources DET_SUSPD MICRO_SOF USB Global IT Sources INT_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES (UDPHS_EPTCTLENBx) SHRT_PCKT EP mask BUSY_BANK EP sources NAK_OUT (UDPHS_IEN) EPT_0 husb2dev interrupt NAK_IN/ERR_FLUSH STALL_SNT/ER_CRC_NTR EPT0 IT Sources RX_SETUP/ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW MDATA_RX DATAX_RX (UDPHS_IEN) EPT_x EP mask EP sources (UDPHS_EPTCTLx) INTDIS_DMA EPT1-6 IT Sources disable DMA channelx request (UDPHS_DMACONTROLx) mask (UDPHS_IEN) DMA_x EN_BUFFIT mask DMA CH x END_TR_IT mask DESC_LD_IT SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 871 34.6.14 Power Modes 34.6.14.1 Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 34-20.UDPHS Device State Diagram Attached Hub Reset Hub or Configured Deconfigured Bus Inactive Powered Suspended Bus Activity Power Interruption Reset Bus Inactive Suspended Default Bus Activity Reset Address Assigned Bus Inactive Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Configured Suspended Bus Activity Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host. 34.6.14.2 Not Powered State Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 872 34.6.14.3 Entering Attached State When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 KΩ pull-downs integrated in the hub downstream ports. When a device is attached to an hub downstream port, the device connects a 1.5 KΩ pull-up on FSDP. The USB bus line goes into IDLE state, FSDP is pulled-up by the device 1.5 KΩ resistor to 3.3V and FSDM is pulled-down by the 15 KΩ resistor to GND of the host. After pull-up connection, the device enters the powered state. The transceiver remains disabled until bus activity is detected. In case of low power consumption need, the device can be stopped. When the device detects the VBUS, the software must enable the USB transceiver by enabling the EN_UDPHS bit in UDPHS_CTRL register. The software can detach the pull-up by setting DETACH bit in UDPHS_CTRL register. 34.6.14.4 From Powered State to Default State (Reset) After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked flag ENDRESET is set in the UDPHS_IEN register and an interrupt is triggered. Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state, the UDPHS software must:  Enable the default endpoint, setting the EPT_ENABL flag in the UDPHS_EPTCTLENB[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_0 of the UDPHS_IEN register. The enumeration then begins by a control transfer.  Configure the Interrupt Mask Register which has been reset by the USB reset detection  Enable the transceiver. In this state, the EN_UDPHS bit in UDPHS_CTRL register must be enabled. 34.6.14.5 From Default State to Address State (Address Assigned) After a Set Address standard device request, the USB host peripheral enters the address state. Warning: before the device enters address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDPHS device sets its new address once the TX_COMPLT flag in the UDPHS_EPTCTL[0] register has been received and cleared. To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN flag in the UDPHS_CTRL register. 34.6.14.6 From Address State to Configured State (Device Configured) Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the BK_NUMBER, EPT_TYPE, EPT_DIR and EPT_SIZE fields in the UDPHS_EPTCFGx registers and enabling them by setting the EPT_ENABL flag in the UDPHS_EPTCTLENBx registers, and, optionally, enabling corresponding interrupts in the UDPHS_IEN register. 34.6.14.7 Entering Suspend State (Bus Activity) When a Suspend (no bus activity on the USB bus) is detected, the DET_SUSPD signal in the UDPHS_STA register is set. This triggers an interrupt if the corresponding bit is set in the UDPHS_IEN register. This flag is cleared by writing to the UDPHS_CLRINT register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500 µA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected. 34.6.14.8 Receiving a Host Resume In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks disabled (however the pull-up should not be removed). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 873 Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. 34.6.14.9 Sending an External Resume In Suspend State it is possible to wake-up the host by sending an external resume. The device waits at least 5 ms after being entered in Suspend State before sending an external resume. The device must force a K state from 1 to 15 ms to resume the host. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 874 34.6.15 Test Mode A device must support the TEST_MODE feature when in the Default, Address or Configured High Speed device states. TEST_MODE can be:  Test_J  Test_K  Test_Packet  Test_SEO_NAK (See Section 34.7.7 “UDPHS Test Register” on page 886 for definitions of each test mode.) const char test_packet_buffer[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, JJJJJJJKKKKKKK * 8 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E 10}, JK }; // JKJKJKJK * 9 // JJKKJJKK * 8 // JJKKJJKK * 8 // // JJJJJJJK * 8 // {JKKKKKKK * SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 875 34.7 USB High Speed Device Port (UDPHS) User Interface Table 34-6. Register Mapping Offset Register Name Access Reset 0x00 UDPHS Control Register UDPHS_CTRL Read-write 0x0000_0200 0x04 UDPHS Frame Number Register UDPHS_FNUM Read-only 0x0000_0000 0x08 - 0x0C Reserved – – – 0x10 UDPHS Interrupt Enable Register UDPHS_IEN Read-write 0x0000_0010 0x14 UDPHS Interrupt Status Register UDPHS_INTSTA Read-only 0x0000_0000 0x18 UDPHS Clear Interrupt Register UDPHS_CLRINT Write-only – 0x1C UDPHS Endpoints Reset Register UDPHS_EPTRST Write-only – 0x20 - 0xCC Reserved – 0xE0 UDPHS Test Register UDPHS_TST 0xE4 - 0xE8 Reserved – 0x100 + endpoint * 0x20 + 0x00 UDPHS Endpoint Configuration Register UDPHS_EPTCFG 0x100 + endpoint * 0x20 + 0x04 UDPHS Endpoint Control Enable Register UDPHS_EPTCTLENB Write-only – 0x100 + endpoint * 0x20 + 0x08 UDPHS Endpoint Control Disable Register UDPHS_EPTCTLDIS Write-only – 0x100 + endpoint * 0x20 + 0x0C UDPHS Endpoint Control Register UDPHS_EPTCTL Read-only 0x0000_0000(1) 0x100 + endpoint * 0x20 + 0x10 Reserved (for endpoint) – – – 0x100 + endpoint * 0x20 + 0x14 UDPHS Endpoint Set Status Register UDPHS_EPTSETSTA Write-only – 0x100 + endpoint * 0x20 + 0x18 UDPHS Endpoint Clear Status Register UDPHS_EPTCLRSTA Write-only – 0x100 + endpoint * 0x20 + 0x1C UDPHS Endpoint Status Register UDPHS_EPTSTA Read-only 0x0000_0040 0x120 - 0x2FC UDPHS Endpoint1 to 15 (2) Registers 0x300 + channel * 0x10 + 0x00 UDPHS DMA Next Descriptor Address Register UDPHS_DMANXTDSC Read-write 0x0000_0000 0x300 + channel * 0x10 + 0x04 UDPHS DMA Channel Address Register UDPHS_DMAADDRESS Read-write 0x0000_0000 0x300 + channel * 0x10 + 0x08 UDPHS DMA Channel Control Register UDPHS_DMACONTROL Read-write 0x0000_0000 0x300 + channel * 0x10 + 0x0C UDPHS DMA Channel Status Register UDPHS_DMASTATUS Read-write 0x0000_0000 0x310 - 0x36C DMA Channel1 to 6 (3) – – Read-write 0x0000_0000 – – Read-write 0x0000_0000 Registers Notes: 1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001. 2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of registers is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120 and 0x2FC. 3. The DMA channel index refers to the corresponding EP number. When no DMA channel is assigned to one EP, the associated registers are reserved. This is the case for EP0, so DMA Channel 0 registers are reserved. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 876 34.7.1 UDPHS Control Register Name: UDPHS_CTRL Address: 0xF8030000 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 PULLD_DIS 10 REWAKEUP 9 DETACH 8 EN_UDPHS 7 FADDR_EN 6 5 4 3 DEV_ADDR 2 1 0 • DEV_ADDR: UDPHS Address This field contains the default address (0) after power-up or UDPHS bus reset (read), or it is written with the value set by a SET_ADDRESS request received by the device firmware (write). • FADDR_EN: Function Address Enable 0: Device is not in address state (read), or only the default function address is used (write). 1: Device is in address state (read), or this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received. • EN_UDPHS: UDPHS Enable 0: UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Switch the host to UTMI. 1: UDPHS is enabled (read), or this bit enables the UDPHS controller (write). Switch the host to UTMI. • DETACH: Detach Command 0: UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write). 1: UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the UDPHS line and forces the UTMI transceiver into suspend state (Suspend M = 0) (write). See PULLD_DIS description below. • REWAKEUP: Send Remote Wake Up 0: Remote Wake Up is disabled (read), or this bit has no effect (write). 1: Remote Wake Up is enabled (read), or this bit forces an external interrupt on the UDPHS controller for Remote Wake UP purposes. An Upstream Resume is sent only after the UDPHS bus has been in SUSPEND state for at least 5 ms. This bit is automatically cleared by hardware at the end of the Upstream Resume. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 877 • PULLD_DIS: Pull-Down Disable When set, there is no pull-down on DP & DM. (DM Pull-Down = DP Pull-Down = 0). Note: If the DETACH bit is also set, device DP & DM are left in high impedance state. (See DETACH description above.) DETACH PULLD_DIS DP DM Condition 0 0 Pull up Pull down Not recommended 0 1 Pull up High impedance state VBUS present 1 0 Pull down Pull down No VBUS 1 1 High impedance state High impedance state VBUS present & software disconnect SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 878 34.7.2 UDPHS Frame Number Register Name: UDPHS_FNUM Address: 0xF8030004 Access: Read-only 31 FNUM_ERR 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 FRAME_NUMBER 9 8 7 6 5 FRAME_NUMBER 4 3 1 MICRO_FRAME_NUM 0 2 • MICRO_FRAME_NUM: Microframe Number Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8). • FRAME_NUMBER: Frame Number as defined in the Packet Field Formats This field is provided in the last received SOF packet (see INT_SOF in the UDPHS Interrupt Status Register). • FNUM_ERR: Frame Number CRC Error This bit is set by hardware when a corrupted Frame Number in Start of Frame packet (or Micro SOF) is received. This bit and the INT_SOF (or MICRO_SOF) interrupt are updated at the same time. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 879 34.7.3 UDPHS Interrupt Enable Register Name: UDPHS_IEN Address: 0xF8030010 Access: Read-write 31 DMA_7 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 EPT_15 22 EPT_14 21 EPT_13 20 EPT_12 19 EPT_11 18 EPT_10 17 EPT_9 16 EPT_8 15 EPT_7 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Enable 0: Disable Suspend Interrupt. 1: Enable Suspend Interrupt. • MICRO_SOF: Micro-SOF Interrupt Enable 0: Disable Micro-SOF Interrupt. 1: Enable Micro-SOF Interrupt. • INT_SOF: SOF Interrupt Enable 0: Disable SOF Interrupt. 1: Enable SOF Interrupt. • ENDRESET: End Of Reset Interrupt Enable 0: Disable End Of Reset Interrupt. 1: Enable End Of Reset Interrupt. Automatically enabled after USB reset. • WAKE_UP: Wake Up CPU Interrupt Enable 0: Disable Wake Up CPU Interrupt. 1: Enable Wake Up CPU Interrupt. • ENDOFRSM: End Of Resume Interrupt Enable 0: Disable Resume Interrupt. 1: Enable Resume Interrupt. • UPSTR_RES: Upstream Resume Interrupt Enable 0: Disable Upstream Resume Interrupt. 1: Enable Upstream Resume Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 880 • EPT_x: Endpoint x Interrupt Enable 0: Disable the interrupts for this endpoint. 1: Enable the interrupts for this endpoint. • DMA_x: DMA Channel x Interrupt Enable 0: Disable the interrupts for this channel. 1: Enable the interrupts for this channel. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 881 34.7.4 UDPHS Interrupt Status Register Name: UDPHS_INTSTA Address: 0xF8030014 Access: Read-only 31 DMA_7 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 EPT_15 22 EPT_14 21 EPT_13 20 EPT_12 19 EPT_11 18 EPT_10 17 EPT_9 16 EPT_8 15 EPT_7 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 SPEED • SPEED: Speed Status 0: Reset by hardware when the hardware is in Full Speed mode. 1: Set by hardware when the hardware is in High Speed mode • DET_SUSPD: Suspend Interrupt 0: Cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register 1: Set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register. • MICRO_SOF: Micro Start Of Frame Interrupt 0: Cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register. 1: Set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn’t change. Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same time. • INT_SOF: Start Of Frame Interrupt 0: Cleared by setting the INT_SOF bit in UDPHS_CLRINT. 1: Set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated. • ENDRESET: End Of Reset Interrupt 0: Cleared by setting the ENDRESET bit in UDPHS_CLRINT. 1: Set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 882 • WAKE_UP: Wake Up CPU Interrupt 0: Cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1: Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation. Note: this interrupt is generated even if the device controller clock is disabled. • ENDOFRSM: End Of Resume Interrupt 0: Cleared by setting the ENDOFRSM bit in UDPHS_CLRINT. 1: Set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN. • UPSTR_RES: Upstream Resume Interrupt 0: Cleared by setting the UPSTR_RES bit in UDPHS_CLRINT. 1: Set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”. This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN. • EPT_x: Endpoint x Interrupt 0: Reset when the UDPHS_EPTSTAx interrupt source is cleared. 1: Set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. • DMA_x: DMA Channel x Interrupt 0: Reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1: Set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 883 34.7.5 UDPHS Clear Interrupt Register Name: UDPHS_CLRINT Address: 0xF8030018 Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – • DET_SUSPD: Suspend Interrupt Clear 0: No effect. 1: Clear the DET_SUSPD bit in UDPHS_INTSTA. • MICRO_SOF: Micro Start Of Frame Interrupt Clear 0: No effect. 1: Clear the MICRO_SOF bit in UDPHS_INTSTA. • INT_SOF: Start Of Frame Interrupt Clear 0: No effect. 1: Clear the INT_SOF bit in UDPHS_INTSTA. • ENDRESET: End Of Reset Interrupt Clear 0: No effect. 1: Clear the ENDRESET bit in UDPHS_INTSTA. • WAKE_UP: Wake Up CPU Interrupt Clear 0: No effect. 1: Clear the WAKE_UP bit in UDPHS_INTSTA. • ENDOFRSM: End Of Resume Interrupt Clear 0: No effect. 1: Clear the ENDOFRSM bit in UDPHS_INTSTA. • UPSTR_RES: Upstream Resume Interrupt Clear 0: No effect. 1: Clear the UPSTR_RES bit in UDPHS_INTSTA. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 884 34.7.6 UDPHS Endpoints Reset Register Name: UDPHS_EPTRST Address: 0xF803001C Access: Write only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EPT_15 14 EPT_14 13 EPT_13 12 EPT_12 11 EPT_11 10 EPT_10 9 EPT_9 8 EPT_8 7 EPT_7 6 EPT_6 5 EPT_5 4 EPT_4 3 EPT_3 2 EPT_2 1 EPT_1 0 EPT_0 • EPT_x: Endpoint x Reset 0: No effect. 1: Reset the Endpointx state. Setting this bit clears all bits in the Endpoint status UDPHS_EPTSTAx register except the TOGGLESQ_STA field. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 885 34.7.7 UDPHS Test Register Name: UDPHS_TST Address: 0xF80300E0 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 OPMODE2 4 TST_PKT 3 TST_K 2 TST_J 1 0 SPEED_CFG • SPEED_CFG: Speed Configuration Speed Configuration: Value 0 Name Description NORMAL Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode 1 Reserved 2 HIGH_SPEED Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. 3 FULL_SPEED Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. • TST_J: Test J Mode 0: No effect. 1: Set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line. • TST_K: Test K Mode 0: No effect. 1: Set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line. • TST_PKT: Test Packet Mode 0: No effect. 1: Set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye patterns, jitter, and any other dynamic waveform specifications. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 886 • OPMODE2: OpMode2 0: No effect. 1: Set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding. Note: For the Test mode, Test_SE0_NAK (see Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Support). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending NAK to the host. Upon command, a port’s transceiver must enter the High Speed receive mode and remain in that mode until the exit action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device response time. This enables testing of the device squelch level circuitry and, additionally, provides a general purpose stimulus/response test for basic functional testing. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 887 34.7.8 UDPHS Endpoint Configuration Register Name: UDPHS_EPTCFGx [x=0..15] Address: 0xF8030100 [0], 0xF8030120 [1], 0xF8030140 [2], 0xF8030160 [3], 0xF8030180 [4], 0xF80301A0 [5], 0xF80301C0 [6], 0xF80301E0 [7], 0xF8030200 [8], 0xF8030220 [9], 0xF8030240 [10], 0xF8030260 [11], 0xF8030280 [12], 0xF80302A0 [13], 0xF80302C0 [14], 0xF80302E0 [15] Access: Read-write 31 EPT_MAPD 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 6 5 4 3 EPT_DIR 2 1 EPT_SIZE 7 BK_NUMBER EPT_TYPE 8 NB_TRANS 0 • EPT_SIZE: Endpoint Size Set this field according to the endpoint size in bytes (see Section 34.6.6 ”Endpoint Configuration”). Endpoint Size (1) Value Note: Name Description 0 8 8 bytes 1 16 16 bytes 2 32 32 bytes 3 64 64 bytes 4 128 128 bytes 5 256 256 bytes 6 512 512 bytes 7 1024 1024 bytes 1. 1024 bytes is only for isochronous endpoint. • EPT_DIR: Endpoint Direction 0: Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1: Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. For Control endpoints this bit has no effect and should be left at zero. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 888 • EPT_TYPE: Endpoint Type Set this field according to the endpoint type (see Section 34.6.6 ”Endpoint Configuration”). (Endpoint 0 should always be configured as control) Endpoint Type Value Name Description 0 CTRL8 Control endpoint 1 ISO Isochronous endpoint 2 BULK Bulk endpoint 3 INT Interrupt endpoint • BK_NUMBER: Number of Banks Set this field according to the endpoint’s number of banks (see Section 34.6.6 ”Endpoint Configuration”). Number of Banks Value Name Description 0 0 Zero bank, the endpoint is not mapped in memory 1 1 One bank (bank 0) 2 2 Double bank (Ping-Pong: bank0/bank1) 3 3 Triple bank (bank0/bank1/bank2) • NB_TRANS: Number Of Transaction per Microframe The Number of transactions per microframe is set by software. Note: Meaningful for high bandwidth isochronous endpoint only. • EPT_MAPD: Endpoint Mapped 0: The user should reprogram the register with correct values. 1: Set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding: – The FIFO max capacity (FIFO_MAX_SIZE in UDPHS_IPFEATURES register) – The number of endpoints/banks already allocated – The number of allowed banks for this endpoint SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 889 34.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLENBx [x=0..15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 7 – 6 – 5 – 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)” on page 899. • EPT_ENABL: Endpoint Enable 0: No effect. 1: Enable endpoint according to the device configuration. • AUTO_VALID: Packet Auto-Valid Enable 0: No effect. 1: Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. • INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. • NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints) 0: No effect. 1: Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. • ERR_OVFLW: Overflow Error Interrupt Enable 0: No effect. 1: Enable Overflow Error Interrupt. • RXRDY_TXKL: Received OUT Data Interrupt Enable 0: No effect. 1: Enable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0: No effect. 1: Enable Transmitted IN Data Complete Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 890 • TXRDY: TX Packet Ready Interrupt Enable 0: No effect. 1: Enable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP: Received SETUP 0: No effect. 1: Enable RX_SETUP Interrupt. • STALL_SNT: Stall Sent Interrupt Enable 0: No effect. 1: Enable Stall Sent Interrupt. • NAK_IN: NAKIN Interrupt Enable 0: No effect. 1: Enable NAKIN Interrupt. • NAK_OUT: NAKOUT Interrupt Enable 0: No effect. 1: Enable NAKOUT Interrupt. • BUSY_BANK: Busy Bank Interrupt Enable 0: No effect. 1: Enable Busy Bank Interrupt. • SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable For OUT endpoints: 0: No effect. 1: Enable Short Packet Interrupt. For IN endpoints: Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 891 34.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) Name: UDPHS_EPTCTLENBx [x=0..15] (ISOENDPT) Address: 0xF8030104 [0], 0xF8030124 [1], 0xF8030144 [2], 0xF8030164 [3], 0xF8030184 [4], 0xF80301A4 [5], 0xF80301C4 [6], 0xF80301E4 [7], 0xF8030204 [8], 0xF8030224 [9], 0xF8030244 [10], 0xF8030264 [11], 0xF8030284 [12], 0xF80302A4 [13], 0xF80302C4 [14], 0xF80302E4 [15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 14 13 12 11 10 9 8 – ERR_FLUSH ERR_CRC_NT R ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW 7 MDATA_RX 6 DATAX_RX 5 – 4 – 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Control Register (Isochronous Endpoint)” on page 902. • EPT_ENABL: Endpoint Enable 0: No effect. 1: Enable endpoint according to the device configuration. • AUTO_VALID: Packet Auto-Valid Enable 0: No effect. 1: Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. • INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. • DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 0: No effect. 1: Enable DATAx Interrupt. • MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 0: No effect. 1: Enable MDATA Interrupt. • ERR_OVFLW: Overflow Error Interrupt Enable 0: No effect. 1: Enable Overflow Error Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 892 • RXRDY_TXKL: Received OUT Data Interrupt Enable 0: No effect. 1: Enable Received OUT Data Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 893 • TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0: No effect. 1: Enable Transmitted IN Data Complete Interrupt. • TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enable 0: No effect. 1: Enable TX Packet Ready/Transaction Error Interrupt. • ERR_FL_ISO: Error Flow Interrupt Enable 0: No effect. 1: Enable Error Flow ISO Interrupt. • ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enable 0: No effect. 1: Enable Error CRC ISO/Error Number of Transaction Interrupt. • ERR_FLUSH: Bank Flush Error Interrupt Enable 0: No effect. 1: Enable Bank Flush Error Interrupt. • BUSY_BANK: Busy Bank Interrupt Enable 0: No effect. 1: Enable Busy Bank Interrupt. • SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable For OUT endpoints: 0: No effect. 1: Enable Short Packet Interrupt. For IN endpoints: Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 894 34.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLDISx [x=0..15] Address: 0xF8030108 [0], 0xF8030128 [1], 0xF8030148 [2], 0xF8030168 [3], 0xF8030188 [4], 0xF80301A8 [5], 0xF80301C8 [6], 0xF80301E8 [7], 0xF8030208 [8], 0xF8030228 [9], 0xF8030248 [10], 0xF8030268 [11], 0xF8030288 [12], 0xF80302A8 [13], 0xF80302C8 [14], 0xF80302E8 [15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 7 – 6 – 5 – 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_DISABL This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)” on page 899. • EPT_DISABL: Endpoint Disable 0: No effect. 1: Disable endpoint. • AUTO_VALID: Packet Auto-Valid Disable 0: No effect. 1: Disable this bit to not automatically validate the current packet. • INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: Disable the “Interrupts Disable DMA”. • NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints) 0: No effect. 1: Let the hardware handle the handshake response for the High Speed Bulk OUT transfer. • ERR_OVFLW: Overflow Error Interrupt Disable 0: No effect. 1: Disable Overflow Error Interrupt. • RXRDY_TXKL: Received OUT Data Interrupt Disable 0: No effect. 1: Disable Received OUT Data Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 895 • TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0: No effect. 1: Disable Transmitted IN Data Complete Interrupt. • TXRDY: TX Packet Ready Interrupt Disable 0: No effect. 1: Disable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP: Received SETUP Interrupt Disable 0: No effect. 1: Disable RX_SETUP Interrupt. • STALL_SNT: Stall Sent Interrupt Disable 0: No effect. 1: Disable Stall Sent Interrupt. • NAK_IN: NAKIN Interrupt Disable 0: No effect. 1: Disable NAKIN Interrupt. • NAK_OUT: NAKOUT Interrupt Disable 0: No effect. 1: Disable NAKOUT Interrupt. • BUSY_BANK: Busy Bank Interrupt Disable 0: No effect. 1: Disable Busy Bank Interrupt. • SHRT_PCKT: Short Packet Interrupt Disable For OUT endpoints: 0: No effect. 1: Disable Short Packet Interrupt. For IN endpoints: Never automatically add a zero length packet at end of DMA transfer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 896 34.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) Name: UDPHS_EPTCTLDISx [x=0..15] (ISOENDPT) Address: 0xF8030108 [0], 0xF8030128 [1], 0xF8030148 [2], 0xF8030168 [3], 0xF8030188 [4], 0xF80301A8 [5], 0xF80301C8 [6], 0xF80301E8 [7], 0xF8030208 [8], 0xF8030228 [9], 0xF8030248 [10], 0xF8030268 [11], 0xF8030288 [12], 0xF80302A8 [13], 0xF80302C8 [14], 0xF80302E8 [15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 14 13 12 11 10 9 8 – ERR_FLUSH ERR_CRC_NT R ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW 7 MDATA_RX 6 DATAX_RX 5 – 4 – 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_DISABL This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Control Register (Isochronous Endpoint)” on page 902. • EPT_DISABL: Endpoint Disable 0: No effect. 1: Disable endpoint. • AUTO_VALID: Packet Auto-Valid Disable 0: No effect. 1: Disable this bit to not automatically validate the current packet. • INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: Disable the “Interrupts Disable DMA”. • DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 0: No effect. 1: Disable DATAx Interrupt. • MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 0: No effect. 1: Disable MDATA Interrupt. • ERR_OVFLW: Overflow Error Interrupt Disable 0: No effect. 1: Disable Overflow Error Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 897 • RXRDY_TXKL: Received OUT Data Interrupt Disable 0: No effect. 1: Disable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0: No effect. 1: Disable Transmitted IN Data Complete Interrupt. • TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Disable 0: No effect. 1: Disable TX Packet Ready/Transaction Error Interrupt. • ERR_FL_ISO: Error Flow Interrupt Disable 0: No effect. 1: Disable Error Flow ISO Interrupt. • ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Disable 0: No effect. 1: Disable Error CRC ISO/Error Number of Transaction Interrupt. • ERR_FLUSH: bank flush error Interrupt Disable 0: No effect. 1: Disable Bank Flush Error Interrupt. • BUSY_BANK: Busy Bank Interrupt Disable 0: No effect. 1: Disable Busy Bank Interrupt. • SHRT_PCKT: Short Packet Interrupt Disable For OUT endpoints: 0: No effect. 1: Disable Short Packet Interrupt. For IN endpoints: Never automatically add a zero length packet at end of DMA transfer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 898 34.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLx [x=0..15] Access: Read-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 7 – 6 – 5 – 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register” on page 888. • EPT_ENABL: Endpoint Enable 0: If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1: If set, the endpoint is enabled according to the device configuration. • AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints) Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints. For IN Transfer: If this bit is set, then the UDPHS_EPTSTAx register TXRDY bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. The user may still set the UDPHS_EPTSTAx register TXRDY bit if the current bank is not full, unless the user wants to send a Zero Length Packet by software. For OUT Transfer: If this bit is set, then the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached. The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s). • INTDIS_DMA: Interrupt Disables DMA If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed. If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested). If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT...), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 899 This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet. • NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints) 0: If cleared, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1: If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. Note: According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During PING Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence. • ERR_OVFLW: Overflow Error Interrupt Enabled 0: Overflow Error Interrupt is masked. 1: Overflow Error Interrupt is enabled. • RXRDY_TXKL: Received OUT Data Interrupt Enabled 0: Received OUT Data Interrupt is masked. 1: Received OUT Data Interrupt is enabled. • TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled 0: Transmitted IN Data Complete Interrupt is masked. 1: Transmitted IN Data Complete Interrupt is enabled. • TXRDY: TX Packet Ready Interrupt Enabled 0: TX Packet Ready Interrupt is masked. 1: TX Packet Ready Interrupt is enabled. Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY flag remains low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TXRDY for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY hardware clear. • RX_SETUP: Received SETUP Interrupt Enabled 0: Received SETUP is masked. 1: Received SETUP is enabled. • STALL_SNT: Stall Sent Interrupt Enabled 0: Stall Sent Interrupt is masked. 1: Stall Sent Interrupt is enabled. • NAK_IN: NAKIN Interrupt Enabled 0: NAKIN Interrupt is masked. 1: NAKIN Interrupt is enabled. • NAK_OUT: NAKOUT Interrupt Enabled 0: NAKOUT Interrupt is masked. 1: NAKOUT Interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 900 • BUSY_BANK: Busy Bank Interrupt Enabled 0: BUSY_BANK Interrupt is masked. 1: BUSY_BANK Interrupt is enabled. For OUT endpoints: an interrupt is sent when all banks are busy. For IN endpoints: an interrupt is sent when all banks are free. • SHRT_PCKT: Short Packet Interrupt Enabled For OUT endpoints: send an Interrupt when a Short Packet has been received. 0: Short Packet Interrupt is masked. 1: Short Packet Interrupt is enabled. For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or INTERRUPT end of transfer, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 901 34.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) Name: UDPHS_EPTCTLx [x=0..15] (ISOENDPT) Address: 0xF803010C [0], 0xF803012C [1], 0xF803014C [2], 0xF803016C [3], 0xF803018C [4], 0xF80301AC [5], 0xF80301CC [6], 0xF80301EC [7], 0xF803020C [8], 0xF803022C [9], 0xF803024C [10], 0xF803026C [11], 0xF803028C [12], 0xF80302AC [13], 0xF80302CC [14], 0xF80302EC [15] Access: Read-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 14 13 12 11 10 9 8 – ERR_FLUSH ERR_CRC_NT R ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW 7 MDATA_RX 6 DATAX_RX 5 – 4 – 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register” on page 888. • EPT_ENABL: Endpoint Enable 0: If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1: If set, the endpoint is enabled according to the device configuration. • AUTO_VALID: Packet Auto-Valid Enabled Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints. For IN Transfer: If this bit is set, then the UDPHS_EPTSTAx register TXRDY_TRER bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. The user may still set the UDPHS_EPTSTAx register TXRDY_TRER bit if the current bank is not full, unless the user wants to send a Zero Length Packet by software. For OUT Transfer: If this bit is set, then the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached. The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 902 • INTDIS_DMA: Interrupt Disables DMA If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed. If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested). If the exception raised is not associated to a new system bank packet (ex: ERR_FL_ISO), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate. • DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 0: No effect. 1: Send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. • MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 0: No effect. 1: Send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data payload has been received. • ERR_OVFLW: Overflow Error Interrupt Enabled 0: Overflow Error Interrupt is masked. 1: Overflow Error Interrupt is enabled. • RXRDY_TXKL: Received OUT Data Interrupt Enabled 0: Received OUT Data Interrupt is masked. 1: Received OUT Data Interrupt is enabled. • TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled 0: Transmitted IN Data Complete Interrupt is masked. 1: Transmitted IN Data Complete Interrupt is enabled. • TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enabled 0: TX Packet Ready/Transaction Error Interrupt is masked. 1: TX Packet Ready/Transaction Error Interrupt is enabled. Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY_TRER flag remains low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TXRDY_TRER for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY_TRER hardware clear. • ERR_FL_ISO: Error Flow Interrupt Enabled 0: Error Flow Interrupt is masked. 1: Error Flow Interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 903 • ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enabled 0: ISO CRC error/number of Transaction Error Interrupt is masked. 1: ISO CRC error/number of Transaction Error Interrupt is enabled. • ERR_FLUSH: Bank Flush Error Interrupt Enabled 0: Bank Flush Error Interrupt is masked. 1: Bank Flush Error Interrupt is enabled. • BUSY_BANK: Busy Bank Interrupt Enabled 0: BUSY_BANK Interrupt is masked. 1: BUSY_BANK Interrupt is enabled. For OUT endpoints: An interrupt is sent when all banks are busy. For IN endpoints: An interrupt is sent when all banks are free. • SHRT_PCKT: Short Packet Interrupt Enabled For OUT endpoints: send an Interrupt when a Short Packet has been received. 0: Short Packet Interrupt is masked. 1: Short Packet Interrupt is enabled. For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling an end of isochronous (micro-)frame data, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 904 34.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSETSTAx [x=0..15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 TXRDY 10 – 9 RXRDY_TXKL 8 – 7 – 6 – 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)” on page 911. • FRCESTALL: Stall Handshake Request Set 0: No effect. 1: Set this bit to request a STALL answer to the host for the next handshake Refer to chapters 8.4.5 (Handshake Packets) and 9.4.5 (Get Status) of the Universal Serial Bus Specification, Rev 2.0 for more information on the STALL handshake. • RXRDY_TXKL: KILL Bank Set (for IN Endpoint) 0: No effect. 1: Kill the last written bank. • TXRDY: TX Packet Ready Set 0: No effect. 1: Set this bit after a packet has been written into the endpoint FIFO for IN data transfers – This flag is used to generate a Data IN transaction (device to host). – Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY is cleared. – Transfer to the FIFO is done by writing in the “Buffer Address” register. – Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting TXRDY to one. – UDPHS bus transactions can start. – TXCOMP is set once the data payload has been received by the host. – Data should be written into the endpoint FIFO only after this bit has been cleared. – Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 905 34.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) Name: UDPHS_EPTSETSTAx [x=0..15] (ISOENDPT) Address: 0xF8030114 [0], 0xF8030134 [1], 0xF8030154 [2], 0xF8030174 [3], 0xF8030194 [4], 0xF80301B4 [5], 0xF80301D4 [6], 0xF80301F4 [7], 0xF8030214 [8], 0xF8030234 [9], 0xF8030254 [10], 0xF8030274 [11], 0xF8030294 [12], 0xF80302B4 [13], 0xF80302D4 [14], 0xF80302F4 [15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 TXRDY_TRER 10 – 9 RXRDY_TXKL 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Status Register (Isochronous Endpoint)” on page 914. • RXRDY_TXKL: KILL Bank Set (for IN Endpoint) 0: No effect. 1: Kill the last written bank. • TXRDY_TRER: TX Packet Ready Set 0: No effect. 1: Set this bit after a packet has been written into the endpoint FIFO for IN data transfers – This flag is used to generate a Data IN transaction (device to host). – Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY_TRER is cleared. – Transfer to the FIFO is done by writing in the “Buffer Address” register. – Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting TXRDY_TRER to one. – UDPHS bus transactions can start. – TXCOMP is set once the data payload has been sent. – Data should be written into the endpoint FIFO only after this bit has been cleared. – Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 906 34.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCLRSTAx [x=0..15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 – 10 TX_COMPLT 9 RXRDY_TXKL 8 – 7 – 6 TOGGLESQ 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)” on page 911. • FRCESTALL: Stall Handshake Request Clear 0: No effect. 1: Clear the STALL request. The next packets from host will not be STALLed. • TOGGLESQ: Data Toggle Clear 0: No effect. 1: Clear the PID data of the current bank For OUT endpoints, the next received packet should be a DATA0. For IN endpoints, the next packet will be sent with a DATA0 PID. • RXRDY_TXKL: Received OUT Data Clear 0: No effect. 1: Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx. • TX_COMPLT: Transmitted IN Data Complete Clear 0: No effect. 1: Clear the TX_COMPLT flag of UDPHS_EPTSTAx. • RX_SETUP: Received SETUP Clear 0: No effect. 1: Clear the RX_SETUP flags of UDPHS_EPTSTAx. • STALL_SNT: Stall Sent Clear 0: No effect. 1: Clear the STALL_SNT flags of UDPHS_EPTSTAx. • NAK_IN: NAKIN Clear 0: No effect. 1: Clear the NAK_IN flags of UDPHS_EPTSTAx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 907 • NAK_OUT: NAKOUT Clear 0: No effect. 1: Clear the NAK_OUT flag of UDPHS_EPTSTAx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 908 34.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) Name: UDPHS_EPTCLRSTAx [x=0..15] (ISOENDPT) Address: 0xF8030118 [0], 0xF8030138 [1], 0xF8030158 [2], 0xF8030178 [3], 0xF8030198 [4], 0xF80301B8 [5], 0xF80301D8 [6], 0xF80301F8 [7], 0xF8030218 [8], 0xF8030238 [9], 0xF8030258 [10], 0xF8030278 [11], 0xF8030298 [12], 0xF80302B8 [13], 0xF80302D8 [14], 0xF80302F8 [15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 – ERR_FLUSH ERR_CRC_NT R ERR_FL_ISO – TX_COMPLT RXRDY_TXKL – 7 – 6 TOGGLESQ 5 – 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register” on page 888. For additional information, see “UDPHS Endpoint Status Register (Isochronous Endpoint)” on page 914. • TOGGLESQ: Data Toggle Clear 0: No effect. 1: Clear the PID data of the current bank For OUT endpoints, the next received packet should be a DATA0. For IN endpoints, the next packet will be sent with a DATA0 PID. • RXRDY_TXKL: Received OUT Data Clear 0: No effect. 1: Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx. • TX_COMPLT: Transmitted IN Data Complete Clear 0: No effect. 1: Clear the TX_COMPLT flag of UDPHS_EPTSTAx. • ERR_FL_ISO: Error Flow Clear 0: No effect. 1: Clear the ERR_FL_ISO flags of UDPHS_EPTSTAx. • ERR_CRC_NTR: Number of Transaction Error Clear 0: No effect. 1: Clear the ERR_CRC_NTR flags of UDPHS_EPTSTAx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 909 • ERR_FLUSH: Bank Flush Error Clear 0: No effect. 1: Clear the ERR_FLUSH flags of UDPHS_EPTSTAx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 910 34.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSTAx [x=0..15] Access: Read-only 31 SHRT_PCKT 30 23 15 NAK_OUT 29 28 22 21 BYTE_COUNT 20 14 NAK_IN 7 6 TOGGLESQ_STA 27 BYTE_COUNT 26 19 18 BUSY_BANK_STA 25 24 17 16 CURBK_CTLDIR 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register” on page 888. • FRCESTALL: Stall Handshake Request 0: No effect. 1: If set a STALL answer will be done to the host for the next handshake. This bit is reset by hardware upon received SETUP. • TOGGLESQ_STA: Toggle Sequencing Toggle Sequencing: – IN endpoint: It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank. – CONTROL and OUT endpoint: These bits are set by hardware to indicate the PID data of the current bank: Value Name Description 0 DATA0 DATA0 1 DATA1 DATA1 2 DATA2 Reserved for High Bandwidth Isochronous Endpoint 3 MDATA Reserved for High Bandwidth Isochronous Endpoint Notes: 1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1). 2. These bits are updated for OUT transfer: - A new data has been written into the current bank. - The user has just cleared the Received OUT Data bit to switch to the next bank. 3. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint). • ERR_OVFLW: Overflow Error This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 911 • RXRDY_TXKL: Received OUT Data/KILL Bank – Received OUT Data (for OUT endpoint or Control endpoint): This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – KILL Bank (for IN endpoint): – The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented. – The bank is not cleared but sent on the IN transfer, TX_COMPLT – The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet. Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed. • TX_COMPLT: Transmitted IN Data Complete This bit is set by hardware after an IN packet has been accepted (ACK’ed) by the host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). • TXRDY: TX Packet Ready This bit is cleared by hardware after the host has acknowledged the packet. For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit. Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). • RX_SETUP: Received SETUP – (for Control endpoint only) This bit is set by hardware when a valid SETUP packet has been received from the host. It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). • STALL_SNT: Stall Sent – (for Control, Bulk and Interrupt endpoints) This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register FRCESTALL bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • NAK_IN: NAK IN This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host. This bit is cleared by software. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 912 • NAK_OUT: NAK OUT This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). • CURBK_CTLDIR: Current Bank/Control Direction – Current Bank (not relevant for Control endpoint): These bits are set by hardware to indicate the number of the current bank. Value Name Description 0 BANK0 Bank 0 (or single bank) 1 BANK1 Bank 1 2 BANK2 Bank 2 Note: The current bank is updated each time the user: - Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank. - Clears the received OUT data bit to access the next bank. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – Control Direction (for Control endpoint only): 0: A Control Write is requested by the Host. 1: A Control Read is requested by the Host. Notes: 1. This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data). 2. This bit is updated after receiving new setup data. • BUSY_BANK_STA: Busy Bank Number These bits are set by hardware to indicate the number of busy banks. IN endpoint: It indicates the number of busy banks filled by the user, ready for IN transfer. OUT endpoint: It indicates the number of busy banks filled by OUT transaction from the Host. Value Name Description 0 1BUSYBANK 1 busy bank 1 2BUSYBANKS 2 busy banks 2 3BUSYBANKS 3 busy banks • BYTE_COUNT: UDPHS Byte Count Byte count of a received data packet. This field is incremented after each write into the endpoint (to prepare an IN transfer). This field is decremented after each reading into the endpoint (OUT transfer). This field is also updated at RXRDY_TXKL flag clear with the next bank. This field is also updated at TXRDY flag set with the next bank. This field is reset by EPT_x of UDPHS_EPTRST register. • SHRT_PCKT: Short Packet An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 913 34.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) Name: UDPHS_EPTSTAx [x=0..15] (ISOENDPT) Address: 0xF803011C [0], 0xF803013C [1], 0xF803015C [2], 0xF803017C [3], 0xF803019C [4], 0xF80301BC [5], 0xF80301DC [6], 0xF80301FC [7], 0xF803021C [8], 0xF803023C [9], 0xF803025C [10], 0xF803027C [11], 0xF803029C [12], 0xF80302BC [13], 0xF80302DC [14], 0xF80302FC [15] Access: Read-only 31 SHRT_PCKT 30 29 28 22 21 BYTE_COUNT 20 15 14 13 – ERR_FLUSH 23 26 25 19 18 BUSY_BANK_STA 17 12 11 10 9 8 ERR_CRC_NT R ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW 5 – 4 – 3 – 2 – 1 – 0 – 7 6 TOGGLESQ_STA 27 BYTE_COUNT 24 16 CURBK This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register” on page 888. • TOGGLESQ_STA: Toggle Sequencing Toggle Sequencing: – IN endpoint: It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank. – OUT endpoint: These bits are set by hardware to indicate the PID data of the current bank: Value Name Description 0 DATA0 DATA0 1 DATA1 DATA1 2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 3 MDATA MData (only for High Bandwidth Isochronous Endpoint) Notes: 1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1). 2. These bits are updated for OUT transfer: - A new data has been written into the current bank. - The user has just cleared the Received OUT Data bit to switch to the next bank. 3. For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/TXRDY_TRER bit to know if the toggle sequencing is correct or not. 4. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 914 • ERR_OVFLW: Overflow Error This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • RXRDY_TXKL: Received OUT Data/KILL Bank – Received OUT Data (for OUT endpoint or Control endpoint): This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – KILL Bank (for IN endpoint): – The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented. – The bank is not cleared but sent on the IN transfer, TX_COMPLT – The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet. Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed. • TX_COMPLT: Transmitted IN Data Complete This bit is set by hardware after an IN packet has been sent. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). • TXRDY_TRER: TX Packet Ready/Transaction Error – TX Packet Ready: This bit is cleared by hardware, as soon as the packet has been sent. For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit. Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY_TRER bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). – Transaction Error (for high bandwidth isochronous OUT endpoints) (Read-Only): This bit is set by hardware when a transaction error occurs inside one microframe. If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still set as long as the current bank contains one “bad” n-transaction. (see “CURBK: Current Bank” on page 916) As soon as the current bank is relative to a new “good” n-transactions, then this bit is reset. Notes: 1. A transaction error occurs when the toggle sequencing does not respect the Universal Serial Bus Specification, Rev 2.0 (5.9.2 High Bandwidth Isochronous endpoints) (Bad PID, missing data....) 2. When a transaction error occurs, the user may empty all the “bad” transactions by clearing the Received OUT Data flag (RXRDY_TXKL). If this bit is reset, then the user should consider that a new n-transaction is coming. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 915 This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). • ERR_FL_ISO: Error Flow This bit is set by hardware when a transaction error occurs. – Isochronous IN transaction is missed, the micro has no time to fill the endpoint (underflow). – Isochronous OUT data is dropped because the bank is busy (overflow). This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • ERR_CRC_NTR: CRC ISO Error/Number of Transaction Error – CRC ISO Error (for Isochronous OUT endpoints) (Read-only): This bit is set by hardware if the last received data is corrupted (CRC error on data). This bit is updated by hardware when new data is received (Received OUT Data bit). – Number of Transaction Error (for High Bandwidth Isochronous IN endpoints): This bit is set at the end of a microframe in which at least one data bank has been transmitted, if less than the number of transactions per micro-frame banks (UDPHS_EPTCFGx register NB_TRANS) have been validated for transmission inside this microframe. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • ERR_FLUSH: Bank Flush Error – (for High Bandwidth Isochronous IN endpoints) This bit is set when flushing unsent banks at the end of a microframe. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). • CURBK: Current Bank – Current Bank: These bits are set by hardware to indicate the number of the current bank. Value Name Description 0 BANK0 Bank 0 (or single bank) 1 BANK1 Bank 1 2 BANK2 Bank 2 Note: The current bank is updated each time the user: - Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank. - Clears the received OUT data bit to access the next bank. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • BUSY_BANK_STA: Busy Bank Number These bits are set by hardware to indicate the number of busy banks. IN endpoint: It indicates the number of busy banks filled by the user, ready for IN transfer. OUT endpoint: It indicates the number of busy banks filled by OUT transaction from the Host. Value Name Description 0 1BUSYBANK 1 busy bank 1 2BUSYBANKS 2 busy banks 2 3BUSYBANKS 3 busy banks SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 916 • BYTE_COUNT: UDPHS Byte Count Byte count of a received data packet. This field is incremented after each write into the endpoint (to prepare an IN transfer). This field is decremented after each reading into the endpoint (OUT transfer). This field is also updated at RXRDY_TXKL flag clear with the next bank. This field is also updated at TXRDY_TRER flag set with the next bank. This field is reset by EPT_x of UDPHS_EPTRST register. • SHRT_PCKT: Short Packet An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 917 34.7.21 UDPHS DMA Channel Transfer Descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer. The structure of the DMA channel transfer descriptor is defined by three parameters as described below: Offset 0: The address must be aligned: 0xXXXX0 Next Descriptor Address Register: UDPHS_DMANXTDSCx Offset 4: The address must be aligned: 0xXXXX4 DMA Channelx Address Register: UDPHS_DMAADDRESSx Offset 8: The address must be aligned: 0xXXXX8 DMA Channelx Control Register: UDPHS_DMACONTROLx To use the DMA channel transfer descriptor, fill the structures with the correct value (as described in the following pages). Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first. Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer descriptor). The descriptor is automatically loaded upon Endpointx request for packet transfer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 918 34.7.22 UDPHS DMA Next Descriptor Address Register Name: UDPHS_DMANXTDSCx [x = 0..6] Address: [6] 0xF8030300 [0], 0xF8030310 [1], 0xF8030320 [2], 0xF8030330 [3], 0xF8030340 [4], 0xF8030350 [5], 0xF8030360 Access: Read-write 31 30 29 28 27 NXT_DSC_ADD 26 25 24 23 22 21 20 19 NXT_DSC_ADD 18 17 16 15 14 13 12 11 NXT_DSC_ADD 10 9 8 7 6 5 4 3 NXT_DSC_ADD 2 1 0 Note: Channel 0 is not used. • NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the address must be equal to zero. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 919 34.7.23 UDPHS DMA Channel Address Register Name: UDPHS_DMAADDRESSx [x = 0..6] Address: [6] 0xF8030304 [0], 0xF8030314 [1], 0xF8030324 [2], 0xF8030334 [3], 0xF8030344 [4], 0xF8030354 [5], 0xF8030364 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD 23 22 21 20 BUFF_ADD 15 14 13 12 BUFF_ADD 7 6 5 4 BUFF_ADD Note: Channel 0 is not used. • BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer. Channel start and end addresses may be aligned on any byte boundary. The firmware may write this field only when the UDPHS_DMASTATUS register CHANN_ENB bit is clear. This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary. The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer. The packet end address is either the channel end address or the latest channel address accessed in the channel buffer. The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either determined by the end of buffer or the UDPHS device, USB end of transfer if the UDPHS_DMACONTROLx register END_TR_EN bit is set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 920 34.7.24 UDPHS DMA Channel Control Register Name: UDPHS_DMACONTROLx [x = 0..6] Address: [6] 0xF8030308 [0], 0xF8030318 [1], 0xF8030328 [2], 0xF8030338 [3], 0xF8030348 [4], 0xF8030358 [5], 0xF8030368 Access: Read-write 31 30 29 28 27 BUFF_LENGTH 26 25 24 23 22 21 20 19 BUFF_LENGTH 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 BURST_LCK 6 DESC_LD_IT 5 END_BUFFIT 4 END_TR_IT 3 END_B_EN 2 END_TR_EN 1 LDNXT_DSC 0 CHANN_ENB Note: Channel 0 is not used. • CHANN_ENB: (Channel Enable Command) 0: DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by hardware when the channel source bus is disabled at end of buffer. If the UDPHS_DMACONTROL register LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to set the corresponding CHANN_ENB bit to start the described transfer, if needed. If the UDPHS_DMACONTROL register LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both UDPHS_DMASTATUS register CHANN_ENB and CHANN_ACT flags read as 0. If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the UDPHS_DMASTATUS register CHANN_ENB bit is cleared. If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 1: UDPHS_DMASTATUS register CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pending request will start the transfer. This may be used to start or resume any requested transfer. • LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command) 0: No channel register is loaded after the end of the channel transfer. 1: The channel controller loads the next descriptor after the end of the current transfer, i.e., when the UDPHS_DMASTATUS/CHANN_ENB bit is reset. If the UDPHS_DMA CONTROL/CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request. DMA Channel Control Command Summary LDNXT_DSC CHANN_ENB Description 0 0 Stop now 0 1 Run and stop at end of buffer 1 0 Load next descriptor now 1 1 Run and link at end of buffer SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 921 • END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0: USB end of transfer is ignored. 1: UDPHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised. This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure. • END_B_EN: End of Buffer Enable (Control) 0: DMA Buffer End has no impact on USB packet transfer. 1: Endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e., when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. This is mainly for short packet IN validation initiated by the DMA reaching end of buffer, but could be used for OUT packet truncation (discarding of unwanted packet data) at the end of DMA buffer. • END_TR_IT: End of Transfer Interrupt Enable 0: UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1: An interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. Use when the receive size is unknown. • END_BUFFIT: End of Buffer Interrupt Enable 0: UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1: An interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. • DESC_LD_IT: Descriptor Loaded Interrupt Enable 0: UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1: An interrupt is generated when a descriptor has been loaded from the bus. • BURST_LCK: Burst Lock Enable 0: The DMA never locks bus access. 1: USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. • BUFF_LENGTH: Buffer Byte Length (Write-only) This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (64 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under UDPHS device control. When this field is written, The UDPHS_DMASTATUSx register BUFF_COUNT field is updated with the write value. Notes: 1. Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”. 2. For reliability it is highly recommended to wait for both UDPHS_DMASTATUSx register CHAN_ACT and CHAN_ENB flags are at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 922 34.7.25 UDPHS DMA Channel Status Register Name: UDPHS_DMASTATUSx [x = 0..6] Address: 0xF803030C [0], 0xF803031C [1], 0xF803032C [2], 0xF803033C [3], 0xF803034C [4], 0xF803035C [5], 0xF803036C [6] Access: Read-write 31 30 29 28 27 BUFF_COUNT 26 25 24 23 22 21 20 19 BUFF_COUNT 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 DESC_LDST 5 END_BF_ST 4 END_TR_ST 3 – 2 – 1 CHANN_ACT 0 CHANN_ENB Note: Channel 0 is not used. • CHANN_ENB: Channel Enable Status 0: If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is automatically reset. 1: If set, the DMA channel is currently enabled and transfers data upon request. This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx register CHANN_ENB bit either by software or descriptor loading. If a channel request is currently serviced when the UDPHS_DMACONTROLx register CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared. • CHANN_ACT: Channel Active Status 0: The DMA channel is no longer trying to source the packet data. When a packet transfer is ended this bit is automatically reset. 1: The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor. • END_TR_ST: End of Channel Transfer Status 0: Cleared automatically when read by software. 1: Set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • END_BF_ST: End of Channel Buffer Status 0: Cleared automatically when read by software. 1: Set by hardware when the BUFF_COUNT downcount reach zero. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 923 • DESC_LDST: Descriptor Loaded Status 0: Cleared automatically when read by software. 1: Set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase. The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word boundary. At the end of buffer, the DMA accesses the UDPHS device only for the number of bytes needed to complete it. This field value is reliable (stable) only if the channel has been stopped or frozen (UDPHS_EPTCTLx register NT_DIS_DMA bit is used to disable the channel request) and the channel is no longer active CHANN_ACT flag is 0. Note: For OUT endpoints, if the receive buffer byte length (BUFF_LENGTH) has been defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received will be 0x10000-BUFF_COUNT. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 924 35. USB Host High Speed Port (UHPHS) 35.1 Description The USB Host High Speed Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface). 35.2 Embedded Characteristics   Compliant with Enhanced HCI Rev 1.0 Specification  Compliant with USB V2.0 High-speed  Supports High-speed 480 Mbps Compliant with OpenHCI Rev 1.0 Specification  Compliant with USB V2.0 Full-speed and Low-speed Specification  Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices  Root Hub Integrated with 3 Downstream USB HS Ports  Embedded USB Transceivers  Supports Power Management  3 Hosts (A and B) High Speed (EHCI), Port A shared with UDPHS SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 925 35.3 Block Diagram Figure 35-1. Block Diagram HCI Slave Block AHB Slave OHCI Registers Root Hub Registers List Processor Block Control ED & TD Registers PORT S/M 1 Root Hub and Host SIE Master AHB HCI Master Block Data PORT S/M 0 HCI Slave Block Slave EHCI Registers USB High-speed Transceiver HFSDPC HFSDMC HHSDPC HHSDMC USB High-speed Transceiver HFSDPB HFSDMB HHSDPB HHSDMB USB High-speed Transceiver HFSDPA HFSDMA HHSDPA HHSDMA FIFO 64 x 8 SOF generator AHB Embedded USB v2.0 Transceiver Packet Buffer FIFO Control List Processor Master AHB HCI Master Block Data Access to the USB host operational registers is achieved through the AHB bus slave interface. The Open HCI host controller and Enhanced HCI host controller initialize master DMA transfers through the AHB bus master interface as follows:  Fetches endpoint descriptors and transfer descriptors  Access to endpoint data from system memory  Access to the HC communication area  Write status and retire transfer descriptor Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not dedicate pads to external over current protection. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 926 35.4 Typical Connection Figure 35-2. Board Schematic to Interface UHP High-speed Host Controller PIO (VBUS ENABLE +5V "A" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND HHSDM/HFSDM 3 4 Shell = Shield 1 2 HHSDP/HFSDP 5K62 ± 1% Ω VBG 10 pF GNDUTMI 35.5 Product Dependencies 35.5.1 I/O Lines HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical transceivers are controlled by the USB host controller. One transceiver is shared with the USB High Speed Device (port A). The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL register. In the case the port A is driven by the USB High Speed Device, the output signals are DFSDP, DFSDM, DHSDP and DHSDM. The transceiver is automatically selected for Device operation once the USB High Speed Device is enabled. In the case the port A is driven by the USB High Speed Host, the output signals are HFSDPA, HFSDMA, HHSDPA and HHSDMA. 35.5.2 Power Management The system embeds 3 transceivers. The USB Host High Speed requires a 480 MHz clock for the embedded High-speed transceivers. This clock (UPLLCK) is provided by the UTMI PLL. In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not possible. Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as the input clock of OHCI. The High-speed transceiver returns a 30 MHz clock to the USB Host controller. The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations. These clocks must be generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV field. Thus the USB Host peripheral receives three clocks from the Power Management Controller (PMC): the Peripheral Clock (MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to interface with the bus USB signals (Recovered 12 MHz domain) in Full-speed operations. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 927 For High-speed operations, the user has to perform the following:  Enable UHP peripheral clock, bit (1 TXD SPI Slave -> RXD MISO SPI Master ->RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1397 Figure 44-38.SPI Transfer Format (CPHA = 0, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 5 8 7 6 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 44.7.7.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 1375. 44.7.7.5 Character Transmission The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for transmitting a character can be added when the USART is configured in SPI master mode. In the USART_MR, the value configured on INACK field can prevent any character transmission (even if US_THR has been written) while the receiver side is not ready (character not read). When WRDBT equals 0, the character is transmitted whatever the receiver status. If WRDBT is set to 1, the transmitter waits for the receiver holding register to be read before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side. The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave Mode and if a character must be sent while the US_THR is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing a one to the RSTSTA (Reset Status) bit in the Control Register (US_CR). In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before the transmission of the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing a one to the RTSEN bit in the US_CR. The slave select line (NSS) can be released at high level only by writing a one to the RTSDIS bit in the US_CR (for example, when all data have been transferred to the slave device). In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1398 44.7.7.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a one to the RSTSTA (Reset Status) bit the US_CR. To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 44.7.7.7 Receiver Timeout Because the receiver baud rate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR). 44.7.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows onboard diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 44.7.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 44-39.Normal Mode Configuration RXD Receiver TXD Transmitter 44.7.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 44-40. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 44-40.Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 44.7.8.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 44-41. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1399 Figure 44-41.Local Loopback Mode Configuration RXD Receiver 1 Transmitter TXD 44.7.8.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 44-42. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 44-42.Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1400 44.7.9 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register (US_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset by reading the US_WPMR with the appropriate access key (WPKEY). The protected registers are:  “USART Mode Register”  “USART Baud Rate Generator Register”  “USART Receiver Time-out Register”  “USART Transmitter Timeguard Register”  “USART FI DI RATIO Register”  “USART IrDA FILTER Register”  “USART Manchester Configuration Register” SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1401 44.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 44-15. Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read-write – 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only – 0x0010 Interrupt Mask Register US_IMR Read-only 0x0 0x0014 Channel Status Register US_CSR Read-only – 0x0018 Receiver Holding Register US_RHR Read-only 0x0 0x001C Transmitter Holding Register US_THR Write-only – 0x0020 Baud Rate Generator Register US_BRGR Read-write 0x0 0x0024 Receiver Time-out Register US_RTOR Read-write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read-write 0x0 – – – 0x2C–0x3C Reserved 0x0040 FI DI Ratio Register US_FIDI Read-write 0x174 0x0044 Number of Errors Register US_NER Read-only – 0x0048 Reserved – – – 0x004C IrDA Filter Register US_IF Read-write 0x0 0x0050 Manchester Encoder Decoder Register US_MAN Read-write 0xB0011004 0x0054–0x005C Reserved – – – 0x0060–0x00E0 Reserved – – – 0x00E4 Write Protect Mode Register US_WPMR Read-write 0x0 0x00E8 Write Protect Status Register US_WPSR Read-only 0x0 – – – 0x00EC–0x00FC Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1402 44.8.1 USART Control Register Name: US_CR Address: 0xF001C000 (0), 0xF0020000 (1), 0xF8020000 (2), 0xF8024000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, see “USART Control Register (SPI_MODE)” on page 1405. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1403 • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1404 44.8.2 USART Control Register (SPI_MODE) Name: US_CR (SPI_MODE) Address: 0xF001C000 (0), 0xF0020000 (1), 0xF8020000 (2), 0xF8024000 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 1407. • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits OVRE, UNRE in US_CSR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1405 • FCS: Force SPI Chip Select Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): 0: No effect. 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). • RCS: Release SPI Chip Select Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE): 0: No effect. 1: Releases the Slave Select Line NSS (RTS pin). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1406 44.8.3 USART Mode Register Name: US_MR Address: 0xF001C004 (0), 0xF0020004 (1), 0xF8020004 (2), 0xF8024004 (3) Access: Read-write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. For SPI configuration, see “USART Mode Register (SPI_MODE)” on page 1410. • USART_MODE: USART Mode of Operation Value Name Description 0x0 NORMAL Normal mode 0x1 RS485 0x2 HW_HANDSHAKING Hardware Handshaking 0x4 IS07816_T_0 IS07816 Protocol: T = 0 0x6 IS07816_T_1 IS07816 Protocol: T = 1 0x8 IRDA 0xE SPI_MASTER SPI Master 0xF SPI_SLAVE SPI Slave RS485 IrDA • USCLKS: Clock Selection Value Name Description 0 MCK Master Clock MCK is selected 1 DIV Internal Clock Divided MCK/DIV (DIV=(DIV=8)) is selected 3 SCK Serial Clock SLK is selected SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1407 • CHRL: Character Length Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type Value Name Description 0 EVEN Even parity 1 ODD Odd parity 2 SPACE Parity forced to 0 (Space) 3 MARK Parity forced to 1 (Mark) 4 NO 6 MULTIDROP No parity Multidrop mode • NBSTOP: Number of Stop Bits Value Name Description 0 1_BIT 1 stop bit 1 1_5_BIT 2 2_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 2 stop bits • CHMODE: Channel Mode Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1408 • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • INVDATA: Inverted Data 0: The data field transmitted on TXD line is the same as the one written in US_THR register or the content read in US_RHR is the same as RXD line. Normal mode of operation. 1: The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR register or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted Mode of operation, useful for contactless card application. To be used with configuration bit MSBF. • VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on MODSYNC value. 1: The sync field is updated when a character is written into US_THR register. • MAX_ITERATION: Maximum Number of Automatic Iteration 0–7: Defines the maximum number of iterations in mode ISO7816, protocol T = 0. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). • MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. • MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1409 44.8.4 USART Mode Register (SPI_MODE) Name: US_MR (SPI_MODE) Address: 0xF001C004 (0), 0xF0020004 (1), 0xF8020004 (2), 0xF8024004 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 – 18 – 17 – 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 7 6 5 4 3 2 1 0 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 1407. This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. • USART_MODE: USART Mode of Operation Value Name Description 0xE SPI_MASTER SPI Master 0xF SPI_SLAVE SPI Slave • USCLKS: Clock Selection Value Name Description 0 MCK Master Clock MCK is selected 1 DIV Internal Clock Divided MCK/DIV (DIV=(DIV=8)) is selected 3 SCK Serial Clock SLK is selected • CHRL: Character Length Value Name Description 3 8_BIT Character length is 8 bits • CPHA: SPI Clock Phase – Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF): 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1410 • CHMODE: Channel Mode Value Name Description 0 NORMAL Normal Mode 1 AUTOMATIC 2 LOCAL_LOOPBACK 3 REMOTE_LOOPBACK Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • CPOL: SPI Clock Polarity Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF): 0: The inactive state value of SPCK is logic level zero. 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices. • WRDBT: Wait Read Data Before Transfer 0: The character transmission starts as soon as a character is written into US_THR register (assuming TXRDY was set). 1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receiver Holding Register has been read). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1411 44.8.5 USART Interrupt Enable Register Name: US_IER Address: 0xF001C008 (0), 0xF0020008 (1), 0xF8020008 (2), 0xF8024008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 1413. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITER: Max number of Repetitions Reached Interrupt Enable • NACK: Non AcknowledgeInterrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1412 44.8.6 USART Interrupt Enable Register (SPI_MODE) Name: US_IER (SPI_MODE) Address: 0xF001C008 (0), 0xF0020008 (1), 0xF8020008 (2), 0xF8024008 (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 1407. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • OVRE: Overrun Error Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • UNRE: SPI Underrun Error Interrupt Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1413 44.8.7 USART Interrupt Disable Register Name: US_IDR Address: 0xF001C00C (0), 0xF002000C (1), 0xF802000C (2), 0xF802400C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 1415. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITER: Max Number of Repetitions Reached Interrupt Disable • NACK: Non AcknowledgeInterrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1414 44.8.8 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address: 0xF001C00C (0), 0xF002000C (1), 0xF802000C (2), 0xF802400C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 1407. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • OVRE: Overrun Error Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • UNRE: SPI Underrun Error Interrupt Disable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1415 44.8.9 USART Interrupt Mask Register Name: US_IMR Address: 0xF001C010 (0), 0xF0020010 (1), 0xF8020010 (2), 0xF8024010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” on page 1417. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITER: Max Number of Repetitions Reached Interrupt Mask • NACK: Non AcknowledgeInterrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1416 44.8.10 USART Interrupt Mask Register (SPI_MODE) Name: US_IMR (SPI_MODE) Address: 0xF001C010 (0), 0xF0020010 (1), 0xF8020010 (2), 0xF8024010 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 1407. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • OVRE: Overrun Error Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • UNRE: SPI Underrun Error Interrupt Mask SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1417 44.8.11 USART Channel Status Register Name: US_CSR Address: 0xF001C014 (0), 0xF0020014 (1), 0xF8020014 (2), 0xF8024014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 1420. • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1418 • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: Max Number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. • NACK: Non AcknowledgeInterrupt 0: Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. • CTS: Image of CTS Input 0: CTS is set to 0. 1: CTS is set to 1. • MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1419 44.8.12 USART Channel Status Register (SPI_MODE) Name: US_CSR (SPI_MODE) Address: 0xF001C014 (0), 0xF0020014 (1), 0xF8020014 (2), 0xF8024014 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in “USART Mode Register” on page 1407. • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • UNRE: Underrun Error 0: No SPI underrun error has occurred since the last RSTSTA. 1: At least one SPI underrun error has occurred since the last RSTSTA. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1420 44.8.13 USART Receive Holding Register Name: US_RHR Address: 0xF001C018 (0), 0xF0020018 (1), 0xF8020018 (2), 0xF8024018 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1421 44.8.14 USART Transmit Holding Register Name: US_THR Address: 0xF001C01C (0), 0xF002001C (1), 0xF802001C (2), 0xF802401C (3) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be Transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1422 44.8.15 USART Baud Rate Generator Register Name: US_BRGR Address: 0xF001C020 (0), 0xF0020020 (1), 0xF8020020 (2), 0xF8024020 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. • CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 CD OVER = 0 OVER = 1 0 1 to 65535 SYNC = 1 or USART_MODE = SPI (Master or Slave) USART_MODE = ISO7816 Baud Rate Clock Disabled Baud Rate = Baud Rate = Baud Rate = Selected Clock/(16*CD) Selected Clock/(8*CD) Selected Clock/CD Baud Rate = Selected Clock/(FI_DI_RATIO*CD) • FP: Fractional Part 0: Fractional divider is disabled. 1–7: Baud rate resolution, defined by FP x 1/8. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1423 44.8.16 USART Receiver Time-out Register Name: US_RTOR Address: 0xF001C024 (0), 0xF0020024 (1), 0xF8020024 (2), 0xF8024024 (3) Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. • TO: Time-out Value 0: The Receiver Time-out is disabled. 1–65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1424 44.8.17 USART Transmitter Timeguard Register Name: US_TTGR Address: 0xF001C028 (0), 0xF0020028 (1), 0xF8020028 (2), 0xF8024028 (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1–255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1425 44.8.18 USART FI DI RATIO Register Name: US_FIDI Address: 0xF001C040 (0), 0xF0020040 (1), 0xF8020040 (2), 0xF8024040 (3) Access: Read-write Reset: 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 FI_DI_RATIO 7 6 5 4 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1–2047: If ISO7816 mode is selected, the baud rate is the clock provided on SCK divided by FI_DI_RATIO. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1426 44.8.19 USART Number of Errors Register Name: US_NER Address: 0xF001C044 (0), 0xF0020044 (1), 0xF8020044 (2), 0xF8024044 (3) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE = 0x4 or 0x6 in “USART Mode Register” on page 1407. • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1427 44.8.20 USART IrDA FILTER Register Name: US_IF Address: 0xF001C04C (0), 0xF002004C (1), 0xF802004C (2), 0xF802404C (3) Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE = 0x8 in “USART Mode Register” on page 1407. This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. • IRDA_FILTER: IrDA Filter The IRDA_FILTER value must be defined to meet the following criteria: tMCK * (IRDA_FILTER + 3) < 1.41 µs SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1428 44.8.21 USART Manchester Configuration Register Name: US_MAN Address: 0xF001C050 (0), 0xF0020050 (1), 0xF8020050 (2), 0xF8024050 (3) Access: Read-write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 25 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 10 – 9 7 – 6 – 5 – 4 – 3 2 1 24 RX_PP 17 16 RX_PL 8 TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 1431. • TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1–15: The Preamble Length is TX_PL x Bit Period • TX_PP: Transmitter Preamble Pattern The following values assume that TX_MPOL field is not set: Value Name Description 00 ALL_ONE The preamble is composed of ‘1’s 01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s • TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1–15: The detected preamble length is RX_PL x Bit Period SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1429 • RX_PP: Receiver Preamble Pattern detected The following values assume that RX_MPOL field is not set: Value Name Description 00 ALL_ONE The preamble is composed of ‘1’s 01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register. • DRIFT: Drift Compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1430 44.8.22 USART Write Protect Mode Register Name: US_WPMR Address: 0xF001C0E4 (0), 0xF00200E4 (1), 0xF80200E4 (2), 0xF80240E4 (3) Access: Read-write Reset: See Table 44-15 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 — — — — — — — WPEN • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII). Protects the registers: • “USART Mode Register” on page 1407 • “USART Baud Rate Generator Register” on page 1423 • “USART Receiver Time-out Register” on page 1424 • “USART Transmitter Timeguard Register” on page 1425 • “USART FI DI RATIO Register” on page 1426 • “USART IrDA FILTER Register” on page 1428 • “USART Manchester Configuration Register” on page 1429 • WPKEY: Write Protect KEY Value Name 0x555341 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1431 44.8.23 USART Write Protect Status Register Name: US_WPSR Address: 0xF001C0E8 (0), 0xF00200E8 (1), 0xF80200E8 (2), 0xF80240E8 (3) Access: Read-only Reset: See Table 44-15 31 30 29 28 27 26 25 24 — — — — — — — — 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 — — — — — — — WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the US_WPSR. 1: A Write Protect Violation has occurred since the last read of the US_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Note: Reading US_WPSR automatically clears all fields. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1432 45. Controller Area Network (CAN) 45.1 Description The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/s. CAN controller accesses are made through configuration registers. 8 independent message objects (mailboxes) are implemented. Any mailbox can be programmed as a reception buffer block (even non-consecutive buffers). For the reception of defined messages, one or several message objects can be masked without participating in the buffer feature. An interrupt is generated when the buffer is full. According to the mailbox configuration, the first message received can be locked in the CAN controller registers until the application acknowledges it, or this message can be discarded by new received messages. Any mailbox can be programmed for transmission. Several transmission mailboxes can be enabled in the same time. A priority can be defined for each mailbox independently. An internal 16-bit timer is used to stamp each received and sent message. This timer starts counting as soon as the CAN controller is enabled. This counter can be reset by the application or automatically after a reception in the last mailbox in Time Triggered Mode. The CAN controller offers optimized features to support the Time Triggered Communication (TTC) protocol. 45.2 Embedded Characteristics  Fully Compliant with CAN 2.0 Part A and 2.0 Part B  Bit Rates up to 1 Mbit/s  8 Object Oriented Mailboxes with the Following Properties:  CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message  Object Configurable in Receive (with Overwrite or Not) or Transmit Modes  Independent 29-bit Identifier and Mask Defined for Each Mailbox  32-bit Access to Data Registers for Each Mailbox Data Object  Uses a 16-bit Timestamp on Receive and Transmit Messages  Hardware Concatenation of ID Masked Bitfields To Speed Up Family ID Processing  16-bit Internal Timer for Timestamping and Network Synchronization  Programmable Reception Buffer Length up to 8 Mailbox Objects  Priority Management between Transmission Mailboxes  Autobaud and Listening Mode  Low Power Mode and Programmable Wake-up on Bus Activity or by the Application  Data, Remote, Error and Overload Frame Handling  Write Protected Registers SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1433 45.3 Block Diagram Figure 45-1. CAN Block Diagram Controller Area Network CANRX CAN Protocol Controller PIO CANTX Error Counter Mailbox Priority Encoder Control & Status MB0 MB1 MCK PMC MBx (x = number of mailboxes - 1) CAN Interrupt User Interface Internal Bus SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1434 45.4 Application Block Diagram Figure 45-2. Application Block Diagram 45.5 Layers Implementation CAN-based Profiles Software CAN-based Application Layer Software CAN Data Link Layer CAN Controller CAN Physical Layer Transceiver I/O Lines Description Table 45-1. I/O Lines Description Name Description Type CANRX CAN Receive Serial Data Input CANTX CAN Transmit Serial Data Output 45.6 Product Dependencies 45.6.1 I/O Lines The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function. If I/O lines of the CAN are not used by the application, they can be used for other purposes by the PIO Controller. Table 45-2. I/O Lines Instance Signal I/O Line Peripheral CAN0 CANRX0 PD14 C CAN0 CANTX0 PD15 C CAN1 CANRX1 PB14 B CAN1 CANTX1 PB15 B 45.6.2 Power Management The programmer must first enable the CAN clock in the Power Management Controller (PMC) before using the CAN. A Low-power Mode is defined for the CAN controller. If the application does not require CAN operations, the CAN clock can be stopped when not needed and be restarted later. Before stopping the clock, the CAN Controller must be in Lowpower Mode to complete the current transfer. After restarting the clock, the application must disable the Low-power Mode of the CAN controller. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1435 45.6.3 Interrupt The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the CAN interrupt requires the interrupt controller to be programmed first. Note that it is not recommended to use the CAN interrupt line in edge-sensitive mode. Table 45-3. Peripheral IDs 45.7 Instance ID CAN0 40 CAN1 41 CAN Controller Features 45.7.1 CAN Protocol Overview The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s. The CAN protocol supports four different frame types:  Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame.  Remote frames: A destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node then sends a data frame as a response to this node request.  Error frames: An error frame is generated by any node that detects a bus error.  Overload frames: They provide an extra delay between the preceding and the successive data frames or remote frames. The Atmel CAN controller provides the CPU with full functionality of the CAN protocol V2.0 Part A and V2.0 Part B. It minimizes the CPU load in communication overhead. The Data Link Layer and part of the physical layer are automatically handled by the CAN controller itself. The CPU reads or writes data or messages via the CAN controller mailboxes. An identifier is assigned to each mailbox. The CAN controller encapsulates or decodes data messages to build or to decode bus data frames. Remote frames, error frames and overload frames are automatically handled by the CAN controller under supervision of the software application. 45.7.2 Mailbox Organization The CAN module has 8 buffers, also called channels or mailboxes. An identifier that corresponds to the CAN identifier is defined for each active mailbox. Message identifiers can match the standard frame identifier or the extended frame identifier. This identifier is defined for the first time during the CAN initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. Several mailboxes can be configured with the same ID. Each mailbox can be configured in receive or in transmit mode independently. The mailbox object type is defined in the MOT field of the CAN_MMRx. 45.7.2.1 Message Acceptance Procedure If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. Once a new message is received, its ID is masked with the CAN_MAMx value and compared with the CAN_MIDx value. If accepted, the message ID is copied to the CAN_MIDx register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1436 Figure 45-3. Message Acceptance Procedure CAN_MAMx CAN_MIDx & Message Received & == No Message Refused Yes Message Accepted CAN_MFIDx If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register (CAN_MFIDx). For example, if the following message IDs are handled by the same mailbox: ID0 101000100100010010000100 0 11 00b ID1 101000100100010010000100 0 11 01b ID2 101000100100010010000100 0 11 10b ID3 101000100100010010000100 0 11 11b ID4 101000100100010010000100 1 11 00b ID5 101000100100010010000100 1 11 01b ID6 101000100100010010000100 1 11 10b ID7 101000100100010010000100 1 11 11b The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values: CAN_MIDx = 001 101000100100010010000100 x 11 xxb CAN_MAMx = 001 111111111111111111111111 0 11 00b If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set: CAN_MIDx = 001 101000100100010010000100 1 11 10b CAN_MFIDx = 00000000000000000000000000000110b If the application associates a handler for each message ID, it may define an array of pointers to functions: void (*pHandler[8])(void); When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits: unsigned int MFID0_register; MFID0_register = Get_CAN_MFID0_Register(); // Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register pHandler[MFID0_register](); 45.7.2.2 Receive Mailbox When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers. Depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application (Receive only), or, if new messages with the same ID are received, then they overwrite the previous ones (Receive with overwrite). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1437 It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers. Several mailboxes can be chained to receive a buffer. They must be configured with the same ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow. Table 45-4. Receive Mailbox Objects Object Type Receive Receive with overwrite Consumer Description The first message received is stored in mailbox data registers. Data remain available until the next transfer request. The last message received is stored in mailbox data register. The next message always overwrites the previous one. The application has to check whether a new message has not overwritten the current one while reading the data registers. A remote frame is sent by the mailbox. The answer received is stored in mailbox data register. This extends Receive mailbox features. Data remain available until the next transfer request. 45.7.2.3 Transmit Mailbox When transmitting a message, the message length and data are written to the transmit mailbox with the correct identifier. For each transmit mailbox, a priority is assigned. The controller automatically sends the message with the highest priority first (set with the field PRIOR in CAN_MMRx). It is also possible to configure a mailbox in Producer Mode. In this mode, when a remote frame is received, the mailbox data are sent automatically. By enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer. Table 45-5. Transmit Mailbox Objects Object Type Transmit Description The message stored in the mailbox data registers will try to win the bus arbitration immediately or later according to or not the Time Management Unit configuration (see Section 45.7.3). The application is notified that the message has been sent or aborted. Producer The message prepared in the mailbox data registers will be sent after receiving the next remote frame. This extends transmit mailbox features. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1438 45.7.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR). It is automatically cleared in the following cases:  after a reset  when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and SLEEP bit set in the CAN_SR)  after a reset of the CAN controller (CANEN bit in the CAN_MR)  in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in the CAN_MSRlast_mailbox_number register). The application can also reset the internal timer by setting TIMRST in the CAN_TCR. The current value of the internal timer is always accessible by reading the CAN_TIM register. When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR is set. TOVF bit in the CAN_SR is cleared by reading the CAN_SR. Depending on the corresponding interrupt mask in the CAN_IMR, an interrupt is generated while TOVF is set. In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device. This feature is enabled by setting TIMFRZ in the CAN_MR. The CAN_TIM register is frozen to the FFFFh value. A clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered. To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR is set, the value is captured at each End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the CAN_IMR, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the CAN_SR. The time management unit can operate in one of the two following modes:  Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame  Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing TTM field in the CAN_MR. Time Triggered Mode is enabled by setting TTM field in the CAN_MR. 45.7.4 CAN 2.0 Standard Features 45.7.4.1 CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments. Figure 45-4. Partition of the CAN Bit Time NOMINAL BIT TIME SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample Point  SYNC SEG: SYNChronization Segment This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. It is one TQ long. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1439  PROP SEG: PROPagation Segment This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal’s propagation time on the bus line, the input comparator delay, and the output driver delay. It is programmable to be 1,2,..., 8 TQ long. This parameter is defined in the PROPAG field of the ”CAN Baudrate Register”.  PHASE SEG1, PHASE SEG2: PHASE Segment 1 and 2 The Phase-Buffer-Segments are used to compensate for edge phase errors. These segments can be lengthened (PHASE SEG1) or shortened (PHASE SEG2) by resynchronization. Phase Segment 1 is programmable to be 1, 2, ..., 8 TQ long. Phase Segment 2 length has to be at least as long as the Information Processing Time (IPT) and may not be more than the length of Phase Segment 1. These parameters are defined in the PHASE1 and PHASE2 fields of the ”CAN Baudrate Register”.  TIME QUANTUM The TIME QUANTUM (TQ) is a fixed unit of time derived from the MCK period. The total number of TIME QUANTA in a bit time is programmable from 8 to 25.  INFORMATION PROCESSING TIME The Information Processing Time (IPT) is the time required for the logic to determine the bit level of a sampled bit. The IPT begins at the sample point, is measured in TQ and is fixed at two TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PHASE SEG2 shall not be less than the IPT.  SAMPLE POINT The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1.  SJW: ReSynchronization Jump Width The ReSynchronization Jump Width defines the limit to the amount of lengthening or shortening of the phase segments. SJW is programmable to be the minimum of PHASE SEG1 and four TQ. If the SMP field in the CAN_BR is set, then the incoming bit stream is sampled three times with a period of half a CAN clock period, centered on sample point. In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and PHASE2). t BIT = t CSC + t PRS + t PHS1 + t PHS2 The time quantum is calculated as follows: t CSC = ( BRP + 1 ) ⁄ MCK Note: The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized. t PRS = t CSC × ( PROPAG + 1 ) t PHS1 = t CSC × ( PHASE1 + 1 ) t PHS2 = t CSC × ( PHASE2 + 1 ) To compensate for phase shifts between clock oscillators of different controllers on the bus, the CAN controller must resynchronize on any relevant signal edge of the current transmission. The resynchronization shortens or lengthens the bit time so that the position of the sample point is shifted with regard to the detected edge. The resynchronization jump width (SJW) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization. t SJW = t CSC × ( SJW + 1 ) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1440 Figure 45-5. CAN Bit Timing MCK CAN Clock tCSC tPRS tPHS1 tPHS2 NOMINAL BIT TIME SYNC_ SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample Point Transmission Point SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1441 Example of bit timing determination for CAN baudrate of 500 Kbit/s: MCK = 48 MHz CAN baudrate = 500 Kbit/s => bit time = 2 µs Delay of the bus driver: 50 ns Delay of the receiver: 30 ns Delay of the bus line (20 m): 110 ns The total number of time quanta in a bit time must be comprised between 8 and 25. If we fix the bit time to 16 time quanta: tCSC = 1 time quanta = bit time / 16 = 125 ns => BRP = (tCSC x MCK) - 1 = 5 The propagation segment time is equal to twice the sum of the signal’s propagation time on the bus line, the receiver delay and the output driver delay: tPRS = 2 * (50+30+110) ns = 380 ns = 3 tCSC => PROPAG = tPRS/tCSC - 1 = 2 The remaining time for the two phase segments is: tPHS1 + tPHS2 = bit time - tCSC - tPRS = (16 - 1 - 3)tCSC tPHS1 + tPHS2 = 12 tCSC Because this number is even, we choose tPHS2 = tPHS1 (else we would choose tPHS2 = tPHS1 + tCSC). tPHS1 = tPHS2 = (12/2) tCSC = 6 tCSC => PHASE1 = PHASE2 = tPHS1/tCSC - 1 = 5 The resynchronization jump width must comprise between one tCSC and the minimum of four tCSC and tPHS1. We choose its maximum value: tSJW = Min(4 tCSC,tPHS1) = 4 tCSC => SJW = tSJW/tCSC - 1 = 3 Finally: CAN_BR = 0x00053255 CAN Bus Synchronization Two types of synchronization are distinguished: “hard synchronization” at the start of a frame and “resynchronization” inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge. The effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width (tSJW). When the magnitude of the phase error is larger than the resynchronization jump width and  the phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the resynchronization jump width.  the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1442 Figure 45-6. CAN Resynchronization THE PHASE ERROR IS POSITIVE (the transmitter is slower than the receiver) Nominal Sample point Sample point after resynchronization Received data bit Nominal bit time (before resynchronization) SYNC_ SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Phase error (max Tsjw) Phase error Bit time with resynchronization SYNC_ SEG SYNC_ SEG PROP_SEG PHASE_SEG1 THE PHASE ERROR IS NEGATIVE (the transmitter is faster than the receiver) PHASE_SEG2 Sample point after resynchronization SYNC_ SEG Nominal Sample point Received data bit Nominal bit time (before resynchronization) PHASE_SEG2 SYNC_ SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 SYNC_ SEG Phase error Bit time with resynchronization PHASE_ SYNC_ SEG2 SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 SYNC_ SEG Phase error (max Tsjw) Autobaud Mode The autobaud feature is enabled by setting the ABM field in the CAN_MR. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It can not send any message. The errors flags are updated. The bit timing can be adjusted until no error occurs (good configuration found). In this mode, the error counters are frozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MR. 45.7.4.2 Error Detection There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence):  CRC error (CERR bit in the CAN_SR): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame.  Bit-stuffing error (SERR bit in the CAN_SR): If a node detects a sixth consecutive equal bit level during the bitstuffing area of a frame, it generates an Error Frame starting with the next bit-time.  Bit error (BERR bit in CAN_SR): A bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. An error frame is generated and starts with the next bit time.  Form Error (FERR bit in the CAN_SR): If a transmitter detects a dominant bit in one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error has occurred and an error frame is generated.  Acknowledgment error (AERR bit in the CAN_SR): The transmitter checks the Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. If this is the case, at least one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an Error Frame transmission. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1443 Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are decremented upon correct transmissions or receptions, respectively. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags. The controller changes to the Error Passive state if there is an accumulation of errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus Off. Figure 45-7. Line Error Mode Init TEC < 127 and REC < 127 ERROR PASSIVE ERROR ACTIVE TEC > 127 or REC > 127 128 occurences of 11 consecutive recessive bits or CAN controller reset BUS OFF TEC > 255 An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the CAN_ECR. The state of the CAN controller is automatically updated according to these counter values. If the CAN controller enters Error Active state, then the ERRA bit is set in the CAN_SR. The corresponding interrupt is pending while the interrupt is not masked in the CAN_IMR. If the CAN controller enters Error Passive Mode, then the ERRP bit is set in the CAN_SR and an interrupt remains pending while the ERRP bit is set in the CAN_IMR. If the CAN enters Bus Off Mode, then the BOFF bit is set in the CAN_SR. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in the CAN_IMR. When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the WARN bit in CAN_SR, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR. Refer to the Bosch CAN specification v2.0 for details on fault confinement. Error Interrupt Handler ERRA, WARN, ERRP and BOFF (CAN_SR) store the key transitions of the CAN bus status as defined in Figure 45-7 on page 1444. The transitions depend on the TEC and REC (CAN_ECR) values as described in Section “Fault Confinement” on page 1444. These flags are latched to keep from triggering a spurious interrupt in case these bits are used as the source of an interrupt. Thus, these flags may not reflect the current status of the CAN bus. The current CAN bus state can be determined by reading the TEC and REC fields of CAN_ECR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1444 45.7.4.3 Overload The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field respectively. Reactive overload frames are transmitted after detection of the following error conditions:  Detection of a dominant bit during the first two bits of the intermission field  Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR. Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR is not set. An overload flag is generated in the same way as an error flag, but error counters do not increment. 45.7.5 Low-power Mode In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive. In Low-power Mode, the SLEEP signal in the CAN_SR is set; otherwise, the WAKEUP signal in the CAN_SR is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Low-power Mode is disabled and the WAKEUP bit is set in the CAN_SR only after detection of 11 consecutive recessive bits on the bus. 45.7.5.1 Enabling Low-power Mode A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent. When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR is set. Depending on the corresponding mask in the CAN_IMR, an interrupt is generated while SLEEP is set. The SLEEP signal in the CAN_SR is automatically cleared once WAKEUP is set. The WAKEUP signal is automatically cleared once SLEEP is set. Reception is disabled while the SLEEP signal is set to one in the CAN_SR. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Lowpower Mode. Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip’s Power Management Controller (PMC). The CAN controller drains only the static current. Error counters are disabled while the SLEEP signal is set to one. Thus, to enter Low-power Mode, the software application must:  Set LPM field in the CAN_MR  Wait for SLEEP signal rising Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1445 Figure 45-8. Enabling Low-power Mode Arbitration lost Mailbox 1 CAN BUS Mailbox 3 LPEN= 1 LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSR1) MRDY (CAN_MSR3) CAN_TIM 0x0 45.7.5.2 Disabling Low-power Mode The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller. To disable Low-power Mode, the software application must:  Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC).  Clear the LPM field in the CAN_MR The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive “recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR is set. Depending on the corresponding mask in the CAN_IMR, an interrupt is generated while WAKEUP is set. The SLEEP signal in the CAN_SR is automatically cleared once WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set. If no message is being sent on the bus, then the CAN controller is able to send a message eleven bit times after disabling Low-power Mode. If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see Figure 45-9). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1446 Figure 45-9. Disabling Low-power Mode Bus Activity Detected CAN BUS Message lost LPM (CAN_MR) Message x Interframe synchronization SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSRx) 45.8 Functional Description 45.8.1 CAN Controller Initialization After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller. The CAN controller must be initialized with the CAN network parameters. The CAN_BR defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the CAN_MR. The CAN controller is enabled by setting the CANEN flag in the CAN_MR. At this stage, the internal CAN controller state machine is reset, error counters are reset to 0, error flags are reset to 0. Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The WAKEUP bit in the CAN_SR is automatically set to 1 when the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset). The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1447 Figure 45-10.Possible Initialization Procedure Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (Interrupt Controller) Configure a Mailbox in Reception Mode Change CAN_BR value (ABM == 1 and CANEN == 1) Errors ? Yes (CAN_SR or CAN_MSRx) No ABM = 0 and CANEN = 0 CANEN = 1 (ABM == 0) End of Initialization 45.8.2 CAN Controller Interrupt Handling There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. All interrupt sources can be masked by writing the corresponding field in the CAN_IDR. They can be unmasked by writing to the CAN_IER. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR. The CAN_SR gives all interrupt source states. The following events may initiate one of the two interrupts:   Message object interrupt  Data registers in the mailbox object are available to the application. In Receive Mode, a new message was received. In Transmit Mode, a message was transmitted successfully.  A sent transmission was aborted. System interrupts  Bus off interrupt: The CAN module enters the bus off state.  Error passive interrupt: The CAN module enters Error Passive Mode.  Error Active Mode: The CAN module is neither in Error Passive Mode nor in Bus Off mode.  Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96.  Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization.  Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all pending messages in transmission have been sent.  Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1448  Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register. All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR. 45.8.3 CAN Controller Message Handling 45.8.3.1 Receive Handling Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox. Simple Receive Mailbox A mailbox is in Receive Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. Message data are stored in the mailbox data register until the software application notifies that data processing has ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx. This automatically clears the MRDY signal. The MMI flag in the CAN_MSRx notifies the software that a message has been lost by the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx. See Figure 45-11. Figure 45-11.Receive Mailbox Message ID = CAN_MIDx CAN BUS Message 1 Message 2 lost Message 3 MRDY (CAN_MSRx) MMI (CAN_MSRx) (CAN_MDLx CAN_MDHx) Message 1 Message 3 MTCR (CAN_MCRx) Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx Note: In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler instruction. Receive with Overwrite Mailbox A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1449 After Receive Mode is enabled, the MRDY flag in the CAN_MSR is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register. If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx notifies the software that a message has been dropped by the mailbox. This flag is cleared when reading the CAN_MSRx. The CAN controller may store a new message in the CAN data registers while the application reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages, the application must check the MMI field in the CAN_MSRx before and after reading CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been read, the software application has to re-read CAN_MDHx and CAN_MDLx (see Figure 45-12). Figure 45-12.Receive with Overwrite Mailbox Message ID = CAN_MIDx CAN BUS Message 1 Message 2 Message 3 Message 4 MRDY (CAN_MSRx) MMI (CAN_MSRx) (CAN_MDLx CAN_MDHx) Message 1 Message 2 Message 3 Message 4 MTCR (CAN_MCRx) Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx Chaining Mailboxes Several mailboxes may be used to receive a buffer split into several messages with the same ID. In this case, the mailbox with the lowest number is serviced first. In the receive and receive with overwrite modes, the field PRIOR in the CAN_MMRx has no effect. If Mailbox 0 and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive Mode (i.e., the first message received is considered) and Mailbox 5 must be configured in Receive with Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced. If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last mailbox and refused by previous ones (see Figure 45-13). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1450 Figure 45-13.Chaining Three Mailboxes to Receive a Buffer Split into Three Messages Buffer split in 3 messages CAN BUS Message s1 Message s2 Message s3 MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz) Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see Figure 45-14). Figure 45-14.Chaining Three Mailboxes to Receive a Buffer Split into Four Messages Buffer split in 4 messages CAN BUS Message s1 Message s2 Message s3 Message s4 MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz) Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1451 45.8.3.2 Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the CAN_MCRx. The MRDY flag remains at zero as long as the message has not been sent or aborted. It is important to note that no access to the mailbox data register is allowed while the MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field. The answer to the remote frame is handled by another reception mailbox. In this case, the device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote frame emission and the answer reception using only one mailbox configured in Consumer Mode. Refer to the section “Remote Frame Handling” on page 1453. Several messages can try to win the bus arbitration in the same time. The message with the highest priority is sent first. Several transfer request commands can be generated at the same time by setting MBx bits in the CAN_TCR. The priority is set in the PRIOR field of the CAN_MMRx. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox 0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first. Setting the MACR bit in the CAN_MCRx aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR. If the message is being sent when the abort command is set, then the application is notified by the MRDY bit set and not the MABT in the CAN_MSRx. Otherwise, if the message has not been sent, then the MRDY and the MABT are set in the CAN_MSR. When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next bus arbitration with the same message if this one still has the highest priority. Messages to be sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by setting the bit DRPT in the CAN_MR. In this case if the message was not sent the first time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set in the CAN_MSRx until the next transfer command. Figure 45-15 shows three MBx message attempts being made (MRDY of MBx set to 0). The first MBx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the CAN transceiver. Figure 45-15.Transmitting Messages CAN BUS MBx message MBx message MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Abort MBx message Try to Abort MBx message Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1452 45.8.3.3 Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. Figure 45-16.Producer / Consumer Model Producer Request PUSH MODEL CAN Data Frame Consumer Indication(s) PULL MODEL Producer Indications Response Consumer CAN Remote Frame Request(s) CAN Data Frame Confirmation(s) In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit Mode to send remote frames, and at least one in Receive Mode to capture the producer’s answer. The same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer. Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the remote frame and the answer. With 8 mailboxes, the CAN controller can handle 8 independent producers/consumers. Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration. The MRDY flag remains at zero as long as the message has not been sent or aborted. No access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. If a remote frame is received while no data are ready to be sent (signal MRDY set in the CAN_MSRx), then the MMI signal is set in the CAN_MSRx. This bit is cleared by reading the CAN_MSRx. The MRTR field in the CAN_MSRx has no meaning. This field is used only when using Receive and Receive with Overwrite modes. After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by setting the MACR bit in the CAN_MCR. Please refer to the section “Transmission Handling” on page 1452. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1453 Figure 45-17.Producer Handling Remote Frame CAN BUS Message 1 Remote Frame Remote Frame Message 2 MRDY (CAN_MSRx) MMI (CAN_MSRx) Reading CAN_MSRx MTCR (CAN_MCRx) (CAN_MDLx CAN_MDHx) Message 1 Message 2 Consumer Configuration A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Consumer Mode is enabled, the MRDY flag in the CAN_MSR is automatically cleared until the first transfer request command. The software application sends a remote frame by setting the MTCR bit in the CAN_MCRx or the MBx bit in the global CAN_TCR. The application is notified of the answer by the MRDY flag set in the CAN_MSRx. The application can read the data contents in the CAN_MDHx and CAN_MDLx registers. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. The MRTR bit in the CAN_MCRx has no effect. This field is used only when using Transmit Mode. After a remote frame has been sent, the consumer mailbox functions as a reception mailbox. The first message received is stored in the mailbox data registers. If other messages intended for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx, they will be lost. The application is notified by reading the MMI field in the CAN_MSRx. The read operation automatically clears the MMI flag. If several messages are answered by the Producer, the CAN controller may have one mailbox in consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in Receive with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR. Figure 45-18.Consumer Handling CAN BUS Remote Frame Message x Remote Frame Message y MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) (CAN_MDLx CAN_MDHx) Message x Message y SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1454 45.8.4 CAN Controller Timing Modes Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes:  Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame.  Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR. Time Triggered Mode is enabled by setting the TTM bit in the CAN_MR. 45.8.4.1 Timestamping Mode Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transferred to the LSB bits of the CAN_MSRx. The value read in the CAN_MSRx corresponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the mailbox. Figure 45-19.Mailbox Timestamp Start of Frame CAN BUS End of Frame Message 1 Message 2 CAN_TIM TEOF (CAN_MR) TIMESTAMP (CAN_TSTP) Timestamp 1 MTIMESTAMP (CAN_MSRx) Timestamp 1 Timestamp 2 MTIMESTAMP (CAN_MSRy) Timestamp 2 45.8.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a predefined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. Figure 45-20.Time Triggered Principle Time Cycle Reference Message Reference Message Time Windows for Messages Global Time Time Trigger Mode is enabled by setting the TTM field in the CAN_MR. In Time Triggered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1455 Synchronization by a Reference Message In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the CAN_MSRx. This allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window. Transmitting within a Time Window A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the CAN_MMRx. At each internal timer clock cycle, the value of the CAN_TIM is compared with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox. In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value defined in the CAN_MMRx. If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and is retried in the next time window when CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting the DRPT field in the CAN_MR. Freezing the Internal Timer Counter The internal counter can be frozen by setting TIMFRZ in the CAN_MR. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR is set when the counter is frozen. The TOVF bit in the CAN_SR is cleared by reading the CAN_SR. Depending on the corresponding interrupt mask in the CAN_IMR, an interrupt is generated when TOVF is set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1456 Figure 45-21.Time Triggered Operations Message x Arbitration Lost End of Frame CAN BUS Reference Message Message y Arbitration Win Message y Internal Counter Reset CAN_TIM Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MTIMEMARKx == CAN_TIM MRDY (CAN_MSRx) MTIMEMARKy == CAN_TIM Timer Event y MRDY (CAN_MSRy) Time Window Basic Cycle Message x Arbitration Win End of Frame CAN BUS Reference Message Message x Internal Counter Reset CAN_TIM Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MTIMEMARKx == CAN_TIM MRDY (CAN_MSRx) Time Window Basic Cycle SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1457 45.8.5 Write Protected Registers To prevent any single software error that may corrupt CAN behavior, the registers listed below can be write-protected by setting the WPEN bit in the CAN Write Protection Mode Register (CAN_WPMR). If a write access in a write-protected register is detected, then the WPVS flag in the CAN Write Protection Status Register (CAN_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset after reading the CAN_WPSR. List of the write-protected registers: Section 45.9.1 “CAN Mode Register” on page 1460 Section 45.9.6 “CAN Baudrate Register” on page 1471 Section 45.9.14 “CAN Message Mode Register” on page 1479 Section 45.9.15 “CAN Message Acceptance Mask Register” on page 1480 Section 45.9.16 “CAN Message ID Register” on page 1481 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1458 45.9 Controller Area Network (CAN) User Interface Table 45-6. Register Mapping Offset Register Name Access Reset 0x0000 Mode Register CAN_MR Read-write 0x0 0x0004 Interrupt Enable Register CAN_IER Write-only – 0x0008 Interrupt Disable Register CAN_IDR Write-only – 0x000C Interrupt Mask Register CAN_IMR Read-only 0x0 0x0010 Status Register CAN_SR Read-only 0x0 0x0014 Baudrate Register CAN_BR Read-write 0x0 0x0018 Timer Register CAN_TIM Read-only 0x0 0x001C Timestamp Register CAN_TIMESTP Read-only 0x0 0x0020 Error Counter Register CAN_ECR Read-only 0x0 0x0024 Transfer Command Register CAN_TCR Write-only – 0x0028 Abort Command Register CAN_ACR Write-only – – – – 0x002C–x00E0 Reserved 0x00E4 Write Protect Mode Register CAN_WPMR Read-write 0x0 0x00E8 Write Protect Status Register CAN_WPSR Read-only 0x0 – – – CAN_MMR Read-write 0x0 0x00EC–0x01FC Reserved (1) 0x0200 + MB * 0x20 + 0x00 Mailbox Mode Register 0x0200 + MB * 0x20 + 0x04 Mailbox Acceptance Mask Register CAN_MAM Read-write 0x0 0x0200 + MB * 0x20 + 0x08 Mailbox ID Register CAN_MID Read-write 0x0 0x0200 + MB * 0x20 + 0x0C Mailbox Family ID Register CAN_MFID Read-only 0x0 0x0200 + MB * 0x20 + 0x10 Mailbox Status Register CAN_MSR Read-only 0x0 0x0200 + MB * 0x20 + 0x14 Mailbox Data Low Register CAN_MDL Read-write 0x0 0x0200 + MB * 0x20 + 0x18 Mailbox Data High Register CAN_MDH Read-write 0x0 0x0200 + MB * 0x20 + 0x1C Mailbox Control Register CAN_MCR Write-only – Notes: 1. Mailbox number ranges from 0 to 7. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1459 45.9.1 CAN Mode Register Name: CAN_MR Address: 0xF000C000 (0), 0xF8010000 (1) Access: Read-write 31 – 23 – 15 – 7 DRPT 30 – 22 – 14 – 6 TIMFRZ 29 – 21 – 13 – 5 TTM 28 – 20 – 12 – 4 TEOF 27 – 19 – 11 – 3 OVL 26 25 24 18 – 10 – 2 ABM 17 – 9 – 1 LPM 16 – 8 – 0 CANEN This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. • CANEN: CAN Controller Enable 0: The CAN Controller is disabled. 1: The CAN Controller is enabled. • LPM: Disable/Enable Low Power Mode w Power Mode. 1: Enable Low Power M CAN controller enters Low Power Mode once all pending messages have been transmitted. • ABM: Disable/Enable Autobaud/Listen mode 0: Disable Autobaud/listen mode. 1: Enable Autobaud/listen mode. • OVL: Disable/Enable Overload Frame 0: No overload frame is generated. 1: An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite Mode, Producer and Consumer. • TEOF: Timestamp messages at each end of Frame 0: The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame. 1: The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame. • TTM: Disable/Enable Time Triggered Mode 0: Time Triggered Mode is disabled. 1: Time Triggered Mode is enabled. • TIMFRZ: Enable Timer Freeze 0: The internal timer continues to be incremented after it reached 0xFFFF. 1: The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See “Freezing the Internal Timer Counter” on page 1456. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1460 • DRPT: Disable Repeat 0: When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1: When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1461 45.9.2 CAN Interrupt Enable Register Name: CAN_IER Address: 0xF000C004 (0), 0xF8010004 (1) Access: Write-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 • MBx: Mailbox x Interrupt Enable 0: No effect. 1: Enable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Enable 0: No effect. 1: Enable ERRA interrupt. • WARN: Warning Limit Interrupt Enable 0: No effect. 1: Enable WARN interrupt. • ERRP: Error Passive Mode Interrupt Enable 0: No effect. 1: Enable ERRP interrupt. • BOFF: Bus Off Mode Interrupt Enable 0: No effect. 1: Enable BOFF interrupt. • SLEEP: Sleep Interrupt Enable 0: No effect. 1: Enable SLEEP interrupt. • WAKEUP: Wakeup Interrupt Enable 0: No effect. 1: Enable SLEEP interrupt. • TOVF: Timer Overflow Interrupt Enable 0: No effect. 1: Enable TOVF interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1462 • TSTP: TimeStamp Interrupt Enable 0: No effect. 1: Enable TSTP interrupt. • CERR: CRC Error Interrupt Enable 0: No effect. 1: Enable CRC Error interrupt. • SERR: Stuffing Error Interrupt Enable 0: No effect. 1: Enable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Enable 0: No effect. 1: Enable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Enable 0: No effect. 1: Enable Form Error interrupt. • BERR: Bit Error Interrupt Enable 0: No effect. 1: Enable Bit Error interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1463 45.9.3 CAN Interrupt Disable Register Name: CAN_IDR Address: 0xF000C008 (0), 0xF8010008 (1) Access: Write-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 • MBx: Mailbox x Interrupt Disable 0: No effect. 1: Disable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Disable 0: No effect. 1: Disable ERRA interrupt. • WARN: Warning Limit Interrupt Disable 0: No effect. 1: Disable WARN interrupt. • ERRP: Error Passive Mode Interrupt Disable 0: No effect. 1: Disable ERRP interrupt. • BOFF: Bus Off Mode Interrupt Disable 0: No effect. 1: Disable BOFF interrupt. • SLEEP: Sleep Interrupt Disable 0: No effect. 1: Disable SLEEP interrupt. • WAKEUP: Wakeup Interrupt Disable 0: No effect. 1: Disable WAKEUP interrupt. • TOVF: Timer Overflow Interrupt 0: No effect. 1: Disable TOVF interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1464 • TSTP: TimeStamp Interrupt Disable 0: No effect. 1: Disable TSTP interrupt. • CERR: CRC Error Interrupt Disable 0: No effect. 1: Disable CRC Error interrupt. • SERR: Stuffing Error Interrupt Disable 0: No effect. 1: Disable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Disable 0: No effect. 1: Disable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Disable 0: No effect. 1: Disable Form Error interrupt. • BERR: Bit Error Interrupt Disable 0: No effect. 1: Disable Bit Error interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1465 45.9.4 CAN Interrupt Mask Register Name: CAN_IMR Address: 0xF000C00C (0), 0xF801000C (1) Access: Read-only 31 – 23 TSTP 15 – 7 MB7 30 – 22 TOVF 14 – 6 MB6 29 – 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 • MBx: Mailbox x Interrupt Mask 0: Mailbox x interrupt is disabled. 1: Mailbox x interrupt is enabled. • ERRA: Error Active Mode Interrupt Mask 0: ERRA interrupt is disabled. 1: ERRA interrupt is enabled. • WARN: Warning Limit Interrupt Mask 0: Warning Limit interrupt is disabled. 1: Warning Limit interrupt is enabled. • ERRP: Error Passive Mode Interrupt Mask 0: ERRP interrupt is disabled. 1: ERRP interrupt is enabled. • BOFF: Bus Off Mode Interrupt Mask 0: BOFF interrupt is disabled. 1: BOFF interrupt is enabled. • SLEEP: Sleep Interrupt Mask 0: SLEEP interrupt is disabled. 1: SLEEP interrupt is enabled. • WAKEUP: Wakeup Interrupt Mask 0: WAKEUP interrupt is disabled. 1: WAKEUP interrupt is enabled. • TOVF: Timer Overflow Interrupt Mask 0: TOVF interrupt is disabled. 1: TOVF interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1466 • TSTP: Timestamp Interrupt Mask 0: TSTP interrupt is disabled. 1: TSTP interrupt is enabled. • CERR: CRC Error Interrupt Mask 0: CRC Error interrupt is disabled. 1: CRC Error interrupt is enabled. • SERR: Stuffing Error Interrupt Mask 0: Bit Stuffing Error interrupt is disabled. 1: Bit Stuffing Error interrupt is enabled. • AERR: Acknowledgment Error Interrupt Mask 0: Acknowledgment Error interrupt is disabled. 1: Acknowledgment Error interrupt is enabled. • FERR: Form Error Interrupt Mask 0: Form Error interrupt is disabled. 1: Form Error interrupt is enabled. • BERR: Bit Error Interrupt Mask 0: Bit Error interrupt is disabled. 1: Bit Error interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1467 45.9.5 CAN Status Register Name: CAN_SR Address: 0xF000C010 (0), 0xF8010010 (1) Access: Read-only 31 OVLSY 23 TSTP 15 – 7 MB7 30 TBSY 22 TOVF 14 – 6 MB6 29 RBSY 21 WAKEUP 13 – 5 MB5 28 BERR 20 SLEEP 12 – 4 MB4 27 FERR 19 BOFF 11 – 3 MB3 26 AERR 18 ERRP 10 – 2 MB2 25 SERR 17 WARN 9 – 1 MB1 24 CERR 16 ERRA 8 – 0 MB0 • MBx: Mailbox x Event 0: No event occurred on Mailbox x. 1: An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx. • ERRA: Error Active Mode 0: CAN controller has not reached Error Active Mode since the last read of CAN_SR. 1: CAN controller has reached Error Active Mode since the last read of CAN_SR. This flag is automatically cleared by reading CAN_SR. This flag is set depending on TEC and REC counter values. It is set when a node is neither in Error Passive Mode nor in Bus Off Mode. • WARN: Warning Limit 0: CAN controller Warning Limit has not been reached since the last read of CAN_SR. 1: CAN controller Warning Limit has been reached since the last read of CAN_SR. This flag is automatically cleared by reading CAN_SR. This flag is set depending on TEC and REC counter values. It is set when at least one of the counter values has reached a value greater or equal to 96. • ERRP: Error Passive Mode 0: CAN controller has not reached Error Passive Mode since the last read of CAN_SR. 1: CAN controller has reached Error Passive Mode since the last read of CAN_SR. This flag is set depending on TEC and REC counters values. This flag is automatically cleared by reading CAN_SR. A node is in error passive state when TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal). • BOFF: Bus Off Mode 0: CAN controller has not reached Bus Off Mode. 1: CAN controller has reached Bus Off Mode since the last read of CAN_SR. This flag is automatically cleared by reading CAN_SR. This flag is set depending on TEC counter value. A node is in bus off state when TEC counter is greater or equal to 256 (decimal). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1468 • SLEEP: CAN controller in Low power Mode 0: CAN controller is not in low power mode. 1: CAN controller is in low power mode. This flag is automatically reset when Low power mode is disabled • WAKEUP: CAN controller is not in Low power Mode 0: CAN controller is in low power mode. 1: CAN controller is not in low power mode. When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN Controller enters Low Power mode. • TOVF: Timer Overflow 0: The timer has not rolled-over FFFFh to 0000h. 1: The timer rolls-over FFFFh to 0000h. This flag is automatically cleared by reading CAN_SR. • TSTP: Timestamp 0: No bus activity has been detected. 1: A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR). This flag is automatically cleared by reading the CAN_SR. • CERR: Mailbox CRC Error 0: No CRC error occurred during a previous transfer. 1: A CRC error occurred during a previous transfer. A CRC error has been detected during last reception. This flag is automatically cleared by reading CAN_SR. • SERR: Mailbox Stuffing Error 0: No stuffing error occurred during a previous transfer. 1: A stuffing error occurred during a previous transfer. A form error results from the detection of more than five consecutive bit with the same polarity. This flag is automatically cleared by reading CAN_SR. • AERR: Acknowledgment Error 0: No acknowledgment error occurred during a previous transfer. 1: An acknowledgment error occurred during a previous transfer. An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. This flag is automatically cleared by reading CAN_SR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1469 • FERR: Form Error 0: No form error occurred during a previous transfer 1: A form error occurred during a previous transfer A form error results from violations on one or more of the fixed form of the following bit fields: – CRC delimiter – ACK delimiter – End of frame – Error delimiter – Overload delimiter This flag is automatically cleared by reading CAN_SR. • BERR: Bit Error 0: No bit error occurred during a previous transfer. 1: A bit error occurred during a previous transfer. A bit error is set when the bit value monitored on the line is different from the bit value sent. This flag is automatically cleared by reading CAN_SR. • RBSY: Receiver busy 0: CAN receiver is not receiving a frame. 1: CAN receiver is receiving a frame. Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving. • TBSY: Transmitter busy 0: CAN transmitter is not transmitting a frame. 1: CAN transmitter is transmitting a frame. Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting. • OVLSY: Overload busy 0: CAN transmitter is not transmitting an overload frame. 1: CAN transmitter is transmitting a overload frame. It is automatically reset when the bus is not transmitting an overload frame. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1470 45.9.6 CAN Baudrate Register Name: CAN_BR Address: 0xF000C014 (0), 0xF8010014 (1) Access: Read-write 31 – 23 – 15 – 7 – 30 – 22 29 – 21 14 – 6 13 28 – 20 12 SJW 5 PHASE1 4 27 – 19 BRP 11 – 3 – 26 – 18 25 – 17 24 SMP 16 10 9 PROPAG 1 PHASE2 8 2 0 This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. Any modification on one of the fields of the CAN_BR must be done while CAN module is disabled. To compute the different bit timings, please refer to the Section 45.7.4.1 “CAN Bit Timing Configuration” on page 1439. • PHASE2: Phase 2 segment This phase is used to compensate the edge phase error. t PHS2 = t CSC × ( PHASE2 + 1 ) Warning: PHASE2 value must be different from 0. • PHASE1: Phase 1 segment This phase is used to compensate for edge phase error. t PHS1 = t CSC × ( PHASE1 + 1 ) • PROPAG: Programming time segment This part of the bit time is used to compensate for the physical delay times within the network. t PRS = t CSC × ( PROPAG + 1 ) • SJW: Re-synchronization jump width To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization. t SJW = t CSC × ( SJW + 1 ) • BRP: Baudrate Prescaler. This field allows user to program the period of the CAN system clock to determine the individual bit timing. t CSC = ( BRP + 1 ) ⁄ MCK The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized. • SMP: Sampling Mode 0 (ONCE): The incoming bit stream is sampled once at sample point. 1 (THREE): The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. SMP Sampling Mode is automatically disabled if BRP = 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1471 45.9.7 CAN Timer Register Name: CAN_TIM Address: 0xF000C018 (0), 0xF8010018 (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 3 2 1 0 TIMER 7 6 5 4 TIMER • TIMER: Timer This field represents the internal CAN controller 16-bit timer value. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1472 45.9.8 CAN Timestamp Register Name: CAN_TIMESTP Address: 0xF000C01C (0), 0xF801001C (1) Access: Read-only 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 7 6 5 28 27 – – 20 19 – – 12 11 MTIMESTAMP 4 3 MTIMESTAMP 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 2 1 0 • MTIMESTAMP: Timestamp This field carries the value of the internal CAN controller 16-bit timer value at the start or end of frame. If the TEOF bit is cleared in the CAN_MR, the internal Timer Counter value is captured in the MTIMESTAMP field at each start of frame else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in the CAN_SR. If the TSTP mask in the CAN_IMR is set, an interrupt is generated while TSTP flag is set in the CAN_SR. This flag is cleared by reading the CAN_SR. Note: The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the CAN_MR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1473 45.9.9 CAN Error Counter Register Name: CAN_ECR Address: 0xF000C020 (0), 0xF8010020 (1) Access: Read-only 31 – 23 30 – 22 29 – 21 28 – 20 15 – 7 14 – 6 13 – 5 12 – 4 27 – 19 26 – 18 25 – 17 24 TEC 16 11 – 3 10 – 2 9 – 1 8 – 0 TEC REC • REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG. When a receiver detects a dominant bit as the first bit after sending an ERROR FLAG, REC is increased by 8. When a receiver detects a BIT ERROR while sending an ACTIVE ERROR FLAG, REC is increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8. After successful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127. • TEC: Transmit Error Counter When a transmitter sends an ERROR FLAG, TEC is increased by 8 except when – the transmitter is error passive and detects an ACKNOWLEDGMENT ERROR because of not detecting a dominant ACK and does not detect a dominant bit while sending its PASSIVE ERROR FLAG. – the transmitter sends an ERROR FLAG because a STUFF ERROR occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant. When a transmitter detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG, the TEC will be increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8. After a successful transmission the TEC is decreased by 1 unless it was already 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1474 45.9.10 CAN Transfer Command Register Name: CAN_TCR Address: 0xF000C024 (0), 0xF8010024 (1) Access: Write-only 31 TIMRST 23 – 15 – 7 MB7 30 – 22 – 14 – 6 MB6 29 – 21 – 13 – 5 MB5 28 – 20 – 12 – 4 MB4 27 – 19 – 11 – 3 MB3 26 – 18 – 10 – 2 MB2 25 – 17 – 9 – 1 MB1 24 – 16 – 8 – 0 MB0 This register initializes several transfer requests at the same time. • MBx: Transfer Request for Mailbox x Mailbox Object Type Description Receive It receives the next message. Receive with overwrite This triggers a new reception. Transmit Sends data prepared in the mailbox as soon as possible. Consumer Sends a remote frame. Producer Sends data prepared in the mailbox after receiving a remote frame from a consumer. This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., MB0 will be transferred before MB1). • TIMRST: Timer Reset Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1475 45.9.11 CAN Abort Command Register Name: CAN_ACR Address: 0xF000C028 (0), 0xF8010028 (1) Access: Write-only 31 – 23 – 15 – 7 MB7 30 – 22 – 14 – 6 MB6 29 – 21 – 13 – 5 MB5 28 – 20 – 12 – 4 MB4 27 – 19 – 11 – 3 MB3 26 – 18 – 10 – 2 MB2 25 – 17 – 9 – 1 MB1 24 – 16 – 8 – 0 MB0 This register initializes several abort requests at the same time. • MBx: Abort Request for Mailbox x Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Cancels transfer request if the message has not been transmitted to the CAN transceiver. Consumer Cancels the current transfer before the remote frame has been sent. Producer Cancels the current transfer. The next remote frame is not serviced. It is possible to set the MACR field (in the CAN_MCRx) for each mailbox. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1476 45.9.12 CAN Write Protection Mode Register Name: CAN_WPMR Address: 0xF000C0E4 (0), 0xF80100E4 (1) Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protection Enable 0: The Write Protection is Disabled if WPKEY is written with 0x43414E (“CAN” written in ASCII) 1: The Write Protection is Enabled if WPKEY is written with0x43414E (“CAN” written in ASCII) Protects the registers: Section 45.9.1 “CAN Mode Register” on page 1460 Section 45.9.6 “CAN Baudrate Register” on page 1471 Section 45.9.14 “CAN Message Mode Register” on page 1479 Section 45.9.15 “CAN Message Acceptance Mask Register” on page 1480 Section 45.9.16 “CAN Message ID Register” on page 1481 • WPKEY: SPI Write Protection Key Password. Value 0x43414E Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1477 45.9.13 CAN Write Protection Status Register Name: CAN_WPSR Address: 0xF000C0E8 (0), 0xF80100E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protection Violation Status 0: No Write Protect Violation has occurred since the last read of the CAN_WPSR. 1: A Write Protect Violation has occurred since the last read of the CAN_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protection Violation Source This Field indicates the offset of the register concerned by the violation SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1478 45.9.14 CAN Message Mode Register Name: CAN_MMRx [x=0..7] Address: 0xF000C200 (0)[0], 0xF000C220 (0)[1], 0xF000C240 (0)[2], 0xF000C260 (0)[3], 0xF000C280 (0)[4], 0xF000C2A0 (0)[5], 0xF000C2C0 (0)[6], 0xF000C2E0 (0)[7], 0xF8010200 (1)[0], 0xF8010220 (1)[1], 0xF8010240 (1)[2], 0xF8010260 (1)[3], 0xF8010280 (1)[4], 0xF80102A0 (1)[5], 0xF80102C0 (1)[6], 0xF80102E0 (1)[7] Access: Read-write 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 7 6 5 4 27 – 19 26 25 24 18 MOT 17 16 PRIOR 11 10 9 8 3 2 1 0 MTIMEMARK MTIMEMARK This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. • MTIMEMARK: Mailbox Timemark This field is active in Time Triggered Mode. Transmit operations are allowed when the internal timer counter reaches the Mailbox Timemark. See “Transmitting within a Time Window” on page 1456. In Timestamp Mode, MTIMEMARK is set to 0. • PRIOR: Mailbox Priority This field has no effect in receive and receive with overwrite modes. In these modes, the mailbox with the lowest number is serviced first. When several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 is serviced before MBx 15 if they have the same priority). • MOT: Mailbox Object Type This field allows the user to define the type of the mailbox. All mailboxes are independently configurable. Five different types are possible for each mailbox: Value Name Description 0 MB_DISABLED Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. 1 MB_RX Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. 2 MB_RX_OVERWRITE Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. 3 MB_TX Transmit mailbox. Mailbox is configured for transmission. 4 MB_CONSUMER Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. 5 MB_PRODUCER Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. 6 – Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1479 45.9.15 CAN Message Acceptance Mask Register Name: CAN_MAMx [x=0..7] Address: 0xF000C204 (0)[0], 0xF000C224 (0)[1], 0xF000C244 (0)[2], 0xF000C264 (0)[3], 0xF000C284 (0)[4], 0xF000C2A4 (0)[5], 0xF000C2C4 (0)[6], 0xF000C2E4 (0)[7], 0xF8010204 (1)[0], 0xF8010224 (1)[1], 0xF8010244 (1)[2], 0xF8010264 (1)[3], 0xF8010284 (1)[4], 0xF80102A4 (1)[5], 0xF80102C4 (1)[6], 0xF80102E4 (1)[7] Access: Read-write 31 – 23 30 – 22 29 MIDE 21 28 27 20 19 26 MIDvA 18 25 24 17 MIDvA 16 MIDvB 15 14 13 12 7 6 5 4 11 10 9 8 3 2 1 0 MIDvB MIDvB This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers. • MIDvB: Complementary bits for identifier in extended frame mode Acceptance mask for corresponding field of the message IDvB register of the mailbox. • MIDvA: Identifier for standard frame mode Acceptance mask for corresponding field of the message IDvA register of the mailbox. • MIDE: Identifier Version 0: Compares IDvA from the received frame with the CAN_MIDx register masked with CAN_MAMx register. 1: Compares IDvA and IDvB from the received frame with the CAN_MIDx register masked with CAN_MAMx register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1480 45.9.16 CAN Message ID Register Name: CAN_MIDx [x=0..7] Address: 0xF000C208 (0)[0], 0xF000C228 (0)[1], 0xF000C248 (0)[2], 0xF000C268 (0)[3], 0xF000C288 (0)[4], 0xF000C2A8 (0)[5], 0xF000C2C8 (0)[6], 0xF000C2E8 (0)[7], 0xF8010208 (1)[0], 0xF8010228 (1)[1], 0xF8010248 (1)[2], 0xF8010268 (1)[3], 0xF8010288 (1)[4], 0xF80102A8 (1)[5], 0xF80102C8 (1)[6], 0xF80102E8 (1)[7] Access: Read-write 31 – 23 30 – 22 29 MIDE 21 28 27 20 19 26 MIDvA 18 25 24 17 MIDvA 16 MIDvB 15 14 13 12 7 6 5 4 11 10 9 8 3 2 1 0 MIDvB MIDvB This register can only be written if the WPEN bit is cleared in ”CAN Write Protection Mode Register”. To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers. • MIDvB: Complementary bits for identifier in extended frame mode If MIDE is cleared, MIDvB value is 0. • MIDE: Identifier Version This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version 2.0 Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages. • MIDvA: Identifier for standard frame mode SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1481 45.9.17 CAN Message Family ID Register Name: CAN_MFIDx [x=0..7] Address: 0xF000C20C (0)[0], 0xF000C22C (0)[1], 0xF000C24C (0)[2], 0xF000C26C (0)[3], 0xF000C28C (0)[4], 0xF000C2AC (0)[5], 0xF000C2CC (0)[6], 0xF000C2EC (0)[7], 0xF801020C (1)[0], 0xF801022C (1)[1], 0xF801024C (1)[2], 0xF801026C (1)[3], 0xF801028C (1)[4], 0xF80102AC (1)[5], 0xF80102CC (1)[6], 0xF80102EC (1)[7] Access: Read-only 31 – 23 30 – 22 29 – 21 28 27 20 25 24 19 26 MFID 18 17 16 11 10 9 8 3 2 1 0 MFID 15 14 13 12 7 6 5 4 MFID MFID • MFID: Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below. As an example: CAN_MIDx = 0x305A4321 CAN_MAMx = 0x3FF0F0FF CAN_MFIDx = 0x000000A3 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1482 45.9.18 CAN Message Status Register Name: CAN_MSRx [x=0..7] Address: 0xF000C210 (0)[0], 0xF000C230 (0)[1], 0xF000C250 (0)[2], 0xF000C270 (0)[3], 0xF000C290 (0)[4], 0xF000C2B0 (0)[5], 0xF000C2D0 (0)[6], 0xF000C2F0 (0)[7], 0xF8010210 (1)[0], 0xF8010230 (1)[1], 0xF8010250 (1)[2], 0xF8010270 (1)[3], 0xF8010290 (1)[4], 0xF80102B0 (1)[5], 0xF80102D0 (1)[6], 0xF80102F0 (1)[7] Access: Read-only 31 – 23 MRDY 15 30 – 22 MABT 14 29 – 21 – 13 7 6 5 28 27 – – 20 19 MRTR 12 11 MTIMESTAMP 4 3 MTIMESTAMP 26 – 18 25 – 17 24 MMI 16 10 9 8 2 1 0 MDLC These register fields are updated each time a message transfer is received or aborted. MMI is cleared by reading the CAN_MSRx. MRDY, MABT are cleared by writing MTCR or MACR in the CAN_MCRx. Warning: MRTR and MDLC state depends partly on the mailbox object type. • MTIMESTAMP: Timer value This field is updated only when time-triggered operations are disabled (TTM cleared in CAN_MR). If the TEOF field in the CAN_MR is cleared, TIMESTAMP is the internal timer value at the start of frame of the last message received or sent by the mailbox. If the TEOF field in the CAN_MR is set, TIMESTAMP is the internal timer value at the end of frame of the last message received or sent by the mailbox. In Time Triggered Mode, MTIMESTAMP is set to 0. • MDLC: Mailbox Data Length Code Mailbox Object Type Description Receive Length of the first mailbox message received Receive with overwrite Length of the last mailbox message received Transmit No action Consumer Length of the mailbox message received Producer Length of the mailbox message to be sent after the remote frame reception • MRTR: Mailbox Remote Transmission Request Mailbox Object Type Description Receive The first frame received has the RTR bit set. Receive with overwrite The last frame received has the RTR bit set. Transmit Reserved Consumer Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1. Producer Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1483 • MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0: Previous transfer is not aborted. 1: Previous transfer has been aborted. This flag is cleared by writing to CAN_MCRx Mailbox Object Type Description Receive Reserved Receive with overwrite Reserved Transmit Previous transfer has been aborted Consumer The remote frame transfer request has been aborted. Producer The response to the remote frame transfer has been aborted. • MRDY: Mailbox Ready An interrupt is triggered when MRDY is set. 0: Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx. 1: Mailbox data registers can be read/written by the software application. This flag is cleared by writing to CAN_MCRx. Mailbox Object Type Description Receive At least one message has been received since the last mailbox transfer order. Data from the first frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. Receive with overwrite At least one frame has been received since the last mailbox transfer order. Data from the last frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. Transmit Consumer Mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1. At least one message has been received since the last mailbox transfer order. Data from the first message received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. Producer A remote frame has been received, mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1. • MMI: Mailbox Message Ignored 0: No message has been ignored during the previous transfer 1: At least one message has been ignored during the previous transfer Cleared by reading the CAN_MSRx. Mailbox Object Type Description Receive Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1484 Mailbox Object Type Description Receive with overwrite Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost. Transmit Reserved Consumer A remote frame has been sent by the mailbox but several messages have been received. The first one is available in the mailbox data register. Others have been ignored. Another mailbox with a lower priority may have accepted the message. Producer A remote frame has been received, but no data are available to be sent. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1485 45.9.19 CAN Message Data Low Register Name: CAN_MDLx [x=0..7] Address: 0xF000C214 (0)[0], 0xF000C234 (0)[1], 0xF000C254 (0)[2], 0xF000C274 (0)[3], 0xF000C294 (0)[4], 0xF000C2B4 (0)[5], 0xF000C2D4 (0)[6], 0xF000C2F4 (0)[7], 0xF8010214 (1)[0], 0xF8010234 (1)[1], 0xF8010254 (1)[2], 0xF8010274 (1)[3], 0xF8010294 (1)[4], 0xF80102B4 (1)[5], 0xF80102D4 (1)[6], 0xF80102F4 (1)[7] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MDL 23 22 21 20 MDL 15 14 13 12 MDL 7 6 5 4 MDL • MDL: Message Data Low Value When MRDY field is set in the CAN_MSRx, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDL value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDL value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx is set. Bytes are received/sent on the bus in the following order: 1. CAN_MDL[7:0] 2. CAN_MDL[15:8] 3. CAN_MDL[23:16] 4. CAN_MDL[31:24] 5. CAN_MDH[7:0] 6. CAN_MDH[15:8] 7. CAN_MDH[23:16] 8. CAN_MDH[31:24] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1486 45.9.20 CAN Message Data High Register Name: CAN_MDHx [x=0..7] Address: 0xF000C218 (0)[0], 0xF000C238 (0)[1], 0xF000C258 (0)[2], 0xF000C278 (0)[3], 0xF000C298 (0)[4], 0xF000C2B8 (0)[5], 0xF000C2D8 (0)[6], 0xF000C2F8 (0)[7], 0xF8010218 (1)[0], 0xF8010238 (1)[1], 0xF8010258 (1)[2], 0xF8010278 (1)[3], 0xF8010298 (1)[4], 0xF80102B8 (1)[5], 0xF80102D8 (1)[6], 0xF80102F8 (1)[7] Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MDH 23 22 21 20 MDH 15 14 13 12 MDH 7 6 5 4 MDH • MDH: Message Data High Value When MRDY field is set in the CAN_MSRx, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDH value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx is set. Bytes are received/sent on the bus in the following order: 1. CAN_MDL[7:0] 2. CAN_MDL[15:8] 3. CAN_MDL[23:16] 4. CAN_MDL[31:24] 5. CAN_MDH[7:0] 6. CAN_MDH[15:8] 7. CAN_MDH[23:16] 8. CAN_MDH[31:24] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1487 45.9.21 CAN Message Control Register Name: CAN_MCRx [x=0..7] Address: 0xF000C21C (0)[0], 0xF000C23C (0)[1], 0xF000C25C (0)[2], 0xF000C27C (0)[3], 0xF000C29C (0)[4], 0xF000C2BC (0)[5], 0xF000C2DC (0)[6], 0xF000C2FC (0)[7], 0xF801021C (1)[0], 0xF801023C (1)[1], 0xF801025C (1)[2], 0xF801027C (1)[3], 0xF801029C (1)[4], 0xF80102BC (1)[5], 0xF80102DC (1)[6], 0xF80102FC (1)[7] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 MTCR 22 MACR 21 – 20 MRTR 19 18 15 – 14 13 – 12 11 – 7 – 6 5 – 4 3 – – – – – 25 24 – – 17 16 10 9 – – 8 – 2 – 1 0 – – MDLC • MDLC: Mailbox Data Length Code Mailbox Object Type Description Receive No action. Receive with overwrite No action. Transmit Length of the mailbox message. Consumer No action. Producer Length of the mailbox message to be sent after the remote frame reception. • MRTR: Mailbox Remote Transmission Request Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Set the RTR bit in the sent frame Consumer No action, the RTR bit in the sent frame is set automatically Producer No action Consumer situations can be handled automatically by setting the mailbox object type in Consumer. This requires only one mailbox. It can also be handled using two mailboxes, one in reception, the other in transmission. The MRTR and the MTCR bits must be set in the same time. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1488 • MACR: Abort Request for Mailbox x Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Cancels transfer request if the message has not been transmitted to the CAN transceiver. Consumer Cancels the current transfer before the remote frame has been sent. Producer Cancels the current transfer. The next remote frame will not be serviced. It is possible to set the MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR. • MTCR: Mailbox Transfer Command Mailbox Object Type Receive Receive with overwrite Transmit Description Allows the reception of the next message. Triggers a new reception. Sends data prepared in the mailbox as soon as possible. Consumer Sends a remote transmission frame. Producer Sends data prepared in the mailbox after receiving a remote frame from a Consumer. This flag clears the MRDY and MABT flags in the CAN_MSRx. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn. The mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 will be serviced before MBx 15 if they have the same priority). It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1489 46. Software Modem Device (SMD) 46.1 Description The Software Modem Device (SMD) is a block for communication via a modem's Digital Isolation Barrier (DIB) with a complementary Line Side Device (LSD). SMD and LSD are two parts of the “Transformer only” solution. The transformer is the only component connecting SMD and LSD and is used for power, clock and data transfers. Power and clock are supplied by the SMD and consumed by the LSD. The data flow is bidirectional. The data transfer is based on pulse width modulation for transmission from the SMD to the LSD, and for receiving from the LSD. There are two channels embedded into the protocol of the DIB link:  data channel  control channel Each channel is bidirectional. The data channel is used to transfer digitized signal samples at a constant rate of 16 bits at 16 kHz. The control channel is used to communicate with control registers of the LSD at a maximum rate of 8 bits at 16 kHz. The SMD performs all protocol-related data conversion for transmission and received data interpretation in both data and control channels of the link. The SMD incorporates both RX and TX FIFOs, available through the DMAC interface. Each FIFO is able to hold eight 32bit words (equivalent to 16 modem data samples). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1490 46.2 Embedded Characteristics    V.90  V.34  V.32bis, V.32, V.22bis, V.22, V.23, V.21  V.23 reverse, V.23 half-duplex  Bell 212A/Bell 103  V.29 FastPOS  V.22bis fast connect  V.80 Synchronous Access Mode Data compression and error correction  V.44 data compression (V.92 model)  V.42bis and MNP 5 data compression  V.42 LAPM and MNP 2-4 error correction  EIA/TIA 578 Class 1 and T.31 Class 1.0  Call Waiting (CW) detection and Type II Caller ID decoding during data mode  Type I Caller ID (CID) decoding  Sixty-three embedded and upgradable country profiles  Embedded AT commands  SmartDAA  46.3 Modulations and protocols  Extension pick-up detection  Digital line protection  Line reversal detection  Line-in-use detection  Remote hang-up detection Worldwide compliance Block Diagram Figure 46-1. Software Modem Device Block Diagram SMD Controller SMD Core Byte Parallel Interface CPU Interrupt AHB Control Channel Logic Control/Status Registers AHB Wrapper FIFO Interface 8x32 (2) DMA Parallel Interface DMA Channel Logic Ring Detection and Pulse Dialing Machines (masters) FIFO 2x16 DIB Interface Circuitry DIB Pads X X FIFO 2x16 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1491 46.4 Software Modem Device (SMD) User Interface The SMD presents a number of registers through the AHB interface for software control and status functions. Table 46-1. Register Mapping 0x0C SMD Drive register SMD_DRIVE Read-write 0x00000002 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1492 46.4.1 SMD Drive Register Name: SMD_DRIVE Address: 0x0040000C Access: Read-write Reset: 0x00000002 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 PWRCLKP_P V 2 PWRCLKP_P V2 1 DC_PWRCL KPN 0 PWRCLKP_PCS PWRCLKN_PCS2 MIE • PWRCLKP_PCS: PWRCLKP Pin Control Select. When DC_PWRCLKPN is a 1, the usage of PWRCLKP_PCS bits for direct control of PWRCLKP pin is enabled as follows: X1 = High impedance on PWRCLKP pin. 00 = Drive low on PWRCLKP pin. 10 = Drive high on PWRCLKP pin. When DC_PWRCLKPN is a 0, the protocol logic controls PWRCLKP pin. If PWRCLKPN_FS bit is a 1, the above information is applied to PWRCLKN pin because of swapping with PWRCLKP. • PWRCLKN_PCS2: PWRCLKN Pin Control Select. When DC_PWRCLKPN is a 1, the usage of PWRCLKN_PCS2 bits for direct control of PWRCLKN pin is enabled as follows: X1 = High impedance on PWRCLKN pin. 00 = Drive low on PWRCLKN pin. 10 = Drive high on PWRCLKN pin. When DC_PWRCLKPN is a 0, the protocol logic controls PWRCLKN pin. If PWRCLKPN_FS bit is a 1, the above information is applied to PWRCLKP pin because of swapping with PWRCLKN. • PWRCLKP_PV: PWRCLKP Pin Value. This bit reflects the PWRCLKP pin value if PWRCLKPN_FS = 0, or the PWRCLKN pin value if PWRCLKPN_FS = 1 (because of swapping with PWRCLKP). • PWRCLKP_PV2: PWRCLKP Pin Value. This bit reflects the PWRCLKN pin value if PWRCLKPN_FS = 0, or the PWRCLKP pin value if PWRCLKPN_FS = 1 (because of swapping with PWRCLKN). • DC_PWRCLKPN: Direct Control of PWRCLKP, PWRCLKN Pins Enable. 0 = Enables protocol logic control of PWRCLKP, PWRCLKN pins. 1 = Enables the use of PWRCLKP_PCS and PWRCLKN_PCS2 bits for direct control of PWRCLKP, PWRCLKN pins making them general purpose input/outputs (GPIOs). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1493 • MIE: MADCVS Interrupt Enable. 0 = Disables smd_irq interrupt generation for MADCVS flag. 1 = Enables smd_irq interrupt generation for MADCVS flag. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1494 47. Timer Counter (TC) 47.1 Description The Timer Counter (TC) includes 6 identical 32-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter (TC) embeds a quadrature decoder logic connected in front of the timers and driven by TIOA0, TIOB0 and TIOB1 inputs. When enabled, the quadrature decoder performs the input lines filtering, decoding of quadrature signals and connects to the timers/counters in order to read the position and speed of the motor through the user interface. The Timer Counter block has two global registers which act upon all TC channels. The Block Control Register allows the channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 47-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2. Table 47-1. Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 div2 TIMER_CLOCK2 div8 TIMER_CLOCK3 div32 TIMER_CLOCK4 div128 TIMER_CLOCK5(1) slow_clock Note: 47.2 1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master Clock Register), TIMER_CLOCK5 input is equivalent to Master Clock. Embedded Characteristics  Provides 6 32-bit Timer Counter channels  Wide range of functions including:   Frequency measurement  Event counting  Interval measurement  Pulse generation  Delay timing  Pulse Width Modulation  Up/down capabilities  Quadrature decoder logic  2-bit gray up/down count for stepper motor Each channel is user-configurable and contains:  Three external clock inputs  Five Internal clock inputs  Two multi-purpose input/output signals acting as trigger event SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1495 47.3  Internal interrupt signal  Two global registers that act on all TC channels  Read of the Capture registers by the DMAC  Configuration registers can be write protected Block Diagram Figure 47-1. Timer Counter Block Diagram Parallel I/O Controller TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIOA1 TIOA2 TIMER_CLOCK3 TCLK1 TIMER_CLOCK4 XC0 XC1 Timer/Counter Channel 0 TIOA TIOA0 TIOB0 TIOA0 TIOB TCLK2 TIOB0 XC2 TIMER_CLOCK5 TC0XC0S SYNC TCLK0 TCLK1 TCLK2 INT0 TCLK0 TCLK1 XC0 TIOA0 XC1 TIOA2 XC2 Timer/Counter Channel 1 TIOA TIOA1 TIOB1 TIOA1 TIOB TCLK2 TIOB1 SYNC TC1XC1S TCLK0 XC0 TCLK1 XC1 Timer/Counter Channel 2 INT1 TIOA TIOA2 TIOB2 TIOA2 TIOB TCLK2 XC2 TIOA0 TIOA1 TC2XC2S TIOB2 SYNC INT2 Timer Counter Interrupt Controller Table 47-2. Signal Name Description Block/Channel Signal Name XC0, XC1, XC2 Channel Signal Description External Clock Inputs TIOA Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT SYNC Interrupt Signal Output (internal signal) Synchronization Input Signal (from configuration register) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1496 47.4 Pin Name List Table 47-3. TC pin list 47.5 Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O Product Dependencies 47.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 47-4. I/O Lines Instance Signal I/O Line Peripheral TC0 TCLK0 PD7 B TC0 TCLK1 PC14 B TC0 TCLK2 PE29 B TC0 TIOA0 PD5 B TC0 TIOA1 PC12 B TC0 TIOA2 PE27 B TC0 TIOB0 PD6 B TC0 TIOB1 PC13 B TC0 TIOB2 PE28 B TC1 TCLK3 PC2 B TC1 TCLK4 PC5 B TC1 TCLK5 PC8 B TC1 TIOA3 PC0 B TC1 TIOA4 PC3 B TC1 TIOA5 PC6 B TC1 TIOB3 PC1 B TC1 TIOB4 PC4 B TC1 TIOB5 PC7 B 47.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. 47.5.3 Interrupt The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires programming the IC before configuring the TC. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1497 47.6 Functional Description 47.6.1 TC Description The 6 channels of the Timer Counter are independent and identical in operation except when quadrature decoder is enabled. The registers for channel programming are listed in Table 47-5 on page 1517. 47.6.2 32-bit Counter Each channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in the TC Status Register (TC_SR) is set. The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 47.6.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC Block Mode Register (TC_BMR). See Figure 47-2 “Clock Chaining Selection”. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 • External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR). The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the TC_CMR defines this signal (none, XC0, XC1, XC2). See Figure 47-3 “Clock Selection”. Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1498 Figure 47-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 47-3. Clock Selection TCCLKS CLKI TIMER_CLOCK1 Synchronous Edge Detection TIMER_CLOCK2 TIMER_CLOCK3 Selected Clock TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 MCK BURST 1 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1499 47.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 47-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC Channel Control Register (TC_CCR). In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in the TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the TC_CCR can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the TC_SR. • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 47-4. Clock Control Selected Clock Trigger CLKSTA Q Q S CLKEN CLKDIS S R R Counter Clock Stop Event Disable Event 47.6.5 TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 47.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. The following triggers are common to both modes: SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1500 • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in the TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting bit ENETRG in the TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. 47.6.7 Capture Operating Mode This mode is entered by clearing the WAVE bit in the TC_CMR. Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 47-6shows the configuration of the TC channel when programmed in Capture Mode. 47.6.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA field in the TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB field defines the TIOA selected edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS bit) in the TC_SR. In this case, the old value is overwritten. When DMA is used, the RAB register address must be configured as source address of the transfer. The RAB register provides the next unread value from Register A and Register B. It may be read by the DMA after a request has been triggered upon loading Register A or Register B. 47.6.9 Transfer with DMAC The DMAC can only perform access from timer to system memory. Figure 47-5 “Example of Transfer with DMAC” illustrates how the RA and RB registers can be loaded in the system memory without CPU intervention. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1501 Figure 47-5. Example of Transfer with DMAC ETRGEDG = 1, LDRA = 1, LDRB = 2, ABETRG = 0, TIOB TIOA RA RB Peripheral trigger Transfer to System Memory RA RB RA RB T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (tmin = 8 MCK) ETRGEDG = 3, LDRA = 3, LDRB = 0, ABETRG = 0 TIOB TIOA RA Peripheral trigger Transfer to System Memory RA RA RA RA T1 T2 T3 T4 T1,T2,T3,T4 = System Bus load dependent (tmin = 8 MCK) 47.6.10 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in the TC_CMR selects TIOA or TIOB input signal as an external trigger . The External Trigger Edge Selection parameter (ETRGEDG field in TC_CMR) defines the edge (rising, falling, or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1502 MTIOA MTIOB 1 ABETRG CLKI If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel BURST MCK Synchronous Edge Detection R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT Figure 47-6. Capture Mode CPCS LOVRS LDRBS ETRGS LDRAS TC1_IMR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1503 47.6.11 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 47-7 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 47.6.12 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1504 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST ENETRG CLKI Timer/Counter Channel Edge Detector EEVTEDG SWTRG MCK Synchronous Edge Detection Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB MTIOB TIOA MTIOA Figure 47-7. Waveform Mode CPCS CPBS COVFS TC1_SR ETRGS TC1_IMR SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1505 47.6.12.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 47-8. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 47-9. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 47-8. WAVSEL = 00 without trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 47-9. WAVSEL= 00 with Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1506 47.6.12.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 47-10. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 47-11. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 47-10.WAVSEL = 10 without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 47-11.WAVSEL = 10 with Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1507 47.6.12.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 47-12. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 47-13. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 47-12.WAVSEL = 01 without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 47-13.WAVSEL = 01 with Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Waveform Examples Time TIOB TIOA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1508 47.6.12.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 47-14. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 47-15. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 47-14.WAVSEL = 11 without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 47-15.WAVSEL = 11 with Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples Time TIOB TIOA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1509 47.6.13 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in the TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 47.6.14 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 47.6.15 Quadrature Decoder Logic 47.6.15.1 Description The quadrature decoder logic is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of channel 0 and 1. Channel 2 can be used as a time base in case of speed measurement requirements (refer to Figure 47-16 “Predefined Connection of the Quadrature Decoder with Timer Counters”). When writing a 0 to bit QDEN of the TC_BMR, the quadrature decoder logic is totally transparent. TIOA0 and TIOB0 are to be driven by the two dedicated quadrature signals from a rotary sensor mounted on the shaft of the off-chip motor. A third signal from the rotary sensor can be processed through pin TIOB1 and is typically dedicated to be driven by an index signal if it is provided by the sensor. This signal is not required to decode the quadrature signals PHA, PHB. Field TCCLKS of TC_CMRx must be configured to select XC0 input (i.e., 0x101). Field TC0XC0S has no effect as soon as quadrature decoder is enabled. Either speed or position/revolution can be measured. Position channel 0 accumulates the edges of PHA, PHB input signals giving a high accuracy on motor position whereas channel 1 accumulates the index pulses of the sensor, therefore the number of rotations. Concatenation of both values provides a high level of precision on motion system position. In speed mode, position cannot be measured but revolution can be measured. Inputs from the rotary sensor can be filtered prior to down-stream processing. Accommodation of input polarity, phase definition and other factors are configurable. Interruptions can be generated on different events. A compare function (using TC_RC register) is available on channel 0 (speed/position) or channel 1 (rotation) and can generate an interrupt by means of the CPCS flag in the TC_SRx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1510 Figure 47-16.Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA0 QDEN PHEdges TIOA0 TIOB0 TIOB1 1 TIOB0 TIOB 1 XC0 XC0 PHA Speed/Position QDEN PHB IDX Timer/Counter Channel 0 TIOA Index 1 TIOB1 TIOB 1 XC0 Timer/Counter Channel 1 XC0 Rotation Direction Timer/Counter Channel 2 Speed Time Base 47.6.15.2 Input Pre-processing Input pre-processing consists of capabilities to take into account rotary sensor factors such as polarities and phase definition followed by configurable digital filtering. Each input can be negated and swapping PHA, PHB is also configurable. The MAXFILT field in the TC_BMR is used to configure a minimum duration for which the pulse is stated as valid. When the filter is active, pulses with a duration lower than MAXFILT +1 * tMCK ns are not passed to down-stream logic. Filters can be disabled using the FILTER bit in the TC_BMR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1511 Figure 47-17.Input Stage Input Pre-Processing MAXFILT SWAP 1 PHA Filter FILTER PHedge 1 TIOA0 Direction and Edge Detection INVA 1 PHB Filter 1 DIR Filter 1 IDX TIOB0 INVB 1 1 IDX TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interference. Or, simply if vibration occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the beginning of one of the reflective or magnetic bars on the rotary sensor disk is aligned with the light or magnetic (Hall) receiver cell of the rotary sensor. Any vibration can make the PHA, PHB signals toggle for a short duration. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1512 Figure 47-18.Filtering Examples MAXFILT=2 MCK particulate contamination PHA,B Filter Out Optical/Magnetic disk strips PHA PHB motor shaft stopped in such a position that rotary sensor cell is aligned with an edge of the disk rotation stop PHA PHB Edge area due to system vibration PHB Resulting PHA, PHB electrical waveforms PHA stop mechanical shock on system PHB vibration PHA, PHB electrical waveforms after filtering PHA PHB SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1513 47.6.15.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the two quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag. Any change in rotation direction is reported in theTC_QISR and can generate an interrupt. The direction change condition is reported as soon as two consecutive edges on a phase signal have sampled the same value on the other phase signal and there is an edge on the other signal. The two consecutive edges of one phase signal sampling the same value on other phase signal is not sufficient to declare a direction change, for the reason that particulate contamination may mask one or more reflective bars on the optical or magnetic disk of the sensor. (Refer to Figure 47-19 “Rotation Change Detection” for waveforms.) Figure 47-19.Rotation Change Detection Direction Change under normal conditions PHA change condition Report Time PHB DIR DIRCHG No direction change due to particulate contamination masking a reflective bar missing pulse PHA same phase PHB DIR spurious change condition (if detected in a simple way) DIRCHG The direction change detection is disabled when QDTRANS is set in the TC_BMR. In this case the DIR flag report must not be used. A quadrature error is also reported by the quadrature decoder logic via the QERR flag in the TC_QISR. This error is reported if the time difference between two edges on PHA, PHB is lower than a predefined value. This predefined value SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1514 is configurable and corresponds to (MAXFILT + 1) * tMCK ns. After being filtered there is no reason to have two edges closer than (MAXFILT + 1) * tMCK ns under normal mode of operation. Figure 47-20.Quadrature Error Detection MAXFILT = 2 MCK Abnormally formatted optical disk strips (theoretical view) PHA PHB strip edge inaccurary due to disk etching/printing process PHA PHB resulting PHA, PHB electrical waveforms PHA Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time. PHB duration < MAXFILT QERR MAXFILT must be tuned according to several factors such as the system clock frequency (MCK), type of rotary sensor and rotation speed to be achieved. 47.6.15.4 Position and Rotation Measurement When the POSEN bit is set in the TC_BMR, the motor axis position is processed on channel 0 (by means of the PHA, PHB edge detections) and the number of motor revolutions are recorded on channel 1 if the IDX signal is provided on the TIOB1 input. The position measurement can be read in the TC_CV0 register and the rotation measurement can be read in the TC_CV1 register. Channel 0 and 1 must be configured in capture mode (WAVE = 0 in TC_CMR0). In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0 register. Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word. The timer/counter channel 0 is cleared for each increment of IDX count value. Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels 0 and 1. The direction status is reported on TC_QISR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1515 47.6.15.5 Speed Measurement When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0. A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in waveform mode (WAVE bit set) in TC_CMR2 register. The WAVSEL field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOA output. This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set. Channel 0 must be configured in capture mode (WAVE = 0 in TC_CMR0). The ABETRG bit of TC_CMR0 must be configured at 1 to select TIOA as a trigger for this channel. EDGTRG can be set to 0x01, to clear the counter on a rising edge of the TIOA signal and field LDRA must be set accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a consequence, at the end of each time base period the differentiation required for the speed calculation is performed. The process must be started by configuring bits CLKEN and SWTRG in the TC_CCR. The speed can be read on field RA in register TC_RA0. Channel 1 can still be used to count the number of revolutions of the motor. 47.6.16 2-bit Gray Up/Down Counter for Stepper Motor Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA, TIOB outputs by means of the GCEN bit in TC_SMMRx. Up or Down count can be defined by writing bit DOWN in TC_SMMRx. It is mandatory to configure the channel in WAVE mode in the TC_CMR. The period of the counters can be programmed in TC_RCx. Figure 47-21.2-bit Gray Up/Down Counter WAVEx = GCENx =1 TIOAx TC_RCx TIOBx DOWNx 47.6.17 Register Write Protection To prevent any single software error from corrupting TC behavior, certain registers in the address space can be writeprotected by setting the WPEN bit in the TC Write Protection Mode Register (TC_WPMR). The following registers can be protected:  TC Block Mode Register  TC Channel Mode Register: Capture Mode  TC Channel Mode Register: Waveform Mode  TC Stepper Motor Mode Register  TC Register A  TC Register B  TC Register C SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1516 47.7 Timer Counter (TC) User Interface Table 47-5. Register Mapping Offset(1) Register Name Access Reset 0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only – 0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read/Write 0 0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR Read/Write 0 0x00 + channel * 0x40 + 0x0C Register AB TC_RAB Read-only 0 0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0 0x00 + channel * 0x40 + 0x14 Register A TC_RA Read/Write (2) 0 Read/Write (2) 0 0x00 + channel * 0x40 + 0x18 Register B TC_RB 0x00 + channel * 0x40 + 0x1C Register C TC_RC Read/Write 0 0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0 0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only – 0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only – 0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0 0xC0 Block Control Register TC_BCR Write-only – 0xC4 Block Mode Register TC_BMR Read/Write 0 0xC8 QDEC Interrupt Enable Register TC_QIER Write-only – 0xCC QDEC Interrupt Disable Register TC_QIDR Write-only – 0xD0 QDEC Interrupt Mask Register TC_QIMR Read-only 0 0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0 0xD8 Reserved – – – 0xE4 Write Protection Mode Register TC_WPMR Read/Write 0 – – – 0xE8–0xFC Reserved Notes: 1. Channel index ranges from 0 to 2. 2. Read-only if WAVE = 0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1517 47.7.1 TC Channel Control Register Name: TC_CCRx [x=0..2] Address: (1)[2] 0xF0010000 (0)[0], 0xF0010040 (0)[1], 0xF0010080 (0)[2], 0xF8014000 (1)[0], 0xF8014040 (1)[1], 0xF8014080 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0: No effect. 1: Disables the clock. • SWTRG: Software Trigger Command 0: No effect. 1: A software trigger is performed: the counter is reset and the clock is started. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1518 47.7.2 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x=0..2] (WAVE = 0) Address: (1)[2] 0xF0010004 (0)[0], 0xF0010044 (0)[1], 0xF0010084 (0)[2], 0xF8014004 (1)[0], 0xF8014044 (1)[1], 0xF8014084 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – 15 14 13 12 11 10 WAVE CPCTRG – – – ABETRG 7 6 5 3 2 LDBDIS LDBSTOP 16 LDRB 4 BURST LDRA CLKI 9 8 ETRGEDG 1 0 TCCLKS This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • TCCLKS: Clock Selection Value Name Description 0 TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 1 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 2 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 3 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 4 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 5 XC0 Clock selected: XC0 6 XC1 Clock selected: XC1 7 XC2 Clock selected: XC2 • CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0: Counter clock is not stopped when RB loading occurs. 1: Counter clock is stopped when RB loading occurs. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1519 • LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. • WAVE: Waveform Mode 0: Capture Mode is enabled. 1: Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge of TIOA 2 FALLING Falling edge of TIOA 3 EDGE Each edge of TIOA • LDRB: RB Loading Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge of TIOA 2 FALLING Falling edge of TIOA 3 EDGE Each edge of TIOA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1520 47.7.3 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x=0..2] (WAVE = 1) Access: Read/Write 31 30 29 BSWTRG 23 22 27 20 14 7 6 CPCDIS CPCSTOP 24 18 17 16 ACPC 13 12 WAVSEL 25 BCPB 19 AEEVT WAVE 26 BCPC 21 ASWTRG 15 28 BEEVT 11 ENETRG 5 4 BURST ACPA 10 9 EEVT 8 EEVTEDG 3 2 CLKI 1 0 TCCLKS This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • TCCLKS: Clock Selection Value Name Description 0 TIMER_CLOCK1 Clock selected: internal TIMER_CLOCK1 clock signal (from PMC) 1 TIMER_CLOCK2 Clock selected: internal TIMER_CLOCK2 clock signal (from PMC) 2 TIMER_CLOCK3 Clock selected: internal TIMER_CLOCK3 clock signal (from PMC) 3 TIMER_CLOCK4 Clock selected: internal TIMER_CLOCK4 clock signal (from PMC) 4 TIMER_CLOCK5 Clock selected: internal TIMER_CLOCK5 clock signal (from PMC) 5 XC0 Clock selected: XC0 6 XC1 Clock selected: XC1 7 XC2 Clock selected: XC2 • CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0: Counter clock is not stopped when counter reaches RC. 1: Counter clock is stopped when counter reaches RC. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1521 • CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge • EEVT: External Event Selection Signal selected as external event. Note: Value Name Description TIOB Direction 0 TIOB TIOB(1) Input 1 XC0 XC0 Output 2 XC1 XC1 Output 3 XC2 XC2 Output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • ENETRG: External Event Trigger Enable 0: The external event has no effect on the counter and its clock. 1: The external event resets the counter and starts the counter clock. Note: Whatever the value programmed in ENETRG, the selected external event only controls the TIOA output and TIOB if not used as input (trigger event input or other input used). • WAVSEL: Waveform Selection Value Name Description 0 UP UP mode without automatic trigger on RC Compare 1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 2 UP_RC UP mode with automatic trigger on RC Compare 3 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare • WAVE: Waveform Mode 0: Waveform Mode is disabled (Capture Mode is enabled). 1: Waveform Mode is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1522 • ACPA: RA Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ACPC: RC Compare Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • AEEVT: External Event Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • ASWTRG: Software Trigger Effect on TIOA Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPB: RB Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BCPC: RC Compare Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1523 • BEEVT: External Event Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle • BSWTRG: Software Trigger Effect on TIOB Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1524 47.7.4 TC Stepper Motor Mode Register Name: TC_SMMRx [x=0..2] Address: (1)[2] 0xF0010008 (0)[0], 0xF0010048 (0)[1], 0xF0010088 (0)[2], 0xF8014008 (1)[0], 0xF8014048 (1)[1], 0xF8014088 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – DOWN GCEN This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • GCEN: Gray Count Enable 0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x. 1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter. • DOWN: DOWN Count 0: Up counter. 1: Down counter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1525 47.7.5 TC Register AB Name: TC_RABx [x=0..2] Address: (1)[2] 0xF001000C (0)[0], 0xF001004C (0)[1], 0xF001008C (0)[2], 0xF801400C (1)[0], 0xF801404C (1)[1], 0xF801408C Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RAB 23 22 21 20 RAB 15 14 13 12 RAB 7 6 5 4 RAB • RAB: Register A or Register B RAB contains the next unread capture Register A or Register B value in real time. It is usually read by the DMA after a request due to a valid load edge on TIOA. When DMA is used, the RAB register address must be configured as source address of the transfer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1526 47.7.6 TC Counter Value Register Name: TC_CVx [x=0..2] Address: (1)[2] 0xF0010010 (0)[0], 0xF0010050 (0)[1], 0xF0010090 (0)[2], 0xF8014010 (1)[0], 0xF8014050 (1)[1], 0xF8014090 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1527 47.7.7 TC Register A Name: TC_RAx [x=0..2] Address: (1)[2] 0xF0010014 (0)[0], 0xF0010054 (0)[1], 0xF0010094 (0)[2], 0xF8014014 (1)[0], 0xF8014054 (1)[1], 0xF8014094 Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • RA: Register A RA contains the Register A value in real time. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1528 47.7.8 TC Register B Name: TC_RBx [x=0..2] Address: (1)[2] 0xF0010018 (0)[0], 0xF0010058 (0)[1], 0xF0010098 (0)[2], 0xF8014018 (1)[0], 0xF8014058 (1)[1], 0xF8014098 Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RB 23 22 21 20 RB 15 14 13 12 RB 7 6 5 4 RB This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • RB: Register B RB contains the Register B value in real time. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1529 47.7.9 TC Register C Name: TC_RCx [x=0..2] Address: (1)[2] 0xF001001C (0)[0], 0xF001005C (0)[1], 0xF001009C (0)[2], 0xF801401C (1)[0], 0xF801405C (1)[1], 0xF801409C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • RC: Register C RC contains the Register C value in real time. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1530 47.7.10 TC Status Register Name: TC_SRx [x=0..2] Address: (1)[2] 0xF0010020 (0)[0], 0xF0010060 (0)[1], 0xF00100A0 (0)[2], 0xF8014020 (1)[0], 0xF8014060 (1)[1], 0xF80140A0 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0: No counter overflow has occurred since the last read of the Status Register. 1: A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0: Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0: RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1: RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0: RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1: RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0: RC Compare has not occurred since the last read of the Status Register. 1: RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0: RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1: RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0: RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1: RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1531 • CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0: TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1: TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1532 47.7.11 TC Interrupt Enable Register Name: TC_IERx [x=0..2] Address: (1)[2] 0xF0010024 (0)[0], 0xF0010064 (0)[1], 0xF00100A4 (0)[2], 0xF8014024 (1)[0], 0xF8014064 (1)[1], 0xF80140A4 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0: No effect. 1: Enables the Load Overrun Interrupt. • CPAS: RA Compare 0: No effect. 1: Enables the RA Compare Interrupt. • CPBS: RB Compare 0: No effect. 1: Enables the RB Compare Interrupt. • CPCS: RC Compare 0: No effect. 1: Enables the RC Compare Interrupt. • LDRAS: RA Loading 0: No effect. 1: Enables the RA Load Interrupt. • LDRBS: RB Loading 0: No effect. 1: Enables the RB Load Interrupt. • ETRGS: External Trigger 0: No effect. 1: Enables the External Trigger Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1533 47.7.12 TC Interrupt Disable Register Name: TC_IDRx [x=0..2] Address: (1)[2] 0xF0010028 (0)[0], 0xF0010068 (0)[1], 0xF00100A8 (0)[2], 0xF8014028 (1)[0], 0xF8014068 (1)[1], 0xF80140A8 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0: No effect. 1: Disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0: No effect. 1: Disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0: No effect. 1: Disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0: No effect. 1: Disables the RC Compare Interrupt. • LDRAS: RA Loading 0: No effect. 1: Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0: No effect. 1: Disables the RB Load Interrupt (if WAVE = 0). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1534 • ETRGS: External Trigger 0: No effect. 1: Disables the External Trigger Interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1535 47.7.13 TC Interrupt Mask Register Name: TC_IMRx [x=0..2] Address: (1)[2] 0xF001002C (0)[0], 0xF001006C (0)[1], 0xF00100AC (0)[2], 0xF801402C (1)[0], 0xF801406C (1)[1], 0xF80140AC Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0: The Load Overrun Interrupt is disabled. 1: The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0: The RA Compare Interrupt is disabled. 1: The RA Compare Interrupt is enabled. • CPBS: RB Compare 0: The RB Compare Interrupt is disabled. 1: The RB Compare Interrupt is enabled. • CPCS: RC Compare 0: The RC Compare Interrupt is disabled. 1: The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0: The Load RA Interrupt is disabled. 1: The Load RA Interrupt is enabled. • LDRBS: RB Loading 0: The Load RB Interrupt is disabled. 1: The Load RB Interrupt is enabled. • ETRGS: External Trigger 0: The External Trigger Interrupt is disabled. 1: The External Trigger Interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1536 47.7.14 TC Block Control Register Name: TC_BCR Address: 0xF00100C0 (0), 0xF80140C0 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1537 47.7.15 TC Block Mode Register Name: TC_BMR Address: 0xF00100C4 (0), 0xF80140C4 (1) Access: Read/Write 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 18 17 16 FILTER – IDXPHB SWAP MAXFILT 25 24 MAXFILT 15 14 13 12 11 10 9 8 INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN 7 6 5 4 3 2 1 – – TC2XC2S TC1XC1S 0 TC0XC0S This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. • TC0XC0S: External Clock Signal 0 Selection Value Name Description 0 TCLK0 Signal connected to XC0: TCLK0 1 – Reserved 2 TIOA1 Signal connected to XC0: TIOA1 3 TIOA2 Signal connected to XC0: TIOA2 • TC1XC1S: External Clock Signal 1 Selection Value Name Description 0 TCLK1 Signal connected to XC1: TCLK1 1 – Reserved 2 TIOA0 Signal connected to XC1: TIOA0 3 TIOA2 Signal connected to XC1: TIOA2 • TC2XC2S: External Clock Signal 2 Selection Value Name Description 0 TCLK2 Signal connected to XC2: TCLK2 1 – Reserved 2 TIOA0 Signal connected to XC2: TIOA0 3 TIOA1 Signal connected to XC2: TIOA1 • QDEN: Quadrature Decoder ENabled 0: Disabled. 1: Enables the quadrature decoder logic (filter, edge detection and quadrature decoding). Quadrature decoding (direction change) can be disabled using QDTRANS bit. One of the POSEN or SPEEDEN bits must be also enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1538 • POSEN: POSition ENabled 0: Disable position. 1: Enables the position measure on channel 0 and 1. • SPEEDEN: SPEED ENabled 0: Disabled. 1: Enables the speed measure on channel 0, the time base being provided by channel 2. • QDTRANS: Quadrature Decoding TRANSparent 0: Full quadrature decoding logic is active (direction change detected). 1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed. • EDGPHA: EDGe on PHA count mode 0: Edges are detected on PHA only. 1: Edges are detected on both PHA and PHB. • INVA: INVerted phA 0: PHA (TIOA0) is directly driving quadrature decoder logic. 1: PHA is inverted before driving quadrature decoder logic. • INVB: INVerted phB 0: PHB (TIOB0) is directly driving quadrature decoder logic. 1: PHB is inverted before driving quadrature decoder logic. • SWAP: SWAP PHA and PHB 0: No swap between PHA and PHB. 1: Swap PHA and PHB internally, prior to driving quadrature decoder logic. • INVIDX: INVerted InDeX 0: IDX (TIOA1) is directly driving quadrature logic. 1: IDX is inverted before driving quadrature logic. • IDXPHB: InDeX pin is PHB pin 0: IDX pin of the rotary sensor must drive TIOA1. 1: IDX pin of the rotary sensor must drive TIOB0. • FILTER: Glitch Filter 0: IDX,PHA, PHB input pins are not filtered. 1: IDX,PHA, PHB input pins are filtered using MAXFILT value. • MAXFILT: MAXimum FILTer 1.. 63: Defines the filtering capabilities. Pulses with a period shorter than MAXFILT+1 MCK clock cycles are discarded. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1539 47.7.16 TC QDEC Interrupt Enable Register Name: TC_QIER Address: 0xF00100C8 (0), 0xF80140C8 (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0: No effect. 1: Enables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0: No effect. 1: Enables the interrupt when a change on rotation direction is detected. • QERR: Quadrature ERRor 0: No effect. 1: Enables the interrupt when a quadrature error occurs on PHA,PHB. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1540 47.7.17 TC QDEC Interrupt Disable Register Name: TC_QIDR Address: 0xF00100CC (0), 0xF80140CC (1) Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0: No effect. 1: Disables the interrupt when a rising edge occurs on IDX input. • DIRCHG: DIRection CHanGe 0: No effect. 1: Disables the interrupt when a change on rotation direction is detected. • QERR: Quadrature ERRor 0: No effect. 1: Disables the interrupt when a quadrature error occurs on PHA, PHB. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1541 47.7.18 TC QDEC Interrupt Mask Register Name: TC_QIMR Address: 0xF00100D0 (0), 0xF80140D0 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0: The interrupt on IDX input is disabled. 1: The interrupt on IDX input is enabled. • DIRCHG: DIRection CHanGe 0: The interrupt on rotation direction change is disabled. 1: The interrupt on rotation direction change is enabled. • QERR: Quadrature ERRor 0: The interrupt on quadrature error is disabled. 1: The interrupt on quadrature error is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1542 47.7.19 TC QDEC Interrupt Status Register Name: TC_QISR Address: 0xF00100D4 (0), 0xF80140D4 (1) Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – DIR 7 6 5 4 3 2 1 0 – – – – – QERR DIRCHG IDX • IDX: InDeX 0: No Index input change since the last read of TC_QISR. 1: The IDX input has changed since the last read of TC_QISR. • DIRCHG: DIRection CHanGe 0: No change on rotation direction since the last read of TC_QISR. 1: The rotation direction changed since the last read of TC_QISR. • QERR: Quadrature ERRor 0: No quadrature error since the last read of TC_QISR. 1: A quadrature error occurred since the last read of TC_QISR. • DIR: DIRection Returns an image of the actual rotation direction. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1543 47.7.20 TC Write Protection Mode Register Name: TC_WPMR Address: 0xF00100E4 (0), 0xF80140E4 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – • WPEN: Write Protect Enable 0: Disables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1: Enables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII). See Section 47.6.17 “Register Write Protection” for list of write-protected registers. • WPKEY: Write Protect KEY Value 0x54494D Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1544 48. Pulse Width Modulation Controller (PWM) 48.1 Description The PWM macrocell controls 4 channels independently. Each channel controls two complementary square output waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM master clock (MCK). All PWM macrocell accesses are made through registers mapped on the peripheral bus. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period, the duty-cycle or the dead-times. Channels can be linked together as synchronous channels to be able to update their duty-cycle or dead-times at the same time. The PWM macrocell provides 8 independent comparison units capable of comparing a programmed value to the counter of the synchronous channels (counter of channel 0). These comparisons are intended to generate software interrupts, to trigger pulses on the 2 independent event lines (in order to synchronize ADC conversions with a lot of flexibility independently of the PWM outputs). The PWM outputs can be overridden synchronously or asynchronously to their channel counter. The PWM block provides a fault protection mechanism with 1 fault inputs, capable to detect a fault condition and to override the PWM outputs asynchronously (outputs forced to ‘0’, ‘1’). For safety usage, some configuration registers are write-protected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1545 48.2 Embedded Characteristics  4 Channels  Common Clock Generator Providing Thirteen Different Clocks   A Modulo n Counter Providing Eleven Clocks  Two Independent Linear Dividers Working on Modulo n Counter Outputs Independent Channels  Independent 16-bit Counter for Each Channel  Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or NonOverlapping Time) for Each Channel  Independent Enable Disable Command for Each Channel  Independent Clock Selection for Each Channel  Independent Period, Duty-Cycle and Dead-Time for Each Channel  Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel  Independent Programmable Selection of The Output Waveform Polarity for Each Channel  Independent Programmable Center or Left Aligned Output Waveform for Each Channel  Independent Output Override for Each Channel  Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration  2 2-bit Gray Up/Down Channels for Stepper Motor Control  Synchronous Channel Mode   Synchronous Channels Share the Same Counter  Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods 2 Independent Events Lines Intended to Synchronize ADC Conversions  Programmable delay for Events Lines to delay ADC measurements  8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines  1 Programmable Fault/Break Inputs Providing an Asynchronous Protection of PWM Outputs   4 User Driven through PIO inputs  PMC Driven when Crystal Oscillator Clock Fails  ADC Controller Driven through Configurable Comparison Function Write Protected Registers SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1546 48.3 Block Diagram Figure 48-1. Pulse Width Modulation Controller Block Diagram PWM Controller Channel x Update Period Comparator OCx DTOHx Dead-Time Generator DTOLx PWMHx OOOHx Output Override Fault OOOLx Protection PWMHx PWMLx PWMLx MUX SYNCx Duty-Cycle Counter Channel x Clock Selector PIO Channel 0 Update Period Comparator OC0 DTOH0 Dead-Time Generator DTOL0 OOOH0 Output Override PWMH0 Fault OOOL0 Protection PWMH0 PWML0 PWML0 Duty-Cycle Counter Channel 0 Clock Selector PWMFIx PIO PWMFI0 event line 0 event line 1 Comparison Units Events Generator ADC event line x PMC MCK CLOCK Generator APB Interface Interrupt Generator Interrupt Controller APB 48.4 I/O Lines Description Each channel outputs two complementary external I/O lines. Table 48-1. I/O Line Description Name Description Type PWMHx PWM Waveform Output High for channel x Output PWMLx PWM Waveform Output Low for channel x Output PWMFIx PWM Fault Input x Input SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1547 48.5 Product Dependencies 48.5.1 I/O Lines The pins used for interfacing the PWM are multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Table 48-2. I/O Lines Instance Signal I/O Line Peripheral PWM PWMFI0 PC28 B PWM PWMFI1 PC31 B PWM PWMFI2 PC29 B PWM PWMFI3 PD16 C PWM PWMH0 PA20 B PWM PWMH0 PB0 B PWM PWMH1 PA22 B PWM PWMH1 PB4 B PWM PWMH1 PB27 C PWM PWMH2 PB8 B PWM PWMH2 PD5 C PWM PWMH3 PB12 B PWM PWMH3 PD7 C PWM PWML0 PA21 B PWM PWML0 PB1 B PWM PWML1 PA23 B PWM PWML1 PB5 B PWM PWML1 PE31 B PWM PWML2 PB9 B PWM PWML2 PD6 C PWM PWML3 PB13 B PWM PWML3 PD8 C 48.5.2 Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. In the PWM description, Master Clock (MCK) is the clock of the peripheral bus to which the PWM is connected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1548 48.5.3 Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PWM interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode. Table 48-3. Peripheral IDs Instance ID PWM 28 48.5.4 Fault Inputs The PWM has the FAULT inputs connected to the different modules. Please refer to the implementation of these module within the product for detailed information about the fault generation procedure. The PWM receives faults from PIO inputs, PMC, ADC controller, . Table 48-4. Fault Inputs Fault Generator External PWM Fault Input Number Polarity Level(1) Fault Input ID PC28 PWMFI0 User Defined 0 PC31 PWMFI1 User Defined 1 PC29 PWMFI2 User Defined 2 PD16 PWMFI3 User Defined 3 Main OSC (PMC) – To be configured to 1 4 ADC – To be configured to 1 5 Note: 1. FPOL field in PWMC_FMR. 48.6 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels.  Clocked by the master clock (MCK), the clock generator module provides 13 clocks.  Each channel can independently choose one of the clock generator outputs.  Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1549 48.6.1 PWM Clock Generator Figure 48-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A PREA clkA DIVA PWM_MR Divider B PREB clkB DIVB PWM_MR The PWM master clock (MCK) is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks:  a modulo n counter which provides 11 clocks: fMCK, fMCK/2, fMCK/4, fMCK/8, fMCK/16, fMCK/32, fMCK/64, fMCK/128, fMCK/256, fMCK/512, fMCK/1024  two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value. After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to ‘0’. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “MCK”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. CAUTION:  Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1550 48.6.2 PWM Channel 48.6.2.1 Channel Block Diagram Figure 48-3. Functional View of the Channel Block Diagram Channel x Update Period MUX Comparator x OCx DTOHx Dead-Time Generator DTOLx PWMHx OOOHx Output Fault Override OOOLx Protection PWMLx Duty-Cycle MUX from Clock Generator Clock Selector SYNCx Counter Channel x from APB Peripheral Bus Counter Channel 0 2-bit gray counter z Comparator y MUX z = 0 (x = 0, y = 1), z = 1 (x = 2, y = 3), z = 2 (x = 4, y = 5), z = 3 (x = 6, y = 7) Channel y (= x+1) OCy PWMHy OOOHy DTOHy Dead-Time Output Fault OOOLy Generator DTOLy Override Protection PWMLy Each of the 4 channels is composed of six blocks:  A clock selector which selects one of the clocks provided by the clock generator (described in Section 48.6.1 on page 1550).  A counter clocked by the output of the clock selector. This counter is incremented or decremented according to the channel configuration and comparators matches. The size of the counter is 16 bits.  A comparator used to compute the OCx output waveform according to the counter value and the configuration. The counter value can be the one of the channel counter or the one of the channel 0 counter according to SYNCx bit in the “PWM Sync Channels Mode Register” (PWM_SCM).  A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2 channels.  A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external power control switches safely.  An output override block that can force the two complementary outputs to a programmed value (OOOHx/OOOLx).  An asynchronous fault protection mechanism that has the highest priority to override the two complementary outputs (PWMHx/PWMLx) in case of fault detection (outputs forced to ‘0’, ‘1’). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1551 48.6.2.2 Comparator The comparator continuously compares its counter value with the channel period defined by CPRD in the “PWM Channel Period Register” (PWM_CPRDx) and the duty-cycle defined by CDTY in the “PWM Channel Duty Cycle Register” (PWM_CDTYx) to generate an output signal OCx accordingly. The different properties of the waveform of the output OCx are:  the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the “PWM Channel Mode Register” (PWM_CMRx). This field is reset at ‘0’.  the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: (-----------------------------X × CPRD )MCK By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (--------------------------------------------------X × C RPD × DIVA )or MCK (--------------------------------------------------X × C RPD × DIVB )MCK If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (---------------------------------------2 × X × CPRD ) MCK By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (------------------------------------------------------------2 × X × C PRD × DIVA ) or MCK (------------------------------------------------------------2 × X × C PRD × DIVB ) MCK  the waveform duty-cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: ( period – 1 ⁄ fchannel_x_clock × CDTY ) duty cycle = ---------------------------------------------------------------------------------------------------period If the waveform is center aligned, then: ( ( period ⁄ 2 ) – 1 ⁄ fchannel_x_clock × CDTY ) ) duty cycle = ------------------------------------------------------------------------------------------------------------------( period ⁄ 2 )  the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL bit of the PWM_CMRx. By default the signal starts by a low level. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1552  the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG bit of the PWM_CMRx. The default mode is left aligned. Figure 48-4. Non Overlapped Center Aligned Waveforms No overlap OC0 OC1 Period Note: 1. See Figure 48-5 on page 1554 for a detailed description of center aligned waveforms. When center aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period. When left aligned, the channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel. Waveforms are fixed at 0 when:  CDTY = CPRD and CPOL = 0  CDTY = 0 and CPOL = 1 Waveforms are fixed at 1 (once the channel is enabled) when:  CDTY = 0 and CPOL = 0  CDTY = CPRD and CPOL = 1 The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Modifying CPOL in “PWM Channel Mode Register” while the channel is enabled can lead to an unexpected behavior of the device being driven by PWM. Besides generating output signals OCx, the comparator generates interrupts in function of the counter value. When the output waveform is left aligned, the interrupt occurs at the end of the counter period. When the output waveform is center aligned, the bit CES of the PWM_CMRx defines when the channel counter interrupt occurs. If CES is set to ‘0’, the interrupt occurs at the end of the counter period. If CES is set to ‘1’, the interrupt occurs at the end of the counter period and at half of the counter period. Figure 48-5 “Waveform Properties” illustrates the counter interrupts in function of the configuration. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1553 Figure 48-5. Waveform Properties Channel x slected clock CHIDx(PWM_SR) CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform OCx CPOL(PWM_CMRx) = 0 Output Waveform OCx CPOL(PWM_CMRx) = 1 Counter Event CHIDx(PWM_ISR) CES(PWM_CMRx) = 0 Counter Event CHIDx(PWM_ISR) CES(PWM_CMRx) = 1 Left Aligned CALG(PWM_CMRx) = 0 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform OCx CPOL(PWM_CMRx) = 0 Output Waveform OCx CPOL(PWM_CMRx) = 1 Counter Event CHIDx(PWM_ISR) 48.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor It is possible to configure a couple of channels to provide a 2-bit gray count waveform on two outputs. Dead-Time Generator and other downstream logic can be configured on these channels. Up or down count mode can be configured on-the-fly by means of PWM_SMMR configuration registers. When GCEN0 is set to ‘1’, channels 0 and 1 outputs are driven with gray counter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1554 Figure 48-6. 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 48.6.2.4 Dead-Time Generator The dead-time generator uses the comparator output OCx to provide the two complementary outputs DTOHx and DTOLx, which allows the PWM macrocell to drive external power control switches safely. When the dead-time generator is enabled by setting the bit DTE to ‘1’ or 0 in the “PWM Channel Mode Register” (PWM_CMRx), dead-times (also called dead-bands or non-overlapping times) are inserted between the edges of the two complementary outputs DTOHx and DTOLx. Note that enabling or disabling the dead-time generator is allowed only if the channel is disabled. The dead-time is adjustable by the “PWM Channel Dead Time Register” (PWM_DTx). Both outputs of the dead-time generator can be adjusted separately by DTH and DTL. The dead-time values can be updated synchronously to the PWM period by using the “PWM Channel Dead Time Update Register” (PWM_DTUPDx). The dead-time is based on a specific counter which uses the same selected clock that feeds the channel counter of the comparator. Depending on the edge and the configuration of the dead-time, DTOHx and DTOLx are delayed until the counter has reached the value defined by DTH or DTL. An inverted configuration bit (DTHI and DTLI bit in the PWM_CMRx) is provided for each output to invert the dead-time outputs. The following figure shows the waveform of the dead-time generator. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1555 Figure 48-7. Complementary Output Waveforms output waveform OCx CPOLx = 0 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 DTHx DTLx DTHx DTLx output waveform OCx CPOLx = 1 output waveform DTOHx DTHIx = 0 output waveform DTOLx DTLIx = 0 output waveform DTOHx DTHIx = 1 output waveform DTOLx DTLIx = 1 48.6.2.5 Output Override The two complementary outputs DTOHx and DTOLx of the dead-time generator can be forced to a value defined by the software. Figure 48-8. Override Output Selection DTOHx 0 OOOHx OOVHx 1 OSHx DTOLx 0 OOOLx OOVLx 1 OSLx The fields OSHx and OSLx in the “PWM Output Selection Register” (PWM_OS) allow the outputs of the dead-time generator DTOHx and DTOLx to be overridden by the value defined in the fields OOVHx and OOVLx in the“PWM Output Override Value Register” (PWM_OOV). The set registers “PWM Output Selection Set Register” (PWM_OSS) and “PWM Output Selection Set Update Register” (PWM_OSSUPD) enable the override of the outputs of a channel regardless of other channels. In the same way, the clear registers “PWM Output Selection Clear Register” (PWM_OSC) and “PWM Output Selection Clear Update Register” (PWM_OSCUPD) disable the override of the outputs of a channel regardless of other channels. By using buffer registers PWM_OSSUPD and PWM_OSCUPD, the output selection of PWM outputs is done synchronously to the channel counter, at the beginning of the next PWM period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1556 By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the channel counter, as soon as the register is written. The value of the current output selection can be read in PWM_OS. While overriding PWM outputs, the channel counters continue to run, only the PWM outputs are forced to user defined values. 48.6.2.6 Fault Protection 1 inputs provide fault protection which can force any of the PWM output pairs to a programmable value. This mechanism has priority over output overriding. Figure 48-9. Fault Protection 0 fault input 0 Glitch Filter FIV0 1 = 0 FMOD0 SET OUT Fault 0 Status FS0 FPEx[0] CLR FPE0[0] FFIL0 0 fault input 1 Glitch Filter 1 Write FCLR0 at 1 FPOL0 FIV1 = FMOD0 0 FMOD1 SET OUT Fault 1 Status FS1 FPEx[1] FPE0[1] FPOL1 Write FCLR1 at 1 0 1 SYNCx from fault 1 1 CLR FFIL1 from fault 0 1 FMOD1 From Output Override OOHx 0 FPVHx 1 PWMHx 0 Fault protection on PWM channel x 1 from fault y SYNCx fault input y FPVLx 1 OOLx From Output Override 0 PWMLx The polarity level of the fault inputs is configured by the FPOL field in the “PWM Fault Mode Register” (PWM_FMR). For fault inputs coming from internal peripherals such as ADC, Timer Counter, to name but a few, the polarity level must be FPOL = 1. For fault inputs coming from external GPIO pins the polarity level depends on the user's implementation. The configuration of the Fault Activation Mode (FMOD field in PWMC_FMR) depends on the peripheral generating the fault. If the corresponding peripheral does not have “Fault Clear” management, then the FMOD configuration to use must be FMOD = 1, to avoid spurious fault detection. Check the corresponding peripheral documentation for details on handling fault generation. The fault inputs can be glitch filtered or not in function of the FFIL field in the PWM_FMR. When the filter is activated, glitches on fault inputs with a width inferior to the PWM master clock (MCK) period are rejected. A fault becomes active as soon as its corresponding fault input has a transition to the programmed polarity level. If the corresponding bit FMOD is set to ‘0’ in the PWM_FMR, the fault remains active as long as the fault input is at this polarity level. If the corresponding FMOD field is set to ‘1’, the fault remains active until the fault input is not at this polarity level anymore and until it is cleared by writing the corresponding bit FCLR in the “PWM Fault Clear Register” (PWM_FCR). By reading the “PWM Fault Status Register” (PWM_FSR), the user can read the current level of the fault inputs by means of the field FIV, and can know which fault is currently active thanks to the FS field. Each fault can be taken into account or not by the fault protection mechanism in each channel. To be taken into account in the channel x, the fault y must be enabled by the bit FPEx[y] in the “PWM Fault Protection Enable Registers” (PWM_FPE1). However the synchronous channels (see Section 48.6.2.7 “Synchronous Channels”) do not use their own fault enable bits, but those of the channel 0 (bits FPE0[y]). The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are enabled for this channel is active. It can be triggered even if the PWM master clock (MCK) is not running but only by a fault input that is not glitch filtered. When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this channel and forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the “PWM Fault Protection Value Register” (PWM_FPV) . The output forcing is made asynchronously to the channel counter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1557 CAUTION:  To prevent an unexpected activation of the status flag FSy in the PWM_FSR, the FMODy bit can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value.  To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value. If a comparison unit is enabled (see Section 48.6.3 “PWM Comparison Units”) and if a fault is triggered in the channel 0, in this case the comparison cannot match. As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt generated at the end of the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading the interrupt status register, even if the fault which has caused the trigger of the fault protection is kept active. 48.6.2.7 Synchronous Channels Some channels can be linked together as synchronous channels. They have the same source clock, the same period, the same alignment and are started together. In this way, their counters are synchronized together. The synchronous channels are defined by the SYNCx bits in the “PWM Sync Channels Mode Register” (PWM_SCM). Only one group of synchronous channels is allowed. When a channel is defined as a synchronous channel, the channel 0 is automatically defined as a synchronous channel too, because the channel 0 counter configuration is used by all the synchronous channels. If a channel x is defined as a synchronous channel, it uses the following configuration fields of the channel 0 instead of its own:  CPRE0 field in PWM_CMR0 instead of CPREx field in PWM_CMRx (same source clock)  CPRD0 field in PWM_CMR0 instead of CPRDx field in PWM_CMRx (same period)  CALG0 field in PWM_CMR0 instead of CALGx field in PWM_CMRx (same alignment) Thus writing these fields of a synchronous channel has no effect on the output waveform of this channel (except channel 0 of course). Because counters of synchronous channels must start at the same time, they are all enabled together by enabling the channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by disabling channel 0 (by the CHID0 bit in PWM_DIS register). However, a synchronous channel x different from channel 0 can be enabled or disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS registers). Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to ‘1’ while it was at ‘0’) is allowed only if the channel is disabled at this time (CHIDx = 0 in PWM_SR). In the same way, defining a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to ‘0’ while it was 1) is allowed only if the channel is disabled at this time. The field UPDM (Update Mode) in the PWM_SCM register allow to select one of the three methods to update the registers of the synchronous channels:  Method 1 (UPDM = 0): The period value, the duty-cycle values and the dead-time values must be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the “PWM Sync Channels Update Control Register” (PWM_SCUC) is set to ‘1’ (see “Method 1: Manual write of duty-cycle values and manual trigger of the update” on page 1559).  Method 2 (UPDM = 1): The period value, the duty-cycle values, the dead-time values and the update period value must be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is triggered at the next PWM period as soon as the bit UPDULOCK in the PWM_SCUC register is set to ‘1’. The update of the duty-cycle values and the update period value is triggered automatically after an update period defined by the field UPR in the “PWM Sync Channels Update Period Register” (PWM_SCUP) (see “Method 2: Manual write of dutycycle values and automatic trigger of the update” on page 1560). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1558 Table 48-5. Summary of the Update of Registers of Synchronous Channels UPDM=0 UPDM=1 Write by the CPU Period Value Update is triggered at the (PWM_CPRDUPDx) next PWM period as soon as the bit UPDULOCK is set to ‘1’ Write by the CPU Update is triggered at the Dead-Time Values (PWM_DTUPDx) next PWM period as soon as the bit UPDULOCK is set to ‘1’ Duty-Cycle Values (PWM_CDTYUPDx) Write by the CPU Write by the CPU Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’ Update is triggered at the next PWM period as soon as the update period Not applicable Write by the CPU Update Period Value (PWM_SCUPUPD) counter has reached the value UPR Update is triggered at the next Not applicable PWM period as soon as the update period counter has reached the value UPR Method 1: Manual write of duty-cycle values and manual trigger of the update In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx). To trigger the update, the user must use the bit UPDULOCK in the PWM_SCUC register which allows to update synchronously (at the same PWM period) the synchronous channels:  If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels.  If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed. After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0. Sequence for Method 1: 1. Select the manual write of duty-cycle values and the manual update by setting the UPDM field to ‘0’ in the PWM_SCM register 2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register. 3. Enable the synchronous channels by writing CHID0 in the PWM_ENA register. 4. If an update of the period value and/or the duty-cycle values and/or the dead-time values is required, write registers that need to be updated (PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx). 5. Set UPDULOCK to ‘1’ in PWM_SCUC. 6. The update of the registers will occur at the beginning of the next PWM period. At this moment the UPDULOCK bit is reset, go to Step 4.) for new values. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1559 Figure 48-10.Method 1 (UPDM = 0) CCNT0 CDTYUPD 0x20 0x40 0x20 0x40 0x60 UPDULOCK CDTY 0x60 Method 2: Manual write of duty-cycle values and automatic trigger of the update In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period value must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD). To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK in the PWM_SCUC register, which allows to update synchronously (at the same PWM period) the synchronous channels:  If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels.  If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed. After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0. The update of the duty-cycle values and the update period is triggered automatically after an update period. To configure the automatic update, the user must define a value for the Update Period by the UPR field in the PWM_SCUP register. The PWM controller waits UPR+1 period of synchronous channels before updating automatically the duty values and the update period value. The status of the duty-cycle value write is reported in the “PWM Interrupt Status Register 2” (PWM_ISR2) by the following flags:  WRDY: this flag is set to ‘1’ when the PWM Controller is ready to receive new duty-cycle values and a new update period value. It is reset to ‘0’ when the PWM_ISR2 register is read. Depending on the interrupt mask in the “PWM Interrupt Mask Register 2” (PWM_IMR2), an interrupt can be generated by these flags. Sequence for Method 2: 1. Select the manual write of duty-cycle values and the automatic update by setting the field UPDM to ‘1’ in the PWM_SCM register 2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register. 3. Define the update period by the field UPR in the PWM_SCUP register. 4. Enable the synchronous channels by writing CHID0 in the PWM_ENA register. 5. If an update of the period value and/or of the dead-time values is required, write registers that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 8. 6. Set UPDULOCK to ‘1’ in PWM_SCUC. 7. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDULOCK is reset, go to Step 5. for new values. 8. If an update of the duty-cycle values and/or the update period is required, check first that write of new update values is possible by polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2. 9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1560 10. The update of these registers will occur at the next PWM period of the synchronous channels when the Update Period is elapsed. Go to Step 8. for new values. Figure 48-11.Method 2 (UPDM=1) CCNT0 CDTYUPD UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x60 0x40 0x20 0x3 0x3 0x1 0x0 0x1 0x20 0x0 0x1 0x1 0x0 0x40 0x2 0x3 0x1 0x0 0x2 0x60 WRDY 48.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 48.6.2.7 “Synchronous Channels”). These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, see Section 48.6.4 “PWM Event Lines”), to generate software interrupts. Figure 48-12.Comparison Unit Block Diagram CEN [PWM_CMPM]x fault on channel 0 CV [PWM_CMPVx] CNT [PWM_CCNT0] Comparison x = 1 CNT [PWM_CCNT0] is decrementing = 0 1 CVM [PWM_CMPVx] CALG [PWM_CMR0] CPRCNT [PWM_CMPMx] CTR [PWM_CMPMx] = The comparison x matches when it is enabled by the bit CEN in the “PWM Comparison x Mode Register” (PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches the comparison value defined by the field CV in “PWM Comparison x Value Register” (PWM_CMPVx for the comparison x). If the counter of the channel 0 is center aligned (CALG = 1 in “PWM Channel Mode Register” ), the bit CVM (in PWM_CMPVx) defines if the SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1561 comparison is made when the counter is counting up or counting down (in left alignment mode CALG = 0, this bit is useless). If a fault is active on the channel 0, the comparison is disabled and cannot match (see Section 48.6.2.6 “Fault Protection”). The user can define the periodicity of the comparison x by the fields CTR and CPR (in PWM_CMPVx). The comparison is performed periodically once every CPR+1 periods of the counter of the channel 0, when the value of the comparison period counter CPRCNT (in PWM_CMPMx) reaches the value defined by CTR. CPR is the maximum value of the comparison period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the counter of the channel 0. The comparison x configuration can be modified while the channel 0 is enabled by using the “PWM Comparison x Mode Update Register” (PWM_CMPMUPDx registers for the comparison x). In the same way, the comparison x value can be modified while the channel 0 is enabled by using the “PWM Comparison x Value Update Register” (PWM_CMPVUPDx registers for the comparison x). The update of the comparison x configuration and the comparison x value is triggered periodically after the comparison x update period. It is defined by the field CUPR in the PWM_CMPMx. The comparison unit has an update period counter independent from the period counter to trigger this update. When the value of the comparison update period counter CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x update period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register. CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx. The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not masked. These interrupts can be enabled by the “PWM Interrupt Enable Register 2” and disabled by the “PWM Interrupt Disable Register 2” . The comparison match interrupt and the comparison update interrupt are reset by reading the “PWM Interrupt Status Register 2” . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1562 Figure 48-13.Comparison Waveform CCNT0 CVUPD 0x6 0x6 0x2 CVMVUPD CTRUPD 0x1 0x2 CPRUPD 0x1 0x3 CUPRUPD 0x3 0x2 CV 0x6 0x2 CTR 0x1 0x2 CPR 0x1 0x3 CUPR 0x3 0x2 CUPRCNT 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 CPRCNT 0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 0x6 CVM Comparison Update CMPU Comparison Match CMPM 48.6.4 PWM Event Lines The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in particular for ADC (Analog-to-Digital Converter)). A pulse (one cycle of the master clock (MCK)) is generated on an event line, when at least one of the selected comparisons is matching. The comparisons can be selected or unselected independently by the CSEL bits in the “PWM Event Line x Register” (PWM_ELMRx for the Event Line x). Figure 48-14.Event Line Block Diagram CMPM0 (PWM_ISR2) CSEL0 (PWM_ELMRx) CMPM1 (PWM_ISR2) CSEL1 (PWM_ELMRx) CMPM2 (PWM_ISR2) CSEL2 (PWM_ELMRx) PULSE GENERATOR Event Line x CMPM7 (PWM_ISR2) CSEL7 (PWM_ELMRx) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1563 48.6.5 PWM Controller Operations 48.6.5.1 Initialization Before enabling the channels, they must have been configured by the software application:  Unlock User Interface by writing the WPCMD field in the PWM_WPCR.  Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required).  Selection of the clock for each channel (CPRE field in PWM_CMRx)  Configuration of the waveform alignment for each channel (CALG field in PWM_CMRx)  Selection of the counter event selection (if CALG = 1) for each channel (CES field in PWM_CMRx)  Configuration of the output waveform polarity for each channel (CPOL bit in PWM_CMRx)  Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CPRDUPDx register to update PWM_CPRDx as explained below.  Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CDTYUPDx register to update PWM_CDTYx as explained below.  Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if enabled (DTE bit in the PWM_CMRx). Writing in the PWM_DTx register is possible while the channel is disabled. After validation of the channel, the user must use PWM_DTUPDx register to update PWM_DTx  Selection of the synchronous channels (SYNCx in the PWM_SCM register)  Configuration of the update mode (UPDM in PWM_SCM register)  Configuration of the update period (UPR in PWM_SCUP register) if needed  Configuration of the comparisons (PWM_CMPVx and PWM_CMPMx)  Configuration of the event lines (PWM_ELMRx)  Configuration of the fault inputs polarity (FPOL in PWM_FMR)  Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and PWM_FPE1)  Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1, and writing WRDYE, ENDTXE, TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2)  Enable of the PWM channels (writing CHIDx in the PWM_ENA register) 48.6.5.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the “PWM Channel Period Register” (PWM_CPRDx) and the “PWM Channel Duty Cycle Register” (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value from between 1 up to 14 in PWM_CDTYx. The resulting duty-cycle quantum cannot be lower than 1/15 of the PWM period. 48.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times It is possible to modulate the output waveform duty-cycle, period and dead-times. To prevent unexpected output waveform, the user must use the “PWM Channel Duty Cycle Update Register” (PWM_CDTYUPDx), the “PWM Channel Period Update Register” (PWM_CPRDUPDx) and the “PWM Channel Dead Time Update Register” (PWM_DTUPDx) to change waveform parameters while the channel is still enabled.  If the channel is an asynchronous channel (SYNCx = 0 in “PWM Sync Channels Mode Register” (PWM_SCM)), these registers hold the new period, duty-cycle and dead-times values until the end of the current PWM period and update the values for the next period.  If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and UPDM = 0 in PWM_SCM register), these registers hold the new period, duty-cycle and dead-times values until the bit SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1564 UPDULOCK is written at ‘1’ (in “PWM Sync Channels Update Control Register” (PWM_SCUC)) and the end of the current PWM period, then update the values for the next period.  Note: If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx = 1 and UPDM = 1 or 2 in PWM_SCM register):  registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-times values until the bit UPDULOCK is written at ‘1’ (in PWM_SCUC) and the end of the current PWM period, then update the values for the next period.  register PWM_CDTYUPDx holds the new duty-cycle value until the end of the update period of synchronous channels (when UPRCNT is equal to UPR in “PWM Sync Channels Update Period Register” (PWM_SCUP)) and the end of the current PWM period, then updates the value for the next period. If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written several times between two updates, only the last written value is taken into account. Figure 48-15.Synchronized Period, Duty-Cycle and Dead-Times Update User's Writing User's Writing User's Writing PWM_DTUPDx Value PWM_CPRDUPDx Value PWM_CDTYUPDx Value PWM_CPRDx PWM_DTx PWM_CDTYx - If Asynchronous Channel -> End of PWM period - If Synchronous Channel -> End of PWM period and UPDULOCK = 1 - If Asynchronous Channel -> End of PWM period - If Synchronous Channel - If UPDM = 0 -> End of PWM period and UPDULOCK = 1 - If UPDM = 1 or 2 -> End of PWM period and end of Update Period 48.6.5.4 Changing the Synchronous Channels Update Period It is possible to change the update period of synchronous channels while they are enabled. (See “Method 2: Manual write of duty-cycle values and automatic trigger of the update” on page 1560) To prevent an unexpected update of the synchronous channels registers, the user must use the “PWM Sync Channels Update Period Update Register” (PWM_SCUPUPD) to change the update period of synchronous channels while they are still enabled. This register holds the new value until the end of the update period of synchronous channels (when UPRCNT is equal to UPR in PWM_SCUP) and the end of the current PWM period, then updates the value for the next period. Note: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value is taken into account. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1565 Note: Changing the update period does make sense only if there is one or more synchronous channels and if the update method 1 or 2 is selected (UPDM = 1 or 2 in “PWM Sync Channels Mode Register” ). Figure 48-16.Synchronized Update of Update Period Value of Synchronous Channels User's Writing PWM_SCUPUPD Value PWM_SCUP End of PWM period and end of Update Period of Synchronous Channels 48.6.5.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see Section 48.6.3 “PWM Comparison Units”). To prevent unexpected comparison match, the user must use the “PWM Comparison x Value Update Register” (PWM_CMPVUPDx) and the “PWM Comparison x Mode Update Register” (PWM_CMPMUPDx) to change respectively the comparison values and the comparison configurations while the channel 0 is still enabled. These registers hold the new values until the end of the comparison update period (when CUPRCNT is equal to CUPR in “PWM Comparison x Mode Register” (PWM_CMPMx) and the end of the current PWM period, then update the values for the next period. CAUTION: The write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx. Note: If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times between two updates, only the last written value are taken into account. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1566 Figure 48-17.Synchronized Update of Comparison Values and Configurations User's Writing User's Writing PWM_CMPVUPDx Value Comparison Value for comparison x PWM_CMPMUPDx Value Comparison configuration for comparison x PWM_CMPVx PWM_CMPMx End of channel0 PWM period and end of Comparison Update Period and and PWM_CMPMx written End of channel0 PWM period and end of Comparison Update Period 48.6.5.6 Interrupts Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2, an interrupt can be generated at the end of the corresponding channel period (CHIDx in the PWM Interrupt Status Register 1 (PWM_ISR1)), after a fault event (FCHIDx in the PWM_ISR1), after a comparison match (CMPMx in the PWM_ISR2), after a comparison update (CMPUx in the PWM_ISR2) or according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and UNRE in the PWM_ISR2). If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the PWM_ISR1 occurs. If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a read operation in the PWM_ISR2 occurs. A channel interrupt is enabled by setting the corresponding bit in PWM_IER1 and PWM_IER2. A channel interrupt is disabled by setting the corresponding bit in PWM_IDR1 and PWM_IDR2. 48.6.5.7 Register Write Protection To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-protected by writing the field WPCMD in the “PWM Write Protection Control Register” (PWM_WPCR). They are divided into six groups:  Register group 0:  Register group 1:     “PWM Clock Register” on page 1572 “PWM Disable Register” on page 1574 Register group 2:  “PWM Sync Channels Mode Register” on page 1580  “PWM Channel Mode Register” on page 1608  “PWM Stepper Motor Mode Register” on page 1600 Register group 3:  “PWM Channel Period Register” on page 1612  “PWM Channel Period Update Register” on page 1613 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1567   Register group 4:  “PWM Channel Dead Time Register” on page 1615  “PWM Channel Dead Time Update Register” on page 1616 Register group 5:  “PWM Fault Mode Register” on page 1594  “PWM Fault Protection Value Register” on page 1597 There are two types of Write Protection:  SW Write Protect—can be enabled or disabled by software  HW Write Protect—can be enabled by software but only disabled by a hardware reset of the PWM controller Both types of Write Protect can be applied independently to a particular register group by means of the WPCMD and WPRGx fields in the PWM_WPCR. If at least one Write Protect is active, the register group is write-protected. The value of field WPCMD defines the action to be performed: 0: disables SW Write Protect of the register groups of which the bit WPRGx is at ‘1’ 1: enables SW Write Protect of the register groups of which the bit WPRGx is at ‘1’ 2: enables HW Write Protect of the register groups of which the bit WPRGx is at ‘1’ At any time, the user can determine which Write Protect is active in which register group by the fields WPSWS and WPHWS in the “PWM Write Protection Status Register” (PWM_WPSR). If a write access in a write-protected register is detected, then the WPVS flag in the PWM_WPSR is set and the field WPVSRC indicates in which register the write access has been attempted, through its address offset without the two LSBs. The WPVS and WPVSRC fields are automatically cleared after reading the PWM_WPSR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1568 48.7 Pulse Width Modulation Controller (PWM) User Interface Table 48-6. Register Mapping Offset Register Name Access Reset 0x00 PWM Clock Register PWM_CLK Read/Write 0x0 0x04 PWM Enable Register PWM_ENA Write-only – 0x08 PWM Disable Register PWM_DIS Write-only – 0x0C PWM Status Register PWM_SR Read-only 0x0 0x10 PWM Interrupt Enable Register 1 PWM_IER1 Write-only – 0x14 PWM Interrupt Disable Register 1 PWM_IDR1 Write-only – 0x18 PWM Interrupt Mask Register 1 PWM_IMR1 Read-only 0x0 0x1C PWM Interrupt Status Register 1 PWM_ISR1 Read-only 0x0 0x20 PWM Sync Channels Mode Register PWM_SCM Read/Write 0x0 0x24 Reserved – – – 0x28 PWM Sync Channels Update Control Register PWM_SCUC Read/Write 0x0 0x2C PWM Sync Channels Update Period Register PWM_SCUP Read/Write 0x0 0x30 PWM Sync Channels Update Period Update Register PWM_SCUPUPD Write-only 0x0 0x34 PWM Interrupt Enable Register 2 PWM_IER2 Write-only – 0x38 PWM Interrupt Disable Register 2 PWM_IDR2 Write-only – 0x3C PWM Interrupt Mask Register 2 PWM_IMR2 Read-only 0x0 0x40 PWM Interrupt Status Register 2 PWM_ISR2 Read-only 0x0 0x44 PWM Output Override Value Register PWM_OOV Read/Write 0x0 0x48 PWM Output Selection Register PWM_OS Read/Write 0x0 0x4C PWM Output Selection Set Register PWM_OSS Write-only – 0x50 PWM Output Selection Clear Register PWM_OSC Write-only – 0x54 PWM Output Selection Set Update Register PWM_OSSUPD Write-only – 0x58 PWM Output Selection Clear Update Register PWM_OSCUPD Write-only – 0x5C PWM Fault Mode Register PWM_FMR Read/Write 0x0 0x60 PWM Fault Status Register PWM_FSR Read-only 0x0 0x64 PWM Fault Clear Register PWM_FCR Write-only – 0x68 PWM Fault Protection Value Register PWM_FPV Read/Write 0x0 0x6C PWM Fault Protection Enable Register PWM_FPE Read/Write 0x0 0x70–0x78 Reserved – – – 0x7C PWM Event Line 0 Mode Register PWM_ELMR0 Read/Write 0x0 0x80 PWM Event Line 1 Mode Register PWM_ELMR1 Read/Write 0x0 0x84–0x9C Reserved – – – 0xA0–0xAC Reserved – – – 0xB0 PWM Stepper Motor Mode Register PWM_SMMR Read/Write 0x0 0xB4–0xBC Reserved – – – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1569 Table 48-6. Register Mapping (Continued) Offset Register Name Access Reset 0xC0–0xE0 Reserved – – – 0xE4 PWM Write Protection Control Register PWM_WPCR Write-only – 0xE8 PWM Write Protection Status Register PWM_WPSR Read-only 0x0 0xEC–0xFC Reserved – – – 0x130 PWM Comparison 0 Value Register PWM_CMPV0 Read/Write 0x0 0x134 PWM Comparison 0 Value Update Register PWM_CMPVUPD0 Write-only – 0x138 PWM Comparison 0 Mode Register PWM_CMPM0 Read/Write 0x0 0x13C PWM Comparison 0 Mode Update Register PWM_CMPMUPD0 Write-only – 0x140 PWM Comparison 1 Value Register PWM_CMPV1 Read/Write 0x0 0x144 PWM Comparison 1 Value Update Register PWM_CMPVUPD1 Write-only – 0x148 PWM Comparison 1 Mode Register PWM_CMPM1 Read/Write 0x0 0x14C PWM Comparison 1 Mode Update Register PWM_CMPMUPD1 Write-only – 0x150 PWM Comparison 2 Value Register PWM_CMPV2 Read/Write 0x0 0x154 PWM Comparison 2 Value Update Register PWM_CMPVUPD2 Write-only – 0x158 PWM Comparison 2 Mode Register PWM_CMPM2 Read/Write 0x0 0x15C PWM Comparison 2 Mode Update Register PWM_CMPMUPD2 Write-only – 0x160 PWM Comparison 3 Value Register PWM_CMPV3 Read/Write 0x0 0x164 PWM Comparison 3 Value Update Register PWM_CMPVUPD3 Write-only – 0x168 PWM Comparison 3 Mode Register PWM_CMPM3 Read/Write 0x0 0x16C PWM Comparison 3 Mode Update Register PWM_CMPMUPD3 Write-only – 0x170 PWM Comparison 4 Value Register PWM_CMPV4 Read/Write 0x0 0x174 PWM Comparison 4 Value Update Register PWM_CMPVUPD4 Write-only – 0x178 PWM Comparison 4 Mode Register PWM_CMPM4 Read/Write 0x0 0x17C PWM Comparison 4 Mode Update Register PWM_CMPMUPD4 Write-only – 0x180 PWM Comparison 5 Value Register PWM_CMPV5 Read/Write 0x0 0x184 PWM Comparison 5 Value Update Register PWM_CMPVUPD5 Write-only – 0x188 PWM Comparison 5 Mode Register PWM_CMPM5 Read/Write 0x0 0x18C PWM Comparison 5 Mode Update Register PWM_CMPMUPD5 Write-only – 0x190 PWM Comparison 6 Value Register PWM_CMPV6 Read/Write 0x0 0x194 PWM Comparison 6 Value Update Register PWM_CMPVUPD6 Write-only – 0x198 PWM Comparison 6 Mode Register PWM_CMPM6 Read/Write 0x0 0x19C PWM Comparison 6 Mode Update Register PWM_CMPMUPD6 Write-only – 0x1A0 PWM Comparison 7 Value Register PWM_CMPV7 Read/Write 0x0 0x1A4 PWM Comparison 7 Value Update Register PWM_CMPVUPD7 Write-only – 0x1A8 PWM Comparison 7 Mode Register PWM_CMPM7 Read/Write 0x0 0x1AC PWM Comparison 7 Mode Update Register PWM_CMPMUPD7 Write-only – 0x1B0–0x1FC Reserved – – – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1570 Table 48-6. Register Mapping (Continued) Offset Register Name Access Reset 0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register(1) PWM_CMR Read/Write 0x0 0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register(1) PWM_CDTY Read/Write 0x0 0x200 + ch_num * 0x20 + 0x08 PWM Channel Duty Cycle Update Register(1) PWM_CDTYUPD Write-only – 0x200 + ch_num * 0x20 + 0x0C PWM Channel Period Register(1) PWM_CPRD Read/Write 0x0 0x200 + ch_num * 0x20 + 0x10 PWM Channel Period Update Register(1) PWM_CPRDUPD Write-only – 0x200 + ch_num * 0x20 + 0x14 PWM Channel Counter Register(1) PWM_CCNT Read-only 0x0 0x200 + ch_num * 0x20 + 0x18 PWM Channel Dead Time Register(1) PWM_DT Read/Write 0x0 0x200 + ch_num * 0x20 + 0x1C PWM Channel Dead Time Update Register(1) PWM_DTUPD Write-only – Notes: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1571 48.7.1 PWM Clock Register Name: PWM_CLK Address: 0xF002C000 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 PREB 19 18 10 DIVB 15 – 14 – 13 – 12 – 11 7 6 5 4 3 PREA 2 DIVA This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the “PWM Write Protection Status Register” . • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2–255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor. • PREA, PREB: CLKA, CLKB Source Clock Selection PREA, PREB Divider Input Clock 0 0 0 0 MCK 0 0 0 1 MCK/2 0 0 1 0 MCK/4 0 0 1 1 MCK/8 0 1 0 0 MCK/16 0 1 0 1 MCK/32 0 1 1 0 MCK/64 0 1 1 1 MCK/128 1 0 0 0 MCK/256 1 0 0 1 MCK/512 1 0 1 0 MCK/1024 Other Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1572 48.7.2 PWM Enable Register Name: PWM_ENA Address: 0xF002C004 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: No effect. 1: Enable PWM output for channel x. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1573 48.7.3 PWM Disable Register Name: PWM_DIS Address: 0xF002C008 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the “PWM Write Protection Status Register” . • CHIDx: Channel ID 0: No effect. 1: Disable PWM output for channel x. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1574 48.7.4 PWM Status Register Name: PWM_SR Address: 0xF002C00C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0: PWM output for channel x is disabled. 1: PWM output for channel x is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1575 48.7.5 PWM Interrupt Enable Register 1 Name: PWM_IER1 Address: 0xF002C010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x Interrupt Enable • FCHIDx: Fault Protection Trigger on Channel x Interrupt Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1576 48.7.6 PWM Interrupt Disable Register 1 Name: PWM_IDR1 Address: 0xF002C014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x Interrupt Disable • FCHIDx: Fault Protection Trigger on Channel x Interrupt Disable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1577 48.7.7 PWM Interrupt Mask Register 1 Name: PWM_IMR1 Address: 0xF002C018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x Interrupt Mask • FCHIDx: Fault Protection Trigger on Channel x Interrupt Mask SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1578 48.7.8 PWM Interrupt Status Register 1 Name: PWM_ISR1 Address: 0xF002C01C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Counter Event on Channel x 0: No new counter event has occurred since the last read of the PWM_ISR1. 1: At least one counter event has occurred since the last read of the PWM_ISR1. • FCHIDx: Fault Protection Trigger on Channel x 0: No new trigger of the fault protection since the last read of the PWM_ISR1. 1: At least one trigger of the fault protection since the last read of the PWM_ISR1. Note: Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1579 48.7.9 PWM Sync Channels Mode Register Name: PWM_SCM Address: 0xF002C020 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 16 UPDM This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the “PWM Write Protection Status Register” . • SYNCx: Synchronous Channel x 0: Channel x is not a synchronous channel. 1: Channel x is a synchronous channel. • UPDM: Synchronous Channels Update Mode Value Name Description 0 MODE0 Manual write of double buffer registers and manual update of synchronous channels(1) 1 MODE1 Manual write of double buffer registers and automatic update of synchronous channels(2) Notes: 1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in “PWM Sync Channels Update Control Register” is set. 2. The update occurs when the Update Period is elapsed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1580 48.7.10 PWM Sync Channels Update Control Register Name: PWM_SCUC Address: 0xF002C028 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 UPDULOCK • UPDULOCK: Synchronous Channels Update Unlock 0: No effect 1: If the UPDM field is set to ‘0’ in “PWM Sync Channels Mode Register” , writing the UPDULOCK bit to ‘1’ triggers the update of the period value, the duty-cycle and the dead-time values of synchronous channels at the beginning of the next PWM period. If the field UPDM is set to ‘1’ or ‘2’, writing the UPDULOCK bit to ‘1’ triggers only the update of the period value and of the dead-time values of synchronous channels. This bit is automatically reset when the update is done. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1581 48.7.11 PWM Sync Channels Update Period Register Name: PWM_SCUP Address: 0xF002C02C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UPRCNT UPR • UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register” ). This time is equal to UPR+1 periods of the synchronous channels. • UPRCNT: Update Period Counter Reports the value of the Update Period Counter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1582 48.7.12 PWM Sync Channels Update Period Update Register Name: PWM_SCUPUPD Address: 0xF002C030 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels. • UPRUPD: Update Period Update Defines the wanted time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in “PWM Sync Channels Mode Register” ). This time is equal to UPR+1 periods of the synchronous channels. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1583 48.7.13 PWM Interrupt Enable Register 2 Name: PWM_IER2 Address: 0xF002C034 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY • WRDY: Write Ready for Synchronous Channels Update Interrupt Enable • UNRE: Synchronous Channels Update Underrun Error Interrupt Enable • CMPMx: Comparison x Match Interrupt Enable • CMPUx: Comparison x Update Interrupt Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1584 48.7.14 PWM Interrupt Disable Register 2 Name: PWM_IDR2 Address: 0xF002C038 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY • WRDY: Write Ready for Synchronous Channels Update Interrupt Disable • UNRE: Synchronous Channels Update Underrun Error Interrupt Disable • CMPMx: Comparison x Match Interrupt Disable • CMPUx: Comparison x Update Interrupt Disable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1585 48.7.15 PWM Interrupt Mask Register 2 Name: PWM_IMR2 Address: 0xF002C03C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY • WRDY: Write Ready for Synchronous Channels Update Interrupt Mask • UNRE: Synchronous Channels Update Underrun Error Interrupt Mask • CMPMx: Comparison x Match Interrupt Mask • CMPUx: Comparison x Update Interrupt Mask SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1586 48.7.16 PWM Interrupt Status Register 2 Name: PWM_ISR2 Address: 0xF002C040 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY • WRDY: Write Ready for Synchronous Channels Update 0: New duty-cycle and dead-time values for the synchronous channels cannot be written. 1: New duty-cycle and dead-time values for the synchronous channels can be written. • UNRE: Synchronous Channels Update Underrun Error 0: No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. 1: At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. • CMPMx: Comparison x Match 0: The comparison x has not matched since the last read of the PWM_ISR2 register. 1: The comparison x has matched at least one time since the last read of the PWM_ISR2 register. • CMPUx: Comparison x Update 0: The comparison x has not been updated since the last read of the PWM_ISR2 register. 1: The comparison x has been updated at least one time since the last read of the PWM_ISR2 register. Note: Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1587 48.7.17 PWM Output Override Value Register Name: PWM_OOV Address: 0xF002C044 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OOVL3 18 OOVL2 17 OOVL1 16 OOVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OOVH3 2 OOVH2 1 OOVH1 0 OOVH0 • OOVHx: Output Override Value for PWMH output of the channel x 0: Override value is 0 for PWMH output of channel x. 1: Override value is 1 for PWMH output of channel x. • OOVLx: Output Override Value for PWML output of the channel x 0: Override value is 0 for PWML output of channel x. 1: Override value is 1 for PWML output of channel x. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1588 48.7.18 PWM Output Selection Register Name: PWM_OS Address: 0xF002C048 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSL3 18 OSL2 17 OSL1 16 OSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSH3 2 OSH2 1 OSH1 0 OSH0 • OSHx: Output Selection for PWMH output of the channel x 0: Dead-time generator output DTOHx selected as PWMH output of channel x. 1: Output override value OOVHx selected as PWMH output of channel x. • OSLx: Output Selection for PWML output of the channel x 0: Dead-time generator output DTOLx selected as PWML output of channel x. 1: Output override value OOVLx selected as PWML output of channel x. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1589 48.7.19 PWM Output Selection Set Register Name: PWM_OSS Address: 0xF002C04C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSL3 18 OSSL2 17 OSSL1 16 OSSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSH3 2 OSSH2 1 OSSH1 0 OSSH0 • OSSHx: Output Selection Set for PWMH output of the channel x 0: No effect. 1: Output override value OOVHx selected as PWMH output of channel x. • OSSLx: Output Selection Set for PWML output of the channel x 0: No effect. 1: Output override value OOVLx selected as PWML output of channel x. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1590 48.7.20 PWM Output Selection Clear Register Name: PWM_OSC Address: 0xF002C050 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCL3 18 OSCL2 17 OSCL1 16 OSCL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCH3 2 OSCH2 1 OSCH1 0 OSCH0 • OSCHx: Output Selection Clear for PWMH output of the channel x 0: No effect. 1: Dead-time generator output DTOHx selected as PWMH output of channel x. • OSCLx: Output Selection Clear for PWML output of the channel x 0: No effect. 1: Dead-time generator output DTOLx selected as PWML output of channel x. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1591 48.7.21 PWM Output Selection Set Update Register Name: PWM_OSSUPD Address: 0xF002C054 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSUPL3 18 OSSUPL2 17 OSSUPL1 16 OSSUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSUPH3 2 OSSUPH2 1 OSSUPH1 0 OSSUPH0 • OSSUPHx: Output Selection Set for PWMH output of the channel x 0: No effect. 1: Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period. • OSSUPLx: Output Selection Set for PWML output of the channel x 0: No effect. 1: Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1592 48.7.22 PWM Output Selection Clear Update Register Name: PWM_OSCUPD Address: 0xF002C058 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCUPL3 18 OSCUPL2 17 OSCUPL1 16 OSCUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCUPH3 2 OSCUPH2 1 OSCUPH1 0 OSCUPH0 • OSCUPHx: Output Selection Clear for PWMH output of the channel x 0: No effect. 1: Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period. • OSCUPLx: Output Selection Clear for PWML output of the channel x 0: No effect. 1: Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1593 48.7.23 PWM Fault Mode Register Name: PWM_FMR Address: 0xF002C05C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 FFIL 15 14 13 12 FMOD 7 6 5 4 FPOL This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the “PWM Write Protection Status Register” . • FPOL: Fault Polarity For each field bit y (fault input number): 0: The fault y becomes active when the fault input y is at 0. 1: The fault y becomes active when the fault input y is at 1. • FMOD: Fault Activation Mode For each field bit y (fault input number): 0: The fault y is active until the Fault condition is removed at the peripheral(1) level. 1: The fault y stays active until the Fault condition is removed at the peripheral(1) level AND until it is cleared in the “PWM Fault Clear Register” . Note: 1. The Peripheral generating the fault. • FFIL: Fault Filtering For each field bit y (fault input number): 0: The fault input y is not filtered. 1: The fault input y is filtered. CAUTION: To prevent an unexpected activation of the status flag FSy in the “PWM Fault Status Register” , the bit FMODy can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1594 48.7.24 PWM Fault Status Register Name: PWM_FSR Address: 0xF002C060 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 FS 7 6 5 4 FIV • FIV: Fault Input Value For each field bit y (fault input number): 0: The current sampled value of the fault input y is 0 (after filtering if enabled). 1: The current sampled value of the fault input y is 1 (after filtering if enabled). • FS: Fault Status For each field bit y (fault input number): 0: The fault y is not currently active. 1: The fault y is currently active. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1595 48.7.25 PWM Fault Clear Register Name: PWM_FCR Address: 0xF002C064 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 FCLR • FCLR: Fault Clear For each field bit y (fault input number): 0: No effect. 1: If bit y of FMOD field is set to ‘1’ and if the fault input y is not at the level defined by the bit y of FPOL field, the fault y is cleared and becomes inactive (FMOD and FPOL fields belong to “PWM Fault Mode Register” ), else writing this bit to ‘1’ has no effect. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1596 48.7.26 PWM Fault Protection Value Register Name: PWM_FPV Address: 0xF002C068 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPVL3 18 FPVL2 17 FPVL1 16 FPVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPVH3 2 FPVH2 1 FPVH1 0 FPVH0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the “PWM Write Protection Status Register” . • FPVHx: Fault Protection Value for PWMH output on channel x 0: PWMH output of channel x is forced to ‘0’ when fault occurs. 1: PWMH output of channel x is forced to ‘1’ when fault occurs. • FPVLx: Fault Protection Value for PWML output on channel x 0: PWML output of channel x is forced to ‘0’ when fault occurs. 1: PWML output of channel x is forced to ‘1’ when fault occurs. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1597 48.7.27 PWM Fault Protection Enable Register Name: PWM_FPE Address: 0xF002C06C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the “PWM Write Protection Status Register” . Only the first 1 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant. • FPEx: Fault Protection Enable for channel x For each field bit y (fault input number): 0: Fault y is not used for the Fault Protection of channel x. 1: Fault y is used for the Fault Protection of channel x. CAUTION: To prevent an unexpected activation of the Fault Protection, the bit y of FPEx field can be set to ‘1’ only if the corresponding FPOL field has been previously configured to its final value in “PWM Fault Mode Register” . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1598 48.7.28 PWM Event Line x Register Name: PWM_ELMRx Address: 0xF002C07C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CSEL7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0 • CSELy: Comparison y Selection 0: A pulse is not generated on the event line x when the comparison y matches. 1: A pulse is generated on the event line x when the comparison y match. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1599 48.7.29 PWM Stepper Motor Mode Register Name: PWM_SMMR Address: 0xF002C0B0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 DOWN1 16 DOWN0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 GCEN1 0 GCEN0 • GCENx: Gray Count ENable 0: Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1] 1: enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1. • DOWNx: DOWN Count 0: Up counter. 1: Down counter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1600 48.7.30 PWM Write Protection Control Register Name: PWM_WPCR Address: 0xF002C0E4 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WPRG1 2 WPRG0 1 0 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 WPRG5 6 WPRG4 5 WPRG3 4 WPRG2 WPCMD • WPCMD: Write Protect Command This command is performed only if the WPKEY value is correct (0x50574D, “PWM” in ASCCII). Value Name 0 DISABLE_SW_PROT Disable the Software Write Protect of the register groups of which the bit WPRGx is at ‘1’. 1 ENABLE_SW_PROT Enable the Software Write Protect of the register groups of which the bit WPRGx is at ‘1’. ENABLE_HW_PROT Enable the Hardware Write Protect of the register groups of which the bit WPRGx is at ‘1’. Only a hardware reset of the PWM controller can disable the hardware write protect. Moreover, to meet security requirements, the PIO lines associated with PWM can not be configured through the PIO interface. 2 Description • WPRGx: Write Protect Register Group x 0: The WPCMD command has no effect on the register group x. 1: The WPCMD command is applied to the register group x. • WPKEY: Write Protect Key Value Name 0x50574D PASSWD Description Writing any other value in this field aborts the write operation of the WPCMD field. Always reads as 0 List of register groups: • Register group 0: – “PWM Clock Register” on page 1572 • Register group 1: – “PWM Disable Register” on page 1574 • Register group 2: – “PWM Sync Channels Mode Register” on page 1580 – “PWM Channel Mode Register” on page 1608 – “PWM Stepper Motor Mode Register” on page 1600 • Register group 3: SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1601 – “PWM Channel Period Register” on page 1612 – “PWM Channel Period Update Register” on page 1613 • Register group 4: – “PWM Channel Dead Time Register” on page 1615 – “PWM Channel Dead Time Update Register” on page 1616 • Register group 5: – “PWM Fault Mode Register” on page 1594 – “PWM Fault Protection Value Register” on page 1597 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1602 48.7.31 PWM Write Protection Status Register Name: PWM_WPSR Address: 0xF002C0E8 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 WPVSRC 23 22 21 20 WPVSRC 15 – 14 – 13 WPHWS5 12 WPHWS4 11 WPHWS3 10 WPHWS2 9 WPHWS1 8 WPHWS0 7 WPVS 6 – 5 WPSWS5 4 WPSWS4 3 WPSWS3 2 WPSWS2 1 WPSWS1 0 WPSWS0 • WPSWSx: Write Protect SW Status 0: The Write Protect SW x of the register group x is disabled. 1: The Write Protect SW x of the register group x is enabled. • WPHWSx: Write Protect HW Status 0: The Write Protect HW x of the register group x is disabled. 1: The Write Protect HW x of the register group x is enabled. • WPVS: Write Protect Violation Status 0: No Write Protect violation has occurred since the last read of the PWM_WPSR. 1: At least one Write Protect violation has occurred since the last read of the PWM_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset) in which a write access has been attempted. Note: The two LSBs of the address offset of the write-protected register are not reported Note: Reading PWM_WPSR automatically clears WPVS and WPVSRC fields. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1603 48.7.32 PWM Comparison x Value Register Name: PWM_CMPVx Address: 0xF002C130 [0], 0xF002C140 [1], 0xF002C150 [2], 0xF002C160 [3], 0xF002C170 [4], 0xF002C180 [5], 0xF002C190 [6], 0xF002C1A0 [7] Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVM 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 16 bits (channel counter size) of field CV are significant. • CV: Comparison x Value Define the comparison x value to be compared with the counter of the channel 0. • CVM: Comparison x Value Mode 0: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing. 1: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing. Note: This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in “PWM Channel Mode Register” on page 1608) SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1604 48.7.33 PWM Comparison x Value Update Register Name: PWM_CMPVUPDx Address: 0xF002C134 [0], 0xF002C144 [1], 0xF002C154 [2], 0xF002C164 [3], 0xF002C174 [4], 0xF002C184 [5], 0xF002C194 [6], 0xF002C1A4 [7] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 CVMUPD 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match. Only the first 16 bits (channel counter size) of field CVUPD are significant. • CVUPD: Comparison x Value Update Define the comparison x value to be compared with the counter of the channel 0. • CVMUPD: Comparison x Value Mode Update 0: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing. 1: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing. Note: This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in “PWM Channel Mode Register” ) CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1605 48.7.34 PWM Comparison x Mode Register Name: PWM_CMPMx Address: 0xF002C138 [0], 0xF002C148 [1], 0xF002C158 [2], 0xF002C168 [3], 0xF002C178 [4], 0xF002C188 [5], 0xF002C198 [6], 0xF002C1A8 [7] Access: Read/Write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 21 20 19 18 CUPRCNT 15 14 13 6 24 – 17 16 9 8 1 – 0 CEN CUPR 12 11 10 CPRCNT 7 25 – CPR 5 4 CTR 3 – 2 – • CEN: Comparison x Enable 0: The comparison x is disabled and can not match. 1: The comparison x is enabled and can match. • CTR: Comparison x Trigger The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR. • CPR: Comparison x Period CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter. • CPRCNT: Comparison x Period Counter Reports the value of the comparison x period counter. Note: The field CPRCNT is read-only • CUPR: Comparison x Update Period Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter. • CUPRCNT: Comparison x Update Period Counter Reports the value of the comparison x update period counter. Note: The field CUPRCNT is read-only SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1606 48.7.35 PWM Comparison x Mode Update Register Name: PWM_CMPMUPDx Address: 0xF002C13C [0], 0xF002C14C [1], 0xF002C15C [2], 0xF002C16C [3], 0xF002C17C [4], 0xF002C18C [5], 0xF002C19C [6], 0xF002C1AC [7] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 – 11 7 6 5 4 3 – CTRUPD 25 – 24 – 17 16 9 8 1 – 0 CENUPD CUPRUPD 10 CPRUPD 2 – This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x match. • CENUPD: Comparison x Enable Update 0: The comparison x is disabled and can not match. 1: The comparison x is enabled and can match. • CTRUPD: Comparison x Trigger Update The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR. • CPRUPD: Comparison x Period Update CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter. • CUPRUPD: Comparison x Update Period Update Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1607 48.7.36 PWM Channel Mode Register Name: PWM_CMRx [x=0..3] Address: 0xF002C200 [0], 0xF002C220 [1], 0xF002C240 [2], 0xF002C260 [3] Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 DTLI 17 DTHI 16 DTE 15 – 14 – 13 – 12 – 11 – 10 CES 9 CPOL 8 CALG 7 – 6 – 5 – 4 – 3 2 1 0 CPRE This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the “PWM Write Protection Status Register” . • CPRE: Channel Pre-scaler Value Name Description 0b0000 MCK Master clock 0b0001 MCK_DIV_2 Master clock/2 0b0010 MCK_DIV_4 Master clock/4 0b0011 MCK_DIV_8 Master clock/8 0b0100 MCK_DIV_16 Master clock/16 0b0101 MCK_DIV_32 Master clock/32 0b0110 MCK_DIV_64 Master clock/64 0b0111 MCK_DIV_128 Master clock/128 0b1000 MCK_DIV_256 Master clock/256 0b1001 MCK_DIV_512 Master clock/512 0b1010 MCK_DIV_1024 Master clock/1024 0b1011 CLKA Clock A 0b1100 CLKB Clock B • CALG: Channel Alignment 0: The period is left aligned. 1: The period is center aligned. • CPOL: Channel Polarity 0: The OCx output waveform (output from the comparator) starts at a low level. 1: The OCx output waveform (output from the comparator) starts at a high level. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1608 • CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in “PWM Interrupt Status Register 1” ). CALG = 0 (Left Alignment): 0/1: The channel counter event occurs at the end of the PWM period. CALG = 1 (Center Alignment): 0: The channel counter event occurs at the end of the PWM period. 1: The channel counter event occurs at the end of the PWM period and at half the PWM period. • DTE: Dead-Time Generator Enable 0: The dead-time generator is disabled. 1: The dead-time generator is enabled. • DTHI: Dead-Time PWMHx Output Inverted 0: The dead-time PWMHx output is not inverted. 1: The dead-time PWMHx output is inverted. • DTLI: Dead-Time PWMLx Output Inverted 0: The dead-time PWMLx output is not inverted. 1: The dead-time PWMLx output is inverted. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1609 48.7.37 PWM Channel Duty Cycle Register Name: PWM_CDTYx [x=0..3] Address: 0xF002C204 [0], 0xF002C224 [1], 0xF002C244 [2], 0xF002C264 [3] Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (channel counter size) are significant. • CDTY: Channel Duty-Cycle Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1610 48.7.38 PWM Channel Duty Cycle Update Register Name: PWM_CDTYUPDx [x=0..3] Address: 0xF002C208 [0], 0xF002C228 [1], 0xF002C248 [2], 0xF002C268 [3] Access: Write-only. 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle. Only the first 16 bits (channel counter size) are significant. • CDTYUPD: Channel Duty-Cycle Update Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1611 48.7.39 PWM Channel Period Register Name: PWM_CPRDx [x=0..3] Address: 0xF002C20C [0], 0xF002C22C [1], 0xF002C24C [2], 0xF002C26C [3] Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the “PWM Write Protection Status Register” . Only the first 16 bits (channel counter size) are significant. • CPRD: Channel Period If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (-----------------------------X × CPRD )MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (----------------------------------------CRPD × DIVA )( CRPD × DIVB ) or -----------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (---------------------------------------2 × X × CPRD ) MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (--------------------------------------------------2 × CPRD × DIVA ) ( 2 × CPRD × DIVB ) or --------------------------------------------------MCK MCK SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1612 48.7.40 PWM Channel Period Update Register Name: PWM_CPRDUPDx [x=0..3] Address: 0xF002C210 [0], 0xF002C230 [1], 0xF002C250 [2], 0xF002C270 [3] Access: Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRDUPD 15 14 13 12 CPRDUPD 7 6 5 4 CPRDUPD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the “PWM Write Protection Status Register” . This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform period. Only the first 16 bits (channel counter size) are significant. • CPRDUPD: Channel Period Update If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (-------------------------------------------X × CPRDUPD ) MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (------------------------------------------------------CRPDUPD × DIVA )( CRPDUPD × DIVB ) or -------------------------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: (----------------------------------------------------2 × X × CPRDUPD -) MCK – By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (---------------------------------------------------------------2 × CPRDUPD × DIVA -) ( 2 × CPRDUPD × DIVB ) or ----------------------------------------------------------------MCK MCK SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1613 48.7.41 PWM Channel Counter Register Name: PWM_CCNTx [x=0..3] Address: 0xF002C214 [0], 0xF002C234 [1], 0xF002C254 [2], 0xF002C274 [3] Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 16 bits (channel counter size) are significant. • CNT: Channel Counter Register Channel counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register). • the channel counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1614 48.7.42 PWM Channel Dead Time Register Name: PWM_DTx [x=0..3] Address: 0xF002C218 [0], 0xF002C238 [1], 0xF002C258 [2], 0xF002C278 [3] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the “PWM Write Protection Status Register” . Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant. • DTH: Dead-Time Value for PWMHx Output Defines the dead-time value for PWMHx output. This value must be defined between 0 and CPRD-CDTY (PWM_CPRx and PWM_CDTYx). • DTL: Dead-Time Value for PWMLx Output Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1615 48.7.43 PWM Channel Dead Time Update Register Name: PWM_DTUPDx [x=0..3] Address: 0xF002C21C [0], 0xF002C23C [1], 0xF002C25C [2], 0xF002C27C [3] Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the “PWM Write Protection Status Register” . This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the dead-time values. Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant. • DTHUPD: Dead-Time Value Update for PWMHx Output Defines the dead-time value for PWMHx output. This value must be defined between 0 and CPRD-CDTY (PWM_CPRx and PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period. • DTLUPD: Dead-Time Value Update for PWMLx Output Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1616 49. Analog-to-Digital Converter (ADC) 49.1 Description The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to Figure 49-1, "Analog-to-Digital Converter Block Diagram". It also integrates a 12-to-1 analog multiplexer, making possible the analogto-digital conversions of 12 analog lines. The conversions extend from 0V to the voltage carried on pin ADVREF. Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given range or outside the range, thresholds and ranges being fully configurable. The ADC Controller internal fault output is directly connected to PWM Fault input. This input can be asserted by means of comparison circuitry in order to immediately put the PWM outputs in a safe state (pure combinational path). The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a DMA channel. These features reduce both power consumption and processor intervention. This ADC has a selectable single-ended or fully differential input and benefits from a 2-bit programmable gain. A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is employed in order to reduce INL and DNL errors. Finally, the user can configure ADC timings, such as Startup Time and Tracking Time. This ADC Controller includes a Resistive Touchscreen Controller. It supports 4-wire and 5-wire technologies. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1617 49.2 Embedded Characteristics  12-bit Resolution  1 MHz Conversion Rate  Wide Range Power Supply Operation  Selectable Single Ended or Differential Input Voltage  Programmable Gain For Maximum Full Scale Input Range 0 - VDD  Resistive 4-wire and 5-wire Touchscreen Controller  Position and Pressure Measurement for 4-wire screens  Position Measurement for 5-wire screens  Average of up to 8 measures for noise filtering  Programmable Pen Detection sensitivity  Integrated Multiplexer Offering Up to 12 Independent Analog Inputs  Individual Enable and Disable of Each Channel  Hardware or Software Trigger  External Trigger Pin  Timer Counter Outputs (Corresponding TIOA Trigger)  Internal Trigger Counter  Trigger on Pen Contact Detection  PWM Event Line  Drive of PWM Fault Input  DMA Support  Possibility of ADC Timings Configuration  Two Sleep Modes and Conversion Sequencer   Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels  Possibility of Customized Channel Sequence Standby Mode for Fast Wakeup Time Response  Power Down Capability  Automatic Window Comparison of Converted Values  Write Protect Registers SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1618 49.3 Block Diagram Figure 49-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels PMC MCK ADC Controller Trigger Selection ADTRG ADC Interrupt Control Logic ADC cell Interrupt Controller VDDANA ADVREF SOC AD0/XP/UL Touchscreen Analog Inputs 0 AD1/XM/UR Touchscreen Switches AD2/YP/LL AD3/YM/Sense System Bus User Interface Cyclic Pipeline 1 12-bit Analog-to-Digital Converter 2 DMA Peripheral Bridge 3 AD4/LR 4 PIO VIN+ VIN- OFFSET S/H PGA APB AD- Other Analog Inputs AD- CHx AD- GND 49.4 Signal Description Table 49-1. ADC Pin Description Pin Name Description VDDANA Analog power supply ADVREF Reference voltage AD0 - AD11 Analog input channels ADTRG External trigger SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1619 49.5 Product Dependencies 49.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 49.5.2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADC interrupt requires the interrupt controller to be programmed first. Table 49-2. Peripheral IDs Instance ID ADC 29 49.5.3 Analog Inputs The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND. 49.5.4 I/O Lines The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function. Table 49-3. I/O Lines Instance Signal I/O Line Peripheral ADC ADTRG PD19 A ADC AD0 PD20 A ADC AD1 PD21 A ADC AD2 PD22 A ADC AD3 PD23 A ADC AD4 PD24 A ADC AD5 PD25 A ADC AD6 PD26 A ADC AD7 PD27 A ADC AD8 PD28 A ADC AD9 PD29 A ADC AD10 PD30 A ADC AD11 PD31 A 49.5.5 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be unconnected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1620 49.5.6 PWM Event Line PWM Event Lines may or may not be used as hardware triggers depending on user requirements. 49.5.7 Fault Output The ADC Controller has the FAULT output connected to the FAULT input of PWM. Please refer to Section 49.7.11 ”Fault Output” and implementation of the PWM in the product. 49.5.8 Conversion Performances For performance and electrical characteristics of the ADC, see the product electrical characteristics. 49.6 Functional Description 49.6.1 Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 12-bit digital data requires Tracking Clock cycles as defined in the field TRACKTIM of the “ADC Mode Register” on page 1646. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The tracking phase starts during the conversion of the previous channel. If the tracking time is longer than the conversion time, the tracking phase is extended to the end of the previous conversion. The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/512, if PRESCAL is set to 255 (0xFF). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the product Electrical Characteristics section. Figure 49-2. Sequence of ADC conversions when Tracking time > Conversion time ADCClock Trigger event (Hard or Soft) ADC_ON Commands from controller to analog cell ADC_Start ADC_SEL CH0 CH1 CH2 LCDR CH0 CH1 DRDY Start Up Transfer Period Time (and tracking of CH0) Conversion of CH0 Tracking of CH1 Transfer Period Conversion of CH1 Tracking of CH2 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1621 Figure 49-3. Sequence of ADC conversions when Tracking time < Conversion time Read the ADC_LCDR ADCClock Trigger event (Hard or Soft) ADC_ON Commands from controller to analog cell ADC_Start ADC_SEL CH0 CH1 LCDR CH3 CH2 CH0 CH1 CH2 DRDY Start Up Time & Tracking of CH0 Transfer Period Conversion of CH0 & Tracking of CH1 Transfer Period Conversion of CH1 & Tracking of CH2 Transfer Period Conversion of CH2 & Tracking of CH3 49.6.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 49.6.3 Conversion Resolution The ADC supports 12-bit resolutions. 49.6.4 Conversion Results When a conversion is completed, the resulting 12-bit digital value is stored in the Channel Data Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data in the CHNB field. The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected DMA channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1622 Figure 49-4. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) DRDY (ADC_SR) If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is set in the Overrun Status Register (ADC_OVER). Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR. The OVREx flag is automatically cleared when ADC_OVER is read, and GOVRE flag is automatically cleared when ADC_SR is read. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1623 Figure 49-5. GOVRE and OVREx Flag Behavior Trigger event CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR Undefined Data ADC_CDR0 Undefined Data ADC_CDR1 EOC0 (ADC_SR) EOC1 (ADC_SR) GOVRE (ADC_SR) Data B Data A Data C Data A Undefined Data Data C Data B Conversion A Conversion C Conversion B Read ADC_CDR0 Read ADC_CDR1 Read ADC_SR DRDY (ADC_SR) Read ADC_OVER OVRE0 (ADC_OVER) OVRE1 (ADC_OVER) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1624 49.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the Mode Register (ADC_MR). The selected hardware trigger is enabled if TRGMOD=1,2 or 3 in “ADC Trigger Register”. The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2. The hardware trigger can be selected by the TRGMOD field in the “ADC Trigger Register” between:  any edge, either rising or falling or both, detected on the external trigger pin, TSADTRG. The hardware trigger source is selected with the TRGSEL field in the Mode Register (ADC_MR). The selected hardware trigger is enabled if TRGMOD=1,2 or 3 in “ADC Trigger Register”.  the Pen Detect, depending on how the PENDET bit is set in the “ADC Touchscreen Mode Register”.  a continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it finishes the current one  a periodic trigger, which is defined by programming the TRGPER field in the “ADC Trigger Register”. The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR. If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a range of 2 MCK clock periods to 1 ADC clock period. Figure 49-6. Hardware Trigger Delay trigger start delay If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers permit the analog channels to be enabled or disabled independently. If the ADC is used with a DMA, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. 49.6.6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the SLEEP bit in the Mode Register ADC_MR. The Sleep mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. This mode can be used when the minimum period of time between 2 successive trigger events is greater than the startup period of Analog-Digital converter (See the product ADC Characteristics section). When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1625 A fast wake-up mode is available in the ADC Mode Register (ADC_MR) as a compromise between power saving strategy and responsiveness. Setting the FWUP bit to ‘1’ enables the fast wake-up mode. In fast wake-up mode the ADC cell is not fully deactivated while no conversion is requested, thereby providing less power saving but faster wakeup. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using the internal timer (ADC_TRGR register) or the PWM event line. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the DMA . The sequence can be customized by programming the Sequence Channel Registers, ADC_SEQR1 and ADC_SEQR2 and setting to 1 the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific order of channels and can program up to 12 conversions by sequence. The user is totally free to create a personal sequence, by writing channel numbers in ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be written in any sequence, channel numbers can be repeated several times. Only enabled sequence bitfields are converted, consequently to program a 15-conversion sequence, the user can simply put a disable in ADC_CHSR[15], thus disabling the 16THCH field of ADC_SEQR2. If all ADC channels (i.e. 12) are used on an application board, there is no restriction of usage of the user sequence. But as soon as some ADC channels are not enabled for conversion but rather used as pure digital inputs, the respective indexes of these channels cannot be used in the user sequence fields (ADC_SEQR1, ADC_SEQR2 bitfields). For example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQR1, ADC_SEQR2 register bitfields USCH1 up to USCH12 must not contain the value 4. Thus the length of the user sequence may be limited by this behavior. As an example, if only 4 channels over 12 (CH0 up to CH3) are selected for ADC conversions, the user sequence length cannot exceed 4 channels. Each trigger event may launch up to 4 successive conversions of any combination of channels 0 up to 3 but no more (i.e. in this case the sequence CH0, CH0, CH1, CH1, CH1 is impossible). A sequence that repeats several times the same channel requires more enabled channels than channels actually used for conversion. For example, a sequence like CH0, CH0, CH1, CH1 requires 4 enabled channels (4 free channels on application boards) whereas only CH0, CH1 are really converted. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. 49.6.7 Comparison Window The ADC Controller features automatic comparison functions. It compares converted values to a low threshold or a high threshold or both, according to the CMPMODE function chosen in the Extended Mode Register (ADC_EMR). The comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To compare all channels the CMP_ALL parameter of ADC_EMR should be set. Moreover a filtering option can be set by writing the number of consecutive comparison errors needed to raise the flag. This number can be written and read in the CMPFILTER field of ADC_EMR. The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt. The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (ADC_CWR). If the comparison window is to be used with LOWRES bit in ADC_MR set to 1, the thresholds do not need to be adjusted as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in consideration of the maximum ADC resolution. 49.6.8 Differential Inputs The ADC can be used either as a single ended ADC (DIFF bit equal to 0) or as a fully differential ADC (DIFF bit equal to 1) as shown in Figure 49-7. By default, after a reset, the ADC is in single ended mode. If ANACH is set in ADC_MR the ADC can apply a different mode on each channel. Otherwise the parameters of CH0 are applied to all channels. The same inputs are used in single ended or differential mode. In single ended mode, inputs are managed by a 16:1 channels analog multiplexer. In the fully differential mode, inputs are managed by an 8:1 channels analog multiplexer. See Table 49-4 and Table 49-5. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1626 Table 49-4. Input Pins and Channel Number in Single Ended Mode Input Pins Channel Number AD0 CH0 AD1 CH1 AD2 CH2 AD3 CH3 AD4 CH4 AD5 CH5 AD6 CH6 AD7 CH7 AD8 CH8 AD9 CH9 AD10 CH10 AD11 CH11 AD12 CH12 AD13 CH13 AD14 CH14 AD15 CH15 Table 49-5. Input Pins and Channel Number In Differential Mode Input Pins Channel Number AD0-AD1 CH0 AD2-AD3 CH2 AD4-AD5 CH4 AD6-AD7 CH6 AD8-AD9 CH8 AD10-AD11 CH10 AD12-AD13 CH12 AD14-AD15 CH14 49.6.9 Input Gain and Offset The ADC has a built in Programmable Gain Amplifier (PGA) and Programmable Offset. The Programmable Gain Amplifier can be set to gains of 1/2, 1, 2 and 4. The Programmable Gain Amplifier can be used either for single ended applications or for fully differential applications. If ANACH is set in ADC_MR the ADC can apply different gain and offset on each channel. Otherwise the parameters of CH0 are applied to all channels. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1627 The gain is configurable through the GAIN bit of the Channel Gain Register (ADC_CGR) as shown in Table 49-6. Table 49-6. Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit. GAIN GAIN (DIFF = 0) GAIN (DIFF = 1) 00 1 0.5 01 1 1 10 2 2 11 4 2 To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Channel Offset Register (ADC_COR). The Offset is only available in Single Ended Mode. Table 49-7. Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G) OFFSET Bit OFFSET (DIFF = 0) 0 0 1 (G-1)Vrefin/2 OFFSET (DIFF = 1) 0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1628 Figure 49-7. Analog Full Scale Ranges in Single Ended/Differential Applications Versus Gain and Offset single ended se0fd1=0 fully differential se0fd1=1 vrefin VIN+ VIN+ same as gain=1 gain=0.5 (½)vrefin (00) VIN- 0 vrefin (¾)vrefin VIN+ VIN+ gain=1 (½)vrefin VIN- (01) (¼)vrefin 0 vrefin offset=1 offset=0 (¾)vrefin (5/8)vrefin gain=2 (½)vrefin VIN+ (3/8)vrefin (10) VIN+ VIN+ VIN- (¼)vrefin 0 vrefin offset=1 gain=4 same as gain=2 offset=0 (5/8)vrefin VIN+ (½)vrefin (3/8)vrefin (11) VIN+ VIN+ VIN- (¼)vrefin (1/8)vrefin 0 49.6.10 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register, ADC_MR. A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1629 When the gain, offset or differential input parameters of the analog cell change between two channels, the analog cell may need a specific settling time before starting the tracking phase. In that case, the controller automatically waits during the settling time defined in the “ADC Mode Register”. Obviously, if the ANACH option is not set, this time is unused. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the TRACKTIM field. See the product ADC Characteristics section. 49.6.11 Automatic Calibration The ADC features an automatic calibration (AUTOCALIB) mode for gain errors (calibration). The automatic calibration sequence can be started at any time writing to '1' the AUTOCAL bit of the ADC Control Register. The automatic calibration sequence requires a software reset command (SWRST in the ADC_CR register) prior to write AUTOCAL bit. The end of calibration sequence is given by the EOCAL bit in the interrupt status register (ADC_ISR), and an interrupt is generated if EOCAL interrupt has been enabled (ADC_IER register). The calibration sequence will perform an automatic calibration on all enabled channels. The channels required for conversion do not need to be all enabled during the calibration process if they are programmed with the same gain. Only channels with different gain settings need to be enabled. The gain settings of all enabled channels must be set before starting the AUTOCALIB sequence. If the gain settings (ADC_CGR and ADC_COR registers) for a given channel are changed, the AUTOCALIB sequence must then be started again. The calibration data (on one or more enabled channels) is stored in the internal ADC memory. Then, when a new conversion is started (on one or more enabled channels), the converted value (in ADC_LCDR or ADC_CDRx registers) is a calibrated value. Autocalibration is for settings, not for channels. Therefore, if a specific combination of gain has been already calibrated, and a new channel with the same settings is enabled after the initial calibration, there is no need to restart a calibration. If different enabled channels have different gain settings, the corresponding channels must be enabled before starting the calibration. If a software reset is performed (SWRST bit in ADC_CR) or after power up (or wake-up from Backup mode), the calibration data in the ADC memory is lost. Changing the ADC running mode (in ADC_CR register) does not affect the calibration data. Changing the ADC reference voltage (ADVREF pin) requires a new calibration sequence. For calibration time, gain error after calibration, refer to the 12-bit ADC electrical characteristics section of the product. 49.7 Touchscreen 49.7.1 Touchscreen Mode The TSMODE parameter of “ADC Touchscreen Mode Register” is used to enable/disable the Touchscreen functionality, to select the type of screen (4-wire or 5-wire) and, in the case of a 4-wire screen, to activate (or not) the pressure measurement. In 4-wire mode, channel 0, 1, 2 and 3 must not be used for classic ADC conversions. Likewise, in 5-wire mode, channel 0, 1, 2, 3, and 4 must not be used for classic ADC conversions. 49.7.2 4-wire Resistive Touchscreen Principles A resistive touchscreen is based on two resistive films, each one being fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. In between, there is a layer acting as an insulator, but also enables contact when you press the screen. This is illustrated in Figure 49-8. The TSADC controller has the ability to perform without external components:  Position Measurement  Pressure Measurement  Pen Detection SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1630 Figure 49-8. Touchscreen Position Measurement Pen Contact XP YM YP XM VDD XP VDD YP YP XP Volt XM GND Vertical Position Detection Volt YM GND Horizontal Position Detection 49.7.3 4-wire Position Measurement Method As shown in Figure 49-8, to detect the position of a contact, a supply is first applied from top to bottom. Due to the linear resistance of the film, there is a voltage gradient from top to bottom. When a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film. If the input impedance on the right and left electrodes sense is high enough, the film does not affect this voltage, despite its resistive nature. For the horizontal direction, the same method is used, but by applying supply from left to right. The range depends on the supply voltage and on the loss in the switches that connect to the top and bottom electrodes. In an ideal world (linear, with no loss through switches), the horizontal position is equal to: VYM / VDD or VYP / VDD. The implementation with on-chip power switches is shown in Figure 49-9. The voltage measurement at the output of the switch compensates for the switches loss. It is possible to correct for switch loss by performing the operation: [VYP - VXM] / [VXP - VXM]. This requires additional measurements, as shown in Figure 49-9. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1631 Figure 49-9. Touchscreen Switches Implementation XP VDDANA 0 XM GND 1 To the ADC YP VDDANA 2 YM GND 3 VDDANA VDDANA Switch Resistor Switch Resistor YP XP XP YP YM XM Switch Resistor Switch Resistor GND Horizontal Position Detection GND Vertical Position Detection 49.7.4 4-wire Pressure Measurement Method The method to measure the pressure (Rp) applied to the touchscreen is based on the known resistance of the X-Panel resistance (Rxp). Three conversions (Xpos,Z1,Z2) are necessary to determine the value of Rp (Zaxis resistance). Rp = Rxp*(Xpos/1024)*[(Z2/Z1)-1] SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1632 Figure 49-10.Pressure Measurement VDDANA VDDANA VDDANA Switch Resistor Switch Resistor XP YP XP YP Rp Open circuit Switch Resistor XP YP Rp YM XM GND XPos Measure(Yp) Rp YM XM YM XM Open circuit Switch Resistor Switch Resistor Open circuit Switch Resistor GND GND Z1 Measure(Xp) Z2 Measure(Xp) 49.7.5 5-wire Resistive Touchscreen Principles To make a 5-wire touchscreen, a resistive layer with a contact point at each corner and a conductive layer are used. The 5-wire touchscreen differs from the 4-wire type mainly in that the voltage gradient is applied only to one layer, the resistive layer, while the other layer is the sense layer for both measurements. The measurement of the X position is obtained by biasing the upper left corner and lower left corner to VDDANA and the upper right corner and lower right to ground. To measure along the Y axis, bias the upper left corner and upper right corner to VDDANA and bias the lower left corner and lower right corner to ground. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1633 Figure 49-11.5-Wire principle UL Pen Contact Resistive layer UR Sense LL LR Conductive Layer UL VDDANA UR VDDANA for Yp GND for Xp Sense LL VDDANA for Xp GND for Yp LR GND 49.7.6 5-wire Position Measurement Method In an application only monitoring clicks, 100 points per second is typically needed. For handwriting or motion detection, the number of measurements to consider is approximately 200 points per second. This must take into account that multiple measurements are included (over sampling, filtering) to compute the correct point. The 5-wire touchscreen panel works by applying a voltage at the corners of the resistive layer and measuring the vertical or horizontal resistive network with the sense input. The ADC converts the voltage measured at the point the panel is touched. A measurement of the Y position of the pointing device is made by:  Connecting Upper left (UL) and upper right (UR) corners to VDDANA  Connecting Lower left (LL) and lower right (LR) corners to ground.  The voltage measured is determined by the voltage divider developed at the point of touch (Yposition) and the SENSE input is converted by ADC. A measurement of the X position of the pointing device is made by:  Connecting the upper left (UL) and lower left (LL) corners to ground  Connecting the upper right and lower right corners to VDDANA.  The voltage measured is determined by the voltage divider developed at the point of touch (Xposition) and the SENSE input is converted by ADC. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1634 Figure 49-12.Touchscreen Switches Implementation UL VDDANA 0 UR GND VDDANA 1 GND LL VDDANA Sense LR UL VDDANA 2 To the ADC 3 GND 4 UR VDDANA for Ypos GND for Xpos Sense LL VDDANA for Xpos GND for Ypos LR GND 49.7.7 Sequence and Noise Filtering The ADC Controller can manage ADC conversions and Touchscreen measurement. On each trigger event the sequence of ADC conversions is performed as described in Section 49.6.6 ”Sleep Mode and Conversion Sequencer”. The Touchscreen measure frequency can be specified in number of trigger events by writing the TSFREQ parameter in the “ADC Touchscreen Mode Register”. An internal counter counts triggers up to TSFREQ, and every time it rolls out, a Touchscreen sequence is appended to the classic ADC conversion sequence (see Figure 49-13). Additionally the user can average multiple Touchscreen measures by writing the TSAV parameter in the “ADC Touchscreen Mode Register”. This can be 1, 2, 4 or 8 measures performed on consecutive triggers as illustrated in Figure 49-13 bellow. Consequently, the TSFREQ parameter must be greater or equal to the TSAV parameter. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1635 Figure 49-13.Insertion of Touchscreen sequences (TSFREQ = 2; TSAV = 1) Trigger event ADC_SEL C T C T C C T C C: Classic ADC Conversion Sequence - C T C T: Touchscreen Sequence XRDY Read the ADC_XPOSR Read the ADC_XPOSR YRDY Read the ADC_YPOSR Read the ADC_YPOSR 49.7.8 Measured Values, Registers and Flags As soon as the controller finishes the Touchscreen sequence, XRDY, YRDY and PRDY are set and can generate an interrupt. These flags can be read in the “ADC Interrupt Status Register”. They are reset independently by reading in ADC_XPOSR, ADC_YPOSR and ADC_PRESSR. for classic ADC conversions. The “ADC Touchscreen X Position Register” presents XPOS (VX - VXmin) on its LSB and XSCALE (VXMAX - VXmin) aligned on the 16th bit. The “ADC Touchscreen Y Position Register” presents YPOS (VY - VYmin) on its LSB and YSCALE (VYMAX - VYmin) aligned on the 16th bit. To improve the quality of the measure, the user must calculate: XPOS/XSCALE and YPOS/YSCALE. VXMAX, VXmin, VYMAX, and VYmin are measured at the first start up of the controller. These values can change during use, so it can be necessary to refresh them. Refresh can be done by writing ‘1’ in the CALIB field of the control register (ADC_CR). The “ADC Touchscreen Pressure Register” presents Z1 on its LSB and Z2 aligned on the 16th bit. See Section 49.7.4 to know how use them. 49.7.9 Pen Detect Method When there is no contact, it is not necessary to perform a conversion. However, it is important to detect a contact by keeping the power consumption as low as possible. The implementation polarizes one panel by closing the switch on (XP/UL) and ties the horizontal panel by an embedded resistor connected to YM / Sense. This resistor is enabled by a fifth switch. Since there is no contact, no current is flowing and there is no related power consumption. As soon as a contact occurs, a current is flowing in the Touchscreen and a Schmitt trigger detects the voltage in the resistor. The Touchscreen Interrupt configuration is entered by programming the PENDET bit in the “ADC Touchscreen Mode Register”. If this bit is written at 1, the controller samples the pen contact state when it is not converting and waiting for a trigger. To complete the circuit, a programmable debouncer is placed at the output of the Schmitt trigger. This debouncer is programmable up to 215 ADC clock periods. The debouncer length can be selected by programming the field PENDBC in “ADC Touchscreen Mode Register”. Due to the analog switch’s structure, the debouncer circuitry is only active when no conversion (Touchscreen or classic ADC channels) is in progress. Thus, if the time between the end of a conversion sequence and the arrival of the next trigger event is lower than the debouncing time configured on PENDBC, the debouncer will not detect any contact. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1636 Figure 49-14.Touchscreen Pen Detect X+/UL X-/UR VDDANA 0 GND VDDANA 1 GND Y+/LL Y-/SENSE LR VDDANA 2 GND 3 GND 4 To the ADC PENDBC Debouncer Pen Interrupt GND The Touchscreen Pen Detect can be used to generate an ADC interrupt to wake up the system. The Pen Detect generates two types of status, reported in the “ADC Interrupt Status Register”:  the PEN bit is set as soon as a contact exceeds the debouncing time as defined by PENDBC and remains set until ADC_SR is read.  the NOPEN bit is set as soon as no current flows for a time over the debouncing time as defined by PENDBC and remains set until ADC_SR is read. Both bits are automatically cleared as soon as the Status Register (ADC_SR) is read, and can generate an interrupt by writing the “ADC Interrupt Enable Register”. Moreover, the rising of either one of them clears the other, they cannot be set at the same time. The PENS bit of the ADC_SR indicates the current status of the pen contact. 49.7.10 Buffer Structure The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR) the structure differs. Each data read to DMA buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register, the 4 most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better checking the DMA buffer integrity. As soon as touchscreen conversions are required, the pen detection function may help the post-processing of the buffer. To get more details refer to Section 49.7.10.4 ”Pen Detection Status”. 49.7.10.1 Classical ADC Channels Only When no touchscreen conversion is required (i.e. TSMODE = 0 in ADC_TSMR register), the structure of data within the buffer is defined by the ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2 registers. If the user sequence is not used (i.e. USEQ is cleared in ADC_MR register) then only the value of ADC_CHSR register defines the data structure. For each trigger event, enabled channels will be consecutively stored in ADC_LCDR register and automatically read to the buffer. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1637 When the user sequence is configured (i.e. USEQ is set in ADC_MR register) not only does ADC_CHSR register modify the data structure of the buffer, but ADC_SEQR1, ADC_SEQR2 registers may modify the data structure of the buffer as well. Figure 49-15. Buffer Structure when TSMODE = 0 Assuming ADC_CHSR = 0x000_01600 ADC_EMR(TAG) = 1 trig.event1 DMA Buffer Structure trig.event2 Assuming ADC_CHSR = 0x000_01600 ADC_EMR(TAG) = 0 0 ADC_CDR5 ADC_CDR6 DMA Transfer trig.event1 Base Address (BA) DMA Buffer Structure BA + 0x02 0 ADC_CDR6 8 ADC_CDR8 BA + 0x04 0 ADC_CDR8 5 ADC_CDR5 BA + 0x06 0 ADC_CDR5 6 ADC_CDR6 BA + 0x08 0 ADC_CDR6 8 ADC_CDR8 BA + 0x0A 0 ADC_CDR8 5 ADC_CDR5 BA + [(N-1) * 6] 0 ADC_CDR5 ADC_CDR6 BA + [(N-1) * 6]+ 0x02 0 ADC_CDR6 ADC_CDR8 BA + [(N-1) * 6]+ 0x04 0 ADC_CDR8 5 ADC_CDR5 6 trig.event2 trig.eventN trig.eventN 6 8 49.7.10.2 Touchscreen Channels Only When only touchscreen conversions are required (i.e. TSMODE differs from 0 in ADC_TSMR register and ADC_CHSR equals 0), the structure of data within the buffer is defined by the ADC_TSMR register. When TSMODE = 1 or 3, each trigger event adds 2 half-words in the buffer (assuming TSAV = 0), first half-word being XPOS of ADC_XPOSR register then YPOS of ADC_YPOSR register. If TSAV/TSFREQ differs from 0, the data structure remains unchanged. Not all trigger events add data to the buffer. When TSMODE = 2, each trigger event adds 4 half-words to the buffer (assuming TSAV=0), first half-word being XPOS of ADC_XPOSR register followed by YPOS of ADC_YPOSR register and finally Z1 followed by Z2, both located in ADC_PRESSR register. When TAG is set (ADC_EMR), the CHNB field (4 most significant bit of the ADC_LCDR) register is set to 0 when XPOS is transmitted and set to 1 when YPOS is transmitted, allowing an easier post-processing of the buffer or better checking buffer integrity. In case 4-wire with pressure mode is selected, Z1 value is transmitted to the buffer along with tag set to 2 and Z2 is tagged with value 3. XSCALE and YSCALE (calibration values) are not transmitted to the buffer because they are supposed to be constant and moreover only measured at the very first start up of the controller or upon user request. There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR register but it is recommended to use the pen detection function for buffer post-processing (refer to “Pen Detection Status” on page 1641). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1638 Figure 49-16. Buffer Structure when only touchscreen channels are enabled Assuming ADC_TSMR(TSMOD) = 1 or 3 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1 trig.event1 DMA Buffer Structure trig.event2 0 ADC_XPOSR 1 ADC_YPOSR Assuming ADC_TSMR(TSMOD) =1 or 3 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0 DMA Transfer trig.event1 Base Address (BA) DMA Buffer Structure BA + 0x02 trig.event2 0 ADC_YPOSR ADC_XPOSR BA + 0x04 0 ADC_XPOSR 1 ADC_YPOSR BA + 0x06 0 ADC_YPOSR 0 ADC_XPOSR BA + [(N-1) * 4] 0 ADC_XPOSR 0 ADC_YPOSR 1 ADC_YPOSR trig.event1 trig.eventN BA + [(N-1) * 4]+ 0x02 Assuming ADC_TSMR(TSMOD) = 2 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1 trig.event2 ADC_XPOSR 0 trig.eventN DMA Buffer Structure 0 Assuming ADC_TSMR(TSMOD) = 2 ADC_TSMR(TSAV) = 0 ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0 0 ADC_XPOSR trig.event1 DMA Transfer Base Address (BA) 0 ADC_XPOSR 1 ADC_YPOSR BA + 0x02 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + 0x04 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + 0x06 0 ADC_PRESSR(Z2) 0 ADC_XPOSR BA + 0x08 0 ADC_XPOSR 1 ADC_YPOSR BA + 0x0A 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + 0x0C 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + 0x0E 0 ADC_PRESSR(Z2) 0 ADC_XPOSR trig.eventN DMA Buffer Structure trig.event2 trig.eventN BA + [(N-1) * 8] 0 ADC_XPOSR 0 ADC_YPOSR 1 ADC_YPOSR BA + [(N-1) * 8]+ 0x02 2 ADC_PRESSR(Z1) BA + [(N-1) * 8]+ 0x04 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + [(N-1) * 8]+ 0x06 0 ADC_PRESSR(Z2) 49.7.10.3 Interleaved Channels When both classic ADC channels (CH4/CH5 up to CH12 are set in ADC_CHSR) and touchscreen conversions are required (TSMODE differs from 0 in ADC_TSMR register) the structure of the buffer differs according to TSAV and TSFREQ values. If TSFREQ differs from 0, not all events generate touchscreen conversions, therefore buffer structure is based on 2TSFREQ trigger events. Given a TSFREQ value, the location of touchscreen conversion results depends on TSAV value. When TSFREQ = 0, TSAV must equal 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1639 There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR register but it is recommended to use the pen detection function for buffer post-processing (refer to “Pen Detection Status” on page 1641). Figure 49-17. Buffer Structure when classic ADC and touchscreen channels are interleaved Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) =1 trig.event1 8 DMA Buffer Structure trig.event2 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) = 0 trig.event1 DMA Buffer Structure trig.event2 8 0 ADC_YPOSR ADC_CDR8 ADC_XPOSR 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR BA + 0x0A 8 ADC_CDR8 BA + [(N-1) * 6] ADC_XPOSR BA + [(N-1) * 6]+ 0x02 ADC_YPOSR BA + [(N-1) * 6]+ 0x04 trig.eventN trig.event1 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 8 ADC_CDR8 BA + 0x06 8 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = 1 ADC_TSMR(TSFREQ) = 1 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) = 1 trig.event1 trig.event2 DMA Buffer Structure BA + 0x08 0 ADC_XPOSR BA + 0x0A 1 ADC_YPOSR BA + 0x0c 8 ADC_CDR8 BA + 0x0e 8 ADC_CDR8 BA + [(N-1) * 8] 0 ADC_XPOSR BA + [(N-1) * 8]+ 0x02 1 ADC_YPOSR BA + [(N-1) * 8]+ 0x04 8 ADC_CDR8 BA + [(N-1) * 8]+ 0x06 trig.eventN 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR trig.event3 ADC_CDR8 8 trig.eventN+1 0 0 Assuming ADC_TSMR(TSMOD) = 1 ADC_TSMR(TSAV) = 0 ADC_TSMR(TSFREQ) = 1 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) = 1 trig.event4 ADC_XPOSR BA + 0x08 ADC_YPOSR 1 trig.event3 0 BA + 0x06 1 0 trig.event2 ADC_CDR8 ADC_CDR8 trig.eventN DMA Buffer Structure 0 trig.event4 trig.eventN trig.eventN+1 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1640 49.7.10.4 Pen Detection Status If the pen detection measure is enabled (PENDET is set in ADC_TSMR register), the XPOS, YPOS, Z1, Z2 values transmitted to the buffer through ADC_LCDR register are cleared (including the CHNB field), if the PENS flag of ADC_ISR register is 0. When the PENS flag is set, XPOS, YPOS, Z1, Z2 are normally transmitted. Therefore, using pen detection together with tag function eases the post-processing of the buffer, especially to determine which touchscreen converted values correspond to a period of time when the pen was in contact with the screen. When the pen detection is disabled or the tag function is disabled, XPOS, YPOS, Z1, Z2 are normally transmitted without tag and no relationship can be found with pen status, thus post-processing may not be easy. Figure 49-18. Buffer Structure with and without pen detection enabled Assuming ADC_TSMR(TSMOD) = 1, PENDET = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) = 1 trig.event1 8 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 8 ADC_CDR8 BA + 0x06 0 ADC_XPOSR BA + 0x08 BA + 0x0A 1 ADC_YPOSR 8 ADC_CDR8 BA + [(N-1) * 6] 0 BA + [(N-1) * 6]+ 0x02 0 0 BA + [(N-1) * 6]+ 0x04 8 ADC_CDR8 0 0 0 0 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR* 0 ADC_YPOSR* 0 ADC_CDR8 0 ADC_XPOSR* 0 ADC_YPOSR* trig.eventN 0 PENS = 0 DMA buffer Structure trig.event2 trig.eventN trig.eventN+1 trig.event1 PENS = 1 PENS = 1 trig.event2 DMA Transfer Base Address (BA) 2 successive tags cleared => PENS = 0 PENS = 0 DMA buffer Structure ADC_CDR8 Assuming ADC_TSMR(TSMOD) = 1, PENDET = 1 ADC_TSMR(TSAV) = ADC_TSMR(TSFREQ) = 0 ADC_CHSR = 0x000_0100 , ADC_EMR(TAG) =0 ADC_XPOSR*, ADC_YPOSR* can be any value when PENS = 0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1641 49.7.11 Fault Output The ADC Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted according to the configuration of ADC_EMR (Extended Mode Register) and ADC_CWR (Compare Window Register) and converted values. When the Compare occurs, the ADC fault output generates a pulse of one Master Clock Cycle to the PWM fault input. This fault line can be enabled or disabled within PWM. Should it be activated and asserted by the ADC Controller, the PWM outputs are immediately placed in a safe state (pure combinational path). Note that the ADC fault output connected to the PWM is not the COMPE bit. Thus the Fault Mode (FMOD) within the PWM configuration must be FMOD = 1. 49.7.12 Write Protected Registers To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR). If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register (ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR). The protected registers are:  “ADC Mode Register” on page 1646  “ADC Channel Sequence 1 Register” on page 1649  “ADC Channel Sequence 2 Register” on page 1650  “ADC Channel Enable Register” on page 1651  “ADC Channel Disable Register” on page 1652  “ADC Extended Mode Register” on page 1661  “ADC Compare Window Register” on page 1662  “ADC Channel Gain Register” on page 1663  “ADC Channel Offset Register” on page 1664  “ADC Analog Control Register” on page 1666  “ADC Touchscreen Mode Register” on page 1667  “ADC Trigger Register” on page 1672 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1642 49.8 Analog-to-Digital Converter (ADC) User Interface Table 49-8. Register Mapping Offset Register Name Access Reset 0x00 Control Register ADC_CR Write-only – 0x04 Mode Register ADC_MR Read-write 0x00000000 0x08 Channel Sequence Register 1 ADC_SEQR1 Read-write 0x00000000 0x0C Channel Sequence Register 2 ADC_SEQR2 Read-write 0x00000000 0x10 Channel Enable Register ADC_CHER Write-only – 0x14 Channel Disable Register ADC_CHDR Write-only – 0x18 Channel Status Register ADC_CHSR Read-only 0x00000000 0x1C Reserved – – – 0x20 Last Converted Data Register ADC_LCDR Read-only 0x00000000 0x24 Interrupt Enable Register ADC_IER Write-only – 0x28 Interrupt Disable Register ADC_IDR Write-only – 0x2C Interrupt Mask Register ADC_IMR Read-only 0x00000000 0x30 Interrupt Status Register ADC_ISR Read-only 0x00000000 0x34 Reserved – – – 0x38 Reserved – – – 0x3C Overrun Status Register ADC_OVER Read-only 0x00000000 0x40 Extended Mode Register ADC_EMR Read-write 0x00000000 0x44 Compare Window Register ADC_CWR Read-write 0x00000000 0x48 Channel Gain Register ADC_CGR Read-write 0x00000000 0x4C Channel Offset Register ADC_COR Read-write 0x00000000 0x50 Channel Data Register 0 ADC_CDR0 Read-only 0x00000000 0x54 Channel Data Register 1 ADC_CDR1 Read-only 0x00000000 ... ... ... ADC_CDR11 Read-only 0x00000000 – – – ADC_ACR Read-write 0x00000100 – – – ADC_TSMR Read-write 0x00000000 ... 0x7C 0x80 - 0x90 0x94 0x98 - 0xAC ... Channel Data Register 11 Reserved Analog Control Register Reserved 0xB0 Touchscreen Mode Register 0xB4 Touchscreen X Position Register ADC_XPOSR Read-only 0x00000000 0xB8 Touchscreen Y Position Register ADC_YPOSR Read-only 0x00000000 0xBC Touchscreen Pressure Register ADC_PRESSR Read-only 0x00000000 0xC0 Trigger Register ADC_TRGR Read-write 0x00000000 – – – ADC_WPMR Read-write 0x00000000 0xC4 - 0xE0 0xE4 Reserved Write Protect Mode Register SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1643 Table 49-8. Register Mapping (Continued) Offset 0xE8 Register Write Protect Status Register Name Access Reset ADC_WPSR Read-only 0x00000000 0xEC - 0xF8 Reserved – – – 0xFC Reserved – – – Note: If an offset is not listed in the table it must be considered as “reserved”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1644 49.8.1 ADC Control Register Name: ADC_CR Address: 0xF8018000 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 AUTOCAL 2 TSCALIB 1 START 0 SWRST • SWRST: Software Reset 0: No effect. 1: Resets the ADC simulating a hardware reset. • START: Start Conversion 0: No effect. 1: Begins analog-to-digital conversion. • TSCALIB: Touchscreen Calibration 0: No effect. 1: Programs screen calibration (VDD/GND measurement) The calibration sequence is performed during the next sequence when command is launched during an already started conversion sequence, or at the start of the second conversion sequence located after the TSCALIB command, if it is launched when no conversion is in progress (sleep mode, waiting a trigger event). TSCALIB measurement sequence does not affect the last data converted register (ADC_LDCR). • AUTOCAL: Automatic Calibration of ADC 0: No effect. 1: Launches an automatic calibration of the ADC cell on the next sequence. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1645 49.8.2 ADC Mode Register Name: ADC_MR Address: 0xF8018004 Access: Read-write 31 USEQ 30 – 29 23 ANACH 22 – 21 15 14 13 28 27 26 TRANSFER 25 24 17 16 TRACKTIM 20 19 18 SETTLING STARTUP 12 11 10 9 8 3 2 TRGSEL 1 0 – PRESCAL 7 – 6 FWUP 5 SLEEP 4 – This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1673. • TRGSEL: Trigger Selection Value Name 0 ADC_TRIG0 ADTRG 1 ADC_TRIG1 TIOA0 2 ADC_TRIG2 TIOA1 3 ADC_TRIG3 TIOA2 4 ADC_TRIG4 PWM event line 0 5 ADC_TRIG5 PWM_even line 1 6 ADC_TRIG6 Reserved 7 – Reserved Note: Description The trigger selection can be performed only if TRGMOD=1,2 or 3 in “ADC Trigger Register”. • SLEEP: Sleep Mode Value Name 0 NORMAL 1 SLEEP Description Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions Sleep Mode: The wake-up time can be modified by programming FWUP bit • FWUP: Fast Wake Up Value Name Description 0 OFF If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions 1 ON If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF • PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1646 • STARTUP: Start Up Time Value Name Description 0 SUT0 0 periods of ADCClock 1 SUT8 8 periods of ADCClock 2 SUT16 16 periods of ADCClock 3 SUT24 24 periods of ADCClock 4 SUT64 64 periods of ADCClock 5 SUT80 80 periods of ADCClock 6 SUT96 96 periods of ADCClock 7 SUT112 112 periods of ADCClock 8 SUT512 512 periods of ADCClock 9 SUT576 576 periods of ADCClock 10 SUT640 640 periods of ADCClock 11 SUT704 704 periods of ADCClock 12 SUT768 768 periods of ADCClock 13 SUT832 832 periods of ADCClock 14 SUT896 896 periods of ADCClock 15 SUT960 960 periods of ADCClock • SETTLING: Analog Settling Time Value Name Description 0 AST3 3 periods of ADCClock 1 AST5 5 periods of ADCClock 2 AST9 9 periods of ADCClock 3 AST17 17 periods of ADCClock • ANACH: Analog Change Value Name Description 0 NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels 1 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers • TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) * ADCClock periods. • TRANSFER: Transfer Period This field must be programmed with value 2. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1647 • USEQ: Use Sequence Enable Value Name Description 0 NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 1 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1648 49.8.3 ADC Channel Sequence 1 Register Name: ADC_SEQR1 Address: 0xF8018008 Access: Read-write 31 30 29 28 27 26 USCH8 23 22 21 20 19 18 USCH6 15 14 13 6 24 17 16 9 8 1 0 USCH5 12 11 10 USCH4 7 25 USCH7 USCH3 5 4 USCH2 3 2 USCH1 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • USCHx: User Sequence Number x The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this field. The allowed range is 0 up to 11. So it is only possible to use the sequencer from CH0 to CH11. This register activates only if ADC_MR(USEQ) field is set to ‘1’. Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in USCHx does not add the corresponding channel in the conversion sequence. Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1649 49.8.4 ADC Channel Sequence 2 Register Name: ADC_SEQR2 Address: 0xF801800C Access: Read-write 31 30 29 28 27 26 – 23 22 21 20 19 18 – 15 14 13 6 24 17 16 9 8 1 0 – 12 11 10 – 7 25 – USCH11 5 4 USCH10 3 2 USCH9 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • USCHx: User Sequence Number x The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this field. The allowed range is 0 up to 11. So it is only possible to use the sequencer from CH0 to CH11. This register activates only if ADC_MR(USEQ) field is set to ‘1’. Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in USCHx does not add the corresponding channel in the conversion sequence. Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1650 49.8.5 ADC Channel Enable Register Name: ADC_CHER Address: 0xF8018010 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel. Note: If USEQ = 1 in the ADC_MR register, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1 and ADC_SEQR2. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1651 49.8.6 ADC Channel Disable Register Name: ADC_CHDR Address: 0xF8018014 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1652 49.8.7 ADC Channel Status Register Name: ADC_CHSR Address: 0xF8018018 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 CH11 10 CH10 9 CH9 8 CH8 7 CH7 6 CH6 5 CH5 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 • CHx: Channel x Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1653 49.8.8 ADC Last Converted Data Register Name: ADC_LCDR Address: 0xF8018020 Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. • CHNB: Channel Number Indicates the last converted channel when the TAG option is set to 1 in the ADC_EMR register. If the TAG option is not set, CHNB = 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1654 49.8.9 ADC Interrupt Enable Register Name: ADC_IER Address: 0xF8018024 Access: Write-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion Interrupt Enable x • XRDY: Touchscreen Measure XPOS Ready Interrupt Enable • YRDY: Touchscreen Measure YPOS Ready Interrupt Enable • PRDY: Touchscreen Measure Pressure Ready Interrupt Enable • EOCAL: End of Calibration Sequence • DRDY: Data Ready Interrupt Enable • GOVRE: General Overrun Error Interrupt Enable • COMPE: Comparison Event Interrupt Enable • PEN: Pen Contact Interrupt Enable • NOPEN: No Pen Contact Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1655 49.8.10 ADC Interrupt Disable Register Name: ADC_IDR Address: 0xF8018028 Access: Write-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion Interrupt Disable x • XRDY: Touchscreen Measure XPOS Ready Interrupt Disable • YRDY: Touchscreen Measure YPOS Ready Interrupt Disable • PRDY: Touchscreen Measure Pressure Ready Interrupt Disable • EOCAL: End of Calibration Sequence • DRDY: Data Ready Interrupt Disable • GOVRE: General Overrun Error Interrupt Disable • COMPE: Comparison Event Interrupt Disable • PEN: Pen Contact Interrupt Disable • NOPEN: No Pen Contact Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1656 49.8.11 ADC Interrupt Mask Register Name: ADC_IMR Address: 0xF801802C Access: Read-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion Interrupt Mask x • XRDY: Touchscreen Measure XPOS Ready Interrupt Mask • YRDY: Touchscreen Measure YPOS Ready Interrupt Mask • PRDY: Touchscreen Measure Pressure Ready Interrupt Mask • EOCAL: End of Calibration Sequence • DRDY: Data Ready Interrupt Mask • GOVRE: General Overrun Error Interrupt Mask • COMPE: Comparison Event Interrupt Mask • PEN: Pen Contact Interrupt Mask • NOPEN: No Pen Contact Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1657 49.8.12 ADC Interrupt Status Register Name: ADC_ISR Address: 0xF8018030 Access: Read-only 31 PENS 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 EOCAL 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 EOC11 10 EOC10 9 EOC9 8 EOC8 7 EOC7 6 EOC6 5 EOC5 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 • EOCx: End of Conversion x 0: The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the corresponding ADC_CDRx registers. 1: The corresponding analog channel is enabled and conversion is complete. • XRDY: Touchscreen XPOS Measure Ready 0: No Measure has been performed since the last read of ADC_XPOSR. 1: At least one Measure has been performed since the last read of ADC_ISR. • YRDY: Touchscreen YPOS Measure Ready 0: No Measure has been performed since the last read of ADC_YPOSR. 1: At least one Measure has been performed since the last read of ADC_ISR. • PRDY: Touchscreen Pressure Measure Ready 0: No Measure has been performed since the last read of ADC_PRESSR. 1: At least one Measure has been performed since the last read of ADC_ISR. • EOCAL: End of Calibration Sequence 0: Calibration sequence is on going, or no calibration sequence has been requested. 1: Calibration sequence is complete. • DRDY: Data Ready 0: No data has been converted since the last read of ADC_LCDR. 1: At least one data has been converted and is available in ADC_LCDR. • GOVRE: General Overrun Error 0: No General Overrun Error occurred since the last read of ADC_ISR. 1: At least one General Overrun Error has occurred since the last read of ADC_ISR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1658 • COMPE: Comparison Error 0: No Comparison Error since the last read of ADC_ISR. 1: At least one Comparison Error (defined in the ADC_EMR and ADC_CWR registers) has occurred since the last read of ADC_ISR. • PEN: Pen contact 0: No pen contact since the last read of ADC_ISR. 1: At least one pen contact since the last read of ADC_ISR. • NOPEN: No Pen contact 0: No loss of pen contact since the last read of ADC_ISR. 1: At least one loss of pen contact since the last read of ADC_ISR. • PENS: Pen detect Status 0: The pen does not press the screen. 1: The pen presses the screen. Note: PENS is not a source of interruption. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1659 49.8.13 ADC Overrun Status Register Name: ADC_OVER Address: 0xF801803C Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 OVRE11 10 OVRE10 9 OVRE9 8 OVRE8 7 OVRE7 6 OVRE6 5 OVRE5 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 • OVREx: Overrun Error x 0: No overrun error on the corresponding channel since the last read of ADC_OVER. 1: There has been an overrun error on the corresponding channel since the last read of ADC_OVER. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1660 49.8.14 ADC Extended Mode Register Name: ADC_EMR Address: 0xF8018040 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 TAG 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 – 10 – 9 CMPALL 8 – 7 6 4 3 – 2 – 1 0 CMPFILTER 5 CMPSEL CMPMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • CMPMODE: Comparison Mode Value Name Description 0 LOW Generates an event when the converted data is lower than the low threshold of the window. 1 HIGH Generates an event when the converted data is higher than the high threshold of the window. 2 IN 3 OUT Generates an event when the converted data is in the comparison window. Generates an event when the converted data is out of the comparison window. • CMPSEL: Comparison Selected Channel If CMPALL = 0: CMPSEL indicates which channel has to be compared. If CMPALL = 1: No effect. • CMPALL: Compare All Channels 0: Only channel indicated in CMPSEL field is compared. 1: All channels are compared. • CMPFILTER: Compare Event Filtering Number of consecutive compare events necessary to raise the flag = CMPFILTER+1 When programmed to 0, the flag rises as soon as an event occurs. • TAG: TAG of the ADC_LDCR register 0: Sets CHNB to zero in ADC_LDCR. 1: Appends the channel number to the conversion result in ADC_LDCR register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1661 49.8.15 ADC Compare Window Register Name: ADC_CWR Address: 0xF8018044 Access: Read-write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • LOWTHRES: Low Threshold Low threshold associated to compare settings of the ADC_EMR register. • HIGHTHRES: High Threshold High threshold associated to compare settings of the ADC_EMR register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1662 49.8.16 ADC Channel Gain Register Name: ADC_CGR Address: 0xF8018048 Access: Read-write 31 30 29 – 23 22 21 GAIN11 15 27 14 20 13 6 18 24 17 GAIN9 12 5 25 – 19 11 GAIN6 GAIN3 26 – GAIN10 GAIN7 7 28 – 10 9 GAIN5 4 GAIN2 3 16 GAIN8 8 GAIN4 2 GAIN1 1 0 GAIN0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • GAINx: Gain for Channel x Gain applied on input of analog-to-digital converter. GAINx Gain applied when DIFFx = 0 Gain applied when DIFFx = 1 0 0 1 0.5 0 1 1 1 1 0 2 2 1 1 4 2 The DIFFx mentioned in this table is described in “ADC Channel Offset Register” . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1663 49.8.17 ADC Channel Offset Register Name: ADC_COR Address: 0xF801804C Access: Read-write 31 – 30 – 29 – 28 – 27 DIFF11 26 DIFF10 25 DIFF9 24 DIFF8 23 DIFF7 22 DIFF6 21 DIFF5 20 DIFF4 19 DIFF3 18 DIFF2 17 DIFF1 16 DIFF0 15 – 14 – 13 – 12 – 11 OFF11 10 OFF10 9 OFF9 8 OFF8 7 OFF7 6 OFF6 5 OFF5 4 OFF4 3 OFF3 2 OFF2 1 OFF1 0 OFF0 This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • OFFx: Offset for channel x 0: No Offset. 1: Centers the analog signal on Vrefin/2 before the gain scaling. The Offset applied is: (G-1)Vrefin/2 where G is the gain applied (see the description of “ADC Channel Gain Register” ). • DIFFx: Differential inputs for channel x 0: Single Ended Mode. 1: Fully Differential Mode. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1664 49.8.18 ADC Channel Data Register Name: ADC_CDRx [x=0..11] Address: 0xF8018050 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1665 49.8.19 ADC Analog Control Register Name: ADC_ACR Address: 0xF8018094 Access: Read-write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 PENDETSENS This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • PENDETSENS: Pen Detection Sensitivity Allows to modify the pen detection input pull-up resistor value. (See the product electrical characteristics for further details). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1666 49.8.20 ADC Touchscreen Mode Register Name: ADC_TSMR Address: 0xF80180B0 Access: Read-write 31 30 29 28 27 – 26 – 18 PENDBC 23 – 22 NOTSDMA 21 – 20 – 19 15 – 14 – 13 – 12 – 11 7 – 6 – 5 4 3 – TSAV 25 – 24 PENDET 17 16 9 8 TSSCTIM 10 TSFREQ 2 – 1 0 TSMODE This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” . • TSMODE: Touchscreen Mode Value Name Description 0 NONE No Touchscreen 1 4_WIRE_NO_PM 2 4_WIRE 4-wire Touchscreen with pressure measurement 3 5_WIRE 5-wire Touchscreen 4-wire Touchscreen without pressure measurement When TSMOD equals 01 or 10 (i.e. 4-wire mode), channel 0, 1, 2 and 3 must not be used for classic ADC conversions. When TSMOD equals 11 (i.e. 5-wire mode), channel 0, 1, 2, 3, and 4 must not be used. • TSAV: Touchscreen Average Value Name Description 0 NO_FILTER No Filtering. Only one ADC conversion per measure 1 AVG2CONV Averages 2 ADC conversions 2 AVG4CONV Averages 4 ADC conversions 3 AVG8CONV Averages 8 ADC conversions • TSFREQ: Touchscreen Frequency Defines the Touchscreen Frequency compared to the Trigger Frequency. TSFREQ must be greater or equal to TSAV. The Touchscreen Frequency is: Touchscreen Frequency = Trigger Frequency / 2TSFREQ • TSSCTIM: Touchscreen Switches Closure Time Defines closure time of analog switches necessary to establish the measurement conditions. The Closure Time is: Switch Closure Time = (TSSCTIM * 4) ADCClock periods. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1667 • PENDET: Pen Contact Detection Enable 0: Pen contact detection disable. 1: Pen contact detection enable. When PENDET = 1, XPOS, YPOS, Z1, Z2 values of ADC_XPOSR, ADC_YPOSR, ADC_PRESSR registers are automatically cleared when PENS = 0 in ADC_ISR. • NOTSDMA: No TouchScreen DMA 0: XPOS, YPOS, Z1, Z2 are transmitted in ADC_LCDR. 1: XPOS, YPOS, Z1, Z2 are never transmitted in ADC_LCDR, therefore the buffer does not contains touchscreen values. • PENDBC: Pen Detect Debouncing Period Debouncing period = 2PENDBC ADCClock periods. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1668 49.8.21 ADC Touchscreen X Position Register Name: ADC_XPOSR Address: 0xF80180B4 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 XSCALE 19 18 11 10 XSCALE 15 – 14 – 13 – 12 – 7 6 5 4 XPOS 3 2 XPOS • XPOS: X Position The Position measured is stored here. if XPOS = 0 or XPOS = XSIZE, the pen is on the border. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), XPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register). • XSCALE: Scale of XPOS Indicates the max value that XPOS can reach. This value should be close to 212. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1669 49.8.22 ADC Touchscreen Y Position Register Name: ADC_YPOSR Address: 0xF80180B8 Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 YSCALE 19 18 11 10 YSCALE 15 – 14 – 13 – 12 – 7 6 5 4 YPOS 3 2 YPOS • YPOS: Y Position The Position measured is stored here. if YPOS = 0 or YPOS = YSIZE, the pen is on the border. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), YPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register). • YSCALE: Scale of YPOS Indicates the max value that YPOS can reach. This value should be close to 212 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1670 49.8.23 ADC Touchscreen Pressure Register Name: ADC_PRESSR Address: 0xF80180BC Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 Z2 19 18 11 10 Z2 15 – 14 – 13 – 12 – 7 6 5 4 Z1 3 2 Z1 • Z1: Data of Z1 Measurement Data Z1 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), Z1 is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register). • Z2: Data of Z2 Measurement Data Z2 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR register), Z2 is tied to 0 while there is no detection of contact on the touchscreen (i.e. when PENS bitfield is cleared in ADC_ISR register). Note: These two values are unavailable if TSMODE is not set to 2 in ADC_TSMR register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1671 49.8.24 ADC Trigger Register Name: ADC_TRGR Address: 0xF80180C0 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 TRGPER 23 22 21 20 TRGPER 15 14 13 12 11 10 9 8 – – – – – – – – 2 1 0 7 6 5 4 3 – – – – – TRGMOD • TRGMOD: Trigger Mode Value Name Description 0 NO_TRIGGER 1 EXT_TRIG_RISE External Trigger Rising Edge 2 EXT_TRIG_FALL External Trigger Falling Edge 3 EXT_TRIG_ANY External Trigger Any Edge 4 PEN_TRIG 5 PERIOD_TRIG Periodic Trigger (TRGPER shall be initiated appropriately) 6 CONTINUOUS Continuous Mode 7 – No trigger, only software trigger can start conversions Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) Reserved • TRGPER: Trigger Period Effective only if TRGMOD defines a Periodic Trigger. Defines the periodic trigger period, with the following equation: Trigger Period = (TRGPER+1) /ADCCLK The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2, ADC_TSMR. When TRGMOD is set to pen detect trigger (i.e. 100) and averaging is used (i.e. bitfield TSAV differs from 0 in ADC_TSMR register) only 1 measure is performed. Thus, XRDY, YRDY, PRDY, DRDY will not rise on pen contact trigger. To achieve measurement, several triggers must be provided either by software or by setting the TRGMOD on continuous trigger (i.e. 110) until flags rise. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1672 49.8.25 ADC Write Protect Mode Register Name: ADC_WPMR Address: 0xF80180E4 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 6 5 4 3 2 1 0 – – – – – – – WPEN • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII). Protects the registers: • “ADC Mode Register” on page 1646 • “ADC Channel Sequence 1 Register” on page 1649 • “ADC Channel Sequence 2 Register” on page 1650 • “ADC Channel Enable Register” on page 1651 • “ADC Channel Disable Register” on page 1652 • “ADC Extended Mode Register” on page 1661 • “ADC Compare Window Register” on page 1662 • “ADC Channel Gain Register” on page 1663 • “ADC Channel Offset Register” on page 1664 • “ADC Analog Control Register” on page 1666 • “ADC Touchscreen Mode Register” on page 1667 • “ADC Trigger Register” on page 1672 • WPKEY: Write Protect KEY Value Name 0x414443 PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1673 49.8.26 ADC Write Protect Status Register Name: ADC_WPSR Address: 0xF80180E8 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 11 10 9 8 WPVSRC 15 14 13 12 WPVSRC 7 6 5 4 3 2 1 0 – – – – – – – WPVS • WPVS: Write Protect Violation Status 0: No Write Protect Violation has occurred since the last read of the ADC_WPSR register. 1: A Write Protect Violation has occurred since the last read of the ADC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. Reading ADC_WPSR automatically clears all fields. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1674 50. True Random Number Generator (TRNG) 50.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3. 50.2 50.3 Embedded Characteristics  Passed NIST Special Publication 800-22 Tests Suite  Passed Diehard Random Tests Suite  May be used as Entropy Source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3  Provides a 32-bit Random Number Every 84 Clock Cycles Block Diagram Figure 50-1. TRNG Block Diagram TRNG Interrupt Controller Control Logic MCK PMC User Interface Entropy Source APB SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1675 50.4 Product Dependencies 50.4.1 Power Management The TRNG interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TRNG user interface clock. The user interface clock is independent from any clock that may be used in the entropy source logic circuitry. The source of entropy can be enabled before enabling the user interface clock. 50.4.2 Interrupt The TRNG interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TRNG. Table 50-1. Peripheral IDs 50.5 Instance ID TRNG 45 Functional Description As soon as the TRNG is enabled in the control register (TRNG_CR), the generator provides one 32-bit value every 84 clock cycles. Interrupt trng_int can be enabled in the TRNG_IER (respectively disabled in the TRNG_IDR). This interrupt is set when a new random value is available and is cleared when the status register (TRNG_ISR) is read. The flag DATRDY of the (TRNG_ISR) is set when the random data is ready to be read out on the 32-bit output data register (TRNG_ODATA). The normal mode of operation checks that the status register flag equals 1 before reading the output data register when a 32-bit random value is required by the software application. Figure 50-2. TRNG Data Generation Sequence Clock trng_cr enable 84 clock cycles 84 clock cycles 84 clock cycles trng_int Read TRNG_ISR Read TRNG_ISR Read TRNG_ODATA Read TRNG_ODATA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1676 50.6 True Random Number Generator (TRNG) User Interface Table 50-2. Register Mapping Offset Register Name Access Reset 0x00 Control Register TRNG_CR Write-only – 0x10 Interrupt Enable Register TRNG_IER Write-only – 0x14 Interrupt Disable Register TRNG_IDR Write-only – 0x18 Interrupt Mask Register TRNG_IMR Read-only 0x0000_0000 0x1C Interrupt Status Register TRNG_ISR Read-only 0x0000_0000 0x50 Output Data Register TRNG_ODATA Read-only 0x0000_0000 0xFC Reserved – – – SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1677 50.6.1 TRNG Control Register Name: TRNG_CR Address: 0xF8040000 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE • ENABLE: Enables the TRNG to provide random values 0: Disables the TRNG. 1: Enables the TRNG if 0x524E47 (“RNG” in ASCII) is written in KEY field at the same time. • KEY: Security Key. Value 0x524E47 Name Description PASSWD Writing any other value in this field aborts the write operation. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1678 50.6.2 TRNG Interrupt Enable Register Name: TRNG_IER Address: 0xF8040010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1679 50.6.3 TRNG Interrupt Disable Register Name: TRNG_IDR Address: 0xF8040014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1680 50.6.4 TRNG Interrupt Mask Register Name: TRNG_IMR Address: 0xF8040018 Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1681 50.6.5 TRNG Interrupt Status Register Name: TRNG_ISR Address: 0xF804001C Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data is not valid or TRNG is disabled. 1: New Random value is completed. DATRDY is cleared when this register is read. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1682 50.6.6 TRNG Output Data Register Name: TRNG_ODATA Address: 0xF8040050 Reset: 0x0000_0000 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1683 51. Advanced Encryption Standard (AES) 51.1 Description The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-38A Recommendation. It is compatible with all these modes via Peripheral DMA Controller channels, minimizing processor intervention for large buffer transfers. The 128-bit/192-bit/256-bit key is stored in four/six/eight 32-bit registers (AES_KEYWRx) which are all write-only. The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit registers (AES_IDATARx and AES_IVRx) which are all write-only. As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data are ready to be read out on the four 32-bit output data registers (AES_ODATARx) or through the DMA channels. 51.2 51.3 Embedded Characteristics  Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)  128-bit/192-bit/256-bit Cryptographic Key  12/14/16 Clock Cycles Encryption/Decryption Processing Time with a 128-bit/192-bit/256-bit Cryptographic Key  Double Input Buffer Optimizes Runtime  Support of the Five Standard Modes of Operation Specified in the NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques:  Electronic Code Book (ECB)  Cipher Block Chaining (CBC) including CBC-MAC  Cipher Feedback (CFB)  Output Feedback (OFB)  Counter (CTR)  8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode  Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation  Connection to DMA Optimizes Data Transfers for all Operating Modes Product Dependencies 51.3.1 Power Management The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to configure the PMC to enable the AES clock. 51.3.2 Interrupt The AES interface has an interrupt line connected to the Interrupt Controller. Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES. Table 51-1. Peripheral IDs Instance ID AES 43 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1684 51.4 Functional Description The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection between the encryption and the decryption processes. The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. This 128-bit/192-bit/256-bit key is defined in the Key Registers (AES_KEYWRx). The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector (IV), which must be set in the Initialization Vector Registers (AES_IVRx). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The Initialization Vector Registers are also used by the CTR mode to set the counter value. 51.4.1 Operation Modes The AES supports the following modes of operation:  ECB: Electronic Code Book  CBC: Cipher Block Chaining  OFB: Output Feedback  CFB: Cipher Feedback   CFB8 (CFB where the length of the data segment is 8 bits)  CFB16 (CFB where the length of the data segment is 16 bits)  CFB32 (CFB where the length of the data segment is 32 bits)  CFB64 (CFB where the length of the data segment is 64 bits)  CFB128 (CFB where the length of the data segment is 128 bits) CTR: Counter The data pre-processing, post-processing and data chaining for the concerned modes are automatically performed. Refer to the NIST Special Publication 800-38A Recommendation for more complete information. These modes are selected by setting the OPMOD field in the AES_MR. In CFB mode, five data sizes are possible (8, 16, 32, 64 or 128 bits), configurable by means of the CFBS field in the AES_MR (Section 51.6.2 “AES Mode Register” on page 1693). In CTR mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after processing 1 megabyte of data. If the file to be processed is greater than 1 megabyte, this file must be split into fragments of 1 megabyte. Prior to loading the first fragment into AES_IDATARx, AES_IVRx must be cleared. For any fragment, after the transfer is completed and prior to transferring the next fragment, AES_IVR0 must be programmed so that the fragment number (0 for the first fragment, 1 for the second one, and so on) is written in the 16 MSB of AES_IVR0. 51.4.2 Double Input Buffer The input data register can be double-buffered to reduce the runtime of large files. This mode allows writing a new message block when the previous message block is being processed. This is only possible when DMA accesses are performed (SMOD = 0x2). The DUALBUFF bit in AES_MR must be set to 1 to access the double buffer. 51.4.3 Start Modes The SMOD field in the AES_MR allows selection of the encryption (or decryption) start mode. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1685 51.4.3.1 Manual Mode The sequence order is as follows:  Write the AES_MR with all required fields, including but not limited to SMOD and OPMOD.  Write the 128-bit/192-bit/256-bit key in the Key Registers (AES_KEYWRx).  Write the initialization vector (or counter) in the Initialization Vector Registers (AES_IVRx). Note: The Initialization Vector Registers concern all modes except ECB.  Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER), depending on whether an interrupt is required or not at the end of processing.  Write the data to be encrypted/decrypted in the authorized Input Data Registers (See Table 51-2). Table 51-2. Authorized Input Data Registers Operation Mode Input Data Registers to Write ECB All CBC All OFB All 128-bit CFB All 64-bit CFB AES_IDATAR0 and AES_IDATAR1 32-bit CFB AES_IDATAR0 16-bit CFB AES_IDATAR0 8-bit CFB AES_IDATAR0 CTR All Note: In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 registers is not allowed and may lead to errors in processing. Note: In 32-, 16- and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 registers is not allowed and may lead to errors in processing.  Set the START bit in the AES Control register AES_CR to begin the encryption or the decryption process.  When processing completes, the DATRDY bit in the AES Interrupt Status Register (AES_ISR) raises. If an interrupt has been enabled by setting the DATRDY bit in AES_IER, the interrupt line of the AES is activated.  When the software reads one of the Output Data Registers (AES_ODATARx), the DATRDY bit is automatically cleared. 51.4.3.2 Auto Mode The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of Input Data registers is written, processing is automatically started without any action in the Control Register. 51.4.4 DMA Mode The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without any action by the software during processing. The SMOD field of the AES_MR must be set to 0x2 and the DMA must be configured with non incremental addresses. The start address of any transfer descriptor must be set to AES_IDATAR0. The DMA chunk size configuration depends on the AES mode of operation and is listed in Table 51-3 "DMA Data Transfer Type for the Different Operation Modes". When writing data to AES with a first DMA channel, data are first fetched from a memory buffer (source data). It is recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1686 size depends on the mode of operation. When reading data from the AES with the second DMA channel, the source data is the data read from AES and data destination is the memory buffer. In this case, source data size depends on the AES mode of operation and is listed in Table 51-3. Table 51-3. DMA Data Transfer Type for the Different Operation Modes Operation Mode Chunk Size Destination/Source Data Transfer Type ECB 4 Word CBC 4 Word OFB 4 Word CFB 128-bit 4 Word CFB 64-bit 1 Word CFB 32-bit 1 Word CFB 16-bit 1 Half-word CFB 8-bit 1 Byte CTR 4 Word 51.4.5 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption algorithm (CBC-MAC algorithm for example). After each end of encryption/decryption, the output data are available either on the output data registers for Manual and Auto mode or at the address specified in the receive buffer pointer for DMA mode (See Table 51-4 "Last Output Data Mode Behavior versus Start Modes"). The Last Output Data bit (LOD) in the AES Mode Register (AES_MR) allows retrieval of only the last data of several encryption/decryption processes. Therefore, there is no need to define a read buffer in DMA mode. This data are only available on the Output Data Registers (AES_ODATARx). 51.4.6 Manual and Auto Modes 51.4.6.1 If LOD = 0 The DATRDY flag is cleared when at least one of the Output Data Registers is read (See Figure 51-1). Figure 51-1. Manual and Auto Modes with LOD = 0 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx register(s) (Auto mode) Read the AES_ODATARx DATRDY Encryption or Decryption Process If the user does not want to read the output data registers between each encryption/decryption, the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user cannot know the end of the following encryptions/decryptions. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1687 51.4.6.2 If LOD = 1 The DATRDY flag is cleared when at least one Input Data Register is written, so before the start of a new transfer (See Figure 51-2). No more Output Data Register reads are necessary between consecutive encryptions/decryptions. Figure 51-2. Manual and Auto Modes with LOD = 1 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx register(s) (Auto mode) Write AES_IDATARx register(s) DATRDY Encryption or Decryption Process 51.4.7 DMA Mode 51.4.7.1 If LOD = 0 This mode may be used for all AES operating modes except CBC-MAC where LOD = 1 mode is recommended. The end of the encryption/decryption is notified by the end of DMA transfer associated to AES_ODATARx (see Figure 51-3). Two DMA channels are required: one for writing message blocks to AES_IDATARx and one to obtain the result from AES_ODATARx. Figure 51-3. DMA transfer with LOD = 0 Enable DMA Channels associated to AES_IDATARx and AES_ODATARx Multiple Encryption or Decryption Processes BTC /channel 0 BTC /channel 1 Write accesses into AES_IDATARx Read accesses into AES_ODATARx Message fully processed (cipher or decipher) last block can be read 51.4.7.2 If LOD = 1 This mode is recommended to process AES CBC-MAC operating mode. The user must first wait for the DMA flag (BTC = Buffer Transfer Complete) to rise, then for DATRDY to ensure that the encryption/decryption is completed (see Figure 51-4). In this case, no receive buffers are required. The output data are only available on the Output Data Registers (AES_ODATARx). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1688 Figure 51-4. DMA transfer with LOD = 1 Enable DMA Channels associated with TDES_IDATARx and TDES_ODATARx registers Multiple Encryption or Decryption Processes Write accesses into AES_IDATARx BTC / channel 0 DATRDY Message fully transferred Message fully processed (cipher or decipher) MAC result can be read Table 51-4 summarizes the different cases. Table 51-4. Last Output Data Mode Behavior versus Start Modes Manual and Auto Modes DMA Transfer Sequence LOD = 0 LOD = 1 LOD = 0 LOD = 1 DATRDY Flag Clearing Condition(1) At least one Output Data Register must be read At least one Input Data Register must be written Not used Managed by the DMA End of Encryption/Decryption Notification DATRDY DATRDY 2 DMA flags (BTC[n/m]) DMA flag (BTC[n]) then AES DATRDY Encrypted/Decrypted Data Result Location In the Output Data Registers In the Output Data Registers At the address specified in the Channel Buffer Transfer Descriptor In the Output Data Registers Note: 1. Depending on the mode, there are other ways of clearing the DATRDY flag. See Section 51.6.6 ”AES Interrupt Status Register”. Warning: In DMA mode, reading to the Output Data registers before the last data transfer may lead to unpredictable results. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1689 51.5 Security Features 51.5.1 Unspecified Register Access Detection When an unspecified register access occurs, the URAD bit in the Interrupt Status Register (AES_ISR) raises. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur:  Input Data Register written during the data processing when SMOD = IDATAR0_START  Output Data Register read during data processing  Mode Register written during data processing  Output Data Register read during sub-keys generation  Mode Register written during sub-keys generation  Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in the AES_CR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1690 51.6 Advanced Encryption Standard (AES) User Interface Table 51-5. Register Mapping Offset Register Name Access Reset 0x00 Control Register AES_CR Write-only – 0x04 Mode Register AES_MR Read-write 0x0 0x08–0x0C Reserved – – – 0x10 Interrupt Enable Register AES_IER Write-only – 0x14 Interrupt Disable Register AES_IDR Write-only – 0x18 Interrupt Mask Register AES_IMR Read-only 0x0 0x1C Interrupt Status Register AES_ISR Read-only 0x0 0x20 Key Word Register 0 AES_KEYWR0 Write-only – 0x24 Key Word Register 1 AES_KEYWR1 Write-only – 0x28 Key Word Register 2 AES_KEYWR2 Write-only – 0x2C Key Word Register 3 AES_KEYWR3 Write-only – 0x30 Key Word Register 4 AES_KEYWR4 Write-only – 0x34 Key Word Register 5 AES_KEYWR5 Write-only – 0x38 Key Word Register 6 AES_KEYWR6 Write-only – 0x3C Key Word Register 7 AES_KEYWR7 Write-only – 0x40 Input Data Register 0 AES_IDATAR0 Write-only – 0x44 Input Data Register 1 AES_IDATAR1 Write-only – 0x48 Input Data Register 2 AES_IDATAR2 Write-only – 0x4C Input Data Register 3 AES_IDATAR3 Write-only – 0x50 Output Data Register 0 AES_ODATAR0 Read-only 0x0 0x54 Output Data Register 1 AES_ODATAR1 Read-only 0x0 0x58 Output Data Register 2 AES_ODATAR2 Read-only 0x0 0x5C Output Data Register 3 AES_ODATAR3 Read-only 0x0 0x60 Initialization Vector Register 0 AES_IVR0 Write-only – 0x64 Initialization Vector Register 1 AES_IVR1 Write-only – 0x68 Initialization Vector Register 2 AES_IVR2 Write-only – 0x6C Initialization Vector Register 3 AES_IVR3 Write-only – – – – 0x70–0xFC Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1691 51.6.1 AES Control Register Name: AES_CR Address: 0xF8038000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START • START: Start Processing 0: No effect 1: Starts manual encryption/decryption process. • SWRST: Software Reset 0: No effect. 1: Resets the AES. A software triggered hardware reset of the AES interface is performed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1692 51.6.2 AES Mode Register Name: AES_MR Address: 0xF8038004 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 CKEY 15 – 14 13 LOD 12 11 OPMOD 7 6 5 CFBS 10 9 KEYSIZE 4 PROCDLY 8 SMOD 3 2 1 0 DUALBUFF – – CIPHER • CIPHER: Processing Mode 0: Decrypts data. 1: Encrypts data. • DUALBUFF: Dual Input Buffer Value Name Description 0x0 INACTIVE AES_IDATARx cannot be written during processing of previous block. 0x1 ACTIVE AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. • PROCDLY: Processing Delay Processing Time = 12 × ( PROCDLY + 1 ) The Processing Time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption. Note: The best performance is achieved with PROCDLY equal to 0. • SMOD: Start Mode Value Name Description 0x0 MANUAL_START Manual Mode 0x1 AUTO_START Auto Mode 0x2 IDATAR0_START AES_IDATAR0 access only Auto Mode Values which are not listed in the table must be considered as “reserved”. If a DMA transfer is used, 0x2 must be configured. Refer to Section 51.4.4 ”DMA Mode” for more details. • KEYSIZE: Key Size Value Name Description 0x0 AES128 AES Key Size is 128 bits 0x1 AES192 AES Key Size is 192 bits 0x2 AES256 AES Key Size is 256 bits Values which are not listed in the table must be considered as “reserved”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1693 • OPMOD: Operation Mode Value Name Description 0x0 ECB ECB: Electronic Code Book mode 0x1 CBC CBC: Cipher Block Chaining mode 0x2 OFB OFB: Output Feedback mode 0x3 CFB CFB: Cipher Feedback mode 0x4 CTR CTR: Counter mode (16-bit internal counter) Values which are not listed in the table must be considered as “reserved”. For CBC-MAC operating mode, please set OPMOD to CBC and LOD to 1. • LOD: Last Output Data Mode 0: No effect. After each end of encryption/decryption, the output data are available either on the output data registers (Manual and Auto modes) or at the address specified in the Channel Buffer Transfer Descriptor for DMA mode. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1: The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions (see “Last Output Data Mode” on page 1687). Warning: In DMA mode, reading to the Output Data registers before the last data encryption/decryption process may lead to unpredictable results. • CFBS: Cipher Feedback Data Size Value Name Description 0x0 SIZE_128BIT 128-bit 0x1 SIZE_64BIT 64-bit 0x2 SIZE_32BIT 32-bit 0x3 SIZE_16BIT 16-bit 0x4 SIZE_8BIT 8-bit Values which are not listed in table must be considered as “reserved”. • CKEY: Key Value 0xE Name Description PASSWD This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE. Always reads as 0. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1694 51.6.3 AES Interrupt Enable Register Name: AES_IER Address: 0xF8038010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. • DATRDY: Data Ready Interrupt Enable • URAD: Unspecified Register Access Detection Interrupt Enable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1695 51.6.4 AES Interrupt Disable Register Name: AES_IDR Address: 0xF8038014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. • DATRDY: Data Ready Interrupt Disable • URAD: Unspecified Register Access Detection Interrupt Disable SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1696 51.6.5 AES Interrupt Mask Register Name: AES_IMR Address: 0xF8038018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. • DATRDY: Data Ready Interrupt Mask • URAD: Unspecified Register Access Detection Interrupt Mask SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1697 51.6.6 AES Interrupt Status Register Name: AES_ISR Address: 0xF803801C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data not valid. 1: Encryption or decryption process is completed. DATRDY is cleared when a Manual encryption/decryption occurs (START bit in AES_CR) or when a software triggered hardware reset of the AES interface is performed (SWRST bit in AES_CR). LOD = 0 (AES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Output Data Registers is read. In DMA mode, DATRDY is set and cleared automatically. LOD = 1 (AES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Input Data Registers is written. In DMA mode, DATRDY is set and cleared automatically. • URAD: Unspecified Register Access Detection Status 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAD bit is reset only by the SWRST bit in the AES_CR. • URAT: Unspecified Register Access: Value Name Description 0x0 IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD = 0x2 mode. 0x1 ODR_RD_PROCESSING Output Data Register read during the data processing. 0x2 MR_WR_PROCESSING Mode Register written during the data processing. 0x3 ODR_RD_SUBKGEN Output Data Register read during the sub-keys generation. 0x4 MR_WR_SUBKGEN Mode Register written during the sub-keys generation. 0x5 WOR_RD_ACCESS Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field. URAT field is reset only by the SWRST bit in the AES_CR. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1698 51.6.7 AES Key Word Register x Name: AES_KEYWRx Address: 0xF8038020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEYW 23 22 21 20 KEYW 15 14 13 12 KEYW 7 6 5 4 KEYW • KEYW: Key Word The four/six/eight 32-bit Key Word registers set the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption. AES_KEYWR0 corresponds to the first word of the key and respectively AES_KEYWR3/AES_KEYWR5/AES_KEYWR7 to the last one. These registers are write-only to prevent the key from being read by another application. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1699 51.6.8 AES Input Data Register x Name: AES_IDATARx Address: 0xF8038040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA • IDATA: Input Data Word The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption. AES_IDATAR0 corresponds to the first word of the data to be encrypted/decrypted, and AES_IDATAR3 to the last one. These registers are write-only to prevent the input data from being read by another application. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1700 51.6.9 AES Output Data Register x Name: AES_ODATARx Address: 0xF8038050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted. AES_ODATAR0 corresponds to the first word, AES_ODATAR3 to the last one. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1701 51.6.10 AES Initialization Vector Register x Name: AES_IVRx Address: 0xF8038060 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV • IV: Initialization Vector The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input. AES_IVR0 corresponds to the first word of the Initialization Vector, AES_IVR3 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application. For CBC, OFB and CFB modes, the IV input value corresponds to the initialization vector. For CTR mode, the IV input value corresponds to the initial counter value. Note: These registers are not used in ECB mode and must not be written. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1702 52. Triple Data Encryption Standard (Triple DES) 52.1 Description The Triple Data Encryption Standard (TDES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 46-3 specification. The TDES supports the four different confidentiality modes of operation (ECB, CBC, OFB and CFB), specified in the FIPS (Federal Information Processing Standard) Publication 81 and is compatible with the Peripheral Data Controller channels for all of these modes, minimizing processor intervention for large buffer transfers. The 64-bit long keys and input data (and initialization vector for some modes) are each stored in two 32-bit registers (TDES_KEYxWRx, TDES_IDATARx and TDES_IVRx) which are both write-only. As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data is ready to be read out on the two 32-bit output data registers (TDES_ODATARx) or through the DMA channels. 52.2 Embedded Characteristics  Supports Single Data Encryption Standard (DES) and Triple Data Encryption Algorithm (TDEA or TDES)  Compliant with FIPS Publication 46-3, Data Encryption Standard (DES)  64-bit Cryptographic Key for TDES  Two-key or Three-key Algorithms for TDES  18-clock Cycles Encryption/Decryption Processing Time for DES  50-clock Cycles Encryption/Decryption Processing Time for TDES  Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES Modes of Operation  Electronic Code Book (ECB)  Cipher Block Chaining (CBC)  Cipher Feedback (CFB)  Output Feedback (OFB)  8-bit, 16-bit, 32-bit and 64-bit Data Sizes Possible in CFB Mode  Last Output Data Mode Allowing Optimized Message (Data) Authentication Code (MAC) Generation  Connection to DMA Optimizes Data Transfers for all Operating Modes SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1703 52.3 Product Dependencies 52.3.1 Power Management The TDES may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the TDES clock. 52.3.2 Interrupt The TDES interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TDES interrupt requires programming the AIC before configuring the TDES. Peripheral IDs 52.4 Instance ID TDES 44 Functional Description The Data Encryption Standard (DES) and the Triple Data Encryption Algorithm (TDES) specify FIPS-approved cryptographic algorithms that can be used to protect electronic data. The TDES bit in the TDES Mode Register (TDES_MR) is used to select either the single DES or the Triple DES mode. Encryption (enciphering) converts data to an unintelligible form called ciphertext. Decrypting (deciphering) the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in the TDES Mode Register is used to choose between encryption and decryption. A DES is capable of using cryptographic keys of 64 bits to encrypt and decrypt data in blocks of 64 bits. This 64-bit key is defined in the Key 1 Word Registers (TDES_KEY1WRx). A TDES key consists of three DES keys, which is also referred to as a key bundle. These three 64-bit keys are defined, respectively, in the Key 1, 2 and 3 Word Registers (TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx). In Triple DES mode (TDESMOD set to 1), the KEYMOD bit in the TDES Mode Register is used to choose between a twoand a three-key algorithm:  In three-key encryption mode, the data is first encrypted with Key 1, then decrypted using Key 2 and then encrypted with Key 3.  In three-key decryption mode, the data is decrypted with Key 3, then encrypted with Key 2 and then decrypted using Key 1.  In two-key encryption mode, the data is first encrypted with Key 1, then decrypted using Key 2 and then encrypted with Key 1.  In two-key decryption mode, the data is decrypted with Key 1, then encrypted with Key 2 and then decrypted using Key 1. The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 64-bit data block called the initialization vector (IV), which must be set in the Initialization Vector Registers (TDES_IVRx). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1704 52.4.1 Operation Modes The TDES supports the following modes of operation:  ECB: Electronic Code Book  CBC: Cipher Block Chaining  OFB: Output Feedback  CFB: Cipher Feedback  CFB8 (CFB where the length of the data segment is 8 bits)  CFB16 (CFB where the length of the data segment is 16 bits)  CFB32 (CFB where the length of the data segment is 32 bits)  CFB64 (CFB where the length of the data segment is 64 bits) The data pre-processing, post-processing and data chaining for each mode are automatically performed. Refer to the FIPS Publication 81 for more complete information. These modes are selected by setting the OPMOD field in the TDES Mode Register (TDES_MR). In CFB mode, four data sizes are possible (8, 16, 32 and 64 bits), configurable by means of the CFBS field in the mode register. (See “TDES Mode Register” on page 1712.). The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD=1 in TDES_MR register). 52.4.2 Start Modes The SMOD field in the TDES Mode Register (TDES_MR) allows selection of encryption (or decryption) start mode. 52.4.2.1 Manual Mode The sequence order is as follows:  Write the Mode Register (TDES_MR) with all required fields, including but not limited to SMOD and OPMOD.  Write the 64-bit key(s) in the different Key Word Registers (TDES_KEYxWRx), depending on whether one, two or three keys are required.  Write the initialization vector (or counter) in the Initialization Vector Registers (TDES_IVRx). Note: The Initialization Vector Registers concern all modes except ECB.  Set the bit DATRDY (Data Ready) in the TDES Interrupt Enable register (TDES_IER), depending on whether an interrupt is required or not at the end of processing.  Write the data to be encrypted/decrypted in the authorized Input Data Registers (See Table 52-1). Table 52-1. Authorized Input Data Registers Operation Mode Input Data Registers to Write ECB All CBC All Note: OFB All CFB 64-bit All CFB 32-bit TDES_IDATAR0 CFB 16-bit TDES_IDATAR0 CFB 8-bit TDES_IDATAR0 In 32-bit, 16-bit and 8-bit CFB mode, writing to TDES_IDATAR1 register is not allowed and may lead to errors in processing.  Set the START bit in the TDES Control register TDES_CR to begin the encryption or the decryption process.  When the processing completes, the bit DATRDY in the TDES Interrupt Status Register (TDES_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in TDES_IER, the interrupt line of the TDES is activated. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1705  When the software reads one of the Output Data Registers (TDES_ODATARx), the DATRDY bit is automatically cleared. 52.4.2.2 Auto Mode The Auto Mode is similar to Manual Mode, except that, as soon as the correct number of Input Data registers is written, processing is automatically started without any action in the control register. 52.4.2.3 DMA Mode The DMA Controller can be used in association with the TDES to perform an encryption/decryption of a buffer without any action by the software during processing. The SMOD field of TDES_MR must be set to 0x2 and the DMA must be configured with non-incremental addresses. The start address of any transfer descriptor must be set in TDES_IDATAR0 register. The DMA chunk size configuration depends on the TDES mode of operation and is listed in Table 52-2 "DMA Data Transfer Type for the Different Operation Modes". When writing data to TDES with the first DMA channel, data will be fetched from a memory buffer (source data). It is recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data size depends on the mode of operation. When reading data from the TDES with the second DMA channel, the source data is the data read from TDES and data destination is the memory buffer. In this case, source data size depends on the TDES mode of operation and is listed in Table 52-2. Table 52-2. DMA Data Transfer Type for the Different Operation Modes Operation Mode Chunk Size Destination/Source Data Transfer Type ECB 1 Word CBC 1 Word OFB 1 Word CFB 64-bit 1 Word CFB 32-bit 1 Word CFB 16-bit 1 Half-word CFB 8-bit 1 Byte 52.4.3 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) using a CBC-MAC or a CFB encryption algorithm (See FIPS Publication 81 Appendix F). After each end of encryption/decryption, the output data is available either on the output data registers for Manual and Auto mode or at the address specified in the receive buffer pointer for DMA mode (See Table 52-3 "Last Output Data Mode Behavior versus Start Modes"). The Last Output Data bit (LOD) in the TDES Mode Register (TDES_MR) allows retrieval of only the last data of several encryption/decryption processes. This data is only available on the Output Data Registers (TDES_ODATARx). No more Output Data Register reads are necessary between consecutive encryptions/decryptions. Therefore, there is no need to define a read buffer in DMA mode. 52.4.3.1 Manual and Auto Modes If LOD = 0: The DATRDY flag is cleared when at least one of the Output Data Registers is read. See Figure 52-1. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1706 Figure 52-1. Manual and Auto Modes with LOD = 0 Write START bit in TDES_CR(Manual mode) or Write TDES_IDATARx register(s) (Auto mode) Read the TDES_ODATARx DATRDY Encryption or Decryption Process If the user does not want to read the output data registers between each encryption/decryption, the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user will not be informed of the end of the encryptions/decryptions that follow. If LOD = 1: The DATRDY flag is cleared when at least one Input Data Register is written, before the start of a new transfer. See Figure 52-2. No further Output Data Register reads are necessary between consecutive encryptions/decryptions. Figure 52-2. Manual and Auto Modes with LOD = 1 Write START bit in TDES_CR(Manual mode) or Write TDES_IDATARx register(s) (Auto mode) Write TDES_IDATARx register(s) DATRDY Encryption or Decryption Process 52.4.3.2 DMA Mode If LOD = 0 This mode may be used for all TDES operating modes except CBC-MAC where LOD = 1 mode is recommended. The end of the encryption/decryption is notified by the end of DMA transfer associated to TDES_ODATARx registers (see Figure 52-3). Two DMA channels are required, one for writing message blocks to TDES_IDATARx registers and the other one to get back the processed from TDES_ODATARx registers. Figure 52-3. DMA transfer with LOD = 0 Enable DMA Channels associated to TDES_IDATARx and TDES_ODATARx Multiple Encryption or Decryption Processes Write accesses into TDES_IDATARx BTC /channel 0 Read accesses into TDES_ODATARx BTC /channel 1 Message fully processed (cipher or decipher) last block can be read SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1707 If LOD = 1 This mode is recommended to process TDES CBC-MAC operating mode. The user must first wait for the DMA flag (BTC = Buffer Transfer Complete) to rise, then for DATRDY to ensure that the encryption/decryption is completed (see Figure 52-4). In this case, no receive buffers are required. The output data is only available on the Output Data Registers (TDES_ODATARx). Figure 52-4. DMA transfer with LOD = 1 Enable DMA Channels associated with TDES_IDATARx and TDES_ODATARx registers Multiple Encryption or Decryption Processes Write accesses into TDES_IDATARx BTC / channel 0 DATRDY Message fully transferred Message fully processed (cipher or decipher) MAC result can be read Table 52-3 summarizes the different cases. Table 52-3. Last Output Data Mode Behavior versus Start Modes Manual and Auto Modes DMA Transfer LOD = 0 LOD = 1 LOD = 0 LOD = 1 DATRDY Flag Clearing Condition(1) At least one Output Data Register must be read At least one Input Data Register must be written Not used Managed by the DMA Encrypted/Decrypted Data Result Location In the Output Data Registers In the Output Data Registers Not available In the Output Data Registers End of Encryption/Decryption DATRDY DATRDY 2 DMA flags (BTC[n/m]) DMA flag (BTC[n]) then TDES DATRDY Note: Depending on the mode, there are other ways of clearing the DATRDY flag. See: Section 52.5.6 ”TDES Interrupt Status Register”. Warning: In DMA mode, reading to the Output Data registers before the last data transfer may lead to unpredictable results. 52.4.4 Security Features 52.4.4.1 Unspecified Register Access Detection When an unspecified register access occurs, the URAD bit in the Interrupt Status Register (TDES_ISR) raises. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur:  Input Data Register written during the data processing in DMA mode  Output Data Register read during the data processing  Mode Register written during the data processing  Write-only register read access SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1708 The URAD bit and the URAT field can only be reset by the SWRST bit in the TDES_CR control register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1709 52.5 Triple Data Encryption Standard (TDES) User Interface Table 52-4. Register Mapping Offset Register Name Access Reset 0x00 Control Register TDES_CR Write-only – 0x04 Mode Register TDES_MR Read-write 0x2 0x08-0x0C Reserved – – – 0x10 Interrupt Enable Register TDES_IER Write-only – 0x14 Interrupt Disable Register TDES_IDR Write-only – 0x18 Interrupt Mask Register TDES_IMR Read-only 0x0 0x1C Interrupt Status Register TDES_ISR Read-only 0x0000001E 0x20 Key 1 Word Register 0 TDES_KEY1WR0 Write-only – 0x24 Key 1 Word Register 1 TDES_KEY1WR1 Write-only – 0x28 Key 2 Word Register 0 TDES_KEY2WR0 Write-only – 0x2C Key 2 Word Register 1 TDES_KEY2WR1 Write-only – 0x30 Key 3 Word Register 0 TDES_KEY3WR0 Write-only – 0x34 Key 3 Word Register 1 TDES_KEY3WR1 Write-only – – – – 0x38-0x3C Reserved 0x40 Input Data Register 0 TDES_IDATAR0 Write-only – 0x44 Input Data Register 1 TDES_IDATAR1 Write-only – – – – 0x48-0x4C Reserved 0x50 Output Data Register 0 TDES_ODATAR0 Read-only 0x0 0x54 Output Data Register 1 TDES_ODATAR1 Read-only 0x0 – – – 0x58-0x5C Reserved 0x60 Initialization Vector Register 0 TDES_IVR0 Write-only – 0x64 Initialization Vector Register 1 TDES_IVR1 Write-only – – – – 0x68 - 0xFC Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1710 52.5.1 TDES Control Register Name: TDES_CR Address: 0xF803C000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START • START: Start Processing 0: No effect 1: Starts Manual encryption/decryption process. • SWRST: Software Reset 0: No effect. 1: Resets the TDES. A software triggered hardware reset of the TDES interface is performed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1711 52.5.2 TDES Mode Register Name: TDES_MR Address: 0xF803C004 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 LOD – – – OPMOD 16 CFBS 9 8 SMOD 7 6 5 4 3 2 1 0 – – – KEYMOD – – TDESMOD CIPHER • CIPHER: Processing Mode 0 (DECRYPT): Decrypts data. 1 (ENCRYPT): Encrypts data. • TDESMOD: ALGORITHM mode 0 (SINGLE_DES): Single DES processing using TDES_KEY1WRx registers. 1 (TRIPLE_DES): Triple DES processing using registers TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx if KEYMOD is set. • KEYMOD: Key Mode 0: Three-key algorithm is selected. 1: Two-key algorithm is selected. There is no need to write TDES_KEY3WRx registers. • SMOD: Start Mode Value Name Description 0x0 MANUAL_START Manual Mode 0x1 AUTO_START Auto Mode 0x2 IDATAR0_START TDES_IDATAR0 access only Auto Mode Values which are not listed in the table must be considered as “reserved”. If a DMA transfer is used, 0x2 must be configured. Refer to Section 52.4.3.2 ”DMA Mode” for more details. • OPMOD: Operation Mode Value Name Description 0x0 ECB ECB: Electronic Code Book mode 0x1 CBC CBC: Cipher Block Chaining mode 0x2 OFB OFB: Output Feedback mode 0x3 CFB CFB: Cipher Feedback mode For CBC-MAC operating mode, please set OPMOD to CBC and LOD to 1. The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD=1). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1712 • LOD: Last Output Data Mode 0: No effect. After each end of encryption/decryption, the output data is available either on the output data registers (Manual and Auto modes). In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1: The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads are necessary between consecutive encryptions/decryptions (See “Last Output Data Mode” on page 1706.). Warning: In DMA mode, reading to the Output Data registers before the last data encryption/decryption process may lead to unpredictable result. • CFBS: Cipher Feedback Data Size Value Name Description 0x0 SIZE_64BIT 64-bit 0x1 SIZE_32BIT 32-bit 0x2 SIZE_16BIT 16-bit 0x3 SIZE_8BIT 8-bit SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1713 52.5.3 TDES Interrupt Enable Register Name: TDES_IER Address: 0xF803C010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable • URAD: Unspecified Register Access Detection Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1714 52.5.4 TDES Interrupt Disable Register Name: TDES_IDR Address: 0xF803C014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable • URAD: Unspecified Register Access Detection Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1715 52.5.5 TDES Interrupt Mask Register Name: TDES_IMR Address: 0xF803C018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask • URAD: Unspecified Register Access Detection Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1716 52.5.6 TDES Interrupt Status Register Name: TDES_ISR Address: 0xF803C01C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data is not valid. 1: Encryption or decryption process is completed. DATRDY is cleared when a Manual encryption/decryption occurs (START bit in TDES_CR) or when a software triggered hardware reset of the TDES interface is performed (SWRST bit in TDES_CR). LOD = 0 (TDES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Output Data Registers is read. LOD = 1 (TDES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Input Data Registers is written. • URAD: Unspecified Register Access Detection Status 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAD bit is reset only by the SWRST bit in the TDES_CR control register. • URAT: Unspecified Register Access Value Name Description 0x0 IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD=0x2 mode. 0x1 ODR_RD_PROCESSING Output Data Register read during the data processing. 0x2 MR_WR_PROCESSING Mode Register written during the data processing. 0x3 WOR_RD_ACCESS Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field. URAT field is reset only by the SWRST bit in the TDES_CR control register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1717 52.5.7 TDES Key 1 Word Register x Name: TDES_KEY1WRx Address: 0xF803C020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1W 23 22 21 20 KEY1W 15 14 13 12 KEY1W 7 6 5 4 KEY1W • KEY1W: Key 1 Word The two 32-bit Key 1 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption. KEY1W0 corresponds to the first word of the key and KEY1W1 to the last one. These registers are write-only to prevent the key from being read by another application. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1718 52.5.8 TDES Key 2 Word Register x Name: TDES_KEY2WRx Address: 0xF803C028 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2W 23 22 21 20 KEY2W 15 14 13 12 KEY2W 7 6 5 4 KEY2W • KEY2W: Key 2 Word The two 32-bit Key 2 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption. KEY2W0 corresponds to the first word of the key and KEY2W1 to the last one. These registers are write-only to prevent the key from being read by another application. Note: KEY2WRx registers are not used in DES mode. . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1719 52.5.9 TDES Key 3 Word Register x Name: TDES_KEY3WRx Address: 0xF803C030 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY3W 23 22 21 20 KEY3W 15 14 13 12 KEY3W 7 6 5 4 KEY3W • KEY3W: Key 3 Word The two 32-bit Key 3 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption. KEY3W0 corresponds to the first word of the key and KEY3W1 to the last one. These registers are write-only to prevent the key from being read by another application. Note: KEY3WRx registers are not used in DES mode, TDES with two-key algorithm selected. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1720 52.5.10 TDES Input Data Register x Name: TDES_IDATARx Address: 0xF803C040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA • IDATA: Input Data The two 32-bit Input Data registers allow to set the 64-bit data block used for encryption/decryption. IDATA0 corresponds to the first word of the data to be encrypted/decrypted, and IDATA1 to the last one. These registers are write-only to prevent the input data from being read by another application. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1721 52.5.11 TDES Output Data Register x Name: TDES_ODATARx Address: 0xF803C050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA • ODATA: Output Data The two 32-bit Output Data registers contain the 64-bit data block which has been encrypted/decrypted. ODATA1 corresponds to the first word, ODATA2 to the last one. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1722 52.5.12 TDES Initialization Vector Register x Name: TDES_IVRx Address: 0xF803C060 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV • IV: Initialization Vector The two 32-bit Initialization Vector registers are used to set the 64-bit initialization vector data block, which is used by some modes of operation as an additional initial input. IV1 corresponds to the first word of the Initialization Vector, IV2 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application. Note: These registers are not used for ECB mode and must not be written. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1723 53. Secure Hash Algorithm (SHA) 53.1 Description The Secure Hash Algorithm (SHA) is compliant with the American FIPS (Federal Information Processing Standard) Publication 180-2 specification. The 512/1024-bit block of message is respectively stored in 16/32 x 32-bit registers (SHA_IDATARx/SHA_IODATARx) which are all write-only. As soon as the input data is written, the hash processing may be started. The registers comprising the block of a padded message must be entered consecutively. Then the message digest is ready to be read out on the 5 up to 8/16 x 32-bit output data registers (SHA_IODATARx) or through the DMA channels. 53.2 53.3 Embedded Characteristics  Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)  Compliant with FIPS Publication 180-2  Configurable Processing Period:  85 Clock Cycles to get a fast SHA1 runtime, 88 clock cycles for SHA384,SHA512 or 209 Clock Cycles for Maximizing Bandwidth of Other Applications  72 Clock Cycles to get a fast SHA224, SHA256 runtime or 194 Clock Cycles for Maximizing Bandwidth of Other Applications  Connection to DMA Channel Capabilities Optimizes Data Transfers  Double Input Buffer Optimizes Runtime Product Dependencies 53.3.1 Power Management The SHA may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the SHA clock. 53.3.2 Interrupt The SHA interface has an interrupt line connected to the Interrupt Controller. Handling the SHA interrupt requires programming the interrupt controller before configuring the SHA. Table 53-1. Peripheral IDs Instance ID SHA 42 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1724 53.4 Functional Description The Secure Hash Algorithm (SHA) module requires a padded message according to FIPS180-2 specification. The first block of the message must be indicated to the module by a specific command. The SHA module produces a N-bit message digest each time a block is written and processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256, 384 for SHA384, 512 for SHA512. 53.4.1 SHA Algorithm The module can process SHA1, SHA224, SHA256, SHA384, SHA512 by means of a configuration field in the SHA_MR register. 53.4.2 Processing Period The processing period can be configured. The short processing period allows to allocate bandwidth to the SHA module whereas the long processing period allocates more bandwidth on the system bus to other applications (example: DMA channels not associated with SHA). In SHA1 mode, the shortest processing period is 85 clock cycles + 2 clock cycles for start command synchronization. The longest period is 209 clock cycles + 2 clock cycles. In SHA384, SHA512 mode, the shortest processing period is 88 clock cycles + 2 clock cycles for start command synchronization. The longest period is 209 clock cycles + 2 clock cycles. In SHA256 and SHA224 mode, the shortest processing period is 72 clock cycles + 2 clock cycles for start command synchronization. The longest period is 194 clock cycles + 2 clock cycles. 53.4.3 Double Input Buffer The input data register can be double-buffered to reduce the runtime of large files. This mode allows to write a new message block while the previous message block is being processed. This is only possible when DMA accesses are performed (SMOD=0x2). The DUALBUFF field in SHA_MR register must be set to 1 to get access to double buffer. 53.4.4 Start Modes The SMOD field in the SHA Mode Register (SHA_MR) is used to select the hash processing start mode. 53.4.4.1 Manual Mode The sequence is as follows:  Set the bit DATRDY (Data Ready) in the SHA Interrupt Enable Register (SHA_IER), depending on whether an interrupt is required or not at the end of processing.  For the first block of a message, the FIRST command must be set by writing a 1 into the corresponding bit of the Control Register (SHA_CR). For the other blocks, there is nothing to write in this Control Register.  Write the block to be processed in the Input Data Registers.  Set the START bit in the SHA Control Register SHA_CR to begin the processing.  When the processing completes, the bit DATRDY in the SHA Interrupt Status Register (SHA_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated.  Repeat the write procedure for each block, start procedure and wait for the interrupt procedure up to the last block of the entire message. Each time the start procedure is complete, the DATRDY flag is cleared.  After the last block is processed (DATRDY flag is set, if an interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated), read the message digest in the Output Data Registers. The DATRDY flag is automatically cleared when reading the SHA_IODATARx registers. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1725 53.4.4.2 Auto Mode Auto Mode is similar to Manual Mode, except that in this mode, as soon as the correct number of Input Data Registers is written, processing is automatically started without any action in the control register. 53.4.4.3 DMA Mode The DMA can be used in association with the SHA to perform the algorithm on a complete message without any action by the software during processing. The SMOD field of the SHA_MR must be set to 0x2. The DMA must be configured with non incremental addresses. The start address of any transfer descriptor must be set to point to the SHA_IDATAR0 register. The DMA chunk size must be set to transfer, for each trigger request, 16 words of 32 bits when processing SHA1/SHA256 algorithms or 32 words of 32 bits when SHA384/SHA512 are being used. Figure 53-1. Enable DMA Channels Enable DMA Channels associa ted with SHA_IDATARx registers Message Processing (Multiple Block) BTC/ channel 0 Write accesses into SHA_IDATARx DATRDY Message fully transferred Message fully processed SHA e r sult can be ead r 53.4.4.4 SHA Register Endianism In ARM processor based products, the AHB bus and processors manipulate data in Little Endian form. However, following the protocol of FIPS 180-2 specification, data is collected, processed and stored by the SHA module in a Big Endian form. The data presented to the SHA module (written to SHA_IDATAxR) must be in Little Endian form. The data read from the SHA module (read from SHA_IODATAxR) will be in Little Endian form. The SHA interface automatically converts into Big Endian format words that are presented into Little Endian. Likewise, the SHA interface returns hash results into Little Endian format even if the internal processing is Big Endian. Managing how data is presented to the SHA registers should be managed by software. As a clarification of this process consider the following example. If the first 64 bits of a message (according to FIPS180-2, i.e. Big Endian format) to be processed is 0xcafe_dede_0123_4567 then the SHA_IDATA0R and SHA_IDATA1R registers should be written with the following pattern:  SHA_IDATA0R = 0xefac  SHA_IDATA1R = 0xeded In a Little Endian system, the message starting with pattern 0xcafe_dede_0123_4567 will be stored into memories as follows:  0xca stored at initial offset (for example 0x00),  then 0xfe stored at initial offset + 1 (i.e. 0x01),  0xde stored at initial offset + 2 (i.e. 0x02),  0xde stored at initial offset +3 (i.e. 0x03). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1726 Let’s assume the message is received through a serial to parallel communication channel, the first received character is 0xca and stored at first memory location (initial offset), second octet being 0xfe is stored at initial offset + 1. When reading on a 32-bit Little Endian system bus, the first word read back from system memory is 0x_dede_feca. When the SHA_IODATAxR registers are read, the hash result is organized in Little Endian format, allowing system memory storage in the same format as the message. Taking an example from the FIPS 180-2 specification Appendix B.1, the endianism conversion can be observed. For this example, the 512-bit message is: 0x6162638000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000000018 and the expected SHA-256 result is: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad If the message has not already been stored in the system memory, the first step is to convert the input message to Little Endian before writing to the SHA_IDATAxR registers. This would result in a write of: SHA_IDATA0R = 0x80636261...... SHA_IDATA15R = 0x18000000 The data in the output message digest registers, SHA_IODATAxR, contain SHA_IODATAxR = 0xbf1678ba... SHA_IODATA7R = 0xad1500f2 which is the Little Endian format of 0xba7816bf,..., 0xf20015ad. Reading SHA_IODATA0R to SHA_IODATA1R and storing into a Little Endian memory system forces hash results to be stored in the same format as the message. When the output message is read, the user can convert back to Big Endian for a resulting message value of: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad 53.4.5 Security Features When an unspecified register access occurs, the URAD bit in the Interrupt Status Register (SHA_ISR) raises. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur:  Input Data Register written during the data processing in DMA mode  Input/Output Data Register read during the data processing  Mode Register written during the data processing  Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in the SHA_CR control register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1727 53.5 Secure Hash Algorithm (SHA) User Interface Table 53-2. Register Mapping Offset Register Name Access Reset 0x00 Control Register SHA_CR Write-only – 0x04 Mode Register SHA_MR Read-write 0x0000100 0x08-0x0C Reserved – – – 0x10 Interrupt Enable Register SHA_IER Write-only – 0x14 Interrupt Disable Register SHA_IDR Write-only – 0x18 Interrupt Mask Register SHA_IMR Read-only 0x0 0x1C Interrupt Status Register SHA_ISR Read-only 0x0 0x20-0x3C 0x40 ... Reserved Input Data 0 Register ... – SHA_IDATAR0 Write-only – ... ... ... 0x7C Input Data 15 Register SHA_IDATAR15 Write-only – 0x80 Input/Output Data 0 Register SHA_IODATAR0 Read-write 0x0 ... ... ... ... ... 0x9C Input/Output Data 7 Register SHA_IODATAR7 Read-write 0x0 0xA0 Input/Output Data 8 Register SHA_IODATAR8 Read-write 0x0 ... ... ... SHA_IODATAR15 Read-write 0x0 – – – ... 0xBC 0x94-0xFC ... Input/Output Data 15 Register Reserved SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1728 53.5.1 SHA Control Register Name: SHA_CR Address: 0xF8034000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – FIRST – – – START • START: Start Processing 0: No effect 1: Starts Manual hash algorithm process • FIRST: First Block of a Message 0: No effect 1: Indicates that the next block to process is the first one of a message. • SWRST: Software Reset 0: No effect. 1: Resets the SHA. A software triggered hardware reset of the SHA interface is performed. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1729 53.5.2 SHA Mode Register Name: SHA_MR Address: 0xF8034004 Access: Read-write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – DUALBUFF 15 14 13 12 11 10 9 8 – – – 7 6 – 5 ALGO 4 3 2 PROCDLY – – 1 0 SMOD • SMOD: Start Mode Value Name Description 0x0 MANUAL_START Manual Mode 0x1 AUTO_START Auto Mode 0x2 IDATAR0_START SHA_IDATAR0 access only Auto Mode Values which are not listed in table must be considered as “reserved”. If a DMA transfer is used, either 0x1 or 0x2 must be configured. Refer to “DMA Mode” on page 1726 for more details. • PROCDLY: Processing Delay Value Name Description 0x0 SHORTEST SHA processing runtime is the shortest one 0x1 LONGEST SHA processing runtime is the longest one When SHA1 algorithm is processed, runtime period is either 85 or 209 clock cycles. When SHA256 or SHA224 algorithm is processed, runtime period is either 72 or 194 clock cycles. When SHA384 or SHA512 algorithm is processed, runtime period is either 88 or 209 clock cycles. • ALGO: SHA Algorithm. Value Name Description 0x0 SHA1 SHA1 algorithm processed 0x1 SHA256 SHA256 algorithm processed 0x2 SHA384 SHA384 algorithm processed 0x3 SHA512 SHA512 algorithm processed 0x4 SHA224 SHA224 algorithm processed Values which are not listed in table must be considered as “reserved”. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1730 • DUALBUFF: Dual Input BUFFer Value Name Description 0x0 INACTIVE SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. 0x1 ACTIVE SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD=0x2. It speeds up the overall runtime of large files. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1731 53.5.3 SHA Interrupt Enable Register Name: SHA_IER Address: 0xF8034010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Enable • URAD: Unspecified Register Access Detection Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1732 53.5.4 SHA Interrupt Disable Register Name: SHA_IDR Address: 0xF8034014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Disable • URAD: Unspecified Register Access Detection Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1733 53.5.5 SHA Interrupt Mask Register Name: SHA_IMR Address: 0xF8034018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready Interrupt Mask • URAD: Unspecified Register Access Detection Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1734 53.5.6 SHA Interrupt Status Register Name: SHA_ISR Address: 0xF803401C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY • DATRDY: Data Ready 0: Output data is not valid. 1: 512-bit block process is completed. DATRDY is cleared when a Manual process occurs (START bit in SHA_CR) or when a software triggered hardware reset of the SHA interface is performed (SWRST bit in SHA_CR). • URAD: Unspecified Register Access Detection Status 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAD bit is reset only by the SWRST bit in the SHA_CR control register. URAT field indicates the unspecified access type. • URAT: Unspecified Register Access Type Value Description 0x0 Input Data Register 0 to 15 written during the data processing in DMA mode. (URAD=0x1 and URAT=0x0 can occur only if DUALBUFF is cleared in SHA_MR) 0x1 Output Data Register read during the data processing. 0x2 Mode Register written during the data processing. 0x3 Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field. URAT field is reset only by the SWRST bit in the SHA_CR control register. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1735 53.5.7 SHA Input Data x Register Name: SHA_IDATARx [x=0.15] Address: 0xF8034040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA • IDATA: Input Data The 32-bit Input Data registers allow to load the data block used for hash processing. These registers are write-only to prevent the input data from being read by another application. SHA_IDATAR0 corresponds to the first word of the block, SHA_IDATAR15 to the last word of the last block in case SHA algorithm is set to SHA1,SHA224,SHA256 or SHA_IODATA15R to the last word of the block if SHA algorithm is SHA384 or SHA512 (please refer to “SHA Input/Output Data x Register” on page 1737). SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1736 53.5.8 SHA Input/Output Data x Register Name: SHA_IODATARx [x=0.15] Address: 0xF8034080 Access: Read-write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IODATA 23 22 21 20 IODATA 15 14 13 12 IODATA 7 6 5 4 IODATA • IODATA: Input/Output Data These registers can be used to read the resulting message digest and to write the second part of the message block when the SHA algorithm is SHA-384 or SHA-512. SHA_IODATA0R to SHA_IODATA15R registers can be written or read but reading these offsets does not return the content of corresponding parts (words) of the message block. Only results from SHA calculation can be read through these registers. When SHA processing is in progress, these registers return 0x0000. SHA_IODATA0R corresponds to the first word of message digest; SHA_IODATA5R to the last one in SHA1 mode, SHA_ODATA6R in SHA224, SHA_IODATA7R in SHA256, SHA_IODATA11R in SHA384 or SHA_IODATA15R in SHA512. When SHA224 is selected, the content of SHA_ODATA7R must not be taken into account. When SHA384 is selected, the content of SHA_IODATA12R to SHA_IODATA15R must not be taken into account. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1737 54. Electrical Characteristics 54.1 Absolute Maximum Ratings Table 54-1. Absolute Maximum Ratings* *NOTICE: Junction Temperature..................................................125°C Storage Temperature.................................-60°C to +150°C Voltage on Input Pins with Respect to Ground.....-0.3V to VDDIO+0.3V(+ 4V max) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage (VDDCORE, VDDPLLA, VDDUTMIC)...........................1.5V (VDDIODDR).................................................................2.0V (VDDIOM, VDDIOPx, VDDUTMII, VDDOSC, VDDANA and VDDBU)..................................................4.0V (VDDFUSE)...................................................................3. 3V Total DC Output Current on all I/O lines...................350 mA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1738 54.2 DC Characteristics The following characteristics are applicable to the operating temperature range TA = -40°C to +105°C, unless otherwise specified. Table 54-2. DC Characteristics Symbol Parameter Conditions Min Typ Max Unit +105 °C TA Operating Temperature — -40 VVDDCORE Core DC Supply Voltage — 1.08 1.2 1.32 V VVDDUTMIC UDPHS and UHPHS UTMI+ Core DC Supply Voltage — 1.08 1.2 1.32 V VVDDUTMII UDPHS and UHPHS UTMI+ Interface DC Supply Voltage — 3.0 3.3 3.6 V VVDDBU Backup DC Supply Voltage — 1.65 — 3.6 V VVDDPLLA PLLA DC Supply Voltage — 1.08 1.2 1.32 V VVDDOSC Oscillator and PLL UTMI DC Supply Voltage If PLL UTMI is used the VVDDIO range is to be 3.0V to 3.6V 1.65 — 3.6 V VVDDIOM EBI I/Os DC Supply Voltage — 1.65/3.0 1.8/3.3 1.95/3.6 V SDRAM I/Os DC Supply Voltage DDR2 or LP-DDR usage 1.7 1.8 1.95 VVDDIODDR LP-DDR2 usage 1.14 1.2 1.30 VVDDIOP0 Peripheral I/Os DC Supply Voltage — 1.65 — 3.6 V VVDDIOP1 Peripheral I/Os DC Supply Voltage — 1.65 — 3.6 V VVDDFUSE FUSE Box DC Supply Voltage For FUSE programming only 2.25 2.5 2.75 V IVDDFUSE VDDFUSE current During FUSE programming — — 40 mA VVDDANA Analog DC Supply Voltage — 3.0 3.3 3.6 V — 0.8 Input Low-level Voltage VVDDIO in 3.3V range -0.3 VIL VVDDIO in 1.8V range -0.3 — 0.3 x VVDDIO — Input High-level Voltage VVDDIO in 3.3V range 2 VIH VVDDIO + 0.3 VVDDIO in 1.8V range 0.7 x VVDDIO — VVDDIO + 0.3 All PIO lines VVDDIOx in 3.3V range 0.34 — — All PIO lines VVDDIOx in 1.8V range 0.21 — — VHYS Schmitt trigger Hysteresis V V V V VOL Output Low-level Voltage IO Max — — 0.4 V VOH Output High-level Voltage IO Max VVDDIO - 0.4 — — V 100 160 310 45 70 130 RPULL Pull-up Resistance Pull-down Resistance All PIO lines VVDDIOx in 1.8V range All PIO lines NTRST and NRST kΩ VVDDIOx in 3.3V range SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1739 Table 54-2. DC Characteristics (Continued) Symbol Parameter Conditions Min TDI, TCK, NTRST, BMS, TMS, TDO, NRST, NANDRDY, PA0-PA27, PA29PA31, PB28-PB31, PC0-PC14, PC16PC23, PC25-PC31, PD0-PD8, PD10PD11, PD13-PD31 Typ Max 5 16 22 (LO_DRIVE) (ME_DRIVE) (HI_DRIVE) 8 26 38 (LO_DRIVE) (ME_DRIVE) (HI_DRIVE) 3 6 7 (LO_DRIVE) (ME_DRIVE) (HI_DRIVE) TMS, TDO, NRST, NANDRDY, PA0-PA27, PA29-PA31, PB28-PB31, PC0-PC14, PC16-PC23, PC25-PC31, PD0-PD8, PD10-PD11, PD13-PD19 — 30 — NCS3, NRD, NWE, PA28, PB0-PB27, PC15, PC24, PD9, PD12, PE0-PE31, D0D15 — 13 — On VVDDCORE = 1.1V, TA = 25°C — 0.4 — MCK = 0 Hz, excluding POR TA = 85°C — — 4.3 All inputs driven TMS, TDI, TCK, NRST = 1 TA = 105°C — — 8.2 On VVDDBU = 3.3V, TA = 25°C — 1.2 — Logic cells consumption, excluding POR TA = 85°C — 1.4 — All inputs driven WKUP = 0 TA = 105°C — 1.8 2.6 Unit VVDDIOPx in 1.8V range IO Output Current TDI, TCK, NTRST, BMS, TMS, TDO, NRST, NANDRDY, PA0-PA27, PA29PA31, PB28-PB31, PC0-PC14, PC16PC23, PC25-PC31, PD0-PD8, PD10PD11, PD13-PD31 mA VVDDIOPx in 3.3V range NCS3, NRD, NWE, PA28, PB0-PB27, PC15, PC24, PD9, PD12, PE0-PE31, D0D15 RSERIAL ISC Serial Resistor Static Current Ω SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 mA µA 1740 54.3 Power Consumption  Typical power consumption of PLLs, Slow Clock and Main Oscillator  Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup  Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock  Software used for power consumption measurements: DHRYSTONE  The Instruction and Data Caches are enabled. The Memory Management Unit (MMU) is enabled. 54.3.1 Static current Static current is measured when the system has no activity at all. It is also called leakage current and is very sensitive to process and operating temperature. This means the value may fluctuate drastically between two different devices, and vary according to the operating temperature. Figures are given in Table 54-2. This variation explains most of the difference between two measures done on different devices or with different temperatures. 54.3.2 Active Mode Active Mode is the normal running mode with the core clock running from a PLL. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. Note: Active power consumption may vary for ±5% depending on compilator used and process. 54.3.3 Low-power Modes The various low-power modes are described below in the following subsections. 54.3.3.1 Backup Mode The purpose of Backup Mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time. The Zero-power Power-on Reset, RTC, Backup registers and 32 kHz oscillator (RC or Crystal Oscillator selected by software in the Supply Controller) are running. The core supply is off. The system can be awakened from this mode through the WKUP0 pin or an RTC wake-up event. Backup mode is entered with the help of the Shutdown Controller that asserts the SHDN output pin. The SHDN pin is to be connected to the enable pin of the VDDCORE regulator. Exit from Backup mode happens if one of the following enable wake-up events occurs:  WKUP0 pin (level transition, configurable debouncing)  RTC alarm The system will restart as for a reset event. 54.3.3.2 Idle Mode The purpose of Idle Mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks, including the DDR Controller clock, can be enabled. The current consumption in this mode is application dependent. This mode is entered via the Wait for Interrupt (WFI) instruction and PCK disabling. The processor can be awakened from an interrupt. The system will resume where it was before entering in WFI mode. Note: The power consumption includes the static current. 54.3.3.3 Ultra Low-power Mode The purpose of Ultra Low-power Mode is to reduce the power consumption of the device to the minimum without disconnecting VDDCORE power supply. It is a combination of very low frequency operations and Idle Mode. This mode is entered via the following steps: SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1741 1. Set the DDR in Self Refresh Mode 2. Reduce the system clock (PCK and MCK) to the minimum with the help of the PMC: 3.  PCK and MCK configuration is to be defined regarding the expected power consumption and wake-up time. Please refer to Table 54-3 for details  PLLs are disabled. CKGR_PLLAR (eventually CKGR_PLLBR) is set to 0x3F00. CKGR_UCKR is set to 0.  Main oscillator is disabled. MOSCXTEN is set to 0 in CKGR_MOR.  Eventually 12 MHz RC oscillator is disabled. MOSCRCEN is set to 0 in CKGR_MOR. Enter in Wait for Interrupt (WFI) mode and disable the PCK clock. The processor can be awakened from an interrupt. Once revived, the system must reprogram the system clocks (OSC, PLL, PCK, MCK, DDRCK) to recover the previous state. Data is maintained in the external memory. 54.3.3.4 Low-power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake-up sources can be individually configured. Table 54-3 below shows a summary of the configurations of the low-power modes. Table 54-3. Low-power Mode Configuration Summary Mode 32K RC, 12 MHz RC, 32 kHz Osc, RTC, Backup Registers, POR VDDCORE Core (Backup External Memory Region) Regulator Peripherals Mode Entry Backup ON OFF OFF (not powered) Idle ON ON Powered (not WFI clocked) Ultra Lowpower ON ON Shutdown Controller DDR in Self Powered (not Refresh clocked) PMC Potential Wake-Up Sources Core at Wake Up WKUP0 pin Reset RTC alarm Any interrupt PIO State while in Low-power PIO State Mode at Wake Up Consumption(2) Reset Inputs with pull-ups 1.2 µA typ(3) Wake-Up Time(1) Start-up time See Table 54-7 Clocked back Previous 285 ns @ Unchanged 10 mA for each at full speed state saved 132 MHz PLL(4) Clocked back Previous Any interrupt at previous Unchanged See Table 54-8 See Table 54-8 state saved one WFI Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the Main Oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. The external loads on PIOs are not taken into account in the calculation. 3. Total current consumption 4. Depends on PLL frequency SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1742 54.3.4 Power Consumption versus Modes The values in Table 54-4, Table 54-5, Table 54-6, Table 54-7, and Table 54-8 are measured values of the power consumption under the following operating conditions:  Parts are from typical process  VDDIOM = 1.8 V  VDDIOP0 and 1 = 3.3 V  VDDPLLA = 1.2 V  VDDCORE = 1.2 V unless specified otherwise in the table  VDDBU = 3.3 V  TA = as specified in the table  There is no consumption on the I/Os of the device  All the peripheral clocks are disabled Figure 54-1. Measures Schematics VDDBU AMP1 VDDCORE AMP2 Table 54-4. VDDCORE Power Consumption in Active Mode (AMP2) Consumption Mode Active Active Active Conditions VDDCORE TA 25°C TA 85°C TA 105°C Unit 1.2 V 90 95 101 mA 1.26 V 117 124 129 mA 1.26 V 117 124 129 mA ARM Core clock is 396 MHz. MCK is 132 MHz. ARM Core clock is 498 MHz. MCK is 166 MHz. ARM Core clock is 528 MHz. MCK is 132 MHz. Table 54-5. Power Consumption by Peripheral in Active Mode (TA 25°C, TA 85°C and TA 105°C) Max Frequency (MHz)(1) Consumption µA/MHz(2) PIO Controller 133 4.5 — USART 66 3.0 — 12 No activity 98 Connect tested EK (as USB Host) to another A5 EK (as USB Device), writing a file into USB key @ 10 MB/s, CPU usage 24%. This includes DDR2 controller power consumption on VDDCORE. Power consumption = 9.6 × transfer speed (MB/s) + 12 Peripheral UHPHS 133 Conditions SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1743 Table 54-5. Power Consumption by Peripheral in Active Mode (TA 25°C, TA 85°C and TA 105°C) (Continued) Peripheral Max Frequency (MHz)(1) Consumption µA/MHz(2) Conditions 31 No activity 88 Connect EK to PC. Read/write a file into DDR2 memory @ 14 MB/s, CPU usage = 17%. Power consumption = 4.1 × transfer speed (MB/s) + 31 UDPHS 133 ADC 66 4.0 — TWI 66 1.3 — SPI 133 2.5 — PWM 133 6.5 — HSMCI 133 14.5 — SSC 66 3.5 — Timer Counter Channels 133 3.0 — DMA 133 50 No activity 66 Data transfer from IF0 to IF1 with 64-byte full FIFO. Bandwidth usage is about 51%. Power consumption = 32.2 × bandwidth usage + 50. SMD 24 5.5 — ISI 133 30 — 7 No activity EMAC GMAC LCDC 133 133 174 EK is acting as a server. CPU usage is 16%. Power consumption = 4.2 × transfer speed (Mb/s) + 7. This includes DDR2 controller power consumption on VDDCORE. 36 No activity 160 EK is acting as a server. CPU usage is 24%. Power consumption = 1.2 × transfer speed (Mb/s) + 36. This includes DDR2 controller power consumption on VDDCORE. 13.0 No activity 160 Frame rate is 43 fps, 5 layers (Base 800px*600px, Ovr1 640px*480px, Ovr2 640px*480px, HEO 32px*48px, Cur 128px*128px), 24-bit data path, pixel clock is 44 MHz. This includes DDR2 controller power consumption on VDDCORE. 230 Frame rate is maximum (85 fps), 5 layers (Base 800px*600px, Ovr1 640px*480px, Ovr2 640px*480px, HEO 32px*48px, Cur 128px*128px), 24-bit data path, pixel clock is 44 MHz. This includes DDR2 controller power consumption on VDDCORE. 133 CAN 66 4.5 — SHA 133 4.0 — AES 133 2.0 — TDES 133 1.0 — TRNG 133 0.2 — Notes: 1. In order to reduce power consumption, each Peripheral Clock has been timed to an optimum value. The peripheral frequency is programmable with the help of a divider in the PMC_PCR. Programming a divider giving higher frequency than required will lead to an unpredictable behavior. 2. Reference frequency is the peripheral frequency. It can be a division (1, 2, 4, 8) of MCK. Please refer to the PMC section for more details. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1744 Table 54-6. VDDBU Power Consumption in Backup mode (AMP1) Consumption Mode Conditions Backup Backup Mode VDDBU 3.3V TA 25°C TA 85°C Unit TA 105°C 1.2 TYP 1.4 TYP 1.9 TYP 1.4 MAX 1.8 MAX 2.6 MAX µA Table 54-7. VDDCORE Power Consumption in Idle Mode (AMP2) Consumption (mA) Mode Conditions VDDCORE TA 25°C TA 85°C TA 105°C Wakeup Time (ns) 1.2V 24 29 33 285 ARM Core clock is disabled. Idle MCK is 132 MHz. Table 54-8. VDDCORE Power Consumption in Ultra Low-Power Mode (AMP2) Consumption (mA) Mode Conditions ULP 12MHz ULP 750kHz ULP 187MHz ULP 32kHz ULP 512Hz 54.4 VDDCORE TA 25°C TA 85°C TA 105°C Wakeup Time (µs) 1.2V 1.68 5.5 9.6 3.80 1.2V 0.5 4.3 8.4 60.8 1.2V 0.43 4.3 8.3 246 1.2V 0.40 4.2 8.2 1390 1.2V 0.40 4.1 8.2 88400 ARM Core clock is disabled. MCK is 12 MHz. ARM Core clock is disabled. MCK is 750 kHz. ARM Core clock is disabled. MCK is 187.5 kHz. ARM Core clock is disabled. MCK is 32 kHz. ARM Core clock is disabled. MCK is 512 Hz. Clock Characteristics 54.4.1 Processor Clock Characteristics Table 54-9. Processor Clock Waveform Parameters Symbol 1/(tCPPCK) Note: Parameter Processor Clock Frequency Conditions VDDCORE[1.08V, 1.32V], TA = 85°C VDDCORE[1.2V, 1.32V], TA = 85°C Min Max (1) 400 (1) 536 250 250 Unit MHz 1. Limitation for DDR2 usage only. There are no limitations to LP-DDR and LP-DDR2. Ratio between PCK and MCK must be DIV2, DIV3 or DIV4. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1745 54.4.2 Master Clock Characteristics The master clock is the maximum clock at which the system is able to run. It is given by the smallest value of the internal bus clock and EBI clock. Table 54-10. Master Clock Waveform Parameters Symbol 1/(tCPMCK) Note: Parameter Master Clock Frequency Conditions Min Max VDDCORE[1.08V, 1.32V], TA = 85°C 125(1) 134 VDDCORE[1.2V, 1.32V], VDDIODDR[1.75V, 1.9V], DDR2 mode only, TA = 85°C 125(1) 166 Unit MHz 1. Limitation for DDR2 usage only. There are no limitations to LP-DDR and LP-DDR2. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1746 54.5 Main Oscillator Characteristics Table 54-11. Main Oscillator Characteristics Symbol Freq Parameter Operating Frequency Conditions Min Load Capacitance Max FREQ = 00, 01(2) 8 FREQ = 10 20 FREQ = 11 44 48 12.5 17.5 FREQ = 00, 01 CLOAD(1) Typ FREQ = 10 4 FREQ = 11 4 Unit 16 — — 24 8 MHz pF 6 CLEXT(1) External Load Capacitance — — — CPARA Parasitic Load Capacitance — 0.6 0.7 0.8 pF — Duty Cycle — 40 — 60 % tST Startup Time — — — 2 ms IDDST Standby Current Consumption Standby mode — — 0.1 µA FREQ = 00, 01 PON Drive Level 150 FREQ = 10 — — FREQ = 11 IDD ON Note: Current Dissipation pF 300 µW 400 @ 12 MHz — 0.5 1 mA 1. The external capacitors value can be determined by using the following formula: CLEXT = (2*CLOAD) - CBOARD - CROUTING - CPACKAGE - (CPARA*2), where CLEXT: external capacitor value which must be soldered from XIN to GND and XOUT to GND, CLOAD: crystal targeted load. Please refer to CLOAD parameter in the electrical specification, CBOARD: external calculated (or measured) parasitic value due to board, CROUTING: parasitic capacitance due to internal chip routing, typically 1.5 pF, CPACKAGE: parasitic capacitance due to package and bonding, typically 0.75 pF, CPARA: internal parasitic load due to internal structure. 2. FREQ field defines the input frequency for the UTMI and the Main Oscillator. It is defined in the UTMI Clock Trimming Register (SFR_UTMICKTRIM) located in the SFR section. Take care to select the correct FREQ value—this has a direct influence on the USB frequency. Figure 54-2. Main Oscillator Schematics XIN XOUT GNDPLL 1K CCRYSTAL CLEXT CLEXT SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1747 54.5.1 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range TA = -40°C to +105°C and worst case of power supply, unless otherwise specified. Table 54-12. Crystal Characteristics Symbol Parameter ESR Equivalent Series Resistance Conditions Min Typ Max — — 150 @16 MHz, FREQ = 00, 01 80 @24 MHz, FREQ = 10 @48 MHz, FREQ = 11 FREQ = 00, 01 Motional Capacitance 5 FREQ = 10 with ESRmax = 150 Ω 1.3 FREQ = 11 with ESRmax = 100 Ω 2 9 — 2 Shunt Capacitance 7 FREQ = 10 with ESRmax = 150 Ω — — 1 FREQ = 11 with ESRmax = 100 Ω Note: fF 3.2 FREQ = 00, 01 CS Ω 100 (1) CM Unit pF 1.3 1. FREQ field defines the input frequency for the UTMI and the Main Oscillator. It is defined in UTMI Clock Trimming Register, located in SFR section. Take care to select the correct FREQ value, this has a direct influence on USB frequency. 54.5.2 XIN Clock Characteristics Table 54-13. XIN Clock Electrical Characteristics Symbol Parameter 1/(tCPXIN) XIN Clock Frequency tCPXIN Min Max Unit — — 50 MHz XIN Clock Period — 20 — ns tCHXIN XIN Clock High Half-period — 0.4 x tCPXIN 0.6 x tCPXIN ns tCLXIN XIN Clock Low Half-period — 0.4 x tCPXIN 0.6 x tCPXIN ns CIN XIN Input Capacitance (1) — 25 pF XIN Pulldown Resistor (1) — 500 kΩ XIN Voltage (1) VDDOSC VDDOSC V RIN VIN Note: Conditions 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1) in the CKGR_MOR. See “PMC Clock Generator Main Oscillator Register” in the PMC section. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1748 54.6 12 MHz RC Oscillator Characteristics Table 54-14. 12 MHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit F0 Nominal Frequency — 11.4 12 12.6 MHz Duty Duty Cycle — 45 50 55 % IDD ON Power Consumption Oscillation — — 220 — µA tON Startup time — — — 10 µs IDD STDBY Standby consumption — — — 22 µA Min Typ Max Unit 54.7 32 kHz Oscillator Characteristics Table 54-15. 32 kHz Oscillator Characteristics Symbol Parameter Conditions 1/(tCP32KHz) Crystal Oscillator Frequency — — 32 768 — kHz CCRYSTAL32 Load Capacitance Crystal @ 32.768 kHz 6 — 12.5 pF CLEXT32(2) CCRYSTAL32 = 6 pF — 6 — pF External Load Capacitance CCRYSTAL32 = 12.5 pF — 19 — pF — 40 50 60 % CCRYSTAL32 = 6 pF — — 400 ms CCRYSTAL32 = 12.5 pF — — 900 ms CCRYSTAL32 = 6 pF — — 600 ms CCRYSTAL32 = 12.5 pF — — 1200 ms — — 0.2 µW Duty Cycle RS = 50 kΩ(1) tST Startup Time RS = 100 kΩ(1) PON Drive Level — Notes: 1. RS is the equivalent series resistance. 2. CLEXT32 is determined by taking into account internal, parasitic and package load capacitance. Figure 54-3. 32 kHz Oscillator Schematics XIN32 XOUT32 GNDBU CCRYSTAL32 CLEXT32 CLEXT32 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1749 54.7.1 32 kHz Crystal Characteristics Table 54-16. 32 kHz Crystal Characteristics Symbol Parameter Conditions Min Typ Max Unit ESR Equivalent Series Resistor Rs Crystal @ 32768 kHz — 50 100 kΩ CM Motional Capacitance Crystal @ 32768 kHz 0.6 — 3 fF CS Shunt Capacitance Crystal @ 32768 kHz 0.6 — 2 pF — 0.3 0.65 µA RS = 50 kΩ(1) CCRYSTAL32 = 12.5pF — 0.45 0.7 µA RS = 100 kΩ(1) CCRYSTAL32 = 6 pF — 0.45 0.75 µA — 0.45 0.65 µA — 5 10 nA (1) RS = 50 kΩ IDD ON Current dissipation CCRYSTAL32 = 6 pF (1) RS = 100 kΩ IDD STDBY Standby consumption CCRYSTAL32 = 12.5 pF — 54.7.2 XIN32 Clock Characteristics Table 54-17. XIN32 Clock Characteristics Symbol Parameter 1/(tCPXIN32) XIN32 Clock Frequency tCPXIN32 Min Max Unit — — 44 kHz XIN32 Clock Period — 22 — µs tCHXIN32 XIN32 Clock High Half-period — 11 — µs tCLXIN32 XIN32 Clock Low Half-period — 11 — µs tCLCH32 XIN32 Clock Rise time — 400 — ns tCLCL32 XIN32 Clock Fall time — 400 — ns XIN32 Input Capacitance (1) — 6 pF XIN32 Pulldown Resistor (1) — 4 MΩ VIN32 XIN32 Voltage (1) VDDBU VDDBU V VINIL32 XIN32 Input Low Level Voltage (1) -0.3 0.3 x VVDDBU V XIN32 Input High Level Voltage (1) 0.7 x VVDDBU VVDDBU + 0.3 V CIN32 RIN32 VINIH32 Conditions Notes: 1. These characteristics apply only when the 32768 kHz oscillator is in bypass mode (i.e., when RCEN = 0, OSC32EN = 0, OSCSEL = 1 and OSC32BYP = 1) in the SCKC_CR. See section “Slow Clock Controller Configuration Register” in the Slow Clock Controller (SCKC) section of this datasheet. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1750 54.8 32 kHz RC Oscillator Characteristics Table 54-18. 32 kHz RC Oscillator Characteristics Symbol Parameter Conditions Min Typ Max Unit 1/(tCPRCz) Crystal Oscillator Frequency — 30.4 32 33.6 kHz — Duty Cycle — 45 — 55 % tST Startup Time — — 290 500 µs IDD ON Power Consumption Oscillation After startup time — 1.1 2.1 µA IDD STDBY Standby consumption — — — 0.2 µA Conditions Min Typ Max Unit VDDPLLA[1.08V, 1.32V] ICPLLA = 0 OUTA = 0 400 — 800 VDDPLLA[1.2V, 1.32V] ICPLLA = 0 OUTA = 0 400 — 1000 — 8 — 50 MHz Active mode @ 800 MHz — 10 14 mA Standby mode — 1 200 µA — — 25 100 µs Min Typ Max Unit 54.9 PLL Characteristics Table 54-19. PLLA Characteristics Symbol fOUT Parameter Output Frequency fIN Input Frequency IPLL Current Consumption t Startup Time MHz 54.9.1 UTMI PLL Characteristics Table 54-20. Phase Lock Loop Characteristics Symbol Parameter Conditions fIN Input Frequency — — 12 — MHz fOUT Output Frequency — — 480 — MHz IPLL Current Consumption Active mode — 5 8 mA Standby mode — — 1.5 µA t Startup Time — — — 50 µs SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1751 54.10 USB HS Characteristics 54.10.1 Electrical Characteristics Table 54-21. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit RPUI Bus Pull-up Resistor on Upstream Port (idle bus) In LS or FS Mode — 1.5 — kΩ RPUA Bus Pull-up Resistor on Upstream Port (upstream port receiving) In LS or FS Mode — 15 — kΩ tBIAS Bias settling time — — — 20 µs tOSC Oscillator settling time With Crystal 12 MHz — — 2 ms tSETTLING Settling time fIN = 12 MHz — 0.3 0.5 ms Min Typ Max Unit Settling time 54.10.2 Static Power Consumption Table 54-22. Static Power Consumption Symbol Parameter Conditions IBIAS Bias current consumption on VBG — — — 1 µA HS Transceiver and I/O current consumption — — — 8 µA LS / FS Transceiver and I/O current consumption No connection (1) — — 3 µA Core, PLL, and Oscillator current consumption — — — 2 µA Min Typ Max Unit IVDDUTMII IVDDUTMIC Note: 1. If cable is connected, add 200 µA (Typical) due to pull-up/pull-down current consumption. 54.10.3 Dynamic Power Consumption Table 54-23. Dynamic Power Consumption Symbol Parameter Conditions IBIAS Bias current consumption on VBG — — 0.7 0.8 mA HS Transceiver current consumption HS transmission — 47 60 mA HS Transceiver current consumption HS reception — 18 27 mA LS / FS Transceiver current consumption FS transmission 0m cable(1) — 4 6 mA LS / FS Transceiver current consumption FS transmission 5m cable(1) — 26 30 mA LS / FS Transceiver current consumption FS reception(1) — 3 4.5 mA PLL, Core and Oscillator current consumption — — 5.5 9 mA IVDDUTMII IVDDUTMIC Note: 1. Including 1 mA due to pull-up/pull-down current consumption. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1752 54.11 12-Bit ADC Characteristics Table 54-24. Analog Power Supply Characteristics Symbol VVDDANA IVDDANA Note: Parameter Conditions Min Typ Max Unit ADC Analog Supply 12-bit 2.4 3.0 3.6 V Max. Voltage Ripple RMS value, 10 kHz to 20 MHz — — 20 mV Sleep Mode — 4 8 µA Fast Wake Up Mode — 2.2 3.4 mA Normal Mode (IBCTL= 00) — 3.3 4.8 mA Normal Mode (IBCTL= 01) — 4.4 6.4 mA Current Consumption Use IBCTL = 00 for Sampling Frequency below 500 kHz and IBCTL = 01 between 500 kHz and 1 MHz. Table 54-25. Channel Conversion Time and ADC Clock Symbol Parameter Conditions Min Typ Max Unit fADC ADC Clock Frequency — 1 — 20 MHz tCP_ADC ADC Clock Period — 50 — 1000 ns fS Sampling Frequency — — — 1 MHz 20 30 40 From OFF Mode to Normal Mode: - Voltage Reference OFF - Analog Circuitry OFF tSTART-UP ADC Startup time µs From Standby Mode to Normal Mode: - Voltage Reference ON - Analog Circuitry OFF tTRACKTIM Track and Hold Time See Section 54.11.1.1 “Track and Hold Time versus Source Output Impedance” for more details tCONV Conversion Time — tSETTLE Settling Time Settling time to change offset and gain 4 8 12 160 — — ns — 20 — tCP_ADC 200 — — ns Table 54-26. External Voltage Reference Input Parameter Conditions Min Typ Max Unit ADVREF Input Voltage Range, 12-bit 2.4V < VVDDIN < 3.6V 2.4 — VDDANA V ADVREF Current — — — 600 µA ADVREF Input DC impedance — 6 8 10 kΩ SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1753 54.11.1 Static performance characteristics In the tables that follow, the LSB is relative to the analog scale:   Single Ended (ex: ADVREF = 3.0 V)  Gain = 1, LSB = (3.0 V / 4096) = 732 µV  Gain = 2, LSB = (1.5 V / 4096) = 366 µV  Gain = 4, LSB = (750 mV / 4096) = 183 µV Differential (ex: ADVREF = 3.0 V)  Gain = 0.5, LSB = (6.0 V / 4096) = 1465 µV  Gain = 1, LSB = (3.0 V / 4096) = 732 µV  Gain = 4, LSB = (750 mV / 4096) = 366 µV Table 54-27. INL, DNL, 12-bit mode, VDDANA 2.4V to 3.6V supply voltage conditions Parameter Conditions Resolution — Integral Non-linearity (INL) Differential Non-linearity (DNL) All mode, all gain Typ = 3.0V supply, 27°C All mode, all gain Typ = 3.0V supply, 27°C Min Typ Max Unit — 12 — Bit -4 ±1 +4 LSB -2 ±0.5 +2 LSB Unit Table 54-28. Gain Error, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions Parameter Conditions Min Typ Max Gain Error, Differential mode, uncalibrated Any gain and offset values -45 — +45 Gain = 0.5 -8 — +8 Gain = 1 -16 — +16 Gain = 2 -24 — +24 Any gain and offset values -45 — +45 Gain = 1 -8 — +8 Gain = 2 -16 — +16 Gain = 4 -24 — +24 Gain Error, Differential mode, after calibration LSB Gain Error, Single Ended, uncalibrated Gain Error, Single Ended, after calibration Table 54-29. Error offset with or without calibration, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions Parameter Offset Error Conditions Min Typ Max Single Ended, Gain = 1 / Differential mode Gain = 0.5 -8 — +8 Single Ended, Gain = 2 / Differential mode Gain = 1 -16 — +16 Single Ended, Gain = 4 / Differential mode Gain = 2 -32 — +32 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 Unit LSB 1754 Table 54-30. Dynamic Performance Characteristics in Single ended and 12 bits mode (1) Parameter Conditions Min Typ Max Unit Signal to Noise Ratio - SNR — 54 61 — dB Total Harmonic Distortion - THD — — -80 -68 dB Signal to Noise and Distortion - SINAD — 54 61 — dB Effective Number of Bits - ENOB (1) 8.7 9.8 — bits Note: 1. ADC Clock (fADC) = 20 MHz, fS = 1 MHz, fIN = 127 kHz, IBCTL = 01, FFT using 1024 points or more, frequency band = [1 kHz, 500 kHz] – Nyquist conditions fulfilled. Table 54-31. Dynamic Performance Characteristics in Differential and 12 bits mode(1) Parameter Conditions Min Typ Max Unit Signal to Noise Ratio - SNR — 58 63 — dB Total Harmonic Distortion - THD — — -80 -72 dB Signal to Noise and Distortion - SINAD — 58 63 — dB Effective Number of Bits - ENOB (1) 9.3 10.2 — bits Note: 1. ADC Clock (fADC) = 20 MHz, fS = 1 MHz, fIN = 127 kHz, IBCTL = 01, FFT using 1024 points or more, frequency band = [1 kHz, 500 kHz] – Nyquist conditions fulfilled. 54.11.1.1 Track and Hold Time versus Source Output Impedance The following figure gives a simplified acquisition path. Figure 54-4. Simplified Acquisition Path ADC Input Zsource Mux. Sample & Hold 12-bit ADC Core Ron Csample During the tracking phase the ADC needs to track the input signal during the tracking time shown below:  10-bit mode: tTRACK = 0.042 x ZSOURCE + 160  12-bit mode: tTRACK = 0.054 x ZSOURCE + 205 With tTRACK expressed in ns and ZSOURCE expressed in Ohms. Two cases must be considered: 1. The calculated tracking time (tTRACK) is lower than 15 tCP_ADC. Set TRANSFER = 1 and TRACTIM = 0. In this case, the allowed ZSOURCE can be computed versus the ADC frequency with the hypothesis of tTRACK = 15 × tCP_ADC: Where tCP_ADC = 1/fADC. See Table 54-32 on page 1756. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1755 Table 54-32. Source Impedance Values fADC = ADC clock (MHz) ZSOURCE (kΩ) for 12 bits ZSOURCE (kΩ) for 10 bits 20.00 10 14 16.00 14 19 10.67 22 30 8.00 31 41 6.40 40 52 5.33 48 63 4.57 57 74 4.00 66 85 3.56 74 97 3.20 83 108 2.91 92 119 2.67 100 130 2.46 109 141 2.29 118 152 2.13 126 164 2.00 135 175 1.00 274 353 2. The calculated tracking time (tTRACK) is higher than 15 tCP_ADC. Set TRANSFER = 1 and TRACTIM = 0. In this case, a timer will trigger the ADC in order to set the correct sampling rate according to the Track time. The maximum possible sampling frequency will be defined by tTRACK in nanoseconds, computed by the previous formula but with minus 15 × tCP_ADC and plus TRANSFER time.  10 bit mode: 1/fS = tTRACK - 15 × tCP_ADC + 5 tCP_ADC  12 bit mode: 1/fS = tTRACK - 15 × tCP_ADC + 5 tCP_ADC Note: CSAMPLE and RON are taken into account in the formulas. Table 54-33. Analog Inputs Parameter Min Typ Max Unit Input Voltage Range 0 — VADVREF V Input Leakage Current — — ±0.5 µA Input Capacitance — — 8 pF Note: Input Voltage range can be up to VDDANA without destruction or over-consumption. If VDDIO < VADVREF max input voltage is VDDIO. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1756 54.11.1.2 ADC Application Information For more information on data converter terminology, please refer to the application note: Data Converter Terminology, Atmel literature No. 6022 http://www.atmel.com/dyn/resources/prod_documents/doc6022.pdf 54.12 POR Characteristics General presentation of Power-On-Reset (POR) characteristics is provided in Figure 54-5. Figure 54-5. General Presentation of POR Behavior VDD Vth+ Dynamic Static VthVop Vnop NRST tres When a very slow (versus tRES) supply rising slope is applied on POR VDD pin, the reset time becomes negligible and the reset signal is released when VDD raises upper than Vth+. When a very fast (versus tRES) supply rising slope is applied on POR VDD pin, the voltage threshold becomes negligible and the reset signal is released after tRES time. It is the smallest possible reset time. 54.12.1 Core Power Supply POR Characteristics Table 54-34. Core Power Supply POR Characteristics Symbol Parameter Conditions Min Typ Max Unit Vth+ Threshold Voltage Rising Minimum Slope of +2.3 V/ms 0.85 1.02 1.08 V Vth- Threshold Voltage Falling — 0.8 0.96 1.06 V tRES Reset Time — 100 260 600 µs IDD Current Consumption After tRES — 250 500 nA 54.12.2 Backup Power Supply POR Characteristics Table 54-35. Backup Power Supply POR Characteristics Symbol Parameter Conditions Min Typ Max Unit Vth+ Threshold Voltage Rising Minimum Slope of +1.9 V/ms 1.50 1.54 1.60 V Vth- Threshold Voltage Falling — 1.39 1.46 1.53 V tRES Reset Time — 80 180 600 µs IDD Current Consumption After tRES — 300 500 nA SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1757 54.13 HSMC Timings 54.13.1 Timing conditions HSMC Timings are given in MAX corners. Timings assuming a capacitance load on data, control and address pads are given in Table 54-36. Table 54-36. Capacitance Load Corner Supply Max Min 3.3V 50 pF 50 pF 1.8V 30 pF 30 pF In tables that follow, tCPMCK is MCK period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1758 54.13.2 Timing extraction 54.13.2.1 Read Timings Table 54-37. SMC Read Signals - NRD Controlled (READ_MODE = 1) Parameter Symbol Min VDDIOM supply 1.8V Max 3.3V 1.8V 3.3V Unit NO HOLD SETTINGS (nrd hold = 0) SMC1 Data Setup before NRD High SMC2 Data Hold after NRD High 9.6 6.8 — — ns 0 0 — — ns HOLD SETTINGS (nrd hold ≠ 0) SMC3 Data Setup before NRD High SMC4 Data Hold after NRD High 9.4 6.6 — — ns 0 0 — — ns HOLD or NO HOLD SETTINGS (nrd hold ≠ 0, nrd hold =0) SMC5 NBS0/A0, NBS1, NBS2/A1, NBS3, A2 - A25 Valid before NRD High SMC6 NCS low before NRD High SMC7 NRD Pulse Width (nrd setup + nrd pulse)* tCPMCK + 2.4 (nrd setup + nrd pulse)* tCPMCK + 2.1 — — ns (nrd setup + nrd pulse - ncs rd setup) * tCPMCK + 2 (nrd setup + nrd pulse - ncs rd setup) * tCPMCK + 1.9 — — ns nrd pulse * tCPMCK + 1.8 nrd pulse * tCPMCK +1.2 — — ns Table 54-38. SMC Read Signals - NCS Controlled (READ_MODE = 0) Parameter Symbol Min VDDIOM supply 1.8V Max 3.3V 1.8V 3.3V Unit NO HOLD SETTINGS (ncs rd hold = 0) SMC8 Data Setup before NCS High SMC9 Data Hold after NCS High 18.5 16.2 — — ns 0 0 — — ns HOLD SETTINGS (ncs rd hold ≠ 0) SMC10 Data Setup before NCS High 17 14.7 — — ns SMC11 Data Hold after NCS High 0 0 — — ns HOLD or NO HOLD SETTINGS (ncs rd hold ≠ 0, ncs rd hold = 0) NBS0/A0, NBS1, NBS2/A1, NBS3, A2 - A25 valid before NCS High (ncs rd setup + ncs rd pulse)* tCPMCK + 19.1 (ncs rd setup + ncs rd pulse)* tCPMCK + 18.8 — — ns SMC13 NRD low before NCS High (ncs rd setup + ncs rd pulse nrd setup)* tCPMCK + 16.8 (ncs rd setup + ncs rd pulse - nrd setup)* tCPMCK +16.1 — — ns SMC14 NCS Pulse Width ncs rd pulse length * tCPMCK +2 ncs rd pulse length * tCPMCK + 1.5 — — ns SMC12 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1759 54.13.2.2 Write Timings Table 54-39. SMC Write Signals - NWE Controlled (WRITE_MODE = 1) Min Symbol Parameter 1.8V Supply Max 3.3V Supply 1.8V Supply 3.3V Supply Unit HOLD or NO HOLD SETTINGS (nwe hold ≠ 0, nwe hold = 0) SMC15 Data Out Valid before NWE High nwe pulse * tCPMCK + 2.4 nwe pulse * tCPMCK + 1.6 — — ns SMC16 NWE Pulse Width nwe pulse * tCPMCK + 1.9 nwe pulse * tCPMCK + 1.3 — — ns SMC17 NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25 valid before NWE low nwe setup * tCPMCK + 2.6 nwe pulse * tCPMCK + 2 — — ns (nwe setup ncs rd setup + nwe pulse) * tCPMCK + 2.2 (nwe setup ncs rd setup + nwe pulse) * tCPMCK + 1.9 — — ns SMC18 NCS low before NWE high HOLD SETTINGS (nwe hold ≠ 0) SMC19 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25 change SMC20 NWE High to NCS Inactive (1) nwe hold * tCPMCK + 2.3 nwe hold * tCPMCK +1.1 — — ns (nwe hold - ncs wr hold)* tCPMCK + 1.9 (nwe hold - ncs wr hold)* tCPMCK +1 — — ns — — ns NO HOLD SETTINGS (nwe hold = 0) SMC21 NWE High to Data OUT, NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25, NCS change(1) 2 1.6 Notes: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “NWE hold length”. Table 54-40. SMC Write NCS Controlled (WRITE_MODE = 0) Min Max Symbol Parameter 1.8V Supply 3.3V Supply 1.8V Supply 3.3V Supply Unit SMC22 Data Out Valid before NCS High ncs wr pulse * tCPMCK + 9.8 ncs wr pulse * tCPMCK + 9.1 — — ns SMC23 NCS Pulse Width ncs wr pulse * tCPMCK + 2 ncs wr pulse * tCPMCK + 1.5 — — ns SMC24 NBS0/A0 NBS1, NBS2/A1, NBS3, A2 - A25 valid before NCS low ncs wr setup * tCPMCK + 4.3 ncs wr setup * tCPMCK + 3.7 — — ns SMC25 NWE low before NCS high (ncs wr setup nwe setup + ncs pulse)* tCPMCK + 2.4 (ncs wr setup nwe setup + ncs pulse)* tCPMCK + 2.1 — — ns SMC26 NCS High to Data Out, NBS0/A0, NBS1, NBS2/A1, NBS3, A2 - A25, change ncs wr hold * tCPMCK + 2.6 ncs wr hold * tCPMCK + 1.7 — — ns SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1760 Table 54-40. SMC Write NCS Controlled (WRITE_MODE = 0) (Continued) Min Max Symbol Parameter 1.8V Supply 3.3V Supply 1.8V Supply 3.3V Supply Unit SMC27 NCS High to NWE Inactive (ncs wr hold nwe hold)* tCPMCK + 5.5 (ncs wr hold nwe hold)* tCPMCK + 5.6 — — ns Figure 54-6. SMC Timings - NCS Controlled Read and Write SMC12 SMC12 SMC26 SMC24 A0/A1/NBS[3:0]/A2-A25 SMC13 SMC13 NRD SMC14 NCS SMC14 SMC9 SMC8 SMC10 SMC23 SMC11 SMC22 SMC26 D0 - D15 SMC27 SMC25 NWE NCS Controlled READ with NO HOLD NCS Controlled READ with HOLD NCS Controlled WRITE Figure 54-7. SMC Timings - NRD Controlled Read and NWE Controlled Write SMC21 SMC17 SMC5 SMC5 SMC17 SMC19 A0/A1/NBS[3:0]/A2-A25 SMC6 SMC21 SMC6 SMC18 SMC18 SMC20 NCS NRD SMC7 SMC7 SMC1 SMC2 SMC15 SMC21 SMC3 SMC4 SMC15 SMC19 D0 - D31 NWE SMC16 NRD Controlled READ with NO HOLD NWE Controlled WRITE with NO HOLD SMC16 NRD Controlled READ with HOLD NWE Controlled WRITE with HOLD SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1761 54.13.2.3 FPGA Timings SMC and PCK2 can be used to interface a FPGA. PCK2 is to be programmed to output MCK. READ_MODE and WRITE_MODE are to be configured to 0. Figure 54-8. FPGA Timings PCK2 FPGA1 FPGA2 FPGA3 FPGA4 ADD, NCS, NDR, NWE DATA Output FPGA5 FPGA6 DATA Input Shaded areas are not valid Table 54-41. FPGA Timings vs PCK2 VDDIOM Supply 1.65–1.95V 3.0–3.6V 3.0–3.6V 1.65–1.95V 3.0–3.6V 3.0–3.6V VDDCORE Supply 1.08–1.32V 1.08–1.32V 1.2–1.32V 1.08–1.32V 1.08–1.32V 1.2–1.32V Symbol Parameter Min Max Unit FPGA1 Address, NCS, NRD, NWE Setup before PCK2 falling edge 1.78 2.07 1.78 — — — ns FPGA2 Address, NCS, NRD, NWE Hold after PCK2 falling edge 0.29 0.35 1.22 — — — ns FPGA3 Data Out Setup before PCK2 falling edge 1.46 1.77 1.59 — — — ns FPGA4 Data Out Hold after PCK2 falling edge 0 0.27 1.10 — — — ns FPGA5 Data In Setup before PCK2 falling edge — — — 14.15 12.08 10.39 ns FPGA6 Data In Hold after PCK2 falling edge — — — 0 0 0 ns SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1762 54.14 SPI Timings 54.14.1 Timing Conditions Timings assuming a capacitance load on MISO, SPCK and MOSI are given in Table 54-42. Table 54-42. Capacitance Load for MISO, SPCK and MOSI (Product Dependent) Corner Supply Max Min 3.3V 40 pF 40 pF 1.8V 20 pF 40 pF These values may be product dependent and should be confirmed by the specification. 54.14.2 Timing Extraction Figure 54-9. SPI Master mode 1 and 2 SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 54-10.SPI Master mode 0 and 3 SPCK SPI3 SPI4 MISO SPI5 MOSI SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1763 Figure 54-11.SPI Slave Mode 0 and 3 NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI Figure 54-12.SPI Slave Mode 1 and 2 NPCS0 SPI13 SPI12 SPCK SPI9 MISO SPI10 SPI11 MOSI Figure 54-13.SPI Slave Mode - NPCS Timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI9 SPI13 SPCK (CPOL = 1) SPI16 MISO SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1764 Table 54-43. SPI Timings with 3v3 peripheral supply Symbol Parameter Conditions Min Max Unit Master Mode SPI0 MISO Setup time before SPCK rises — 8.7 — ns SPI1 MISO Hold time after SPCK rises — 5.9 — ns SPI2 SPCK rising to MOSI — 0.8(1) 3.7(1) ns SPI3 MISO Setup time before SPCK falls — 8.7 — ns SPI4 MISO Hold time after SPCK falls — 5.8 — ns SPI5 SPCK falling to MOSI — 0.9(1) 3.8(1) ns Slave Mode SPI6 SPCK falling to MISO — 5.8(1) 9.4(1) ns SPI7 MOSI Setup time before SPCK rises — 2 — ns SPI8 MOSI Hold time after SPCK rises — 0.3 — ns SPI9 SPCK rising to MISO — 5.8(1) 9.4(1) ns SPI10 MOSI Setup time before SPCK falls — 2 — ns SPI11 MOSI Hold time after SPCK falls — 0.3 — ns SPI12 NPCS0 setup to SPCK rising — 3.5 — ns SPI13 NPCS0 hold after SPCK falling — 19.5 — ns SPI14 NPCS0 setup to SPCK falling — 1.9 — ns SPI15 NPCS0 hold after SPCK rising — 19.8 — ns SPI16 NPCS0 falling to MISO valid — — 8.8 ns Notes: 1. For output signals, Min and Max access time must be extracted. The Min access time is the time between the SPCK rising or falling edge and the signal change. The Max access timing is the time between the SPCK rising or falling edge and the signal stabilizes. Figure 54-13 illustrates Min and Max accesses for SPI2. The same applies for SPI5, SPI6, SPI9. Table 54-44. SPI Timings with 1v8 Peripheral Supply Symbol Parameter Conditions Min Max Unit Master Mode SPI0 MISO Setup time before SPCK rises — 10.9 — ns SPI1 MISO Hold time after SPCK rises — 0 — ns (1) SPI2 SPCK rising to MOSI — 0.8 SPI3 MISO Setup time before SPCK falls — SPI4 MISO Hold time after SPCK falls SPI5 SPCK falling to MOSI (1) 3.5 ns 10.4 — ns — 0 — ns — 1.2(1) 3.2(1) ns Slave Mode SPI6 SPCK falling to MISO — 3.2(1) 9.4(1) ns SPI7 MOSI Setup time before SPCK rises — 1.7 — ns SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1765 Table 54-44. SPI Timings with 1v8 Peripheral Supply (Continued) Symbol Parameter Conditions SPI8 MOSI Hold time after SPCK rises — SPI9 SPCK rising to MISO — SPI10 MOSI Setup time before SPCK falls — SPI11 MOSI Hold time after SPCK falls SPI12 Min Max Unit 1 — ns (1) 2.9 (1) 10.9 ns 1.7 — ns — 1 — ns NPCS0 setup to SPCK rising — 2.1 — ns SPI13 NPCS0 hold after SPCK falling — 19 — ns SPI14 NPCS0 setup to SPCK falling — 3.2 — ns SPI15 NPCS0 hold after SPCK rising — 19.6 — ns SPI16 NPCS0 falling to MISO valid — — 10.6 ns Figure 54-14.Min and Max access time for SPI output signal SPCK SPI0 SPI1 MISO SPI2max MOSI SPI2min SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1766 54.15 MPDDRC Timings 54.15.1 Board Design Constraints As SAMA5D3 series embeds impedance calibrated pads, there are no capacitive constraints on DDR signals. However, a board must be designed and equipped in order to respect DQS setup times, including propagation time and intrinsic delay in SDRAM device. In all cases, line length to memory device must not exceed 5 cm. 54.15.2 DDR2-SDRAM Table 54-45. System Clock Waveform Parameters Symbol Parameter Conditions VDDCORE[1.08V,1.32V] TA = 85°C tDDRCK DDRCK Cycle time Min Max Unit 7.5 8.0 ns 6.0 8.0 ns — 0.6 ns — 0.7 ns Min Max Unit 7.5 — ns — 7.3 ns Min Max Unit 7.5 — ns — 6.2 ns VDDCORE[1.2V,1.32V], VDDIODDR[1.75V,1.9V], TA = 85°C VDDCORE[1.08V,1.32V] TA = 85°C tSDQS DQS setup time VDDCORE[1.2V,1.32V], VDDIODDR[1.75V,1.9V], TA = 85°C 54.15.3 LPDDR1-SDRAM Table 54-46. System Clock Waveform Parameters Symbol Parameter tDDRCK DDRCK Cycle time tSDQS DQS setup time Conditions VDDCORE[1.08V,1.32V] TA = 85°C VDDCORE[1.08V,1.32V] TA = 85°C 54.15.4 LPDDR2-SDRAM Table 54-47. System Clock Waveform Parameters Symbol Parameter tDDRCK DDRCK Cycle time tSDQS DQS setup time Conditions VDDCORE[1.08V,1.32V] TA = 85°C VDDCORE[1.08V,1.32V] TA = 85°C SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1767 Figure 54-15.DQS Timings tDDRCK DDRCK tSDQS DQS 54.16 SSC Timings 54.16.1 Timing conditions Timings assuming a capacitance load are given in Table 54-48. Table 54-48. Capacitance Load Corner Supply Max Min 3.3V 30 pF 30 pF 1.8V 20 pF 20 pF These values may be product dependant and should be confirmed by the specification. 54.16.2 Timing Extraction Figure 54-16.SSC Transmitter, TK and TF in Output TK (CKI =0) TK (CKI =1) SSC0 TF/TD SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1768 Figure 54-17.SSC Transmitter, TK in Input and TF in Output TK (CKI =0) TK (CKI =1) SSC1 TF/TD Figure 54-18.SSC Transmitter, TK in Output and TF in Input TK (CKI=0) TK (CKI=1) SSC2 SSC3 TF SSC4 TD Figure 54-19.SSC Transmitter, TK and TF in Input TK (CKI=1) TK (CKI=0) SSC5 SSC6 TF SSC7 TD SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1769 Figure 54-20.SSC Receiver RK and RF in Input RK (CKI=0) RK (CKI=1) SSC8 SSC9 RF/RD Figure 54-21.SSC Receiver, RK in Input and RF in Output RK (CKI=1) RK (CKI=0) SSC8 SSC9 RD SSC10 RF Figure 54-22.SSC Receiver, RK and RF in Output RK (CKI=1) RK (CKI=0) SSC11 SSC12 RD SSC13 RF Figure 54-23.SSC Receiver, RK in Output and RF in Input RK (CKI=0) RK (CKI=1) SSC11 SSC12 RF/RD SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1770 Table 54-49. SSC Timings with 3.3V Peripheral supply Symbol Parameter Conditions Min Max Unit Transmitter SSC0 TK edge to TF/TD (TK output, TF output) — 1.2(2) 3.8 (2) ns SSC1 TK edge to TF/TD (TK input, TF output) — 2.3 (2) 10.6 (2) ns SSC2 TF setup time before TK edge (TK output) — 7.7 — ns SSC3 TF hold time after TK edge (TK output) — 7.3 SSC4(1) TK edge to TF/TD (TK output, TF input) — SSC5 TF setup time before TK edge (TK input) — 0 SSC6 TF hold time after TK edge (TK input) — tCPMCK SSC7(1) TK edge to TF/TD (TK input, TF input) — 1.2 (+2*tCPMCK) 2.4 (+3*tCPMCK) — (1)(2) 2.1(+2*tCPMCK) ns (1)(2) — ns — (1)(2) 8.8 (+3*tCPMCK) ns ns (1)(2) ns Receiver SSC8 RF/RD setup time before RK edge (RK input) — 0 — ns SSC9 RF/RD hold time after RK edge (RK input) — tCPMCK — ns 2.5 (2) 8.8 (2) SSC10 RK edge to RF (RK input) — ns SSC11 RF/RD setup time before RK edge (RK output) — 7.6 - tCPMCK — ns SSC12 RF/RD hold time after RK edge (RK output) — tCPMCK - 2.2 — ns SSC13 RK edge to RF (RK output) — 0.7(2) 2.2(2) ns Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7 (Receive Start Selection), two Periods of the MCK must be added to timings. 2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization. Figure 54-24 illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7, SSC10 and SSC13. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1771 Table 54-50. SSC Timing with 1V8 Peripheral supply Symbol Parameter Conditions Min Max Unit Transmitter SSC0 TK edge to TF/TD (TK output, TF output) — 1.2(2) 3.8 (2) ns SSC1 TK edge to TF/TD (TK input, TF output) — 2.3 (2) 10.6 (2) ns SSC2 TF setup time before TK edge (TK output) — 7.7 — ns SSC3 TF hold time after TK edge (TK output) — 7.3 SSC4(1) TK edge to TF/TD (TK output, TF input) — SSC5 TF setup time before TK edge (TK input) — 0 SSC6 TF hold time after TK edge (TK input) — tCPMCK SSC7(1) TK edge to TF/TD (TK input, TF input) — 1.2 (+2*tCPMCK) 2.4 (+3*tCPMCK) — (1)(2) 2.1(+2*tCPMCK) ns (1)(2) — ns — (1)(2) 8.8 (+3*tCPMCK) ns ns (1)(2) ns Receiver SSC8 RF/RD setup time before RK edge (RK input) — 0 — ns SSC9 RF/RD hold time after RK edge (RK input) — tCPMCK — ns 2.5 (2) 8.8 (2) SSC10 RK edge to RF (RK input) — ns SSC11 RF/RD setup time before RK edge (RK output) — 7.6 - tCPMCK — ns SSC12 RF/RD hold time after RK edge (RK output) — tCPMCK - 2.2 — ns SSC13 RK edge to RF (RK output) — 0.7(2) 2.2(2) ns Figure 54-24.Min and Max Access Time of Output Signals TK (CKI =1) TK (CKI =0) SSC0min SSC0max TF/TD SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1772 54.17 ISI Timings 54.17.1 Timing conditions Timings assuming capacitance loads are given in Table 54-51. Table 54-51. Capacitance Load Corner Supply Max Min 3.3V 30 pF 30 pF 1.8V 20 pF 20 pF These values may be product dependant and should be confirmed by the specification. 54.17.2 Timing Extraction Figure 54-25.ISI Timing Diagram PIXCLK 3 DATA[7:0] VSYNC HSYNC Valid Data 1 Valid Data Valid Data 2 Table 54-52. ISI Timings with Peripheral Supply 3.3V Symbol Parameter Min Max Unit ISI1 DATA/VSYNC/HSYNC setup time 3.1 — ns ISI2 DATA/VSYNC/HSYNC hold time 1 — ns ISI3 PIXCLK frequency — 80 MHz Table 54-53. ISI Timings with Peripheral Supply 1.8V Symbol Parameter Min Max Unit ISI1 DATA/VSYNC/HSYNC setup time 3.4 — ns ISI2 DATA/VSYNC/HSYNC hold time 1.2 — ns ISI3 PIXCLK frequency — 80 MHz SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1773 54.18 MCI Timings The High Speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification, and CE-ATA V1.1. 54.19 EMAC/GMAC Timings 54.19.1 Timing conditions Timings assuming a capacitance load on data and clock are given in Table 54-54. Table 54-54. Capacitance Load on Data, Clock Pads Corner Supply Max Min 3.3V 20 pF 0 pF 1.8V 20 pF 0 pF These values may be product dependant and should be confirmed by the specification. 54.19.2 Timing constraints To satisfy the timings of standard given in Table 54-55 and Table 54-56, the Ethernet controller (EMAC) must be constrained in MAX corners. Table 54-55. EMAC Signals Relative to EMDC Symbol Parameter Min Max Unit EMAC1 Setup for EMDIO from EMDC rising 10 — ns EMAC2 Hold for EMDIO from EMDC rising 10 — ns EMDIO toggling from EMDC rising (1) EMAC3 0 (1) 300 ns Notes: 1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC rising edge and the signal change. The Max access timing is the time between the EDMC rising edge and the signal stabilizes. Figure 54-26 illustrates Min and Max accesses for EMAC3. Figure 54-26.Min and Max access time of EMAC output signals EMDC EMAC1 EMAC2 EMAC3 max EMDIO EMAC4 EMAC5 EMAC3 min SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1774 54.19.2.1 MII Mode Table 54-56. EMAC MII Specific Signals Symbol Parameter Min Max Unit EMAC4 Setup for ECOL from ETXCK rising 10 — ns EMAC5 Hold for ECOL from ETXCK rising 10 — ns EMAC6 Setup for ECRS from ETXCK rising 10 — ns EMAC7 Hold for ECRS from ETXCK rising 10 — ns EMAC8 ETXER toggling from ETXCK rising (1) 10 (1) (1) ns (1) 25 EMAC9 ETXEN toggling from ETXCK rising 10 25 ns EMAC10 ETX toggling from ETXCK rising 10(1) 25(1) ns EMAC11 Setup for ERX from ERXCK 10 — ns EMAC12 Hold for ERX from ERXCK 10 — ns EMAC13 Setup for ERXER from ERXCK 10 — ns EMAC14 Hold for ERXER from ERXCK 10 — ns EMAC15 Setup for ERXDV from ERXCK 10 — ns EMAC16 Hold for ERXDV from ERXCK 10 — ns Notes: 1. See Note (1) of Table 54-55. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1775 Figure 54-27.EMAC MII Mode EMDC EMAC1 EMAC3 EMAC2 EMDIO EMAC4 EMAC5 EMAC6 EMAC7 ECOL ECRS ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0] ERXCK EMAC11 EMAC12 ERX[3:0] EMAC13 EMAC14 EMAC15 EMAC16 ERXER ERXDV Table 54-57. RMII Mode Symbol Parameter Min Max (1) (1) Unit ns EMAC21 ETXEN toggling from EREFCK rising 2 16 EMAC22 ETX toggling from EREFCK rising 2(1) 16(1) ns EMAC23 Setup for ERX from EREFCK rising 4 — ns EMAC24 Hold for ERX from EREFCK rising 2 — ns EMAC25 Setup for ERXER from EREFCK rising 4 — ns EMAC26 Hold for ERXER from EREFCK rising 2 — ns EMAC27 Setup for ECRSDV from EREFCK rising 4 — ns EMAC28 Hold for ECRSDV from EREFCK rising 2 — ns SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1776 Notes: 1. See Note (1) of Table 54-55. Figure 54-28.EMAC RMII Timings EREFCK EMAC21 ETXEN EMAC22 ETX[1:0] EMAC23 EMAC24 ERX[1:0] EMAC25 EMAC26 EMAC27 EMAC28 ERXER ECRSDV SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1777 54.20 UART in SPI Mode Timings 54.20.1 Timing conditions Timings assuming a capacitance load on MISO, SPCK and MOSI are given in Table 54-58. Table 54-58. Capacitance Load for MISO, SPCK and MOSI (product dependent) Corner Supply Max Min 3.3V 40 pF 40 pF 1.8V 20 pF 40 pF These values may be product dependant and should be confirmed by the specification. 54.20.2 Timing Extraction Figure 54-29.UART SPI Master mode NPCSx SPI5 SPI3 CPOL=1 SPI0 SPCK=0 CPOL=0 SPI4 MISO SPI4 SPI1 SPI2 LSB MSB MOSI Figure 54-30.UART SPI Slave mode NPCS0 SPI13 SPI12 SPCK SPI6 MISO SPI7 SPI8 MOSI SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1778 Figure 54-31.SPI Slave mode - NPCS timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI13 SPI9 SPCK (CPOL = 1) SPI16 MISO Table 54-59. UART SPI Timings 3.3V Peripheral Supply Symbol Parameter Conditions Min Max Unit Master Mode SPI0 SPCK Period — MCK/6 — ns SPI1 Input Data Setup Time — 2.4 — ns SPI2 Input Data Hold Time — 0.4 — ns SPI3 Chip Select Active to Serial Clock — — 1.1 ns SPI4 Output Data Setup Time — — 6.5 ns SPI5 Serial Clock to Chip Select Inactive — — 0.6 ns Slave Mode SPI6 SPCK falling to MISO — 2.2(1) 8.7(1) ns SPI7 MOSI Setup time before SPCK rises — — — ns SPI8 MOSI Hold time after SPCK rises — 0.1 — ns (1) 8 ns (1) SPI9 SPCK rising to MISO — 5.6 SPI10 MOSI Setup time before SPCK falls — 2 — ns SPI11 MOSI Hold time after SPCK falls — 0.5 — ns SPI12 NPCS0 setup to SPCK rising — 1 — ns SPI13 NPCS0 hold after SPCK falling — 0.9 — ns SPI14 NPCS0 setup to SPCK falling — 0.8 — ns SPI15 NPCS0 hold after SPCK rising — 0.4 — ns SPI16 NPCS0 falling to MISO valid — — 7.6 ns Notes: 1. For output signals, Min and Max access time must be extracted. The Min access time is the time between the SPCK rising or falling edge and the signal change. The Max access timing is the time between the SPCK rising or falling edge and the signal stabilizes. Figure 54-13 illustrates Min and Max accesses for SPI2. The same applies for SPI5, SPI6, SPI9. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1779 54.21 Two-wire Interface Characteristics Table 54-60 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols, please refer to Figure 54-32. Table 54-60. Two-wire Serial Bus Requirements Symbol Parameter Conditions Min Max Unit VIL Input Low-voltage — -0.3 0.3 VVDDIO V VIH Input High-voltage — 0.7xVVDDIO VCC + 0.3 V VHYS Hysteresis of Schmitt Trigger Inputs — 0.150 – V VOL Output Low-voltage 3 mA sink current — 0.4 V 0.1Cb(1)(2) 300 ns 20 + 0.1Cb(1)(2) 250 ns tR Rise Time for both TWD and TWCK tOF Output Fall Time from VIHmin to VILmax Ci(1) Capacitance for each I/O Pin — — 10 pF fTWCK TWCK Clock Frequency — 0 400 kHz Rp tLOW Value of Pull-up Resistor Low Period of the TWCK Clock tHIGH High Period of the TWCK Clock tHD;STA Hold Time (repeated) START Condition tSU;STA Set-up Time for a Repeated START Condition tHD;DAT tSU;DAT tSU;STO tHD;STA Data Hold Time 20 + 10 pF < Cb < 400 pF Figure 54-32 fTWCK ≤ 100 kHz V VDDIO – 0,4V ------------------------------------3mA 1000ns ----------------Cb Ω fTWCK > 100 kHz V VDDIO – 0,4V ------------------------------------3mA 300ns -------------Cb Ω fTWCK ≤ 100 kHz (3) — µs fTWCK > 100 kHz (3) — µs fTWCK ≤ 100 kHz (4) — µs fTWCK > 100 kHz (4) — µs fTWCK ≤ 100 kHz tHIGH — µs fTWCK > 100 kHz tHIGH — µs fTWCK ≤ 100 kHz tHIGH — µs fTWCK > 100 kHz tHIGH — fTWCK ≤ 100 kHz 0 µs 3 x tCP_MCK (5) µs 3 x tCP_MCK (5) µs fTWCK > 100 kHz 0 fTWCK ≤ 100 kHz tLOW - 3 x tCP_MCK(5) — ns fTWCK > 100 kHz tLOW - 3 x tCP_MCK(5) — ns fTWCK ≤ 100 kHz tHIGH — µs fTWCK > 100 kHz tHIGH — µs Bus free time between a STOP and START fTWCK ≤ 100 kHz tHIGH — µs condition fTWCK > 100 kHz tHIGH — µs Data Setup Time Setup Time for STOP Condition Notes: 1. Required only for fTWCK > 100 kHz. 2. Cb = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF 3. The TWCK low period is defined as follows: t low = ( ( CLDIV × 2 CKDIV 4. The TWCK high period is defined as follows: t high = ( ( CHDIV × 2 ) + 4 ) × t MCK CKDIV ) + 4 ) × t MCK 5. tCP_MCK = MCK bus period. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1780 Figure 54-32.Two-wire Serial Bus Timing tof tHIGH tLOW tr tLOW SCL tSU;STA SDA tHD;STA tHD;DAT tSU;DAT tSU;STO tBUF SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1781 55. Mechanical Characteristics 55.1 324-ball LFBGA Mechanical Characteristics Figure 55-1. 324-ball LFBGA Package Drawing TITLE Low Profile Fine Pitch Ball Grid Array 324 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1782 Table 55-1. 324-ball LFBGA Package Characteristics Moisture Sensitivity Level 3 Table 55-2. Device and 324-ball LFBGA Package Maximum Weight 400 mg Table 55-3. Package Reference JEDEC Drawing Reference MO-275-KAAE-1 JESD97 Classification e8 Table 55-4. Package Information Ball Land 0.350 mm ± 0.05 Nominal Ball Diameter 0.30 mm Solder Mask Opening 0.275 mm ± 0.05 Solder Mask Definition SMD Solder SAC105 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1783 55.2 324-ball TFBGA Mechanical Characteristics Figure 55-2. 324-ball TFBGA Package Drawing SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1784 Table 55-5. 324-ball TFBGA Package Characteristics Moisture Sensitivity Level 3 Table 55-6. Device and 324-ball TFBGA Package Maximum Weight 280 mg Table 55-7. Package Reference JEDEC Drawing Reference — JESD97 Classification — Table 55-8. Package Information Ball Land 0.350 mm ± 0.05 Nominal Ball Diameter 0.30 mm Solder Mask Opening 0.275 mm ± 0.05 Solder Mask Definition SMD Solder LF35 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1785 55.3 Marking All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats: YYWW V XXXXXXXXX ARM where  “YY”: manufactory year  “WW”: manufactory week  “V”: revision  “XXXXXXXXX”: lot number SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1786 56. SAMA5D3 Ordering Information Table 56-1. SAMA5D3 Ordering Information Ordering Code Carrier Type ATSAMA5D31A-CU Packing Package Type Operating Temperature Range Tray LFBGA324 ATSAMA5D31A-CUR Tape and Reel ATSAMA5D31A-CFU Tray TFBGA324 ATSAMA5D31A-CFUR Tape and Reel ATSAMA5D33A-CU Tray ATSAMA5D33A-CUR Tape and Reel ATSAMA5D34A-CU Industrial -40°C to 85°C Tray ATSAMA5D34A-CUR Tape and Reel Green ATSAMA5D35A-CU Tray ATSAMA5D35A-CUR Tape and Reel LFBGA324 ATSAMA5D36A-CU ATSAMA5D36A-CUR ATSAMA5D35A-CN ATSAMA5D35A-CNR ATSAMA5D36A-CN ATSAMA5D36A-CNR Tray Tape and Reel Tray Tape and Reel Industrial Tray -40°C to 105°C Tape and Reel SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1787 57. SAMA5D3 Series Errata The present errata provides information on Rev. A parts. 57.1 Standard Boot Strategies 57.1.1 Boot ROM: Boot on MCI1 is Not Working Boot on MCI1 is not working. Problem Fix/Workaround Use a different boot media. 57.1.2 Boot ROM: NAND Flash Detection using ONFI Parameters does Not Work During Nandflash initialization, the ONFI parameter detection may not work correctly. This can lead to incorrect configuration of ECC settings and to reading wrong data from the Nandflash memory, thus making it impossible to boot from this memory. Problem Fix/Workaround When programming the bootable program in the Nandflash, always use the header method, with any Nandflash memory, ONFI compliant or not. 57.2 Static Memory Controller (HSMC) 57.2.1 HSMC: ECC Value after ERASE is Not Correct When ERASE page command is issued, the NAND Flash page resets to "ALL_ONE" pattern. The ECC value of ALL_ONE is a fixed but non-zero pattern leading to error detection after page erase. Problem Fix/Workaround None. 57.3 LCD Controller (LCDC) 57.3.1 LCDC: LCDC PWM Is Not Usable with DIV_1 When PWMPS field is set to DIV_1 value, the pwm ouput is stuck. It works fine for every other divider (DIV_2 up to DIV_64). Problem Fix/Workaround None. 57.4 PWM Controller (PWM) 57.4.1 PWM: Wrong Counter Event. A synchronous channel (but not channel 0) can generate a wrong counter event, which does not match the alignment configuration of the channel 0. The issue occurs if the alignment configuration of the channel is different from that of channel 0. Problem Fix/Workaround None. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1788 57.5 Gigabit Ethernet MAC (GMAC) 57.5.1 GMAC: TX Packet Buffer DMA Lockup when Reading Used Status In the following conditions:  Frame N-1 has completed the transmission on GMII and its post-transmit status has been passed from the MAC to DMA.  The descriptor write back for frame N-1 has been requested on AHB and is awaiting completion.  Frame N has completed the transmission on GMII and its post-transmit status has been passed from the MAC to DMA.  A “used” bit has been read from the buffer descriptor queue after the descriptors associated with frame N. This means a buffer descriptor with bit [31] set in word 1 of the descriptor pair.  Status associated with this used bit is passed from MAC to DMA on the exact AHB clock cycle that the writeback request for frame N-1 completes (either; BREADY high in the case of HREADY or high in the data phase in the case of AHB). When this precise sequence occurs, the AHB write back request for frame N never actually occurs, but the TX DMA state machine waits in the DMA_MANWR state, awaiting the AHB response for the write. This response never happens since the request was never sent. Problem Fix/Workaround 1. Avoid the issue by sending only one frame at a time. To send only a single frame at a time, each frame queued in the descriptor buffers must be followed by a buffer descriptor with the used bit set. GEM will send the frame and then halt and update status. Once frame status indicates that the frame has completed, then a new frame may be queued and transmit DMA restarted. 2. Avoid issue by changing used bit status to exhausted mid-frame status. For this workaround the buffer descriptors with used bit set, that mark the end of the queues are replaced with two zero length descriptors with particular bits set or clear. The effect is an exhausted mid-frame status instead of the usual used bit read status. This requires changes to SW for adding new frames to queues. For this discussion, assume that the last descriptor associated with the last valid frame queued is descriptor N, which is at address offset X from the queue base pointer. Currently the end of the queue is marked with descriptor N+1 with its used bit set as follows:  descriptor N: X+0x00: FC800000 X+0x04: 0000803C - Last frame queued  descriptor N+1: X+0x08: xxxxxxxx +0x0C: 8xxxxxxx - Used bit set (‘x’ is a don’t care value) For the workaround buffer descriptor N+1 and also N+2 should be replaced with the following:  descriptor N: X+0x00: FC800000 X+0x04: 0000803C - Last frame queued  descriptor N+1: X+0x08: 00000000 X+0x0C: 00000000  descriptor N+2: X+0x10: 00000000 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1789 X+0x14: 80008000 - last buffer and used bit set 57.5.2 GMAC: TX Packet Buffer DMA Writeback Status Overflow The issue occurs due to an overflow of the pipeline for the post-transmit status that is returned from the read side of the packet buffer memory back to the write side. Problem Fix/Workaround As there are four pipeline stages, having only 3 outstanding frames at any one time will avoid the issue. 57.6 Watchdog Timer (WDT) 57.6.1 WDT: WDRPROC = 1 leads to Unpredictible Behavior A Processor Reset not generated in conjunction with PERRST leads to Unpredictible Behavior. That is the reason why the Watchdog must not activate the processor reset only. WDRPROC bit must not be set in WDT_MR. Problem Fix/Workaround Use only WDRPROC = 0, leading to activate all resets on Watchdog fault if WDRRSTEN is set. SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1790 Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during document review and approval loop. Change Request Ref. Doc. Rev. 11121C Comments “Description” - minor editorial changes rfo - added SAMA5D36 device reference (“four SAMA5D3 devices” --> “five SAMA5D3 devices”) 8822 Section 1. “Features” Minor editorial and formatting changes rfo Bullet “Memories”: - replaced “Boot on NAND Flash” with “Boot on 8-bit NAND Flash” in first subbullet rfo - replaced “DDR2/LPDDR/LPDDR2” with “DDR2/LPDDR/LPDDR2 with datapath scrambling” in third subbullet rfo - replaced “Controller with SLC/MLC NAND Support” with “Controller with datapath scrambling and SLC/MLC NAND Support” in fourth subbullet rfo Bullet “System running up to 166 MHz”: deleted “Power-on Reset Cells” from first subbullet rfo Bullet “Peripherals: deleted subbullet “Write Protected Registers” rfo Inserted new bullet “Safety” (includes six subfeatures) rfo Bullet “Security”: deleted subbullet “SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512)” rfo Introduced 324-ball TFBGA package 9035 Table 1-1 “SAMA5D3 Device Differences”: changed table title (was “SAMA5D3 Devices”); reorganized table content; added SAMA5D36 device rfo 8822 Section 2. “Block Diagram”: added a note on peripheral bridges APB0/APB1 and updated Figure 2-1 “SAMA5D3 Block Diagram” 8956 Section 3. “Signal Description” Table 3-1 “Signal Description List”: rfo - removed empty columns “Frequency” and “Comments” - in DDR2/LPDDR Controller signals, replaced instances of “I/O/-PD” and “I/O- PD” with “I/O” - minor punctuation and formatting changes Section 4. “Package and Pinout” Editorial changes and formatting changes; inserted dashes in all empty table cells rfo Added Section 4.3 “324-ball TFBGA Package (12 x 12 x 1.2 mm, pitch 0.5 mm)” 9035 Added Section 4.4 “324-ball TFBGA Package Pinout” 9035 Table 4-1 “SAMA5D3 Pinout for 324-ball LFBGA Package”: inserted “Reference voltage” as “I/O Type” for pin C13 rfo Table 4-3 “SAMA5 I/O Types Description”: added column headers rfo Table 4-4 “SAMA5 I/O Type Assignation and Frequency”: changed column header “I/O Frequency (MHz)” to read “Max I/O Frequency (MHz)” rfo SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1791 Change Request Ref. Doc. Rev. 11121C Comments Section 5. “Power Considerations” Minor punctuation and formatting changes rfo Table 5-1 “SAMA5D3 Power supplies”: updated “Powers” information for VDDOSC 8818/rfo Section 6. “Memories” Minor editorial changes rfo Figure 6-1 “Memory Mapping”: corrected register name (was SCKCR; is SCKC_CR) rfo Section 7. “Real-time Event Management”: minor formatting changes rfo Section 8. “System Controller” Minor punctuation and formatting changes rfo Figure 8-1 “SAMA5D3 System Controller Block Diagram”: corrected register name (was SCKCR; is SCKC_CR) rfo Table 8-1 “Chip Identification of SAMA5D3 Devices”: added SAMA5D36 device 8822 Section 9. “Peripherals” Minor editorial and formatting changes rfo Section 9.3 “Peripheral Signal Multiplexing on I/O Lines”: updated content to reference additional multiplexing table for TFBGA324 rfo Section 10. “ARM Cortex-A5 Processor” Minor formatting and editorial changes throughout Amended Section 10.1.1 “Power Management” with bullet list of main levels of power management 8978 Table 10-4 “CP15 Registers”: for register No. 12, replaced empty row with row “Interrupts management / Read/Write” rfo Section 10.5.2 “Memory Management System”: deleted content “When the processor is put into dormant mode rfo ... in the Cortex-A5 Technical Reference Manual, DDI0433” from end of section Section 11. “SAMA5D3 Series Debug and Test” Removed RTCK references in Figure 11-1 “Debug and Test Block Diagram”, Table 11-1 “Debug and Test Pin rfo List”, and Section 11.6.3 “JTAG Signal Description” (removed the last paragraph) Section 12. “Standard Boot Strategies” Minor editorial and formatting changes rfo Updated note “JTAG access is disabled...” rfo Table 12-1 Values of the Boot Sequence Configuration Register: replaced column header “NAND Flash” with “8-bit NAND Flash” rfo Section 12.3.4.1 “NAND Flash Boot: NAND Flash Detection”: added note “Booting on 16-bit NAND Flash is not rfo possible; only 8-bit NAND Flash memories are supported” below bullet “Through the ONFI parameters...” and below “NAND Flash Specific Header Detection” bitmap Section 13. “Boot Sequence Controller (BSC)” Minor editorial and formatting changes throughout Section 13.4.1 “Boot Sequence Configuration Register”: 9006 - in description of field BOOT, replaced instance of BOOTKEY with WPKEY - changed name of field BOOTKEY to WPKEY and updated field description Section 14. “AXI Bus Matrix (AXIMX)”: No changes Section 15. “Bus Matrix (MATRIX)”: No changes SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1792 Change Request Ref. Doc. Rev. 11121C Comments Section 16. “Special Function Registers (SFR)” Minor punctuation changes Table 16-1 "Register Mapping": inserted reserved row for offsets 0x20–0x24 8539 Section 17. “Advanced Interrupt Controller (AIC)” Minor formatting changes throughout Section 17.8.4.4 “Fast Interrupt Handlers”: replaced 6-step sequence with 5-step sequence (step 3 updated) rfo Section 17.9.23 “AIC Write Protect Mode Register”: updated KEY field description rfo Section 18. “Watchdog Timer (WDT)” Section 18.1 “Description”: replaced “(slow clock at 32768 kHz)” with “(slow clock around 32 kHz)” rfo Section 18.2 “Embedded Characteristics”: added “Watchdog Clock is independent from Processor Clock” rfo Section 18.4 “Functional Description”: replaced “(with a typical Slow Clock of 32768 kHz)” with “(with a typical Slow Clock of 32.768 kHz)” rfo Section 18.5.1 “Watchdog Timer Control Register”: updated KEY field description 8844 Section 18.5.2 “Watchdog Timer Mode Register”: rfo - added note “The first write access prevents any further modification of the value of this register, read accesses remain possible” - added note “The WDD and WDV values must not be modified within a period of time of 3 slow clock periods following a restart of the watchdog performed by means of a write access in the WDT_CR register, else the watchdog may trigger an end of period earlier than expected.” Section 18.5.3 “Watchdog Timer Status Register”: deleted note “The WDD and WDV values ... of period earlier rfo than expected.” Section 19. “Reset Controller (RSTC)” Minor editorial and formatting changes throughout rfo Section 19.4.4.1 “General Reset”: replaced “remain valid for Y cycles” with “remain valid for 3 cycles” rfo Section 19.4.4.4 “Software Reset”: removed phrase “Except for Debug purposes,” from “PERRST” bullet 9017 Section 19.5.1 “Reset Controller Control Register”: updated KEY field description 9043 Section 19.5.2 “Reset Controller Status Register”, in ‘RSTTYP’ field configuration table: - replaced column headers “RSTTYP Reset/Type/Comments” with “Value/Name/Description” and replaced binary configuration values with decimal values’ 9043 - updated reset type names in ‘RSTTYP’ field description: rfo -- was “General Reset”; is “GENERAL_RST” -- was “Wake Up Reset”; is “WKUP_RST” -- was “Watchdog Reset”; is “WDT_RST” -- was “Software Reset”; is “SOFT_RST” -- was “User Reset”; is “USER_RST” Section 19.5.3 “Reset Controller Mode Register”: updated KEY field description 9043 Section 20. “Shutdown Controller (SHDWC)” Table 20-2 Register Mapping: added “0x0000_0003” as a reset value of SHDW_MR 8828 Section 20.7.1 “Shutdown Control Register”: updated KEY field description 8869 Section 20.7.2 “Shutdown Mode Register”: updated WKMODE0 and CPTWK0 field descriptions 8432 Section 20.7.3 “Shutdown Status Register”: updated WAKEUP0 field description 8432 Section 21. “General-Purpose Backup Registers (GPBR)”: No changes SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1793 Change Request Ref. Doc. Rev. 11121C Comments Section 22. “Periodic Interval Timer (PIT)”: No changes Section 23. “Real-time Clock (RTC)” Section 23.2 “Embedded Characteristics”: added new bullet "Safety/security features” (includes “Valid Time and Date Programmation Check” as subbullet) 8544 Updated Section 23.5.3 “Alarm” 8900/9027 Added note in Section 23.6.5 “RTC Time Alarm Register” and Section 23.6.6 “RTC Calendar Alarm Register” 9027 Section 24. “Slow Clock Controller (SCKC)” Minor editorial changes throughout rfo Replaced all instances of “Read-write” with “Read/Write” rfo Section 24.3 “Block Diagram”: corrected referenced register name (was “Slow Clock Configuration Register”; is rfo “Slow Clock Controller Configuration Register”) Table 24-1 “Register Mapping”: corrected register name (was “Slow Clock Configuration Register”; is “Slow Clock Controller Configuration Register”) rfo Section 24.4.1 “Slow Clock Controller Configuration Register”: corrected register name (was “Slow Clock Configuration Register”) rfo Section 25. “Fuse Controller (FUSE)” (relocated—was previously section 51) Minor editorial changes throughout rfo Reformatted Table 25-1 “FUSE Bit Mapping” rfo Section 25.4.2 “Fuse Programming”: rfo - in step 1, replaced “using the SWEL field” with “using the WSEL field” - in step 5, replaced “Check the WS bit of FUSE_SRx” with “Check the WS bit of FUSE_IR” Reformatted register description sections rfo Section 25.5.1 “Fuse Control Register”: updated field descriptions rfo “Clock Generator“ section is now a subsection of Section 26. “Power Management Controller (PMC)” rfo SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1794 Change Request Ref. Doc. Rev. 11121C Comments Section 26. “Power Management Controller (PMC)” Minor editorial and formatting changes throughout (including replacing instances of “Read-write” with “Read/Write”) rfo Section 26.1.4 “Main Clock Selection”: removed “SAMA5D3” reference in first sentence 8983 Updated Section 26.1.5.2 “12 MHz Fast RC Oscillator Clock Frequency Adjustment” 8852 Updated Section 26.1.5.4 “Main Clock Oscillator Selection” rfo Added Section 26.1.5.5 “Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator” 9425 Section 26.1.5.6 “Software Sequence to Detect the Presence of Fast Crystal”: - updated register names (PLL_MCKR –> PMC_MCKR, PLL_SR –> PMC_SR) rfo - added “during this sequence the Main RC oscillator must be kept enabled (MOSCRCEN = 1)” to sequence introduction 9245 Updated Figure 26-8 “General Clock Block Diagram” 9022 Updated Section 26.2.7 “DDR2/LPDDR/LPDDR2 Clock” rfo Section 26.2.12 “Programming Sequence”: revised content (changed total number of steps—was 6; is 10) rfo Added Section 26.2.14 “Register Write Protection” rfo Table 26-3 “Register Mapping”: rfo - changed PMC_PLLICPR access from “Write-only” to “Read/Write” - changed reset value (was 0x0100_0100; is 0x0000_0000) Section 26.2.15.8 “PMC Clock Generator Main Oscillator Register”: - corrected order of field descriptions rfo - updated KEY field description 8837 Added note in Section 26.2.15.9 “PMC Clock Generator Main Clock Frequency Register” 8852 Section 26.2.15.14 “PMC Programmable Clock Register”: appended name PMC_PCKx with “[x = 0..2]” 9071 Section 26.2.15.17 “PMC Status Register”: replaced “of the main on-chip RC oscillator clock” with “of the fast crystal oscillator clock” in the description of fields CFDEV and CFDS rfo Section 26.2.15.20 “PLL Charge Pump Current Register”: rfo - changed access from “Write-only” to “Read/Write” - replaced “Should be written to 0” with “Should be written to 3” in description of field IPLL_PLLA Section 26.2.15.21 “PMC Write Protection Mode Register”: - modified register name (was PMC Write Protect Mode Register) rfo - updated WPKEY field description 8838 - replaced list of protectable registers with cross-reference to section “Register Write Protection” rfo Section 26.2.15.22 “PMC Write Protection Status Register”: modified register name (was PMC Write Protect Status Register) and updated description of field WPVSRC rfo Section 26.2.15.26 “PMC Peripheral Control Register”: 9085 - changed access from “Write-only” to “Read-Write” - updated PID field description SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1795 Change Request Ref. Doc. Rev. 11121C Comments Section 27. “Parallel Input/Output Controller (PIO)” Figure 27-3 “I/O Line Control Logic”: added pull-down resistor and registers rfo Section 27.5.14 “Register Write Protection”: Changed section title and revised content rfo Section 27.7.29 “PIO Slow Clock Divider Debouncing Register”: below bitmap, replaced name “DIVx” with “DIV” rfo Section 27.7.46 “PIO Write Protection Mode Register”: modified register name and aligned bit descriptions; replaced list of protectable registers with cross-reference to Section 27.5.14 “Register Write Protection” 8522/rfo rfo Section 27.7.47 “PIO Write Protection Status Register”: modified register name and aligned bit descriptions; removed note rfo Section 27.7.48 “PIO Schmitt Trigger Register”: updated SCHMITTx field description rfo Section 28. “External Memories”: No changes SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1796 Change Request Ref. Doc. Rev. 11121C Comments Section 29. “Multi-port DDR-SDRAM Controller (MPDDRC)” Formatting and editorial changes throughout Updated Section 29.1 “Description” rfo Section 29.2 “Embedded Characteristics”: rfo - replaced “CAS Latency of 2, 3, 4, 5, 6 Supported” with “CAS Latency of 2, 3 Supported” - replaced “OCD (Off-chip Driver) Mode Not Supported” with “OCD (Off-chip Driver) mode, ODT (On-die Termination) are not supported” - added new bullet “Dynamic Scrambling with user key (no impact on bandwidth)” 9223 Section 29.5.1 “DDR-SDRAM Controller Write Cycle”: replaced “fixed to 2/3/4/5 in case of DDR2-SDRAM” with rfo “fixed to 2 in case of DDR2-SDRAM” Section 29.5.2 “DDR-SDRAM Controller Read Cycle”: updated latency range (was 2 to 6; is 2 to 3) and corresponding number of anticipated read accesses rfo Section 29.5.4 “Multi-port Functionality”: replaced “set at 2 or 6 cycles (CAS latency)” with “set at 2 or 3 cycles rfo (CAS latency)” Added new Section 29.6 “Scrambling/Unscrambling Function” 9223 Section 29.8 “AHB Multi-port DDR-SDRAM Controller (MPDDRC) User Interface”: changed all instances of “Read-write” to “Read/Write” rfo Table 29-25 “Register Mapping”: corrected the offset values of MPDDRC DLL Status MASTERx registers 8884 Section 29.8.1 “MPDDRC Mode Register”: updated format of field description tables and replaced some descriptions with tables 8883 Updated Section 29.8.3 “MPDDRC Configuration Register” 8883 Section 29.8.4 “MPDDRC Timing Parameter 0 Register”: added a note on SDCK rfo Section 29.8.5 “MPDDRC Timing Parameter 1 Register”: - added a note on SDCK rfo - updated size of field TRFC in bitmap (TRFC now spans bits 4:0) 9058 - updated TRFC field description rfo Section 29.8.6 “MPDDRC Timing Parameter 2 Register”: added a note on SDCK rfo Section 29.8.7 “MPDDRC Low-power Register”: updated format of field description tables and replaced some descriptions with tables 8883 Section 29.8.10 “MPDDRC Low-power DDR2 Timing Calibration Register”: added a note on SDCK rfo Section 29.8.11 “MPDDRC I/O Calibration Register”: - added a note on SDCK rfo - updated RDIV field description 8883 Section 29.8.15 “MPDDRC Memory Device Register”: updated format of field description tables and replaced some descriptions with tables 8883 Section 29.8.17 “MPDDRC Write Protect Mode Register”: 8883 - updated the register name from “MPDDRC Write Protect Control Register” (MPDDRC_WPCR) to “MPDDRC Write Protect Mode Register” (MPDDRC_WPMR) - updated WPEN and WPKEY field descriptions SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1797 Change Request Ref. Doc. Rev. 11121C Comments Section 30. “Static Memory Controller (SMC)” Editorial and formatting changes throughout rfo Replaced all instances of “HSMC” with “SMC” (except in register names) rfo Replaced instances of “Read-write” with “Read/Write” rfo Section 30.1 “Description”: deleted first paragraph “The External Bus Interface is designed ... a Static Memory rfo Controller (HSMC).” Section 30.2 “Embedded Characteristics”: - removed following bullets: 9352 -- Programmable Flash Data Width 8 bits or 16 bits -- Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path -- Supports NAND Flash with Page Sizes of 528, 1056, 2112 and 4224 Bytes, Specified by Software -- Supports 1-bit Correction for a Page of 512, 1024, 2048 and 4096 Bytes with 8- or 16-bit Data Path -- Supports 1-bit Correction per 512 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path -- Supports 1-bit Correction per 256 Bytes of Data for a Page Size of 512, 2048 and 4096 Bytes with 8-bit Data Path -- Programmable Spare Area Size - added bullet “Supports NAND Flash Devices with 8-bit Data Path” Added Section 30.16 “Register Write Protection” 9089 Section 30.17.4 “NFC SRAM”: replaced single mapping table with five mapping tables rfo Section 30.17.4.1 “NFC SRAM Mapping”: updated second paragraph rfo Figure 30-40 “NAND Write Operation with Spare Encoding”: reformatted to unhide caption “Write NAND operation with SPAREEN set to one” in upper portion of figure rfo Figure 30-41 “NAND Write Operation”: reformatted to unhide caption “Write NAND operation with SPAREEN set to zero” in upper portion of figure rfo Table 30-19 “Register Mapping”: - changed names of following four registers: 9089 -- HSMC_OCMS (was “HSMC OCMS Register”; is “HSMC Off Chip Memory Scrambling Register”) -- HSMC_KEY1 (was “HSMC OCMS KEY1 Register”; is “HSMC Off Chip Memory Scrambling Key1 Register”) -- HSMC_KEY2 (was “HSMC OCMS KEY2 Register”; is “HSMC Off Chip Memory Scrambling Key2 Register”) -- “HSMC Write Protection Control Register (HSMC_WPCR)” changed to “HSMC Write Protection Mode Register (HSMC_WPMR)” - changed access of HSMC_WPMR (was write-only; is read-write) 9089 - updated access for registers HSMC_KEY1 and HSMC_KEY2: (was Write-only; is Write-once) rfo Section 30.20.1 “HSMC NFC Configuration Register”: updated PAGESIZE field description 8986 Section 30.20.8 “HSMC NFC Bank Register”: updated BANK bit description rfo Section 30.20.32 “HSMC Setup Register”—added following sentence below bitmap: “This register can only be 9089 written if the WPEN bit is cleared in the HSMC Write Protection Control Register” Section 30.20.33 “HSMC Pulse Register”—added following sentence below bitmap: “This register can only be 9089 written if the WPEN bit is cleared in the HSMC Write Protection Control Register” Section 30.20.34 “HSMC Cycle Register”—added following sentence below bitmap: “This register can only be 9089 written if the WPEN bit is cleared in the HSMC Write Protection Control Register” Section 30.20.35 “HSMC Timings Register”—added following sentence below bitmap: “This register can only be written if the WPEN bit is cleared in the HSMC Write Protection Control Register” 9089 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1798 Change Request Ref. Doc. Rev. 11121C Comments Section 30. “Static Memory Controller (SMC)” (continued) Section 30.20.36 “HSMC Mode Register”: 9089 - added following sentence below bitmap: “This register can only be written if the WPEN bit is cleared in the HSMC Write Protection Control Register” - updated READ_MODE and WRITE_MODE field descriptions Changed name of Section 30.20.37 “HSMC Off Chip Memory Scrambling Register” (was “HSMC OCMS Register”) rfo Changed name of Section 30.20.38 “HSMC Off Chip Memory Scrambling Key1 Register” (was “HSMC OCMS rfo KEY1 Register”)) Changed name of Section 30.20.39 “HSMC Off Chip Memory Scrambling Key2 Register” (was “HSMC OCMS rfo KEY2 Register”) Section 30.20.40 “HSMC Write Protection Mode Register”: changed section name (was “HSMC Write Protection Control Register”); changed access from write-only to read-write; updated field names (were “WP_EN” and “WP_KEY”; are “WPEN” and “WPKEY”) and updated descriptions of same rfo Section 30.20.41 “HSMC Write Protection Status Register”: updated field names (were “WP_VS” and “WP_VSRC”; are “WPVS” and “WPVSRC”); corrected size of field WPVS (was 4 bits; is 1 bit) rfo Section 31. “DMA Controller (DMAC)” Updated introduction text in Section 31.3.1 “DMA Controller 0” and Section 31.3.2 “DMA Controller 1” 8955/rfo Section 31.8.1 “DMAC Global Configuration Register”: updated ARB_CFG field description 8835 Section 31.8.15 “DMAC Channel x [x = 0..7] Descriptor Address Register”: added DMA Master Interface references to DSCR_IF field description rfo Section 31.8.17 “DMAC Channel x [x = 0..7] Control B Register”: added DMA Master Interface references to DIF and SIF field descriptions rfo Section 31.8.21 “DMAC Write Protect Mode Register”: updated WPKEY field description 8834 Section 32. “AHB LCD Controller (LCDC)” Section 32.2 “Embedded Characteristics”: updated “Display Size” (was “up to 2048x2048”; is “up to 8808 2048x2048, or up to 720p in video format” In Section 32.6.7.1 “Line Striding” and in Section 32.6.7.2 “Pixel Striding”: inserted formula for pixel address calculation 9019 Section 32.7 “LCD Controller (LCDC) User Interface”: changed “name” on Overlay registers in the corresponding register sections (“LCDC_OVR1CHER” --> “LCDC_OVRCHER1”, etc.) 8812 Updated Table 32-54 ”Register Mapping”: - changed “name” on Overlay registers (“LCDC_OVR1CHER” --> “LCDC_OVRCHER1”, etc.) 8812 - added new register LCDC_ATTR 9024 Section 32.7.10 “LCD Controller Status Register”: updated SIPSTS bit description 9008 Added Section 32.7.15 “LCD Controller Attribute Register” 9024 Section 32.7.96 “High End Overlay Layer Configuration 1 Register”: added detail on rotation angle to YUV422ROT bit description 9019 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1799 Change Request Ref. Doc. Rev. 11121C Comments Section 33. “Image Sensor Interface (ISI)” Formatting and editorial changes throughout document (including harmonization of register names) Section 33.2 “Embedded Characteristics”: updated “Preview Path” bullet to specify “Up to 2048*2048 in Grayscale mode” and “Up to 640*480 in RGB mode” 9078 Section 33.5.2 “ISI Configuration 2 Register”: updated field descriptions 8988 Section 33.5.11 “ISI Status Register”: updated field descriptions 8988 Section 33.5.12 “ISI Interrupt Enable Register”: added missing bit configuration values rfo Section 33.5.13 “ISI Interrupt Disable Register”: added missing bit configuration values rfo Section 33.5.16 “DMA Channel Disable Register”: updated field descriptions 8988 Section 33.5.17 “DMA Channel Status Register”: updated field descriptions 8988 Section 33.5.19 “DMA Preview Control Register”: updated field descriptions 8988 Section 33.5.22 “DMA Codec Control Register”: updated field descriptions 8988 Section 33.5.24 “ISI Write Protection Control Register”: updated field names in bitmap and updated field descriptions 8886 Section 34. “USB High Speed Device Port (UDPHS)” Improved readabiltiy of graphics 9004 Minor formatting and editorial changes throughout rfo Figure 34-2 “Board Schematic”: replaced resistor 6K8 with 5K62 rfo Section 34.5.1 “Power Management”: corrected names of referenced registers rfo Figure 34-3 “USB Transfer Events”: rfo - added column headers - in CONTROL row, replaced two diameter symbols with arrow symbols Section 35. “USB Host High Speed Port (UHPHS)” Minor formatting and editorial changes throughout rfo Figure 35-2 “Board Schematic to Interface UHP High-speed Host Controller”: replaced resistor 6K8 with 5K62 rfo Section 35.5.2 “Power Management”: corrected names of referenced registers and bits rfo Section 36. “Gigabit Ethernet MAC (GMAC)” Minor editorial and formatting changes throughout Section 36.6.1.6 “Interrupts”: in first paragraph, deleted content “Depending on the overall system ... CPU enters the interrupt handler” and “Note that in the default ... be write-one-to-clear if desired” rfo Section 36.6.2 “Statistics Registers”: deleted sentence “In order to reduce overall design area, the Statistics Registers may be optionally removed in the configuration file if they are deemed unnecessary for a particular design.” 8865 Section 36.7.1 “Network Control Register”: removed bit RDS (“Read Snapshot” function not supported) rfo Section 36.7.35 “Stacked VLAN Register”: added missing description to field ESVLAN rfo Section 37. “Ethernet MAC 10/100 (EMAC)”: No changes SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1800 Change Request Ref. Doc. Rev. 11121C Comments Section 38. “High Speed MultiMedia Card Interface (HSMCI)” Minor formatting and editorial changes throughout Harmonized register access type naming throughout (“Read-write” change to “Read/Write”, “Read” changed to rfo “Read-only”, “Write” changed to “Write-only”) Figure 38-1 “Block Diagram (8-bit configuration)”: added “(8-bit configuration)” to title Figure 38-2 “Block Diagram (4-bit configuration)”: added “(4-bit configuration)” to title; added missing note below figure Section 38.8.1 “Command - Response Operation”: reorganized table content in ALL_SEND_CID command example rfo Figure 38-9 “Read Functional Flow Diagram”: corrected HSMCI_MR to HSMCI_BLKR when referring to Block 9012 Length field that is not available in HSMCI_MR; deleted note “This field is also accessible in the HSMCI Block Register (HSMCI_BLKR)” Figure 38-10 “Write Functional Flow Diagram”: corrected HSMCI_MR to HSMCI_BLKR when referring to Block 9012 Length field that is not available in HSMCI_MR; deleted note “This field is also accessible in the HSMCI Block Register (HSMCI_BLKR)” Figure 38-11 “Read Multiple Block and Write Multiple Block”: corrected HSMCI_MR to HSMCI_BLKR when referring to Block Length field that is not available in HSMCI_MR 9012 Section 38.13 “Register Write Protection”: changed title (was “Write Protection Registers”); revised content rfo Section 38.14.7 “HSMCI Block Register”: deleted sentence “This field is also accessible in the HSMCI Mode Register (HSMCI_MR)” from BLKLEN field description rfo Section 38.14.18 “HSMCI Write Protection Mode Register”: - modified register name (was HSMCI Write Protect Mode Register) rfo - updated field names in bitmap and updated field descriptions 8827/8868 - replaced list of protectable registers with cross-reference to section “Register Write Protection” rfo Section 38.14.19 “HSMCI Write Protection Status Register”: modified register name (was HSMCI Write Protect rfo Status Register) and updated register description Section 39. “Serial Peripheral Interface (SPI)” Minor editorial and formatting changes Section 39.7.4 “SPI Slave Mode”: in paragraph beginning with “Then, a new data is loaded...”, replaced “the Shift Register is not modified and the last received character is retransmitted” with “the SPI_TDR is retransmitted” 8792 Table 39-5 ”Register Mapping”: 8840 - replaced offset range 0x4C–0xE0 with 0x40–0xE0 - replaced offset range 0x00E8–0x00F8 with 0x00EC–0x00F8 Section 39.8.10 “SPI Write Protection Mode Register”: updated WPKEY field description 8840 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1801 Change Request Ref. Doc. Rev. 11121C Comments Section 40. “Two-wire Interface (TWI)” Formatting and minor editorial changes throughout rfo Replaced “N” with “NA” as acronym for “Not Acknowledge” where needed Section 40.6.2 “Power Management”: deleted rogue bullet “Enable the peripheral clock” below section heading rfo Added missing “yes” and “no” in following figures: 8944/rfo - Figure 40-18 “TWI Write Operation with Multiple Data Bytes with or without Internal Address” - Figure 40-20 “TWI Read Operation with Single Data Byte and Internal Address” - Figure 40-21 “TWI Read Operation with Multiple Data Bytes with or without Internal Address” Section 40.10 “Slave Mode”: added Section 40.10.6 “Using the DMA Controller” 9055 Changed register acronym in Section 40.11 “Write Protection System” and renamed referenced field and flag names 8845 Table 40-7 “Register Mapping”: inserted reserved offset range 0x38–0xE0 8944 Section 40.12.6 “TWI Status Register”: updated NACK (used in Master mode) bit description 9145 Section 40.12.11 “TWI Transmit Holding Register”: corrected access (was Read-write; is Write-only) 9050 Changed register acronym in Section 40.12.12 “TWI Write Protection Mode Register” and updated filed names 8845 and field descriptions Changed register acronym in Section 40.12.13 “TWI Write Protection Status Register” and updated filed names 8845 and field descriptions Section 41. “Synchronous Serial Controller (SSC)” Minor editorial and formatting changes throughout Section 41.9.17 “SSC Write Protect Mode Register”: updated WPKEY field description 8841 Section 42. “Debug Unit (DBGU)”: No changes Section 43. “Universal Asynchronous Receiver Transmitter (UART)” Minor editorial and formatting changes throughout Changed register bit configuration value notations from ‘0 =’ to ‘0:’ and from ‘1 =’ to ‘1:’ rfo Table 43-3 “Register Mapping”: - inserted offset range 0x0040 - 0x00E8 (reserved) 8537 - changed access from Read-write to Read/Write where applicable rfo Section 44. “Universal Synchronous Asynchronous Receiver Transceiver (USART)” Minor formatting and editorial changes throughout Corrected Figure 44-22 “Parity Error” for stop bit value 8943 Table 44-10 “Maximum Timeguard Length Depending on Baud Rate”: replaced baud rate 33400 bit/s with 38400 bit/s 8943 Table 44-11 “Maximum Time-out Period”: replaced baud rate 33400 bit/s with 38400 bit/s 8943 Table 44-13 “IrDA Baud Rate Error”: added missing units of measure to column headers (“Bit/s” for Baud Rate rfo and “µs” for Pulse Time) Section 44.7.5.3 “IrDA Demodulator”: replaced instances of “T” with “t” when used to express time rfo Table 44-15 “Register Mapping”: 8943 - inserted offset range 0x0054–0x005C (reserved) - inserted offset range 0x0060–0x00E0 (reserved) - replaced range 0x5C–0xFC with range 0x00EC–0x00FC (reserved) Section 44.8.22 “USART Write Protect Mode Register”: updated WPKEY field description 8791 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1802 Change Request Ref. Doc. Rev. 11121C Comments Section 45. “Controller Area Network (CAN)” Minor editorial formatting changes throughout Section 45.6.3 “Interrupt”: replaced “AIC” occurrences with “interrupt controller” 8594 Table 45-4 “Receive Mailbox Objects”: added missing title rfo Table 45-5 “Transmit Mailbox Objects”: added missing title rfo Section 45.7.4.1 “CAN Bit Timing Configuration”: moved three bullets describing the phase segments to precede the bullet “TIME QUANTAM” rfo Section 45.8.1 “CAN Controller Initialization”: replaced “AIC” occurrences with “interrupt controller” 8594 Figure 45-10 “Possible Initialization Procedure”: replaced instance of “AIC” with “Interrupt Controller” 8594 WPMR register reformat using WPKEY table in Section 45.9.12 “CAN Write Protection Mode Register” 8867 Section 46. “Software Modem Device (SMD)” Section 46.1 “Description”: replaced acronym HLSD with LSD 9014 Added Section 46.4 “Software Modem Device (SMD) User Interface” (includes Section 46.4.1 “SMD Drive Register”) 8950 Section 47. “Timer Counter (TC)” Editorial and formatting changes throughout Section 47.1 “Description”: replaced “and TIOA1 inputs” with “and TIOB1 inputs” 8885 Figure 47-5 “Example of Transfer with DMAC” replaced “Internal PDC trigger” with “Peripheral trigger” 9325 Section 47.6.15.3 “Direction Status and Change Detection”: rewrote sixth paragraph for clarity rfo Section 47.6.15.4 “Position and Rotation Measurement”: rewrote first paragraph for clarity rfo Section 47.6.15.5 “Speed Measurement”: replaced sentence “The speed can be read on TC_RA0 register in TC_CMR0” with “The speed can be read on field RA in register TC_RA0” rfo Section 47.6.17 “Register Write Protection”: changed title (was “Write Protection System”); revised content rfo Section 47.7.2 “TC Channel Mode Register: Capture Mode”: updated TCCLKS field description (values 0 to 4) 9107 Section 47.7.3 “TC Channel Mode Register: Waveform Mode”: - updated ENETRG bit description 8885 - updated TCCLKS field description (values 0 to 4) 9107 Section 47.7.15 “TC Block Mode Register”: - updated FILTER bit description rfo - corrected TC2XC2S field configuration values: value 2 is TIOA0 (was TIOA1); value 3 is TIOA1 (was TIOA2) 9353 Section 47.7.20 “TC Write Protection Mode Register”: modified register name (was “TC Write Protect Mode Register”); updated field descriptions rfo/8842 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1803 Change Request Ref. Doc. Rev. 11121C Comments Section 48. “Pulse Width Modulation Controller (PWM)” Editorial and formatting changes throughout; replaced instances of “Read-write” with “Read/Write” rfo Section 48.6.2.2 “Comparator”: corrected PWM waveform period formulas 9123 Table 6-1 “Fault Inputs”: in “Polarity Level” column, replaced all instances of “1” with “To be configured to 1” rfo Section 48.6.5.4 “Changing the Synchronous Channels Update Period”: removed cross-reference to section “Method 3: Automatic write of duty-cycle values and automatic trigger of the update” from first paragraph rfo Section 48.6.1 “PWM Clock Generator”: replaced instances of “F” with “f” when used to represent frequency rfo Section 48.6.5.7 “Register Write Protection”: at end of section, replaced sentence “The WPVS and PWM_WPSR fields are automatically reset after reading the PWM_WPSR register” with “The WPVS and WPVSRC fields are automatically cleared after reading the PWM_WPSR” rfo Section 48.7.9 “PWM Sync Channels Mode Register”: removed table row for value 3 “reserved” in UPDM field rfo description Section 48.7.30 “PWM Write Protection Control Register”: updated WPKEY and WPCMD field descriptions 8849 Section 49. “Analog-to-Digital Converter (ADC)” Editorial and formatting changes throughout Added title to Figure 49-6 “Hardware Trigger Delay” 8997 Section 49.5.8 “Conversion Performances”: updated wording (‘see the product DC Characteristics section’ --> 9184 ‘see the product electrical characteristics’) Section 49.8.25 “ADC Write Protect Mode Register”: updated WPKEY field description 8856 Section 50. “True Random Number Generator (TRNG)” Figure 50-1 “TRNG Block Diagram”: reformatted graphics to improve readability 9001 Section 50.4.1 “Power Management”: minor editorial changes rfo Section 50.5 “Functional Description”: minor editorial changes rfo Section 50.6.1 “TRNG Control Register”: updated KEY field description 8843 Section 51. “Advanced Encryption Standard (AES)” Editorial and minor formatting changes throughout Section 51.2 “Embedded Characteristics”: added bullet “Double Input Buffer Optimizes Runtime” 9076 Added Section 51.4.2 “Double Input Buffer” 9076 Table 51-4 “Last Output Data Mode Behavior versus Start Modes” 9103 - reorganized order of rows - replaced “Not available” with “At the address specified in the Channel Buffer Transfer Descriptor” in row Encrypted/Decrypted Data Result Location at DMA Transfer LOD = 0 Section 51.6.2 “AES Mode Register”: - updated CKEY field description 8859 - updated LOD field description 9103 - added field DUALBUFF 9076 Section 51.6.10 “AES Initialization Vector Register x”: updated IV field description 8892 Section 52. “Triple Data Encryption Standard (Triple DES)”: No changes Section 53. “Secure Hash Algorithm (SHA)”: No changes SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1804 Change Request Ref. Doc. Rev. 11121C Comments Section 54. “Electrical Characteristics” Minor editorial and formatting changes throughout rfo Table 54-1 “Absolute Maximum Ratings*”: rfo - deleted “Operating Temperature (Industrial)..............-40° C to +85°C” - added (VDDFUSE)...3.3V Section 54.2 “DC Characteristics”: in first sentence, replaced “TA = -40°C to +85°C” with “TA = -40°C to +105°C” rfo Table 54-2 “DC Characteristics”: rfo - deleted parameters VVDDCORErip / VDDCORE ripple, VVDDBUrip / VDDBU ripple, VVDDPLLArip / VDDPLLA ripple, and VVDDOSCrip / VDDOSC ripple - added parameters VVDDFUSE / DC Supply FUSE box and IVDDFUSE / VDDFUSE current - updated parameter ISC / Static Current - updated parameter name and conditions of VVDDOSC Updated Section 54.3 “Power Consumption” rfo Table 54-9 “Processor Clock Waveform Parameters”: updated conditions, minimum values and footnote rfo Table 54-10 “Master Clock Waveform Parameters”: updated conditions and footnote rfo Section 54.5.1 “Crystal Oscillator Characteristics”: in first sentence, replaced “TA = -40°C to +85°C” with “TA = - rfo 40°C to +105°C” Table 54-15 “32 kHz Oscillator Characteristics”: corrected referenced register name and section in note rfo Table 54-19 “PLLA Characteristics”: updated output frequency conditions 9031 Table 54-45 “System Clock Waveform Parameters”: replaced “T = 85°C” with “TA = 85°C” in conditions rfo Table 54-46 “System Clock Waveform Parameters”: replaced “T = 85°C” with “TA = 85°C” in conditions rfo Table 54-47 “System Clock Waveform Parameters”: replaced “T = 85°C” with “TA = 85°C” in conditions rfo Section 54.18 “MCI Timings”: updated content; removed “MCI Timings” figure and table rfo Section 54.21 “Two-wire Interface Characteristics”: updated Table 54-60 “Two-wire Serial Bus Requirements” and the corresponding notes 8819 Table 54-56 “EMAC MII Specific Signals”: in footnote, corrected link to note 2 of Table 54-55 “EMAC Signals Relative to EMDC” (was incorrectly linked to note of Table 54-49 “SSC Timings with 3.3V Peripheral supply”) rfo Table 54-57 “RMII Mode”: in footnote, corrected link to note 2 of Table 54-55 “EMAC Signals Relative to EMDC” (was incorrectly linked to note of Table 54-49 “SSC Timings with 3.3V Peripheral supply”) rfo Section 55. “Mechanical Characteristics” Added Section 55.2 “324-ball TFBGA Mechanical Characteristics” (introduced new package) 9035 Section 56. “SAMA5D3 Ordering Information” Updated Table 56-1 “SAMA5D3 Ordering Information” (includes adding SAMA5D36 device references and introduction of 324-ball TFBGA package) 8822 9035 Section 57. “SAMA5D3 Series Errata” Updated Section 57.3 “LCD Controller (LCDC)” 8971 Added Section 57.6 “Watchdog Timer (WDT)” 8969 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1805 Doc. Rev. 11121B Change Request Ref. Comments Introduction: Section 8.1 “Chip Identification”, updated Chip ID: “0x8A5C07C1” --> “0x8A5C07C2”. rfo “Description” , added a cross-reference to Table 1-1 “SAMA5D3 Device Differences” in the last paragraph. rfo Replaced “Cortex™” references with “Cortex®” in “Description” and further on in the entire document. rfo Removed “AT91SAM” from the document title. Standard Boot Strategies: Section 12.3.4.1 “NAND Flash Boot: NAND Flash Detection”, added the eccBitReq field description in “NAND Flash Specific Header Detection” . 8796 SFR: Added a row for SFR_UTMICKTRIM register (offset value “0x30”) in Table 16-1 "Register Mapping" and the corresponding Table 16.3.5 "UTMI Clock Trimming Register". 8683 External Memories: Section 28.1.5 “Product Dependencies”, updated LPDDR2 Mode data in Table 28-2 “DDR2 I/O Lines Usage vs rfo Operating Modes” (DDR_WE, DDR_RAS - DDR_CAS, and DDR_A[13..0]). Section 28.1.6.2 “2x16-bit LPDDR2”, added references on CAx LP-DDR2 signals and Table 28-3 “CAx LPDDR2 Signal Connection”. USART: Added a paragraph on IRDA_FILTER programming criteria in Section 44.7.5.3 “IrDA Demodulator” and in the corresponding field description in Section 44.8.20 “USART IrDA FILTER Register”. 8508 Section 44.8.18 “USART FI DI RATIO Register”, expanded FI_DI_RATIO field to 16 bits in the register table. 8643 FUSE: Section 50.2 “Embedded Characteristics”, added references on FUSE bits. 8785 Added Section 50.2.1 “FUSE Bit Mapping” and Section 50.2.2 “Special Functions”. Electrical Characteristics: Section 54.6 “12 MHz RC Oscillator Characteristics”, updated the IDDON value in Table 54-12. rfo Section 54.7 “32 kHz Oscillator Characteristics”, added a row on PON in Table 54-13. Section 54.11 “12-Bit ADC Characteristics”, updated data in: - Table 54-22 “Analog Power Supply Characteristics” - Table 54-23 “Channel Conversion Time and ADC Clock” - Table 54-24 “External Voltage Reference Input” - Table 54-25 “INL, DNL, 12-bit mode, VDDANA 2.4V to 3.6V supply voltage conditions” - Table 54-26 “Gain Error, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions” - Table 54-27 “Error offset with or without calibration, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions” - Table 54-28 “Dynamic Performance Characteristics in Single ended and 12 bits mode (1)”; and - Table 54-29 “Dynamic Performance Characteristics in Differential and 12 bits mode(1)” Added Section 54.15 “MPDDRC Timings” rfo Section 54.16 “SSC Timings”, updated PIXCLK frequency maximum value and fixed transmitter parameter data rfo for SSC7 in Table 54-47 “SSC Timings with 3.3V Peripheral supply” and Table 54-48 “SSC Timing with 1V8 Peripheral supply” SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1806 Doc. Rev. 11121B Change Request Ref. Comments Mechanical Characteristics: Added “Nominal Ball Diameter” and “Solder” rows in Table 55-4 “Package Information”. rfo Errata: Added the introduction paragraph in Section 57. “SAMA5D3 Series Errata”. rfo Added Section 57.1.2 “Boot ROM: NAND Flash Detection using ONFI Parameters does Not Work”. 8785 Comments Change Request Ref. Doc. Rev. 11121A First Issue SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1807 Table of Contents 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 4.2 4.3 4.4 4.5 324-ball LFBGA Package (15 x 15 x 1.4 mm, pitch 0.8 mm) . . . . . . . . . . . . . 324-ball LFBGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324-ball TFBGA Package (12 x 12 x 1.2 mm, pitch 0.5 mm) . . . . . . . . . . . . . 324-ball TFBGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 19 20 28 5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 5.2 5.3 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power-up Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power-down Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 6.2 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. Real-time Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 7.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Real-time Event Mapping List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8. System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 8.2 Chip Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Backup Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 9.2 9.3 9.4 Peripheral Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Signal Multiplexing on I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Clock Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 39 39 10. ARM Cortex-A5 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.1 10.2 10.3 10.4 10.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 41 41 48 11. SAMA5D3 Series Debug and Test . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 11.2 11.3 11.4 11.5 11.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 52 52 53 54 56 57 1808 11.7 11.8 The Boundary JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 The Cortex-A5 DP Identification Code Register IDCODE . . . . . . . . . . . . . . . 60 12. Standard Boot Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.1 12.2 12.3 12.4 Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 63 64 74 13. Boot Sequence Controller (BSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.1 13.2 13.3 13.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boot Sequence Controller (BSC) Registers User Interface . . . . . . . . . . . . . . 78 78 78 79 14. AXI Bus Matrix (AXIMX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.1 14.2 14.3 14.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AXI Matrix (AXIMX) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 81 82 85 15. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Bus Granting Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Default Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Last Access Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed Default Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Matrix (MATRIX) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 89 90 90 90 90 91 91 93 94 16. Special Function Registers (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . 103 16.1 16.2 16.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Special Function Registers (SFR) User Interface . . . . . . . . . . . . . . . . . . . . 104 17. Advanced Interrupt Controller (AIC) . . . . . . . . . . . . . . . . . . . . . . . . 111 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AIC Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Line Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Interrupt Controller (AIC) User Interface . . . . . . . . . . . . . . . . . . . 111 111 112 112 112 113 113 113 124 18. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 18.1 18.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1809 18.3 18.4 18.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Watchdog Timer (WDT) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 19. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 19.1 19.2 19.3 19.4 19.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 158 158 159 167 20. Shutdown Controller (SHDWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 20.1 20.2 20.3 20.4 20.5 20.6 20.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shutdown Controller (SHDWC) User Interface . . . . . . . . . . . . . . . . . . . . . . 171 171 171 171 172 172 173 21. General-Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . 177 21.1 21.2 21.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 General Purpose Backup Registers (GPBR) User Interface . . . . . . . . . . . . 178 22. Periodic Interval Timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 22.1 22.2 22.3 22.4 22.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Periodic Interval Timer (PIT) User Interface . . . . . . . . . . . . . . . . . . . . . . . . 180 180 181 182 183 23. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 23.1 23.2 23.3 23.4 23.5 23.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 188 189 189 189 193 24. Slow Clock Controller (SCKC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 24.1 24.2 24.3 24.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock Controller (SCKC) User Interface . . . . . . . . . . . . . . . . . . . . . . . 206 206 207 209 25. Fuse Controller (FUSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 25.1 25.2 25.3 25.4 25.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fuse Controller (FUSE) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 211 211 213 214 216 1810 26. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . 222 26.1 26.2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 27. Parallel Input/Output Controller (PIO) . . . . . . . . . . . . . . . . . . . . . . 274 27.1 27.2 27.3 27.4 27.5 27.6 27.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . 274 274 275 276 277 284 286 28. External Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 28.1 28.2 MPDDRC Multi-port DDRSDR Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 340 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 29. Multi-port DDR-SDRAM Controller (MPDDRC) . . . . . . . . . . . . . . . 351 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPDDRC Module Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies, Initialization Sequence . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambling/Unscrambling Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Interface/SDRAM Organization, Address Mapping . . . . . . . . . . . AHB Multi-port DDR-SDRAM Controller (MPDDRC) User Interface . . . . . . 351 351 352 353 356 368 369 374 30. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 404 30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 30.9 30.10 30.11 30.12 30.13 30.14 30.15 30.16 30.17 30.18 30.19 30.20 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connection to External Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Read and Write Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scrambling/Unscrambling Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slow Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND Flash Controller Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMECC Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . 404 405 406 407 407 408 408 408 409 411 418 419 422 426 432 434 434 446 452 457 31. DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 31.1 31.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1811 31.3 31.4 31.5 31.6 31.7 31.8 DMA Controller Peripheral Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMAC Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Controller (DMAC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 512 513 538 539 540 32. AHB LCD Controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 32.1 32.2 32.3 32.4 32.5 32.6 32.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller (LCDC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 566 567 568 568 570 606 33. Image Sensor Interface (ISI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 33.1 33.2 33.3 33.4 33.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Image Sensor Interface (ISI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . 807 807 808 808 816 34. USB High Speed Device Port (UDPHS) . . . . . . . . . . . . . . . . . . . . 848 34.1 34.2 34.3 34.4 34.5 34.6 34.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB High Speed Device Port (UDPHS) User Interface . . . . . . . . . . . . . . . . 848 849 849 850 850 851 876 35. USB Host High Speed Port (UHPHS) . . . . . . . . . . . . . . . . . . . . . . 925 35.1 35.2 35.3 35.4 35.5 35.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 925 926 927 927 929 36. Gigabit Ethernet MAC (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 36.1 36.2 36.3 36.4 36.5 36.6 36.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet MAC (GMAC) User Interface . . . . . . . . . . . . . . . . . . . . . . 930 930 931 932 932 958 962 37. Ethernet MAC 10/100 (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 37.1 37.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1812 37.3 37.4 37.5 37.6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet MAC 10/100 (EMAC) User Interface . . . . . . . . . . . . . . . . . . . . . . 1075 1076 1086 1089 38. High Speed MultiMedia Card Interface (HSMCI) . . . . . . . . . . . . . 1144 38.1 38.2 38.3 38.4 38.5 38.6 38.7 38.8 38.9 38.10 38.11 38.12 38.13 38.14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed MultiMedia Card Operations . . . . . . . . . . . . . . . . . . . . . . . . . SD/SDIO Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Boot Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMCI Transfer Done Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Speed MultiMedia Card Interface (HSMCI) User Interface . . . . . . . . 1144 1144 1145 1147 1148 1149 1150 1152 1169 1170 1171 1171 1173 1174 39. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . 1202 39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . 1202 1202 1203 1204 1204 1204 1205 1217 40. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 40.1 40.2 40.3 40.4 40.5 40.6 40.7 40.8 40.9 40.10 40.11 40.12 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-wire Interface (TWI) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 1233 1234 1234 1235 1236 1237 1238 1251 1254 1261 1262 41. Synchronous Serial Controller (SSC) . . . . . . . . . . . . . . . . . . . . . 1279 41.1 41.2 41.3 41.4 41.5 41.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1279 1279 1280 1280 1281 1281 1813 41.7 41.8 41.9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 SSC Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294 Synchronous Serial Controller (SSC) User Interface . . . . . . . . . . . . . . . . . 1296 42. Debug Unit (DBGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323 42.1 42.2 42.3 42.4 42.5 42.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Unit (DBGU) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323 1324 1325 1326 1326 1333 43. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . 1348 43.1 43.2 43.3 43.4 43.5 43.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Asynchronous Receiver Transmitter (UART) User Interface . . 1348 1348 1348 1349 1349 1355 44. Universal Synchronous Asynchronous Receiver Transceiver (USART) 1365 44.1 44.2 44.3 44.4 44.5 44.6 44.7 44.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367 I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface 1402 45. Controller Area Network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . 1433 45.1 45.2 45.3 45.4 45.5 45.6 45.7 45.8 45.9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAN Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controller Area Network (CAN) User Interface . . . . . . . . . . . . . . . . . . . . . 1433 1433 1434 1435 1435 1435 1436 1447 1459 46. Software Modem Device (SMD) . . . . . . . . . . . . . . . . . . . . . . . . . 1490 46.1 46.2 46.3 46.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Modem Device (SMD) User Interface . . . . . . . . . . . . . . . . . . . . . 1490 1491 1491 1492 47. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 47.1 47.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1814 47.3 47.4 47.5 47.6 47.7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter (TC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496 1497 1497 1498 1517 48. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . 1545 48.1 48.2 48.3 48.4 48.5 48.6 48.7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulation Controller (PWM) User Interface . . . . . . . . . . . . . 1545 1546 1547 1547 1548 1549 1569 49. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . 1617 49.1 49.2 49.3 49.4 49.5 49.6 49.7 49.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Touchscreen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter (ADC) User Interface . . . . . . . . . . . . . . . . . . . 1617 1618 1619 1619 1620 1621 1630 1643 50. True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . 1675 50.1 50.2 50.3 50.4 50.5 50.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . True Random Number Generator (TRNG) User Interface . . . . . . . . . . . . . 1675 1675 1675 1676 1676 1677 51. Advanced Encryption Standard (AES) . . . . . . . . . . . . . . . . . . . . . 1684 51.1 51.2 51.3 51.4 51.5 51.6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Encryption Standard (AES) User Interface . . . . . . . . . . . . . . . . 1684 1684 1684 1685 1690 1691 52. Triple Data Encryption Standard (Triple DES) . . . . . . . . . . . . . . . 1703 52.1 52.2 52.3 52.4 52.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple Data Encryption Standard (TDES) User Interface . . . . . . . . . . . . . . 1703 1703 1704 1704 1710 53. Secure Hash Algorithm (SHA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724 53.1 53.2 53.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724 SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1815 53.4 53.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725 Secure Hash Algorithm (SHA) User Interface . . . . . . . . . . . . . . . . . . . . . . 1728 54. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738 54.1 54.2 54.3 54.4 54.5 54.6 54.7 54.8 54.9 54.10 54.11 54.12 54.13 54.14 54.15 54.16 54.17 54.18 54.19 54.20 54.21 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MHz RC Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 kHz Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 kHz RC Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB HS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-Bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HSMC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPDDRC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC/GMAC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART in SPI Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-wire Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738 1739 1741 1745 1747 1749 1749 1751 1751 1752 1753 1757 1758 1763 1767 1768 1773 1774 1774 1778 1780 55. Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782 55.1 55.2 55.3 324-ball LFBGA Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 1782 324-ball TFBGA Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 1784 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786 56. SAMA5D3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . 1787 57. SAMA5D3 Series Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788 57.1 57.2 57.3 57.4 57.5 57.6 Standard Boot Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static Memory Controller (HSMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Controller (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gigabit Ethernet MAC (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAMA5D3 Series [DATASHEET] 11121C–ATARM–15-Oct-13 1788 1788 1788 1788 1789 1790 1816 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81) (3) 6417-0370 Fax: (+852) 2722-1369 © 2013 Atmel Corporation. All rights reserved. / Rev.: 11121C–ATARM–15-Oct-13 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, QTouch®, SAM-BA® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Windows® and others, are registered trademarks or trademarks of Microsoft Corporation in the US and/or other countries. ARM®, Cortex®, Thumb®-2 and others are registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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