ATSAMD10D13A-MNT

厂商：
ACTEL(微芯科技)
封装：
QFN24
描述：

数据手册：

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数据手册
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ATSAMD10D13A-MNT 数据手册

Atmel SAM D10 SMART ARM-Based Microcontroller DATASHEET Description The Atmel® | SMART™ SAM D10 is a series of low-power microcontrollers using the 32-bit ARM® Cortex®-M0+ processor, and ranging from 14- to 24-pins with up to 16KB Flash and 4KB of SRAM. The SAM D10 devices operate at a maximum frequency of 48MHz and reach 2.46 Coremark/MHz. They are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. The SAM D10 series is compatible to the other product series in the SAM D family, enabling easy migration to larger device with added features. The Atmel SAM D10 devices provide the following features: In-system programmable Flash, sixchannel direct memory access (DMA) controller, 6 channel Event System, programmable interrupt controller, up to 22 programmable I/O pins, 32-bit real-time clock and calendar, two 16bit Timer/Counters (TC) and one 24-bit Timer/Counter for Control (TCC), where each TC can be configured to perform frequency and waveform generation, accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs can operate in 8or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and one timer/counter has extended functions optimized for motor, lighting and other control applications. The series provide up to three Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus and LIN slave; up to 10-channel 350ksps 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with window mode, Peripheral Touch Controller supporting up to 72 buttons, sliders, wheels and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD) program and debug interface. All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for the system clock. Different clock domains can be independently configured to run at different frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency while reducing power consumption. The SAM D10 devices have two software-selectable sleep modes, idle and standby. In idle mode the CPU is stopped while all other functions can be kept running. In standby all clocks and functions are stopped expect those selected to continue running. The device supports SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in standby mode. The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be used for non-intrusive on-chip debug and trace of application code. A boot loader running in the device can use any communication interface to download and upgrade the application program in the Flash memory. The Atmel SAM D10 devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits. Atmel-42242H-SAM-D10-Datasheet_09/2016 SMART Features z Processor z ARM Cortex-M0+ CPU running at up to 48MHz z Single-cycle hardware multiplier z Micro Trace Buffer z Memories z 8/16KB in-system self-programmable Flash z 4KB SRAM Memory z System z Power-on reset (POR) and brown-out detection (BOD) z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M) z External Interrupt Controller (EIC) z 8 external interrupts z One non-maskable interrupt z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface z Low Power z Idle and standby sleep modes z SleepWalking peripherals z Peripherals z 6-channel Direct Memory Access Controller (DMAC) z 6-channel Event System z Two 16-bit Timer/Counters (TC), configurable as either: z One 16-bit TC with compare/capture channels z One 8-bit TC with compare/capture channels z One 32-bit TC with compare/capture channels, by using two TCs z One 24-bit Timer/Counters for Control (TCC), with extended functions: z Up to four compare channels with optional complementary output z Generation of synchronized pulse width modulation (PWM) pattern across port pins z Deterministic fault protection, fast decay and configurable dead-time between complementary output z Dithering that increase resolution with up to 5 bit and reduce quantization error z 32-bit Real Time Counter (RTC) with clock/calendar function z Watchdog Timer (WDT) z CRC-32 generator z Up to three Serial Communication Interfaces (SERCOM), each configurable to operate as either: z USART with full-duplex and single-wire half-duplex configuration z I2C Bus up to 3.4MHz z SMBUS/PMBUS z SPI z LIN slave z 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 10 channels z Differential and single-ended input z 1/2x to 16x programmable gain stage z Automatic offset and gain error compensation z Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution z 10-bit, 350ksps Digital-to-Analog Converter (DAC) z Two Analog Comparators (AC) with window compare function z Peripheral Touch Controller (PTC) z Up to 72-channel capacitive touch and proximity sensing z I/O z Up to 22 programmable I/O pins z Packages z 24-pin QFN z 20-pin SOIC z 20-ball WLCSP z 14-pin SOIC z Operating Voltage z 1.62V – 3.63V Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 2 1. Configuration Summary Table 1-1. Configuration Summary SAM D10D – 24-pin QFN SAM D10D – 20-pin SOIC / WLCSP SAM D10C – 14-pin SOIC Pins 24 20 14 General Purpose I/O-pins (GPIOs) 22 18 12 Flash 16/8KB 16/8KB 16/8KB SRAM 4KB 4KB 4KB Timer Counter (TC) 2 2 2(3) Waveform output channels for TC 2 2 2 Timer Counter for Control (TCC) 1 1 1 Waveform output channels per TCC 8 8 8 DMA channels 6 6 6 Serial Communication Interface (SERCOM) 3 3 2 Analog-to-Digital Converter (ADC) channels 10 8 5 Analog Comparators (AC) 2 2 2 Digital-to-Analog Converter (DAC) channels 1 1 1 Yes Yes Yes 1 1 1 Real-Time Counter (RTC) RTC alarms Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 3 Table 1-1. Configuration Summary (Continued) SAM D10D – 24-pin QFN SAM D10D – 20-pin SOIC / WLCSP SAM D10C – 14-pin SOIC 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values 8 8 8 Peripheral Touch Controller (PTC) channels (X- x Y-lines) for mutual capacitance(1) 72 (9x8) 42 (7x6) 12 (4x3) Peripheral Touch Controller (PTC) channels for self capacitance (Ylines only)(2) 16 13 7 48MHz 48MHz 48MHz QFN SOIC / WLCSP SOIC RTC compare values External Interrupt lines Maximum CPU frequency Packages 32.768kHz crystal oscillator (XOSC32K) 0.4-32MHz crystal oscillator (XOSC) 32.768kHzinternal oscillator (OSC32K) 32kHz ultra-low-power internal oscillator (OSCULP32K) 8MHz high-accuracy internal oscillator (OSC8M) 48MHz Digital Frequency Locked Loop (DFLL48M) 96MHz Fractional Digital Phased Locked Loop (FDPLL96M) Oscillators Event System channels 6 6 6 SW Debug Interface Yes Yes Yes Watchdog Timer (WDT) Yes Yes Yes Notes: 1. 2. 3. The number of X- and Y-lines depends on the configuration of the device, as some I/O lines can be configured as either X-lines or Y-lines. Refer to “I/O Multiplexing and Considerations” on page 13 for details. The number in the “Configuration Summary” on page 3 is the maximum number of channels that can be obtained. The number of Y-lines depends on the configuration of the device, as some I/O lines can be configured as either X-lines or Y-lines. The number given here is the maximum number of Y-lines that can be obtained. The signals for TC2 are not routed out on the 14-pin package. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 4 2. Ordering Information SAMD 10 C 14 A - M U T Product Family Package Carrier SAMD = General Purpose Microcontroller No character = Tray (Default) T = Tape and Reel Product Series 10 = Cortex M0+ DMA Package Grade O Pin Count U = -40 - 85 C Matte Sn Plating N = -40 - 105 C Matte Sn Plating O C = 14 pins D = 20/24 pins Package Type Flash Memory Density M = QFN SS = SOIC U = WLCSP 14 = 16KB 13 = 8KB Device Variant A = Default Variant 2.1 SAM D10C – 14-pin SOIC Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMD10C13A-SSUT 8K 4K SOIC14 Tape & Reel ATSAMD10C13A-SSNT 8K 4K SOIC14 Tape & Reel ATSAMD10C14A-SSUT 16K 4K SOIC14 Tape & Reel ATSAMD10C14A-SSNT 16K 4K SOIC14 Tape & Reel FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMD10D13A-SSUT 8K 4K SOIC20 Tape & Reel ATSAMD10D13A-SSNT 8K 4K SOIC20 Tape & Reel ATSAMD10D14A-SSUT 16K 4K SOIC20 Tape & Reel ATSAMD10D14A-SSNT 16K 4K SOIC20 Tape & Reel 2.2 SAM D10D – 20-pin SOIC Ordering Code Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 5 2.3 SAM D10D – 20-ball WLCSP Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type 16K 4K WLCSP20 Tape & Reel FLASH (bytes) SRAM (bytes) Package Carrier Type ATSAMD10D13A-MUT 8K 4K QFN24 Tape & Reel ATSAMD10D13A-MNT 8K 4K QFN24 Tape & Reel ATSAMD10D14A-MUT 16K 4K QFN24 Tape & Reel ATSAMD10D14A-MNT 16K 4K QFN24 Tape & Reel ATSAMD10D14A-UUT 2.4 SAM D10D – 24-pin QFN Ordering Code 2.5 Device Identification The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification register (DID.DEVSEL) in order to identify the device by software. The device variants have a reset value of DID=0x1001drxx, with the LSB identifying the die number ('d'), the die revision ('r') and the device selection ('xx'). Table 2-1. Device Identification Values Device Variant DID.DEVSEL Device ID (DID) SAMD10D14AM 0x00 0x10020r00 SAMD10D13AM 0x01 0x10020r01 Reserved 0x02 SAMD10D14ASS 0x03 0x10020r03 SAMD10D13ASS 0x04 0x10020r04 Reserved 0x05 SAMD10C14A 0x06 0x10020r06 SAMD10C13A 0x07 0x10020r07 Reserved 0x08 SAMD10D14AU 0x09 0x10020r09 Note: The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. The device variant denotes functional differences, whereas the die revision marks evolution of the die Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 6 3. Block Diagram SWCLK CORTEX-M0+ PROCESSOR Fmax 48 MHz SERIAL WIRE SWDIO MICRO TRACE BUFFER IOBUS DEVICE SERVICE UNIT M 8/16 KB NVM 4 KB RAM NVM CONTROLLER Cache SRAM CONTROLLER M M S M HIGH SPEED BUS MATRIX PERIPHERAL ACCESS CONTROLLER S AHB-APB BRIDGE B S AHB-APB BRIDGE A AHB-APB BRIDGE C PERIPHERAL ACCESS CONTROLLER SYSTEM CONTROLLER PORT DMA S PERIPHERAL ACCESS CONTROLLER DMA 36xxSERCOM SERCOM VREF BOD33 S PAD0 PAD1 PAD2 PAD3 OSCULP32K XOUT32 XIN32 OSC32K XOSC32K DMA OSC8M XIN XOUT XOSC 2 x TIMER / COUNTER 8 x Timer Counter WO0 WO1 DFLL48M POWER MANAGER CLOCK CONTROLLER RESETN RESET CONTROLLER GCLK_IO[5..0] SLEEP CONTROLLER WATCHDOG TIMER Notes: 1. 2. 1 x TIMER / COUNTER FOR CONTROL EXTERNAL INTERRUPT CONTROLLER WO0 WO1 (2) WOn AIN[9..0] DMA 10-CHANNEL 12-bit ADC 350KSPS GENERIC CLOCK CONTROLLER REAL TIME COUNTER EXTINT[7..0] NMI EVENT SYSTEM DMA PORT FDPLL96M 2 ANALOG COMPARATORS DMA VREFA VREFB AIN[3..0] VOUT 10-bit DAC VREFA X[10] PERIPHERAL TOUCH CONTROLLER Y[5..0] X[9..0] / Y[15..6] (3) Some products have different number of SERCOM instances, PTC signals and ADC signals. The number of PTC X- and Y-lines depend on the configuration of the device, as some I/O lines can be configured as either X-lines or Y-lines. Refer to “I/O Multiplexing and Considerations” on page 13 for details. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 7 4. Pinout 4.1 SAM D10C 14-pin SOIC PA05 1 14 PA04 PA08 2 13 PA02 PA09 3 12 VDDIO/IN/ANA PA14 4 11 GND PA15 5 10 PA25 6 9 PA24 7 8 PA31 PA28/RST PA30 DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY RESET/GPIO PIN 4.2 SAM D10D 20-pin SOIC PA05 1 20 PA04 PA06 2 19 PA03 PA07 3 18 PA02 PA08 4 17 VDDIO/IN/ANA PA09 5 16 GND PA14 6 15 PA25 PA15 7 14 PA24 PA16 8 13 PA31 PA22 9 12 PA30 PA23 10 11 PA28/RST DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY RESET/GPIO PIN Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 8 4.3 SAM D10D 20-ball WLCSP A 1 02 PA 3 A0 2 P 3 PA 4 PA 04 06 B D VD/IN/ANA IO 5 A0 P 07 PA 08 PA C 25 PA ND G 16 PA 09 PA D 24 PA 0 A3 P 23 PA 14 PA E 31 PA / 28 A P ST R 22 PA 15 PA Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 9 GND PA25 PA24 PA31 PA30 24 23 22 21 20 19 VDDIO/IN/ANA SAM D10D 24-pin QFN 1 2 3 4 5 6 18 17 16 15 14 13 PA28/RST PA27 PA23 PA22 PA17 PA16 7 8 9 10 11 12 PA02 PA03 PA04 PA05 PA06 PA07 DIGITAL PIN ANALOG PIN OSCILLATOR GROUND INPUT SUPPLY RESET/GPIO PIN PA08 PA09 PA10 PA11 PA14 PA15 4.4 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 10 5. Signal Descriptions List The following table gives details on signal names classified by peripheral. Table 5-1. Signal Descriptions List Signal Name Function Type Active Level Analog Comparators - AC AIN[3:0] AC Analog Inputs Analog CMP[1:0] AC Comparator Outputs Digital Analog Digital Converter - ADC AIN[19:0] ADC Analog Inputs Analog VREFA ADC Voltage External Reference A Analog VREFB ADC Voltage External Reference B Analog Digital Analog Converter - DAC VOUT DAC Voltage output Analog VREFA DAC Voltage External Reference A Analog External Interrupt Controller EXTINT[7:0] External Interrupts Input NMI External Non-Maskable Interrupt Input Generic Clock Generator - GCLK GCLK_IO[5:0] Generic Clock (source clock or generic clock generator output) I/O Power Manager - PM RESET Reset Input Low Serial Communication Interface - SERCOMx PAD[3:0] SERCOM I/O Pads I/O System Control - SYSCTRL XIN Crystal Input Analog/ Digital XIN32 32kHz Crystal Input Analog/ Digital XOUT Crystal Output Analog XOUT32 32kHz Crystal Output Analog Waveform Outputs Output Waveform Outputs Output Timer Counter - TCx WO[1:0] Timer Counter - TCCx WO[1:0] Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 11 Table 5-1. Signal Descriptions List (Continued) Signal Name Function Type Active Level Peripheral Touch Controller - PTC X[15:0] PTC Input Analog Y[15:0] PTC Input Analog General Purpose I/O - PORT PA25 - PA00 Parallel I/O Controller I/O Port A I/O PA28 - PA27 Parallel I/O Controller I/O Port A I/O PA31 - PA30 Parallel I/O Controller I/O Port A I/O PB17 - PB00 Parallel I/O Controller I/O Port B I/O PB23 - PB22 Parallel I/O Controller I/O Port B I/O PB31 - PB30 Parallel I/O Controller I/O Port B I/O Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 12 6. I/O Multiplexing and Considerations 6.1 Multiplexed Signals Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. Table 5-1 on page 11 describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1. PORT Function Multiplexing Pin A SAMD10D SAMD10C 20-pin SAMD10D SOIC/ 14-pin 24-pin WLCSP SOIC QFN I/O Pin Supply 13 18 / A1 1 PA02 Type VDD EIC B REF EXTINT[2] ADC AC PTC DAC VOUT C D E F G H SERCOM(1) SERCOMALT TC/TCC TCC COM GCLK AIN[0] Y[0] AIN[1] Y[1] AIN[2] AIN[0] Y[2] SERCOM0/ PAD[2] SERCOM0/ PAD[0] TC1/WO[0] TCC0/ WO[0] 19 / A2 2 PA03 VDD EXTINT[3] ADC/VREFA DAC/VREFA 14 20 / A3 3 PA04 VDD EXTINT[4] ADC/VREFB 1 1 / B2 4 PA05 VDD EXTINT[5] AIN[3] AIN[1] Y[3] SERCOM0/ PAD[3] SERCOM0/ PAD[1] TC1/WO[1] TCC0/ WO[1] 2 / A4 5 PA06 VDD EXTINT[6] AIN[4] AIN[2] Y[4] SERCOM0/ PAD[0] SERCOM0/ PAD[2] TC2/WO[0] TCC0/ WO[2] 3 / B3 6 PA07 VDD EXTINT[7] AIN[5] AIN[3] Y[5] SERCOM0/ PAD[1] SERCOM0/ PAD[3] TC2/WO[1] TCC0/ WO[3] 2 4 / B4 7 PA08 VDD EXTINT[6] SERCOM1/ PAD[2] SERCOM0/ PAD[2] TCC0/WO[2] TCC0/ WO[4] GCLK_IO[0] 3 5 / C4 8 PA09 VDD EXTINT[7] SERCOM1/ PAD[3] SERCOM0/ PAD[3] TCC0/WO[3] TCC0/ WO[5] GCLK_IO[1] 9 PA10 VDD EXTINT[2] AIN[8] CMP[0] X[2]/Y[8] SERCOM0/ PAD[2] SERCOM2/ PAD[2] TC2/WO[0] TCC0/ WO[2] GCLK_IO[4] 10 PA11 VDD EXTINT[3] AIN[9] CMP[1] X[3]/Y[9] SERCOM0/ PAD[3] SERCOM2/ PAD[3] TC2/WO[1] TCC0/ WO[3] GCLK_IO[5] 4 6 / D4 11 PA14 VDD I2C NMI AIN[6] CMP[0] X[0]/Y[6] SERCOM0/ PAD[0] SERCOM2/ PAD[0] TC1/WO[0] TCC0/ WO[0] GCLK_IO[4] 5 7 / E4 12 PA15 VDD I2C EXTINT[1] AIN[7] CMP[1] X[1]/Y[7] SERCOM0/ PAD[1] SERCOM2/ PAD[1] TC1/WO[1] TCC0/ WO[1] GCLK_IO[5] 8 / C3 13 PA16 VDD EXTINT[0] X[4]/Y[10] SERCOM1/ PAD[2] SERCOM2/ PAD[2] TC1/WO[0] TCC0/ WO[6] GCLK_IO[2] 14 PA17 VDD EXTINT[1] X[5]/Y[11] SERCOM1/ PAD[3] SERCOM2/ PAD[3] TC1/WO[1] TCC0/ WO[7] GCLK_IO[3] 15 PA22 VDD EXTINT[6] X[6]/Y[12] SERCOM1/ PAD[0] SERCOM2/ PAD[0] TC1/WO[0] TCC0/ WO[4] GCLK_IO[1] 9 / E3 I2C 13 Table 6-1. PORT Function Multiplexing (Continued) Pin A Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 SAMD10D SAMD10C 20-pin SAMD10D SOIC/ 14-pin 24-pin WLCSP SOIC QFN I/O Pin Supply 10 / D3 16 PA23 VDD B Type EIC REF ADC AC PTC I2C EXTINT[7] X[7]/Y[13] EXTINT[7] X[10] DAC C D E F G H SERCOM(1) SERCOMALT TC/TCC TCC COM GCLK SERCOM1/ PAD[1] SERCOM2/ PAD[1] TC1/WO[1] TCC0/ WO[5] GCLK_IO[2] 17 PA27 VDD 6 11 / E2 18 PA28 VDD 7 12 / D2 19 PA30 VDD EXTINT[2] SERCOM1/ PAD[0] SERCOM1/ PAD[2] TC2/WO[0] TCC0/ WO[2] CORTEX_ GCLK_IO[0] M0P/ SWCLK 8 13 / E1 20 PA31 VDD EXTINT[3] SERCOM1/ PAD[1] SERCOM1/ PAD[3] TC2/WO[1] TCC0/ WO[3] SWDIO(2) 9 14 / D1 21 PA24(3) VDD EXTINT[4] X[8]/Y[14] SERCOM1/ PAD[2] SERCOM2/ PAD[2] TCC0/WO[2] TCC0/ WO[4] 10 15 / C1 22 PA25(3) VDD EXTINT[5] X[9]/Y[15] SERCOM1/ PAD[3] SERCOM2/ PAD[3] TCC0/WO[3] Notes: 1. 2. 3. GCLK_IO[0] GCLK_IO[0] GCLK_IO[0] GCLK_IO[0] Refer to “Electrical Characteristics” on page 804 for details on the I2C pin characteristics.Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode This function is only activated in the presence of a debugger. If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and PA25 through input GPIO mode. The aim is to avoid an eventually extract power consumption ( 2.0V) 0x3 VREFA External reference 0x4 VREFB External reference 0x5-0xF Description 1.0V voltage reference Reserved Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 731 30.8.3 Average Control Name: AVGCTRL Offset: 0x02 Reset: 0x00 Access: Read-Write Property: Write-Protected Bit 7 6 5 4 3 ADJRES[2:0] 2 1 0 SAMPLENUM[3:0] Access R R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. This bit will always return zero when read. z Bits 6:4 – ADJRES[2:0]: Adjusting Result / Division Coefficient These bits define the division coefficient in 2n steps. z Bits 3:0 – SAMPLENUM[3:0]: Number of Samples to be Collected These bits define how many samples should be added together.The result will be available in the Result register (RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed. Table 30-8. Number of Samples to be Collected SAMPLENUM[3:0] Name 0x0 1 1 sample 0x1 2 2 samples 0x2 4 4 samples 0x3 8 8 samples 0x4 16 16 samples 0x5 32 32 samples 0x6 64 64 samples 0x7 128 128 samples 0x8 256 256 samples 0x9 512 512 samples 0xA 1024 1024 samples 0xB-0xF Description Reserved Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 732 30.8.4 Sampling Time Control Name: SAMPCTRL Offset: 0x03 Reset: 0x00 Access: Read-Write Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SAMPLEN[5:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:0 – SAMPLEN[5:0]: Sampling Time Length These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. Sampling time is set according to the equation: CLK ADC Sampling time = ( SAMPLEN + 1 ) ⋅ ⎛ ----------------------⎞ ⎝ ⎠ 2 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 733 30.8.5 Control B Name: CTRLB Offset: 0x04 Reset: 0x0000 Access: Read-Write Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PRESCALER[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CORREN FREERUN LEFTADJ DIFFMODE RESSEL[1:0] Access R R R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 15:11 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 10:8 – PRESCALER[2:0]: Prescaler Configuration These bits define the ADC clock relative to the peripheral clock according to Table 30-9. These bits can only be written while the ADC is disabled. Table 30-9. Prescaler Configuration PRESCALER[2:0] Name Description 0x0 DIV4 Peripheral clock divided by 4 0x1 DIV8 Peripheral clock divided by 8 0x2 DIV16 Peripheral clock divided by 16 0x3 DIV32 Peripheral clock divided by 32 0x4 DIV64 Peripheral clock divided by 64 0x5 DIV128 Peripheral clock divided by 128 0x6 DIV256 Peripheral clock divided by 256 0x7 DIV512 Peripheral clock divided by 512 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 5:4 – RESSEL[1:0]: Conversion Result Resolution These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution. These bits can be written only while the ADC is disabled. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 734 Table 30-10. Conversion Result Resolution z RESSEL[1:0] Name Description 0x0 12BIT 12-bit result 0x1 16BIT For averaging mode output 0x2 10BIT 10-bit result 0x3 8BIT 8-bit result Bit 3 – CORREN: Digital Correction Logic Enabled 0: Disable the digital result correction. 1: Enable the digital result correction. The ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. Conversion time will be increased by X cycles according to the value in the Offset Correction Value bit group in the Offset Correction register. This bit can be changed only while the ADC is disabled. z Bit 2 – FREERUN: Free Running Mode 0: The ADC run is single conversion mode. 1: The ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. This bit can be changed only while the ADC is disabled. z Bit 1 – LEFTADJ: Left-Adjusted Result 0: The ADC conversion result is right-adjusted in the RESULT register. 1: The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust the value in the RESULT register. This bit can be changed only while the ADC is disabled. z Bit 0 – DIFFMODE: Differential Mode 0: The ADC is running in singled-ended mode. 1: The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. This bit can be changed only while the ADC is disabled. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 735 30.8.6 Window Monitor Control Name: WINCTRL Offset: 0x08 Reset: 0x00 Access: Read-Write Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 WINMODE[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 2:0 – WINMODE[2:0]: Window Monitor Mode These bits enable and define the window monitor mode. Table 30-11 shows the mode selections. Table 30-11. Window Monitor Mode WINMODE[2:0] Name 0x0 DISABLE No window mode (default) 0x1 MODE1 Mode 1: RESULT > WINLT 0x2 MODE2 Mode 2: RESULT < WINUT 0x3 MODE3 Mode 3: WINLT < RESULT < WINUT 0x4 MODE4 Mode 4: !(WINLT < RESULT < WINUT) 0x5-0x7 Description Reserved Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 736 30.8.7 Software Trigger Name: SWTRIG Offset: 0x0C Reset: 0x00 Access: Read-Write Property: Write-Protected, Write-Synchronized Bit 7 6 5 4 3 2 1 0 START FLUSH Access R R R R R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 – START: ADC Start Conversion 0: The ADC will not start a conversion. 1: The ADC will start a conversion. The bit is cleared by hardware when the conversion has started. Setting this bit when it is already set has no effect. Writing this bit to zero will have no effect. z Bit 0 – FLUSH: ADC Conversion Flush 0: No flush action. 1: The ADC pipeline will be flushed. A flush will restart the ADC clock on the next peripheral clock edge, and all conversions in progress will be aborted and lost. This bit is cleared until the ADC has been flushed. After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a new conversion. Writing this bit to zero will have no effect. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 737 30.8.8 Input Control Name: INPUTCTRL Offset: 0x10 Reset: 0x00000000 Access: Read-Write Property: Write-Protected, Write-Synchronized Bit 31 30 29 28 27 26 25 24 GAIN[3:0] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 INPUTOFFSET[3:0] Access INPUTSCAN[3:0] R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 MUXNEG[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MUXPOS[4:0] Access R R R R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 31:28 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 27:24 – GAIN[3:0]: Gain Factor Selection These bits set the gain factor of the ADC gain stage according to the values shown in Table 30-12. Table 30-12. Gain Factor Selection GAIN[3:0] Name Description 0x0 1X 1x 0x1 2X 2x 0x2 4X 4x 0x3 8X 8x Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 738 GAIN[3:0] Name 0x4 16X 0x5-0xe 0xF z Description 16x Reserved DIV2 1/2x Bits 23:20 – INPUTOFFSET[3:0]: Positive Mux Setting Offset The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the first conversion triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET. Setting this register to zero causes the first conversion to use a positive input equal to MUXPOS. After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion to be done with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and INPUTOFFSET gives the input that is actually converted. z Bits 19:16 – INPUTSCAN[3:0]: Number of Input Channels Included in Scan This register gives the number of input sources included in the pin scan. The number of input sources included is INPUTSCAN + 1. The input channels included are in the range from MUXPOS + INPUTOFFSET to MUXPOS + INPUTOFFSET + INPUTSCAN. The range of the scan mode must not exceed the number of input channels available on the device. z Bits 15:13 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 12:8 – MUXNEG[4:0]: Negative Mux Input Selection These bits define the Mux selection for the negative ADC input. Table 30-13 shows the possible input selections. Table 30-13. Negative Mux Input Selection MUXNEG[4:0] Name Description 0x00 PIN0 ADC AIN0 pin 0x01 PIN1 ADC AIN1 pin 0x02 PIN2 ADC AIN2 pin 0x03 PIN3 ADC AIN3 pin 0x04 PIN4 ADC AIN4 pin 0x05 PIN5 ADC AIN5 pin 0x06 PIN6 ADC AIN6 pin 0x07 PIN7 ADC AIN7 pin 0x08 - 0x17 Reserved 0x18 GND Internal ground 0x19 IOGND I/O ground 0x1A - 0x1F z Reserved Bits 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 739 z Bits 4:0 – MUXPOS[4:0]: Positive Mux Input Selection These bits define the Mux selection for the positive ADC input. Table 30-14 shows the possible input selections. If the internal bandgap voltage or temperature sensor input channel is selected, then the Sampling Time Length bit group in the Sampling Control register must be written with a corresponding value. Table 30-14. Positive Mux Input Selection MUXPOS[4:0] Group configuration Description 0x00 PIN0 ADC AIN0 pin 0x01 PIN1 ADC AIN1 pin 0x02 PIN2 ADC AIN2 pin 0x03 PIN3 ADC AIN3 pin 0x04 PIN4 ADC AIN4 pin 0x05 PIN5 ADC AIN5 pin 0x06 PIN6 ADC AIN6 pin 0x07 PIN7 ADC AIN7 pin 0x08 PIN8 ADC AIN8 pin 0x09 PIN9 ADC AIN9 pin 0x0A-0x17 Reserved 0x18 TEMP Temperature reference 0x19 BANDGAP Bandgap voltage 0x1A SCALEDCOREVCC 1/4 scaled core supply 0x1B SCALEDIOVCC 1/4 scaled I/O supply 0x1C DAC DAC output 0x1D-0x1F Reserved Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 740 30.8.9 Event Control Name: EVCTRL Offset: 0x14 Reset: 0x00 Access: Read-Write Property: Write-Protected Bit 7 6 5 4 WINMONEO RESRDYEO 3 2 1 0 SYNCEI STARTEI Access R R R/W R/W R R R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 5 – WINMONEO: Window Monitor Event Out This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated when the window monitor detects something. 0: Window Monitor event output is disabled and an event will not be generated. 1: Window Monitor event output is enabled and an event will be generated. z Bit 4 – RESRDYEO: Result Ready Event Out This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated when the conversion result is available. 0: Result Ready event output is disabled and an event will not be generated. 1: Result Ready event output is enabled and an event will be generated. z Bits 3:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 1 – SYNCEI: Synchronization Event In 0: A flush and new conversion will not be triggered on any incoming event. 1: A flush and new conversion will be triggered on any incoming event. z Bit 0 – STARTEI: Start Conversion Event In 0: A new conversion will not be triggered on any incoming event. 1: A new conversion will be triggered on any incoming event. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 741 30.8.10 Interrupt Enable Clear Name: INTENCLR Offset: 0x16 Reset: 0x00 Access: Read-Write Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding interrupt request. z Bit 2 – WINMON: Window Monitor Interrupt Enable 0: The window monitor interrupt is disabled. 1: The window monitor interrupt is enabled, and an interrupt request will be generated when the Window Monitor interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt request. z Bit 1 – OVERRUN: Overrun Interrupt Enable 0: The Overrun interrupt is disabled. 1: The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request. z Bit 0 – RESRDY: Result Ready Interrupt Enable 0: The Result Ready interrupt is disabled. 1: The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result Ready interrupt flag is set. Writing a zero to this bit has no effect. Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt request. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 742 30.8.11 Interrupt Enable Set Name: INTENSET Offset: 0x17 Reset: 0x00 Access: Read-Write Property: Write-Protected Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable 0: The Synchronization Ready interrupt is disabled. 1: The Synchronization Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the Synchronization Ready interrupt. z Bit 2 – WINMON: Window Monitor Interrupt Enable 0: The Window Monitor interrupt is disabled. 1: The Window Monitor interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt. z Bit 1 – OVERRUN: Overrun Interrupt Enable 0: The Overrun interrupt is disabled. 1: The Overrun interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt. z Bit 0 – RESRDY: Result Ready Interrupt Enable 0: The Result Ready interrupt is disabled. 1: The Result Ready interrupt is enabled. Writing a zero to this bit has no effect. Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 743 30.8.12 Interrupt Flag Status and Clear Name: INTFLAG Offset: 0x18 Reset: 0x00 Access: Read-Write Property: - Bit 7 6 5 4 3 2 1 0 SYNCRDY WINMON OVERRUN RESRDY Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 z Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bit 3 – SYNCRDY: Synchronization Ready This flag is cleared by writing a one to the flag. This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), except when caused by an enable or software reset, and will generate an interrupt request if INTENCLR/SET.SYNCRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Synchronization Ready interrupt flag. z Bit 2 – WINMON: Window Monitor This flag is cleared by writing a one to the flag or by reading the RESULT register. This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an interrupt request will be generated if INTENCLR/SET.WINMON is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Window Monitor interrupt flag. z Bit 1 – OVERRUN: Overrun This flag is cleared by writing a one to the flag. This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be generated if INTENCLR/SET.OVERRUN is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Overrun interrupt flag. z Bit 0 – RESRDY: Result Ready This flag is cleared by writing a one to the flag or by reading the RESULT register. This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/SET.RESRDY is one. Writing a zero to this bit has no effect. Writing a one to this bit clears the Result Ready interrupt flag. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 744 30.8.13 Status Name: STATUS Offset: 0x19 Reset: 0x00 Access: Read-Only Property: - Bit 7 6 5 4 3 2 1 0 SYNCBUSY Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bit 7 – SYNCBUSY: Synchronization Busy This bit is cleared when the synchronization of registers between the clock domains is complete. This bit is set when the synchronization of registers between clock domains is started. z Bits 6:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 745 30.8.14 Result Name: RESULT Offset: 0x1A Reset: 0x0000 Access: Read-Only Property: Read-Synchronized Bit 15 14 13 12 11 10 9 8 RESULT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RESULT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 z Bits 15:0 – RESULT[15:0]: Result Conversion Value These bits will hold up to a 16-bit ADC result, depending on the configuration. In single-ended without averaging mode, the ADC conversion will produce a 12-bit result, which can be left- or right-shifted, depending on the setting of CTRLB.LEFTADJ. If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8], while the remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit result is required; i.e., one can read only the high byte of the entire 16-bit register. If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be available in bit locations [11:0], and the result is then 12 bits long. If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the Average Control register (AVGCTRL). Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 746 30.8.15 Window Monitor Lower Threshold Name: WINLT Offset: 0x1C Reset: 0x0000 Access: Read-Write Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 WINLT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINLT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – WINLT[15:0]: Window Lower Threshold If the window monitor is enabled, these bits define the lower threshold value. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 747 30.8.16 Window Monitor Upper Threshold Name: WINUT Offset: 0x20 Reset: 0x0000 Access: Read-Write Property: Write-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 WINUT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINUT[7:0] Access Reset z R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:0 – WINUT[15:0]: Window Upper Threshold If the window monitor is enabled, these bits define the upper threshold value. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 748 30.8.17 Gain Correction Name: GAINCORR Offset: 0x24 Reset: 0x0000 Access: Read-Write Property: Write-Protected Bit 15 14 13 12 11 10 9 8 GAINCORR[11:8] Access R R R R R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GAINCORR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 z Bits 15:12 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. These bits will always return zero when read. z Bits 11:0 – GAINCORR[11:0]: Gain Correction Value If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for gain error before being written to the result register. The gaincorrection is a fractional value, a 1-bit integer plusan 11-bit fraction, and therefore 1/2 1.6V, IOL maxI - 0.1*VDD 0.2*VDD VDD>1.6V, IOH maxI 0.8*VDD 0.9*VDD - VDD=1.62V-3V, PORT.PINCFG.DRVSTR=0 - - 1 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=0 - - 2.5 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=1 - - 3 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=1 - - 10 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=0 - - 0.7 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=0 - - 2 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=1 - - 2 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=1 - - 7 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, Vdd = 3.3V - 15 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, Vdd = 3.3V - 15 +/-0.015 1 Pull-up resistors disabled V mA nS -1 µA These values are based on simulation. These values are not covered by test limits in production or characterization. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 812 34.8.2 I2C Pins Refer to “I/O Multiplexing and Considerations” on page 13 to get the list of I2C pins. Table 34-11. I2C Pins Characteristics in I2C configuration Symbol Parameter Condition RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VHYS Hysteresis of Schmitt trigger inputs VOL Output low-level voltage CI Capacitance for each I/O Pin IOL SCL clock frequency RP Value of pull-up resistor Typ. Max. Units 20 40 60 kΩ VDD=1.62V-2.7VI - - 0.25*VDD VDD=2.7V-3.63V - - 0.3*VDD VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63VI 0.55*VDD - - 0.08*VDD - - VDD> 2.0VI, IOL=3mA - - 0.4 VDD≤2.0V IOL=2mA - - 0.2*VDD I V pF I Output low-level current fSCL Min. VOL =0.4V Standard, Fast and HS Modes 3 - - VOL =0.4V Fast Mode+ 20 - - VOL =0.6V 6 - - I - - 3.4 mA fSCL ≤ 100kHz MHz Ω fSCL > 100kHz I2C pins timing characteristics can be found in “SERCOM in I2C Mode Timing” on page 842. Table 34-12. I2C Pins Characteristics in I/O Configuration Symbol Parameter RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage Conditions Min. Typ. Max. Units 20 40 60 kΩ VDD=1.62V-2.7V - - 0.25*VDD VDD=2.7V-3.63V - - 0.3*VDD VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63V 0.55*VDD - - VDD>1.6V, IOL maxI - 0.1*VDD 0.2*VDD VDD>1.6V, IOH maxI 0.8*VDD 0.9*VDD - I V Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 813 Symbol IOL Parameter Output low-level current IOH Output high-level current Rise time(1) tRISE Fall time(1) tFALL ILEAK Input leakage current Note: 1. Conditions Min. Typ. Max. VDD=1.62V-3V, PORT.PINCFG.DRVSTR=0 - - 1 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=0 - - 2.5 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=1 - - 3 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=1 - - 10 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=0 - - 0.7 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=0 - - 2 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=1 - - 2 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=1 - - 7 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, VDD = 3.3V - 15 +/-0.015 1 Pull-up resistors disabled Units mA nS -1 µA These values are based on simulation. These values are not covered by test limits in production or characterization. 34.8.3 XOSC Pin XOSC pins behave as normal pins when used as normal I/Os. Refer to Table 34-10. 34.8.4 XOSC32 Pin XOSC32 pins behave as normal pins when used as normal I/Os. Refer to Table 34-10. 34.8.5 External Reset Pin Reset pin has the same electrical characteristics as normal I/O pins. Refer to Table 34-10. 34.9 Injection Current Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 814 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 34-13. Injection Current(1) Symbol Parameter Min. Max. Iinj1(2) IO pin injection current -1 +1 Tinj2(3) IO pin injection current -15 +15 Iinjtotal Sum of IO pins injection current -45 +45 Notes: 1. 2. Units mA Injecting current may have an effect on the accuracy of Analog blocks Conditions for Vpin: Vpin < GND-0.3V or 3.6V < Vpin ≤ 4.2V Conditions for VDD: 3V < VDD ≤ 3.6V. If Vpin is lower than GND-0.6V, then a current limiting resistor is required. The negative DC injection current limiting resistor R is calculated as R = |(GND-0.6V . Vpin)/Iinj1|. If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting resistor R is calculated as R = (Vpin-(VDD+0.6V))/Iinj1 3. Conditions for Vpin: Vpin < GND-0.6V or Vpin ≤ 3.6V. Conditions for VDD: VDD ≤ 3V. If Vpin is lower than GND-0.6V, a current limiting resistor is required. The negative DC injection current limiting resistor R is calculated as R = |(GND-0.6V . Vpin)/Iinj2|. If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting resistor R is calculated as R = (Vpin-(VDD+0.6V))/Iinj2. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 815 34.10 Analog Characteristics 34.10.1 Voltage Regulator Characteristics Table 34-14. Decoupling requirements Symbol Parameter Conditions Input regulator capacitor, between VDDIN and GND CIN Note: Min. Typ. Max. Units - 4.7 - µF I Supplying any external components using VDDCORE pin is not allowed to assure the integrity of the core supply voltage. 34.10.2 Power-On Reset (POR) Characteristics Table 34-15. POR Characteristics Symbol Parameter Conditions VPOT+ Voltage threshold on VDDIN rising I Voltage threshold on VDDIN falling Typ. Max. 1.27 1.43 1.58 0.72 1.02 1.32 Units V VDD Figure 34-2. POR Operating Principle VPOT+ VPOT- Time Reset VPOT- VDD falls at 1V/ms or slower Min. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 816 34.10.3 Brown-Out Detectors Characteristics 34.10.3.1 BOD33 Figure 34-3. BOD33 Hysteresis OFF VCC VBOD RESET Figure 34-4. BOD33 Hysteresis ON VCC VBOD+ VBOD- RESET Table 34-16. BOD33 LEVEL Value Symbol BOD33.LEVEL Conditions Min. Typ. Max. - 1.67 1.71 - 1.70 1.75 - 2.81 2.83 48 - 3.09 3.20 6 1.61 1.64 1.65 1.64 1.67 1.69 2.72 2.76 2.79 3.00 3.07 3.10 6 7 VBOD+ 39 VBODor VBOD 7 39 Hysteresis ON Hysteresis ON or Hysteresis OFF 48 Note: See chapter Memories table “NVM Units V User Row Mapping” on page 23 for the BOD33 default value settings. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 817 Table 34-17. BOD33 Characteristics Symbol Parameter Conditions Min. Typ. Max. - 34 - 35 - 100 Step size, between adjacent values in BOD33.LEVEL I VHYST VBOD+ - VBOD- Hysteresis ON tDET Detection time Time with VDDANA < VTH necessary to generate a reset signal - 0.9(1) - tSTARTUP Startup time I - 2.2(1) - I Note: 1. Units mV µs These values are based on simulation. These values are not covered by test limits in production or characterization. Table 34-18. BOD33 Mode Characteristics Symbol Parameter Conditions IDLE2, Continuous mode IBOD33 Current consumption IDLE2, Sampling mode STDBY, Sampling mode TA VCC 25°C Typ. Max. 25 48 - 50 0.034 0.21 - 1.62 0.132 0.38 - 1 3.3V -40 to 85°C 25°C 1.8V -40 to 85°C 25°C 3.3V -40 to 85°C Units µA 34.10.4 Analog-to-Digital (ADC) Characteristics Table 34-19. Operating Conditions Symbol Parameter RES Resolution ADC Clock frequency fCLK_ADC Conditions Min. Typ. Max. Units I 8 - 12 bits I 30 - 2100 kHz Conversion speed Sample rate(1) 10 Single shot 5 - 300 Free running 5 - 350(3) 0.5 - - cycles 6 - - cycles Sampling time(1) Conversion time(1) 1000 1x Gain ksps VREF Voltage reference range 1.0 - VDDANA-0.6 V VREFINT1V Internal 1V reference (2) - 1.0 - V Internal ratiometric reference 0(2) - VDDANA/1.48 - V VREFINTVCC0 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 818 Table 34-19. Operating Conditions (Continued) Symbol VREFINTVCC0 Voltage Error VREFINTVCC1 VREFINTVCC1 Voltage Error Parameter Conditions Min. Typ. Max. Units Internal ratiometric reference 0(2) error 2.0V 0.2*VDDANA - 0.1V 4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*Vref/GAIN) Table 34-21. Single-Ended Mode Symbol ENOB Parameter Conditions Min. Typ. Max. Units Effective Number of Bits With gain compensation 9.5 9.8 Bits TUE Total Unadjusted Error 1x gain 10.5 40.0 LSB INL Integral Non-Linearity 1x gain 1.0 1.6 10.0 LSB DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.98 LSB Gain Error Ext. Ref. 1x -5.0 0.7 +5.0 mV Ext. Ref. 0.5x +/-0.09 +/-0.59 +/-3.5 % Ext. Ref. 2x to 16X +/-0.03 +/-0.2 +/-4.0 % -5 2.0 10 mV 54.2 65.0 67.0 dB 47.5 59.5 61 dB 48 60.0 64 dB -74 -68.8 -62.1 dB - 1.0 - mV Gain Accuracy(3) Offset Error SFDR SINAD Spurious Free Dynamic Range Signal-to-Noise and Distortion SNR Signal-to-Noise Ratio THD Total Harmonic Distortion Noise RMS Notes: Ext. Ref. 1x 1x Gain FCLK_ADC = 2.1MHz FIN = 40kHz AIN = 95%FSR T = 25°C 1. 2. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN: z VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V z VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V 3. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (VREF/GAIN) Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 820 34.10.4.1 Performance with the Averaging Digital Feature Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-tobe-collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT). Table 34-22. Averaging feature Average Number Conditions 1 8 32 In differential mode, 1x gain, VDDANA=3.0V, VREF=1.0V, 350kSps T= 25°C 128 SNR (dB) SINAD (dB) SFDR (dB) ENOB (bits) 66.0 65.0 72.8 9.75 67.6 65.8 75.1 10.62 69.7 67.1 75.3 10.85 70.4 67.5 75.5 10.91 34.10.4.2 Performance with the hardware offset and gain correction Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register (GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result register (RESULT). Table 34-23. Offset and Gain correction feature Gain Factor Conditions Offset Error (mV) Gain Error (mV) Total Unadjusted Error (LSB) 0.25 1.0 2.4 0.20 0.10 1.5 0.15 -0.15 2.7 -0.05 0.05 3.2 0.10 -0.05 6.1 0.5x 1x 2x 8x In differential mode, 1x gain, VDDANA=3.0V, VREF=1.0V, 350ksps T= 25°C 16x 34.10.4.3 Inputs and Sample and Hold Acquisition Times The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor ( R SAMPLE ) and a capacitor ( CSAMPLE ). In addition, the source resistance ( R SOURCE ) must be taken into account when calculating the required sample and hold time. Figure 34-5 shows the ADC input channel equivalent circuit. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 821 Figure 34-5. ADC Input VDDIN/2 Analog Input AINx CSAMPLE RSOURCE RSAMPLE VIN To achieve n bits of accuracy, the V CSAMPLE ≥ V IN × ( 1 – 2 –( n + 1 ) C SAMPLE capacitor must be charged at least to a voltage of ) The minimum sampling time t SAMPLEHOLD for a given R SOURCE can be found using this formula: t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × ( n + 1 ) × ln ( 2 ) for a 12 bits accuracy: t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × 9.02 where 1 t SAMPLEHOLD = -------------------2 × f ADC 34.10.5 Digital to Analog Converter (DAC) Characteristics Table 34-24. Operating Conditions(1) Symbol Parameter VDDANA Analog supply voltage AVREF External reference voltage Conditions Min. Typ. Max. Units I 1.62 - 3.63 V I 1.0 - VDDANA-0.6 V Internal reference voltage 1 - 1 - V Internal reference voltage 2 - VDDANA - V 0.05 - VDDANA-0.05 V I Linear output voltage range I Minimum resistive load I 5 - - kΩ I Maximum capacitance load I - - 100 pF Voltage pump disabled - 184 230 µA IDD DC supply current(2) Notes: 1. 2. I These values are based on specifications otherwise noted. These values are based on characterization. These values are not covered by test limits in production. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 822 Table 34-25. Clock and Timing(1) Symbol Parameter Conditions Startup time Note: 1. Typ. Max. Normal mode - - 350 For ΔDATA=+/-1 - - 1000 VDDNA > 2.6V - - 2.85 µs VDDNA < 2.6V - - 10 µs Cload=100pF Rload > 5kΩ Conversion rate I Min. Units ksps These values are based on simulation. These values are not covered by test limits in production or characterization. Table 34-26. Accuracy Characteristics(1) Symbol RES Parameter Conditions Input resolution Integral non-linearity VREF = VDDANA VREF= INT1V VREF= Ext 1.0V DNL Typ. I VREF= Ext 1.0V INL Min. Differential non-linearity VREF= VDDANA VREF= INT1V Max. Units 10 Bits VDD = 1.6V 0.4 0.5 1.5 VDD = 3.6V 0.6 0.7 1.5 VDD = 1.6V 1.4 1.5 2.5 VDD = 3.6V 0.7 0.8 1.5 VDD = 1.6V 0.4 0.5 1.5 VDD = 3.6V 0.3 0.4 1.5 VDD = 1.6V +/-0.2 +/-0.5 +/-1.5 VDD = 3.6V +/-0.4 +/-0.6 +/-1.2 VDD = 1.6V +/-1.1 +/-1.3 +/-1.5 VDD = 3.6V +/-1.0 +/-1.1 +/-1.2 VDD = 1.6V +/-0.2 +/-0.6 +/-1.5 VDD = 3.6V +/-0.3 +/-0.6 +/-1.6 LSB LSB I Gain error Ext. VREF +/-1.5 +/-4.0 +/-10 mV I Offset error Ext. VREF +/-1.0 +/-2 +/-6 mV Min. Typ. Max. Note: 1. All values measured using a conversion rate of 350ksps. 34.10.6 Analog Comparator Characteristics Table 34-27. Electrical and Timing Symbol Parameter Conditions I Positive input voltage range I 0 - VDDANA I Negative input voltage range I 0 - VDDANA Units V Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 823 Table 34-27. Electrical and Timing (Continued) Symbol Parameter Offset I Hysteresis Conditions Min. Typ. Max. Hysteresis = 0, Fast mode -15 0.0 15 Hysteresis = 0, Low power mode -25 0.0 25 Hysteresis = 1, Fast mode 20 50 85 Hysteresis = 1, Low power mode 15 40 75 90 180 Changes for VACM=VDDANA/2 100mV overdrive, Fast mode Propagation delay tSTARTUP 520 Enable to ready delay Fast mode 1 2.6 Enable to ready delay Low power mode 14 22 -1.4 0.75 1.4 DNL -0.9 0.25 0.9 Offset Error (1)(2) -0.2 0.260 0.92 Gain Error (1)(2) -0.89 0.215 0.89 Conditions Min. Typ. Max. Over voltage and [-40°C, +85°C] 1.08 1.1 1.12 Over voltage at 25°C 1.07 1.1 1.11 INL(3) (3) VSCALE Notes: 1. 2. 3. mV ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode 282 Startup time Units µs LSB According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64 Data computed with the Best Fit method Data computed using histogram 34.10.7 Bandgap Reference Characteristics Table 34-28. Internal 1.1V Bandgap reference characteristics Symbol Parameter INT1V Internal 1.1V Bandgap reference Units V Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 824 34.10.8 Temperature Sensor Characteristics 34.10.8.1 Temperature Sensor Characteristics Table 34-29. Temperature Sensor Characteristics(1) Symbol I Parameter Conditions Temperature sensor output voltage I Temperature sensor slope I Variation over VDDANA voltage Temperature Sensor accuracy Note: 1. 2. Min. T= 25°C, VDDANA = 3.3V Typ. Max. 0.688 Units V 2.06 2.16 2.26 mV/°C VDDANA=1.62V to 3.6V -0.4 1.4 3.0 mV/V Using the method described in Section 34.10.8.2 -10 - 10 °C These values are based on characterization. These values are not covered by test limits in production. See also rev C errata concerning the temperature sensor. 34.10.8.2 Software-based Refinement of the Actual Temperature The temperature sensor behavior is linear but it depends on several parameters such as the internal voltage reference which itself depends on the temperature. To take this into account, each device contains a Temperature Log row with data measured and written during the production tests. These calibration values should be read by software to infer the most accurate temperature readings possible. This Software Temperature Log row can be read at address 0x00806030. The Software Temperature Log row cannot be written. This section specifies the Temperature Log row content and explains how to refine the temperature sensor output using the values in the Temperature Log row. Temperature Log Row All values in this row were measured in the following conditions: z VDDIN = VDDIO = VDDANA = 3.3V z ADC Clock frequency = 1.0MHz z ADC sample rate: 125ksps z ADC sampling time: 57µs z ADC mode: Free running mode, ADC averaging mode with 4 averaged samples z Data computed on the average of 10 ADC conversions z ADC voltage reference= 1.0V internal reference (INT1V) z ADC input = temperature sensor Table 34-30. Temperature Log Row Content Bit Position Name Description 07:00 ROOM_TEMP_VAL_INT Integer part of room temperature in °C 11:08 ROOM_TEMP_VAL_DEC Decimal part of room temperature 19:12 HOT_TEMP_VAL_INT Integer part of hot temperature in °C 23:20 HOT_TEMP_VAL_DEC Decimal part of hot temperature Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 825 Table 34-30. Temperature Log Row Content (Continued) Bit Position Name Description 31:24:00 ROOM_INT1V_VAL 2’s complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) 39:32:00 HOT_INT1V_VAL 2’s complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) 51:40:00 ROOM_ADC_VAL 12bit ADC conversion at room temperature 63:52:00 HOT_ADC_VAL 12bit ADC conversion at hot temperature The temperature sensor values are logged during test production flow for Room and Hot insertions: z ROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contains the measured temperature at room insertion (e.g. for ROOM_TEMP_VAL_INT=25 and ROOM_TEMP_VAL_DEC=2, the measured temperature at room insertion is 25.2°C). z HOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contains the measured temperature at hot insertion (e.g. for HOT_TEMP_VAL_INT=83 and HOT_TEMP_VAL_DEC=3, the measured temperature at room insertion is 83.3°C). The temperature log row also contains the corresponding 12bit ADC conversions of both Room and Hot temperatures: z ROOM_ADC_VAL contains the 12bit ADC value corresponding to (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) z HOT_ADC_VAL contains the 12bit ADC value corresponding to (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) The temperature log row also contains the corresponding 1V internal reference of both Room and Hot temperatures: z ROOM_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) z HOT_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) z ROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In other words, the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1, -127] corresponds to [1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges. Using Linear Interpolation For concise equations, we’ll use the following notations: z (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) is denoted tempR z (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) is denoted tempH z ROOM_ADC_VAL is denoted ADCR, its conversion to Volt is denoted VADCR z HOT_ADC_VAL is denoted ADCH, its conversion to Volt is denoted VADCH z ROOM_INT1V_VAL is denoted INT1VR z HOT_INT1V_VAL is denoted INT1VH Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 826 Using the (tempR, ADCR) and (tempH, ADCH) points, using a linear interpolation we have the following equation: V ADC – V ADCR⎞ V ADCH – V ADCR⎞ ⎛ ---------------------------------- = ⎛ -------------------------------------⎝ temp – temp R ⎠ ⎝ temp H – temp R ⎠ Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as: [Equation 1] temp C INT1V ⎫ ⎧⎛ 1 -⎞ – ⎛ ADC R ⋅ --------------------R-⎞ ⎬ ⋅ ( temp H – temp R ) ⎨ ⎝ ADC m ⋅ -------------------12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ = temp R + ---------------------------------------------------------------------------------------------------------------------------------------------------------INT1V H ⎞ ⎛ INT1V ⎫ ⎧⎛ - – ADC R ⋅ --------------------R-⎞ ⎬ ⎨ ⎝ ADC H ⋅ -------------------12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ Note 1: in the previous expression, we’ve added the conversion of the ADC register value to be expressed in V Note 2: this is a coarse value because we assume INT1V=1V for this ADC conversion. Using the (tempR, INT1VR) and (tempH, INT1VH) points, using a linear interpolation we have the following equation: INT1V – INT1V R⎞ INT1V H – INT1V R⎞ ⎛ ------------------------------------------ = ⎛ ---------------------------------------------⎝ temp – temp R ⎠ ⎝ temp H – temp R ⎠ Then using the coarse temperature value, we can infer a closer to reality INT1V value during the ADC conversion as: ( INT1V H – INT1V R ) ⋅ ( temp C – temp R ) INT1V m = INT1V R + ⎛ --------------------------------------------------------------------------------------------------⎞ ⎝ ⎠ ( temp H – temp R ) Back to [Equation 1], we replace INT1V=1V by INT1V = INT1Vm, we can then deduce a finer temperature value as: [Equation 1bis] INT1V m ⎞ ⎛ INT1V ⎫ ⎧⎛ - – ADC R ⋅ --------------------R-⎞ ⎬ ⋅ ( temp H – temp R ) ⎨ ⎝ ADC m ⋅ -------------------12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ temp f = temp R + ---------------------------------------------------------------------------------------------------------------------------------------------------------INT1V H ⎞ ⎛ INT1V ⎫ ⎧⎛ - – ADC R ⋅ --------------------R-⎞ ⎬ ⎨ ⎝ ADC H ⋅ -------------------12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 827 34.11 NVM Characteristics Table 34-31. Maximum Operating Frequency VDD range NVM Wait States 1.62V to 2.7V 2.7V to 3.63V Maximum Operating Frequency 0 14 1 28 2 42 3 48 0 24 1 67 Units MHz Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is reached, a row erase is mandatory. Table 34-32. Flash Endurance and Data Retention Symbol Parameter Conditions Min. Typ. Max. Units RetNVM25k Retention after up to 25k Average ambient 55°C 10 50 - Years RetNVM2.5k Retention after up to 2.5k Average ambient 55°C 20 100 - Years RetNVM100 Retention after up to 100 Average ambient 55°C 25 >100 - Years CycNVM Cycling Endurance(1) -40°C < Ta < 85°C 25k 150k - Cycles Min. Typ. Max. Units Note: 1. An endurance cycle is a write and an erase operation. Table 34-33. EEPROM Emulation(1) Endurance and Data Retention Symbol Parameter Conditions RetEEPROM100k Retention after up to 100k Average ambient 55°C 10 50 - Years RetEEPROM10k Retention after up to 10k Average ambient 55°C 20 100 - Years 100k 600k - Cycles Min. Typ. Max. Units CycEEPROM Cycling Endurance Notes: 1. 2. (2) -40°C < Ta < 85°C The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle is a write and an erase operation. Table 34-34. NVM Characteristics Symbol Parameter Conditions tFPP Page programming time - - - 2.5 ms tFRE Row erase time I - - - 6 ms tFCE DSU chip erase time (CHIP_ERASE) - - - 240 ms Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 828 Table 34-35. Flash Erase and Programming Current Symbol Parameter IDDNVM Maximum current (peak) during whole programming or erase operation Min. Typ. Max. Units - 10 - mA Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 829 34.12 Oscillators Characteristics 34.12.1 Crystal Oscillator (XOSC) Characteristics 34.12.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 34-36. Digital Clock Characteristics Symbol fCPXIN Parameter Conditions XIN clock frequency Min. Typ. Max. Units - - 32 MHz Digital mode 34.12.1.2 Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure 34-6. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: C LEXT = 2 ( C L – C STRAY – C SHUNT ) where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal. Table 34-37. Crystal Oscillator Characteristics Symbol fOUT ESR CXIN Parameter Crystal oscillator frequency Crystal Equivalent Series Resistance Safety Factor = 3 Conditions Min. Typ. Max. Units 0.4 - 32 MHz f = 0.455MHz, CL = 100pF XOSC.GAIN = 0 - - 5.6K f = 2MHz, CL = 20pF XOSC.GAIN = 0 - - 416 f = 4MHz, CL = 20pF XOSC.GAIN = 1 - - 243 f = 8MHz, CL = 20pF XOSC.GAIN = 2 - - 138 f = 16MHz, CL = 20pF XOSC.GAIN = 3 - - 66 f = 32MHz, CL = 18pF XOSC.GAIN = 4 - - 56 - 6.5 - pF - 4.3 - pF I Parasitic capacitor load Ω I CXOUT Parasitic capacitor load Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 830 Table 34-37. Crystal Oscillator Characteristics (Continued) Symbol IXOSC Parameter Conditions Current Consumption tSTARTUP Startup time Min. Typ. Max. f = 2MHz, CL = 20pF, AGC off 65 85 f = 2MHz, CL = 20pF, AGC on 52 73 f = 4MHz, CL = 20pF, AGC off 117 150 f = 4MHz, CL = 20pF, AGC on 74 100 f = 8MHz, CL = 20pF, AGC off 226 296 f = 8MHz, CL = 20pF, AGC on 128 172 f = 16MHz, CL = 20pF, AGC off 502 687 f = 16MHz, CL = 20pF, AGC on 307 552 f = 32MHz, CL = 18pF, AGC off 1622 2200 f = 32MHz, CL = 18pF, AGC on 615 1200 f = 2MHz, CL = 20pF, XOSC.GAIN = 0, ESR = 600Ω 14K 48K f = 4MHz, CL = 20pF, XOSC.GAIN = 1, ESR = 100Ω 6800 19.5K f = 8MHz, CL = 20pF, XOSC.GAIN = 2, ESR = 35Ω 5550 13K f = 16MHz, CL = 20pF, XOSC.GAIN = 3, ESR = 25Ω 6750 14.5K f = 32MHz, CL = 18pF, XOSC.GAIN = 4, ESR = 40Ω 5.3K 9.6K Units µA cycles Figure 34-6. Oscillator Connection Xin C LEXT Crystal LM C SHUNT RM C STRAY CM Xout C LEXT Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 831 34.12.2 External 32kHz Crystal Oscillator (XOSC32K) Characteristics 34.12.2.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 34-38. Digital Clock Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fCPXIN32 XIN32 clock frequency Digital mode - 32.768 - kHz I XIN32 clock duty cycle I Digital mode - 50 - % 34.12.2.2 Crystal Oscillator Characteristics Figure 34-6 and the equation in “Crystal Oscillator Characteristics” on page 830 also applies to the 32kHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. Table 34-39. 32kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fOUT Crystal oscillator frequency I - 32768 tSTARTUP Startup time ESRXTAL = 39.9kΩ, CL = 12.5pF - 28K 30K CL Crystal load capacitance I - - 12.5 CSHUNT Crystal shunt capacitance I - 0.1 CXIN32 Parasitic capacitor load - 6.5 CXOUT32 Parasitic capacitor load - 4.3 IXOSC32K Current consumption - 1.22 2.19 µA ESR Crystal equivalent series resistance f=32.768kHz Safety Factor = 3 - - 100 kΩ SOIC20/14 packages CL=12.5pF Hz cycles pF Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 832 34.12.3 Digital Frequency Locked Loop (DFLL48M) Characteristics Table 34-40. DFLL48M Characteristics - Open Loop Mode(1) Symbol Parameter Conditions Min. Typ. Max. Units DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 47 48 49 MHz - 403 453 µA 8 9 µs Min. Typ. Max. Units I fOUT Output frequency IDFLL Power consumption on VDDIN DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 Startup time DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 fOUT within 90% of final value I tSTARTUP Note: 1. DFLL48M in Open loop after calibration at room temperature. Table 34-41. DFLL48M Characteristics - Close Loop Mode(1) Symbol Parameter Conditions fOUT Average Output frequency fREF = 32.768kHz 47.76 48 48.24 MHz fREF Reference frequency I 0.732 32.768 33 kHz Jitter Cycle to Cycle jitter fREF = 32.768kHz - - 0.42 ns IDFLL Power consumption on VDDIN fREF = 32.768kHz - 403 453 µA Lock time fREF = 32.768kHz DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 200 500 µs tLOCK Note: 1. To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy. 34.12.4 32.768kHz Internal oscillator (OSC32K) Characteristics Table 34-42. 32kHz RC Oscillator Characteristics Symbol fOUT Parameter Output frequency Conditions Min. Typ. Max. Calibrated against a 32.768kHz reference at 25°C, over [-40, +85]°C, over [1.62, 3.63]V 30.3 32.768 34.2 Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 32.6 32.768 32.8 Calibrated against a 32.768kHz reference at 25°C, over [1.62, 3.63]V 32.4 32.768 33.1 Units kHz Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 833 Symbol Parameter Conditions Min. Typ. Max. Units IOSC32K Current consumption I 0.67 1.31 µA tSTARTUP Startup time I 1 2 cycle Duty Duty Cycle I 50 % 34.12.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics Table 34-43. Ultra Low Power Internal 32kHz RC Oscillator Characteristics Symbol fOUT Parameter Output frequency Duty Duty Cycle Conditions Min. Typ. Max. Calibrated against a 32.768kHz reference at 25°C, over [-40, +85]C, over [1.62, 3.63]V 27.8 32.768 37.8 Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 32.85 32.768 32.8 Calibrated against a 32.768kHz reference at 25°C, over [1.62, 3.63]V 31.9 32.768 33.1 50 I Units kHz % 34.12.6 Multi RC Oscillator (OSC8M) Characteristics Table 34-44. Multi RC Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max. Calibrated against a 8MHz reference at 25°C, over [-40, +85]C, over [1.62, 3.63]V 7.8 8 8.14 Calibrated against a 8MHz reference at 25°C, at VDD=3.3V 7.94 8 8.06 Calibrated against a 8MHz reference at 25°C, over [1.62, 3.63]V 7.92 8 8.08 Units I fOUT Output frequency TempCo Freq vs. temperature drift SupplyCo Freq vs supply drift IOSC8M Current consumption IDLEIDLE2 on OSC32K versus IDLE2 on calibrated OSC8M enabled at 8MHz (FRANGE=1, PRESC=0) tSTARTUP Startup time Duty Duty cycle MHz -2.3 1.6 % -1 1 % 64 96 µA I 2.4 3.3 µs I 50 % Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 834 34.12.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics Table 34-45. FDPLL96M Characteristics(1) Symbol Parameter Conditions Min. Typ. Max. Units fIN Input frequency 32 - 2000 KHz fOUT Output frequency 48 - 96 MHz IFDPLL96M Current consumption fIN= 32 kHz, fOUT= 48 MHz 400 700 fIN= 32 kHz, fOUT= 96 MHz 650 900 fIN= 32 kHz, fOUT= 48 MHz 1.5 2 fIN= 32 kHz, fOUT= 96 MHz 3.0 10 fIN= 2 MHz, fOUT= 48 MHz 1.3 2 fIN= 2 MHz, fOUT= 96 MHz 3.0 7 After startup, time to get lock signal. fIN= 32 kHz, fOUT= 96 MHz 1.3 2 ms fIN= 2 MHz, fOUT= 96 MHz 25 50 µs 50 60 % Jp Period jitter tLOCK Lock Time Duty Duty cycle Note: 1. 40 µA % All values have been characterized with FILTSEL[1/0] as default value. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 835 34.13 PTC Typical Characteristics Figure 34-7. Power consumption [µA]. 1 sensor, Frequency mode = None, CPU Clk = 48MHz, PTC Clk = 4MHz, VDD=3.3V 160 140 Average Current [μA] 120 10ms 100 50ms 100ms 80 200ms 60 40 20 0 1 2 4 8 16 32 64 Sample Averaging Figure 34-8. Power consumption [µA]. 1 sensor, Frequency mode = HOP, CPU Clk = 48MHz, PTC Clk = 2MHz, VDD=3.3V 200 180 rage Cu Average Current μA 160 140 10ms 120 50ms 100 100ms 80 200ms 200 60 40 20 0 1 2 4 8 16 32 64 Sample Averaging Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 836 Figure 34-9. Power consumption [µA]. 10 sensors, Frequency mode = None, CPU Clk = 48MHz, PTC Clk = 4MHz, VDD=3.3V 900 800 Average Current μA 700 10ms 600 50ms 500 100ms 400 200ms 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Figure 34-10.Power consumption [µA]. 10 sensors, Frequency mode = HOP, CPU Clk = 48MHz, PTC Clk = 2MHz, VDD=3.3V 900 800 Average Current μA 700 10ms 600 50ms 500 100ms 400 200ms 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 837 Figure 34-11.Power consumption [µA]. 50 sensors, Frequency mode = None, CPU Clk = 48MHz, PTC Clk = 4MHz, VDD=3.3V 1000 900 Average Current nt μA 800 700 50ms 600 100ms 500 200ms 400 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 838 Figure 34-12.Power consumption [µA]. 50 sensors, Frequency mode = HOP, CPU Clk = 48MHz, PTC Clk = 2MHz, VDD=3.3V 1000 900 Average Current rrent μ μA 800 700 50ms 600 100ms 500 200ms 400 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Figure 34-13.CPU utilization. 80 % 70 % 60 % 50 % Channel count 1 40 % Channel count 10 30 % Channel count 100 20 % 10 % 0% 10 50 100 200 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 839 34.14 Timing Characteristics 34.14.1 External Reset Table 34-46. External reset characteristics Symbol tEXT Parameter Condition Minimum reset pulse width I Min. Typ. Max. Units 10 - - ns 34.14.2 SERCOM in SPI Mode Timing Figure 34-14.SPI timing requirements in master mode SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 34-15.SPI timing requirements in slave mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data Input) tSIH MSB tSOSSS MISO (Data Output) tSSCK LSB tSOS MSB tSOSSH LSB Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 840 Table 34-47. SPI timing characteristics and requirements(1) Symbol Parameter tSCK SCK period Master tSCKW SCK high/low width Master - 0.5*tSCK - tSCKR SCK rise time(2) Master - - - tSCKF SCK fall time(2) Master - - - tMIS MISO setup to SCK Master - 21 - tMIH MISO hold after SCK Master - 13 - tMOS MOSI setup SCK Master - tSCK/2 - 3 - tMOH MOSI hold after SCK Master - 3 - tSSCK Slave SCK Period Slave 1*tCLK_APB - - tSSCKW SCK high/low width Slave 0.5*tSSCK - - tSSCKR SCK rise time(2) Slave - - - tSSCKF SCK fall time(2) Slave - - - tSIS MOSI setup to SCK Slave tSSCK/2 - 9 - - tSIH MOSI hold after SCK Slave tSSCK/2 - 3 - - PRELOADEN=1 2*tCLK_APB + tSOS - - PRELOADEN=0 tSOS+7 - - tSSS SS setup to SCK Conditions Slave Min. Typ. Max. 84 tSSH SS hold after SCK Slave tSIH - 4 - - tSOS MISO setup SCK Slave - tSSCK/2 - 18 - tSOH MISO hold after SCK Slave - 18 - tSOSS MISO setup after SS low Slave - 18 - MISO hold after SS high Slave - 10 - tSOSH Notes: 1. 2. Units ns These values are based on simulation. These values are not covered by test limits in production. See “I/O Pin Characteristics” on page 812 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 841 34.14.3 SERCOM in I2C Mode Timing Table 34-48 describes the requirements for devices connected to the I2C Interface Bus. Timing symbols refer to Figure 34-16. Figure 34-16. I2C Interface Bus Timing tHIGH tOF tR tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF Table 34-48. I2C Interface Timing(1) Symbol Parameter Conditions Min. Typ. Max. Standard / Fast mode Cb(2) = 400pF - 230 350 Fast mode + Cb(2) = 550pF - 60 100 High speed mode Cb(2) - 30 60 Standard / Fast mode 10pF < Cb(2) < 400pF - 25 50 Fast mode + 10pF < Cb(2) < 550pF - 20 30 High speed mode 10pF < Cb(2) < 100pF - 10 20 Hold time (repeated) START condition fSCL > 100kHz, Master tLOW-9 - - tLOW Low period of SCL Clock fSCL > 100kHz 113 - - tBUF Bus free time between a STOP and a START condition fSCL > 100kHz tLOW - - tSU;STA Setup time for a repeated START condition fSCL > 100kHz, Master tLOW+7 - - tHD;DAT Data hold time fSCL > 100kHz, Master 9 - 12 tSU;DAT Data setup time fSCL > 100kHz, Master 104 - - tSU;STO Setup time for STOP condition fSCL > 100kHz, Master tLOW+9 - - tSU;DAT;Rx Data setup time (receive mode) fSCL > 100kHz, Slave 51 - 56 tHD;DAT;Tx Data hold time (send mode) fSCL > 100kHz, Slave 71 90 138 Rise time for both SDA and SCL(3) tR Output fall time from VIHmin to VILmax (3) tOF tHD;STA Notes: 1. 2. 3. = 100pF Units ns These values are based on simulation. These values are not covered by test limits in production. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF. These values are based on characterization. These values are not covered by test limits in production. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 842 34.14.4 SWD Timing Figure 34-17.SWD Interface Signals Read Cycle From debugger to SWDIO pin Stop Park Tri State Thigh Tos Data Data Parity Start Tlow From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Tri State Write Cycle From debugger to SWDIO pin Stop Park Tri State Tis Start Tih From debugger to SWDCLK pin SWDIO pin to debugger Tri State Acknowledge Data Data Parity Tri State Table 34-49. SWD Interface Timings(1) Symbol Parameter THIGH Min. Max. SWDCLK High period 10 500000 TLOW SWDCLK Low period 10 500000 TOS SWDIO output skew to falling edge SWDCLK -5 5 TIS Input Setup time required between SWDIO 4 - TIH Input Hold time required between SWDIO and rising edge SWDCLK 1 - Note: 1. Conditions VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Units ns These values are based on simulation. These values are not covered by test limits in production or characterization. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 843 35. Packaging Information 35.1 Thermal Considerations 35.1.1 Thermal Resistance Data Table 6-1 on page 13 summarizes the thermal resistance data depending on the package. Table 35-1. Thermal Resistance Data Package Type θJA θJC Units 24-pin QFN 61.7 25.4 °C/W 20-pin SOIC 44.0 21.0 °C/W 20-ball WLCSP 37.4 6.6 °C/W 14-pin SOIC 58.5 26.3 °C/W 35.1.2 Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: Equation 1 T J = T A + ( P D × θ JA ) Equation 2 T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) where: z θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 6-1 on page 13. z θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 6-1 on page 13. z θHEATSINK = cooling device thermal resistance (°C/W), provided in the device datasheet. z PD = device power consumption (W). z TA = ambient temperature (°C). From the Equation 1, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 844 35.2 Package Drawings 35.2.1 24-pin QFN Table 35-2. Device and Package Maximum Weight 44 mg Table 35-3. Package Characteristics Moisture Sensitivity Level MSL3 Table 35-4. Package Reference JEDEC Drawing Reference MO-220 JESD97 Classification E3 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 845 35.2.2 20-pin SOIC Table 35-5. Device and Package Maximum Weight 530 mg Table 35-6. Package Characteristics Moisture Sensitivity Level MSL3 Table 35-7. Package Reference JEDEC Drawing Reference MS-013 JESD97 Classification E3 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 846 35.2.3 20-ball WLCSP Table 35-8. Device and Package Maximum Weight 7 mg Table 35-9. Package Characteristics Moisture Sensitivity Level MSL3 Table 35-10. Package Reference JEDEC Drawing Reference MS-220 JESD97 Classification E8 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 847 35.2.4 14-pin SOIC Table 35-11. Device and Package Maximum Weight 230 mg Table 35-12. Package Characteristics Moisture Sensitivity Level MSL3 Table 35-13. Package Reference JEDEC Drawing Reference MS-012 JESD97 Classification E3 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 848 35.3 Soldering Profile The following table gives the recommended soldering profile from J-STD-20. Profile Feature Green Package Average Ramp-up Rate (217°C to peak) 3°C/s max Preheat Temperature 175°C +/-25°C 150-200°C Time Maintained Above 217°C 60-150s Time within 5°C of Actual Peak Temperature 30s Peak Temperature Range 260°C Ramp-down Rate 6°C/s max Time 25°C to Peak Temperature 8 minutes max A maximum of three reflow passes is allowed per component. ___REV___383142 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 849 36. Schematic Checklist 36.1 Introduction A good hardware design comes from a proper schematic. This chapter describes a common checklist which should be used when starting and reviewing the schematics for the design of the device. This chapter illustrates a recommended power supply connection, how to connect external analog references, programmer, debugger, oscillator, and crystal. 36.1.1 Operation in Noisy Environment If the microcontroller is operating in an environment with much electromagnetic noise it must be protected from this noise to ensure reliable operation. In addition to following best practice EMC design guidelines, the recommendations listed in the schematic checklist sections must be followed. In particular placing decoupling capacitors very close to the power pins, a RC-filter on the RESET pin, and a pull-up resistor on the SWCLK pin is critical for reliable operations. It is also relevant to eliminate or attenuate noise in order to avoid that it reaches supply pins, I/O pins and crystals. 36.2 Power Supply The device supports a single power supply from 1.62 to 3.63V. 36.2.1 Power Supply Connections Figure 36-1. Power Supply Schematic 100nF 4.7μF Table 36-1. Power Supply Connections, VDDCORE From Internal Regulator Signal Name VDDIO/IN/ANA Recommended Pin Connection 1.6V to 3.6V Decoupling/filtering capacitors 100nF(1)(2) and 4.7µF(1) GND Description Supply voltage Ground Notes: 1. 2. These values are only given as typical examples. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group, low ESR caps should be used for better decoupling. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 850 36.3 External Analog Reference Connections The following schematic checklist is only necessary if the application is using one or more of the external analog references. If the internal references are used instead, the following circuits in Figure 36-2 and Figure 36-3 are not necessary. Figure 36-2. External Analog Reference Schematic With Two References Figure 36-3. External Analog Reference Schematic With One Reference Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 851 Table 36-2. External Analog Reference Connections Signal Name Recommended Pin Connection Description 1.0V to VDDANA - 0.6V for ADC 1.0V to VDDANA - 0.6V for DAC VREFx Decoupling/filtering capacitors External reference from VREFx pin on the analog port 100nF(1)(2) and 4.7µF(1) GND Ground Notes: 1. 2. These values are given as a typical example. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 852 36.4 External Reset Circuit The external reset circuit is connected to the RESET pin when the external reset function is used. If the external reset function has been disabled, the circuit is not necessary. The reset switch can also be removed, if the manual reset is not necessary. After power up, the RESET pin has RESET functionality enabled by default. To use this pin as GPIO, user has to disable the RESET functionality using External Reset Controller (EXTCTRL) register. The RESET pin itself has an internal pull-up resistor, hence it is optional to also add an external pull-up resistor. Figure 36-4. External Reset Circuit Example Schematic DD A pull-up resistor makes sure that the reset does not go low unintended causing a device reset. An additional resistor has been added in series with the switch to safely discharge the filtering capacitor, i.e. preventing a current surge when shorting the filtering capacitor which again causes a noise spike that can have a negative effect on the system. Table 36-3. Reset Circuit Connections Signal Name Recommended Pin Connection Description Reset low level threshold voltage VDDIO = 1.6V - 2.0V: Below 0.33 * VDDIO VDDIO = 2.7V - 3.6V: Below 0.36 * VDDIO RESET Decoupling/filter capacitor 100nF(1) Reset pin Pull-up resistor 10kΩ(1)(2) Resistor in series with the switch 330Ω(1) Notes: 1. 2. 36.5 These values are given as a typical example. The device features an internal pull-up resistor on the RESET pin, hence an external pull-up is optional. Unused or Unconnected Pins For unused pins the default state of the pins for the will give the lowest current leakage. There is thus no need to do any configuration of the unused pins in order to lower the power consumption. 36.6 Clocks and Crystal Oscillators The device can be run from internal or external clock sources, or a mix of internal and external sources. An example of usage will be to use the internal 8MHz oscillator as source for the system clock, and an external 32.768kHz watch crystal as clock source for the Real-Time counter (RTC). Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 853 36.6.1 External Clock Source Figure 36-5. External Clock Source Example Schematic Table 36-4. External Clock Source Connections Signal Name Recommended Pin Connection Description XIN XIN is used as input for an external clock signal Input for inverting oscillator pin XOUT/GPIO Can be left unconnected or used as normal GPIO 36.6.2 Crystal Oscillator Figure 36-6. Crystal Oscillator Example Schematic The crystal should be located as close to the device as possible. Long signal lines may cause too high load to operate the crystal, and cause crosstalk to other parts of the system. Table 36-5. Crystal Oscillator Checklist Signal Name Recommended Pin Connection XIN Load capacitor 15pF(1)(2) XOUT Load capacitor 15pF(1)(2) Notes: 1. 2. Description External crystal between 0.4 to 30MHz These values are given only as typical example. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group. 36.6.3 External Real Time Oscillator The low frequency crystal oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into consideration. Both values are specified by the crystal vendor. The device's oscillator is optimized for very low power consumption, hence close attention should be made when selecting crystals, see “Crystal Oscillator Characteristics” on page 830 for maximum ESR recommendations on 12.5pF crystals. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 854 The Low-frequency Crystal Oscillator provides an internal load capacitance of typical values available in Table 34-39. This internal load capacitance and PCB capacitance can allow to use a Crystal inferior to 12.5pF load capacitance without external capacitors as shown in Figure 36-7. Figure 36-7. External Real Time Oscillator without Load Capacitor However, to improve Crystal accuracy and Safety Factor, it can be recommended by crystal datasheet to add external capacitors as shown in the figure below. To find suitable load capacitance for a 32.768kHz crystal, consult the crystal datasheet. Figure 36-8. External Real Time Oscillator with Load Capacitor Table 36-6. External Real Time Oscillator Checklist Signal Name Recommended Pin Connection Description XIN32 Load capacitor 22pF(1)(2) Timer oscillator input XOUT32 Load capacitor 22pF Notes: 1. 2. (1)(2) Timer oscillator output These values are given only as typical examples. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal group. 36.6.4 Calculating the Correct Crystal Decoupling Capacitor In order to calculate correct load capacitor for a given crystal one can use the model shown in the following figure which includes internal capacitors CLn, external parasitic capacitance CELn and external load capacitance CPn. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 855 Figure 36-9. Crystal Circuit With Internal, External and Parasitic Capacitance CL1 CEL1 CP1 CL2 CP2 CEL2 Using this model the total capacitive load for the crystal can be calculated as shown in the equation below: ∑ ( C L1 + C P1 + C EL1 ) ( C L2 + C P2 + C EL2 ) C tot = -------------------------------------------------------------------------------------------------------C L1 + C P1 + C EL1 + C L2 + C P2 + C EL2 where Ctot is the total load capacitance seen by the crystal, this value should be equal to the load capacitance value found in the crystal manufacturer datasheet. The parasitic capacitance CELn can in most applications be disregarded as these are usually very small. If accounted for the value is dependent on the PCB material and PCB layout. For some crystal the internal capacitive load provided by the device itself can be enough. To calculate the total load capacitance in this case. CELn and CPn are both zero, CL1 = CL2 = CL, and the equation reduces to the following: ∑ CL C tot = ------2 See “Electrical Characteristics” on page 804 for the device equivalent internal pin capacitance. 36.7 Programming and Debug Ports For programming and/or debugging, the device should be connected using the Serial Wire Debug, SWD, interface. Currently the SWD interface is supported by several Atmel and third party programmers and debuggers, like the SAMICE, JTAGICE3 or the device’s Xplained Pro (device’s evaluation kit) Embedded Debugger. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 856 Refer to the SAM-ICE, JTAGICE3 or the device’s Xplained Pro user guides for details on debugging and programming connections and options. For connecting to any other programming or debugging tool please refer to that specific programmer or debugger’s user guide. The device’s Xplained Pro evaluation board for the device supports programming and debugging through the onboard embedded debugger so no external programmer or debugger is needed. Note that a pull-up resistor on the SWCLK pin is critical for reliable operations. Refer to “Operation in Noisy Environment” on page 850. Figure 36-10.SWCLK Circuit Connections VDD 1kΩ SWCLK Table 36-7. SWCLK Circuit Connections Pin Name Description Recommended Pin Connection SWCLK Serial wire clock pin Pull-up resistor 1kΩ 36.7.1 Cortex Debug Connector (10-pin) For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the signals should be connected as shown in the following figure and detailed table. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 857 Figure 36-11.Cortex Debug Connector (10-pin) DD 1 Table 36-8. Cortex Debug Connector (10-pin) Signal Name Description SWDCLK Serial wire clock pin SWDIO Serial wire bidirectional data pin RESET Target device reset pin, active low VTref Target voltage sense, should be connected to the device VDD GND Ground 36.7.2 10-pin JTAGICE3 Compatible Serial Wire Debug Interface The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin) directly, hence a special pinout is needed to directly connect the device to the JTAGICE3, alternatively one can use the JTAGICE3 squid cable and manually match the signals between the JTAGICE3 and the device. The following figure describes how to connect a 10-pin header that support connecting the JTAGICE3 directly to the device without the need for a squid cable. To connect the JTAGICE3 programmer and debugger to the device, one can either use the JTAGICE3 squid cable, or use a 10-pin connector as shown in the figure with details given in the table to connect to the target using the JTAGICE3 cable directly. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 858 Figure 36-12.10-pin JTAGICE3 Compatible Serial Wire Debug Interface 10-pin JTAGICE3 Compatible VDD Serial Wire Debug Header SWDCLK 1 NC SWDIO GND VTG RESET RESET NC NC NC NC SWDCLK SWDIO GND Table 36-9. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface Signal Name Description SWDCLK Serial wire clock pin SWDIO Serial wire bidirectional data pin RESET Target device reset pin, active low VTG Target voltage sense, should be connected to the device VDD GND Ground 36.7.3 20-pin IDC JTAG Connector For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the signals should be connected as shown in the figure with details described in the table. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 859 Figure 36-13.20-pin IDC JTAG Connector VDD 20-pin IDC JTAG Connector VTref 1 NC NC GND NC GND SWDIO GND SWDCLK GND NC GND NC GND* RESET GND* NC GND* NC GND* RESET SWDCLK SWDIO GND Table 36-10. 20-pin IDC JTAG Connector Signal Name Description SWCLK Serial wire clock pin SWDIO Serial wire bidirectional data pin RESET Target device reset pin, active low VTref Target voltage sense, should be connected to the device VDD GND Ground GND* These pins are reserved for firmware extension purposes. They can be left open or connected to GND in normal debug environment. They are not essential for SWD in general. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 860 37. Errata 37.1 Revision A Not Sampled 37.2 Revision B 37.2.1 DSU 1 - The MBIST ""Pause-on-Error"" feature is not functional on this device. Errata reference: 14324 Fix/Workaround: Do not use the ""Pause-on-Error"" feature. 37.2.2 DMAC 1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect. Errata reference: 13507 Fix/Workaround: Add a NOP instruction between each write to CRCDATAIN register. 37.2.3 NVMCTRL 1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134 This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area. Fix/Workaround: Set MANW in the NVM.CTRLB to 1 at startup 2 - When external reset is active it causes a high leakage current on VDDIO. Errata reference: 13446 Fix/Workaround: Minimize the time external reset is active. 37.2.4 Device 1 - Internal BOD12 could be re-enabled too early on some parts when leaving standby sleep mode, this could lead to a device reset with BOD12 as reset cause when leaving standby mode. Errata reference: 15513 Fix/Workaround: Disable BOD12 by software just before entering standby sleep mode writing 0x00000004 value at 0x40000838 location and re-enable it writing 0x00000006 at 0x40000838 when exiting sleep mode. 2 - The SYSTICK calibration value is incorrect. Errata reference: 14157 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 861 Fix/Workaround: The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation. 3 - If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible. Errata reference: 10416 Fix/Workaround: Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin. 4 - The voltage regulator in low power mode is not functional at temperatures above 85C. Errata reference: 12291 Fix/Workaround: Enable normal mode on the voltage regulator in standby sleep mode. Example code: // Set the voltage regulator in normal mode configuration in standby sleep mode SYSCTRL->VREG.bit.RUNSTDBY = 1; 5 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset. Errata reference: 13574 Fix/Workaround: Write CTRLB.ACKACT to 0 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Write CTRLB.ACKACT to 1 using the following sequence: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 862 Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction. When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position. Code replacements examples: Current: SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; // Re-enable interrupts if applicable. Current: SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; Change to: // If higher priority interrupts exist, then disable so that the // following two writes are atomic. SERCOM - STATUS.reg = 0; SERCOM - CTRLB.reg = 0; // Re-enable interrupts if applicable. Current: /* ACK or NACK address */ SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); Change to: // CMD=0x3 clears all interrupts, so to keep the result similar, // PREC is cleared if it was set. if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; 6 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock. Errata reference: 12164 Fix/Workaround: Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 863 Do a power cycle to reset the GCLK generators after an external XOSC32K failure. 37.2.5 DFLL48M 1 - The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device. Errata reference: 9905 Fix/Workaround: Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module. 2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669 Fix/Workaround: Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt. 37.2.6 EIC 1 - When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit. Errata reference: 15341 Fix/Workaround: Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts. 37.2.7 SERCOM 1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested. Errata reference: 12003 Fix/Workaround: To use the Master or Slave SCL low extend time-outs, enable the SCL Low Timeout (CTRLA.LOWTOUT=1). 2 - In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852 Fix/Workaround: None Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 864 3 - If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated. Errata reference: 13369 Fix/Workaround: Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1. 4 - In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled. Errata reference: 12499 Fix/Workaround: In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode. 37.2.8 TCC 1 - Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work. Errata reference: 14817 Fix/Workaround: Basic capture mode must be set in lower channel and advance capture mode in upper channel. Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX All capture will be done as expected. 2 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference: 13262 If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts. Fix/Workaround: Avoid faults few cycles before the end or the beginning of a ramp. 3 - All DMA MCx triggers are not raised, on a CCx match. Errata reference: 13084 Fix/Workaround: To update CC/CCBUF values through DMA, use DMA OVF triggers Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 865 4 - With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked. Errata reference: 12519 Fix/Workaround: None 5 - In Dual slope mode a Retrigger Event does not clear the TCC counter. Errata reference: 12354 Fix/Workaround: None 6 - In two ramp mode, two events will be generated per cycle, one on each ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle. Errata reference: 12224 Fix/Workaround: None 7 - When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected. Errata reference: 12477 Fix/Workaround: None. 8 - TCC fault filtering on inverted fault is not working. Errata reference: 12512 Fix/Workaround: Use only non-inverted faults. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 866 38. About This Document 38.1 Conventions 38.1.1 Numerical Notation Table 38-1. Numerical notation 165 Decimal number 0101b Binary number (example 0b0101 = 5 decimal) 0101 Binary numbers are given without suffix if unambiguous 0x3B24 Hexadecimal number X Represents an unknown or don't care value Z Represents a high-impedance (floating) state for either a signal or a bus 38.1.2 Memory Size and Type Table 38-2. Memory Size and Bit Rate Symbol Description kB/kbyte kilobyte (210 = 1024) MB/Mbyte megabyte (220 = 1024*1024) GB/Gbyte gigabyte (230 = 1024*1024*1024) b bit (binary 0 or 1) B byte (8 bits) 1kbit/s 1,000 bit/s rate (not 1,024 bit/s) 1Mbit/s 1,000,000 bit/s rate 1Gbit/s 1,000,000,000 bit/s rate 38.1.3 Frequency and Time Table 38-3. Frequency and Time Symbol Description kHz 1kHz = 103Hz = 1,000Hz MHz 106 = 1,000,000Hz GHz 109 = 1,000,000,000Hz s second ms millisecond µs microsecond ns nanosecond Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 867 38.1.4 Registers and Bits Table 38-4. Register and bit mnemonics R/W Read/Write accessible register bit. The user can read from and write to this bit. R Read-only accessible register bit. The user can only read this bit. Writes will be ignored. W Write-only accessible register bit. The user can only write this bit. Reading this bit will return an undefined value. BIT Bit names are shown in uppercase. (Example PINA1) BITS[n:m] A set of bits from bit n down to m. (Example: PINA3..0 = {PINA3, PINA2, PINA1, PINA0} Reserved Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to zero when the register is written. Reserved bits will always return zero when read. PERIPHERALi If several instances of a peripheral exist, the peripheral name is followed by a number to indicate the number of the instance in the range 0-n. PERIPHERALi denotes one specific instance. Reset SET/CLR 38.2 Registers with SET/CLR suffix allows the user to clear and set bits in a register without doing a readmodify-write operation. These registers always come in pairs. Writing a one to a bit in the CLR register will clear the corresponding bit in both registers, while writing a one to a bit in the SET register will set the corresponding bit in both registers. Both registers will return the same value when read. If both registers are written simultaneously, the write to the CLR register will take precedence. Acronyms and Abbreviations Table 38-5 contains acronyms and abbreviations used in this document. Table 38-5. Acronyms and Abbreviations Abbreviation Description AC Analog Comparator ADC Analog-to-Digital Converter ADDR Address AHB AMBA Advanced High-performance Bus APB AMBA Advanced Peripheral Bus AREF Analog reference voltage AVDD Analog supply voltage BLB Boot Lock Bit BOD Brown-out detector CAL Calibration CC Compare/capture CLK Clock CRC Cyclic Redundancy Check Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 868 CTRL Control DAC Digital to Analog converter DFLL Digital Frequency Locked Loop DSU Device service unit EEPROM Electrically Erasable Programmable Read-Only Memory EIC External interrupt controller EVSYS Event System GCLK Generic clock GND Ground GPIO General Purpose Input/Output I2C Inter-integrated circuit IF Interrupt Flag INT Interrupt IOBUS I/O Bus NMI Non-Maskable Interrupt NVIC Nested vector interrupt controller NVMCTRL Non-Volatile Memory controller OSC Oscillator PAC Peripheral access controller PC Program counter PER Period PM Power manager POR Power-on reset PTC Peripheral touch controller PWM Pulse Width Modulation RAM Random-access memory REF Reference RMW Read-modify-write RTC Real-time counter RX Receiver SERCOM Serial communication interface SMBus System Management Bus SP Stack Pointer SPI Serial peripheral interface Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 869 SRAM Static random-access memory SYSCTRL System controller SWD Single-wire debug TC Timer/Counter TX Transmitter ULP Ultra Low Power USART Universal synchronous and asynchronous serial receiver and transmitter VDD Digital supply voltage VREF Voltage reference WDT Watchdog timer XOSC Crystal oscillator Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 870 39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 Rev. H – 08/2016 “Ordering Information” on page 5 Added “Device Identification” on page 6 “I/O Multiplexing and Considerations” on page 13 Added SWDIO in IO multiplexing table “I/O Multiplexing and Considerations” on page 13 Added a table note related to PA24 and PA25 pins “Memories” on page 21 Updated “Embedded Memories” on page 21: Added reference to the EEPROM Updated the Table : Set as “Reserved” 73:64 bit position Added “NVM Calibration and Auxiliary Space” on page 21 “PAC – Peripheral Access Controller” on page 30 Updated the PAC overiew: CLK_PAC0_APB and CLK_PAC1_APB are enabled at reset while CLK_PAC2_APB is disabled at reset. Added “Register Description” on page 31 “DSU – Device Service Unit” on page 39 Updated the table in “System Services Availability When Accessed Externally” on page 48. MBIST is not available when the device is protected from the external address space. Yes has been changed to No in the table. Updated the content in “Testing of Onboard Memories (MBIST)” on page 47 about the MBIST run time “GCLK – Generic Clock Controller” on page 88 “Signal Description” on page 89: Updated the signal name to GCLK_IO[5:0] Updated all the tables according to generic clock generator [5:0] Updated GENDIV GENDIV Reset value tables “SYSCTRL – System Controller” on page 143 Updated the content in “Open-Loop Operation” on page 152 and in “Closed-Loop Operation” on page 152 Updated “Debug Operation” on page 148 about debugger cold-plugging and hot plugging “WDT – Watchdog Timer” on page 208 Updated the content in “Debug Operation” on page 209 “RTC – Real-Time Counter” on page 227 Updated the content in “Clock/Calendar (Mode 2)” on page 231 “ADC – Analog-to-Digital Converter” on page 714 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 871 “Prescaler” on page 718: Added the formula of the PropagationDelay for Free Running Mode Updated the Table 30-1 Updated the description of Interrupts “AC – Analog Comparators” on page 753 “Block Diagram” on page 754: Removed one block diagram without DAC “Electrical Characteristics” on page 804 Updated Table 34-1 “Absolute Maximum Ratings: VPIN: min and max changed respectively from GND-0.3V to GND-0.6V and GND+0.3V to GND+0.6V Updated Table 34-10: Normal I/O Pins Characteristics, the Pull-up - Pull-down resistance excludes PA24 and PA25 pins. Those USB pins have different pull-up and pull-down Added “Injection Current” on page 814 Updated “Analog-to-Digital (ADC) Characteristics” on page 818: Removed “Conversion Speed” from the Table 34-19 “Operating Conditions” Added Table 34-35 “Flash Erase and Programming Current” Updated Table 34-4: Renamed the table to “Supply Slew Rates” and added “Max Fall Rate = 0.05 V/µs Updated the Table 34-2 “General Operating Conditions”: Voltage drop caution added “Electrical Characteristics at 105°C” on page 876 Updated Table 34-1 “Absolute Maximum Ratings: VPIN: min and max changed respectively from GND-0.3V to GND-0.6V and GND+0.3V to GND+0.6V Added “Injection Current” on page 814 Updated “Analog Characteristics” on page 816: Removed “Conversion Speed” from the Table 34-19 “Operating Conditions” Updated Table 34-4: Renamed the table to “Supply Slew Rates” and added “Max Fall Rate = 0.05 V/µs Updated the Table 34-2 “General Operating Conditions”: Voltage drop caution added 39.2 Rev. G – 05/2016 “SYSCTRL – System Controller” on page 143 “Principle of Operation” on page 148: Updated the last paragraph to “To force the oscillator to run in standby mode except for DFLL and DPLL, the RUNSTDBY bit must be written to one” DFLLCTRL: Removed RUNSTDBY bit DPLLCTRLA: Removed RUNSTDBY bit “ADC – Analog-to-Digital Converter” on page 714 Table 30-13 and Table 30-14: Updated the content in the two respective tables “Electrical Characteristics” on page 804 Table 34-20 and Table 34-21: The device has single power domain. The table notes updated accordingly. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 872 39.3 Rev. F – 04/2016 “Ordering Information” on page 5 Added 105C ordering information for SAMD10 and SAMD11 “Memories” on page 21 “NVM User Row Mapping” on page 23: Added “Production setting” in the table 39.4 Rev. E – 03/2016 “Packaging Information” on page 844 Table 35-1: Updated the thermal resistance values of the package 20-ball WLCSP “20-ball WLCSP” on page 847: Updated the value of the device maximum weight “Schematic Checklist” on page 850 “Operation in Noisy Environment” on page 850: This section has been added “Programming and Debug Ports” on page 856: The pull-up resistor to SWCLK pin is 1kΩ Errata: Revision B: Added errata related to EIC. Errata reference 15341 39.5 Rev. D – 02/2016 “I/O Multiplexing and Considerations” on page 13 Table 6-1: Added AC: CMP0/1 in the IO multiplexing table “Memories” on page 21 “NVM Software Calibration Row Mapping” on page 24: Removed the text “CRr_SYSCTRL_DFLLVAL” “TC – Timer/Counter” on page 573 “Capture Operations” on page 582: Removed timestamp from “Event Capture Action” “Electrical Characteristics at 105°C” on page 876 “SERCOM in SPI Mode Timing” on page 906: added in the datasheet “SERCOM in I2C Mode Timing” on page 908: Added in the datasheet Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 873 39.6 Rev. C – 01/2016 Introduced WLCSP20 package offering: “Features” on page 2: Added 20-ball WLCSP. “Ordering Information” on page 5: Added ATSAMD10D14A-UUT. “Configuration Summary” on page 3: Added WLCSP to “Pinout” on page 8: Added “SAM D10D 20-ball WLCSP” on page 9. “I/O Multiplexing and Considerations” on page 13: Added WLCSP20 multiplexing signals. “Packaging Information” on page 844: - Added WLCSP20 to Table 35-1. - Added “20-ball WLCSP” on page 847 package drawing. “DSU – Device Service Unit” on page 39 Updated Bit 21-16 - SERIES [5:0] in DID. The value of the field is 0x02. “SYSCTRL – System Controller” on page 143 Updated description in “Drift Compensation” on page 154. “NVMCTRL – Non-Volatile Memory Controller” on page 355 Removed the text related to “AUTOWS bit” from “Clocks” on page 356 “PORT” on page 378 Updated Bit 17 - INEN in WRCONFIGn. This bit determines the new value written to PINCFGy.INEN for all pins selected by..... “TC – Timer/Counter” on page 573 TC instances are paired ..... starting from TC1 (not from TC0) in “Clocks” on page 575 “TCC – Timer/Counter for Control Applications” on page 614 Updated “Stop Command”, “Pause Event Action” and “Event Action Off” in “Counter Operation” on page 620 “Electrical Characteristics” on page 804 “Digital Frequency Locked Loop (DFLL48M) Characteristics” on page 833: Removed note from Table 34-41. “Digital Frequency Locked Loop (DFLL48M) Characteristics” on page 833: Added note to Table 34-41. “NVM Characteristics” on page 828: Updated the Table 34-31 “Power Consumption” on page 807: Added Max values in the Table 34-7 Appendix A Added “Electrical Characteristics at 105°C” on page 876 39.7 Rev. B – 07/2015 “Description” on page 1 CoreMark score updated from 2.14 to 2.46 CoreMark/MHz. “NVM User Row Mapping” on page 23 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 874 Added WDT window default value which is WINDOW_1 = 0x5. Row bits [24:17] Reserved and Default value = 0x70. Row bit [41] Reserved and Default value = 0. “ Starting CRC32 Calculation” on page 46 Updated how NVMCTRL security bit affects only CRC32 through SWD interface. “SERCOM SPI – SERCOM Serial Peripheral Interface” on page 476 Updated the features. Serial clock speed up to 12MHz in Master Operation. REFCTRL Register Updated Table 30-7 on page 731. AREFx changed to VREFx. CTRLB Register Updated Table 32-3 on page 791. VREFP changed to VREFA. “Electrical Characteristics” on page 804 Updated all SAMD10 Electrical characteristic values. “Ordering Information” on page 5: Removed carrier type “Tray” for ordering code selection Errata: Revision B: Removed errata reference 11938. “Schematic Checklist” on page 850 Added “Schematic Checklist” on page 850 39.8 Rev. A – 01/2015 Initial revision Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 875 Appendix A. Electrical Characteristics at 105°C A.1 Disclaimer All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid across operating temperature and voltage unless otherwise specified. A.2 Absolute Maximum Ratings Stresses beyond those listed in Table 39-1 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 39-1. Absolute maximum ratings Symbol Parameter Min. Max. Units VDD Power supply voltage 0 3.8 V IVDD Current into a VDD pin - 92(1) mA IGND Current out of a GND pin - 130(1) mA VPIN Pin voltage with respect to GND and VDD GND-0.6V VDD+0.6V V -60 150 °C Tstorage Note: A.3 Storage temp 1. Maximum source current is 46mA and maximum sink current is 65mA per cluster. Also note that each VDD/GND pair is connected to 2 clusters so current consumption through the pair will be the sum of the clusters source/sink currents. General Operating Ratings The device must operate within the ratings listed in Table 39-2 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 39-2. General operating conditions(2) Symbol VDD TA Parameter Power supply voltage Temperature range TJ Junction temperature Notes: 1. 2. Min. Typ. Max. Units 1.62(1) 3.3 3.63 V -40 25 105 °C - - 125 °C With BOD33 disabled. If the BOD33 is enabled, check Table 39-14 CAUTION: In debugger cold-plugging mode, NVM erase operations are not protected by the BOD33 and BOD12. NVM erase operation at supply voltages below specified minimum can cause corruption of NVM areas that are mandatory for correct device behavior. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 876 A.4 Supply Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 105°C, unless otherwise specified and are valid for a junction temperature up to TJ = 125°C. Refer to “Power Supply and Start-Up Considerations” on page 17. Table 39-3. Supply voltage Characteristics Symbol VDD Conditions Min. Max. Units Full Voltage Range 1.62 3.63 V Table 39-4. Supply Rise Rates Symbol VDDIO DC supply peripheral I/Os, internal regulator and analog supply voltage VDDANA A.5 Parameter Fall Rate Max Rise Rate Max. 0.05 0.1 0.05 0.1 Units V/µs Maximum Clock Frequencies Table 39-5. Maximum GCLK Generator Output Frequencies Symbol fGCLKGEN0 / fGCLK_MAIN fGCLKGEN1 fGCLKGEN2 fGCLKGEN3 fGCLKGEN4 fGCLKGEN5 Description GCLK Generator Output Frequency Undivided Divided Units 96 48 MHz Table 39-6. Maximum Peripheral Clock Frequencies Symbol Description Max. Units fCPU CPU clock frequency 48 MHz fAHB AHB clock frequency 48 MHz fAPBA APBA clock frequency 48 MHz fAPBB APBB clock frequency 48 MHz fAPBC APBC clock frequency 48 MHz DFLL48M Reference clock frequency 33 kHz FDPLL96M Reference clock frequency 2 MHz FDPLL96M 32k Reference clock frequency 32 kHz fGCLK_WDT WDT input clock frequency 48 MHz fGCLK_RTC RTC input clock frequency 48 MHz fGCLK_EIC EIC input clock frequency 48 MHz fGCLK_DFLL48M_REF fGCLK_DPLL fGCLK_DPLL_32K Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 877 Table 39-6. Maximum Peripheral Clock Frequencies (Continued) Symbol Description Max. Units fGCLK_EVSYS_CHANNEL_0 EVSYS channel 0 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_1 EVSYS channel 1 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_2 EVSYS channel 2 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_3 EVSYS channel 3 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_4 EVSYS channel 4 input clock frequency 48 MHz fGCLK_EVSYS_CHANNEL_5 EVSYS channel 5 input clock frequency 48 MHz fGCLK_SERCOMx_SLOW Common SERCOM slow input clock frequency 48 MHz fGCLK_SERCOM0_CORE SERCOM0 input clock frequency 48 MHz fGCLK_SERCOM1_CORE SERCOM1 input clock frequency 48 MHz fGCLK_SERCOM2_CORE SERCOM2 input clock frequency 48 MHz TCC0 input clock frequency 96 MHz TC1,TC2 input clock frequency 48 MHz ADC input clock frequency 48 MHz fGCLK_AC_DIG AC digital input clock frequency 48 MHz fGCLK_AC_ANA AC analog input clock frequency 64 kHz fGCLK_DAC DAC input clock frequency 350 kHz fGCLK_PTC PTC input clock frequency 48 MHz fGCLK_TCC0 fGCLK_TC1, GCLK_TC2 fGCLK_ADC A.6 Power Consumption The values in Table 39-7 are measured values of power consumption under the following conditions, except where noted: z z z Operating conditions z VVDDIN = 3.3V z VDDIN = 1.8V, CPU is running on Flash with 3 wait state z Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first instruction fetched in flash. Oscillators z XOSC (crystal oscillator) stopped z XOSC32K (32kHz crystal oscillator) running with external 32kHz crystal z DFLL48M using XOSC32K as reference and running at 48MHz Clocks z DFLL48M used as main clock source, except otherwise specified. z CPU, AHB clocks undivided z APBA clock divided by 4 z APBB and APBC bridges off z The following AHB module clocks are running: NVMCTRL, APBA bridge z z All other AHB clocks stopped The following peripheral clocks running: PM, SYSCTRL, RTC Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 878 z All other peripheral clocks stopped z I/Os are inactive with internal pull-up z CPU is running on flash with 1 wait states z NVMCTRL cache enabled z BOD33 disabled Table 39-7. Current Consumption Mode Conditions TA VCC 25°C 3.3V 3.01 105°C 3.3V 3.06 25°C 1.8V 2.95 105°C 1.8V 3.06 25°C 3.3V 53*freq + 330 105°C 3.3V 53*freq + 402 25°C 3.3V 3.39 105°C 3.3V 3.45 25°C 1.8V 3.33 wait states 105°C 1.8V 3.45 CPU running a Fibonacci algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference 25°C 3.3V 61*freq + 335 105°C 3.3V 61*freq + 404 25°C 3.3V 4.04 105°C 3.3V 4.13 25°C 1.8V 3.62 wait states 105°C 1.8V 3.77 CPU running a CoreMark algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference 25°C 3.3V 74*freq + 356 105°C 3.3V 75*freq + 414 CPU running a While(1) algorithm CPU running a While(1) algorithm VDDIN=1.8V, CPU is running on Flash with 3 wait states CPU running a While(1) algorithm, CPU is running on Flash with 3 wait states with GCLKIN as reference CPU running a Fibonacci algorithm CPU running a Fibonacci algorithm VDDIN=1.8V, CPU is running on flash with 3 ACTIVE CPU running a CoreMark algorithm CPU running a CoreMark algorithm VDDIN=1.8V, CPU is running on flash with 3 Min. Typ. Max. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 Units mA µA (with freq in MHz) mA µA (with freq in MHz) mA µA (with freq in MHz) 879 Table 39-7. Current Consumption (Continued) Mode Conditions IDLE0 I IDLE1 I IDLE2 I XOSC32K running RTC running at 1kHz STANDBY XOSC32K and RTC stopped TA VCC Min. Typ. Max. 25°C 3.3V 1.89 105°C 3.3V 1.95 25°C 3.3V 1.36 105°C 3.3V 1.40 25°C 3.3V 1.17 105°C 3.3V 1.19 25°C 3.3V 10.40 105°C 3.3V 142.50 25°C 3.3V 9.20 105°C 3.3V 137.50 Units mA µA Table 39-8. Wake-up Time Mode Conditions IDLE0 OSC8M used as main clock source, cache disabled IDLE1 I IDLE2 I STANDBY I OSC8M used as main clock source, cache disabled OSC8M used as main clock source, cache disabled OSC8M used as main clock source, cache disabled TA Min. Typ. 25°C 4.0 105°C 4.0 25°C 12.1 105°C 14.3 25°C 13.0 105°C 15.2 25°C 19.6 105°C 20.1 Max. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 Units µs 880 Figure 39-1. Measurement Schematic VDDIN VDDANA VDDIO Amp 0 A.7 I/O Pin Characteristics A.7.1 Normal I/O Pins Table 39-9. Normal I/O Pins Characteristics Symbol Parameter RPULL Pull-up - Pull-down resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage Conditions Min. Typ. Max. Units 20 40 60 kΩ VDD=1.62V-2.7V - - 0.25*VDD VDD=2.7V-3.63V - - 0.3*VDD VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63V 0.55*VDD - - VDD>1.6V, IOL maxI - 0.1*VDD 0.2*VDD VDD>1.6V, IOH maxI 0.8*VDD 0.9*VDD - I V Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 881 Symbol IOL Output low-level current IOH Output high-level current Rise time(1) tRISE Fall time(1) tFALL ILEAK Input leakage current Note: A.7.2 Parameter 1. Conditions Min. Typ. Max. VDD=1.62V-3V, PORT.PINCFG.DRVSTR=0 - - 1 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=0 - - 2.5 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=1 - - 3 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=1 - - 10 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=0 - - 0.7 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=0 - - 2 VDD=1.62V-3V, PORT.PINCFG.DRVSTR=1 - - 2 VDD=3V-3.63V, PORT.PINCFG.DRVSTR=1 - - 7 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=0 load = 5pF, VDD = 3.3V - 15 PORT.PINCFG.DRVSTR=1 load = 20pF, VDD = 3.3V - 15 +/-0.015 1 Pull-up resistors disabled Units mA nS -1 µA These values are based on simulation. These values are not covered by test limits in production or characterization. I2C Pins Refer to “I/O Multiplexing and Considerations” on page 13 to get the list of I2C pins. Table 39-10. I2C Pins Characteristics in I2C configuration Symbol RPULL Parameter Pull-up - Pull-down resistance Condition I Min. Typ. Max. Units 20 40 60 kΩ Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 882 Symbol Parameter VIL Input low-level voltage VIH Input high-level voltage VHYS Hysteresis of Schmitt trigger inputs VOL Output low-level voltage CI Capacitance for each I/O Pin IOL Output low-level current fSCL SCL clock frequency RP Value of pull-up resistor A.8 Condition Min. Typ. Max. VDD=1.62V-2.7VI - - 0.25*VDD VDD=2.7V-3.63V - - 0.3*VDD VDD=1.62V-2.7V 0.7*VDD - - VDD=2.7V-3.63VI 0.55*VDD - - 0.08*VDD - - VDD> 2.0VI, IOL=3mA - - 0.4 VDD≤2.0V IOL=2mA - - 0.2*VDD Units V pF I VOL =0.4V Standard, Fast and HS Modes 3 - - VOL =0.4V Fast Mode+ 20 - - VOL =0.6V 6 - - I - - 3.4 mA fSCL ≤ 100kHz MHz Ω fSCL > 100kHz Injection Current Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 39-11. Injection Current(1) Symbol Parameter Min. Max. Iinj1(2) IO pin injection current -1 +1 Tinj2(3) IO pin injection current -15 +15 Iinjtotal Sum of IO pins injection current -45 +45 Notes: 1. 2. Units mA Injecting current may have an effect on the accuracy of Analog blocks Conditions for Vpin: Vpin < GND-0.3V or 3.6V < Vpin ≤ 4.2V Conditions for VDD: 3V < VDD ≤ 3.6V. If Vpin is lower than GND-0.6V, then a current limiting resistor is required. The negative DC injection current limiting resistor R is calculated as R = |(GND-0.6V . Vpin)/Iinj1|. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 883 If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting resistor R is calculated as R = (Vpin-(VDD+0.6V))/Iinj1 3. Conditions for Vpin: Vpin < GND-0.6V or Vpin ≤ 3.6V. Conditions for VDD: VDD ≤ 3V. If Vpin is lower than GND-0.6V, a current limiting resistor is required. The negative DC injection current limiting resistor R is calculated as R = |(GND-0.6V . Vpin)/Iinj2|. If Vpin is greater than VDD+0.6V, a current limiting resistor is required. The positive DC injection current limiting resistor R is calculated as R = (Vpin-(VDD+0.6V))/Iinj2. A.9 Analog Characteristics A.9.1 Voltage Regulator Characteristics Table 39-12. Decoupling requirements Symbol Parameter Input regulator capacitor, between VDDIN and GND CIN Note: A.9.2 Conditions Min. Typ. Max. Units - 4.7 - µF I Supplying any external components using VDDCORE pin is not allowed to assure the integrity of the core supply voltage. Power-On Reset (POR) Characteristics Table 39-13. POR Characteristics Symbol Parameter Conditions VPOT+ Voltage threshold on VDDIN rising I Voltage threshold on VDDIN falling Typ. Max. 1.27 1.43 1.58 0.62 1.02 1.32 Units V VDD Figure 39-2. POR Operating Principle VPOT+ VPOT- Time Reset VPOT- VDD falls at 1V/ms or slower Min. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 884 A.9.3 Brown-Out Detectors Characteristics BOD33 Figure 39-3. BOD33 Hysteresis OFF VCC VBOD RESET Figure 39-4. BOD33 Hysteresis ON VCC VBOD+ VBOD- RESET Table 39-14. BOD33 LEVEL Value Symbol BOD33.LEVEL Conditions Min. Typ. Max. - 1.67 1.71 - 1.70 1.75 - 2.81 2.83 48 - 3.09 3.20 6 1.61 1.64 1.65 1.64 1.67 1.69 2.72 2.76 2.79 3.00 3.07 3.10 6 7 VBOD+ 39 VBODor VBOD 7 39 Hysteresis ON Hysteresis ON or Hysteresis OFF 48 Note: See chapter Memories table “NVM Units V User Row Mapping” on page 23 for the BOD33 default value settings. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 885 Table 39-15. BOD33 Characteristics Symbol Parameter Conditions Min. Typ. Max. - 34 - 35 - 100 Step size, between adjacent values in BOD33.LEVEL I VHYST VBOD+ - VBOD- Hysteresis ON tDET Detection time Time with VDDANA < VTH necessary to generate a reset signal - 0.9(1) - tSTARTUP Startup time I - 2.2(1) - I Note: 1. Units mV µs These values are based on simulation. These values are not covered by test limits in production or characterization. Table 39-16. BOD33 Mode Characteristics Symbol Parameter Conditions IDLE2, Continuous mode Current consumption IBOD33 IDLE2, Sampling mode STDBY, Sampling mode A.9.4 TA VCC Typ. Max. 25 48 - 51 0.034 0.21 - 2.44 0.132 0.38 - 1.5 Min. Typ. Max. Units 25°C 3.3V -40 to 105°C 25°C 1.8V -40 to 105°C 25°C 3.3V -40 to 105°C Units µA Analog-to-Digital (ADC) Characteristics Table 39-17. Operating Conditions Symbol Parameter RES Resolution I 8 - 12 bits ADC Clock frequency I 30 - 2100 kHz Single shot 5 - 300 Free running 5 - 350(3) 0.5 - - cycles fCLK_ADC Sample rate(1) Conditions Sampling time(1) VDDANA ksps Conversion time(1) 1x Gain 6 - - cycles Power supply voltage T > 85°C 2.7 - 3.6 V VREF Voltage reference range 1.0 - VDDANA-0.6 V VREFINT1V Internal 1V reference (2) - 1.0 - V Internal ratiometric reference 0(2) - VDDANA/1.48 - V VREFINTVCC0 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 886 Table 39-17. Operating Conditions (Continued) Symbol Parameter VREFINTVCC0 Voltage Error VREFINTVCC1 VREFINTVCC1 Voltage Error Conditions Min. Typ. Max. Units Internal ratiometric reference 0(2) error 2.0V 0.2*VDDANA - 0.1V e. 4. 5. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*Vref/GAIN) Table 39-19. Single-Ended Mode Symbol ENOB Parameter Conditions Min. Typ. Max. Units Effective Number of Bits With gain compensation 9.5 9.8 Bits TUE Total Unadjusted Error 1x gain 10.5 40.0 LSB INL Integral Non-Linearity 1x gain 1.0 1.6 10.0 LSB DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.98 LSB Gain Error Ext. Ref. 1x -5.0 0.7 +5.0 mV Ext. Ref. 0.5x +/-0.09 +/-0.59 +/-3.5 % Ext. Ref. 2x to 16X +/-0.03 +/-0.2 +/-4.0 % -5 2.0 10 mV 54.2 65.0 76.0 dB 47.5 59.5 61 dB 48 60.0 64 dB -74 -68.8 -62.1 dB - 1.0 - mV Gain Accuracy(4) Offset Error SFDR SINAD Spurious Free Dynamic Range Signal-to-Noise and Distortion SNR Signal-to-Noise Ratio THD Total Harmonic Distortion Noise RMS Notes: Ext. Ref. 1x 1x Gain FCLK_ADC = 2.1MHz FIN = 40kHz AIN = 95%FSR T = 25°C 1. 2. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN: z VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V z VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V 3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (VREF/GAIN) 4. Performance with the Averaging Digital Feature Averaging is a feature which increases the sample accuracy. ADC automatically computes an average value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the Number-of-Samples-tobe-collected bit group in the Average Control register (AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT). Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 888 Table 39-20. Averaging feature Average Number Conditions 1 In differential mode, 1x gain, VDDANA=3.0V, VREF=1.0V, 350kSps T= 25°C 8 32 128 SNR (dB) SINAD (dB) SFDR (dB) ENOB (bits) 66.0 65.0 72.8 9.75 67.6 65.8 75.1 10.62 69.7 67.1 75.3 10.85 70.4 67.5 75.5 10.91 Performance with the hardware offset and gain correction Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain Correction register (GAINCORR). The offset and gain correction value is subtracted from the converted data before writing the Result register (RESULT). Table 39-21. Offset and Gain correction feature Gain Factor Conditions 0.5x 1x In differential mode, 1x gain, VDDANA=3.0V, VREF=1.0V, 350ksps T= 25°C 2x 8x 16x Offset Error (mV) Gain Error (mV) Total Unadjusted Error (LSB) 0.25 1.0 2.4 0.20 0.10 1.5 0.15 -0.15 2.7 -0.05 0.05 3.2 0.10 -0.05 6.1 Inputs and Sample and Hold Acquisition Times The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor ( R SAMPLE ) and a capacitor ( CSAMPLE ). In addition, the source resistance ( R SOURCE ) must be taken into account when calculating the required sample and hold time. Figure 34-5 shows the ADC input channel equivalent circuit. To achieve n bits of accuracy, the V CSAMPLE ≥ V IN × ( 1 – 2 –( n + 1 ) C SAMPLE capacitor must be charged at least to a voltage of ) The minimum sampling time t SAMPLEHOLD for a given R SOURCE can be found using this formula: t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × ( n + 1 ) × ln ( 2 ) for a 12 bits accuracy: t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × 9.02 where 1 t SAMPLEHOLD = -------------------2 × f ADC Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 889 A.9.5 Digital to Analog Converter (DAC) Characteristics Table 39-22. Operating Conditions(1) Symbol Parameter VDDANA Analog supply voltage AVREF External reference voltage Conditions Min. Typ. Max. Units I 1.62 - 3.63 V I 1.0 - VDDANA-0.6 V Internal reference voltage 1 - 1 - V Internal reference voltage 2 - VDDANA - V 0.05 - VDDANA-0.05 V I Linear output voltage range I Minimum resistive load I 5 - - kΩ I Maximum capacitance load I - - 100 pF Voltage pump disabled - 184 230 µA Units I DC supply current(2) IDD Notes: 1. 2. These values are based on specifications otherwise noted. These values are based on characterization. These values are not covered by test limits in production. Table 39-23. Clock and Timing(1) Symbol Parameter Conversion rate Startup time I Note: 1. Conditions Min. Typ. Max. Normal mode - - 350 For ΔDATA=+/-1 - - 1000 VDDNA > 2.6V - - 2.85 µs VDDNA < 2.6V - - 10 µs Cload=100pF Rload > 5kΩ ksps These values are based on simulation. These values are not covered by test limits in production or characterization. Table 39-24. Accuracy Characteristics(1) Symbol RES Parameter Input resolution Conditions Integral non-linearity Typ. I VREF= Ext 1.0V INL Min. VREF = VDDANA VREF= INT1V Max. Units 10 Bits VDD = 1.6V 0.4 0.5 2.5 VDD = 3.6V 0.6 0.7 1.5 VDD = 1.6V 1.4 1.5 2.5 VDD = 3.6V 0.7 0.8 1.5 VDD = 1.6V 0.4 0.5 1.5 VDD = 3.6V 0.3 0.4 1.5 LSB Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 890 Table 39-24. Accuracy Characteristics(1) Symbol Parameter Conditions VREF= Ext 1.0V DNL Differential non-linearity VREF= VDDANA VREF= INT1V Min. Typ. Max. VDD = 1.6V +/-0.2 +/-0.5 +/-1.5 VDD = 3.6V +/-0.4 +/-0.6 +/-1.2 VDD = 1.6V +/-1.1 +/-1.3 +/-1.5 VDD = 3.6V +/-1.0 +/-1.1 +/-1.2 VDD = 1.6V +/-0.2 +/-0.6 +/-1.5 VDD = 3.6V +/-0.3 +/-0.6 +/-1.6 Units LSB I Gain error Ext. VREF +/-1.5 +/-4.0 +/-10 mV I Offset error Ext. VREF +/-1.0 +/-2 +/-6 mV Min. Typ. Max. Note: A.9.6 1. All values measured using a conversion rate of 350ksps. Analog Comparator Characteristics Table 39-25. Electrical and Timing Symbol Parameter Conditions I Positive input voltage range I 0 - VDDANA I Negative input voltage range I 0 - VDDANA Offset Hysteresis = 0, Fast mode -15 0.0 15 I Hysteresis = 0, Low power mode -25 0.0 25 Hysteresis = 1, Fast mode 20 50 85 Hysteresis = 1, Low power mode 15 40 75 90 180 Hysteresis V Changes for VACM=VDDANA/2 100mV overdrive, Fast mode Propagation delay tSTARTUP VSCALE Startup time 282 520 Enable to ready delay Fast mode 1 2.6 Enable to ready delay Low power mode 14 22 µs -1.4 0.75 1.4 DNL(3) -0.9 0.25 0.9 Offset Error (1)(2) -0.2 0.260 0.92 Gain Error (1)(2) -0.89 0.215 0.89 1. 2. 3. mV ns Changes for VACM=VDDANA/2 100mV overdrive, Low power mode INL(3) Notes: Units LSB According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64 Data computed with the Best Fit method Data computed using histogram Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 891 A.9.7 Bandgap Reference Characteristics Table 39-26. Bandgap (Internal 1.1V reference) characteristics Symbol Parameter INT1V Internal 1.1V Bandgap reference A.9.8 Conditions Min. Typ. Max. Over voltage and [-40°C, +105°C] 1.08 1.1 1.12 Over voltage at 25°C 1.07 1.1 1.11 Units V Temperature Sensor Characteristics Temperature Sensor Characteristics Table 39-27. Temperature Sensor Characteristics(1) Symbol I Parameter Temperature sensor output voltage I Temperature sensor slope I Variation over VDDANA voltage Temperature Sensor accuracy Note: 1. 2. Conditions Min. T= 25°C, VDDANA = 3.3V Typ. Max. 0.688 Units V 2.06 2.16 2.26 mV/°C VDDANA=1.62V to 3.6V -0.4 1.4 3.0 mV/V Using the method described in “Software-based Refinement of the Actual Temperature” on page 892 -10 - 10 °C These values are based on characterization. These values are not covered by test limits in production. See also rev C errata concerning the temperature sensor. Software-based Refinement of the Actual Temperature The temperature sensor behavior is linear but it depends on several parameters such as the internal voltage reference which itself depends on the temperature. To take this into account, each device contains a Temperature Log row with data measured and written during the production tests. These calibration values should be read by software to infer the most accurate temperature readings possible. This Software Temperature Log row can be read at address 0x00806030. The Software Temperature Log row cannot be written. This section specifies the Temperature Log row content and explains how to refine the temperature sensor output using the values in the Temperature Log row. Temperature Log Row All values in this row were measured in the following conditions: z VDDIN = VDDIO = VDDANA = 3.3V z ADC Clock frequency = 1.0MHz z ADC sample rate: 125ksps z ADC sampling time: 57µs Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 892 z ADC mode: Free running mode, ADC averaging mode with 4 averaged samples z Data computed on the average of 10 ADC conversions z ADC voltage reference= 1.0V internal reference (INT1V) z ADC input = temperature sensor Table 39-28. Temperature Log Row Content Bit Position Name Description 07:00 ROOM_TEMP_VAL_INT Integer part of room temperature in °C 11:08 ROOM_TEMP_VAL_DEC Decimal part of room temperature 19:12 HOT_TEMP_VAL_INT Integer part of hot temperature in °C 23:20 HOT_TEMP_VAL_DEC Decimal part of hot temperature 31:24:00 ROOM_INT1V_VAL 2’s complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) 39:32:00 HOT_INT1V_VAL 2’s complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) 51:40:00 ROOM_ADC_VAL 12bit ADC conversion at room temperature 63:52:00 HOT_ADC_VAL 12bit ADC conversion at hot temperature The temperature sensor values are logged during test production flow for Room and Hot insertions: z ROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contains the measured temperature at room insertion (e.g. for ROOM_TEMP_VAL_INT=25 and ROOM_TEMP_VAL_DEC=2, the measured temperature at room insertion is 25.2°C). z HOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contains the measured temperature at hot insertion (e.g. for HOT_TEMP_VAL_INT=83 and HOT_TEMP_VAL_DEC=3, the measured temperature at room insertion is 83.3°C). The temperature log row also contains the corresponding 12bit ADC conversions of both Room and Hot temperatures: z ROOM_ADC_VAL contains the 12bit ADC value corresponding to (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) z HOT_ADC_VAL contains the 12bit ADC value corresponding to (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) The temperature log row also contains the corresponding 1V internal reference of both Room and Hot temperatures: z ROOM_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) z HOT_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) z ROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In other words, the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1, -127] corresponds to [1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 893 Using Linear Interpolation For concise equations, we’ll use the following notations: z (ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) is denoted tempR z (HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) is denoted tempH z ROOM_ADC_VAL is denoted ADCR, its conversion to Volt is denoted VADCR z HOT_ADC_VAL is denoted ADCH, its conversion to Volt is denoted VADCH z ROOM_INT1V_VAL is denoted INT1VR z HOT_INT1V_VAL is denoted INT1VH Using the (tempR, ADCR) and (tempH, ADCH) points, using a linear interpolation we have the following equation: V ADC – V ADCR⎞ V ADCH – V ADCR⎞ ⎛ ---------------------------------- = ⎛ -------------------------------------⎝ temp – temp R ⎠ ⎝ temp H – temp R ⎠ Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature tempC as: [Equation 1] temp C INT1V ⎫ ⎧⎛ 1 -⎞ ⎛ --------------------R-⎞ ⎬ ⋅ ( temp H – temp R ) – ADC ⋅ ⎨ ⎝ ADC m ⋅ -------------------R 12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ = temp R + ---------------------------------------------------------------------------------------------------------------------------------------------------------INT1V H ⎞ ⎛ INT1V ⎫ ⎧⎛ - – ADC R ⋅ --------------------R-⎞ ⎬ ⎨ ⎝ ADC H ⋅ -------------------12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ Note 1: in the previous expression, we’ve added the conversion of the ADC register value to be expressed in V Note 2: this is a coarse value because we assume INT1V=1V for this ADC conversion. Using the (tempR, INT1VR) and (tempH, INT1VH) points, using a linear interpolation we have the following equation: INT1V – INT1V R⎞ INT1V H – INT1V R⎞ ⎛ ------------------------------------------ = ⎛ ---------------------------------------------⎝ temp – temp R ⎠ ⎝ temp H – temp R ⎠ Then using the coarse temperature value, we can infer a closer to reality INT1V value during the ADC conversion as: ( INT1V H – INT1V R ) ⋅ ( temp C – temp R ) INT1V m = INT1V R + ⎛ --------------------------------------------------------------------------------------------------⎞ ⎝ ⎠ ( temp H – temp R ) Back to [Equation 1], we replace INT1V=1V by INT1V = INT1Vm, we can then deduce a finer temperature value as: [Equation 1bis] Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 894 INT1V m ⎞ ⎛ INT1V ⎫ ⎧⎛ - – ADC R ⋅ --------------------R-⎞ ⎬ ⋅ ( temp H – temp R ) ⎨ ⎝ ADC m ⋅ -------------------12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ temp f = temp R + ---------------------------------------------------------------------------------------------------------------------------------------------------------INT1V H ⎞ ⎛ INT1V ⎫ ⎧⎛ - – ADC R ⋅ --------------------R-⎞ ⎬ ⎨ ⎝ ADC H ⋅ -------------------12 12 ⎠ ⎝ ⎠ (2 – 1) (2 – 1) ⎭ ⎩ A.10 NVM Characteristics Table 39-29. Maximum Operating Frequency VDD range 1.62V to 2.7V 2.7V to 3.63V NVM Wait States Maximum Operating Frequency 0 14 1 28 2 42 3 48 0 24 1 48 Units MHz Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this number is reached, a row erase is mandatory. Table 39-30. Flash Endurance and Data Retention Symbol Parameter Conditions Min. Typ. Max. Units RetNVM25k Retention after up to 25k Average ambient 55°C 10 50 - Years RetNVM2.5k Retention after up to 2.5k Average ambient 55°C 20 100 - Years RetNVM100 Retention after up to 100 Average ambient 55°C 25 >100 - Years CycNVM Cycling Endurance(1) -40°C < Ta < 105°C 25k 150k - Cycles Min. Typ. Max. Units Note: 1. An endurance cycle is a write and an erase operation. Table 39-31. EEPROM Emulation(1) Endurance and Data Retention Symbol Parameter Conditions RetEEPROM100k Retention after up to 100k Average ambient 55°C 10 50 - Years RetEEPROM10k Retention after up to 10k Average ambient 55°C 20 100 - Years 100k 600k - Cycles CycEEPROM Notes: Cycling Endurance 1. 2. (2) -40°C < Ta < 105°C The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle is a write and an erase operation. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 895 Table 39-32. NVM Characteristics Symbol Parameter Conditions Min. Typ. Max. Units tFPP Page programming time - - - 2.5 ms tFRE Row erase time I - - - 6 ms tFCE DSU chip erase time (CHIP_ERASE) - - - 240 ms A.11 Oscillators Characteristics A.11.1 Crystal Oscillator (XOSC) Characteristics Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 39-33. Digital Clock Characteristics Symbol fCPXIN Parameter Conditions XIN clock frequency Min. Typ. Max. Units - - 32 MHz Digital mode Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure 39-5. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: C LEXT = 2 ( C L – C STRAY – C SHUNT ) where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal. Table 39-34. Crystal Oscillator Characteristics Symbol fOUT Parameter Crystal oscillator frequency Conditions I Min. Typ. Max. Units 0.4 - 32 MHz Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 896 Table 39-34. Crystal Oscillator Characteristics (Continued) Symbol ESR CXIN Parameter Crystal Equivalent Series Resistance Safety Factor = 3 Conditions Min. Typ. Max. Units f = 0.455MHz, CL = 100pF XOSC.GAIN = 0 - - 5.6K f = 2MHz, CL = 20pF XOSC.GAIN = 0 - - 416 f = 4MHz, CL = 20pF XOSC.GAIN = 1 - - 243 f = 8MHz, CL = 20pF XOSC.GAIN = 2 - - 138 f = 16MHz, CL = 20pF XOSC.GAIN = 3 - - 66 f = 32MHz, CL = 18pF XOSC.GAIN = 4 - - 56 - 6.5 - pF - 4.3 - pF f = 2MHz, CL = 20pF, AGC off 65 87 f = 2MHz, CL = 20pF, AGC on 52 76 f = 4MHz, CL = 20pF, AGC off 117 155 f = 4MHz, CL = 20pF, AGC on 74 104 f = 8MHz, CL = 20pF, AGC off 226 308 f = 8MHz, CL = 20pF, AGC on 128 180 f = 16MHz, CL = 20pF, AGC off 502 714 f = 16MHz, CL = 20pF, AGC on 307 590 f = 32MHz, CL = 18pF, AGC off 1622 2257 f = 32MHz, CL = 18pF, AGC on 615 1280 f = 2MHz, CL = 20pF, XOSC.GAIN = 0, ESR = 600Ω 14K 48K f = 4MHz, CL = 20pF, XOSC.GAIN = 1, ESR = 100Ω 6800 19.5K f = 8MHz, CL = 20pF, XOSC.GAIN = 2, ESR = 35Ω 5550 13K f = 16MHz, CL = 20pF, XOSC.GAIN = 3, ESR = 25Ω 6750 14.5K f = 32MHz, CL = 18pF, XOSC.GAIN = 4, ESR = 40Ω 5.3K 9.6K Ω Parasitic capacitor load I CXOUT IXOSC tSTARTUP Parasitic capacitor load Current Consumption Startup time µA cycles Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 897 Figure 39-5. Oscillator Connection Xin C LEXT Crystal LM C SHUNT RM C STRAY CM Xout C LEXT A.11.2 External 32kHz Crystal Oscillator (XOSC32K) Characteristics Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin. Table 39-35. Digital Clock Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fCPXIN32 XIN32 clock frequency Digital mode - 32.768 - kHz I XIN32 clock duty cycle I Digital mode - 50 - % Crystal Oscillator Characteristics Figure 39-5 and the equation in “Crystal Oscillator Characteristics” on page 896 also applies to the 32kHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 898 Table 39-36. 32kHz Crystal Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max. Units fOUT Crystal oscillator frequency I - 32768 tSTARTUP Startup time ESRXTAL = 39.9kΩ, CL = 12.5pF - 28K 30K CL Crystal load capacitance I - - 12.5 CSHUNT Crystal shunt capacitance I - 0.1 CXIN32 Parasitic capacitor load - 6.5 CXOUT32 Parasitic capacitor load - 4.3 IXOSC32K Current consumption - 1.22 2.2 µA ESR Crystal equivalent series resistance f=32.768kHz Safety Factor = 3 - - 100 kΩ Min. Typ. Max. Units DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 47 48 49 MHz - 403 453 µA 8 9 µs SOIC20/14 packages CL=12.5pF Hz cycles pF A.11.3 Digital Frequency Locked Loop (DFLL48M) Characteristics Table 39-37. DFLL48M Characteristics - Open Loop Mode(1) Symbol Parameter Conditions I fOUT Output frequency IDFLL Power consumption on VDDIN DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 Startup time DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 fOUT within 90% of final value I tSTARTUP Note: 1. DFLL48M in Open loop after calibration at room temperature. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 899 Table 39-38. DFLL48M Characteristics - Close Loop Mode(1) Symbol Parameter Conditions Min. Typ. Max. Units fOUT Average Output frequency fREF = 32.768kHz 47.76 48 48.24 MHz fREF Reference frequency I 0.732 32.768 33 kHz Jitter Cycle to Cycle jitter fREF = 32.768kHz - - 0.42 ns IDFLL Power consumption on VDDIN fREF = 32.768kHz - 403 453 µA Lock time fREF = 32.768kHz DFLLVAL.COARSE = DFLL48M COARSE CAL DFLLVAL.FINE = 512 DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10 200 500 µs tLOCK Note: 1. To insure that the device stays within the maximum allowed clock frequency, any reference clock for DFLL in close loop must be within a 2% error accuracy. A.11.4 32.768kHz Internal oscillator (OSC32K) Characteristics Table 39-39. 32kHz RC Oscillator Characteristics Symbol fOUT Parameter Output frequency Conditions Min. Typ. Max. Calibrated against a 32.768kHz reference at 25°C, over [-40, +105]°C, over [1.62, 3.63]V 30.3 32.768 34.4 Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 32.6 32.768 32.8 Calibrated against a 32.768kHz reference at 25°C, over [1.62, 3.63]V 32.4 32.768 33.1 Units kHz IOSC32K Current consumption I 0.67 1.9 µA tSTARTUP Startup time I 1 2 cycle Duty Duty Cycle I 50 % Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 900 A.11.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics Table 39-40. Ultra Low Power Internal 32kHz RC Oscillator Characteristics Symbol fOUT Parameter Output frequency Duty Duty Cycle Conditions Min. Typ. Max. Calibrated against a 32.768kHz reference at 25°C, over [-40, +105]°C, over [1.62, 3.63]V 27.8 32.768 38.3 Calibrated against a 32.768kHz reference at 25°C, at VDD=3.3V 32.5 32.768 32.8 Calibrated against a 32.768kHz reference at 25°C, over [1.62, 3.63]V 31.9 32.768 33.1 50 I Units kHz % A.11.6 Multi RC Oscillator (OSC8M) Characteristics Table 39-41. Multi RC Oscillator Characteristics Symbol Parameter Conditions Min. Typ. Max. Calibrated against a 8MHz reference at 25°C, over [-40, +105]°C, over [1.62, 3.63]V 7.8 8 8.16 Calibrated against a 8MHz reference at 25°C, at VDD=3.3V 7.94 8 8.06 Calibrated against a 8MHz reference at 25°C, over [1.62, 3.63]V 7.92 8 8.08 Units I fOUT Output frequency TempCo Freq vs. temperature drift SupplyCo Freq vs supply drift IOSC8M Current consumption IDLEIDLE2 on OSC32K versus IDLE2 on calibrated OSC8M enabled at 8MHz (FRANGE=1, PRESC=0) tSTARTUP Startup time Duty Duty cycle MHz -2.3 1.6 % -1 1 % 64 96 µA I 2.4 3.3 µs I 50 % A.11.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics Table 39-42. FDPLL96M Characteristics(1) Symbol Parameter Conditions Min. Typ. Max. Units fIN Input frequency 32 - 2000 KHz fOUT Output frequency 48 - 96 MHz IFDPLL96M Current consumption fIN= 32 kHz, fOUT= 48 MHz 400 733 fIN= 32 kHz, fOUT= 96 MHz 650 1235 µA Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 901 Symbol Parameter Jp Conditions Period jitter tLOCK Lock Time Duty Min. Typ. Max. fIN= 32 kHz, fOUT= 48 MHz 1.5 2 fIN= 32 kHz, fOUT= 96 MHz 3.0 10 fIN= 2 MHz, fOUT= 48 MHz 1.3 2 fIN= 2 MHz, fOUT= 96 MHz 3.0 7 After startup, time to get lock signal. fIN= 32 kHz, fOUT= 96 MHz 1.3 2 ms fIN= 2 MHz, fOUT= 96 MHz 25 50 µs 50 60 % Duty cycle Note: 1. 40 Units % All values have been characterized with FILTSEL[1/0] as default value. A.12 PTC Typical Characteristics Figure 39-6. Power consumption [µA]. 1 sensor, Frequency mode = None, CPU Clk = 48MHz, PTC Clk = 4MHz, VDD=3.3V 160 140 Average Current [μA] 120 10ms 100 50ms 100ms 80 200ms 60 40 20 0 1 2 4 8 16 32 64 Sample Averaging Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 902 Figure 39-7. Power consumption [µA]. 1 sensor, Frequency mode = HOP, CPU Clk = 48MHz, PTC Clk = 2MHz, VDD=3.3V 200 180 rage Current Average Cu μA 160 140 10ms 120 50ms 100 100ms 80 200ms 200 60 40 20 0 1 2 4 8 16 32 64 Sample Averaging Figure 39-8. Power consumption [µA]. 10 sensors, Frequency mode = None, CPU Clk = 48MHz, PTC Clk = 4MHz, VDD=3.3V 900 800 Average Current μA 700 10ms 600 50ms 500 100ms 400 200ms 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 903 Figure 39-9. Power consumption [µA]. 10 sensors, Frequency mode = HOP, CPU Clk = 48MHz, PTC Clk = 2MHz, VDD=3.3V 900 800 Average Current μA 700 10ms 600 50ms 500 100ms 400 200ms 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Figure 39-10.Power consumption [µA]. 50 sensors, Frequency mode = None, CPU Clk = 48MHz, PTC Clk = 4MHz, VDD=3.3V 1000 900 Average Current nt μA 800 700 50ms 600 100ms 500 200ms 400 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 904 Figure 39-11.Power consumption [µA]. 50 sensors, Frequency mode = HOP, CPU Clk = 48MHz, PTC Clk = 2MHz, VDD=3.3V 1000 900 Average Current rrent μ μA 800 700 50ms 600 100ms 500 200ms 400 300 200 100 0 1 2 4 8 16 32 64 Sample Averaging Figure 39-12.CPU utilization. 80 % 70 % 60 % 50 % Channel count 1 40 % Channel count 10 30 % Channel count 100 20 % 10 % 0% 10 50 100 200 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 905 A.13 Timing Characteristics A.13.1 External Reset Table 39-43. External reset characteristics Symbol tEXT Parameter Condition Minimum reset pulse width I Min. Typ. Max. Units 10 - - ns A.13.2 SERCOM in SPI Mode Timing Figure 39-13.SPI timing requirements in master mode SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 906 Figure 39-14.SPI timing requirements in slave mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS MOSI (Data Input) tSIH MSB tSOSSS MISO (Data Output) tSSCK LSB tSOS MSB tSOSSH LSB Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 907 Table 39-44. SPI timing characteristics and requirements(1) Symbol Parameter tSCK SCK period Master tSCKW SCK high/low width Master - 0.5*tSCK - tSCKR SCK rise time(2) Master - - - tSCKF SCK fall time(2) Master - - - tMIS MISO setup to SCK Master - 21 - tMIH MISO hold after SCK Master - 13 - tMOS MOSI setup SCK Master - tSCK/2 - 3 - tMOH MOSI hold after SCK Master - 3 - tSSCK Slave SCK Period Slave 1*tCLK_APB - - tSSCKW SCK high/low width Slave 0.5*tSSCK - - tSSCKR SCK rise time(2) Slave - - - tSSCKF SCK fall time(2) Slave - - - tSIS MOSI setup to SCK Slave tSSCK/2 - 9 - - tSIH MOSI hold after SCK Slave tSSCK/2 - 3 - - PRELOADEN=1 2*tCLK_APB + tSOS - - PRELOADEN=0 tSOS+7 - - tSSS SS setup to SCK Conditions Slave Min. Typ. Max. 84 tSSH SS hold after SCK Slave tSIH - 4 - - tSOS MISO setup SCK Slave - tSSCK/2 - 18 - tSOH MISO hold after SCK Slave - 18 - tSOSS MISO setup after SS low Slave - 18 - MISO hold after SS high Slave - 10 - tSOSH Notes: 1. 2. Units ns These values are based on simulation. These values are not covered by test limits in production. See “I/O Pin Characteristics” on page 812 A.13.3 SERCOM in I2C Mode Timing Table 34-48 describes the requirements for devices connected to the I2C Interface Bus. Timing symbols refer to Figure 34-16. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 908 Figure 39-15. I2C Interface Bus Timing tHIGH tOF tR tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF Table 39-45. I2C Interface Timing(1) Symbol Parameter Rise time for both SDA and SCL(3) tR Conditions Min. Typ. Max. Standard / Fast mode Cb(2) = 400pF - 230 350 Fast mode + Cb(2) = 550pF - 60 100 High speed mode Cb(2) = 100pF - 30 60 Cb(2) Standard / Fast mode 10pF < < 400pF - 25 50 Fast mode + 10pF < Cb(2) < 550pF - 20 30 High speed mode 10pF < Cb(2) < 100pF - 10 20 Hold time (repeated) START condition fSCL > 100kHz, Master tLOW-9 - - tLOW Low period of SCL Clock fSCL > 100kHz 113 - - tBUF Bus free time between a STOP and a START condition fSCL > 100kHz tLOW - - tSU;STA Setup time for a repeated START condition fSCL > 100kHz, Master tLOW+7 - - tHD;DAT Data hold time fSCL > 100kHz, Master 9 - 12 tSU;DAT Data setup time fSCL > 100kHz, Master 104 - - tSU;STO Setup time for STOP condition fSCL > 100kHz, Master tLOW+9 - - tSU;DAT;Rx Data setup time (receive mode) fSCL > 100kHz, Slave 51 - 56 tHD;DAT;Tx Data hold time (send mode) fSCL > 100kHz, Slave 71 90 138 Output fall time from VIHmin to VILmax (3) tOF tHD;STA Notes: 1. 2. 3. Units ns These values are based on simulation. These values are not covered by test limits in production. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF. These values are based on characterization. These values are not covered by test limits in production. Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 909 Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 2.5 SAM D10C – 14-pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM D10D – 20-pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM D10D – 20-ball WLCSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAM D10D – 24-pin QFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 6 6 6 3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 4.2 4.3 4.4 SAM D10C 14-pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SAM D10D 20-pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SAM D10D 20-ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SAM D10D 24-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. Signal Descriptions List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. I/O Multiplexing and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 6.2 Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. Power Supply and Start-Up Considerations . . . . . . . . . . . . . . . . . . . 17 7.1 7.2 7.3 7.4 Power Domain Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset and Brown-Out Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 18 19 8. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1 9.2 9.3 9.4 9.5 9.6 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Calibration and Auxiliary Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM User Row Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Software Calibration Row Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 23 24 24 10. Processor And Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.1 10.2 10.3 10.4 10.5 10.6 Cortex M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nested Vector Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Speed Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AHB-APB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAC – Peripheral Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 26 27 30 30 31 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 910 11. Peripherals Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . 37 12. DSU – Device Service Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intellectual Property Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 39 40 40 41 42 43 43 44 45 50 53 13. Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous and Asynchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling a Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-demand, Clock Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption vs Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks after Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 81 81 85 86 86 86 14. GCLK – Generic Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 88 88 89 89 90 95 96 15. PM – Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 110 111 111 111 113 121 122 16. SYSCTRL – System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 143 16.1 16.2 16.3 16.4 16.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 143 145 147 147 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 911 16.6 16.7 16.8 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 17. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 208 208 209 209 210 215 216 18. RTC – Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 227 227 228 228 230 235 238 19. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . 271 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 271 272 272 272 273 292 295 20. EIC – External Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . 336 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 336 336 337 337 338 342 343 21. NVMCTRL – Non-Volatile Memory Controller . . . . . . . . . . . . . . . . 355 21.1 21.2 21.3 21.4 21.5 21.6 21.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 355 355 355 356 356 362 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 912 21.8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 22. PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 378 379 379 379 381 386 388 23. EVSYS – Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 405 406 406 406 407 412 413 24. SERCOM – Serial Communication Interface . . . . . . . . . . . . . . . . . 430 24.1 24.2 24.3 24.4 24.5 24.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 430 430 430 431 432 25. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter 438 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 438 439 439 439 441 452 454 26. SERCOM SPI – SERCOM Serial Peripheral Interface . . . . . . . . . 476 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 476 476 476 477 478 487 489 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 913 27. SERCOM I2C – SERCOM Inter-Integrated Circuit . . . . . . . . . . . . 509 27.1 27.2 27.3 27.4 27.5 27.6 27.7 27.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 509 509 510 510 511 529 534 28. TC – Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 28.1 28.2 28.3 28.4 28.5 28.6 28.7 28.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 573 574 575 575 576 587 590 29. TCC – Timer/Counter for Control Applications . . . . . . . . . . . . . . . 614 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 614 615 615 616 617 647 650 30. ADC – Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . 714 30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 714 715 715 716 717 727 729 31. AC – Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 31.1 31.2 31.3 31.4 31.5 31.6 31.7 31.8 31.9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 753 754 754 754 756 762 765 766 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 914 32. DAC – Digital-to-Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . 782 32.1 32.2 32.3 32.4 32.5 32.6 32.7 32.8 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 782 782 782 783 784 788 789 33. PTC - Peripheral Touch Controller . . . . . . . . . . . . . . . . . . . . . . . . 799 33.1 33.2 33.3 33.4 33.5 33.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 799 800 801 801 803 34. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 34.1 34.2 34.3 34.4 34.5 34.6 34.7 34.8 34.9 34.10 34.11 34.12 34.13 34.14 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Injection Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PTC Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 804 804 805 805 807 810 812 814 816 828 830 836 840 35. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 35.1 35.2 35.3 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 36. Schematic Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 36.1 36.2 36.3 36.4 36.5 36.6 36.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Analog Reference Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused or Unconnected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming and Debug Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 850 851 853 853 853 856 37. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 37.1 37.2 Revision A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 Revision B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 915 38. About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 38.1 38.2 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868 39. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 Rev. H – 08/2016 Rev. G – 05/2016 Rev. F – 04/2016 Rev. E – 03/2016 Rev. D – 02/2016 Rev. C – 01/2016 Rev. B – 07/2015 Rev. A – 01/2015 ............................................. ............................................. ............................................. ............................................. ............................................. ............................................. ............................................. ............................................. 871 872 873 873 873 874 874 875 Appendix A. Electrical Characteristics at 105°C. . . . . . . . . . . . . . . . . . 876 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Injection Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PTC Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 876 876 877 877 878 881 883 884 895 896 902 906 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 Atmel | SMART SAM D10 [DATASHEET] Atmel-42242H-SAM-D10-Datasheet_09/2016 916 ARM Connected Logo XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2016 Atmel Corporation. / Rev.: Atmel-42242H-SAM-D10-Datasheet_09/2016. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®, ARM Connected® logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.

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