SMART ARM-Based Microcontrollers
SAM D20E / SAM D20G / SAM D20J
DATASHEET COMPLETE
Introduction
®
™
Atmel | SMART SAM D20 is a series of low-power microcontrollers using
®
®
the 32-bit ARM Cortex -M0+ processor, and ranging from 32- to 64-pins
with up to 256KB Flash and 32KB of SRAM. The SAM D20 devices operate
®
at a maximum frequency of 48MHz and reach 2.46 CoreMark /MHz. They
are designed for simple and intuitive migration with identical peripheral
modules, hex compatible code, identical linear address map and pin
compatible migration paths between all devices in the product series. All
devices include intelligent and flexible peripherals, Atmel Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and
wheel user interfaces.
Features
•
•
•
•
•
Processor
– ARM Cortex-M0+ CPU running at up to 48MHz
• Single-cycle hardware multiplier
Memories
– 16/32/64/128/256KB in-system self-programmable Flash
– 2/4/8/16/32KB SRAM Memory
System
– Power-on reset (POR) and brown-out detection (BOD)
– Internal and external clock options with 48MHz Digital Frequency
Locked Loop (DFLL48M)
– External Interrupt Controller (EIC)
– 16 external interrupts
– One non-maskable interrupt
– Two-pin Serial Wire Debug (SWD) programming, test and
debugging interface
Low Power
– Idle and standby sleep modes
– SleepWalking peripherals
Peripherals
– 8-channel Event System
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
–
–
–
–
–
–
–
–
–
•
•
•
•
Up to five 16-bit Timer/Counters (TC), configurable as either:
• One 16-bit TC with two compare/capture channels
• One 8-bit TC with two compare/capture channels
• One 32-bit TC with two compare/capture channels, by using two TCs
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as
either:
• USART with full-duplex and single-wire half-duplex configuration
• Inter-Integrated Circuit (I2C) up to 400kHz
• Serial Peripheral Interface (SPI)
One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
• Differential and single-ended input
• 1/2x to 16x programmable gain stage
• Automatic offset and gain error compensation
• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
10-bit, 350ksps Digital-to-Analog Converter (DAC)
Two Analog Comparators (AC) with window compare function
Peripheral Touch Controller (PTC)
• 256-Channel capacitive touch and proximity sensing
I/O
– Up to 52 programmable I/O pins
Packages
– 64-pin TQFP, QFN
– 64-ball UFBGA
– 48-pin TQFP, QFN
– 45-ball WLCSP
– 32-pin TQFP, QFN
Operating Voltage
– 1.62V – 3.63V
Power Consumption
– Down to 70µA/MHz in active mode
– Down to 8µA running the Peripheral Touch Controller
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
2
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description...............................................................................................................10
2. Configuration Summary........................................................................................... 11
3. Ordering Information................................................................................................12
3.1.
3.2.
3.3.
3.4.
SAM D20E..................................................................................................................................12
SAM D20G................................................................................................................................. 14
SAM D20J.................................................................................................................................. 15
Device Identification................................................................................................................... 17
4. Block Diagram......................................................................................................... 19
5. Pinout.......................................................................................................................20
5.1.
5.2.
5.3.
SAM D20J.................................................................................................................................. 20
SAM D20G................................................................................................................................. 22
SAM D20E..................................................................................................................................24
6. Signal Descriptions List........................................................................................... 25
7. I/O Multiplexing and Considerations........................................................................ 27
7.1.
7.2.
Multiplexed Signals.....................................................................................................................27
Other Functions..........................................................................................................................29
8. Power Supply and Start-Up Considerations............................................................ 31
8.1.
8.2.
8.3.
Power Domain Overview............................................................................................................31
Power Supply Considerations.................................................................................................... 31
Power-Up....................................................................................................................................33
8.4.
Power-On Reset and Brown-Out Detector................................................................................. 33
9. Product Mapping......................................................................................................35
10. Memories.................................................................................................................36
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
Embedded Memories................................................................................................................. 36
Physical Memory Map................................................................................................................ 36
NVM Calibration and Auxiliary Space.........................................................................................37
NVM User Row Mapping............................................................................................................37
NVM Software Calibration Area Mapping...................................................................................38
Serial Number.............................................................................................................................39
11. Processor And Architecture..................................................................................... 40
11.1. Cortex M0+ Processor................................................................................................................40
11.2. Nested Vector Interrupt Controller..............................................................................................41
11.3. High-Speed Bus System............................................................................................................ 43
11.4. AHB-APB Bridge........................................................................................................................ 44
11.5. PAC - Peripheral Access Controller............................................................................................45
11.6. Register Description................................................................................................................... 46
12. Peripherals Configuration Summary........................................................................59
13. DSU - Device Service Unit...................................................................................... 61
13.1. Overview.....................................................................................................................................61
13.2. Features..................................................................................................................................... 61
13.3. Block Diagram............................................................................................................................ 62
13.4. Signal Description.......................................................................................................................62
13.5. Product Dependencies............................................................................................................... 62
13.6. Debug Operation........................................................................................................................ 63
13.7. Chip Erase..................................................................................................................................65
13.8. Programming..............................................................................................................................65
13.9. Intellectual Property Protection...................................................................................................66
13.10. Device Identification................................................................................................................... 67
13.11. Functional Description................................................................................................................68
13.12. Register Summary..................................................................................................................... 74
13.13. Register Description...................................................................................................................76
14. Clock System.........................................................................................................100
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
14.7.
Clock Distribution......................................................................................................................100
Synchronous and Asynchronous Clocks..................................................................................101
Register Synchronization..........................................................................................................101
Enabling a Peripheral............................................................................................................... 106
On-demand, Clock Requests................................................................................................... 106
Power Consumption vs. Speed................................................................................................ 107
Clocks after Reset.................................................................................................................... 107
15. GCLK - Generic Clock Controller.......................................................................... 108
15.1. Overview...................................................................................................................................108
15.2. Features................................................................................................................................... 108
15.3.
15.4.
15.5.
15.6.
15.7.
15.8.
Block Diagram.......................................................................................................................... 108
Signal Description.....................................................................................................................109
Product Dependencies............................................................................................................. 109
Functional Description.............................................................................................................. 110
Register Summary.................................................................................................................... 115
Register Description................................................................................................................. 116
16. PM – Power Manager............................................................................................129
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
Overview...................................................................................................................................129
Features................................................................................................................................... 129
Block Diagram.......................................................................................................................... 130
Signal Description.....................................................................................................................130
Product Dependencies............................................................................................................. 130
Functional Description..............................................................................................................132
Register Summary....................................................................................................................140
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
4
16.8. Register Description................................................................................................................. 140
17. SYSCTRL – System Controller............................................................................. 162
17.1.
17.2.
17.3.
17.4.
17.5.
17.6.
17.7.
17.8.
Overview...................................................................................................................................162
Features................................................................................................................................... 162
Block Diagram.......................................................................................................................... 164
Signal Description.....................................................................................................................164
Product Dependencies............................................................................................................. 165
Functional Description..............................................................................................................166
Register Summary....................................................................................................................178
Register Description................................................................................................................. 179
18. WDT – Watchdog Timer........................................................................................ 216
18.1.
18.2.
18.3.
18.4.
18.5.
18.6.
18.7.
18.8.
Overview...................................................................................................................................216
Features................................................................................................................................... 216
Block Diagram.......................................................................................................................... 217
Signal Description.....................................................................................................................217
Product Dependencies............................................................................................................. 217
Functional Description..............................................................................................................218
Register Summary....................................................................................................................223
Register Description................................................................................................................. 223
19. RTC – Real-Time Counter..................................................................................... 234
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
Overview...................................................................................................................................234
Features................................................................................................................................... 234
Block Diagram.......................................................................................................................... 235
Signal Description.....................................................................................................................235
Product Dependencies............................................................................................................. 235
Functional Description..............................................................................................................237
Register Summary....................................................................................................................243
Register Description................................................................................................................. 245
20. EIC – External Interrupt Controller........................................................................ 278
20.1.
20.2.
20.3.
20.4.
20.5.
20.6.
20.7.
20.8.
Overview...................................................................................................................................278
Features................................................................................................................................... 278
Block Diagram.......................................................................................................................... 278
Signal Description.....................................................................................................................279
Product Dependencies............................................................................................................. 279
Functional Description..............................................................................................................280
Register Summary....................................................................................................................285
Register Description................................................................................................................. 285
21. NVMCTRL – Non-Volatile Memory Controller....................................................... 297
21.1.
21.2.
21.3.
21.4.
21.5.
21.6.
Overview...................................................................................................................................297
Features................................................................................................................................... 297
Block Diagram.......................................................................................................................... 297
Signal Description.....................................................................................................................297
Product Dependencies............................................................................................................. 298
Functional Description..............................................................................................................299
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
5
21.7. Register Summary....................................................................................................................306
21.8. Register Description................................................................................................................. 306
22. PORT - I/O Pin Controller...................................................................................... 320
22.1.
22.2.
22.3.
22.4.
22.5.
22.6.
22.7.
22.8.
Overview...................................................................................................................................320
Features................................................................................................................................... 320
Block Diagram.......................................................................................................................... 321
Signal Description.....................................................................................................................321
Product Dependencies............................................................................................................. 321
Functional Description..............................................................................................................324
Register Summary....................................................................................................................329
Register Description................................................................................................................. 331
23. EVSYS – Event System........................................................................................ 349
23.1.
23.2.
23.3.
23.4.
23.5.
23.6.
23.7.
23.8.
Overview...................................................................................................................................349
Features................................................................................................................................... 349
Block Diagram.......................................................................................................................... 349
Signal Description.....................................................................................................................350
Product Dependencies............................................................................................................. 350
Functional Description..............................................................................................................351
Register Summary....................................................................................................................357
Register Description................................................................................................................. 357
24. SERCOM – Serial Communication Interface.........................................................369
24.1.
24.2.
24.3.
24.4.
24.5.
24.6.
Overview...................................................................................................................................369
Features................................................................................................................................... 369
Block Diagram.......................................................................................................................... 370
Signal Description.....................................................................................................................370
Product Dependencies............................................................................................................. 370
Functional Description..............................................................................................................372
25. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver
and Transmitter......................................................................................................377
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
25.7.
25.8.
Overview...................................................................................................................................377
USART Features...................................................................................................................... 377
Block Diagram.......................................................................................................................... 378
Signal Description.....................................................................................................................378
Product Dependencies............................................................................................................. 378
Functional Description..............................................................................................................380
Register Summary....................................................................................................................388
Register Description................................................................................................................. 388
26. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................405
26.1.
26.2.
26.3.
26.4.
26.5.
26.6.
Overview...................................................................................................................................405
Features................................................................................................................................... 405
Block Diagram.......................................................................................................................... 406
Signal Description.....................................................................................................................406
Product Dependencies............................................................................................................. 406
Functional Description..............................................................................................................408
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
6
26.7. Register Summary....................................................................................................................416
26.8. Register Description................................................................................................................. 416
27. SERCOM I2C – SERCOM Inter-Integrated Circuit................................................ 431
27.1. Overview...................................................................................................................................431
27.2. Features................................................................................................................................... 431
27.3. Block Diagram.......................................................................................................................... 432
27.4. Signal Description.....................................................................................................................432
27.5. Product Dependencies............................................................................................................. 432
27.6. Functional Description..............................................................................................................434
27.7. Register Summary - I2C Slave.................................................................................................451
27.8. Register Description - I2C Slave...............................................................................................451
27.9. Register Summary - I2C Master...............................................................................................463
27.10. Register Description - I2C Master.............................................................................................463
28. TC – Timer/Counter............................................................................................... 478
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
Overview...................................................................................................................................478
Features................................................................................................................................... 478
Block Diagram.......................................................................................................................... 479
Signal Description.....................................................................................................................479
Product Dependencies............................................................................................................. 480
Functional Description..............................................................................................................481
Register Summary....................................................................................................................491
Register Description................................................................................................................. 493
29. ADC – Analog-to-Digital Converter........................................................................520
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
29.7.
29.8.
Overview...................................................................................................................................520
Features................................................................................................................................... 520
Block Diagram.......................................................................................................................... 521
Signal Description.....................................................................................................................521
Product Dependencies............................................................................................................. 522
Functional Description..............................................................................................................523
Register Summary....................................................................................................................532
Register Description................................................................................................................. 533
30. AC – Analog Comparators.....................................................................................558
30.1.
30.2.
30.3.
30.4.
30.5.
30.6.
30.7.
30.8.
Overview...................................................................................................................................558
Features................................................................................................................................... 558
Block Diagram.......................................................................................................................... 559
Signal Description.....................................................................................................................559
Product Dependencies............................................................................................................. 559
Functional Description..............................................................................................................560
Register Summary....................................................................................................................569
Register Description................................................................................................................. 570
31. DAC – Digital-to-Analog Converter........................................................................586
31.1. Overview...................................................................................................................................586
31.2. Features................................................................................................................................... 586
31.3. Block Diagram.......................................................................................................................... 586
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
7
31.4. Signal Description.....................................................................................................................586
31.5.
31.6.
31.7.
31.8.
Product Dependencies............................................................................................................. 586
Functional Description..............................................................................................................588
Register Summary....................................................................................................................592
Register Description................................................................................................................. 592
32. PTC - Peripheral Touch Controller.........................................................................602
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
Overview...................................................................................................................................602
Features................................................................................................................................... 602
Block Diagram.......................................................................................................................... 603
Signal Description.....................................................................................................................604
Product Dependencies............................................................................................................. 604
Functional Description..............................................................................................................605
33. Electrical Characteristics....................................................................................... 606
33.1. Disclaimer.................................................................................................................................606
33.2. Absolute Maximum Ratings......................................................................................................606
33.3. General Operating Ratings.......................................................................................................607
33.4. Supply Characteristics..............................................................................................................607
33.5. Maximum Clock Frequencies................................................................................................... 608
33.6. Power Consumption................................................................................................................. 609
33.7. Peripheral Power Consumption................................................................................................ 611
33.8. I/O Pin Characteristics..............................................................................................................613
33.9. Injection Current....................................................................................................................... 615
33.10. Analog Characteristics............................................................................................................. 616
33.11. NVM Characteristics.................................................................................................................628
33.12. Oscillators Characteristics........................................................................................................629
33.13. PTC Typical Characteristics..................................................................................................... 634
33.14. Timing Characteristics..............................................................................................................637
34. Packaging Information...........................................................................................641
34.1. Thermal Considerations........................................................................................................... 641
34.2. Package Drawings....................................................................................................................642
34.3. Soldering Profile....................................................................................................................... 651
35. Schematic Checklist.............................................................................................. 652
35.1.
35.2.
35.3.
35.4.
35.5.
35.6.
35.7.
Introduction...............................................................................................................................652
Power Supply........................................................................................................................... 652
External Analog Reference Connections................................................................................. 653
External Reset Circuit...............................................................................................................654
Clocks and Crystal Oscillators..................................................................................................655
Unused or Unconnected Pins...................................................................................................659
Programming and Debug Ports................................................................................................659
36. Errata.....................................................................................................................663
36.1. Device Variant A....................................................................................................................... 663
37. Datasheet Revision History................................................................................... 688
37.1. Rev. O - 08/2016...................................................................................................................... 688
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
8
37.2. Rev. N - 01/2015.......................................................................................................................689
37.3. Rev. M - 12/2014...................................................................................................................... 689
37.4. Rev. L - 09/2014....................................................................................................................... 690
37.5. Rev. K – 05/2014...................................................................................................................... 692
37.6. Rev. J – 12/2013.......................................................................................................................695
37.7. Rev. I 12/2013......................................................................................................................... 695
37.8. Rev. H 10/2013........................................................................................................................704
37.9. Rev. G 10/2013.........................................................................................................................705
37.10. Rev. F 10/2013.........................................................................................................................706
37.11. Rev. E 09/2013......................................................................................................................... 706
37.12. Rev. D 08/2013.........................................................................................................................706
37.13. Rev. C – 07/2013......................................................................................................................707
37.14. Rev. B – 07/2013......................................................................................................................708
37.15. Rev. A 06/2013.........................................................................................................................709
38. Conventions...........................................................................................................710
38.1.
38.2.
38.3.
38.4.
Numerical Notation...................................................................................................................710
Memory Size and Type.............................................................................................................710
Frequency and Time.................................................................................................................710
Registers and Bits.....................................................................................................................711
39. Acronyms and Abbreviations.................................................................................712
40. Appendix A: Electrical Characteristics at 105°C....................................................715
40.1.
40.2.
40.3.
40.4.
40.5.
40.6.
40.7.
40.8.
40.9.
Disclaimer.................................................................................................................................715
Absolute Maximum Ratings......................................................................................................715
General Operating Ratings.......................................................................................................715
Maximum Clock Frequencies................................................................................................... 716
Power Consumption................................................................................................................. 717
Injection Current....................................................................................................................... 719
Analog Characteristics..............................................................................................................720
NVM Characteristics.................................................................................................................727
Oscillators Characteristics........................................................................................................728
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
9
1.
Description
®
™
®
®
The Atmel | SMART SAM D20 is a series of low-power microcontrollers using the 32-bit ARM Cortex M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and 32KB of SRAM. The SAM
D20 devices operate at a maximum frequency of 48MHz and reach 2.46 CoreMark/MHz. They are
designed for simple and intuitive migration with identical peripheral modules, hex compatible code,
identical linear address map and pin compatible migration paths between all devices in the product
series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral
signaling, and support for capacitive touch button, slider and wheel user interfaces.
The SAM D20 devices provide the following features: In-system programmable Flash, eight-channel
Event System, programmable interrupt controller, up to 52 programmable I/O pins, 32-bit real-time clock
and calendar, up to eight 16-bit Timer/Counters (TC) . The timer/counters can be configured to perform
frequency and waveform generation, accurate program execution timing or input capture with time and
frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be
cascaded to form a 32-bit TC. The series provide up to six Serial Communication Modules (SERCOM)
that each can be configured to act as an USART, UART, SPI, I2C up to 400kHz, up to twenty-channel
350ksps 12-bit ADC with programmable gain and optional oversampling and decimation supporting up to
16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with window mode, Peripheral Touch
Controller supporting up to 256 buttons, sliders, wheels and proximity sensing; programmable Watchdog
Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD) program and debug
interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a
source for the system clock. Different clock domains can be independently configured to run at different
frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus
maintaining a high CPU frequency while reducing power consumption.
The SAM D20 devices have two software-selectable sleep modes, idle and standby. In idle mode the
CPU is stopped while all other functions can be kept running. In standby all clocks and functions are
stopped expect those selected to continue running. The device supports SleepWalking. This feature
allows the peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to
wake up only when needed, e.g. when a threshold is crossed or a result is ready. The Event System
supports synchronous and asynchronous events, allowing peripherals to receive, react to and send
events even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same
interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the
device can use any communication interface to download and upgrade the application program in the
Flash memory.
The SAM D20 devices are supported with a full suite of program and system development tools, including
C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
10
2.
Configuration Summary
SAM D20J
SAM D20G
SAM D20E
Pins
64
48
32
General Purpose I/O-pins (GPIOs)
52
38
26
Flash
256/128/64/32KB
256/128/64/32KB
256/128/64/32KB
SRAM
32/16/8/4/2KB
32/16/8/4/2KB
32/16/8/4/2KB
Timer Counter (TC) instances
8
6
6
Waveform output channels per TC instance
2
2
2
Serial Communication Interface (SERCOM)
instances
6
6
4
Analog-to-Digital Converter (ADC) channels
20
14
10
Analog Comparators (AC)
2
2
2
Digital-to-Analog Converter (DAC) channels
1
1
1
Real-Time Counter (RTC)
Yes
Yes
Yes
RTC alarms
1
1
1
RTC compare values
One 32-bit value or One 32-bit value or One 32-bit value or
two 16-bit values
two 16-bit values
two 16-bit values
External Interrupt lines
16
16
16
Peripheral Touch Controller (PTC) X and Y lines
16x16
12x10
10x6
Maximum CPU frequency
48MHz
Packages
QFN
QFN
QFN
TQFP
TQFP
TQFP
UFBGA
WLCSP
Oscillators
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
32KHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
Event System channels
8
8
8
SW Debug Interface
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Yes
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
11
3.
Ordering Information
SAMD 20 E 14 A - M U T
Product Family
Package Carrier
SAMD = General Purpose Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
Package Grade
20 = Cortex M0+ CPU, Basic Feature Set
Pin Count
U = -40 - 85 C Matte Sn Plating
N = -40 - 105 C Matte Sn Plating
O
D = 25 Pins
E = 32 Pins
G = 48 Pins
J = 64 Pins
O
Package Type
Flash Memory Density
A = TQFP
M = QFN
C = UFBGA
U = WLCSP
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
14 = 16KB
Device Variant
A = Default Variant
3.1.
SAM D20E
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20E14A-AU
16K
2K
TQFP32
Tray
ATSAMD20E14A-AUT
Tape & Reel
ATSAMD20E14A-AN
Tray
ATSAMD20E14A-ANT
Tape & Reel
ATSAMD20E14A-MU
QFN32
Tray
ATSAMD20E14A-MUT
Tape & Reel
ATSAMD20E14A-MN
Tray
ATSAMD20E14A-MNT
Tape & Reel
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
12
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20E15A-AU
32K
4K
TQFP32
Tray
ATSAMD20E15A-AUT
Tape & Reel
ATSAMD20E15A-AN
Tray
ATSAMD20E15A-ANT
Tape & Reel
ATSAMD20E15A-MU
QFN32
Tray
ATSAMD20E15A-MUT
Tape & Reel
ATSAMD20E15A-MN
Tray
ATSAMD20E15A-MNT
Tape & Reel
ATSAMD20E16A-AU
64K
8K
TQFP32
Tray
ATSAMD20E16A-AUT
Tape & Reel
ATSAMD20E16A-AN
Tray
ATSAMD20E16A-AFT
Tape & Reel
ATSAMD20E16A-MU
QFN32
Tray
ATSAMD20E16A-MUT
Tape & Reel
ATSAMD20E16A-MN
Tray
ATSAMD20E16A-MNT
Tape & Reel
ATSAMD20E17A-AU
128K
16K
TQFP32
Tray
ATSAMD20E17A-AUT
Tape & Reel
ATSAMD20E17A-AN
Tray
ATSAMD20E17A-ANT
Tape & Reel
ATSAMD20E17A-MU
QFN32
Tray
ATSAMD20E17A-MUT
Tape & Reel
ATSAMD20E17A-MN
Tray
ATSAMD20E17A-MNT
Tape & Reel
ATSAMD20E18A-AU
256K
32K
TQFP32
Tray
ATSAMD20E18A-AUT
Tape & Reel
ATSAMD20E18A-AN
Tray
ATSAMD20E18A-AFT
Tape & Reel
ATSAMD20E18A-MU
QFN32
Tray
ATSAMD20E18A-MUT
Tape & Reel
ATSAMD20E18A-MN
Tray
ATSAMD20E18A-MNT
Tape & Reel
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
13
3.2.
SAM D20G
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20G14A-AU
16K
2K
TQFP32
Tray
ATSAMD20G14A-AUT
Tape & Reel
ATSAMD20G14A-AN
Tray
ATSAMD20G14A-ANT
Tape & Reel
ATSAMD20G14A-MU
QFN32
Tray
ATSAMD20G14A-MUT
Tape & Reel
ATSAMD20G14A-MN
Tray
ATSAMD20G14A-MNT
Tape & Reel
ATSAMD20G15A-AU
32K
4K
TQFP48
Tray
ATSAMD20G15A-AUT
Tape & Reel
ATSAMD20G15A-AN
Tray
ATSAMD20G15A-ANT
Tape & Reel
ATSAMD20G15A-MU
QFN48
Tray
ATSAMD20G15A-MUT
Tape & Reel
ATSAMD20G15A-MN
Tray
ATSAMD20G15A-MNT
Tape & Reel
ATSAMD20G16A-AU
64K
8K
TQFP48
Tray
ATSAMD20G16A-AUT
Tape & Reel
ATSAMD20G16A-AN
Tray
ATSAMD20G16A-ANT
Tape & Reel
ATSAMD20G16A-MU
QFN48
Tray
ATSAMD20G16A-MUT
Tape & Reel
ATSAMD20G16A-MN
Tray
ATSAMD20G16A-MNT
Tape & Reel
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
14
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20G17A-AU
128K
16K
TQFP48
Tray
ATSAMD20G17A-AUT
Tape & Reel
ATSAMD20G17A-AN
Tray
ATSAMD20G17A-ANT
Tape & Reel
ATSAMD20G17A-MU
QFN48
ATSAMD20G17A-MUT
Tape & Reel
ATSAMD20G17A-MN
Tray
ATSAMD20G17A-MNT
Tape & Reel
ATSAMD20G17A-UUT
ATSAMD20G18A-AU
256K
32K
WLCSP45
Tape & Reel
TQFP48
Tray
ATSAMD20G18A-AUT
Tape & Reel
ATSAMD20G18A-AN
Tray
ATSAMD20G18A-ANT
Tape & Reel
ATSAMD20G18A-MU
QFN48
Tray
ATSAMD20G18A-MUT
Tape & Reel
ATSAMD20G18A-MN
Tray
ATSAMD20G18A-MNT
Tape & Reel
ATSAMD20G18A-UUT
3.3.
Tray
WLCSP45
Tape & Reel
SAM D20J
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J14A-AU
16K
2K
TQFP64
Tray
ATSAMD20J14A-AUT
Tape & Reel
ATSAMD20J14A-AN
Tray
ATSAMD20J14A-ANT
Tape & Reel
ATSAMD20J14A-MU
QFN64
Tray
ATSAMD20J14A-MUT
Tape & Reel
ATSAMD20J14A-MN
Tray
ATSAMD20J14A-MNT
Tape & Reel
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
15
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J15A-AU
32K
4K
TQFP64
Tray
ATSAMD20J15A-AUT
Tape & Reel
ATSAMD20J15A-AN
Tray
ATSAMD20J15A-ANT
Tape & Reel
ATSAMD20J15A-MU
QFN64
Tray
ATSAMD20J15A-MUT
Tape & Reel
ATSAMD20J15A-MN
Tray
ATSAMD20J15A-MNT
Tape & Reel
ATSAMD20J16A-AU
64K
8K
TQFP64
Tray
ATSAMD20J16A-AUT
Tape & Reel
ATSAMD20J16A-AN
Tray
ATSAMD20J16A-ANT
Tape & Reel
ATSAMD20J16A-MU
QFN64
Tray
ATSAMD20J16A-MUT
Tape & Reel
ATSAMD20J16A-MN
Tray
ATSAMD20J16A-MNT
Tape & Reel
ATSAMD20J16A-CU
UFBGA64
ATSAMD20J16A-CUT
ATSAMD20J17A-AU
Tray
Tape & Reel
128K
16K
TQFP64
Tray
ATSAMD20J17A-AUT
Tape & Reel
ATSAMD20J17A-AN
Tray
ATSAMD20J17A-ANT
Tape & Reel
ATSAMD20J17A-MU
QFN64
Tray
ATSAMD20J17A-MUT
Tape & Reel
ATSAMD20J17A-MN
Tray
ATSAMD20J17A-MNT
Tape & Reel
ATSAMD20J17A-CU
ATSAMD20J17A-CUT
UFBGA64
Tray
Tape & Reel
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
16
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J18A-AU
256K
32K
TQFP64
Tray
ATSAMD20J18A-AUT
Tape & Reel
ATSAMD20J18A-AN
Tray
ATSAMD20J18A-ANT
Tape & Reel
ATSAMD20J18A-MU
QFN64
ATSAMD20J18A-MUT
Tape & Reel
ATSAMD20J18A-MN
Tray
ATSAMD20J18A-MNT
Tape & Reel
ATSAMD20J18A-CU
UFBGA64
ATSAMD20J18A-CUT
3.4.
Tray
Tray
Tape & Reel
Device Identification
The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification
register (DID.DEVSEL) in order to identify the device by software. The device variants have a reset value
of DID=0x1001drxx, with the LSB identifying the die number ('d'), the die revision ('r') and the device
selection ('xx').
Table 3-1. Device Identification Values
Device Variant
DID.DEVSEL
Device ID (DID)
SAMD20J18C
0x00
0x10001300
SAMD20J18A
0x00
0x10001300
SAMD20J17A
0x01
0x10001301
SAMD20J16A
0x02
0x10001302
SAMD20J15A
0x03
0x10001303
SAMD20J14A
0x04
0x10001304
SAMD20G18A
0x05
0x10001305
SAMD20G17A
0x06
0x10001306
SAMD20G16A
0x07
0x10001307
SAMD20G15A
0x08
0x10001308
SAMD20G14A
0x09
0x10001309
SAMD20E18A
0x0A
0x1000130A
SAMD20E17A
0x0B
0x1000130B
SAMD20E16A
0x0C
0x1000130C
SAMD20E15A
0x0D
0x1000130D
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
17
Device Variant
DID.DEVSEL
Device ID (DID)
SAMD20E14A
0x0E
0x1000130E
Reserved
0x0F
SAMD20G18U
0x10
0x10001310
SAMD20G17U
0x11
0x10001311
Reserved
0x12 - 0xFF
Note: The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks
evolution of the die. The device variant denotes functional differences, whereas the die revision marks
evolution of the die.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
18
Block Diagram
IOBUS
SWCLK
ARM CORTEX-M0+
PROCESSOR
Fmax 48MHz
SERIAL
WIRE
SWDIO
DEVICE
SERVICE
UNIT
256/128/64/32/16KB
NVM
NVM
CONTROLLER
Cache
S
M
M
32/16/8/4/2KB
RAM
HIGH SPEED
BUS MATRIX
S
PERIPHERAL
ACCESS CONTROLLER
S
S
AHB-APB
BRIDGE A
AHB-APB
BRIDGE C
S
AHB-APB
BRIDGE B
SRAM
CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
SYSTEM CONTROLLER
PORT
VREF
BOD33
66xxSERCOM
SERCOM
PIN[3:0]
8 x TIMER COUNTER
8 x(See
Timer
Counter
Note1)
WO[1:0]
OSCULP32K
OSC32K
XOSC32K
OSC8M
XIN
XOUT
XOSC
DFLL48M
POWER MANAGER
CLOCK
CONTROLLER
RESET
RESET
CONTROLLER
GCLK_IO[7:0]
SLEEP
CONTROLLER
WATCHDOG
TIMER
EXTERNAL INTERRUPT
CONTROLLER
VREFA
VREFB
AIN[3:0]
2 ANALOG
COMPARATORS
GENERIC CLOCK
CONTROLLER
REAL TIME
COUNTER
EXTINT[15:0]
NMI
AIN[19:0]
ADC
PORT
XIN32
XOUT32
EVENT SYSTEM
4.
CMP1:0]
VOUT
DAC
PERIPHERAL
TOUCH
CONTROLLER
VREFA
X[15:0]
Y[15:0]
Note: 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC
signals and ADC signals. Refer to Peripherals Configuration Summary for details.
Related Links
Peripherals Configuration Summary on page 59
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
19
Pinout
5.1.
SAM D20J
5.1.1.
QFN64 / TQFP64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB03
PB02
PB01
PB00
PB31
PB30
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
5.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA00
PA01
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
20
5.1.2.
UFBGA64
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
21
SAM D20G
5.2.1.
QFN48 / TQFP48
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
5.2.
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
22
5.2.2.
WLCSP45
A
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
23
SAM D20E
5.3.1.
QFN32 / TQFP32
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
5.3.
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
VDDANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
9
10
11
12
13
14
15
16
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
24
6.
Signal Descriptions List
The following table gives details on signal names classified by peripheral.
Signal Name Function
Type
Active Level
Analog Comparators - AC
AIN[3:0]
AC Analog Inputs
Analog
CMP[1:0]
AC Comparator Outputs
Digital
Analog Digital Converter - ADC
AIN[19:0]
ADC Analog Inputs
Analog
VREFA
ADC Voltage External Reference A
Analog
VREFB
ADC Voltage External Reference B
Analog
Digital Analog Converter - DAC
VOUT
DAC Voltage output
Analog
VREFA
DAC Voltage External Reference
Analog
External Interrupt Controller
EXTINT[15:0] External Interrupts
Input
NMI
Input
External Non-Maskable Interrupt
Generic Clock Generator - GCLK
GCLK_IO[7:0] Generic Clock (source clock or generic clock generator
output)
I/O
Power Manager - PM
RESET
Reset
Input
Low
Serial Communication Interface - SERCOMx
PAD[3:0]
SERCOM I/O Pads
I/O
System Control - SYSCTRL
XIN
Crystal Input
Analog/ Digital
XIN32
32kHz Crystal Input
Analog/ Digital
XOUT
Crystal Output
Analog
XOUT32
32kHz Crystal Output
Analog
Timer Counter - TCx
WO[1:0]
Waveform Outputs
Output
Peripheral Touch Controller - PTC
X[15:0]
PTC Input
Analog
Y[15:0]
PTC Input
Analog
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
25
Signal Name Function
Type
Active Level
General Purpose I/O - PORT
PA25 - PA00
Parallel I/O Controller I/O Port A
I/O
PA28 - PA27
Parallel I/O Controller I/O Port A
I/O
PA31 - PA30
Parallel I/O Controller I/O Port A
I/O
PB17 - PB00
Parallel I/O Controller I/O Port B
I/O
PB23 - PB22
Parallel I/O Controller I/O Port B
I/O
PB31 - PB30
Parallel I/O Controller I/O Port B
I/O
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
26
7.
I/O Multiplexing and Considerations
Related Links
I2C Pins on page 614
7.1.
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a
pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A
to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing
register (PMUXn.PMUXE/O) in the PORT.
This table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 7-1. PORT Function Multiplexing
Pin(1)
I/O Pin
Supply
Type
A
B(2)
EIC
REF
ADC
AC
PTC
DAC
C
D
E
G
H
SERCOM(3
)
SERCOMALT
TC(4)
COM
AC/GCLK
SAMD20E
SAMD20G
SAMD20J
1
1
1
PA00
VDDANA
EXTINT[0]
SERCOM1/
PAD[0]
TC2/
WO[0]
2
2
2
PA01
VDDANA
EXTINT[1]
SERCOM1/
PAD[1]
TC2/
WO[1]
3
3
3
PA02
VDDANA
EXTINT[2]
4
4
4
PA03
VDDANA
EXTINT[3]
5
PB04
VDDANA
6
PB05
VDDANA
9
PB06
10
PB07
7
11
8
5
AIN[0]
Y[0]
AIN[1]
Y[1]
EXTINT[4]
AIN[12]
Y[10]
EXTINT[5]
AIN[13]
Y[11]
VDDANA
EXTINT[6]
AIN[14]
Y[12]
VDDANA
EXTINT[7]
AIN[15]
Y[13]
PB08
VDDANA
EXTINT[8]
AIN[2]
Y[14]
SERCOM4/
PAD[0]
TC4/
WO[0]
12
PB09
VDDANA
EXTINT[9]
AIN[3]
Y[15]
SERCOM4/
PAD[1]
TC4/
WO[1]
9
13
PA04
VDDANA
EXTINT[4]
6
10
14
PA05
VDDANA
7
11
15
PA06
8
12
16
11
13
12
ADC/
VREFA
DAC/
VREFA
ADC/
VREFB
VOUT
AIN[4]
AIN[0]
Y[2]
SERCOM0/
PAD[0]
TC0/
WO[0]
EXTINT[5]
AIN[5]
AIN[1]
Y[3]
SERCOM0/
PAD[1]
TC0/
WO[1]
VDDANA
EXTINT[6]
AIN[6]
AIN[2]
Y[4]
SERCOM0/
PAD[2]
TC1/
WO[0]
PA07
VDDANA
EXTINT[7]
AIN[7]
AIN[3]
Y[5]
SERCOM0/
PAD[3]
TC1/
WO[1]
17
PA08
VDDIO
I2C
NMI
AIN[16]
X[0]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TC0/
WO[0]
14
18
PA09
VDDIO
I2C
EXTINT[9]
AIN[17]
X[1]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TC0/
WO[1]
13
15
19
PA10
VDDIO
EXTINT[10]
AIN[18]
X[2]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TC1/
WO[0]
GCLK_IO[4]
14
16
20
PA11
VDDIO
EXTINT[11]
AIN[19]
X[3]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TC1/
WO[1]
GCLK_IO[5]
19
23
PB10
VDDIO
EXTINT[10]
SERCOM4/
PAD[2]
TC5/
WO[0]
GCLK_IO[4]
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
27
Pin(1)
Supply
Type
A
B(2)
EIC
REF
C
D
E
G
H
SERCOM(3
)
SERCOMALT
TC(4)
COM
AC/GCLK
SERCOM4/
PAD[3]
TC5/
WO[1]
GCLK_IO[5]
SERCOM4/
PAD[0]
TC4/
WO[0]
GCLK_IO[6]
X[13]
SERCOM4/
PAD[1]
TC4/
WO[1]
GCLK_IO[7]
EXTINT[14]
X[14]
SERCOM4/
PAD[2]
TC5/
WO[0]
GCLK_IO[0]
EXTINT[15]
X[15]
SERCOM4/
PAD[3]
TC5/
WO[1]
GCLK_IO[1]
SERCOM4/
PAD[0]
TC2/
WO[0]
AC/CMP[0]
SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TC2/
WO[1]
AC/CMP[1]
EXTINT[14]
SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TC3/
WO[0]
GCLK_IO[0]
EXTINT[15]
SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TC3/
WO[1]
GCLK_IO[1]
X[4]
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TCC2/
WO[0]
GCLK_IO[2]
EXTINT[1]
X[5]
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TC2/
WO[1]
GCLK_IO[3]
VDDIO
EXTINT[2]
X[6]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC3/
WO[0]
AC/CMP[0]
PA19
VDDIO
EXTINT[3]
X[7]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC3/
WO[1]
AC/CMP[1]
39
PB16
VDDIO
I2C
EXTINT[0]
SERCOM5/
PAD[0]
TC6/
WO[0]
GCLK_IO[2]
40
PB17
VDDIO
I2C
EXTINT[1]
SERCOM5/
PAD[1]
TC6/
WO[1]
GCLK_IO[3]
29
41
PA20
VDDIO
EXTINT[4]
X[8]
SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TC7/
WO[0]
GCLK_IO[4]
30
42
PA21
VDDIO
EXTINT[5]
X[9]
SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TC7/
WO[1]
GCLK_IO[5]
21
31
43
PA22
VDDIO
I2C
EXTINT[6]
X[10]
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TC4/
WO[0]
GCLK_IO[6]
22
32
44
PA23
VDDIO
I2C
EXTINT[7]
X[11]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TC4/
WO[1]
GCLK_IO[7]
23
33
45
PA24(6)
VDDIO
EXTINT[12]
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TC5/
WO[0]
24
34
46
PA25(6)
VDDIO
EXTINT[13]
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TC5/
WO[1]
37
49
PB22
VDDIO
EXTINT[6]
SERCOM5/
PAD[2]
TC7/
WO[0]
GCLK_IO[0]
38
50
PB23
VDDIO
EXTINT[7]
SERCOM5/
PAD[3]
TC7/
WO[1]
GCLK_IO[1]
25
39
51
PA27
VDDIO
EXTINT[15]
27
41
53
PA28
VDDIO
EXTINT[8]
31
45
57
PA30
VDDIO
EXTINT[10]
SERCOM1/
PAD[2]
TC1/
WO[0]
SWCLK
32
46
58
PA31
VDDIO
EXTINT[11]
SERCOM1/
PAD[3]
TC1/
WO[1]
SWDIO
(5)
59
PB30
VDDIO
I2C
EXTINT[14]
SERCOM5/
PAD[0]
TC0/
WO[0]
60
PB31
VDDIO
I2C
EXTINT[15]
SERCOM5/
PAD[1]
TC0/
WO[1]
SAMD20E
I/O Pin
SAMD20G
SAMD20J
ADC
AC
PTC
DAC
20
24
PB11
VDDIO
25
PB12
VDDIO
I2C
EXTINT[12]
X[12]
26
PB13
VDDIO
I2C
EXTINT[13]
27
PB14
VDDIO
28
PB15
VDDIO
21
29
PA12
VDDIO
I2C
EXTINT[12]
SERCOM2/
PAD[0]
22
30
PA13
VDDIO
I2C
EXTINT[13]
15
23
31
PA14
VDDIO
16
24
32
PA15
VDDIO
17
25
35
PA16
VDDIO
I2C
EXTINT[0]
18
26
36
PA17
VDDIO
I2C
19
27
37
PA18
20
28
38
EXTINT[11]
GCLK_IO[0]
GCLK_IO[0]
GCLK_IO[0]
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
28
Pin(1)
SAMD20E
I/O Pin
SAMD20G
Supply
SAMD20J
Type
A
B(2)
EIC
REF
ADC
AC
PTC
DAC
C
D
E
G
H
SERCOM(3
)
SERCOMALT
TC(4)
COM
AC/GCLK
61
PB00
VDDANA
EXTINT[0]
AIN[8]
Y[6]
SERCOM5/
PAD[2]
TC7/
WO[0]
62
PB01
VDDANA
EXTINT[1]
AIN[9]
Y[7]
SERCOM5/
PAD[3]
TC7/
WO[1]
47
63
PB02
VDDANA
EXTINT[2]
AIN[10]
Y[8]
SERCOM5/
PAD[0]
TC6/
WO[0]
48
64
PB03
VDDANA
EXTINT[3]
AIN[11]
Y[9]
SERCOM5/
PAD[1]
TC6/
WO[1]
Note:
1. Use the SAMD20J pinout muxing for WLCSP45 package.
2. All analog pin functions are on peripheral function B. Peripheral function B must be selected to
disable the digital control of the pin.
3. Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin
in I2C mode. Refer to Electrical Characteristics for details on the I2C pin characteristics.
4. Note that TC6 and TC7 are not supported on the SAM D20E and SAM D20G devices. Refer to
Configuration Summary for details.
5. This function is only activated in the presence of a debugger.
6. If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and
PA25 through input GPIO mode. The aim is to avoid an eventually extract power consumption
( 2.0V)
0x3
VREFA
External reference
0x4
VREFB
External reference
0x5-0xF
Reserved
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
535
29.8.3.
Average Control
Name: AVGCTRL
Offset: 0x02
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
3
2
ADJRES[2:0]
Access
Reset
1
0
SAMPLENUM[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bits 6:4 – ADJRES[2:0]: Adjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
Bits 3:0 – SAMPLENUM[3:0]: Number of Samples to be Collected
These bits define how many samples should be added together.The result will be available in the Result
register (RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed.
SAMPLENUM[3:0]
Name
Description
0x0
1
1 sample
0x1
2
2 samples
0x2
4
4 samples
0x3
8
8 samples
0x4
16
16 samples
0x5
32
32 samples
0x6
64
64 samples
0x7
128
128 samples
0x8
256
256 samples
0x9
512
512 samples
0xA
1024
1024 samples
0xB-0xF
Reserved
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
536
29.8.4.
Sampling Time Control
Name: SAMPCTRL
Offset: 0x03
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
3
2
1
0
SAMPLEN[5:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 5:0 – SAMPLEN[5:0]: Sampling Time Length
These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler
value, thus controlling the ADC input impedance. Sampling time is set according to the equation:
Sampling time = SAMPLEN+1 ⋅
CLKADC
2
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
537
29.8.5.
Control B
Name: CTRLB
Offset: 0x04
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PRESCALER[2:0]
Access
Reset
Bit
7
6
5
4
RESSEL[1:0]
Access
Reset
R/W
R/W
R/W
0
0
0
3
2
1
0
CORREN
FREERUN
LEFTADJ
DIFFMODE
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 10:8 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock.
PRESCALER[2:0]
Name
Description
0x0
DIV4
Peripheral clock divided by 4
0x1
DIV8
Peripheral clock divided by 8
0x2
DIV16
Peripheral clock divided by 16
0x3
DIV32
Peripheral clock divided by 32
0x4
DIV64
Peripheral clock divided by 64
0x5
DIV128
Peripheral clock divided by 128
0x6
DIV256
Peripheral clock divided by 256
0x7
DIV512
Peripheral clock divided by 512
Bits 5:4 – RESSEL[1:0]: Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution.
RESSEL[1:0]
Name
Description
0x0
12BIT
12-bit result
0x1
16BIT
For averaging mode output
0x2
10BIT
10-bit result
0x3
8BIT
8-bit result
Bit 3 – CORREN: Digital Correction Logic Enabled
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
538
Value
Description
0
Disable the digital result correction.
1
Enable the digital result correction. The ADC conversion result in the RESULT register is
then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL
registers. Conversion time will be increased by X cycles according to the value in the Offset
Correction Value bit group in the Offset Correction register.
Bit 2 – FREERUN: Free Running Mode
Value
Description
0
The ADC run is single conversion mode.
1
The ADC is in free running mode and a new conversion will be initiated when a previous
conversion completes.
Bit 1 – LEFTADJ: Left-Adjusted Result
Value
Description
0
The ADC conversion result is right-adjusted in the RESULT register.
1
The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12bit result will be present in the upper part of the result register. Writing this bit to zero
(default) will right-adjust the value in the RESULT register.
Bit 0 – DIFFMODE: Differential Mode
Value
Description
0
The ADC is running in singled-ended mode.
1
The ADC is running in differential mode. In this mode, the voltage difference between the
MUXPOS and MUXNEG inputs will be converted by the ADC.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
539
29.8.6.
Window Monitor Control
Name: WINCTRL
Offset: 0x08
Reset: 0x00
Property: Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
WINMODE[2:0]
Access
R/W
R/W
R/W
0
0
0
Reset
Bits 2:0 – WINMODE[2:0]: Window Monitor Mode
These bits enable and define the window monitor mode.
WINMODE[2:0]
Name
Description
0x0
DISABLE
No window mode (default)
0x1
MODE1
Mode 1: RESULT > WINLT
0x2
MODE2
Mode 2: RESULT < WINUT
0x3
MODE3
Mode 3: WINLT < RESULT < WINUT
0x4
MODE4
Mode 4: !(WINLT < RESULT < WINUT)
0x5-0x7
Reserved
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
540
29.8.7.
Software Trigger
Name: SWTRIG
Offset: 0x0C
Reset: 0x00
Property: Write-Protected, Write-Synchronized
Bit
7
6
5
4
Access
Reset
3
2
1
0
START
FLUSH
R/W
R/W
0
0
Bit 1 – START: ADC Start Conversion
Writing this bit to zero will have no effect.
Value
Description
0
The ADC will not start a conversion.
1
The ADC will start a conversion. The bit is cleared by hardware when the conversion has
started. Setting this bit when it is already set has no effect.
Bit 0 – FLUSH: ADC Conversion Flush
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a
new conversion.
Writing this bit to zero will have no effect.
Value
Description
0
No flush action.
1
"Writing a '1' to this bit will flush the ADC pipeline. A flush will restart the ADC clock on the
next peripheral clock edge, and all conversions in progress will be aborted and lost. This bit
will be cleared after the ADC has been flushed.
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the
ADC will start a new conversion.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
541
29.8.8.
Input Control
Name: INPUTCTRL
Offset: 0x10
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
R/W
R/W
R/W
R/W
0
0
0
0
19
18
17
16
GAIN[3:0]
Access
Reset
Bit
23
22
21
20
INPUTOFFSET[3:0]
Access
INPUTSCAN[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
MUXNEG[4:0]
Access
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
4
3
2
1
0
Reset
Bit
7
6
5
MUXPOS[4:0]
Access
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Reset
Bits 27:24 – GAIN[3:0]: Gain Factor Selection
These bits set the gain factor of the ADC gain stage.
GAIN[3:0]
Name
Description
0x0
1X
1x
0x1
2X
2x
0x2
4X
4x
0x3
8X
8x
0x4
16X
16x
0x5-0xE
-
Reserved
0xF
DIV2
1/2x
Bits 23:20 – INPUTOFFSET[3:0]: Positive Mux Setting Offset
The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the
first conversion triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET.
Setting this register to zero causes the first conversion to use a positive input equal to MUXPOS.
After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion
to be done with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and
INPUTOFFSET gives the input that is actually converted.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
542
Bits 19:16 – INPUTSCAN[3:0]: Number of Input Channels Included in Scan
This register gives the number of input sources included in the pin scan. The number of input sources
included is INPUTSCAN + 1. The input channels included are in the range from MUXPOS +
INPUTOFFSET to MUXPOS + INPUTOFFSET + INPUTSCAN.
The range of the scan mode must not exceed the number of input channels available on the device.
Bits 12:8 – MUXNEG[4:0]: Negative Mux Input Selection
These bits define the Mux selection for the negative ADC input selections.
Value
Name
Description
0x00
PIN0
ADC AIN0 pin
0x01
PIN1
ADC AIN1 pin
0x02
PIN2
ADC AIN2 pin
0x03
PIN3
ADC AIN3 pin
0x04
PIN4
ADC AIN4 pin
0x05
PIN5
ADC AIN5 pin
0x06
PIN6
ADC AIN6 pin
0x07
PIN7
ADC AIN7 pin
0x08-0x1 7
Reserved
0x18
GND
Internal ground
0x19
IOGND
I/O ground
0x1A-0x1 F
Reserved
Bits 4:0 – MUXPOS[4:0]: Positive Mux Input Selection
These bits define the Mux selection for the positive ADC input. The following table shows the possible
input selections. If the internal bandgap voltage or temperature sensor input channel is selected, then the
Sampling Time Length bit group in the SamplingControl register must be written.
MUXPOS[4:0]
Group configuration
Description
0x00
PIN0
ADC AIN0 pin
0x01
PIN1
ADC AIN1 pin
0x02
PIN2
ADC AIN2 pin
0x03
PIN3
ADC AIN3 pin
0x04
PIN4
ADC AIN4 pin
0x05
PIN5
ADC AIN5 pin
0x06
PIN6
ADC AIN6 pin
0x07
PIN7
ADC AIN7 pin
0x08
PIN8
ADC AIN8 pin
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
543
MUXPOS[4:0]
Group configuration
Description
0x09
PIN9
ADC AIN9 pin
0x0A
PIN10
ADC AIN10 pin
0x0B
PIN11
ADC AIN11 pin
0x0C
PIN12
ADC AIN12 pin
0x0D
PIN13
ADC AIN13 pin
0x0E
PIN14
ADC AIN14 pin
0x0F
PIN15
ADC AIN15 pin
0x10
PIN16
ADC AIN16 pin
0x11
PIN17
ADC AIN17 pin
0x12
PIN18
ADC AIN18 pin
0x13
PIN19
ADC AIN19 pin
0x14-0x17
Reserved
0x18
TEMP
Temperature reference
0x19
BANDGAP
Bandgap voltage
0x1A
SCALEDCOREVCC
1/4 scaled core supply
0x1B
SCALEDIOVCC
1/4 scaled I/O supply
0x1C
DAC
DAC output
0x1D-0x1F
Reserved
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
544
29.8.9.
Event Control
Name: EVCTRL
Offset: 0x14
Reset: 0x00
Property: Write-Protected
Bit
7
6
Access
Reset
5
4
1
0
WINMONEO
RESRDYEO
3
2
SYNCEI
STARTEI
R/W
R/W
R/W
R/W
0
0
0
0
Bit 5 – WINMONEO: Window Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be
generated when the window monitor detects something.
Value
Description
0
Window Monitor event output is disabled and an event will not be generated.
1
Window Monitor event output is enabled and an event will be generated.
Bit 4 – RESRDYEO: Result Ready Event Out
This bit indicates whether the Result Ready event output is enabled or not and an output event will be
generated when the conversion result is available.
Value
Description
0
Result Ready event output is disabled and an event will not be generated.
1
Result Ready event output is enabled and an event will be generated.
Bit 1 – SYNCEI: Synchronization Event In
Value
Description
0
A flush and new conversion will not be triggered on any incoming event.
1
A flush and new conversion will be triggered on any incoming event.
Bit 0 – STARTEI: Start Conversion Event In
Value
Description
0
A new conversion will not be triggered on any incoming event.
1
A new conversion will be triggered on any incoming event.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
545
29.8.10. Interrupt Enable Clear
Name: INTENCLR
Offset: 0x16
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
Access
Reset
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
R/W
R/W
R/W
R/W
0
0
0
0
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding
interrupt request.
Value
Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled, and an interrupt request will be generated
when the Synchronization Ready interrupt flag is set.
Bit 2 – WINMON: Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt
request.
Value
Description
0
The window monitor interrupt is disabled.
1
The window monitor interrupt is enabled, and an interrupt request will be generated when the
Window Monitor interrupt flag is set.
Bit 1 – OVERRUN: Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled, and an interrupt request will be generated when the
Overrun interrupt flag is set.
Bit 0 – RESRDY: Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt
request.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
546
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled, and an interrupt request will be generated when the
Result Ready interrupt flag is set.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
547
29.8.11. Interrupt Enable Set
Name: INTENSET
Offset: 0x17
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
Access
Reset
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
R/W
R/W
R/W
R/W
0
0
0
0
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the
Synchronization Ready interrupt.
Value
Description
0
The Synchronization Ready interrupt is disabled.
1
The Synchronization Ready interrupt is enabled.
Bit 2 – WINMON: Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt.
Value
Description
0
The Window Monitor interrupt is disabled.
1
The Window Monitor interrupt is enabled.
Bit 1 – OVERRUN: Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled.
Bit 0 – RESRDY: Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
548
29.8.12. Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00
Property:
Bit
7
6
5
4
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
R/W
R/W
R/W
R/W
0
0
0
0
Access
Reset
Bit 3 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY), except when caused by an enable or software reset, and will generate an
interrupt request if INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Bit 2 – WINMON: Window Monitor
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an
interrupt request will be generated if INTENCLR/SET.WINMON is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Window Monitor interrupt flag.
Bit 1 – OVERRUN: Overrun
This flag is cleared by writing a one to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt
request will be generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
Bit 0 – RESRDY: Result Ready
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/
SET.RESRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Result Ready interrupt flag.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
549
29.8.13. Status
Name: STATUS
Offset: 0x19
Reset: 0x00
Property:
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
R
Reset
0
Bit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
550
29.8.14. Result
Name: RESULT
Offset: 0x1A
Reset: 0x0000
Property: Read-Synchronized
Bit
15
14
13
12
11
10
9
8
RESULT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RESULT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 15:0 – RESULT[15:0]: Result Conversion Value
These bits will hold up to a 16-bit ADC result, depending on the configuration.
In single-ended without averaging mode, the ADC conversion will produce a 12-bit result, which can be
left- or right-shifted, depending on the setting of CTRLB.LEFTADJ.
If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8],
while the remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit
result is required; i.e., one can read only the high byte of the entire 16-bit register.
If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be
available in bit locations [11:0], and the result is then 12 bits long.
If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the
Average Control register (AVGCTRL).
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
551
29.8.15. Window Monitor Lower Threshold
Name: WINLT
Offset: 0x1C
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
WINLT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WINLT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – WINLT[15:0]: Window Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
552
29.8.16. Window Monitor Upper Threshold
Name: WINUT
Offset: 0x20
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
WINUT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WINUT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – WINUT[15:0]: Window Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
553
29.8.17. Gain Correction
Name: GAINCORR
Offset: 0x24
Reset: 0x0000
Property: Write-Protected
Bit
15
14
13
12
11
10
9
8
GAINCORR[11:8]
Access
Reset
Bit
7
6
5
4
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
GAINCORR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 11:0 – GAINCORR[11:0]: Gain Correction Value
If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for
gain error before being written to the result register. The gain-correction is a fractional value, a 1-bit
integer plusan 11-bit fraction, and therefore 1/2 1.6V, IOL max
-
0.1*VDD
0.2*VDD
VOH
Output high-level voltage
VDD > 1.6V, IOH max
0.8*VDD
0.9*VDD
-
IOL
Output low-level current
VDD = 1.62V-3V,
PORT.PINCFG.DRVSTR=0
-
-
1
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
2.5
VDD = 1.62V-3V,
PORT.PINCFG.DRVSTR=1
-
-
3
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
10
VDD = 1.62V-3V,
PORT.PINCFG.DRVSTR=0
-
-
0.7
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
2
VDD = 1.62V-3V,
PORT.PINCFG.DRVSTR=1
-
-
2
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
7
IOH
Output high-level current
mA
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
613
Symbol Parameter
tRISE
tFALL
ILEAK
Rise time(1)
Fall time(1)
Input leakage current
Conditions
Min.
Typ.
Max.
Units
PORT.PINCFG.DRVSTR=0
load = 5pF, VDD = 3.3V
-
-
15
ns
PORT.PINCFG.DRVSTR=1
load = 20pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=0
load = 5pF, VDD = 3.3V
-
-
15
PORT.PINCFG.DRVSTR=1
load = 20pF, VDD = 3.3V
-
-
15
Pull-up resistors disabled
-1
+/-0.015 1
μA
Note: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
Table 33-12. SAMD20 revC/revB Normal I/O Pins Characteristics
Symbol
Parameter
RPULL
Pull-up - Pull-down resistance
VIL
Input low-level voltage
VIH
Input high-level voltage
Conditions
Min.
Typ.
Max.
Units
20
40
60
kΩ
VDD = 1.62V-2.7V
-
-
0.25*VDD
V
VDD = 2.7V-3.63V
-
-
0.3*VDD
VDD = 1.62V-2.7V
0.7*VDD
-
-
VDD = 2.7V-3.63V
0.55*VDD
-
-
VOL
Output low-level voltage
VDD > 1.6V, IOL max
-
0.1*VDD
0.2*VDD
VOH
Output high-level voltage
VDD > 1.6V, IOH max
0.8*VDD
0.9*VDD
-
IOL
Output low-level current
VDD = 1.6V-3V
-
-
8
VDD = 3V-3.63V
-
-
20
VDD = 1.6V-3V
-
-
4.5
VDD = 3V-3.63V
-
-
10
load = 30pF,VDD = 3.3V,
slope range [10%-90%]
-
7
-
-
9.5
-
Pull-up resistors
disabled
-1
+/-0.015
1
IOH
Output high-level current
tRISE
Rise time(1)
tFALL
Fall time(1)
ILEAK
Input leakage current
mA
ns
μA
Note: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
33.8.2.
I2C Pins
Refer to I/O Multiplexing and Considerations to get the list of I2C pins.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
614
Table 33-13. I2C Pins Characteristics in I2C configuration
Symbol
Parameter
RPULL
Pull-up - Pull-down resistance
VIL
Input low-level voltage
VIH
Condition
Input high-level voltage
VHYS
Hysteresis of Schmitt trigger inputs
VOL
Output low-level voltage
IOL
fSCL
Output low-level current
Min.
Typ.
Max.
Units
20
40
60
kΩ
VDD = 1.62V-2.7V
-
-
0.25*VDD
V
VDD = 2.7V-3.63V
-
-
0.3*VDD
VDD = 1.62V-2.7V
0.7*VDD
-
-
VDD = 2.7V-3.63V
0.55*VDD
-
-
0.08*VDD
-
-
VDD > 2.0V
IOL = 3mA
-
-
0.4
VDD ≤ 2.0V
IOL = 2mA
-
-
0.2*VDD
VOL = 0.4V
3
-
-
VOL = 0.6V
6
-
-
-
-
400
SCL clock frequency
mA
kHz
I2C pins timing characteristics can be found in SERCOM in I2C Mode Timing
Related Links
I/O Multiplexing and Considerations on page 27
33.8.3.
XOSC Pin
XOSC pins behave as normal pins when used as normal I/Os. Refer to Table 33-11
33.8.4.
XOSC32 Pin
XOSC32 pins behave as normal pins when used as normal I/Os. Refer to Table 33-11.
33.8.5.
External Reset Pin
Reset pin has the same electrical characteristics as normal I/O pins. Refer to Table 33-11.
33.9.
Injection Current
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 33-14. Injection Current(1)
Symbol
Description
min
max
Unit
Iinj1 (2)
IO pin injection current
-1
+1
mA
Iinj2 (3)
IO pin injection current
-15
+15
mA
Iinjtotal
Sum of IO pins injection current
-45
+45
mA
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
615
Note:
1. Injecting current may have an effect on the accuracy of Analog blocks
2. Conditions for Vpin: Vpin < GND-0.3V or 3.6V VREF/4 -0.05*VDDANA -0.1V
b. If |VIN| < VREF/4
•
•
VCM_IN < 1.2*VDDANA - 0.75V
VCM_IN > 0.2*VDDANA - 0.1V
Note: The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power
supply. The ADC performance of these pins will not be the same as all the other ADC channels on
pins powered from the VDDANA power supply.
Note: The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) =
(Gain Error in V x 100) / (2*VREF/GAIN)
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
620
Table 33-22. Single-Ended Mode
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.5
9.8
Bits
TUE
Total Unadjusted Error
1x gain
-
10.5
14.0
LSB
INL
Integral Non-Linearity
1x gain
1.0
1.6
3.5
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.5
+/-0.6
+/-0.95
LSB
Gain Error
Ext. Ref. 1x
-5.0
0.7
+5.0
mV
Gain Accuracy(4)
Ext. Ref. 0.5x
+/-0.2
+/-0.34
+/-0.4
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.2
%
Offset Error
Ext. Ref. 1x
-5.0
1.5
+5.0
mV
SFDR
Spurious Free Dynamic Range
63.1
65.0
67.0
dB
SINAD
Signal-to-Noise and Distortion
47.5
59.5
61.0
dB
SNR
Signal-to-Noise Ratio
1x Gain
FCLK_ADC = 2.1MHz
FIN = 40kHz
AIN = 95%FSR
48.0
60.0
64.0
dB
THD
Total Harmonic Distortion
-65.4
-63.0
-62.1
dB
-
1.0
-
mV
Noise RMS
T = 25°C
Note: Maximum numbers are based on characterization and not tested in production, and for 5%
to 95% of the input voltage range.
•
•
Note: Respect the input common mode voltage through the following equations (where VCM_IN is
the Input channel common mode voltage) for all VIN:
VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
Note: The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power
supply. The ADC performance of these pins will not be the same as all the other ADC channels on
pins powered from the VDDANA power supply.
Note: The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) =
(Gain Error in V x 100) / (VREF/GAIN)
33.10.4.1. Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average
value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the
Number-of-Samples-to-be-collected bit group in the Average Control register
(AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT).
Table 33-23. Averaging feature
Average Number
Conditions
SNR (dB)
SINAD (dB)
SFDR (dB)
ENOB (bits)
1
In differential mode, 1x gain,
VDDANA=3.0V, VREF=1.0V, 350ksps
T= 25°C
66.0
65.0
72.8
9.75
67.6
65.8
75.1
10.62
32
69.7
67.1
75.3
10.85
128
70.4
67.5
75.5
10.91
8
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
621
33.10.4.2. Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is
handled by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain
Correction register (GAINCORR). The offset and gain correction value is subtracted from the converted
data before writing the Result register (RESULT).
Table 33-24. Offset and Gain correction feature
Gain Factor Conditions
0.5x
1x
2x
Offset Error (mV) Gain Error (mV) Total Unadjusted Error
(LSB)
In differential mode, 1x gain,
0.25
VDDANA=3.0V, VREF=1.0V, 350ksps
0.20
T= 25°C
0.15
1.0
2.4
0.10
1.5
-0.15
2.7
8x
-0.05
0.05
3.2
16x
0.10
-0.05
6.1
33.10.4.3. Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in
order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (�SAMPLE) and a
capacitor (�SAMPLE). In addition, the source resistance (�SOURCE) must be taken into account when
calculating the required sample and hold time. The figure below shows the ADC input channel equivalent
circuit.
Figure 33-5. ADC Input
VDDANA/2
RSOURCE
Analog Input
AINx
CSAMPLE
RSAMPLE
VIN
To achieve n bits of accuracy, the �SAMPLE capacitor must be charged at least to a voltage of
�CSAMPLE ≥ �
IN
× 1 − 2−
�+1
The minimum sampling time �SAMPLEHOLD for a given �SOURCEcan be found using this formula:
�SAMPLEHOLD ≥ �SAMPLE + �
SOURCE
× �SAMPLE × � + 1 × ln 2
for a 12 bits accuracy: �SAMPLEHOLD ≥ �SAMPLE + �
where
�SAMPLEHOLD =
SOURCE
× �SAMPLE × 9.02
1
2 × �ADC
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
622
33.10.5. Digital to Analog Converter (DAC) Characteristics
Table 33-25. Operating Conditions(1)
Symbol
Parameter
VDDANA
AVREF
IDD
Conditions
Min.
Typ.
Max.
Units
Analog supply voltage
1.62
-
3.63
V
External reference voltage
1.0
-
VDDANA-0.6
V
Internal reference voltage 1
-
1
-
V
Internal reference voltage 2
-
VDDANA
-
V
Linear output voltage range
0.05
-
VDDANA-0.05
V
Minimum resistive load
5
-
-
kΩ
Maximum capacitance load
-
-
100
pF
-
160
230
μA
DC supply current(2)
Voltage pump disabled
Notes: 1. These values are based on specifications otherwise noted.
2. These values are based on characterization. These values are not covered by test limits in production.
Table 33-26. Clock and Timing(1)
Symbol
Parameter
Conditions
Conversion rate
Cload = 100pF
Rload > 5kΩ
Startup time
Min.
Typ.
Max.
Units
Normal mode
-
-
350
ksps
For ΔDATA = +/-1
-
-
1000
VDDNA > 2.6V
-
-
2.85
μs
VDDNA < 2.6V
-
-
10
μs
Note: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
Table 33-27. Accuracy Characteristics(1)
Symbol
Parameter
RES
Input resolution
INL
Integral non-linearity
Conditions
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Min.
Typ.
Max.
Units
-
-
10
Bits
VDD = 1.6V
0.75
1.1
2.5
LSB
VDD = 3.6V
0.6
1.2
1.5
VDD = 1.6V
1.4
2.2
2.5
VDD = 3.6V
0.9
1.4
1.5
VDD = 1.6V
0.75
1.3
1.5
VDD = 3.6V
0.8
1.2
1.5
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
623
Symbol
Parameter
Conditions
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
Min.
Typ.
Max.
Units
VDD = 1.6V
+/-0.9
+/-1.2
+/-1.5
LSB
VDD = 3.6V
+/-0.9
+/-1.1
+/-1.2
VDD = 1.6V
+/-1.1
+/-1.5
+/-1.7
VDD = 3.6V
+/-1.0
+/-1.1
+/-1.2
VDD = 1.6V
+/-1.1
+/-1.4
+/-1.5
VDD = 3.6V
+/-1.0
+/-1.5
+/-1.6
Gain error
Ext. VREF
+/-1.5
+/-5
+/-10
mV
Offset error
Ext. VREF
+/-2
+/-3
+/-6
mV
Note: 1. All values measured using a conversion rate of 350ksps.
33.10.6. Analog Comparator Characteristics
Table 33-28. Electrical and Timing
Symbol
Parameter
Min.
Typ.
Max.
Positive input voltage range
0
-
VDDANA V
Negative input voltage range
0
-
VDDANA
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low power mode
-25
0.0
+25
mV
Hysteresis = 1, Fast mode
20
50
80
mV
Hysteresis = 1, Low power mode
15
40
75
mV
Changes for VACM = VDDANA/2
100mV overdrive, Fast mode
-
60
116
ns
Changes for VACM = VDDANA/2
100mV overdrive, Low power mode
-
225
370
ns
Enable to ready delay
Fast mode
-
1
2
μs
Enable to ready delay
Low power mode
-
12
19
μs
INL(3)
-1.4
0.75
+1.4
LSB
DNL(3)
-0.9
0.25
+0.9
LSB
Offset Error (1)(2)
-0.200 0.260 +0.920
LSB
Gain Error (1)(2)
-0.89
LSB
Offset
Hysteresis
Propagation delay
tSTARTUP Startup time
VSCALE
Conditions
0.215 0.89
Units
Notes: 1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
624
33.10.7. Bandgap Reference Characteristics
Table 33-29. Bandgap (Internal 1.1V reference) characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
INTBG
Bandgap reference
Over voltage and [-40°C, +85°C]
1.08
1.1
1.12
V
Over voltage at 25°C
1.09
1.1
1.11
33.10.8. Temperature Sensor Characteristics
33.10.8.1. Temperature Sensor Characteristics
Table 33-30. Temperature Sensor Characteristics(1)
Symbol Parameter
Temperature sensor
output voltage
Conditions
Min. Typ.
T= 25°C, VDDANA = 3.3V
-
0.667 -
V
2.3
2.4
2.5
mV/°C
Temperature sensor slope
Max. Units
Variation over VDDANA
voltage
VDDANA = 1.62V to 3.6V
-1.7 1
3.7
mV/V
Temperature Sensor
accuracy
Using the method described in the following
section
-10
10
°C
-
Note: 1. These values are based on characterization. These values are not covered by test limits in
production.
2. See also rev C errata concerning the temperature sensor.
33.10.8.2. Software-based Refinement of the Actual Temperature
The temperature sensor behavior is linear but it depends on several parameters such as the internal
voltage reference which itself depends on the temperature. To take this into account, each device
contains a Temperature Log row with data measured and written during the production tests. These
calibration values should be read by software to infer the most accurate temperature readings possible.
This Software Temperature Log row can be read at address 0x00806030. The Software Temperature Log
row cannot be written.
This section specifies the Temperature Log row content and explains how to refine the temperature
sensor output using the values in the Temperature Log row.
Temperature Log Row
All values in this row were measured in the following conditions:
•
•
•
•
•
VDDIN = VDDIO = VDDANA = 3.3V
ADC Clock speed = 1MHz
ADC mode: Free running mode, ADC averaging mode with 4 averaged samples
ADC voltage reference = 1.0V internal reference (INT1V)
ADC input = Temperature sensor
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
625
Table 33-31. Temperature Log Row Content
Bit position Name
Description
7:0
ROOM_TEMP_VAL_INT
Integer part of room temperature in °C
11:8
ROOM_TEMP_VAL_DEC Decimal part of room temperature
19:12
HOT_TEMP_VAL_INT
Integer part of hot temperature in °C
23:20
HOT_TEMP_VAL_DEC
Decimal part of hot temperature
31:24
ROOM_INT1V_VAL
2’s complement of the internal 1V reference drift at room
temperature (versus a 1.0 centered value)
39:32
HOT_INT1V_VAL
2’s complement of the internal 1V reference drift at hot
temperature (versus a 1.0 centered value)
51:40
ROOM_ADC_VAL
12-bit ADC conversion at room temperature
63:52
HOT_ADC_VAL
12-bit ADC conversion at hot temperature
The temperature sensor values are logged during test production flow for Room and Hot insertions:
•
•
ROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contains the measured temperature at
room insertion (e.g. for ROOM_TEMP_VAL_INT=25 and ROOM_TEMP_VAL_DEC=2, the
measured temperature at room insertion is 25.2°C).
HOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contains the measured temperature at hot
insertion (e.g. for HOT_TEMP_VAL_INT=83 and HOT_TEMP_VAL_DEC=3, the measured
temperature at room insertion is 83.3°C).
The temperature log row also contains the corresponding 12-bit ADC conversions of both Room and Hot
temperatures:
•
•
ROOM_ADC_VAL contains the 12-bit ADC value corresponding to (ROOM_TEMP_VAL_INT,
ROOM_TEMP_VAL_DEC)
HOT_ADC_VAL contains the 12-bit ADC value corresponding to (HOT_TEMP_VAL_INT,
HOT_TEMP_VAL_DEC)
The temperature log row also contains the corresponding 1V internal reference of both Room and Hot
temperatures:
•
•
•
ROOM_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC)
HOT_INT1V_VAL is the 2’s complement of the internal 1V reference value corresponding to
(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC)
ROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In
other words, the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1,
-127] corresponds to [1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges.
Using Linear Interpolation
For concise equations, we’ll use the following notations:
•
•
•
•
•
(ROOM_TEMP_VAL_INT, ROOM_TEMP_VAL_DEC) is denoted tempR
(HOT_TEMP_VAL_INT, HOT_TEMP_VAL_DEC) is denoted tempH
ROOM_ADC_VAL is denoted ADCR, its conversion to Volt is denoted VADCR
HOT_ADC_VAL is denoted ADCH, its conversion to Volt is denoted VADCH
ROOM_INT1V_VAL is denoted INT1VR
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
626
•
HOT_INT1V_VAL is denoted INT1VH
Using the (tempR, ADCR) and (tempH, ADCH) points, using a linear interpolation we have the following
equation:
�ADC − �ADCR
�ADCH − �ADCR
=
temp − temp�
temp� − temp�
Given a temperature sensor ADC conversion value ADCm, we can infer a coarse value of the temperature
tempC as:
[Equation 1]
temp� = temp� +
ADC� ⋅
1
212 − 1
ADC� ⋅
− ADC� ⋅
INT1��
2
12 − 1
INT1��
212 − 1
− ADC� ⋅
⋅ temp� − temp�
INT1��
2
12 − 1
Note 1: in the previous expression, we’ve added the conversion of the ADC register value to be
expressed in V
Note 2: this is a coarse value because we assume INT1V=1V for this ADC conversion.
Using the (tempR, INT1VR) and (tempH, INT1VH) points, using a linear interpolation we have the following
equation:
INT1� − INT1��
INT1�� − INT1��
=
temp − temp�
temp� − temp�
Then using the coarse temperature value, we can infer a closer to reality INT1V value during the ADC
conversion as:
INT1�� = INT1�� +
INT1�� − INT1�� ⋅ temp� − temp�
temp� − temp�
Back to [Equation 1], we replace INT1V=1V by INT1V = INT1Vm, we can then deduce a finer temperature
value as:
[Equation 1bis]
temp� = temp� +
ADC� ⋅
INT1��
212 − 1
ADC� ⋅
− ADC� ⋅
INT1��
212 − 1
INT1��
212 − 1
− ADC� ⋅
⋅ temp� − temp�
INT1��
212 − 1
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
627
33.11. NVM Characteristics
Table 33-32. Maximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Units
1.62V to 2.7V
0
14
MHz
1
28
2
42
3
48
0
24
1
48
2.7V to 3.63V
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this
number is reached, a row erase is mandatory.
Table 33-33. Flash Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
CycNVM
Cycling Endurance(1)
-40°C < Ta < 85°C
25k
150k
-
Cycles
Note: 1. An endurance cycle is a write and an erase operation.
Table 33-34. EEPROM Emulation(1) Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
RetEEPROM10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
CycEEPROM
Cycling Endurance(2)
-40°C < Ta < 85°C
100k
600k
-
Cycles
Notes: 1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
Table 33-35. NVM Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tFPP
Page programming time
-
-
-
2.5
ms
tFRE
Row erase time
-
-
-
6
ms
tFCE
DSU chip erase time (CHIP_ERASE)
-
-
-
240
ms
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
628
33.12. Oscillators Characteristics
33.12.1. Crystal Oscillator (XOSC) Characteristics
33.12.1.1. Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 33-36. Digital Clock Characteristics
Symbol
Parameter
fCPXIN
XIN clock frequency
Conditions
Min.
Typ.
Max.
Units
-
-
32
MHz
33.12.1.2. Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between
XIN and XOUT as shown in the figure Oscillator Connection. The user must choose a crystal oscillator
where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be
found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed
as follows:
CLEXT = 2 CL − CSTRAY − CSHUNT
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal.
Table 33-37. Crystal Oscillator Characteristics
Symbol Parameter
fOUT
Crystal oscillator frequency
ESR
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
Conditions
Min. Typ. Max.
Units
0.4
-
32
MHz
f = 0.455 MHz, CL = 100pF
XOSC.GAIN = 0
-
-
5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
-
-
243
f = 8 MHz, CL = 20pF
XOSC.GAIN = 2
-
-
138
f = 16 MHz, CL = 20pF
XOSC.GAIN = 3
-
-
66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
-
-
56
CXIN
Parasitic capacitor load
-
5.9
-
pF
CXOUT
Parasitic capacitor load
-
3.2
-
pF
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
629
Symbol Parameter
Current Consumption
Conditions
Min. Typ. Max.
Units
f = 2MHz, CL = 20pF, AGC off
27
65
85
μA
f = 2MHz, CL = 20pF, AGC on
14
52
73
f = 4MHz, CL = 20pF, AGC off
61
117
150
f = 4MHz, CL = 20pF, AGC on
23
74
100
f = 8MHz, CL = 20pF, AGC off
131
226
296
f = 8MHz, CL = 20pF, AGC on
56
128
172
f = 16MHz, CL = 20pF, AGC off 305
502
687
f = 16MHz, CL = 20pF, AGC on 116
307
552
f = 32MHz, CL = 18pF, AGC off 1031 1622 2200
tSTARTUP Startup time
f = 32MHz, CL = 18pF, AGC on 278
615
1200
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
14K
48K
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
6800 19.5K
f = 8 MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
-
5550 13K
f = 16 MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
-
6750 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
-
5.3K 9.6K
cycles
Figure 33-6. Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
C LEXT
Xout
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
630
33.12.2. External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
33.12.2.1. Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32
pin.
Table 33-38. Digital Clock Characteristics
Symbol
Parameter
fCPXIN32
Conditions
Min.
Typ.
Max.
Units
XIN32 clock frequency
-
32.768
-
kHz
XIN32 clock duty cycle
-
50
-
%
33.12.2.2. Crystal Oscillator Characteristics
Figure 33-6 and the equation in Crystal Oscillator Characteristics also applie to the 32 kHz oscillator
connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the
range given in the table. The exact value of CL can be found in the crystal datasheet.
Table 33-39. 32kHz Crystal Oscillator Characteristics
Symbol Parameter
fOUT
Conditions
Min. Typ.
Crystal oscillator frequency
-
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL = 12.5 pF -
Max. Units
32768 -
Hz
28K
30K
cycles
CL
Crystal load capacitance
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.1
-
-
3.3
-
AGC off
-
1.22
2.19 μA
AGC on(1)
-
-
-
CL=12.5pF
-
-
141
Min.
Typ.
Max. Units
48
49
TQFP64/48/32 packages
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
ESR
Crystal equivalent series resistance
f=32.768kHz
Safety Factor = 3
kΩ
Note: 1. See revD/revC/revB errata concerning the XOSC32K.
33.12.3. Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 33-40. DFLL48M Characteristics - Closed Loop Mode(1)(2)
Symbol Parameter
Conditions
fOUT
Average Output frequency fREF = 32.768kHz
47
fREF
Reference frequency
0.732 32.768 35.1 kHz
Jitter
Period jitter
fREF = 32.768kHz
-
-
0.42 ns
IDFLL
Power consumption on
VDDIN
fREF = 32.768kHz. For SAMD20 revC devices
-
397
-
fREF = 32.768kHz. For SAMD20 revD and later. -
292
-
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
MHz
μA
631
Symbol Parameter
Conditions
Min.
Typ.
Max. Units
tLOCK
fREF = 32.768kHz
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
100
200
500
Quick lock disabled,
Chill cycle disabled,
CSTEP=3,FSTEP=1,
fREF = 32.768kHz
-
600
-
Lock time
μs
Note: 1. See revC/revB errata related to the DFLL48M.
2. All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL
closed loop mode with an external OSC reference or in DFLL closed loop mode using the internal
OSC8M (Only applicable for revC).
33.12.4. 32.768kHz Internal oscillator (OSC32K) Characteristics
Table 33-41. 32kHz RC Oscillator Characteristics
Symbol Parameter
Conditions
Min.
fOUT
Calibrated against a 32.768kHz reference at
25°C, over [-40, +85]°C, over [1.62, 3.63]V
28.508 32.768 34.734 kHz
Calibrated against a 32.768kHz reference at
25°C, at VDD = 3.3V
32.276 32.768 33.260
Calibrated against a 32.768kHz reference at
25°C, over [1.62, 3.63]V
31.457 32.768 34.079
IOSC32K
Output frequency
Current consumption
Typ.
Max.
Units
-
0.67
1.31
μA
tSTARTUP Startup time
-
1
2
cycle
Duty
-
50
-
%
Typ.
Max.
Units
Duty Cycle
33.12.5. Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table 33-42. Ultra Low Power Internal 32kHz RC Oscillator Characteristics
Symbol
Parameter
fOUT
Output frequency Calibrated against a 32.768kHz reference at
25°C, over [-40, +85]C, over [1.62, 3.63]V
IOSCULP32K(1)(2)
Conditions
Min.
25.559 32.768 38.011 kHz
Calibrated against a 32.768kHz reference at
25°C, at VDD = 3.3V
31.293 32.768 34.570
Calibrated against a 32.768kHz reference at
25°C, over [1.62, 3.63]V
31.293 32.768 34.570
-
-
125
nA
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
632
Symbol
Parameter
tSTARTUP
Duty
Conditions
Min.
Typ.
Max.
Units
Startup time
-
10
-
cycles
Duty Cycle
-
50
-
%
Notes: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
2. This oscillator is always on.
33.12.6. 8MHz RC Oscillator (OSC8M) Characteristics
Table 33-43. Internal 8MHz RC Oscillator Characteristics
Symbol Parameter
Conditions
fOUT
Calibrated against a 8MHz reference at 25°C, over [-40, 7.8
+85]C, over [1.62, 3.63]V
Output frequency
Min. Typ. Max. Units
8
8.16 MHz
Calibrated against a 8MHz reference at 25°C, at
VDD=3.3V
7.94 8
8.06
Calibrated against a 8MHz reference at 25°C, over
[1.62, 3.63]V
7.92 8
8.08
34.5 71
96
μA
tSTARTUP Startup time
-
2.1
3
μs
Duty
-
50
-
%
IOSC8M
Current consumption IIDLEIDLE2 on OSC32K versus IDLE2 on calibrated
OSC8M enabled at 8MHz (FRANGE=1, PRESC=0)
Duty cycle
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
633
33.13. PTC Typical Characteristics
33.13.1.
Figure 33-7. Power Consumption [μA]
1 sensor, noise countermeasures disabled, f=48MHz, Vcc=3.3V
140
120
100
80
Scan rate 10ms
60
Scan rate 50ms
40
Scan rate 100ms
Scan rate 200ms
20
0
1
2
4
8
16
32
64
Sample averaging
Figure 33-8. Power Consumption [μA]
1 sensor, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
200
180
160
140
120
Scan rate 10ms
100
80
Scan rate 50ms
60
Scan rate 100ms
40
Scan rate 200ms
20
0
1
2
4
8
16
32
64
Sample averaging
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
634
Figure 33-9. Power Consumption [μA]
10 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
1200
1000
800
Scan rate 10ms
600
Scan rate 50ms
Scan rate 100ms
400
Scan rate 200ms
200
Linear (Scan rate 50ms)
0
1
2
4
8
16
32
64
Sample averaging
Figure 33-10. Power Consumption [μA]
10 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
900
800
700
600
500
Scan rate 10ms
400
Scan rate 50ms
300
Scan rate 100ms
200
Scan rate 200ms
100
0
1
2
4
8
16
32
64
Sample averaging
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
635
Figure 33-11. Power Consumption [μA]
100 sensors, noise countermeasures disabled, f=48MHz, Vcc=3.3V
5000
4500
4000
3500
3000
Scan rate 10ms
2500
2000
Scan rate 50ms
1500
Scan rate 100ms
1000
Scan rate 200ms
500
0
1
2
4
8
16
32
64
Sample averaging
Figure 33-12. Power Consumption [μA]
100 sensors, noise countermeasures Enabled, f=48MHz, Vcc=3.3V
1800
1600
1400
1200
1000
Scan rate 10ms
800
Scan rate 50ms
600
Scan rate 100ms
400
Scan rate 200ms
200
0
1
2
4
8
16
32
64
Sample averaging
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
636
Figure 33-13. CPU Utilization
80 %
70 %
60 %
50 %
Channel count 1
40 %
Channel count 10
30 %
Channel count 100
20 %
10 %
0%
10
50
100
200
33.14. Timing Characteristics
33.14.1. External Reset
Table 33-44. External reset characteristics
Symbol
Parameter
Condition
tEXT
Minimum reset pulse width
Min.
Typ.
Max.
Units
10
-
-
ns
33.14.2. SERCOM in SPI Mode Timing
Figure 33-14. SPI timing requirements in master mode
SS
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
637
Figure 33-15. SPI timing requirements in slave mode
SS
tSSCKR
tSSS
tSSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data Input)
tSIH
MSB
tSOSS
MISO
(Data Output)
tSSCK
LSB
tSOS
tSOSH
MSB
LSB
Table 33-45. SPI timing characteristics and requirements(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
tSCK
SCK period
Master
tSCKW
SCK high/low width
Master
-
0.5*tSCK
-
tSCKR
SCK rise time(2)
Master
-
-
-
tSCKF
SCK fall time(2)
Master
-
-
-
tMIS
MISO setup to SCK
Master
-
29
-
tMIH
MISO hold after SCK
Master
-
8
-
tMOS
MOSI setup SCK
Master
-
tSCK/2 - 16
-
tMOH
MOSI hold after SCK
Master
-
16
-
tSSCK
Slave SCK Period
Slave
1*tCLK_APB
-
-
tSSCKW
SCK high/low width
Slave
0.5*tSSCK
-
-
tSSCKR
SCK rise time(2)
Slave
-
-
-
tSSCKF
SCK fall time(2)
Slave
-
-
-
tSIS
MOSI setup to SCK
Slave
tSSCK/2 - 19
-
-
tSIH
MOSI hold after SCK
Slave
tSSCK/2 - 5
-
-
tSSS
SS setup to SCK
Slave PRELOADEN=1
2*tCLK_APB + tSOS
-
-
tSOS+7
-
-
84
PRELOADEN=0
ns
tSSH
SS hold after SCK
Slave
tSIH - 4
-
-
tSOS
MISO setup SCK
Slave
-
tSSCK/2 - 20
-
tSOH
MISO hold after SCK
Slave
-
20
-
tSOSS
MISO setup after SS low
Slave
-
16
-
tSOSH
MISO hold after SS high
Slave
-
11
-
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
638
Notes: 1. These values are based on simulation. These values are not covered by test limits in
production.
2. See I/O Pin Characteristics
33.14.3. SERCOM in I2C Mode Timing
The following table describes the requirements for devices connected to the I2C Interface Bus. Timing
symbols refer to the figure below.
Figure 33-16. I2C Interface Bus Timing
tOF
tHIGH
tR
tLOW
tLOW
SCL
tS U;S TA
tHD;S TA
tHD;DAT
tS U;DAT
tS U;S TO
SDA
tBUF
Table
33-46. I2C
Interface
Timing(1)
Symbol Parameter
Conditions
Min.
Typ. Max. Units
-
-
7.0
10.0 50.0
tR
Rise time for both SDA and SCL(3)
tOF
Output fall time from VIHmin to VILmax (3)
10pF < Cb(2) < 400pF
tHD;STA
Hold time (repeated) START condition
fSCL > 100kHz, Master tLOW-9 -
-
tLOW
Low period of SCL Clock
fSCL > 100kHz
113
-
-
tBUF
Bus free time between a STOP and a START
condition
fSCL > 100kHz
tLOW
-
-
tSU;STA
Setup time for a repeated START condition
fSCL > 100kHz, Master tLOW+7 -
-
tHD;DAT
Data hold time
fSCL > 100kHz, Master 9
-
12
tSU;DAT
Data setup time
fSCL > 100kHz, Master 104
-
-
tSU;STO
Setup time for STOP condition
fSCL > 100kHz, Master tLOW+9 -
-
tSU;DAT;rx Data setup time (receive mode)
fSCL > 100kHz, Slave
51
-
56
tHD;DAT;tx Data hold time (send mode)
fSCL > 100kHz, Slave
71
90
138
300
ns
Notes: 1. These values are based on simulation. These values are not covered by test limits in
production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF.
3. These values are based on characterization. These values are not covered by test limits in production.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
639
33.14.4. SWD Timing
Figure 33-17. SWD Interface Signals
Read Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Thigh
Tos
Data
Data
Parity
Start
Tlow
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Tri State
Write Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Tis
Start
Tih
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Data
Data
Parity
Tri State
Table 33-47. SWD Timings(1)
Symbol Parameter
Conditions
Min. Max.
Units
Thigh
SWDCLK High period
10
500000 ns
Tlow
SWDCLK Low period
VVDDIO from 3.0 V to 3.6 V, maximum external
capacitor = 40 pF
10
500000
Tos
SWDIO output skew to falling
edge SWDCLK
-5
5
Tis
Input Setup time required
between SWDIO
4
-
Tih
Input Hold time required
between SWDIO and rising
edge SWDCLK
1
-
Note: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
640
34.
Packaging Information
34.1.
Thermal Considerations
Related Links
Junction Temperature on page 641
34.1.1.
Thermal Resistance Data
The following table summarizes the thermal resistance data depending on the package.
Table 34-1. Thermal Resistance Data
34.1.2.
Package Type
θJA
θJC
32-pin TQFP
68.0°C/W
25.8°C/W
48-pin TQFP
78.8°C/W
12.3°C/W
64-pin TQFP
66.7°C/W
11.9°C/W
32-pin QFN
37.2°C/W
13.1°C/W
48-pin QFN
33.0°C/W
11.4°C/W
64-pin QFN
33.5°C/W
11.2°C/W
64-ball UFBGA
67.4°C/W
12.4°C/W
45-ball WLCSP
37.0°C/W
0.36°C/W
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal
Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling
device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be
used to compute the resulting average chip-junction temperature TJ in °C.
Related Links
Thermal Considerations on page 641
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
641
34.2.
Package Drawings
34.2.1.
64 pin TQFP
Table 34-2. Device and Package Maximum Weight
300
mg
Table 34-3. Package Characteristics
Moisture Sensitivity Level
MSL3
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
642
Table 34-4. Package Reference
34.2.2.
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
64 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
643
Table 34-5. Device and Package Maximum Weight
200
mg
Table 34-6. Package Charateristics
Moisture Sensitivity Level
MSL3
Table 34-7. Package Reference
34.2.3.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
64-ball UFBGA
Table 34-8. Device and Package Maximum Weight
27.4
mg
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
644
Table 34-9. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 34-10. Package Reference
34.2.4.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E8
48 pin TQFP
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
645
Table 34-11. Device and Package Maximum Weight
140
mg
Table 34-12. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 34-13. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
646
34.2.5.
48 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Table 34-14. Device and Package Maximum Weight
140
mg
Table 34-15. Package Characteristics
Moisture Sensitivity Level
MSL3
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
647
Table 34-16. Package Reference
34.2.6.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
45-ball WLCSP
Table 34-17. Device and Package Maximum Weight
7.3
mg
Table 34-18. Package Characteristics
Moisture Sensitivity Level
MSL1
Table 34-19. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E1
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
648
34.2.7.
32 pin TQFP
Table 34-20. Device and Package Maximum Weight
100
mg
Table 34-21. Package Charateristics
Moisture Sensitivity Level
MSL3
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
649
Table 34-22. Package Reference
34.2.8.
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
32 pin QFN
Note: The exposed die attach pad is connected inside the device to GND and GNDANA.
Table 34-23. Device and Package Maximum Weight
90
mg
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
650
Table 34-24. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 34-25. Package Reference
34.3.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Table 34-26.
Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
3°C/s max.
Preheat Temperature 175°C ±25°C
150-200°C
Time Maintained Above 217°C
60-150s
Time within 5°C of Actual Peak Temperature
30s
Peak Temperature Range
260°C
Ramp-down Rate
6°C/s max.
Time 25°C to Peak Temperature
8 minutes max.
A maximum of three reflow passes is allowed per component.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
651
35.
35.1.
Schematic Checklist
Introduction
This chapter describes a common checklist which should be used when starting and reviewing the
schematics for a SAM D20 design. This chapter illustrates a recommended power supply connection,
how to connect external analog references, programmer, debugger, oscillator and crystal.
35.1.1.
Operation in Noisy Environment
If the device is operating in an environment with much electromagnetic noise it must be protected from
this noise to ensure reliable operation. In addition to following best practice EMC design guidelines, the
recommendations listed in the schematic checklist sections must be followed. In particular placing
decoupling capacitors very close to the power pins, a RC-filter on the RESET pin, and a pull-up resistor
on the SWCLK pin is critical for reliable operations. It is also relevant to eliminate or attenuate noise in
order to avoid that it reaches supply pins, I/O pins and crystals.
35.2.
Power Supply
The SAM D20 supports a single power supply from 1.62V - 3.63V.
35.2.1.
Power Supply Connections
Figure 35-1. Power Supply Schematic
Close to device
(for every pin)
1.62V-3.63V
VDDANA
10µF
100nF
GNDANA
VDDIO
100nF
VDDIN
100nF
10µF
VDDCORE
1µF
GND
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
652
Table 35-1. Power Supply Connections, VDDCORE From Internal Regulator
Signal Name Recommended Pin Connection
Description
VDDIO
Digital supply voltage
1.62V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
Decoupling/filtering inductor 10μH(1)(3)
VDDANA
1.62V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
Analog supply voltage
Ferrite bead(4) prevents the VDD noise interfering the VDDANA
VDDCORE
1.6V to 1.8V
Decoupling/filtering capacitor 1μF(1)(2)
Core supply voltage / external
decoupling pin
GND
Ground
GNDANA
Ground for the analog power domain
Note:
1. These values are only given as typical examples.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group, low ESR caps should be used for better decoupling.
3. An inductor should be added between the external power and the VDD for power filtering.
4. Ferrite bead has better filtering performance than the common inductor at high frequencies. It can
be added between VDD and VDDANA for preventing digital noise from entering the analog power
domain. The bead should provide enough impedance (e.g. 50Ω at 20MHz and 220Ω at 100MHz)
for separating the digital power from the analog power domain. Make sure to select a ferrite bead
designed for filtering applications with a low DC resistance to avoid a large voltage drop across the
ferrite bead.
35.3.
External Analog Reference Connections
The following schematic checklist is only necessary if the application is using one or more of the external
analog references. If the internal references are used instead, the following circuits are not necessary.
Figure 35-2. External Analog Reference Schematic With Two References
Close to device
(for every pin)
4.7μF
100nF
4.7μF
100nF
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
653
Figure 35-3. External Analog Reference Schematic With One Reference
Close to device
(for every pin)
VREFA
EXTERNAL
REFERENCE
4.7μF
100nF
GND
VREFB
100nF
GND
Table 35-2. External Analog Reference Connections
Signal Name
Recommended Pin Connection
Description
VREFx
1.0V to VDDANA - 0.6V for ADC
External reference from VREFx pin on
the analog port
1.0V to VDDANA- 0.6V for DAC
Decoupling/filtering capacitors
100nF(1)(2) and 4.7μF(1)
GND
1.
2.
35.4.
Ground
These values are given as a typical example.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group.
External Reset Circuit
The external reset circuit is connected to the RESET pin when the external reset function is used. If the
external reset function has been disabled, the circuit is not necessary. The reset switch can also be
removed, if the manual reset is not necessary. The RESET pin itself has an internal pull-up resistor,
hence it is optional to also add an external pull-up resistor.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
654
Figure 35-4. External Reset Circuit Example Schematic
VDD
10kΩ
330Ω
RESET
100nF
GND
A pull-up resistor makes sure that the reset does not go low unintended causing a device reset. An
additional resistor has been added in series with the switch to safely discharge the filtering capacitor, i.e.
preventing a current surge when shorting the filtering capacitor which again causes a noise spike that can
have a negative effect on the system.
Table 35-3. Reset Circuit Connections
Signal Name
Recommended Pin Connection
Description
RESET
Reset low level threshold voltage
VDDIO = 1.V - 2.0V: Below 0.33 * VDDIO
Reset pin
VDDIO = 2.7V - 3.6V: Below 0.36 * VDDIO
Decoupling/filter capacitor 100nF(1)
Pull-up resistor 10kΩ(1)(2)
Resistor in series with the switch 330Ω(1)
1.
2.
35.5.
These values are given as a typical example.
The SAM D20 features an internal pull-up resistor on the RESET pin, hence an external pull-up is
optional.
Clocks and Crystal Oscillators
The SAM D20 can be run from internal or external clock sources, or a mix of internal and external
sources. An example of usage will be to use the internal 8MHz oscillator as source for the system clock,
and an external 32.768kHz watch crystal as clock source for the Real-Time counter (RTC).
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
655
35.5.1.
External Clock Source
Figure 35-5. External Clock Source Example Schematic
External
Clock
XIN
XOUT/GPIO
NC/GPIO
Table 35-4. External Clock Source Connections
35.5.2.
Signal Name
Recommended Pin Connection
Description
XIN
XIN is used as input for an external clock signal
Input for inverting oscillator pin
XOUT/GPIO
Can be left unconnected or used as normal GPIO
Crystal Oscillator
Figure 35-6. Crystal Oscillator Example Schematic
XIN
15pF
XOUT
15pF
The crystal should be located as close to the device as possible. Long signal lines may cause too high
load to operate the crystal, and cause crosstalk to other parts of the system.
Table 35-5. Crystal Oscillator Checklist
Signal Name
Recommended Pin Connection
Description
XIN
Load capacitor 15pF(1)(2)
External crystal between 0.4 to 30MHz
XOUT
Load capacitor 15pF(1)(2)
1.
2.
35.5.3.
These values are given only as typical example.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group.
External Real Time Oscillator
The low frequency crystal oscillator is optimized for use with a 32.768kHz watch crystal. When selecting
crystals, load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into
consideration. Both values are specified by the crystal vendor.
The SAM D20 oscillator is optimized for very low power consumption, hence close attention should be
made when selecting crystals, see the table below for maximum ESR recommendations on 9pF and
12.5pF crystals.
The Low-frequency Crystal Oscillator provides an internal load capacitance of typical values available in
Table , 32kHz Crystal Oscillator Characteristics. This internal load capacitance and PCB capacitance can
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
656
allow to use a Crystal inferior to 12.5pF load capacitance without external capacitors as shown in the
following figure.
Table 35-6. Maximum ESR Recommendation for 32.768kHz Crystal
Crystal CL (pF)
Max ESR [kΩ]
12.5
313
Note: Maximum ESR is typical value based on characterization. These values are not covered by test
limits in production.
Figure 35-7. External Real Time Oscillator without Load Capacitor
XIN32
32.768kHz
XOUT32
However, to improve Crystal accuracy and Safety Factor, it can be recommended by crystal datasheet to
add external capacitors as shown in the next figure.
To find suitable load capacitance for a 32.768kHz crystal, consult the crystal datasheet.
Figure 35-8. External Real Time Oscillator with Load Capacitor
XIN32
22pF
32.768kHz
XOUT32
22pF
Table 35-7. External Real Time Oscillator Checklist
Signal Name
Recommended Pin Connection
Description
XIN32
Load capacitor 22pF(1)(2)
Timer oscillator input
XOUT32
Load capacitor 22pF(1)(2)
Timer oscillator output
1.
2.
35.5.4.
These values are given only as typical examples.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group.
Calculating the Correct Crystal Decoupling Capacitor
In order to calculate correct load capacitor for a given crystal one can use the model shown in the next
figure which includes internal capacitors CLn, external parasitic capacitance CELn and external load
capacitance CPn.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
657
Figure 35-9. Crystal Circuit With Internal, External and Parasitic Capacitance
CL2
CEL1
XOUT
CP1
CP2
External
XIN
Internal
CL1
CEL2
Using this model the total capacitive load for the crystal can be calculated as shown in the equation
below:
�tot =
��1 + ��1 + �EL1 ��2 + ��2 + �EL2
��1 + ��1 + �EL1 + ��2 + ��2 + �EL2
where Ctot is the total load capacitance seen by the crystal, this value should be equal to the load
capacitance value found in the crystal manufacturer datasheet.
The parasitic capacitance CELn can in most applications be disregarded as these are usually very small. If
accounted for the value is dependent on the PCB material and PCB layout.
For some crystal the internal capacitive load provided by the device itself can be enough. To calculate the
total load capacitance in this case. CELn and CPn are both zero, CL1 = CL2 = CL, and the equation reduces
to the following:
�tot =
��
2
The next table shows the device equivalent internal pin capacitance.
Table 35-8. Equivalent Internal Pin Capacitance
Symbol
Value
Description
CXIN32
3.05pF
Equivalent internal pin capacitance
CXOUT32
3.29pF
Equivalent internal pin capacitance
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
658
35.6.
Unused or Unconnected Pins
For unused pins the default state of the pins for the will give the lowest current leakage. There is thus no
need to do any configuration of the unused pins in order to lower the power consumption.
35.7.
Programming and Debug Ports
For programming and/or debugging the SAM D20 the device should be connected using the Serial Wire
Debug, SWD, interface. Currently the SWD interface is supported by several Atmel and third party
programmers and debuggers, like the SAM-ICE, JTAGICE3 or SAM D20 Xplained Pro (SAM D20
evaluation kit) Embedded Debugger.
Refer to the SAM-ICE, JTAGICE3 or SAM D20 Xplained Pro user guides for details on debugging and
programming connections and options. For connecting to any other programming or debugging tool, refer
to that specific programmer or debugger’s user guide.
The SAM D20 Xplained Pro evaluation board for the SAM D20 supports programming and debugging
through the onboard embedded debugger so no external programmer or debugger is needed.
Note that a pull-up resistor on the SWCLK pin is critical for reliable operations. Refer to related link for
more information.
Figure 35-10. SWCLK Circuit Connections
VDD
1kΩ
SWCLK
Table 35-9. SWCLK Circuit Connections
Pin Name
Description
Recommended Pin Connection
SWCLK
Serial wire clock pin
Pull-up resistor 1kΩ
Related Links
Operation in Noisy Environment on page 652
35.7.1.
Cortex Debug Connector (10-pin)
For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the
signals should be connected as shown in the figure below with details described in the next table.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
659
Figure 35-11. Cortex Debug Connector (10-pin)
VDD
Cortex Debug Connector
(10-pin)
VTref
1
SWDIO
GND
SWDCLK
GND
NC
NC
NC
NC
nRESET
RESET
SWCLK
SWDIO
GND
Table 35-10. Cortex Debug Connector (10-pin)
Header Signal
Name
Description
Recommended Pin
Connection
SWDCLK
Serial wire clock pin
Pull-up resistor 1kΩ
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
Refer to External Reset Circuit.
35.7.2.
VTref
Target voltage sense, should be connected to the
device VDD
GND
Ground
10-pin JTAGICE3 Compatible Serial Wire Debug Interface
The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin)
directly, hence a special pinout is needed to directly connect the SAM D20 to the JTAGICE3, alternatively
one can use the JTAGICE3 squid cable and manually match the signals between the JTAGICE3 and
SAM D20. The following figure describes how to connect a 10-pin header that support connecting the
JTAGICE3 directly to the SAM D20 without the need for a squid cable.
To connect the JTAGICE3 programmer and debugger to the SAM D20, one can either use the JTAGICE3
squid cable, or use a 10-pin connector as shown in the figure below with details given in the next table to
connect to the target using the JTAGICE3 50 mil cable directly.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
660
Figure 35-12. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
10-pin JTAGICE3 Compatible
VDD
Serial Wire Debug Header
SWDCLK
1
NC
SWDIO
GND
RESET
VTG
RESET
NC
NC
NC
NC
SWCLK
SWDIO
GND
Table 35-11. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
35.7.3.
Header Signal Name
Description
SWDCLK
Serial wire clock pin
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
VTG
Target voltage sense, should be connected to the device VDD
GND
Ground
20-pin IDC JTAG Connector
For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the
signals should be connected as shown in the next figure with details described in the table.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
661
Figure 35-13. 20-pin IDC JTAG Connector
VDD
20-pin IDC JTAG Connector
VCC
1
NC
NC
GND
NC
GND
SWDIO
GND
SWDCLK
GND
NC
GND
NC
GND*
nRESET
GND*
NC
GND*
NC
GND*
RESET
SWCLK
SWDIO
GND
Table 35-12. 20-pin IDC JTAG Connector
Header Signal Name Description
SWDCLK
Serial wire clock pin
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
VCC
Target voltage sense, should be connected to the device VDD
GND
Ground
GND*
These pins are reserved for firmware extension purposes. They can be left open
or connected to GND in normal debug environment. They are not essential for
SWD in general.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
662
36.
Errata
36.1.
Device Variant A
The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks
evolution of the die.
36.1.1.
Die Revision A
Not sampled.
36.1.2.
Die Revision B
36.1.2.1. Device
1 – When VDDIN is lower than the POR threshold during power rise or
fall, an internal pull-up resistor is enabled on pins with PTC
functionality (see PORT Function Multiplexing). Note that this behavior
will be present even if PTC functionality is not enabled on the pin. The
POR level is defined in the “Power-On Reset (POR) Characteristics”
chapter.
Errata reference: 10805
Fix/Workaround:
Use a pin without PTC functionality if the pull-up could damage your
application during power up.
2 – The values stored in the NVM software calibration area for the DFLL
calibration are not valid.
Errata reference: 12843
Fix/Workaround:
None.
3 – In the table ""NVM User Row Mapping"", the WDT Window bitfield
default value on silicon is not as specified in the datasheet. The
datasheet defines the default value as 0x5, while it is 0xB on silicon.
Errata reference: 13951
Fix/Workaround:
None.
4 – Clock Failure detection for external OSC does not work in standby
mode.
Errata reference: 12688
Fix/Workaround:
Before entering standby mode, move the CPU clock to an internal RC,
disable external OSC and disable the Clock Failure detector. Upon CPU
wakeup, restart external OSC (if it does not start, the failure occurred during
standby), enable the Clock Failure detector and move the CPU clock to the
external OSC.
5 – If APB clock is stopped and GCLK clock is running, APB read
access to read-synchronized registers will freeze the system. The CPU
and the DAP AHB-AP are stalled, as a consequence debug operation is
impossible.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
663
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 – The PORT output driver strength feature is not available.
Errata reference: 12684
Fix/Workaround:
None
7 – The SYSTICK calibration value is incorrect.
Errata reference: 14153
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not
be used to initialize the Systick RELOAD value register, which should be
initialized instead with a value depending on the main clock frequency and
on the tick period required by the application. For a detailed description of
the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
8 – Maximum toggle frequency on all pins in worst case operating
condition is 8MHz. This affects all operations on the pins, including
serial communications.
Errata reference: 10335
Fix/Workaround:
None.
9 – Do not enable Timers/Counters, AC (Analog Comparator), GCLK
(Generic Clock Controller), and SERCOM (I2C and SPI) to control
Digital outputs in standby sleep mode.
Errata reference: 12786
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep
mode. This is done by setting the RUNSTDBY bit in the VREG register.
10 – After a clock failure detection (INTFLAG.CFD = 1), if INTFLAG.CFD
is cleared while the clock is still broken, the system is stuck.
Errata reference: 12687
Fix/Workaround:
After a clock failure detection, do not clear INTFLAG.CFD or perform a
system reset.
11 – With default bit and register settings the device does not work as
specified in STANDBY mode if load current exceeds 100µA.
Errata reference: 11082
Fix/Workaround:
Set the FORCELDO bit in the VREG register.
12 – In Standby, Idle1 and Idle2 sleep modes the device might not wake
up from sleep. An External Reset, Power on Reset or Watch Dog Reset
will start the device again.
Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
664
device. The average power consumption of the device will increase with
20uA compared to numbers in the electrical characteristics chapter.
13 – The temperature sensor is not accurate. No value is written into
the Temperature Log row during production test.
Errata reference: 11731
Fix/Workaround:
None
14 – The DFLLVAL.COARSE, DFLLVAL.FINE, DFLLMUL.CSTEP and
DFLLMUL.FSTEP bit groups are not correctly located in the register
map. DFLLVAL.COARSE is only 5 bits and located in DFLLVAL[12..8].
DFLLVAL.FINE is only 8 bits and located in DFLLVAL[7:0].
DFLLMUL.CSTEP is only 5 bits and located in DFLLMUL[28:24].
DFLLMUL.FSTEP is only 8 bits and located in DFLLMUL[23:16]
Errata reference: 10988
Fix/Workaround:
DFLLVAL.COARSE, DFLLVAL.FINE, DFLLMUL.CSTEP and
DFLLMUL.FSTEP should not be used if code compatibility is required with
future device revisions.
15 – If the external XOSC32K is broken, neither the external pin RST
nor the GCLK software reset can reset the GCLK generators using
XOSC32K as source clock.
Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
36.1.2.2. Flash
1 – When cache read mode is set to deterministic (READMODE=2),
setting CACHEDIS=1 does not lead to 0 wait states on Flash access.
Errata reference: 10830
Fix/Workaround:
When disabling the cache (CTRLB.CACHEDIS=1), the user must also set
READMODE to 0 (CTRLB.READMODE=0).
2 – When NVMCTRL issues either erase or write commands and the
NVMCTRL cache is not in LOW_POWER mode, CPU hardfault
exception may occur.
Errata reference: 10804
Fix/Workaround:
Either:
- turn off cache before issuing flash commands by setting the NVMCTRL
CTRLB.CACHEDIS bit to one.
- Configure the cache in LOW_POWER mode by writing 0x1 into the
NVMCTRL CTRLB.READMODE bits.
36.1.2.3. DSU
1 – If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU
will be held in ""CPU Reset Extension"" after any upcoming reset
event.
Errata reference: 12015
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
665
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by
writing a one in the DSU STATUSA.CRSTEXT register or by applying an
external reset with SWCLK high or by power cycling the device.
2 – The MBIST ""Pause-on-Error"" feature is not functional on this
device.
Errata reference: 14324
Fix/Workaround:
Do not use the ""Pause-on-Error"" feature.
36.1.2.4. PM
1 – In debug mode, if a watchdog reset occurs, the debug session is
lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
2 – The SysTick timer does not generate a wake up signal to the Power
Manager, and therefore cannot be used to wake up the CPU from sleep
mode.
Errata reference: 11012
Fix/Workaround:
None.
36.1.2.5. GCLK
1 – When the GCLK generator is enabled (GENCTRL.GENEN = 1), set
as output (GENCTRL.OE = 1) and use a division factor of one
(GENDIV.DIV = 1 or 0 and GENCTRL.DIVSEL=0), the GCLK_IO might not
be set to the configured GENCTRL.OOV value after disabling the GCLK
generator (GENCTRL.GENEN=0).
Errata reference: 10716
Fix/Workaround:
Disable the OE request of the GCLK generator (GENCTRL.OE = 0) before
disabling the GCLK generator (GENCTRL.GENEN = 0).
2 – The GCLK Generator clock is stuck when disabling the generator
and changing the division factor from one to a different value while the
GCLK generator is set as output. When the GCLK generator is enabled
(GENCTRL.GENEN=1), set as output (GENCTRL.OE=1) and use a
division factor of one (GENDIV.DIV=1 or 0 and GENCTRL.DIVSEL=0), if
the division factor is written to a value different of one or zero after
disabling the GCLK generator (GENCTRL.GENEN=0), the GCLK
generator will be stuck.
Errata reference: 10686
Fix/Workaround:
Disable the OE request of the GCLK generator (GENCTRL.OE=0) before
disabling the GCLK generator (GENCTRL.GENEN=0).
3 – When a GCLK is locked and the generator used by the locked GCLK
is not GCLK generator 1, issuing a GCLK software reset will lock up the
GCLK with the SYNCBUSY flag always set.
Errata reference: 10645
Fix/Workaround:
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
666
Do not issue a GCLK SWRST or map GCLK generator 1 to ""locked""
GCLKs.
36.1.2.6. DFLL48M
1 – If the firmware writes to the DFLLMUL.MUL register in the same
cycle as the closed loop mode tries to update it, the fine calibration will
first be reset to midpoint and then incremented/decremented by the
closed loop mode. Then the coarse calibration will be performed with
the updated fine value. If this happens before the dfll have got a lock,
the new fine calibration value can be anything between 128DFLLMUL.FSTEP and 128+DFLLMUL.FSTEP which could give smaller
calibration range for the fine calibration.
Errata reference: 10634
Fix/Workaround:
Always wait until the DFLL48M has locked before writing the DFLLMUL.MUL
register
2 – The DFLL clock must be requested before being configured
otherwise a write access to a DFLL register can freeze the device.
Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
3 – Changing the DFLLVAL.FINE calibration bits of the DFLL48M Digital
Frequency Locked Loop might result in a short output frequency
overshoot. This might occur both in open loop mode while writing
DFLLVAL.FINE by software and closed loop mode when the DFLL
automatically adjusts its output frequency.
Errata reference: 10537
Fix/Workaround:
- When using DFLL48M in open loop mode, be sure the DFLL48M is not
used by any module while DFLLVAL.FINE is written.
- When using DFLL48M in closed loop mode, be sure that
DFLLCTRL.STABLE is written to 1. The DFLL clock should not be used by
any modules until the DFLL locks are set.
If the application requires on-the-fly DFLL calibration (temperature/VCC drift
compensation), the firmware should perform, either periodically or when the
DFLL48M frequency differ too much from target frequency (indicated by
DFLLVAL.DIFF), the following:
o Switch system clock/module clocks to different clock than DFLL48M
o Re-initiate a DFLL48M closed loop lock sequence by disabling and reenabling the DFLL48M
o Wait for fine lock (PCLKSR.DFLLLCKF set to 1)
o Switch back system clock/module clocks to the DFLL48M
Better accuracy is achieved using a high multiplier for the DFLL48M, using a
scaled down or slow clock as reference. A multiplier of 6 will have a
theoretical worst case frequency deviation from the reference clock of +/8.33%. A multiplier of 500 will have a theoretical worst case frequency
deviation from the reference clock of +/- 0.1%.
4 – If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
667
interrupt will be generated. These interrupts will be generated even if
the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts.
Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL
Interrupt Flag Status and Clear register (INTFLAG) are both set before
enabling the DFLLOOB interrupt.
36.1.2.7. XOSC32K
1 – The automatic amplitude control of the XOSC32K does not work.
Errata reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
36.1.2.8. EIC
1 – When the EIC is configured to generate an interrupt on a low level
or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled
(CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin
on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using
CTRLA ENABLE bit.
Errata reference: 15341
Fix/Workaround:
Clear the INTFLAG bit once the EIC enabled and before enabling the
interrupts.
36.1.2.9. NVMCTRL
1 – Default value of MANW in NVM.CTRLB is 0.
This can lead to spurious writes to the NVM if a data write is done
through a pointer with a wrong address corresponding to NVM area.
Errata reference: 13134
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 – When external reset is active it causes a high leakage current on
VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
3 – When the part is secured and EEPROM emulation area configured
to none, the CRC32 is not executed on the entire flash area but up to
the on-chip flash size minus half a row.
Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash
size minus half row.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
668
36.1.2.10. EVSYS
1 – Using synchronous or resynchronized paths, some channels
(0,3,6,7) detect an overrun on every event even if no overrun condition
is present.
Errata reference: 10895
Fix/Workaround:
- Ignore overrun detection bit for channels 0,3,6,7.
- Use channels 1,2,4,5 if overrun detection is required.
2 – Changing the selected generator of a channel can trigger a
spurious interrupt/event.
Errata reference: 10443
Fix/Workaround:
To change the generator of a channel, first write with EDGESEL written to
zero, then perform a second write with EDGESEL written to its target value.
36.1.2.11. SERCOM
1 – The SERCOM SPI CTRLA register bit 17 (DOPO Bit 1) will always be
zero, and cannot be changed. Therefore the SERCOM SPI cannot be
switched between master and slave mode on the same DI and DO pins.
Errata reference: 10812
Fix/Workaround:
Connect the alternate DI and DO pins externally and use the port MUX to
switch between pin configurations for master and slave functionality.
2 – When the SERCOM is in slave SPI mode, the BUFOVF flag is not
automatically cleared when CTRLB.RXEN is set to zero.
Errata reference: 10563
Fix/Workaround:
The BUFOVF flag must be manually cleared by software.
3 – In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters
debug mode. Instead, it is stopped when the current byte transaction is
completed and the corresponding interrupt is triggered if enabled.
Errata reference: 12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
4 – The SERCOM SPI BUFOVF status bit is not set until the next
character is received after a buffer overflow, instead of directly after
the overflow has occurred. Furthermore the CTRLA.IBON bit will
always be zero and cannot be changed.
Errata reference: 10551
Fix/Workaround:
None.
36.1.2.12. TC
1 – Spurious TC overflow and Match/Capture events may occur.
Errata reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the
corresponding Interrupts instead.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
669
36.1.2.13. ADC
1 – When the ADC bus clock frequency(CLK_ADC_APB) is smaller than
the ADC asynchronous clock frequency(GCLK_ADC), issuing an ADC
SWRST (ADC.CTRLA.SWRST) will lock up the ADC with the
SYNCBUSY (ADC.STATUS.SYNCBUSY) flag always set.
Errata reference: 10987
Fix/Workaround:
Do not issue an ADC SWRST if the ADC bus clock frequency
(CLK_ADC_APB) is smaller than the ADC asynchronous clock
frequency(GCLK_ADC).
2 – The automatic right shift of the result when accumulating/averaging
ADC samples does not work.
Errata reference: 10530
Fix/Workaround:
To accumulate or average more than 16 samples, one must add the number
of automatic right shifts to AVGCTRL.ADJRES to perform the correct
number of right shifts. For example, for averaging 128 samples,
AVGCTRL.ADJRES must be written to 7 instead of 4, as the automatic right
shift of 3 is not done. For oversampling to 16 bits resolution,
AVGCTRL.ADJRES must be written to 4 instead of 0 as the automatic right
shift of 4 is not done.
The maximum number of right shifts that can be done using ADJRES is 7.
This means that when averaging more than 128 samples, the result will be
more than 12 bits, and the additional right shifts to get the result down to 12
bits must be done by firmware.
36.1.2.14. BOD33
1 – The BOD33 HYST bit is not updated from NVM user row at power
on. The reset value of this bit is zero.
Errata reference: 10565
Fix/Workaround:
None.
36.1.2.15. BOD12
1 – The BOD12 HYST bit is not updated from NVM user row at power
on. The reset value of this bit is zero.
Errata reference: 10568
Fix/Workaround:
None.
36.1.2.16. PTC
1 – Some gain settings for the PTC in self-capacitance mode do not
work. The two lowest gain settings are not selectable and an attempt
by the QTouch Library to set enable of these may result in a higher
sensitivity than optimal for the sensor. The PTC will not detect all
touches. This errata does not affect mutual-capacitance mode which
operates as specified.
Errata reference: 10684
Fix/Workaround:
Use SAM D20 revision C or later for self-capacitance touch sensing.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
670
2 – WCOMP interrupt flag is not stable. The WCOMP interrupt flag will
not always be set as described in the datasheet.
Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
36.1.3.
Die Revision C
36.1.3.1. Device
1 – When VDDIN is lower than the POR threshold during power rise or
fall, an internal pull-up resistor is enabled on pins with PTC
functionality (see PORT Function Multiplexing). Note that this behavior
will be present even if PTC functionality is not enabled on the pin. The
POR level is defined in the “Power-On Reset (POR) Characteristics”
chapter.
Errata reference: 10805
Fix/Workaround:
Use a pin without PTC functionality if the pull-up could damage your
application during power up.
2 – The values stored in the NVM software calibration area for the DFLL
calibration are not valid.
Errata reference: 12843
Fix/Workaround:
None.
3 – In the table ""NVM User Row Mapping"", the WDT Window bitfield
default value on silicon is not as specified in the datasheet. The
datasheet defines the default value as 0x5, while it is 0xB on silicon.
Errata reference: 13951
Fix/Workaround:
None.
4 – Clock Failure detection for external OSC does not work in standby
mode.
Errata reference: 12688
Fix/Workaround:
Before entering standby mode, move the CPU clock to an internal RC,
disable external OSC and disable the Clock Failure detector. Upon CPU
wakeup, restart external OSC (if it does not start, the failure occurred during
standby), enable the Clock Failure detector and move the CPU clock to the
external OSC.
5 – If APB clock is stopped and GCLK clock is running, APB read
access to read-synchronized registers will freeze the system. The CPU
and the DAP AHB-AP are stalled, as a consequence debug operation is
impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 – The PORT output driver strength feature is not available.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
671
Errata reference: 12684
Fix/Workaround:
None
7 – The SYSTICK calibration value is incorrect.
Errata reference: 14153
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not
be used to initialize the Systick RELOAD value register, which should be
initialized instead with a value depending on the main clock frequency and
on the tick period required by the application. For a detailed description of
the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
8 – Maximum toggle frequency on all pins in worst case operating
condition is 8MHz. This affects all operations on the pins, including
serial communications.
Errata reference: 10335
Fix/Workaround:
None.
9 – Do not enable Timers/Counters, AC (Analog Comparator), GCLK
(Generic Clock Controller), and SERCOM (I2C and SPI) to control
Digital outputs in standby sleep mode.
Errata reference: 12786
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep
mode. This is done by setting the RUNSTDBY bit in the VREG register.
10 – After a clock failure detection (INTFLAG.CFD = 1), if INTFLAG.CFD
is cleared while the clock is still broken, the system is stuck.
Errata reference: 12687
Fix/Workaround:
After a clock failure detection, do not clear INTFLAG.CFD or perform a
system reset.
11 – With default bit and register settings the device does not work as
specified in STANDBY mode if load current exceeds 100µA.
Errata reference: 11082
Fix/Workaround:
Set the FORCELDO bit in the VREG register.
12 – In Standby, Idle1 and Idle2 sleep modes the device might not wake
up from sleep. An External Reset, Power on Reset or Watch Dog Reset
will start the device again.
Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with
20uA compared to numbers in the electrical characteristics chapter.
13 – The temperature sensor is not accurate. No value is written into
the Temperature Log row during production test.
Errata reference: 11731
Fix/Workaround:
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
672
None
14 – The DFLLVAL.COARSE, DFLLVAL.FINE, DFLLMUL.CSTEP and
DFLLMUL.FSTEP bit groups are not correctly located in the register
map. DFLLVAL.COARSE is only 5 bits and located in DFLLVAL[12..8].
DFLLVAL.FINE is only 8 bits and located in DFLLVAL[7:0].
DFLLMUL.CSTEP is only 5 bits and located in DFLLMUL[28:24].
DFLLMUL.FSTEP is only 8 bits and located in DFLLMUL[23:16]
Errata reference: 10988
Fix/Workaround:
DFLLVAL.COARSE, DFLLVAL.FINE, DFLLMUL.CSTEP and
DFLLMUL.FSTEP should not be used if code compatibility is required with
future device revisions.
15 – If the external XOSC32K is broken, neither the external pin RST
nor the GCLK software reset can reset the GCLK generators using
XOSC32K as source clock.
Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
36.1.3.2. Flash
1 – When cache read mode is set to deterministic (READMODE=2),
setting CACHEDIS=1 does not lead to 0 wait states on Flash access.
Errata reference: 10830
Fix/Workaround:
When disabling the cache (CTRLB.CACHEDIS=1), the user must also set
READMODE to 0 (CTRLB.READMODE=0).
2 – When NVMCTRL issues either erase or write commands and the
NVMCTRL cache is not in LOW_POWER mode, CPU hardfault
exception may occur.
Errata reference: 10804
Fix/Workaround:
Either:
- turn off cache before issuing flash commands by setting the NVMCTRL
CTRLB.CACHEDIS bit to one.
- Configure the cache in LOW_POWER mode by writing 0x1 into the
NVMCTRL CTRLB.READMODE bits.
36.1.3.3. DSU
1 – If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU
will be held in ""CPU Reset Extension"" after any upcoming reset
event.
Errata reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by
writing a one in the DSU STATUSA.CRSTEXT register or by applying an
external reset with SWCLK high or by power cycling the device.
2 – The MBIST ""Pause-on-Error"" feature is not functional on this
device.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
673
Errata reference: 14324
Fix/Workaround:
Do not use the ""Pause-on-Error"" feature.
36.1.3.4. PM
1 – In debug mode, if a watchdog reset occurs, the debug session is
lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
2 – The SysTick timer does not generate a wake up signal to the Power
Manager, and therefore cannot be used to wake up the CPU from sleep
mode.
Errata reference: 11012
Fix/Workaround:
None.
36.1.3.5. GCLK
1 – When the GCLK generator is enabled (GENCTRL.GENEN = 1), set
as output (GENCTRL.OE = 1) and use a division factor of one
(GENDIV.DIV = 1 or 0 and GENCTRL.DIVSEL=0), the GCLK_IO might not
be set to the configured GENCTRL.OOV value after disabling the GCLK
generator (GENCTRL.GENEN=0).
Errata reference: 10716
Fix/Workaround:
Disable the OE request of the GCLK generator (GENCTRL.OE = 0) before
disabling the GCLK generator (GENCTRL.GENEN = 0).
2 – The GCLK Generator clock is stuck when disabling the generator
and changing the division factor from one to a different value while the
GCLK generator is set as output. When the GCLK generator is enabled
(GENCTRL.GENEN=1), set as output (GENCTRL.OE=1) and use a
division factor of one (GENDIV.DIV=1 or 0 and GENCTRL.DIVSEL=0), if
the division factor is written to a value different of one or zero after
disabling the GCLK generator (GENCTRL.GENEN=0), the GCLK
generator will be stuck.
Errata reference: 10686
Fix/Workaround:
Disable the OE request of the GCLK generator (GENCTRL.OE=0) before
disabling the GCLK generator (GENCTRL.GENEN=0).
3 – When a GCLK is locked and the generator used by the locked GCLK
is not GCLK generator 1, issuing a GCLK software reset will lock up the
GCLK with the SYNCBUSY flag always set.
Errata reference: 10645
Fix/Workaround:
Do not issue a GCLK SWRST or map GCLK generator 1 to ""locked""
GCLKs.
36.1.3.6. DFLL48M
1 – If the firmware writes to the DFLLMUL.MUL register in the same
cycle as the closed loop mode tries to update it, the fine calibration will
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
674
first be reset to midpoint and then incremented/decremented by the
closed loop mode. Then the coarse calibration will be performed with
the updated fine value. If this happens before the dfll have got a lock,
the new fine calibration value can be anything between 128DFLLMUL.FSTEP and 128+DFLLMUL.FSTEP which could give smaller
calibration range for the fine calibration.
Errata reference: 10634
Fix/Workaround:
Always wait until the DFLL48M has locked before writing the DFLLMUL.MUL
register
2 – The DFLL clock must be requested before being configured
otherwise a write access to a DFLL register can freeze the device.
Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
3 – Changing the DFLLVAL.FINE calibration bits of the DFLL48M Digital
Frequency Locked Loop might result in a short output frequency
overshoot. This might occur both in open loop mode while writing
DFLLVAL.FINE by software and closed loop mode when the DFLL
automatically adjusts its output frequency.
Errata reference: 10537
Fix/Workaround:
- When using DFLL48M in open loop mode, be sure the DFLL48M is not
used by any module while DFLLVAL.FINE is written.
- When using DFLL48M in closed loop mode, be sure that
DFLLCTRL.STABLE is written to 1. The DFLL clock should not be used by
any modules until the DFLL locks are set.
If the application requires on-the-fly DFLL calibration (temperature/VCC drift
compensation), the firmware should perform, either periodically or when the
DFLL48M frequency differ too much from target frequency (indicated by
DFLLVAL.DIFF), the following:
o Switch system clock/module clocks to different clock than DFLL48M
o Re-initiate a DFLL48M closed loop lock sequence by disabling and reenabling the DFLL48M
o Wait for fine lock (PCLKSR.DFLLLCKF set to 1)
o Switch back system clock/module clocks to the DFLL48M
Better accuracy is achieved using a high multiplier for the DFLL48M, using a
scaled down or slow clock as reference. A multiplier of 6 will have a
theoretical worst case frequency deviation from the reference clock of +/8.33%. A multiplier of 500 will have a theoretical worst case frequency
deviation from the reference clock of +/- 0.1%.
4 – If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds
interrupt will be generated. These interrupts will be generated even if
the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts.
Errata reference: 10669
Fix/Workaround:
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
675
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL
Interrupt Flag Status and Clear register (INTFLAG) are both set before
enabling the DFLLOOB interrupt.
36.1.3.7. XOSC32K
1 – The automatic amplitude control of the XOSC32K does not work.
Errata reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
36.1.3.8. EIC
1 – When the EIC is configured to generate an interrupt on a low level
or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled
(CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin
on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using
CTRLA ENABLE bit.
Errata reference: 15341
Fix/Workaround:
Clear the INTFLAG bit once the EIC enabled and before enabling the
interrupts.
36.1.3.9. NVMCTRL
1 – Default value of MANW in NVM.CTRLB is 0.
This can lead to spurious writes to the NVM if a data write is done
through a pointer with a wrong address corresponding to NVM area.
Errata reference: 13134
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 – When external reset is active it causes a high leakage current on
VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
3 – When the part is secured and EEPROM emulation area configured
to none, the CRC32 is not executed on the entire flash area but up to
the on-chip flash size minus half a row.
Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash
size minus half row.
36.1.3.10. EVSYS
1 – Using synchronous or resynchronized paths, some channels
(0,3,6,7) detect an overrun on every event even if no overrun condition
is present.
Errata reference: 10895
Fix/Workaround:
- Ignore overrun detection bit for channels 0,3,6,7.
- Use channels 1,2,4,5 if overrun detection is required.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
676
2 – Changing the selected generator of a channel can trigger a
spurious interrupt/event.
Errata reference: 10443
Fix/Workaround:
To change the generator of a channel, first write with EDGESEL written to
zero, then perform a second write with EDGESEL written to its target value.
36.1.3.11. SERCOM
1 – The SERCOM SPI CTRLA register bit 17 (DOPO Bit 1) will always be
zero, and cannot be changed. Therefore the SERCOM SPI cannot be
switched between master and slave mode on the same DI and DO pins.
Errata reference: 10812
Fix/Workaround:
Connect the alternate DI and DO pins externally and use the port MUX to
switch between pin configurations for master and slave functionality.
2 – When the SERCOM is in slave SPI mode, the BUFOVF flag is not
automatically cleared when CTRLB.RXEN is set to zero.
Errata reference: 10563
Fix/Workaround:
The BUFOVF flag must be manually cleared by software.
3 – In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters
debug mode. Instead, it is stopped when the current byte transaction is
completed and the corresponding interrupt is triggered if enabled.
Errata reference: 12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
4 – The SERCOM SPI BUFOVF status bit is not set until the next
character is received after a buffer overflow, instead of directly after
the overflow has occurred. Furthermore the CTRLA.IBON bit will
always be zero and cannot be changed.
Errata reference: 10551
Fix/Workaround:
None.
36.1.3.12. TC
1 – Spurious TC overflow and Match/Capture events may occur.
Errata reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the
corresponding Interrupts instead.
36.1.3.13. ADC
1 – When the ADC bus clock frequency(CLK_ADC_APB) is smaller than
the ADC asynchronous clock frequency(GCLK_ADC), issuing an ADC
SWRST (ADC.CTRLA.SWRST) will lock up the ADC with the
SYNCBUSY (ADC.STATUS.SYNCBUSY) flag always set.
Errata reference: 10987
Fix/Workaround:
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
677
Do not issue an ADC SWRST if the ADC bus clock frequency
(CLK_ADC_APB) is smaller than the ADC asynchronous clock
frequency(GCLK_ADC).
2 – The automatic right shift of the result when accumulating/averaging
ADC samples does not work.
Errata reference: 10530
Fix/Workaround:
To accumulate or average more than 16 samples, one must add the number
of automatic right shifts to AVGCTRL.ADJRES to perform the correct
number of right shifts. For example, for averaging 128 samples,
AVGCTRL.ADJRES must be written to 7 instead of 4, as the automatic right
shift of 3 is not done. For oversampling to 16 bits resolution,
AVGCTRL.ADJRES must be written to 4 instead of 0 as the automatic right
shift of 4 is not done.
The maximum number of right shifts that can be done using ADJRES is 7.
This means that when averaging more than 128 samples, the result will be
more than 12 bits, and the additional right shifts to get the result down to 12
bits must be done by firmware.
36.1.3.14. BOD33
1 – The BOD33 HYST bit is not updated from NVM user row at power
on. The reset value of this bit is zero.
Errata reference: 10565
Fix/Workaround:
None.
36.1.3.15. BOD12
1 – The BOD12 HYST bit is not updated from NVM user row at power
on. The reset value of this bit is zero.
Errata reference: 10568
Fix/Workaround:
None.
36.1.3.16. PTC
1 – WCOMP interrupt flag is not stable. The WCOMP interrupt flag will
not always be set as described in the datasheet.
Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
36.1.4.
Die Revision D
36.1.4.1. Device
1 – When VDDIN is lower than the POR threshold during power rise or
fall, an internal pull-up resistor is enabled on pins with PTC
functionality (see PORT Function Multiplexing). Note that this behavior
will be present even if PTC functionality is not enabled on the pin. The
POR level is defined in the “Power-On Reset (POR) Characteristics”
chapter.
Errata reference: 10805
Fix/Workaround:
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
678
Use a pin without PTC functionality if the pull-up could damage your
application during power up.
2 – In the table ""NVM User Row Mapping"", the WDT Window bitfield
default value on silicon is not as specified in the datasheet. The
datasheet defines the default value as 0x5, while it is 0xB on silicon.
Errata reference: 13951
Fix/Workaround:
None.
3 – Clock Failure detection for external OSC does not work in standby
mode.
Errata reference: 12688
Fix/Workaround:
Before entering standby mode, move the CPU clock to an internal RC,
disable external OSC and disable the Clock Failure detector. Upon CPU
wakeup, restart external OSC (if it does not start, the failure occurred during
standby), enable the Clock Failure detector and move the CPU clock to the
external OSC.
4 – In single shot mode and at 105°C, the ADC conversions have
linearity errors.
Errata reference: 13276
Fix/Workaround:
- Workaround 1: At 105°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
- Workaround 2: At 105°C, use the ADC in single shot mode only with
VDDANA > 2.7V.
5 – If APB clock is stopped and GCLK clock is running, APB read
access to read-synchronized registers will freeze the system. The CPU
and the DAP AHB-AP are stalled, as a consequence debug operation is
impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 – The SYSTICK calibration value is incorrect.
Errata reference: 14153
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not
be used to initialize the Systick RELOAD value register, which should be
initialized instead with a value depending on the main clock frequency and
on the tick period required by the application. For a detailed description of
the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
7 – In the table ""NVM User Row Mapping"", bits 40 & 41 default values
on silicon are not as specified in the datasheet. The datasheet defines
the default value as 0, it is 1 for both bits on silicon.
Errata reference: 13950
Fix/workaround:
None.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
679
8 – In I2C Slave mode, writing the CTRLB register when in the AMATCH
or DRDY interrupt service routines can cause the state machine to
reset.
Errata reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to
close out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to
its bit position instead of using CTRLB.CMD. The DRDY interrupt is
automatically cleared by reading/writing to the DATA register in smart mode.
If not in smart mode, DRDY should be cleared by writing a 1 to its bit
position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
680
9 – The voltage regulator in low power mode is not functional at
temperatures above 85C.
Errata reference: 12290
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep
mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
10 – After a clock failure detection (INTFLAG.CFD = 1), if INTFLAG.CFD
is cleared while the clock is still broken, the system is stuck.
Errata reference: 12687
Fix/Workaround:
After a clock failure detection, do not clear INTFLAG.CFD or perform a
system reset.
11 – In Standby, Idle1 and Idle2 sleep modes the device might not wake
up from sleep. An External Reset, Power on Reset or Watch Dog Reset
will start the device again.
Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with
20uA compared to numbers in the electrical characteristics chapter.
12 – Digital pin outputs from Timer/Counters, AC (Analog Comparator),
GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not
change value during standby sleep mode.
Errata reference: 12537
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep
mode in order to keep digital pin output enabled. This is done by setting the
RUNSTDBY bit in the VREG register.
13 – If the external XOSC32K is broken, neither the external pin RST
nor the GCLK software reset can reset the GCLK generators using
XOSC32K as source clock.
Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
36.1.4.2. DSU
1 – If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU
will be held in ""CPU Reset Extension"" after any upcoming reset
event.
Errata reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by
writing a one in the DSU STATUSA.CRSTEXT register or by applying an
external reset with SWCLK high or by power cycling the device.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
681
2 – The MBIST ""Pause-on-Error"" feature is not functional on this
device.
Errata reference: 14324
Fix/Workaround:
Do not use the ""Pause-on-Error"" feature.
36.1.4.3. PM
1 – In debug mode, if a watchdog reset occurs, the debug session is
lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
36.1.4.4. DFLL48M
1 – The DFLL clock must be requested before being configured
otherwise a write access to a DFLL register can freeze the device.
Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 – If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds
interrupt will be generated. These interrupts will be generated even if
the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts.
Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL
Interrupt Flag Status and Clear register (INTFLAG) are both set before
enabling the DFLLOOB interrupt.
36.1.4.5. XOSC32K
1 – The automatic amplitude control of the XOSC32K does not work.
Errata reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
36.1.4.6. EIC
1 – When the EIC is configured to generate an interrupt on a low level
or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled
(CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin
on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using
CTRLA ENABLE bit.
Errata reference: 15341
Fix/Workaround:
Clear the INTFLAG bit once the EIC enabled and before enabling the
interrupts.
36.1.4.7. NVMCTRL
1 – Default value of MANW in NVM.CTRLB is 0.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
682
This can lead to spurious writes to the NVM if a data write is done
through a pointer with a wrong address corresponding to NVM area.
Errata reference: 13134
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 – When external reset is active it causes a high leakage current on
VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
3 – When the part is secured and EEPROM emulation area configured
to none, the CRC32 is not executed on the entire flash area but up to
the on-chip flash size minus half a row.
Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash
size minus half row.
36.1.4.8. SERCOM
1 – In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters
debug mode. Instead, it is stopped when the current byte transaction is
completed and the corresponding interrupt is triggered if enabled.
Errata reference: 12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
36.1.4.9. TC
1 – Spurious TC overflow and Match/Capture events may occur.
Errata reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the
corresponding Interrupts instead.
36.1.4.10. PTC
1 – WCOMP interrupt flag is not stable. The WCOMP interrupt flag will
not always be set as described in the datasheet.
Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
36.1.5.
Die Revision E
36.1.5.1. Device
1 – In the table ""NVM User Row Mapping"", the WDT Window bitfield
default value on silicon is not as specified in the datasheet. The
datasheet defines the default value as 0x5, while it is 0xB on silicon.
Errata reference: 13951
Fix/Workaround:
None.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
683
2 – Clock Failure detection for external OSC does not work in standby
mode.
Errata reference: 12688
Fix/Workaround:
Before entering standby mode, move the CPU clock to an internal RC,
disable external OSC and disable the Clock Failure detector. Upon CPU
wakeup, restart external OSC (if it does not start, the failure occurred during
standby), enable the Clock Failure detector and move the CPU clock to the
external OSC.
3 – In single shot mode and at 105°C, the ADC conversions have
linearity errors.
Errata reference: 13276
Fix/Workaround:
- Workaround 1: At 105°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
- Workaround 2: At 105°C, use the ADC in single shot mode only with
VDDANA > 2.7V.
4 – If APB clock is stopped and GCLK clock is running, APB read
access to read-synchronized registers will freeze the system. The CPU
and the DAP AHB-AP are stalled, as a consequence debug operation is
impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
5 – The SYSTICK calibration value is incorrect.
Errata reference: 14153
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not
be used to initialize the Systick RELOAD value register, which should be
initialized instead with a value depending on the main clock frequency and
on the tick period required by the application. For a detailed description of
the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
6 – In the table ""NVM User Row Mapping"", bits 40 & 41 default values
on silicon are not as specified in the datasheet. The datasheet defines
the default value as 0, it is 1 for both bits on silicon.
Errata reference: 13950
Fix/workaround:
None.
7 – In I2C Slave mode, writing the CTRLB register when in the AMATCH
or DRDY interrupt service routines can cause the state machine to
reset.
Errata reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
684
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to
close out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to
its bit position instead of using CTRLB.CMD. The DRDY interrupt is
automatically cleared by reading/writing to the DATA register in smart mode.
If not in smart mode, DRDY should be cleared by writing a 1 to its bit
position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
8 – The voltage regulator in low power mode is not functional at
temperatures above 85C.
Errata reference: 12290
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep
mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
685
9 – After a clock failure detection (INTFLAG.CFD = 1), if INTFLAG.CFD
is cleared while the clock is still broken, the system is stuck.
Errata reference: 12687
Fix/Workaround:
After a clock failure detection, do not clear INTFLAG.CFD or perform a
system reset.
10 – If the external XOSC32K is broken, neither the external pin RST
nor the GCLK software reset can reset the GCLK generators using
XOSC32K as source clock.
Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
36.1.5.2. DSU
1 – The MBIST ""Pause-on-Error"" feature is not functional on this
device.
Errata reference: 14324
Fix/Workaround:
Do not use the ""Pause-on-Error"" feature.
36.1.5.3. DFLL48M
1 – The DFLL clock must be requested before being configured
otherwise a write access to a DFLL register can freeze the device.
Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 – If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds
interrupt will be generated. These interrupts will be generated even if
the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts.
Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL
Interrupt Flag Status and Clear register (INTFLAG) are both set before
enabling the DFLLOOB interrupt.
36.1.5.4. XOSC32K
1 – The automatic amplitude control of the XOSC32K does not work.
Errata reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
36.1.5.5. EIC
1 – When the EIC is configured to generate an interrupt on a low level
or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled
(CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
686
on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using
CTRLA ENABLE bit.
Errata reference: 15341
Fix/Workaround:
Clear the INTFLAG bit once the EIC enabled and before enabling the
interrupts.
36.1.5.6. NVMCTRL
1 – Default value of MANW in NVM.CTRLB is 0.
This can lead to spurious writes to the NVM if a data write is done
through a pointer with a wrong address corresponding to NVM area.
Errata reference: 13134
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 – When external reset is active it causes a high leakage current on
VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
36.1.5.7. SERCOM
1 – In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters
debug mode. Instead, it is stopped when the current byte transaction is
completed and the corresponding interrupt is triggered if enabled.
Errata reference: 12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
687
37.
Datasheet Revision History
The referring page numbers in this section are referred to this datasheet. The referring revision in this
section are referring to the datasheet revision.
37.1.
Rev. O - 08/2016
Description
Description: Updated CoreMark score from 2.14 to 2.46 CoreMark/MHz.
Block Diagram
Updated Block Diagram.
Power Manager
Updated description for bits [31:4] in APBBMASK.
System Control
Updated description in Drift Compensation.
Electrical
Characteristics
Brown-Out Detectors Characteristics: Updated Table 33-18.
Digital Frequency Locked Loop (DFLL48M) Characteristics: Note 2 in Table 33-40 updated
to only be applicable for die revision C.
Schematic
Checklist
Updated the content in section Unused or Unconnected Pins.
Power Supply Schematic: VDDCORE decoupling capacitor value updated from 100nF to 1nF.
Electrical
Characteristics at
85°C
Electrical
Characteristics at
105°C
•
Updated Absolute Maximum Ratings
– Vpin: min and max changed respectively from GND-0.3V to GND-0.6V and from
GND+0.3V to GND+0.6V
•
Added Injection Current
•
Updated Absolute Maximum Ratings
– Vpin: min and max changed respectively from GND-0.3V to GND-0.6V and from
GND+0.3V to GND+0.6V
•
•
–
Added Injection Current
BOD33: Updated Table 33-19.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
688
37.2.
Rev. N - 01/2015
Electrical
Characteristics
•
Updated Table 33-20 in the Analog-to-Digital (ADC) Characteristics
– added two rows. One for Internal ratiometric reference 0 error and the other for
Internal ratiometric reference 1 error
– added more details in Conditions of VREFINTVCC0 and VREFINTVCC1
Errata
•
•
Added Errata revision E
Updated Errata revision D:
– Added new Errata references: 12290; 13950 and 13951
– Updated Errata reference 13574: The software workaround: In I2C Slave mode,
writing the CTRLB register when in the AMATCH or DRDY interrupt service
routines can cause the state machine to reset
– Updated Errata reference 13276 Workaround 2: At 105ºC, use the ADC in single
shot mode only with VDDANA > 2.7V
Updated Errata revision C:
•
– Added new Errrata reference:13951
– Updated Errata reference 10537
Updated Errata revision B:
– Added new Errrata reference:13951
•
Appendix
37.3.
•
Added Appendix A: Electrical Characteristics at 105°C
Rev. M - 12/2014
Signal Description List
•
VREFP renamed VREFA and VREFB in the Signal Descriptions List
Memories
•
Added a table note to the Table 10-4
DSU - Device Service
Unit
•
Updated the Register Summary
– Added register bit AMOD[1:0]
Updated the register ADDR
– Added the description of “Bits 1:0 – AMOD[1:0]”
•
System Controller
•
•
Removed all references to 1khz from 32kHz External Crystal Oscillator
(XOSC32K) Operation, 32kHz Internal Oscillator (OSC32K) Operation and 32kHz
Ultra Low Power Internal Oscillator (OSCULP32K) Operation
Changed EN1K bits to “Reserved” in XOSC32K and in OSC32K
PORT
•
Updated I/O Pin Configuration
– Removed reference to Open-drain
ADC - Analog-toDigital Converte
•
Replaced AREFA/AREFB by VREFA/VREFB in Analog Connections
DAC - Digital -toAnalog Converter
•
Replaced VREFP by VREFA in Digital to Analog Conversion and in DAC as an
Internal Reference
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
689
Electrical
Characteristics
•
•
•
•
Brown-Out Detectors Characteristics:
– Added Figure 33-3, Figure 33-4 and clarifications.
– Updated conditions in the Table 33-18 and in the Table 33-19.
Analog-to-Digital (ADC) Characteristics:
– Updated conditions in the Table 33-23 and in the Table 33-24.
Updated the table Table 33-40 in Digital Frequency Locked Loop (DFLL48M)
Characteristics:
– Renamed “Power consumption on VDDANA” to “Power consumption on VDDIN”
– Added IDFLL specific typical value for revD and later
Updated the table Table 33-45 in SERCOM in SPI Mode Timing:
– The value of tSCK SCK period updated from 42 to 84
Package Information
•
Updated Thermal Considerations:
– Added ThetaJA and ThetaJC values for the packages: 64-ball UFBGA and 45ball WLCSP
Schematic Checklist
•
•
•
Updated the Introduction Content
Replaced AREFA/AREFB by VREFA/VREFB in the content
Updated the content in theProgramming and Debug Ports
– Updated all sub-sections, tables and figures
Errata
•
Updated Errata revision D:
– Added Errata reference 13574 related to CTRLB register / I2C in Slave Mode.
37.4.
Rev. L - 09/2014
Features
•
•
Added UFBGA64 and WLCSP45 packages
Introduced the 105ºC devices
Pinout
•
Added two more pinouts: UFBGA64 and WLCSP45
Configuration
Summary
•
UpdatedConfiguration Summary to include UFBGA64 and WLCSP45 packages
Ordering Information
•
Updated Ordering Information to include UFBGA64, WLCSP45 packages and the
ordering codes for 105ºC devices
Peripheral
Configuration
•
Updated Peripherals Configuration Summary
– Added one column “SleepWalking” in the Table 12-1
PM – Power Manager
•
Updated the table note 1 of the Table 16-3
System Controller
•
Updated Interrupts
– Interrupt source “BOD33DET - BOD33 Detection” is an Asynchronous
interrupt that can be used to wake-up the device from any sleep mode
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
690
Watchdog Timer
•
•
Updated Always-On Mode
– Added conditions for which CTRL.ALWAYSON bit must never be set to one by
software
Updated Interrupts
– Early Warning (EW) is an asynchronous interrupt that can be used to wake-up
the device from any sleep mode
RTC – Real-Time
Counter
•
Updated the section Interrupts
– Overflow (INTFLAG.OVF), Compare n (INTFLAG.CMPn), Alarm 0
(INTFLAG.ALARMn) and Synchronization Ready (INTFLAG.SYNCRDY) are
all asynchronous and can be used to wake-up the device from any sleep
mode
EIC – External
Interrupt Controller
•
Updated the section Interrupts
– External interrupt pins (EXTINTx) and Non-maskable interrupt pin (NMI) are
both asynchronous and can be used to wake-up the device from any sleep
mode
PORT - I/O Pin
Controller
•
Updated the Basic Operation section
– Instances “pad” changed to “pin”
– Edited the content in the section
EVSYS – Event
System
•
Updated the section Interrupts
– Overrun Channel x (OVRx) and Event Detected Channel x (EVDx) are
asynchronous and can be used to wake-up the device from any sleep mode
Updated the section Sleep Mode Operations
•
SERCOM USART
•
Updated the section Interrupts
– RXS, RXC, TXC and DRE interrupts are asynchronous and can be used to
wake-up the device from any sleep mode.
ADC – Analog-toDigital Converter
•
•
Fix a typo in the description of the bitfield MUXPOS of the register INPUTCTRL
Added more info to the table “Delay Gain” and about the propagation delay in subsection 7.3 “Prescaler”
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
691
Electrical
Characteristics
•
Updated the Maximum Clock Frequencies
– Added the Table 32-6
– Renamed the Table 32-7 to "Maximum Peripheral Clock Frequencies" and
updated the whole table content including the symbols and descriptions
Added the section Peripheral Power Consumption
Updated the section I/O Pin Characteristics
– Updated the table Table 32-11
For tRISE and tFALL added different load conditions depending on DVRSTR
value
•
•
•
Updated SERCOM in SPI Mode Timing
– Added typical tSCK in the table Table 32-44
Updated Voltage Regulator Characteristics
– Added minimum value to the Cout parameter in the Table 32-15
Updated Digital Frequency Locked Loop (DFLL48M) Characteristics
– Renamed the Table 32-39 to DFLL48M Characteristics - Closed Loop Mode
– Updated the content and the table note of the Table 32-39
Updated the Analog-to-Digital (ADC) Characteristics
– Table 32-19. Operating Conditions
Updated Single rate (single shot) maximum value to 300 ksps
•
•
•
Updated the table note 3
– Updated Table 32-20 and Table 32-21:
Added definition of the gain accuracy parameter
Updated Temperature Sensor Characteristics
– Updated the table Table 32-29. Temperature Sensor Characteristics
Added temperature sensor accuracy parameters and its condition
•
Schematic Checklist
•
Added link for the values of XIN32/XOUT32 pins parasitic capacitance in the Table
32-38. 32kHz Crystal Oscillator Characteristics
Package Information
•
Added two more packages: 64UFBGA and 45WLCSP
Errata
•
Updated errata for revision B, C and D. Added errata references: 10805, 12015,
12499, 13140, 13140 and 13268
37.5.
Rev. K – 05/2014
Description
•
Updated the content in the Description
Block Diagram
•
VREFP on DAC renamed VREFA
Memories
•
Updated the tableNVM User Row Mapping
– Changed the WDT window default value, WINDOW_1 to 0x5
DSU - Device Service
Unit
•
Updated DSU Chip Identification Method:
– “Family” renamed “Product family” and subfamily became “Product series”
Updated the protection state of the device in Starting CRC32 Calculation
•
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
692
SYSCTRL - System
Controller
•
•
•
•
•
•
Updated 8MHz Internal Oscillator (OSC8M) Operation
– Updated the description of writing to FRANGE and CALIB
Updated the table Behavior of the Oscillators
– DFLL renamed DFLL48M
Added Note on how to enter standby mode in:
– External Multipurpose Crystal Oscillator (XOSC) Operation
– 32kHz External Crystal Oscillator (XOSC32K) Operation
Added VREG register
– Added VREG register in Register Summary
– Updated the description of Bit 6 – RUNSTDBY and Bit 13 – FORCELDO
Updated the description of Interrupts
Updated OSC8M
– Bits 11:0 - CALIB has two calibration fields CALIB[11-6] and CALIB[5:0]
RTC - Real-Time
Counter
•
Updated Analog Connections
– TOSC1 and TOSC2 renamed respectively XIN32 and XOUT32
PORT
•
Updated Principle of Operation
– The reference for Pin Configuration registers changed to PINCFGy
SERCOM SPI
•
Updated CTRLB register
– Bit 17 - RXEN is R/W
TC - Timer/Counter
•
•
Updated the table Waveform Generation Operation
Updated CTRLC register
– Bits 1:0 - INVENx: Waveform Output x Invert Enable
AC - Analog
Comparators
•
Added Bit 7 - LPMUX in CTRLA register and updated Register Summary
DAC - Digital -toAnalog Converter
•
•
Added a new DAC in the Block Diagram with VREFP replaced by VREFA
Updated Signal Description
– VREFP renamed VREFA
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
693
Electrical
Characteristics
•
•
•
•
Updated the table Absolute maximum ratings
– Updated IVDD and IGND max values
– Added a detailed table note for IVDD and IGND
Added the table GPIO Clusters
Updated the table General operating conditions
– Removed table note (1) related to the operating conditions
Updated the table Current Consumption
– Updated values in ACTIVE and IDLE0/1/2 modes
–
•
•
•
•
•
•
•
•
•
•
•
ERRATA
•
•
•
Updated the max values @ 85ºC in STANDBY modes
l Max values updated to 100μA both for RTC stopped and RTC running
Updated I/O Pin Characteristics section
– Updated title of the table to RevD and later normal I/O Pins Characteristics
– Updated IOL and IOH values in the table RevD and later normal I/O Pins
Characteristics
– Updated IOL and IOH in the table I2C Pins Characteristics in I2C configuration
Table note (1) on COUT removed from the table Decoupling requirements
Updated the content in Analog Characteristics
– Updated max value of VPOT-in the table POR Characteristics. New max value
is 1.32V
– Updated table note 3 in Differential Mode
– Updated table note 2 in Single-Ended Mode
– Updated RSAMPLE in the table Operating Conditions
Added conversion rate for max 1000ksps in the table Clock and Timing
Updated the table Accuracy Characteristics
– Added table note “All values measured using a conversion rate of 350ksps”
Updated Software-based Refinement of the Actual Temperature
– Added the address of the temperature log row
Updated the table DFLL48M Characteristics - Closed Loop Mode
– Removed the Tlcoarse parameter as it is already set from calibration
– Updated IDFLL and tSTARTU typical values
Updated Crystal Oscillator Characteristics section:
– Updated the max values of ESR
– Updated the typical values of CXIN and CXOUT
Updated the table 32kHz Crystal Oscillator Characteristics:
– Updated the table note
Updated the max value of ESR to 141kΩ, the typical values of CXIN32 and CXOUT32
to respectively 3.1 and 3.3pF
Updated the table I2C Interface Timing
– Added table note (3) to tR and tOF
Added Errata Revision D
Updated Errata Revision C
Updated Errata Revision B
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
694
37.6.
Rev. J – 12/2013
NVMCTRL - Non-Volatile Memory Controller
37.7.
Updated the NVM NVMCTRL.CTRLB register.
Rev. I 12/2013
General
Removed Preliminary
Description
•
Updated the description
Features
•
Power Consumption has been updated to Down to 8μA running the Peripheral Touch
Controller
Configuration
Summary
Updated the Configuration Summary
Ordering
Information
Updated Ordering Information
•
Added AT prefix at the start of the ordering codes
Block Diagram
•
•
Added the description of the connection between PORT and ARM CORTEX-M0+
CPU: ARM SINGLE CYCLE IOBUS
Renamed GENERIC CLOCK to GENERIC CLOCK CONTROLLER
I/O Multiplexing
and
Considerations
Updated the Table 5-1. PORT Function Multiplexing
•
Renamed all GCLK/IO[x] to GCLK_IO[x]
•
Updated the description of the Serial Wire Debug Interface Pinout section
•
Added SWDIO to PA31 column G in the Table 5-1 and added a footnote
Product Mapping
Changed Peripheral to AHB-APB
Signal Description
•
•
Removed GCLK from the heading “Generic Clock Generator”
Renamed IO[7:0] to GCLK_IO[7:0]
Memories
•
•
•
•
Added a new section Serial Number
Software Calibration Row changed to Software Calibration Area
Added Figure 9-1. Calibration and Auxiliary space
Updated the Table 9-4. NVM Software Calibration Area Mapping
– Added the BOD33 and BOD12 default settings
– Added DFLL48M COARSE CAL and DFLL48M FINE CAL
– Added table notes on rev C (Bit 40 and Bit 41) to the Table 9-3. NVM User Row
Mapping
DSU - Device
Service Unit
•
Updated the Table 12-7. Register Summary
– Redefined DID register. FAMILY changed from 4 bits to 5 bits and SERIES from
8 bits to 6 bits
Updated the Device Identification- DID register
– Updated Family and Series bit registers
– Updated the Table 12-8. Device Selection. Added ATSAMD20E18A device at
0xA.
•
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
695
Clock System
•
•
•
•
•
Generic Clock
Controller
Updated the clock names in the Figure 13-1. Clock distribution
Updated the description of Generic Clock generators and Generic Clocks in the Clock
Distribution
Updated the Figure 13-2. Example of SERCOM clock
– Synchronous Clock Controller renamed to Main clock controller
Updated the descriptive content of the Read-Synchronization section
Changed the title “Enable Write-Synchronization” to Write-Synchronization of
CTRL.ENABLE
•
Updated the content in Clocks after Resetsection
– Renamed GCLKMAIN to GCLK_MAIN
•
Updated the Overview section and renamed GCLK_PERIPH to GCLK_PERIPHERAL
throughout the datasheet
Updated the Features list
Updated Figure 14-1. Device Clocking Diagram and added a figure note
Updated links in the sections: Power Manageme and in Clocks
Updated the content in the Functional Description
– Added links in the section Initialization for GENDIV, GENCTRL and CLKCTRL
– Updated the Figure 14-3. Generic Clock Generator
•
•
•
•
–
•
•
•
Renamed “External Clock” to Generic Clock Output on I/O Pins and updated the
description
– Updated the Figure 14-4. Generic Clock Multiplexer
– Updated the descriptive content in the Disabling a Generic Clock” section
– Updated the Figure 14-5. GCLK Indirect Access. GCLK becomes Generic Clock
– Updated links in the sections: Run in Standby Mode and Synchronization
Added a table note on the Reset of GENCTRL register
Added a third column “Generator Clock Source” in the tableGENCTRL Reset Value
after a Power Reset
Updated the content and replaced the text “if the generator is not used by the RTC” by
the “if the generator is not used by the RTC and not a source of a 'locked' generic
clock” in two tables:GENCTRL Reset Value after a User Reset and GENDIV Reset
Value after a User Reset
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
696
Power Manager
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated the content Overview
– “power save modes” is changed to “sleep modes”
– A new line is added: “This is because during STANDBY sleep mode the internal
voltage regulator will be in low power mode”
Updated Featureslist
– Clock control: “Generates” is changed to “Controls”
Updated le content in the Clockssection
– “This clock” is changed to “The clock source for GCLK_MAIN”
Updated the content in Interrupts section
– Added: “Refer to Nested Vector Interrupt Controller"
Updated Register Access Protection
– Added: “Refer to Interrupt Flag Status and Clear - INTFLAG register for details”
– Added: “Refer to Reset Cause - RCAUSE register for details”
Updated the sections: Synchronous Clocks and Sleep Mode Controller
– Added: "see Table 15-4. Sleep Mode Overview"
Updated Reset Controller section
– “resets” corrected to “reset”
Updated Initialization section
– Added: “- refer to Reset Cause - RCAUSE register for details”
Updated Selecting the Synchronous Clock Division Ratio
– Added: “(APBxSEL.APBxDIV)”
Updated the figure Synchronous Clock Selection and Prescaler
Updated Clock Ready Flag section
– “CKSEL” is changed to “CPUSEL”
Updated the Peripheral Clock Masking section
– Added: “refer to APBA Mask - APBAMASK register for details”
– The first sentence below the figure has been changed to: “When the APB clock
for a module is not provided its registers cannot be read or written.”
Updated the content Clock Failure Detector section
– “CFDEN.CTRL” has been changed to “CTRL.CFDEN”
– Added: “Refer to Control - CTRL register for details”
– “divided” has been changed to “undivided”
– “is generated, if enabled” has been changed to "is set and the corresponding
interrupt request will be generated if enabled"
– “GCLKMAIN” has been changed to “GCLK_MAIN”
– Added: Note 3
Updated the table Effects of the Different Reset Events
– “GCLK” has been changed to “Generic Clock”
Updated the figure Reset Controller
Updated the table Sleep Mode Entry and Exit
– Two notes (“Synchronous” and “Asynchronous”) are added below the table
Updated the Sleep Mode Controller section
– Updated the text in STANDBY mode
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
697
Power Manager
(cont.)
•
•
•
•
•
Updated the table Sleep Mode Overview
– Replaced the table with an accurate one
Updated IDLE Mode section
– Second bullet: “any non-masked interrupt” changed to “the occurrence of any
interrupt that is not masked in the NVIC Controller”
Updated STANDBY Mode section
– “GCLK” is changed to “Generic Clock”
Added: SleepWalking section
Updated Bit 4 – BKUPCLK: Backup Clock Select”
– “GCLKMAIN” is changed to “GCLK_MAIN”
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
698
SYSCTRL –
System Controller
•
Updated the content in Overview section
– “XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, BOD33,
BOD12, VREG and VREF” is changed to “clock sources, brown out detectors,
on-chip voltage regulator and voltage reference of the device."
– Added: “ refer to Power and Clocks Status - PCLKSR register"
– Added: “(INTENSET)”
– Added: “(INTENCLR)”
– Added: “(INTFLAG)”
•
Updated the content in Principle of Operationsection
– Added two tables for the behavior of Oscillators and Sleep modes
Updated Register Access Protection
– Added: “- refer to INFLAG
Updated Analog Connections section
– Changed “load. Refer” to “load, refer”
Updated External Multipurpose Crystal Oscillator (XOSC) Operation section
– Changed “the only” to “only the”
– “the XTAL Enable bit (XOSC.XTALEN) must written to one” is changed to “a one
must be written to the XTAL Enable bit (XOSC.XTALEN)."
Updated the content in 32kHz External Crystal Oscillator (XOSC32K) Operation
section
– “power-on, reset” is changed to “power-on reset (POR)”
– Added: "XOSC32K can provide two clock outputs when connected to a crystal.”
Updated the content in 8MHz Internal Oscillator (OSC8M) Operation section
Updated the content in 32kHz Internal Oscillator (OSC32K) Operation section
– Changed “CALIB” to “OSC32K.CALIB”
– Changed “non-volatile memory” to “NVM Software Calibration ROW”
– Added: “(refer to NVM Software Calibration Area Mapping
Updated the content in 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
Operation section
– Added: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control OSCULP32K register
Updated the content in Closed-Loop Operation section
– List #3: Changed “device” to “DFLL”
– Below “Drift Compensation”: “set” has been replaced by “triggered”
– The text “shown in the SYSCTRL Block Diagram" has been removed
•
•
•
•
•
•
•
•
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
699
SYSCTRL System Control
(cont.)
•
•
•
•
•
•
•
•
•
•
•
•
WDT – Watchdog
Timer
•
•
•
•
Updated Additional Features
– The text “when disabling the DFLL48M” below “Wake from Sleep Modes” has
been replaced by the text “when the DFLL is turned off”
Updated 3.3V Brown-Out Detector (BOD33) section
– “Brown-Out Detector” is replaced by “BOD33”
Updated 32kHz Internal Oscillator (OSC32K) Control - OSC32K register
– The reference for Bits 22:16 - CALIB[6:0] has been corrected
Updated the table Start-UpTime for External Multipurpose Crystal Oscillator
– Both notes for this table has been updated/changed
– New “Note 3” is added
Updated the table Start-Up Time for 32kHz External Crystal Oscillator
– Both notes for this table has been updated/changed
– New “Note 3” is added
Updated the table Start-Up Time for 32kHz Internal Oscillator
– New column for “Number of OSC32K Clock Cycles” is added
– The values in the column for the “old” “Number of OSC32K Clock Cycles” has
been corrected
– Both notes for this table has been updated/changed
– New “Note 3” is added
Updated DFLL48M Control - DFLLCTRL register
– For “Property” the following has been added: “, Write-Synchronized”
– Removed RUNSTDBY
Updated DFLL48M Value - DFLLVAL register
– For “Property” the following has been added: “, Read-Synchronized”
Updated Register Access Protection register
– In the bullet point the following is added: “ refer to Interrupt Flag Status and Clear
- INTFLAG register”
Updated Principle of Operation section
– Added: “- refer to Control - CTRL register "and “- refer to Interrupt Enable Clear INTENCLR register”
Updated the Default Reset value in 8MHz Internal Oscillator (OSC8M) Control OSC8M register and fixed the RANGE bitfield
Updated the description of the Bit 4 DFLL Ready in Power and Clocks Status PCLKSR register and updated Bit 11 BOD33 Synchronization Ready
Updated Intitialization
– Added: “- refer to CTRL register”, “- refer to CONFIG register”, and “- refer to
EWCTRL regsiter”
Updated Normal Mode
– Added: “- refer to Clear - CLEAR register
Updated the description of the Bit 2 (CTRL.WEN) in the Control - CTRL register
Removed “Asynchronous Watchdog Clock Characterization”
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
700
SERCOM SPI –
SERCOM Serial
Peripheral
Interface
•
Updated the description of the SPI Transfer Modes section
RTC - Real-Time
Counter
•
Updated Register Access Protection section
– Added: “- refer to INTFLAG register”, “- refer to READREQ register”, “- refer to
STATUS register”, and “- refer to DBGCTRL register”
Updated the content in Initialization section
– Added: “- refer to Event Control - EVCTRL register”
•
EIC - External
Interrupt Controller
•
•
•
•
NVMCTRL - NonVolatile Memory
Controller
•
•
•
•
•
•
•
•
PORT
•
•
Updated the content in Events section
– Added text “External Interrupt Controller generates events as pulses”
Updated the content Sleep Mode Operation section
– Added text “Using WAKEUPEN[x]=1 with INTENSET=0 is not recommended”
Updated the content Register Access Protection
– Added: “- refer to INTFLAG register” and “- refer to NMIFLAG register”
Updated Additional Features
– Added: “- refer to NMICTRL register”
Updated Power Management section
– Added: “- refer to CTRLB register”
Added Basic Operations section
Updated Interrupts section
– Added a reference link to Nested Vector Interrupt Controller
Updated the description of NVM Read section
Updated the content in Register Access Protection section
Added: “- refer to INTFLAG regsiter” and “- refer to STATUS register”
Updated the description of MANW bit in CTRLB register
Updated the description of ERROR and READY bits in INTENCLR register
Updated CPU Local Bus section
– Added: “- refer to DIR register”, “- refer to OUT register”, “- refer to IN register",
and “- refer to CTRL register”
Updated Principle of Operation section
– Added: “- refer to DIR register”, “- refer to OUT register”, “- refer to PINCFG0
register”, “- refer to IN register”, and “- refer to PMUX0 register”
TC
•
Updated the table Waveform Generation Operation. Switched “Clear” and “Set” for
CCO value (MPWM).
ADC
•
Updated the content in Sleep Mode Operation section
– Added “While the CPU is sleeping, ADC conversion can only be triggered by
vents”
Software Calibration Row changed to Software Calibration Area
•
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
701
AC
•
Updated the content in Sleep Mode Operation section
– Added “While the CPU is sleeping, single-shot comparisons are only triggerable
by events”
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
702
Electrical
Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Package
•
•
Updated Disclaimer section. Removed the preliminary disclaimer
Updated the table Absolute maximum ratings
– Updated IVDD and IGND max values
– Added TSTORAGE
Updated the table General operating conditions
– Added VDDIO - VDDANA
Updated the table Current Consumption
– Added min and max values
– Added consumption data
Updated IOL and IOH in the table RevD and later normal I/O Pins Characteristics
Updated VHYS min value in I2C Pins Characteristics in I2C configuration
Duplicated all tables in the table I/O Pin Characteristics” to differentiate rev D (the table
RevD and later normal I/O Pins Characteristics) from rev C (the table RevC and later
normal I/O Pins Characteristics)
Updated the table and renamed to Voltage Regulator Electrical Characteristics
– Added condition to VDDCORE characteristics
Updated the table BOD33 LEVEL Value
– Added a table note to specify BOD33.LEVEL default production settings
Updated the table BOD33 Characteristics
– Added current consumption data (IBOD33)
ADC Characteristics: Removed the min value of IDD from the table Operating
Conditions
Updated the Bandgap Gain Error min and max values in the table Differential Mode
DAC characteristics: Updated IDD values and conditions in the table Operating
Conditions
Removed the table note from the table Bandgap (Internal 1.1V reference)
characteristics
Updated the Accuracy unit in the table Accuracy Characteristics
Removed tFFP from the tableNVM Characteristics
Updated the table Temperature Sensor Characteristics
Updated the content in Crystal Oscillator (SOSC) Characteristics section
– Added new characterization data
– Removed fCPXIN min value from Digital Clock Characteristics table
Changed the title to Digital Frequency Locked Loop (DFLL48M) Characteristics and
added table note to DFLL48M Characteristics - Closed Loop Mode
Updated the table 32kHz Crystal Oscillator Characteristics
– Updated IXOSC32K
– Added a table note for “AGC on”: data are not yet available for rev D
Added current consumption data (IOSC32K) in the table 32kHz RC Oscillator
Characteristics
Updated IOSC8M in the table Internal 8MHz RC Oscillator Characteristics
Added notes to 64QFN, 48QFN and to 32QFN packages
Updated Device and Package Maximum Weight for 32-pin TQFP and for 32-pin QFN
– Device and Package Maximum Weight is 100mg for TQFP32 and 90mg for
QFN32
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
703
37.8.
Rev. H 10/2013
Configuration
Summary
Added 256KB Flash and 32KB SRAM to the SAM D20E
Ordering
Information
Added ATSAMD20E18 ordering code
SYSCTRL
Added note to INFLAG register
NVMCTRL
Updated links to the Flash size for EEPROM emulation table
SERCOM USART
Updated the table Transmit Data Pinout. SERCOM PAD[X] renamed PAD[X]
ADC
•
•
•
Updated the Features list. Added "Up to 350,000 samples per second (350ksps)"
Updated the broken link for INPUTCTRL register
Removed “Additional Features”
Schematic
Checklist
•
•
•
Added information about JTAGICE3 compatible SWD connector
Updated connector names to match the names used by ARM
Added information about general debugging and programming to Programming and
Debug Ports
Electrical
Characteristics
•
•
•
•
Updated the table General operating conditions. Added table note related to BOD33
Updated I/O Pin Characteristics. All VDDANA ranges are 1.62V - 2.7V and 2.7V - 3.63V
Updated Digital Frequency Locked Loop (DFLL48M) Characteristics
Updated the table Supply Rise Rates
– Replaced the Maximum value that was based on simulation by the actual
measurement value
– Removed the unused columns
Updated the typical values of while(1) at 1.8V in the table Current Consumption
•
•
•
•
Updated the table Decoupling requirements
– Used measurement values
– Removed the min and max values
– Added values for CIN and COUT
– Added a table note
Updated the table ADC: Operating Conditions
– Added min and max values for IDD
– Updated typical values
Updated the table Single-Ended Mode
– Added min and max values
– Added characteristics for ENOB, SFDR, SINAD and THD
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
704
Electrical
Characteristics
•
•
•
•
•
•
•
•
•
ERRATA
37.9.
Replaced VDD by VDDANA in the table Clock and Timing
Updated the table Electrical and Timing
– Added min and max values
– Added characterization data for VSCALE
Updated the tables: Differential Mode, Accuracy Characteristics and Temperature
Sensor Characteristics
– Added min and max values
Updated the tableFlash Endurance and Data Retention and EEPROM Emulation
Endurance and Data Retention . Added table note related to the cycling endurance
Added output frequency characteristics data to the tables: 32kHz RC Oscillator
Characteristics, Ultra Low Power Internal 32kHz RC Oscillator Characteristics and
Internal 8MHz RC Oscillator Characteristics
Updated all tables in I/O Pin Characteristics section. Added new characterization data
Added VDDCORE characteristics to the Voltage Regulator Electrical Characteristics
Updated the tables: POR Characteristics, Bandgap (Internal 1.1V reference)
characteristics, BOD33 LEVEL Value and BOD33 Characteristics. Added new
characterization data
Updated all tables in Oscillators Characteristics section. Added new characterization
data
Added Errata Revision C
Rev. G 10/2013
Features
Added the Power Consumption
GCLK
Updated Division Factor
•
Generic clock generator 0 has 8 division factor bits - DIV[7:0]
NVMCTRL
Updated the table Flash size for EEPROM emulation
Electrical
characteristics
•
Updated the table Current Consumption. Added values of CPU running a “While(1)”
algorithm
•
Moved the PTC typical figures from the Typical characteristics into the Electrical
Characteristics
Updated the Analog Characteristics Cout max value in the Decoupling requirements
table is 1000nF instead of 200nF
Updated the NVM Characteristics:
– Added note about the max number of consecutive write in a row before an erase
becomes mandatory
– Removed all “based on simulation” notes
– Updated the tables: Maximum Operating Frequency, Flash Endurance and Data
Retention and EEPROM Emulation Endurance and Data Retention
•
•
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
705
37.10. Rev. F 10/2013
I/O Multiplexing and
Considerations
Updated the table PORT Function Multiplexing
•
PA16 and PA17 are I2C pins in SERCOM1
Memories
Updated the table NVM Software Calibration Area Mapping
•
Bit Positions [14:3] and [26:15] are “Reserved”
ADC
Updated the Calibration according to the update done in the NVM Software
Calibration Area Mapping
Typical Characteristics
Added the PTC in the Typical Characteristics
ERRATA
Added PTC in Errata Revision B
37.11. Rev. E 09/2013
Ordering
Information
Updated the figure of the Ordering Information
•
Removed “H = -40 - 85C NiPdAu Plating” from the Package Grade
•
Renamed “Product Variant” to “Device variant” in the figure of the Ordering Information
DSU
Updated the DID register
•
Renamed SUBFAMILY [7:0] bits to SERIES [7:0] bits
•
The whole description of the DID bit registers updated
•
Added Device (all products in the SAM D20 family) column in Device Selection table
(DEVSEL)
SYSCTRL
Added ENABLE bits for the BODs and oscillators
Electrical
characteristics
Updated Supply Characteristics
•
Updated the table Supply Rise Rates
Updated the I/O Pin Characteristics
•
Fixed typos in the tables RevD and later normal I/O Pins Characteristics, SAMD20
revC/revB Normal I/O Pins Characteristics and I2C Pins Characteristics in I2C
configuration: “Vdd” was missing in some cells of the tables.
37.12. Rev. D 08/2013
Description
The content updated
General
Fixed different typos throughout the datasheet and applied correctly the template
Block Diagram
DSU
Clock System
•
Added 2KB RAM and 16KB FLASH
Updated the Block Diagram
•
Removed HRAM from the block diagram
•
•
The description of the Basic Read Request has been updated
Updated the figure Synchronization
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
706
SYSCTRL
NVMCTRL
PORT
EVSYS
•
•
Updated the writing of the interrupt sources in the Interrupts section
Added the reference to INFLAG register
Updated the figure Row Organization
•
Removed the blue mark from the figure
•
•
IOBUS address 0x60000000 added in CPU Local Bus section
Removed RWM from the description
Updated the CHANNEL register:
•
Bits 25:24: CHANNEL:PATH description updated.
Schematic Checklist
•
•
•
Updated the Introduction content
Replaced all TDB by their respective values
Corrected the typo: the Ohm symbol in External Reset Circuit
Electrical Characteristics
•
•
Removed the colors from Electrical Characteristics
Added footnote in the table Operating Conditions, fADC = 6 * CLKADC
Table Of Contents
•
Applied correctly the template for the TOC
37.13. Rev. C – 07/2013
Description
Updated the front page:
•
Removed the “Embedded Flash” from the title and from the description on
the page 1
•
Replaced “speeds” by “frequencies” on the page 1
•
Added a sub-bullet on PTC in feature list (256-Channel capacitive touch and
proximity sensing) on the page 2
•
Replaced IO lines by IO pins on the page 2
Configuration Summary
Updated the table
•
The RTC
•
I/O lines changed to I/O pins
•
Changed 32.768kHz high-accuracy oscillator to 32.768kHz oscillator
•
Changed 32.768kHz ultra-low power internal oscillator to 32kHz ULP
oscillator
•
Changed 8MHz internal oscillator to 8MHz high-accuracy internal oscillator
•
Updated SW Debug Interface
•
Updated the WDT
Ordering information
•
•
Replaced “base line” by “general purpose”
Centered the tables except the ordering code table.
About the Document
•
•
•
Renamed the chapter to Appendix A and Appendix B
Moved the two Appendixes at the end of the datasheet
Changed the tag of the tables to the tag of appendix tables
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
707
Pinout
•
•
•
•
Updated the description of “Multiplexing Signals”
Replaced “PORT controller” by “PORT”
Set the table PORT Function Multiplexing as a continuing table and updated
the table notes
Replaced I/O lines by I/O pins
Signal Description
•
Removed the column “Comment” from the table
Power Supply
•
•
•
Removed “nominal” from power supplies
Updated the description of vector regulator
Added link to the “Schematic Checklist”
Clock System
Added the link in the description of Write-Synchronization
Power Manager
Updated the table Sleep Mode Overview:
•
The column “Clock Sources” has been updated with new commands
•
The table note 2 replaced by a reference to On-demand, Clock Requests
ADC
Updated the content in Interrupt Flag Status and Clear - INFLAG register:
•
Bit 2: INTFLAG.WINMON description updated
•
Bit 1: INTFLAG.OVERRUN description updated
•
Bit 0: INTFLAG.RESRDY description updated
DAC
•
•
•
Register Summary: DATA and DATABUF register bit fields updated.
DATA register: Bit fields and description updated.
DATABUF register: Bit fields and description updated.
Electrical
CharacteristicsElectrical
Chara
Added Electrical Characteristicsat 85ºC
Package Information
Corrected the 64 pins QFN drawing
37.14. Rev. B – 07/2013
Block Diagram
Added output from Analog Comparator block
Signal
Description
Updated the content in Signal Description table
Memories
Added OSC32K Calibration (bit position 44:38) in the table NVM Software Calibration Area
Mapping
DSU
Updated the content in Die Identification - DID register:
•
Bit 15:12: Added DIE[3:0] bit group
•
Bit 11:8: Added REVISION[3:0] bit group
EVSYS
Updated Features: Number of event generators updated from 59 to 58
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
708
SERCOM SPI
Updated Control A - CTRLA register:
•
Bit 16: CTRLA.DOPO updated to Bit17:16: CTRLA.DOPO[1:0]
•
Bit 17:16 - DOPO[1:0] description updated
Updated Status - STATUSregister:
•
Bit 2 - STATUS.BUFOVF description updated
ADC
Added Accumulation section
Updated Averaging section
Updated Oversampling and Decimation section
AC
Heading updated from Basic Operation to Starting a Comparison.
Updated the list of write-synchronized bits and registers in Synchronization section
Register property updated to “Write-Synchronized” in registers:
SYSCTRL
Errata Rev. B
•
Control A - CTRLA and Comparator Control n - COMPCTRLn
•
•
Removed VDDMON and ENABLE bits from registers.
Updated start-up time tables for XOSC32K and OSC32K:
– XOSC register: Table Start-UpTime for External Multipurpose Crystal Oscillator
– XOSC32K register: Table Start-Up Time for 32kHz External Crystal Oscillator
– OSC32K register: TableStart-Up Time for 32kHz Internal Oscillator
Errata Revision B updates:
•
Device: Two errata added (10988 and 10537)
•
PM: Two errata added (10858 and 11012)
•
XOSC32K: One errata added (10933)
•
DFLL48M: Two errata added (10634, 10537), one errata updated (10669)
•
EVSYS: One errata added (10895)
•
SERCOM: Two errata added (10812 and 10563), one errata removed (10563)
•
ADC: One errata updated (10530)
•
Errata Rev. A
Flash: One errata updated (10804)
Status changed to “Not Sampled”
37.15. Rev. A 06/2013
1.
Initial revision
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
709
38.
Conventions
38.1.
Numerical Notation
Table 38-1. Numerical Notation
38.2.
Symbol
Description
165
Decimal number
0b0101
Binary number (example 0b0101 = 5 decimal)
'0101'
Binary numbers are given without prefix if
unambiguous.
0x3B24
Hexadecimal number
X
Represents an unknown or don't care value
Z
Represents a high-impedance (floating) state for
either a signal or a bus
Memory Size and Type
Table 38-2. Memory Size and Bit Rate
38.3.
Symbol
Description
KB (kbyte)
kilobyte (210 = 1024)
MB (Mbyte)
megabyte (220 = 1024*1024)
GB (Gbyte)
gigabyte (230 = 1024*1024*1024)
b
bit (binary '0' or '1')
B
byte (8 bits)
1kbit/s
1,000 bit/s rate (not 1,024 bit/s)
1Mbit/s
1,000,000 bit/s rate
1Gbit/s
1,000,000,000 bit/s rate
word
32 bit
half-word
16 bit
Frequency and Time
Symbol
Description
kHz
1kHz = 103Hz = 1,000Hz
KHz
1KHz = 1,024Hz, 32KHz = 32,768Hz
MHz
106 = 1,000,000Hz
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
710
38.4.
Symbol
Description
GHz
109 = 1,000,000,000Hz
s
second
ms
millisecond
µs
microsecond
ns
nanosecond
Registers and Bits
Table 38-3. Register and Bit Mnemonics
Symbol
Description
R/W
Read/Write accessible register bit. The user can read from and write to this bit.
R
Read-only accessible register bit. The user can only read this bit. Writes will be
ignored.
W
Write-only accessible register bit. The user can only write this bit. Reading this bit will
return an undefined value.
BIT
Bit names are shown in uppercase. (Example ENABLE)
FIELD[n:m]
A set of bits from bit n down to m. (Example: PINA[3:0] = {PINA3, PINA2, PINA1,
PINA0}
Reserved
Reserved bits are unused and reserved for future use. For compatibility with future
devices, always write reserved bits to zero when the register is written. Reserved bits
will always return zero when read.
PERIPHERALi If several instances of a peripheral exist, the peripheral name is followed by a number
to indicate the number of the instance in the range 0-n. PERIPHERAL0 denotes one
specific instance.
Reset
Value of a register after a power reset. This is also the value of registers in a peripheral
after performing a software reset of the peripheral, except for the Debug Control
registers.
SET/CLR
Registers with SET/CLR suffix allows the user to clear and set bits in a register without
doing a read-modify-write operation. These registers always come in pairs. Writing a
one to a bit in the CLR register will clear the corresponding bit in both registers, while
writing a one to a bit in the SET register will set the corresponding bit in both registers.
Both registers will return the same value when read. If both registers are written
simultaneously, the write to the CLR register will take precedence.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
711
39.
Acronyms and Abbreviations
The below table contains acronyms and abbreviations used in this document.
Table 39-1. Acronyms and Abbreviations
Abbreviation
Description
AC
Analog Comparator
ADC
Analog-to-Digital Converter
ADDR
Address
AES
Advanced Encryption Standard
AHB
AMBA Advanced High-performance Bus
®
AMBA
Advanced Microcontroller Bus Architecture
APB
AMBA Advanced Peripheral Bus
AREF
Analog reference voltage
BLB
Boot Lock Bit
BOD
Brown-out detector
CAL
Calibration
CC
Compare/Capture
CCL
Configurable Custom Logic
CLK
Clock
CRC
Cyclic Redundancy Check
CTRL
Control
DAC
Digital-to-Analog Converter
DAP
Debug Access Port
DFLL
Digital Frequency Locked Loop
DMAC
DMA (Direct Memory Access) Controller
DSU
Device Service Unit
EEPROM
Electrically Erasable Programmable Read-Only Memory
EIC
External Interrupt Controller
EVSYS
Event System
GCLK
Generic Clock Controller
GND
Ground
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
IF
Interrupt flag
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
712
Abbreviation
Description
INT
Interrupt
MBIST
Memory built-in self-test
MEM-AP
Memory Access Port
MTB
Micro Trace Buffer
NMI
Non-maskable interrupt
NVIC
Nested Vector Interrupt Controller
NVM
Non-Volatile Memory
NVMCTRL
Non-Volatile Memory Controller
OSC
Oscillator
PAC
Peripheral Access Controller
PC
Program Counter
PER
Period
PM
Power Manager
POR
Power-on reset
PORT
I/O Pin Controller
PTC
Peripheral Touch Controller
PWM
Pulse Width Modulation
RAM
Random-Access Memory
REF
Reference
RTC
Real-Time Counter
RX
Receiver/Receive
SERCOM
Serial Communication Interface
™
SMBus
System Management Bus
SP
Stack Pointer
SPI
Serial Peripheral Interface
SRAM
Static Random-Access Memory
SUPC
Supply Controller
SWD
Serial Wire Debug
TC
Timer/Counter
TCC
Timer/Counter for Control Applications
TRNG
True Random Number Generator
TX
Transmitter/Transmit
ULP
Ultra-low power
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
713
Abbreviation
Description
USART
Universal Synchronous and Asynchronous Serial Receiver and Transmitter
USB
Universal Serial Bus
VDD
Common voltage to be applied to VDDIO and VDDANA
VDDIO
Digital supply voltage
VDDANA
Analog supply voltage
VREF
Voltage reference
WDT
Watchdog Timer
XOSC
Crystal Oscillator
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
714
40.
Appendix A: Electrical Characteristics at 105°C
40.1.
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum
values are valid across operating temperature and voltage unless otherwise specified.
These electrical characteristics are relevant for SAMD20 revD and later.
40.2.
Absolute Maximum Ratings
Stresses beyond those listed in the following table may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 40-1. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Units
VDD
Power supply voltage
0
3.8
V
IVDD
Current into a VDD pin
-
48(1)
mA
IGND
Current out of a GND pin
-
68(1)
mA
VPIN
Pin voltage with respect to GND and VDD
GND-0.6V
VDD+0.6V
V
Tstorage
Storage temperature
-60
150
°C
Note: 1. Maximum source current is 24mA and maximum sink current is 34mA per cluster. A cluster is a
group of GPIOs as shown in GPIO Clusters table. Also note that each VDD/GND pair is connected to 2
clusters so current consumption through the pair will be a sum of the clusters source/sink currents.
See GPIO Clusters table through the related link below.
Related Links
Absolute Maximum Ratings on page 606
40.3.
General Operating Ratings
The device must operate within the ratings listed in the following table in order for all other electrical
characteristics and typical characteristics of the device to be valid.
Table 40-2. General operating conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
Power supply voltage
1.62(1)
3.3
3.63
V
VDDANA
Analog supply voltage
1.62(1)
3.3
3.63
V
TA
Temperature range
-40
25
105
°C
TJ
Junction temperature
-
-
145
°C
Notes: 1. With BOD33 disabled. If the BOD33 is enabled, check BOD33 LEVEL ValueTable 40-9
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
715
Related Links
BOD33 on page 617
40.4.
Maximum Clock Frequencies
Table 40-3. Maximum GCLK Generator Output Frequencies
Symbol
Description
Conditions
Max.
Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
GCLK Generator Output Frequency
Undivided
48
Divided
32
MHz
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
fGCLKGEN6
fGCLKGEN7
Table 40-4. Maximum Peripheral Clock Frequencies
Symbol
Description
Max.
Units
fCPU
CPU clock frequency
32
MHz
fAHB
AHB clock frequency
32
MHz
fAPBA
APBA clock frequency
32
MHz
fAPBB
APBB clock frequency
32
MHz
fAPBC
APBC clock frequency
32
MHz
fGCLK_DFLL48M_REF
DFLL48M Reference clock frequency
35.1
kHz
fGCLK_WDT
WDT input clock frequency
48
MHz
fGCLK_RTC
RTC input clock frequency
48
MHz
fGCLK_EIC
EIC input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency
48
MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock frequency
48
MHz
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
716
Symbol
Description
Max.
Units
fGCLK_SERCOM0_CORE
SERCOM0 input clock frequency
48
MHz
fGCLK_SERCOM1_CORE
SERCOM1 input clock frequency
48
MHz
fGCLK_SERCOM2_CORE
SERCOM2 input clock frequency
48
MHz
fGCLK_SERCOM3_CORE
SERCOM3 input clock frequency
48
MHz
fGCLK_SERCOM4_CORE
SERCOM4 input clock frequency
48
MHz
fGCLK_SERCOM5_CORE
SERCOM5 input clock frequency
48
MHz
fGCLK_TC0, GCLK_TC1
TC0,TC1 input clock frequency
48
MHz
fGCLK_TC2, GCLK_TC3
TC2,TC3 input clock frequency
48
MHz
fGCLK_TC4, GCLK_TC5
TC4,TC5 input clock frequency
48
MHz
fGCLK_TC6, GCLK_TC7
TC6,TC7 input clock frequency
48
MHz
fGCLK_ADC
ADC input clock frequency
48
MHz
fGCLK_AC_DIG
AC digital input clock frequency
48
MHz
fGCLK_AC_ANA
AC analog input clock frequency
64
kHz
fGCLK_DAC
DAC input clock frequency
350
kHz
fGCLK_PTC
PTC input clock frequency
48
MHz
40.5.
Power Consumption
The values in the Current Consumption table are measured values of power consumption under the
following conditions, except where noted:
•
•
•
•
•
•
•
Operating conditions
– VVDDIN = 3.3 V
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of
the first instruction fetched in flash.
Oscillators
– XOSC (crystal oscillator) with an external 32MHz clock on XIN
– XOSC32K (32 kHz crystal oscillator) stopped
– DFLL48M stopped
Clocks
– XOSC used as main clock source, except otherwise specified
– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
I/Os are inactive with internal pull-up
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
717
•
•
•
CPU is running on flash with 1 wait states
Low power cache enabled
BOD33 disabled
Table 40-5. Current Consumption
Mode
Conditions
TA
Max.
Units
ACTIVE
CPU running a While(1) algorithm
105°C -
2.55
2.75
mA
CPU running a While(1) algorithm VDDIN
=1.8V,
CPU is running on Flash with 3 wait states
-
2.56
2.82
CPU running a While(1) algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
-
42*freq +318 42*freq +432 μA
(with freq in
MHz)
CPU running a Fibonacci algorithm
-
4.21
4.59
CPU running a Fibonacci algorithm
VDDIN =1.8V, CPU is running on flash with 3
wait states
-
4.23
4.57
CPU running a Fibonacci algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
-
80*freq +320 82*freq +432 μA
(with freq in
MHz)
CPU running a CoreMark algorithm
-
6.02
6.54
CPU running a CoreMark algorithm
VDDIN =1.8V, CPU is running on flash with 3
wait states
-
5.21
5.57
CPU running a CoreMark algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
-
96*freq +322 98*freq +432 μA
(with freq in
MHz)
IDLE0
-
1.55
1.62
IDLE1
-
1.13
1.18
IDLE2
-
0.96
1.01
-
71.3
-
105°C -
214
627
25°C
-
69.8
-
105°C -
212
624
STANDBY XOSC32K running
RTC running at 1kHz (1)
XOSC32K and RTC stopped (1)
25°C
Min. Typ.
mA
mA
mA
μA
Note: 1. Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
718
Table 40-6. Wake-up Time
Mode
Conditions
TA
Min. Typ. Max. Units
IDLE0
OSC8M used as main clock source, low power cache disabled
105°C 3.8
4
4.1
μs
IDLE1
12.8 14.3 15.7
IDLE2
13.7 15.2 16.6
STANDBY
18.7 20.1 21.6
Figure 40-1. Measurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
40.6.
Injection Current
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 40-7. Injection Current(1)
Symbol
Description
min
max
Unit
Iinj1 (2)
IO pin injection current
-1
+1
mA
Iinj2 (3)
IO pin injection current
-15
+15
mA
Iinjtotal
Sum of IO pins injection current
-45
+45
mA
Note:
1. Injecting current may have an effect on the accuracy of Analog blocks
2. Conditions for Vpin: Vpin < GND-0.3V or 3.6V2.0V
-
VDDANA/2
-
V
VREFINTVCC1
Internal ratiometric
reference 1 error (2)
2.0V < VDDANA <
3.63V
-40°C to 85°C
-1.0
-
+1.0
%
Conversion range(1)
Differential mode
-VREF/
GAIN
-
+VREF/GAIN V
Single-ended mode
0.0
-
+VREF/GAIN V
Voltage Error
Voltage Error
Conditions
CSAMPLE
Sampling capacitance(2)
-
3.5
-
pF
RSAMPLE
Input channel source
resistance(2)
-
-
3.5
kΩ
IDD
DC supply current(1)
1.25
2.78
mA
fCLK_ADC = 2.1MHz(3) -
Notes: 1. These values are based on characterization. These values are not covered by test limits in
production.
2. These values are based on simulation. These values are not covered by test limits in production or
characterization.
3. In this condition and for a sample rate of 350ksps, a conversion takes 6 clock cycles of the ADC clock
(conditions: 1X gain, 12-bit resolution, differential mode, free-running).
4. All single-shot measurements are performed with VDDANA > 2.7V (cf. ADC errata)
Table 40-11. Differential Mode
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number Of Bits
With gain compensation
-
10.5
10.7
bits
TUE
Total Unadjusted Error
1x Gainn
1.5
4.3
17.0
LSB
INL
Integral Non Linearity
1x Gainn
1.0
1.3
6.3
LSB
DNL
Differential Non Linearity
1x Gainn
+/-0.3
+/-0.5
+/-0.95
LSB
Gain Error
Ext. Ref 1x
-15.0
2.5
+20.0
mV
VREF=VDDANA/1.48
-20.0
-1.5
+10.0
mV
VREF= INT1V
-15.0
-5.0
+10.0
mV
Ext. Ref. 0.5x
+/-0.1
+/-0.2
+/-0.45
%
Ext. Ref. 2x to 16x
+/-0.1
+/-0.2
+/-2.0
%
Gain Accuracy(5)
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
722
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Offset Error
Ext. Ref. 1x
-10.0
-1.5
+10.0
mV
VREF=VDDANA/1.48
-10.0
0.5
+10.0
mV
VREF= INT1V
-10.0
3.0
+10.0
mV
1x Gain
FCLK_ADC = 2.1MHz
FIN = 40kHz
AIN = 95%FSR
64.2
70.0
78.9
dB
61.4
65.0
66.0
dB
64.3
65.5
66.0
dB
-74.8
-64.0
-65.0
dB
0.6
1.0
1.6
mV
SFDR
Spurious Free Dynamic Range
SINAD
Signal-to-Noise and Distortion
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
Noise RMS
T=25°C
Note: Maximum numbers are based on characterization and not tested in production, and valid for 5% to
95% of the input voltage range.
Note: Dynamic parameter numbers are based on characterization and not tested in production.
Note: Respect the input common mode voltage through the following equations (where VCM_IN is the
Input channel common mode voltage):
a. If |VIN| > VREF/4
•
•
VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 -0.05*VDDANA -0.1V
b. If |VIN| < VREF/4
•
•
VCM_IN < 1.2*VDDANA - 0.75V
VCM_IN > 0.2*VDDANA - 0.1V
Note: The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power
supply. The ADC performance of these pins will not be the same as all the other ADC channels on
pins powered from the VDDANA power supply.
Note: The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) =
(Gain Error in V x 100) / (2*VREF/GAIN)
Table 40-12. Single-Ended Mode
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ENOB
Effective Number of Bits
With gain compensation
-
9.5
9.8
Bits
TUE
Total Unadjusted Error
1x gain
-
10.5
40.0
LSB
INL
Integral Non-Linearity
1x gain
1.0
1.6
7.5
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.5
+/-0.6
+/-0.95
LSB
Gain Error
Ext. Ref. 1x
-5.0
0.7
+5.0
mV
Gain Accuracy(4)
Ext. Ref. 0.5x
+/-0.1
+/-0.34
+/-0.4
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.15
%
Ext. Ref. 1x
-5.0
1.5
+10.0
mV
Offset Error
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
723
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
SFDR
Spurious Free Dynamic Range
63.1
65.0
66.5
dB
SINAD
Signal-to-Noise and Distortion
50.7
59.5
61.0
dB
SNR
Signal-to-Noise Ratio
1x Gain
FCLK_ADC = 2.1MHz
FIN = 40kHz
AIN = 95%FSR
49.9
60.0
64.0
dB
THD
Total Harmonic Distortion
-65.4
-63.0
-62.1
dB
-
1.0
-
mV
Noise RMS
T = 25°C
Note: Maximum numbers are based on characterization and not tested in production, and for 5%
to 95% of the input voltage range.
•
•
Note: Respect the input common mode voltage through the following equations (where VCM_IN is
the Input channel common mode voltage) for all VIN:
VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
Note: The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power
supply. The ADC performance of these pins will not be the same as all the other ADC channels on
pins powered from the VDDANA power supply.
Note: The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) =
(Gain Error in V x 100) / (VREF/GAIN)
40.7.3.1. Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in
order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (�SAMPLE) and a
capacitor (�SAMPLE). In addition, the source resistance (�SOURCE) must be taken into account when
calculating the required sample and hold time. The figure below shows the ADC input channel equivalent
circuit.
Figure 40-3. ADC Input
VDDANA/2
RSOURCE
Analog Input
AINx
CSAMPLE
RSAMPLE
VIN
To achieve n bits of accuracy, the �SAMPLE capacitor must be charged at least to a voltage of
�CSAMPLE ≥ �
IN
× 1 − 2−
�+1
The minimum sampling time �SAMPLEHOLD for a given �SOURCEcan be found using this formula:
�SAMPLEHOLD ≥ �SAMPLE + �
SOURCE
× �SAMPLE × � + 1 × ln 2
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
724
for a 12 bits accuracy: �SAMPLEHOLD ≥ �SAMPLE + �
SOURCE
where
40.7.4.
�SAMPLEHOLD =
× �SAMPLE × 9.02
1
2 × �ADC
Digital to Analog Converter (DAC) Characteristics
Table 40-13. Operating Conditions(1)
Symbol
Parameter
VDDANA
AVREF
IDD
Min.
Typ.
Max.
Units
Analog supply voltage
1.62
-
3.63
V
External reference voltage
1.0
-
VDDANA-0.6
V
Internal reference voltage 1
-
1
-
V
Internal reference voltage 2
-
VDDANA
-
V
Linear output voltage range
0.05
-
VDDANA-0.05
V
Minimum resistive load
5
-
-
kΩ
Maximum capacitance load
-
-
100
pF
-
160
378
μA
DC supply current(2)
Conditions
Voltage pump disabled
Notes: 1. These values are based on specifications otherwise noted.
2. These values are based on characterization. These values are not covered by test limits in production.
Table 40-14. Clock and Timing(1)
Symbol
tSTARTUP
Parameter
Conditions
Conversion rate
Cload=100pF
Rload > 5kΩ
Startup time
Min.
Typ.
Max.
Units
Normal mode
-
-
350
ksps
For ΔDATA=+/-1
-
-
1000
VDDNA > 2.6V
-
-
2.85
μs
VDDNA < 2.6V
-
-
10
μs
Note: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
725
Table 40-15. Accuracy Characteristics(1)
Symbol
Parameter
RES
Input resolution
INL
Integral non-linearity
Conditions
VREF = Ext 1.0V
VREF = VDDANA
VREF = INT1V
DNL
Differential non-linearity
VREF = Ext 1.0V
VREF = VDDANA
VREF= INT1V
Min.
Typ.
Max.
Units
-
-
10
Bits
VDD = 1.6V
0.75
1.1
2.0
LSB
VDD = 3.6V
0.6
1.2
2.5
VDD = 1.6V
1.4
2.2
3.5
VDD = 3.6V
0.9
1.4
1.5
VDD = 1.6V
0.75
1.3
2.5
VDD = 3.6V
0.8
1.2
1.5
VDD = 1.6V
+/-0.9
+/-1.2
+/-2.0
VDD = 3.6V
+/-0.9
+/-1.1
+/-1.5
VDD = 1.6V
+/-1.1
+/-1.7
+/-3.0
VDD = 3.6V
+/-1.0
+/-1.1
+/-1.6
VDD = 1.6V
+/-1.1
+/-1.4
+/-2.5
VDD = 3.6V
+/-1.0
+/-1.5
+/-1.8
LSB
Gain error
Ext. VREF
+/-1.0
+/-5
+/-10
mV
Offset error
Ext. VREF
+/-2
+/-3
+/-8
mV
Note: 1. All values measured using a conversion rate of 350ksps.
40.7.5.
Analog Comparator Characteristics
Table 40-16. Electrical and Timing
Symbol
Parameter
Min.
Typ.
Max.
Positive input voltage range
0
-
VDDANA V
Negative input voltage range
0
-
VDDANA
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low power mode
-25
0.0
+25
mV
Hysteresis = 1, Fast mode
20
50
80
mV
Hysteresis = 1, Low power mode
15
40
75
mV
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
-
60
116
ns
Changes for VACM=VDDANA/2
100mV overdrive, Low power mode
-
225
370
ns
Offset
Hysteresis
Propagation delay
Conditions
Units
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
726
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Enable to ready delay
Fast mode
-
1
2
μs
Enable to ready delay
Low power mode
-
12
19
μs
INL(3)
-1.4
0.75
+1.4
LSB
DNL(3)
-0.9
0.25
+0.9
LSB
Offset Error (1)(2)
-0.200 0.260 +0.920
LSB
Gain Error (1)(2)
-0.89
LSB
tSTARTUP Startup time
VSCALE
0.215 0.89
Notes: 1. According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2. Data computed with the Best Fit method
3. Data computed using histogram
40.7.6.
Temperature Sensor Characteristics
Table 40-17. Temperature Sensor Characteristics(1)
Symbol Parameter
Temperature sensor output
voltage
Conditions
Min. Typ.
T = 25°C, VDDANA = 3.3V
-
0.667 -
V
2.3
2.4
2.5
mV/°C
-4
1
6
mV/V
-
10
°C
Temperature sensor slope
Variation over VDDANA
voltage
VDDANA = 1.62V to 3.6V
Temperature sensor
accuracy
Using the method described in section 32.9.8.2 -10
Max. Units
Note: 1. These values are based on characterization. These values are not covered by test limits in
production.
Related Links
Software-based Refinement of the Actual Temperature on page 625
40.8.
NVM Characteristics
Table 40-18. Maximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Units
1.62V to 2.7V
0
14
MHz
1
28
2
32
0
20
1
32
2.7V to 3.63V
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
727
Note that on this flash technology, a max number of 4 consecutive write is allowed per row. Once this
number is reached, a row erase is mandatory.
Table 40-19. Flash Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
CycNVM
Cycling Endurance(1)
-40°C < Ta < 105°C
25k
150k
-
Cycles
Note: 1. An endurance cycle is a write and an erase operation.
Table 40-20. EEPROM Emulation(1) Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetEEPROM100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
RetEEPROM10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
CycEEPROM
Cycling Endurance(2)
-40°C < Ta < 105°C
100k
600k
-
Cycles
Notes: 1. The EEPROM emulation is a software emulation described in the App note AT03265.
2. An endurance cycle is a write and an erase operation.
Table 40-21. NVM Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tFPP
Page programming time
-
-
-
2.5
ms
tFRE
Row erase time
-
-
-
6
ms
tFCE
DSU chip erase time
(CHIP_ERASE)
-
-
-
240
ms
40.9.
Oscillators Characteristics
40.9.1.
Crystal Oscillator (XOSC) Characteristics
40.9.1.1. Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 40-22. Digital Clock Characteristics
Symbol
Parameter
fCPXIN
XIN clock frequency
Conditions
Min.
Typ.
Max.
Units
-
-
32
MHz
40.9.1.2. Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between
XIN and XOUT as shown in the figure Oscillator Connection. The user must choose a crystal oscillator
where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
728
found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed
as follows:
CLEXT = 2 CL − CSTRAY − CSHUNT
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal.
Table 40-23. Crystal Oscillator Characteristics
Symbol Parameter
fOUT
Crystal oscillator frequency
ESR
Crystal Equivalent Series Resistance
Safety Factor = 3
The AGC doesn’t have any noticeable
impact on these measurements.
Conditions
Min. Typ. Max.
Units
0.4
-
32
MHz
f = 0.455 MHz, CL = 100pF
XOSC.GAIN = 0
-
-
5.6K
Ω
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
-
-
243
f = 8 MHz, CL = 20pF
XOSC.GAIN = 2
-
-
138
f = 16 MHz, CL = 20pF
XOSC.GAIN = 3
-
-
66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
-
-
56
CXIN
Parasitic capacitor load
-
5.9
-
pF
CXOUT
Parasitic capacitor load
-
3.2
-
pF
f = 2MHz, CL = 20pF, AGC off
27
65
87
μA
f = 2MHz, CL = 20pF, AGC on
14
52
76
f = 4MHz, CL = 20pF, AGC off
61
117
155
f = 4MHz, CL = 20pF, AGC on
23
74
104
f = 8MHz, CL = 20pF, AGC off
131
226
308
f = 8MHz, CL = 20pF, AGC on
56
128
181
f = 16MHz, CL = 20pF, AGC off 305
502
714
f = 16MHz, CL = 20pF, AGC on 116
307
590
Current Consumption
f = 32MHz, CL = 18pF, AGC off 1031 1622 2260
f = 32MHz, CL = 18pF, AGC on 278
615
1280
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
729
Symbol Parameter
Conditions
Min. Typ. Max.
tSTARTUP Startup time
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
14K
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
6800 19.5K
f = 8 MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
-
5550 13K
f = 16 MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
-
6750 14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
-
5.3K 9.6K
48K
Units
cycles
Figure 40-4. Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
Xout
C LEXT
40.9.2.
External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
40.9.2.1. Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32
pin.
Table 40-24. Digital Clock Characteristics
Symbol
Parameter
fCPXIN32
Conditions
Min.
Typ.
Max.
Units
XIN32 clock frequency
-
32.768
-
kHz
XIN32 clock duty cycle
-
50
-
%
40.9.2.2. Crystal Oscillator Characteristics
Figure 33-6 and the equation in Crystal Oscillator Characteristics also applies to the 32 kHz oscillator
connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the
range given in the table. The exact value of CL can be found in the crystal datasheet.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
730
Table 40-25. 32kHz Crystal Oscillator Characteristics
Symbol Parameter
fOUT
Conditions
Min. Typ.
Crystal oscillator frequency
tSTARTUP Startup time
ESRXTAL = 39.9 kΩ, CL = 12.5 pF -
Max. Units
32768 -
Hz
28K
30K
cycles
CL
Crystal load capacitance
-
-
12.5 pF
CSHUNT
Crystal shunt capacitance
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.1
-
-
3.3
-
AGC off
-
1.22
2.25 μA
AGC on(1)
-
-
-
CL=12.5pF
-
-
141
TQFP64/48/32 packages
CXOUT32 Parasitic capacitor load
IXOSC32K Current consumption
ESR
Crystal equivalent series resistance
f=32.768kHz
Safety Factor = 3
kΩ
Note: 1. See revD/revC/revB errata concerning the XOSC32K.
40.9.3.
Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 40-26. DFLL48M Characteristics - Closed Loop Mode(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Average Output frequency
fREF = 32.768kHz
47
48
49
MHz
fREF
Reference frequency
0.732
32.768
35.1
kHz
Jitter
Period jitter
fREF = 32.768kHz
-
-
0.84
ns
IDFLL
Power consumption on VDDIN
fREF = 32.768kHz
-
292
-
μA
tLOCK
Lock time
fREF = 32.768kHz
DFLLVAL.COARSE =
DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
100
200
500
μs
Quick lock disabled,
Chill cycle disabled,
CSTEP=3,FSTEP=1,
fREF = 32.768kHz
-
600
-
Note: 1. See revC/revB errata concerning the DFLL48M.
2. All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL
closed loop mode with an external OSC reference or in DFLL closed loop mode using the internal
OSC8M (Only applicable for revC).
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
731
40.9.4.
32.768kHz Internal oscillator (OSC32K) Characteristics
Table 40-27. 32kHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency
Calibrated against a 32.768kHz
reference at 25°C, over [-40, +105]C,
over [1.62, 3.63]V
28.508
32.768
35.062
kHz
Calibrated against a 32.768kHz
reference at 25°C, at VDD=3.3V
32.276
32.768
33.260
Calibrated against a 32.768kHz
reference at 25°C, over [1.62, 3.63]V
31.457
32.768
34.079
IOSC32K
Current consumption
-
0.67
1.62
μA
tSTARTUP
Startup time
-
1
2
cycle
Duty
Duty Cycle
-
50
-
%
40.9.5.
Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table 40-28. Ultra Low Power Internal 32kHz RC Oscillator Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Output frequency
Calibrated against a 32.768kHz
reference at 25°C, over [-40,
+105]C, over [1.62, 3.63]V
25.559
32.768
39.016
kHz
Calibrated against a 32.768kHz
reference at 25°C, at VDD=3.3V
31.293
32.768
34.570
Calibrated against a 32.768kHz
reference at 25°C, over
[1.62, 3.63]V
31.293
32.768
34.570
-
-
180
nA
IOSCULP32K(1)(2)
tSTARTUP
Startup time
-
10
-
cycles
Duty
Duty Cycle
-
50
-
%
Notes: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
2. This oscillator is always on.
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
732
40.9.6.
8MHz RC Oscillator (OSC8M) Characteristics
Table 40-29. Internal 8MHz RC Oscillator Characteristics
Symbol Parameter
Conditions
Min. Typ. Max. Units
fOUT
ICalibrated against a 8MHz reference at 25°C, over
[-40, +105]C, over [1.62, 3.63]V
7.65 8
8.17 MHz
Calibrated against a 8MHz reference at 25°C, at
VDD=3.3V
7.94 8
8.06
Calibrated against a 8MHz reference at 25°C, over
[1.62, 3.63]V
7.92 8
8.08
-
71
168
μA
tSTARTUP Startup time
-
2.1
3
μs
Duty
-
50
-
%
IOSC8M
Output frequency
Current consumption IDLEIDLE2 on OSC32K versus IDLE2 on calibrated
OSC8M enabled at 8MHz (FRANGE=1, PRESC=0)
Duty cycle
Atmel SAM D20E / SAM D20G / SAM D20J [DATASHEET]
Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
733
Atmel Corporation
©
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
2016 Atmel Corporation. / Rev.: Atmel-42129O-SAM D20_Datasheet_Complete-08/2016
®
®
Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
®
®
other countries. ARM , ARM Connected logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be
trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND
CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED
OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS
INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED
OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to
update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive
applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any
applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without
an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the
operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments
unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically
designated by Atmel as automotive-grade.
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Atmel:
ATSAMD20J17A-AU ATSAMD20E18A-AU ATSAMD20E18A-AUT ATSAMD20E18A-MUT ATSAMD20E18A-MU
ATSAMD20J16A-CU ATSAMD20J17A-MN ATSAMD20E17A-ANT ATSAMD20E14A-MNT ATSAMD20G14A-MNT
ATSAMD20J14A-AN ATSAMD20J15A-CN ATSAMD20J14A-CNT ATSAMD20E16A-MN ATSAMD20G17A-ANT
ATSAMD20J18A-CN ATSAMD20J15A-CUT ATSAMD20J16A-CNT ATSAMD20J16A-MN ATSAMD20E17A-MNT
ATSAMD20G18A-ANT ATSAMD20J16A-MNT ATSAMD20E15A-MN ATSAMD20J18A-CU ATSAMD20E16A-AN
ATSAMD20G14A-ANT ATSAMD20J16A-CUT ATSAMD20E18A-MNT ATSAMD20J16A-CN ATSAMD20J14A-ANT
ATSAMD20G18A-AUES ATSAMD20G14A-MN ATSAMD20G17A-MNT ATSAMD20J17A-CU ATSAMD20G17A-UUT
ATSAMD20J17A-ANT ATSAMD20G16A-AN ATSAMD20J15A-CNT ATSAMD20J17A-MNT ATSAMD20G15A-MN
ATSAMD20G17A-AN ATSAMD20J18A-AN ATSAMD20G15A-ANT ATSAMD20J14A-CN ATSAMD20J18A-ANT
ATSAMD20E16A-MNT ATSAMD20E14A-ANT ATSAMD20G16A-ANT ATSAMD20J15A-AN ATSAMD20J15A-ANT
ATSAMD20J17A-CUT ATSAMD20J14A-MN ATSAMD20G18A-UUT ATSAMD20E17A-MN ATSAMD20J15A-CU
ATSAMD20G18A-MN ATSAMD20G15A-MNT ATSAMD20E15A-MNT ATSAMD20J16A-ANT ATSAMD20G14A-AN
ATSAMD20J18A-MN ATSAMD20G16A-MN ATSAMD20E15A-ANT ATSAMD20G18A-MNT ATSAMD20G16A-MNT
ATSAMD20J17A-AN ATSAMD20J15A-MN ATSAMD20J14A-CU ATSAMD20E15A-AN ATSAMD20J14A-MNT
ATSAMD20G15A-AN ATSAMD20G18A-AN ATSAMD20E14A-AN ATSAMD20J17A-CN ATSAMD20E18A-AN
ATSAMD20J16A-AN ATSAMD20J18A-CUT ATSAMD20E16A-ANT ATSAMD20E17A-AN ATSAMD20E14A-MN
ATSAMD20J15A-MNT ATSAMD20J14A-CUT ATSAMD20E18A-MN ATSAMD20J18A-MNT ATSAMD20J18A-CNT
ATSAMD20G17A-MN ATSAMD20E18A-ANT ATSAMD20J17A-CNT
