SAM R34/R35
SAM R34/R35 Low Power LoRa® Sub-GHz SiP Datasheet
Introduction
The SAM R34/R35 is a family of ultra-low power microcontrollers combined with a UHF transceiver
communication interface. It uses a 32-bit ARM® Cortex® -M0+ processor and offers up to 256 KB of
Flash and 40 KB of SRAM, including an area of battery backed-up SRAM. The UHF transceiver supports
LoRa® and FSK modulation. LoRa technology is a spread spectrum protocol optimized for low data-rate,
ultra-long range signaling. It is ideal for battery-powered remote sensors and controls.
The SAM R34 includes an integrated microcontroller with USB and the UHF transceiver, making it
suitable for USB dongle applications or for software updates via USB. The SAM R35 offers the same
microcontroller functions along with the UHF transceiver without the USB interface.
Features
Operational Features
• Processor:
– ARM Cortex -M0+ CPU running at up to 48 MHz (2.46CoreMark®/MHz)
– Single-Cycle Hardware Multiplier
– Micro Trace Buffer (MTB)
• Memory:
– In-System Self-Programmable Flash Memory, with options for sizes - 256 KB, 128 KB or 64 KB
– Static Random Access Memory (SRAM) with options for sizes - 32 KB, 16 KB or 8 KB
– Low power SRAM Memory with option for sizes - 4 KB or 8 KB
• System:
– Power-on Reset (POR) and Brown-out Reset
– Internal and External Clock Options with 48 MHz Digital Frequency Locked Loop (DFLL48M)
and 48 MHz to 96 MHz Fractional Digital Phase Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
– Up to 16 External Interrupts
– One Non-Maskable Interrupt
– Two Pin Serial Wire Debug (SWD) Programming, Test and Debugging Interfaces
• Operating Voltage: 1.8V- 3.6V
• Low Power Consumption
– Transceiver:
• RX = 16 mA (typical)
• RFO_HF = 33 mA (typical)
• PA_BOOST = 95 mA (typical)
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 1
SAM R34/R35
– MCU:
• Idle, Standby, and Backup Sleep Modes
• SleepWalking peripherals
• Temperature Range: -40°C to +85°C (Industrial)
RF/Analog Features
• Integrated LoRa Technology Transceiver:
– Tri-band Coverage
• 137 MHz to 175 MHz
• 410 MHz to 525 MHz
• 862 MHz to 1020 MHz
– +20 dBm (100 mW) Max Power (VDDANA > 2.4 VDC)
– +17 dBm (50 mW) Max Power (Regulated PA)
– +13 dBm (20 mW) High-efficency PA
• High Sensitivity:
– Down to -136 dBm (LoRaWAN™ protocol compliant modes)
– Down to -148 dBm (proprietary narrowband modes)
•
•
•
•
•
•
•
•
•
Up to 168 dB Maximum Link Budget
Robust Front-End: IIp3 = -11 dBm
Excellent Blocking Immunity
Low RX Current of 17 mA (typical)
Fully Integrated Synthesizer with a Resolution of 61 Hz
LoRa Technology, (G)FSK, (G)MSK and OOK Modulation
Preamble Detection
127 dB Dynamic Range RSSI
Automatic RF Sense and CAD with Ultra-Fast Automatic Frequency Control (AFC) Packet Engine up
to 256 bytes with Cyclic Redundancy Check (CRC)
Peripheral Information
• 16-Channel Direct Memory Access Controller (DMAC)
• 12-Channel Event System
• Three 16-bit Timer/Counters (TC), configurable as either of the following:
– One 8-bit TC with compare/capture channels
– One 16-bit TC with compare/capture channels
– One 32-bit TC with compare/capture channels, by using two TCs
• Two 24-bit and one 16-bit Timer/Counters for Control (TCC), with Extended Functions:
– Up to four compare channels with optional complementary output
– Generation of synchronized Pulse Width Modulation (PWM) pattern across port pins
– Deterministic fault protection, fast decay and configurable dead-time between complementary
output
– Dithering that increases resolution with up to five bit and reduces quantization error
• 32-bit Real Time Counter (RTC) with Clock/Calendar Function
• Watchdog Timer (WDT)
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 2
SAM R34/R35
• CRC-32 Generator
• One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0 Interface:
– Embedded host and device function
– Eight endpoints
• Up to Five Serial Communication Interfaces (SERCOM), each configurable to operate as either of the
following:
– USART with full-duplex and single-wire half-duplex configuration
– I2C up to 3.4 MHz
– Serial Peripheral Interface (SPI)
– Local Interconnect Network (LIN) Slave
• One 12-bit, 1 Msps Analog-to-Digital Converter (ADC) with up to Eight External Channels:
– Differential and single-ended input
– Automatic offset and gain error compensation
– Oversampling and decimation in hardware to support 13-, 14-, 15-, or 16-bit resolution
• Two Analog Comparators (AC) with Window Compare Function
• Peripheral Touch Controller (PTC):
– 18-channel capacitive touch and proximity sensing
Package Information
• 27 Programmable I/O Pins
• 64 Lead Ball Grid Array (BGA)
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 3
SAM R34/R35
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description.................................................................................................................6
2. Configuration Summary.............................................................................................7
3. Ordering Information for SAM R34/R35.................................................................... 9
3.1.
SAM R34/R35 Ordering Codes.................................................................................................... 9
4. System Introduction.................................................................................................10
4.1.
4.2.
4.3.
SAM R34/R35 Pinout Details..................................................................................................... 10
SiP Block Diagram..................................................................................................................... 10
Peripheral Key Table.................................................................................................................. 11
5. I/O Multiplexing and Considerations........................................................................14
5.1.
5.2.
5.3.
Multiplexed Signals.................................................................................................................... 14
Internal Multiplexed Signals....................................................................................................... 15
Other Functions..........................................................................................................................16
6. Signal Description....................................................................................................18
6.1.
Signal Details............................................................................................................................. 18
7. Processor and Architecture..................................................................................... 21
7.1.
7.2.
7.3.
7.4.
Cortex M0+ Processor............................................................................................................... 21
Nested Vector Interrupt Controller..............................................................................................22
Micro Trace Buffer...................................................................................................................... 24
High-Speed Bus System............................................................................................................ 25
8. Application Schematic Introduction......................................................................... 30
8.1.
8.2.
SAM R34/R35 Basic Application Schematic.............................................................................. 30
SAM R34/R35 Bill of Materials................................................................................................... 32
9. Transceiver Circuit Description................................................................................34
9.1.
9.2.
Transceiver Pin Description........................................................................................................34
Transceiver Validation................................................................................................................ 35
10. Microcontroller Interface.......................................................................................... 36
11. Electrical Characteristics......................................................................................... 38
11.1. Absolute Maximum Ratings........................................................................................................38
11.2. General Operating Conditions....................................................................................................38
11.3. Performance Characteristics...................................................................................................... 39
12. SAM R34/R35 Package Information........................................................................44
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 4
SAM R34/R35
12.1. Package Drawings..................................................................................................................... 44
12.2. SAM R34/R35 Land Pattern.......................................................................................................45
13. Best Practices for Designers................................................................................... 46
13.1.
13.2.
13.3.
13.4.
13.5.
13.6.
Introduction.................................................................................................................................46
Power Supply............................................................................................................................. 46
External Reset Circuit.................................................................................................................49
Unused or Unconnected Pins.....................................................................................................50
Clocks and Crystal Oscillators....................................................................................................50
Programming and Debug Ports..................................................................................................52
14. Reference Documentation.......................................................................................57
15. Document Revision History..................................................................................... 58
The Microchip Web Site................................................................................................ 59
Customer Change Notification Service..........................................................................59
Customer Support......................................................................................................... 59
Microchip Devices Code Protection Feature................................................................. 59
Legal Notice...................................................................................................................60
Trademarks................................................................................................................... 60
Quality Management System Certified by DNV.............................................................61
Worldwide Sales and Service........................................................................................62
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 5
SAM R34/R35
Description
1.
Description
The SAM R34/R35 devices are a series of ultra-low power microcontrollers equipped with a UHF
transceiver. It uses the 32-bit ARM Cortex-M0+ processor at max. 48 MHz (2.46 CoreMark/MHz) and
offers 256 KB of Flash and 40 KB of SRAM. Sophisticated power management technologies, such as
power domain gating, SleepWalking, ultra-low power peripherals and more, allow for very low line-power
consumptions.
The UHF transceiver supports LoRa and FSK modulation schemes. The LoRa technology is optimized for
long-range communication with minimal line-power demand. The transceiver can work from frequencies
of 137 MHz to 1020 MHz. Maximum transmit power is +20 dBm without an external amplification.
Operational frequency bands and power limits are defined by local regulations and the LoRa Alliance.
LoRa network stack regional options insure compliance. FSK modulation is also supported for
applications including IEEE 802.15.4g, WiSUN, and legacy proprietary networks.
All devices have accurate low power external and internal oscillators. Different clock domains can be
independently configured to run at different frequencies, enabling power-saving by running each
peripheral at its optimal clock frequency, thus maintaining a high CPU frequency while reducing power
consumption.
The SAM R34/R35 devices have four software-selectable sleep modes: Idle, Standby, Backup and Off. In
Idle mode, the CPU is stopped while all other functions may be kept running. In Standby mode, all clocks
and functions are stopped except those selected to continue running. In this mode all RAMs and logic
contents are retained. The device supports SleepWalking, which allows some peripherals to wake-up
from sleep based on predefined conditions, thus allowing some internal operations like DMA transfer
and/or the CPU to wake-up only when needed; for example, when a threshold is crossed or a result is
ready. The event system supports synchronous and asynchronous events, allowing peripherals to
receive, react to and send events even in Standby mode. Off mode is not advised, as high impedance on
the internal SPI bus results in metastability.
The SAM R34/R35 devices have two software-selectable performance levels (PL0 and PL2) allowing the
user to scale the lowest core voltage level that supports the operating frequency. To further minimize
current consumption, specifically leakage dissipation, the devices utilize a power domain gating technique
with retention to turn off some logic areas while keeping their logic state. This technique is fully handled in
hardware.
The Flash program memory can be reprogrammed in-system through the Serial Wire Debug (SWD)
interface. The same interface can also be used for non-intrusive on-chip debugging of application code. A
boot loader running in the device can use any communication interface to download and upgrade the
application program in the Flash memory.
The SAM R34/R35 devices are supported with a full suite of programs and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation
kits.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 6
SAM R34/R35
Configuration Summary
2.
Configuration Summary
Table 2-1. Configuration Summary
Parameter
SAM R34
SAM R35
Total Pins
64
64
General Purpose I/O pins 27
(GPIOs)
27
Flash
256 KB
256 KB
Flash RWW Section
8 KB
8 KB
System SRAM
32 KB
32 KB
Low Power SRAM
8 KB
8 KB
Timer Counter (TC)
Instances
3
3
Waveform Output
Channels per TC
Instance
2
2
Timer Counter for Control 3
(TCC) Instances
3
Waveform Output
Channels per TCC
4/2/2
4/2/2
USB Interface
1
0
Serial Communication
Interface (SERCOM)
Instances
5+1 (1)
5+1 (1)
Analog-to-Digital
Converter (ADC)
Channels
8
8
Analog Comparators
(AC)
2
2
Real-Time Counter (RTC) Yes
Yes
RTC Alarms
1
1
RTC Compare Values
1 for 32-bit value or
1 for 32-bit value or
2 for 16-bit values
2 for 16-bit values
External Interrupt Lines
15
15
Maximum CPU
Frequency
48 MHz
48 MHz
Package
BGA
BGA
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 7
SAM R34/R35
Configuration Summary
...........continued
Parameter
SAM R34
SAM R35
32.768 kHz Crystal
Oscillator (XOSC32K)
External
External
Oscillators
• 16 MHz crystal oscillator for TRX
(XOSCRF)
• 0.4-32 MHz crystal oscillator
(XOSC)
• 32.768 kHz external oscillator
(OSC32K)
• 32 kHz ultra-low power internal
oscillator (OSCULP32K)
• 8 MHz high-accuracy internal
oscillator (OSC8M)
• 48 MHz Digital Frequency
Locked Loop (DFLL48M)
• 96 MHz Fractional Digital
Phased Locked Loop (FDPLL96)
• 16 MHz crystal oscillator for TRX
(XOSCRF)
• 0.4-32 MHz crystal oscillator
(XOSC)
• 32.768 kHz external oscillator
(OSC32K)
• 32 kHz ultra-low power internal
oscillator (OSCULP32K)
• 8 MHz high-accuracy internal
oscillator (OSC8M)
• 48 MHz Digital Frequency
Locked Loop (DFLL48M)
• 96 MHz Fractional Digital
Phased Locked Loop (FDPLL96)
Event System Channels
12
12
SW Debug Interface
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
1.
SERCOM4 is internally connected to the Transceiver (TRX).
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 8
SAM R34/R35
Ordering Information for SAM R34/R35
3.
Ordering Information for SAM R34/R35
Figure 3-1. SAM R34/R35 Ordering Information
ATSAMR
34
J
18
B
T-
I/
xxx
Product Family
SAMR = SoC Microcontroller with RF
Product Series
34 = Cortex M0+ CPU + DMA + USB + LoRa Transeiver
35 = Cortex M0+ CPU + DMA + LoRa Transeiver
Pin Count
J = 64 Pins
Flash Memory Density
16 = 64 KB
17 = 128 KB
18 = 256 KB
Device Variant
B = Release to Production
Package Carrier
T = Tape and Reel
Temperature Rating
I = - 40 to + 85 oC
Package Type
7JX = 64 Ball 6x6 mm TFBGA
3.1
SAM R34/R35 Ordering Codes
Table 3-1. SAM R34/R35 Ordering Codes
Ordering Code
Description
ATSAMR34J16BT-I/7JX
LoRa SiP Transceiver USB 64K Flash 8K SRAM, 4KB LP SRAM, T&R
ATSAMR34J17BT-I/7JX
LoRa SiP Transceiver USB 128K Flash 16K SRAM, 8KB LP SRAM,
T&R
ATSAMR34J18BT-I/7JX
LoRa SiP Transceiver USB 256K Flash 32K SRAM, 8KB LP SRAM,
T&R
ATSAMR35J16BT-I/7JX
LoRa SiP Transceiver 64K Flash 8K SRAM, 4KB LP SRAM, T&R
ATSAMR35J17BT-I/7JX
LoRa SiP Transceiver 128K Flash 16K SRAM, 8KB LP SRAM, T&R
ATSAMR35J18BT-I/7JX
LoRa SiP Transceiver 256K Flash 32K SRAM, 8KB LP SRAM, T&R
Note: The device variant (last letter of the ordering number) is independent of the die revision.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 9
SAM R34/R35
System Introduction
4.
4.1
System Introduction
SAM R34/R35 Pinout Details
Figure 4-1. SAM R34/R35 Pin Placement
1
4.2
2
3
4
5
6
7
8
A
RFI_HF
GND_RF
PA00
PA01
VDDCORE
VSW
VDDIN
VDDIO2
B
RFO_HF
GND_RF
GNDANA
PB02
GND
RESET*
GND
PA24
C
VBAT_RF
VDDANA
PB03
PA05
PA30
PA28
PB23
PA25
D
VR_PA
RXTX
PA04
GND
PA31
GND
PA23
PA22
E
GND_RF
GNDANA
PA06
PA27
PB22
PA17
PA18
PA19
F
PA_BOOST
GND_RF
PA07
PA08
PA09
PA13
PA16
PA14
G
RFO_LF
GND_RF
GND_RF
VDDI01
GND_RF
GND_RF
GND_RF
PA15
H
RFI_LF
VR_ANA
VBAT_ANA
VR_DIG
GND_RF
XTA
XTB
VBAT_DIG
SiP Block Diagram
The following figure illustrates the SAM R34/R35 System-in-Package (SiP) block diagram.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 10
SAM R34/R35
System Introduction
Figure 4-2. System Block Diagram with MCU and Transceiver
SWCLK
CORTEX-M0+
PROCESSOR
SERIAL
WIRE
Fmax 48 MHz
256/128/64KB
NVM
32/16/8KB
RAM
NVM Controller
SRAM
CONTROLLER
EVENT
SWDIO
MEMORY
TRACE BUFFER
IOBUS
DEVICE
SERVICE
UNIT
Cache
M
M
S
S
S
HIGH SPEED
BUS MATRIX
S
S
M
M
S
DP
USB FS
DEVICE
MINI-HOST
(SAMR34 ONLY)
DM
SOF 1KHZ
8/8/4KB
RAM
AHB-APB
BRIDGE B
S
LP SRAM
CONTROLLER
S
LOW POWER
BUS MATRIX
PERIPHERAL
ACCESS
CONTROLLER
S
DMA
M
S
S
EVENT
AHB-APB
BRIDGE A
AHB-APB
BRIDGE D
AHB-APB
BRIDGE C
DMA
56xxSERCOM
SERCOM
MAIN CLOCKS
CONTROLLER
4 x TIMER / COUNTER
8 x Timer Counter
PORT
DMA
OSC16M
WO1
FDPLL96M
GENERIC CLOCK
CONTROLLER
EVENT
DMA
WO0
WO1
(2)
WOn
AES
DMA
TRNG
PORT
GCLK_IO[7..0]
3x TIMER / COUNTER
FOR CONTROL
EVENT SYSTEM
DFLL48M
XOSC
WO0
DMA
EVENT
OSCILLATORS CONTROLLER
XIN
XOUT
PAD0
PAD1
PAD2
PAD3
EVENT
AHB-APB
BRIDGE E
WATCHDOG
TIMER
POWER
MANAGER
XIN32
XOUT32
OSC32K CONTROLLER
XOSC32K
WO0
DMA
OSCULP32K
WO1
TIMER / COUNTER
OSC32K
DMA
SUPPLY CONTROLLER
BOD33
EVENT
VREF
RESET
RESET
CONTROLLER
REAL TIME
COUNTER
EXTINT[15..0]
NMI
EVENT
AIN[19..0]
VREFA
VREFB
AIN[3..0]
2 ANALOG
COMPARATORS
EVENT
VREG
EXTWAKEx
8-CHANNEL
12-bit ADC 1MSPS
X[15..0]
PERIPHERAL
TOUCH
CONTROLLER
Y[15..0]
IN[2..0]
3 x CCL
EVENT
OUT
EVENT
EXTERNAL INTERRUPT
CONTROLLER
PAD0
PAD1
PAD2
PAD3
SERCOM
DIO(0...5)
SERCOM4
CONFIGURATION REGISTERS AND FIFO
DEMOD
LoRa/FSK/OOK
MODULATOR
LoRa/FSK/OOK
ADC
i
MUX
Q
HIGH BAND
FRAC-N PLL
LOW BAND
FRAC-N PLL
PA
HF
4.3
PA
HP
OSC
RF
PA
HF
Peripheral Key Table
The following table lists all the peripherals supported in SAM R34 and SAM R35. Also, provides the
references to relevant sections for detailed information.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 11
SAM R34/R35
System Introduction
Note: The peripherals that are not listed in the following table must not be used.
Table 4-1. Peripheral Key Table
Peripheral
Description
Reference
Document
Topic # and Keyword
AC
Analog Comparator
1
43. AC – Analog Comparators
ADC
Analog-to-Digital
Converter
1
42. ADC – Analog-to-Digital
Converter
AES
Advanced Encryption
Engine
1
38. AES – Advanced Encryption
Standard
BOD33
Brown-out Detector
1
23. SUPC – Supply Controller
CCL
Configurable Custom
Logic
1
40. CCL – Configurable Custom
Logic
CRC
Cyclic Redundancy
Check-sum
1
15.11.3 32-bit Cyclic
Redundancy Check CRC32
DMA
Direct Memory Access
Controller
1
26. DMAC – Direct Memory
Access Controller
EIC
External Interrupt
1
27. EIC – External Interrupt
Controller
EVSYS
Event System
1
30. EVSYS – Event System
GCLK
Generic Clock Control
1
17. GCLK - Generic Clock
Controller
I2C
Inter-integrated Circuit
Interface
1
34. SERCOM I2C – SERCOM
Inter-integrated Circuit
MCLK
Main Clock Control
1
18. MCLK – Main Clock
NVMCTRL
Nonvolatile Memory
Controller
1
28. NVMCTRL – Nonvolatile
Memory Controller
OSC32KCTRL 32 kHz Clock
1
22. OSC32KCTRL – 32KHz
Oscillators Controller
OSCCTRL
Clock Control
1
21. OSCCTRL – Oscillators
Controller
PA_BOOST
RF Output High-power
5
5.4.2. RF Power Amplifiers
PM
Power Management
1
20. PM – Power Manager
PORT
GPIO Port Controller
1
29. PORT - I/O Pin Controller
PORT
Power-On Reset
1
23. SUPC – Supply Controller
© 2019 Microchip Technology Inc.
Datasheet
Notes
Peripheral function FSERCOM4 pins
(PB30, PB31, PC18,
PC19) are internally
connected to
Transceiver. For
details, refer to 10.
Microcontroller
Interface.
Limited to 27 ports
DS70005356C-page 12
SAM R34/R35
System Introduction
...........continued
Peripheral
Description
Reference
Document
Topic # and Keyword
Notes
PTC
Peripheral Touch
Controller (RC)
1
45. PTC - Peripheral Touch
Controller
RFI_HF
RF Input High
Frequency
5
5.5. Receiver Description
RFI_LF
RF Input Low Frequency 5
5.5. Receiver Description
RFO_HF
RF Output High
Frequency
5
5.4.2. RF Power Amplifiers
RFO_LF
RF Output Low
Frequency
5
5.4.2. RF Power Amplifiers
RSTC
Reset Control
1
19. RSTC – Reset Controller
RTC
Real-Time Counter
1
25. RTC – Real-Time Counter
SPI
Serial Peripheral
Interface
1
33. SERCOM SPI – SERCOM
Serial Peripheral Interface
TC
Timer Counter
1
35. TC – Timer/Counter
TCC
Timer Counter for
Control
1
36. TCC – Timer/Counter for
Control Applications
TRNG
Random Number
Generator
1
37. TRNG – True Random
Number Generator
USART
Universal Synchronous
and Asynchronous
Receiver/Transmitter
1
32. SERCOM USART –
SERCOM Universal
Synchronous and
Asynchronous Receiver and
Transmitter
Peripheral function FSERCOM4 pins
(PB30, PB31, PC18,
PC19) are internally
connected to
Transceiver.
USB
Full-speed Universal
Serial Bus 2.0 interface
1
39. USB – Universal Serial Bus
SAMR34 Only. For
details, refer to 10.
Microcontroller
Interface.
VBAT
External Battery Input
1
23. SUPC – Supply Controller
WDT
Watchdog Timer
1
24. WDT – Watchdog Timer
XTA/B
RF Oscillator
5
5.3. Frequency Synthesis
Peripheral function FSERCOM4 pins
(PB30, PB31, PC18,
PC19) are internally
connected to
Transceiver. For
details, refer to 10.
Microcontroller
Interface.
Note: For more details on the peripherals supported by the SAM R34, refer to Table 5-1.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 13
SAM R34/R35
I/O Multiplexing and Considerations
5.
I/O Multiplexing and Considerations
5.1
Multiplexed Signals
By default, each pin is controlled by the PORT as a general purpose I/O and alternatively may be
assigned to one of the peripheral functions A, B, C, D, E, F, G, H or I. To enable a peripheral function on a
pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0..31) in the PORT must be written to '1'. The selection of peripheral functions
A to H are done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing
register (PMUXn.PMUXE/O) in the PORT.
Table 5-1. Port Function Multiplexing
SAM
R34/R35
Pin
I/O Pin
Supply
B (1)(2)
A
EIC
RSTC
REF
ADC
AC
PTC X-
PTC Y-
lines
lines
C
D
E
F
G
H
I
SERCOM (1)(2)
SERCOM- ALT
TC/TCC
TCC
COM
AC/GCLK/
SUPC
CCL
A3
PA00
VSWOUT
EXTINT[0]
EXTWAKE[0]
-
-
-
-
-
-
SERCOM1/
PAD[0]
TCC2/WO[0]
-
-
-
-
A4
PA01
VSWOUT
EXTINT[1]
EXTWAKE[1]
-
-
-
-
-
-
SERCOM1/
PAD[1]
TCC2/WO[1]
-
-
-
-
D3
PA04
VDDANA
EXTINT[4]
EXTWAKE[4]
VREFB
AIN[4]
AIN[0]
-
-
-
SERCOM0/
PAD[0]
TCC0/WO[0]
-
-
-
CCL0/ IN[0]
C4
PA05
VDDANA
EXTINT[5]
EXTWAKE[5]
-
AIN[5]
AIN[1]
-
-
-
SERCOM0/
PAD[1]
TCC0/WO[1]
-
-
-
CCL0/ IN[1]
E3
PA06
VDDANA
EXTINT[6]
EXTWAKE[6]
-
AIN[6]
AIN[2]
-
Y[4]
-
SERCOM0/
PAD[2]
TCC1/WO[0]
-
-
-
CCL0/ IN[2]
F3
PA07
VDDANA
EXTINT[7]
EXTWAKE[7]
-
AIN[7]
AIN[3]
-
-
-
SERCOM0/
PAD[3]
TCC1/WO[1]
-
-
-
CCL0/
OUT[0]
F4
PA08
VDDIO
NMI
—
-
AIN[16]
-
X[0]
Y[6]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0]
TCC1/
WO[2]
-
-
CCL1/ IN[3]
F5
PA09
VDDIO
EXTINT[9]
—
—
AIN[17]
X[1]
Y[7]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC0/WO[1]
TCC1/
WO[3]
—
—
CCL1/ IN[1]
F6
PA13
VDDIO
EXTINT[13]
—
—
—
—
—
—
SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TCC2/WO[1]
TCC0/
WO[7]
—
AC/CMP[1]
—
F8
PA14
VDDIO
EXTINT[14]
—
—
—
—
—
—
SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TC4/ WO[0]
TCC0/
WO[4]
—
GCLK_IO[0]
—
G8
PA15
VDDIO
EXTINT[15]
—
—
—
—
—
—
SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TC4/ WO[1]
TCC0/
WO[5]
—
GCLK_IO[1]
—
F7
PA16
VDDIO
EXTINT[0]
—
—
—
—
X[4]
—
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TCC2/WO[0]
TCC0/
WO[6]
—
GCLK_IO[2]
CCL0/ IN[0]
E6
PA17
VDDIO
EXTINT[1]
—
—
—
—
X[5]
—
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TCC2/WO[1]
TCC0/
WO[1]
—
GCLK_IO[3]
CCL0/ IN[1]
E7
PA18
VDDIO
EXTINT[2]
—
—
—
—
X[6]
—
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC4/ WO[0]
TCC0/
WO[2]
—
AC/CMP[0]
CCL0/ IN[2]
E8
PA19
VDDIO
EXTINT[3]
—
—
—
—
X[7]
—
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC4/ WO[1]
TCC0/
WO[3]
—
AC/CMP[1]
CCL0/
OUT[0]
D8
PA22
VDDIO
EXTINT[6]
—
—
—
—
X[10]
—
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TC0/ WO[0]
TCC0/
WO[4]
—
GCLK_IO[6]
CCL2/ IN[0]
D7
PA23
VDDIO
EXTINT[7]
—
—
—
—
X[11]
—
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TC0/ WO[1]
TCC0/
WO[5]
USB/SOF 1
kHz[6]
GCLK_IO[7]
CCL2/ IN[1]
B8
PA24
VDDIO
EXTINT[12]
—
—
—
—
—
—
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TC1/ WO[0]
TCC1/
WO[2]
USB/ DM[6]
—
CCL2/ IN[2]
C8
PA25
VDDIO
EXTINT[13]
—
—
—
—
—
—
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TC1/ WO[1]
TCC1/
WO[3]
USB/ DP[6]
—
CCL2/
OUT[2]
E5
PB22
VDDIN
EXTINT[6]
—
—
—
—
—
—
—
SERCOM5/
PAD[2]
TC3/ WO[0]
—
—
GCLK_IO[0]
CCL0/ IN[0]
C7
PB23
VDDIN
EXTINT[7]
—
—
—
—
—
—
—
SERCOM5/
PAD[3]
TC3/ WO[1]
—
—
GCLK_IO[1]
CCL0/
OUT[0]
E4
PA27
VDDIN
EXTINT[15]
—
—
—
—
—
—
—
—
—
—
—
GCLK_IO[0]
—
C6
PA28
VDDIN
EXTINT[8]
—
—
—
—
—
—
—
—
—
—
—
GCLK_IO[0]
—
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 14
SAM R34/R35
I/O Multiplexing and Considerations
...........continued
SAM
R34/R35
Pin
I/O Pin
Supply
A
EIC
RSTC
B (1)(2)
C
D
E
F
G
H
I
REF
SERCOM (1)(2)
SERCOM- ALT
TC/TCC
TCC
COM
AC/GCLK/
SUPC
CCL
ADC
AC
PTC X-
PTC Y-
lines
lines
C5
PA30
VDDIN
EXTINT[10]
—
—
—
—
—
—
—
SERCOM1/
PAD[2]
TCC1/WO[0]
—
SWCLK
GCLK_IO[0]
CCL1/ IN[0]
D5
PA31
VDDIN
EXTINT[11]
—
—
—
—
—
—
—
SERCOM1/
PAD[3]
TCC1/WO[1]
—
SWDIO(3)
—
CCL1/
OUT[1]
B4
PB02
VSWOUT
EXTINT[2]
—
—
AIN[10]
—
—
—
—
SERCOM5/
PAD[0]
TC2/ WO[0]
—
—
SUPC/ OUT[1]
CCL0/
OUT[0]
C3
PB03
VSWOUT
EXTINT[3]
—
—
AIN[11]
—
—
—
—
SERCOM5/
PAD[1]
TC2/ WO[1]
—
—
SUPC/VBAT
1.
2.
3.
4.
5.
6.
5.2
All analog pin functions are on peripheral function B. Peripheral function B must be selected to
disable the digital control of the pin.
Only some pins can be used in SERCOM I2C mode. See 5.3.3 SERCOM I2C Pins .
This function is only activated in the presence of a debugger.
When an analog peripheral is enabled, the analog output of the peripheral interferes with the
alternative functions of this pin. This is also true even when the peripheral is used for internal
purposes.
Clusters of multiple GPIO pins are sharing the same supply pin. See 5.3.4 GPIO Cluster.
USB is not available on the SAM R35 devices.
Internal Multiplexed Signals
By default, each pin is controlled by the PORT as a general purpose I/O and alternatively may be
assigned to one of the peripheral functions A, B, C, D, E, F, G, H or I. To enable a peripheral function on a
pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to ‘1’. The selection of peripheral functions A
to H are done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing
register (PMUXn.PMUXE/O) in the PORT.
Table 5-2. Internal Multiplexed Signals
Internal
Signal
I/O Pin
Supply
Type
A
EIC
B
RSTC
REF
ADC
AC
PTC
Xlines
PTC
C
D
E
F
G
H
I
SERCOM
SERCOMALT
TC/TCC
TCC/
SERCOM
COM
AC/GCLK/
SUPC
CCL
Ylines
DIO0
PB16
VDDIO
I/O
EXTINT[0]
-
-
-
-
-
-
SERCOM5/
PAD[0]
-
TCC2/
WO[0]
TCC0/ WO[4]
-
GCLK_IO[2]
CCL3/
IN[11]
DIO1/
DCLK
PA11
VDDIO
I/O
EXTINT[11]
-
-
AIN[19]
-
X[3]
Y[9]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/
WO[1]
TCC0/ WO[3]
-
GCLK_IO[5]
CCL1/
OUT[1]
DIO2/
DATA
PA12
VDDIO
I/O
EXTINT[12]
-
-
-
-
-
-
SERCOM2/
PAD[0]
SERCOM4/
PAD[0]
TCC2/
WO[0]
TCC0/ WO[6]
-
AC/CMP[0]
-
DIO3
PB17
VDDIO
I/O
EXTINT[1]
-
-
-
-
-
-
SERCOM5/
PAD[1]
-
TCC2/
WO[1]
TCC0/ WO[5]
-
GCLK_IO[3]
CCL3/
OUT[3]
DIO4
PA10
VDDIO
I/O
EXTINT[10]
-
-
AIN[18]
-
X[2]
Y[8]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/
WO[0]
TCC0/ WO[2]
-
GCLK_IO[4]
CCL1/
IN[5]
DIO5
PB00
VDDANA
I/O
EXTINT[0]
-
-
AIN[8]
-
-
-
-
SERCOM5/
PAD[2]
TCC3/
WO[0]
-
-
SUPC_PSOK
CCL0/
IN[1]
RF_RST
PB15
VDDIO
I/O
EXTINT[15]
-
-
-
-
X[15]
-
SERCOM4/
PAD[3]
-
TCC0/
WO[1]
-
-
GCLK_IO[1]
CCL3/
IN[10]
MOSI
PB30
VDDIO
I/O
EXTINT[14]
-
-
-
-
-
-
-
SERCOM5/
PAD[0]
TCC0/
WO[0]
SERCOM4/
PAD[2]
-
-
-
SEL
PB31
VDDIO
I/O
EXTINT[15]
-
-
-
-
-
-
-
SERCOM5/
PAD[1]
TCC0/
WO[1]
SERCOM4/
PAD[1]
-
-
-
SCLK
PC18
VDDIO
I/O
-
-
-
-
-
-
-
-
-
-
SERCOM4/
PAD[3]
-
-
-
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 15
SAM R34/R35
I/O Multiplexing and Considerations
...........continued
Internal
Signal
I/O Pin
Supply
Type
A
EIC
MISO
PC19
VDDIO
I/O
-
B
RSTC
-
REF
-
ADC
-
AC
-
PTC
Xlines
PTC
-
-
C
D
E
F
G
H
I
SERCOM
SERCOMALT
TC/TCC
TCC/
SERCOM
COM
AC/GCLK/
SUPC
CCL
-
-
-
SERCOM4/
PAD[0]
-
-
-
Ylines
5.3
Other Functions
5.3.1
Oscillator Pinout
The oscillators are not mapped to the normal PORT functions, and their multiplexing is controlled by
registers in the Oscillator Controller (OSCCTROL) and in the 32kHz Oscillators Controller
(OSC32KCTRL).
Table 5-3. Oscillator Pinout
Oscillator
Supply
Signal
I/O Port
XOSC
VDDIO
XIN
PA14
XOUT
PA15
XIN32
PA00
XOUT32
PA01
XOSC32K
5.3.2
VSWOUT
Serial Wire Debug Interface Pins
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging
detection will automatically switch the SWDIO port to the SWDIO function.
Table 5-4. Serial Wire Debug Interface Pinout
5.3.3
Signal
Supply
I/O Pin
SWCLK
VDDIN
PA30
SWDIO
VDDIN
PA31
SERCOM I2C Pins
Table 5-5. SERCOM Pins Supporting I2C
Device
Pins Supporting I2C HS Mode
SAM R34/R35
PA08, PA09, PA13, PA16, PA17, PA22, PA23
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 16
SAM R34/R35
I/O Multiplexing and Considerations
5.3.4
GPIO Cluster
Table 5-6. GPIO Clusters
Package Cluster GPIO
64 Pins
5.3.5
Supply Pins Connected to
the Cluster
1
PA31 PA30 -
-
-
-
-
-
-
-
-
-
VDDIN C4/GND D4
2
PA28 PA27 PB23 PB22 -
-
-
-
-
-
-
-
-
VDDIN C4/GND D4 and
VDDIO C6/GND C5
3
PA25 PA24 PA23
PA22
-
-
PA19 PA18 PA17 PA16 PA15 PA14 PA13 VDDIO C6/GND C5 and
VDDIO F3/GND F4
4
-
PA09
PA08
-
-
-
-
-
-
-
-
-
VDDIO F3/GND F4
5
PA07 PA06 PA05
PA04
-
-
-
-
-
-
-
-
-
VDDANA C1/GNDANA C3
6
-
PA00
PB03 PB02 -
-
-
-
-
-
-
VDDANA C1/GNDANA C3
-
-
PA01
-
TCC Configurations
The SAML21 has three instances of the Timer/Counter for Control applications (TCC) peripheral,
TCC.
Table 5-7. TCC Configuration Summary
TCC Channels Waveform Counter Fault Dithering Output Dead
SWAP Pattern
No. (CC_NUM) Output
Size
Matrix Time
Generation
(WO_NUM)
Insertion
(DTI)
0
4
8
24-bit
Yes
Yes
Yes
Yes
Yes
Yes
1
2
4
24-bit
Yes
Yes
—
—
—
Yes
2
2
2
16-bit
Yes
—
—
—
—
Note: The number of CC register (CC_NUM)_ for each TCC corresponds to the number of compare/
capture channels to ensure that a TCC can have more Waveform Outputs (WO_NUM) than CC registers.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 17
SAM R34/R35
Signal Description
6.
Signal Description
This section provides the required information to understand the origin and the function of each such
signal. The nature of a SIP results in the situation where the package pins may be bonded to the
microcontroller die or the transceiver die. There are also signals bonded in-between the two dies.
6.1
Signal Details
This section provides the naming and functional description of the internal and external signals. 5. I/O
Multiplexing and Considerations describes the routing of these signals between the MCU core and
transceiver subsystem and to the external package pins.
Table 6-1. Signal Descriptions List
Signal Name
Function
Type
Analog Comparators (AC)
AIN
AC analog inputs
Analog
CMP
AC comparator outputs
Digital
Analog Digital Converter (ADC)
AIN
ADC analog inputs
Analog
VREFB
ADC voltage external reference B
Analog
External Interrupt Controller (EIC)
EXTINT
External interrupts inputs
Digital
NMI
External non-maskable interrupt input
Digital
Reset Controller (RSTC)
EXTWAKE External wake-up inputs
Digital
Generic Clock Generator (GCLK)
GCLK_IO
Generic clock (source clock inputs or generic clock generator output)
Digital
Custom Control Logic (CCL)
IN
Logic inputs
Digital
OUT
Logic outputs
Digital
Supply Controller (SUPC)
VBAT
External battery supply inputs
Analog
PSOK
Main power supply OK input
Digital
OUT
Logic outputs
Digital
Power Manager (PM)
RESETN
Active low Reset input
Digital
Serial Communication Interface (SERCOMx)
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 18
SAM R34/R35
Signal Description
...........continued
Signal Name
Function
Type
PAD
SERCOM Input/Output pads
Digital
Oscillators Control (OSCCTRL)
XIN
Crystal or external clock input
Analog/Digital
XOUT
Crystal output
Analog
32KHz Oscillators Control (OSC32KCTRL)
XIN32
32KHz crystal or external clock input
Analog/Digital
XOUT32
32KHz crystal output
Analog
Timer Counter (TCx)
WO
Waveform outputs
Digital
Timer Counter (TCCx)
WO
Waveform outputs
Digital
General Purpose I/O (PORT)
PA01-PA00
Parallel I/O controller I/O Port A
Digital
PA09-PA04
Parallel I/O controller I/O Port A
Digital
PA25-PA22
Parallel I/O controller I/O Port A
Digital
PA28-PA27
Parallel I/O controller I/O Port A
Digital
PA03-PB02
Parallel I/O controller I/O Port B
Digital
PA23-PB22
Parallel I/O controller I/O Port B
Digital
Universal Serial Bus (USB)
DP
DP for USB (SAM R34 only)
Digital
DM
DM for USB (SAM R34 only)
Digital
External RF Signals
RF_XTB
XTAL connection
OSC
RF_XTA
XTAL connection or TCXO input
OSC
VR_DIG
Regulated supply voltage for digital blocks
Reg Output
VBAT_ANA
Supply voltage for analog circuitry
Analog Power
VR_ANA
Regulated supply voltage for analog circuitry
Reg Output
RFI_LF
RF input for bands 2 and 3
RF Input
RFO_LF
RF output for bands 2 and 3
RF Output
PA_BOOST
Optional high-power PA output, all frequency bands
RF Output
VR_PA
Regulated supply voltage for the PA
Reg Output
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 19
SAM R34/R35
Signal Description
...........continued
Signal Name
Function
Type
VBAT_RF
Supply voltage for RF blocks
RF Power
RFO_HF
RF output for band 1
RF Output
VBAT_DIG
Supply voltage for digital blocks
Digital Power
RXTX
RX/TX switch control: High in TX
Digital I/O
RFI_HF
RF input for band 1
RF Input
Internal Interconnect Signals
DIO0
Digital I/O, software configured
I/O
DIO1/DCLK
Digital I/O, software configured
I/O
DIO2/DATA
Digital I/O, software configured
I/O
DIO3
Digital I/O, software configured
I/O
DIO4
Digital I/O, software configured
I/O
DIO5
Digital I/O, software configured
I/O
SCLK
SPI clock input
Input
MISO
SPI data output
Output
MOSI
SPI data input
Input
SEL
SPI chip select input
Input
RF_RST
Reset trigger input
I/O
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 20
SAM R34/R35
Processor and Architecture
7.
Processor and Architecture
7.1
Cortex M0+ Processor
The SAM R34/R35 contains an ATSAML21 Die Revision C ARM Cortex-M0+ processor. The processor is
based on the ARMv6 Architecture and Thumb®-2 ISA. The Cortex-M0+ is 100% instruction set
compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores.
The implemented ARM Cortex-M0+ is revision r0p1. For more information, refer to http://www.arm.com.
7.1.1
Cortex M0+ Configuration
Table 7-1. Cortex M0+ Configuration in SAM R34/R35
Features
Cortex M0+ options
SAM R34/R35 configuration
Interrupts
External interrupts 0-32
29
Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint
comparators
0, 1, 2
2
Number of breakpoint
comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Absent - All software run in
privileged mode only
Memory Protection Unit
Not present or 8-region
Not present
Reset all registers
Present or absent
Absent
Instruction fetch width
16-bit only or mostly 32-bit
32-bit
The ARM Cortex-M0+ core has two bus interfaces:
• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all
system memory including Flash memory and RAM
• Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores
7.1.1.1
Cortex M0+ Peripherals
• System Control Space (SCS)
– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical
Reference Manual for details (http://www.arm.com)
• Nested Vectored Interrupt Controller (NVIC)
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 21
SAM R34/R35
Processor and Architecture
– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software
can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely
coupled, providing low latency interrupt processing and efficient processing of late arriving
interrupts. Refer to the Cortex-M0+ Technical Reference Manual for details (http://
www.arm.com).
Note: When the CPU frequency is much higher than the APB frequency it is recommended to
insert a memory read barrier after each CPU write to registers mapped on the APB. Failing to do
so in such conditions may lead to unexpected behavior such as re-entering a peripheral interrupt
handler just after leaving it.
• System Timer (SysTick)
– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both
the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details
(http://www.arm.com).
• System Control Block (SCB)
– The System Control Block provides system implementation information, and system control. This
includes configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+
Devices Generic User Guide for details (http://www.arm.com)
• Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+
processor. Refer to section MTB-Micro Trace Buffer and the CoreSight MTB-M0+ Technical
Reference Manual for details (http://www.arm.com).
Related Links
7.2 Nested Vector Interrupt Controller
7.1.1.2
Cortex M0+ Address Map
Table 7-2. Cortex-M0+ Address Map
7.1.1.3
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)
0x41006000
Micro Trace Buffer (MTB)
I/O Interface
™
The device allows direct access to PORT registers. Accesses to the AMBA® AHB-Lite and the single
cycle I/O interface can be made concurrently, so the Cortex M0+ processor can fetch the next instructions
while accessing the I/Os. This enables single cycle I/O access to be sustained for as long as necessary.
7.2
Nested Vector Interrupt Controller
7.2.1
Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM R34/R35 supports 32 interrupt lines with four
different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (http://
www.arm.com).
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 22
SAM R34/R35
Processor and Architecture
7.2.2
Interrupt Line Mapping
Each of the 23 interrupt lines is connected to one peripheral instance, as shown in the table below. Each
peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear
(INTFLAG) register.
An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be
individually enabled by writing a 1 to the corresponding bit in the peripheral’s Interrupt Enable Set
(INTENSET) register, and disabled by writing 1 to the corresponding bit in the peripheral’s Interrupt
Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding
interrupt is enabled.
The interrupt requests for one peripheral are ORed together on system level, generating one interrupt
request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the
NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/
CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for
each interrupt.
Table 7-3. Interrupt Line Mapping
Peripheral Source
NVIC Line
EIC NMI – External Interrupt Controller
NMI
PM – Power Manager
0
MCLK - Main Clock
OSCCTRL - Oscillators Controller
OSC32KCTRL - 32KHz Oscillators Controller
SUPC - Supply Controller
PAC - Protecion Access Controller
WDT – Watchdog Timer
1
RTC – Real Time Counter
2
EIC – External Interrupt Controller
3
NVMCTRL – Non-Volatile Memory Controller
4
DMAC - Direct Memory Access Controller
5
USB - Universal Serial Bus
6
EVSYS – Event System
7
SERCOM0 – Serial Communication Interface 0
8
SERCOM1 – Serial Communication Interface 1
9
SERCOM2 – Serial Communication Interface 2
10
SERCOM3 – Serial Communication Interface 3
11
SERCOM4 – Serial Communication Interface 4
12
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 23
SAM R34/R35
Processor and Architecture
...........continued
Peripheral Source
NVIC Line
SERCOM5 – Serial Communication Interface 5
13
TCC0 – Timer Counter for Control 0
14
TCC1 – Timer Counter for Control 1
15
TCC2 – Timer Counter for Control 2
16
TC0 – Timer Counter 0
17
TC1 – Timer Counter 1
18
TC4 – Timer Counter 4
19
ADC – Analog-to-Digital Converter
20
AC – Analog Comparator
21
7.3
Micro Trace Buffer
7.3.1
Features
•
•
•
•
7.3.2
Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant
Overview
When enabled, the MTB records the changes in program flow that are reported by the Cortex-M0+
processor over the execution trace interface. This interface is shared between the Cortex-M0+ processor
and the CoreSight MTB-M0+. The information is stored by the MTB in the SRAM as trace packets. An offchip debugger can extract the trace information using the Debug Access Port to read the trace
information from the SRAM. The debugger can then reconstruct the program flow from this information.
The MTB stores trace information into the SRAM and gives the processor access to the SRAM
simultaneously. The MTB ensures that trace write accesses have priority over processor accesses.
An execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects a
non-sequential change of the program pounter (PC) value. A non-sequential PC change can occur during
branch instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual
for more details on the MTB execution trace packet format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various
ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical
Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s
MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a
specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the
watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around
overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM
Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTB-
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 24
SAM R34/R35
Processor and Architecture
M0+ Technical Reference Manual. The MTB has four programmable registers to control the behavior of
the trace features:
• POSITION: Contains the trace write pointer and the wrap bit
• MASTER: Contains the main trace enable bit and other trace control fields
• FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits
• BASE: Indicates where the SRAM is located in the processor memory map. This register is provided
to enable auto discovery of the MTB SRAM location by a debug agent
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
7.4
High-Speed Bus System
7.4.1
Features
High-Speed Bus Matrix has the following features:
•
•
•
•
Symmetric crossbar bus switch implementation
Allows concurrent accesses from different masters to different slaves
32-bit data bus
Operation at a one-to-one clock frequency with the bus masters
H2LBRIDGE has the following features:
• LP clock division support
• Write: Posted-write FIFO of 3 words, no bus stall until it is full
• Write: 1 cycle bus stall when full when LP clock is not divided
• 2 stall cycles on read when LP clock is not divided
• Ultra-Low Latency mode:
– Suitable when the HS clock frequency is not above half the maximum device clock frequency
– Removes all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)
– Enabled by writing a '1' in 0x41008120 using a 32-bit write access
L2HBRIDGE has the following features:
• LP clock division support
• Write: Posted-write FIFO of 1 word, no bus stall until it is full
• Write: 1 cycle bus stall when full when LP clock is not divided
• 2 stall cycles on read when LP clock is not divided
• Ultra-Low Latency mode:
– Suitable when the HS clock frequency is not above half the maximum device clock frequency
– Removes all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)
– Enabled by writing a '1' in 0x41008120 using a 32-bit write access
Figure 7-1. High-Speed Bus System Components
M M
H2LBRIDGES S
H2LBRIDGE
HMATRIXLP
HMATRIXHS
S S S S S
© 2019 Microchip Technology Inc.
M M
M H2LBRIDGEM
L2HBRIDGES M
L2HBRIDGE
Datasheet
S L2HBRIDGES
S S S S S S S S
DS70005356C-page 25
SAM R34/R35
Processor and Architecture
Configuration
Figure 7-2. Master-Slave Relations High-Speed Bus Matrix
High-Speed Bus
MASTERS
CM0+
0
DSU
1
L2HBRIDGEM
2
Internal Flash
HS SRAM PORT 0
HS SRAM PORT 1
AHB-APB Bridge B
H2LBRIDGES
High-Speed Bus SLAVES
0
1
2
3
4
Figure 7-3. Master-Slave Relations Low-Power Bus Matrix
H2LBRIDGEM
0
DMAC
2
AHB-APB Bridge A
AHB-APB Bridge C
AHB-APB Bridge D
AHB-APB Bridge E
LP SRAM PORT 2
LP SRAM PORT 1
L2HBRIDGES
HS SRAM PORT 2
Low-Power Bus SLAVES
Low-Power Bus
MASTERS
7.4.2
0
1
2
3
5
7
8
9
Table 7-4. High-Speed Bus Matrix Masters
High-Speed Bus Matrix Masters
Master ID
CM0+ - Cortex M0+ Processor
0
DSU - Device Service Unit
1
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 26
SAM R34/R35
Processor and Architecture
...........continued
High-Speed Bus Matrix Masters
Master ID
L2HBRIDGEM - Low-Power to High-Speed bus
matrix AHB to AHB bridge
2
Table 7-5. High-Speed Bus Matrix Slaves
High-Speed Bus Matrix Slaves
Slave ID
Internal Flash Memory
0
HS SRAM Port 0 - CM0+ Access
1
HS SRAM Port 1 - DSU Access
2
AHB-APB Bridge B
3
H2LBRIDGES - High-Speed to Low-Power bus
matrix AHB to AHB bridge
4
Table 7-6. Low-Power Bus Matrix Masters
Low-Power Bus Matrix Masters
Master ID
H2LBRIDGEM - High-Speed to Low-Power bus
matrix AHB to AHB bridge
0
DMAC - Direct Memory Access Controller - Data
Access
2
Table 7-7. Low-Power Bus Matrix Slaves
7.4.3
Low-Power Bus Matrix Slaves
Slave ID
AHB-APB Bridge A
0
AHB-APB Bridge C
1
AHB-APB Bridge D
2
AHB-APB Bridge E
3
LP SRAM Port 2- H2LBRIDGEM access
5
LP SRAM Port 1- DMAC access
7
L2HBRIDGES - Low-Power to High-Speed bus
matrix AHB to AHB bridge
8
HS SRAM Port 2- HMATRIXLP access
9
SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, priority
levels can be assigned to the masters for different types of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any
access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit
values for the QoS level configuration are shown in the following table.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 27
SAM R34/R35
Processor and Architecture
Table 7-8. Quality of Service
Value
Name
Description
0x0
DISABLE
Background (no sensitive
operation)
0x1
LOW
Sensitive Bandwidth
0x2
MEDIUM
Sensitive Latency
0x3
HIGH
Critical Latency
If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of
one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master
and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the
tables below for details.
The MTB has a fixed QoS level HIGH (0x3).
The CPU QoS level can be written/read, using 32-bit access only, at address 0x41008114 bits [1:0]. Its
reset value is 0x3.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).
Table 7-9. HS SRAM Port Connections QoS
HS SRAM Port Connection Port ID
Connection Type QoS
default QoS
MTB - Micro Trace Buffer
4
Direct
STATIC-3
0x3
USB - Universal Serial Bus
3
Direct
IP-QOSCTRL
0x3
HMATRIXLP - Low-Power
Bus Matrix
2
Bus Matrix
0x44000934(1), bits[1:0]
0x2
DSU - Device Service Unit
1
Bus Matrix
0x4100201C(1)
0x2
CM0+ - Cortex M0+
Processor
0
Bus Matrix
0x41008114(1), bits[1:0]
0x3
Note:
1. Using 32-bit access only.
Table 7-10. LP SRAM Port Connections QoS
LP SRAM Port Connection Port ID
Connection Type QoS
default QoS
DMAC - Direct Memory
Access Controller - WriteBack Access
5, 6
Direct
IP-QOSCTRL.WRBQOS
0x2
DMAC - Direct Memory
Access Controller - Fetch
Access
3, 4
Direct
IP-QOSCTRL.FQOS
0x2
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 28
SAM R34/R35
Processor and Architecture
...........continued
LP SRAM Port Connection Port ID
Connection Type QoS
default QoS
H2LBRIDGEM - HS to LP
bus matrix AHB to AHB
bridge
2
Bus Matrix
0x44000924(1), bits[1:0]
0x2
DMAC - Direct Memory
Access Controller - Data
Access
1
Bus Matrix
IP-QOSCTRL.DQOS
0x2
Note:
1. Using 32-bit access only.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 29
SAM R34/R35
Application Schematic Introduction
8.
Application Schematic Introduction
The SAM R34/R35 application schematic has to provide the environment for both integrated circuits
inside the package. The microcontroller as well as the radio have integrated LDOs to provide the required
core voltages. To achieve the full radio performance, the application layout has to take the noise
decoupling in-between the analog radio part and the digital processor and signal processing power
domains into account.
8.1
SAM R34/R35 Basic Application Schematic
The following application schematic shows the minimum circuit elements required for the SAM R34/R35
system. In this schematic, both the high-power PA_BOOST and high-efficiency RFO_HF transmitter
configurations are populated. Some applications may require only one transmitter configuration.
For unused pins, the default state of the pins will give the lowest current leakage. Thus, there is no need
to perform any configuration of the unused pins in order to lower the power consumption.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 30
rotatethispage90
U300
C316
100nF
VDD
GND
GND
RESET
B3
E2
B5
B7
D4
D6
B6
PA00_XIN32
PA01_XOUT32
A3
A4
D3
C4
E3
F3
F4
F5
F6
F8
G8
F7
E6
E7
E8
D8
D7
B8
C8
E4
C6
C5
D5
B4
C3
E5
C7
PA04_S0_UART_TX
PA05_S0_UART_RX
RFSW_PWR
BAND_SEL
PA30_SWDCLK
PA31_SWDIO
GNDANA
GNDANA
GND
GND
GND
GND
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
GND_RF
RESET
Datasheet
PA00
PA01
PA04
PA05
PA06
PA07
PA08
PA09
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA22
PA23
PA24
PA25
PA27
PA28
PA30
PA31
PB02
PB03
PB22
PB23
RFO_HF
RFI_HF
PA_BOOST
A2
B2
E1
F2
G2
G3
G5
G6
G7
H5
B1
A1
F1
XTA
C330
33pF
C311
100nF
GND
C312
100nF
GND
C313
100nF
GND
C314
100nF
GND
C340
4.7pF
GND
C315
100nF
DNP C321 DNP C300
DNF
DNF
GND
GND
VR_PA
NC
GND
VSW
VDDCORE
GND
GND
50Ohm
i
XC1
TYETBCSANF-32.000000
GND
A5
3
GND
L301
DNP
LQH3NPN100MJ0
C308
100nF
32 MHz TCXO
1
GND
C307
100nF
H4
VR_DIG
H2
VR_ANA
D1
VR_PA
OUTPUT
GND
C304
100nF
VDDANA
VCC
C303
100nF
A6
H8
VBAT_DIG
H3
VBAT_ANA
C1
VBAT_RF
2
VDDANA
VDD
G4
VDDIO1
A8
VDDIO2
A7
VDDIN
C2
VDDANA
4
VDD
100k
R300
VDD
RFO_HF
50Ohm
i
L300
VDDANA
RFSW_PWR
GND
BLM15AG121SN1D
C306
10uF
RFI_HF
50Ohm
i
PA_BOOST
C320
100nF
GND
GND
RFO_LF
RFI_LF
RXTX
G1
H1
D2
TXRX
H6
XTA
32 kHz Cr ystal
Y301
XTA
XTB
PA01_XOUT32
PA00_XIN32
H7
C309
10pF
SAMR34J18B
ANTENNA
ABS05-32.768KHZ-9-T
GND
C310
10pF
GND
SMA Antenna connector
C902
5.6pF
GND
DNP
DS70005356C-page 31
RFO_HF
50Ohm
i
50Ohm
50Ohm
i C910 i
L906
22pF
50Ohm
i
11nH
DNP
50Ohm
i
10nH
C911
3.9pF
GND
DNF
L907
DNF
L909
50Ohm
i
10
11
RFC
GND
GND
J3
GND
8
C905
50Ohm
i
GND
C914
1 nF
GND
RFI_HF
GND
C908
2.7pF
7
C916
3.3pF
50Ohm
i
L904
10nH
47pF
RFSW_PWR
C913
5.6pF
GND
50Ohm
i
9
10nH
C912
8.2pF
GND
3
J2
VDD
C915
J1
V2
GND
C909
GND
2
SKY13373-460LF
GND
V1
V2
0
0
Shutdown
RF Switch State
1
0
RFC to J2 (RFI_HF)
0
1
RFC to J1 (PA_BOOST)
1
1
RFC to J3 (RFO_HF)
GND
BAND_SEL
TXRX
1
3
5
7
9
2
4
6
8
10
HEADER 2x5
1310-1205SNS073R1
PA31_SWDIO
PA30_SWDCLK
RESET
SAM R34/R35
GND
1
C907
4.7nF
J303
VREF
GND
EP
L905
33nH
5
VDD
U900
VR_PA
DNP C906
DNF
GND
GND
13
GND
3
2
C903
3.3pF
6
GND
GND
Cor tex Debug Connector
GND
10nH
C917
3.3pF
J901
SMA Edge Mount
1
50Ohm
i
L901
10nH
18 pF
C901
3.9pF
L903
33nH
DNF
50Ohm
i
L902
5
2.2nH
50Ohm
i
12
C900
GND
50Ohm
i
V1
PA_BOOST
50Ohm
i
L900
Application Schematic Introduction
50Ohm
i
DNP
4
GND
C904
4
© 2019 Microchip Technology Inc.
Figure 8-1. SAM R34/R35 Basic Application Schematic
SAM R34/R35
Application Schematic Introduction
8.2
SAM R34/R35 Bill of Materials
Table 8-1. Bill of Materials for SAM R34/R35
Sl. No. Designator
Quantity Value
Manufacturer
MPN
Description
1
C303, C304, C307,
C308, C311, C312,
C313, C314, C315,
C316, C320
11
100nF
KEMET
C0201C104K9PACTU
CAP CER 0.1UF 6.3V 10% X5R 0201
2
C306
1
10uF
Murata
GRM155R60J106ME15
Ceramic capacitor, SMD 0402, X5R, 6.3V, 20%
3
C309, C310
2
10pF
TDK Corporation
C0603C0G1E100C
CAP CER 10PF 25V C0G 0201
4
C330
1
33pF
Johanson Technology
Inc.
250R05L330GV4T
Ceramic capacitor, SMD 0201, C0G/NP0, 25V,
+/-2%
5
C340
1
4.7pF
Johanson Technology
Inc.
250R05L4R7BV4T
Ceramic capacitor, SMD 0201, C0G/NP0, 25V,
+/-0.1pF
6
C900
1
18pF
Murata
GRM0335C1H180GA01D
CAP CER 18PF 50V C0G/NP0 0201 +/- 2%
7
C901, C911
2
3.9pF
Murata
GRM0335C1H3R9BA01D
CAP CER 3.9PF 50V C0G/NP0 0201, +/-0.1pF
8
C902, C913
2
5.6pF
Murata
GRM0335C1E5R6BA01D
CAP CER 5.6PF 25V 0201
9
C903, C916, C917
3
3.3pF
Johanson Technology
Inc.
250R05L3R3BV4T
Ceramic capacitor, SMD 0201, C0G/NP0, 25V,
+/-0.1pF
10
C905
1
47pF
Johanson Technology
Inc.
250R05L470GV4T
Ceramic capacitor, SMD 0201, C0G/NP0, 25V,
+/-2%
11
C907
1
4.7nF
Murata
GRM033R71A472KA01D
Ceramic capacitor, SMD 0201, X7R, 10V,
+/-10%
12
C908
1
2.7pF
Murata
GJM0335C1E2R7BB01E
Ceramic capacitor, SMD 0201, C0G/NP0, 25V,
+/-0.1pF
13
C910
1
22pF
Johanson Technology
Inc.
250R05L220GV4T
Ceramic capacitor, SMD 0201, C0G/NP0, 25V,
+/-2%
14
C912
1
8.2pF
Johanson Technology
Inc.
250R05L8R2CV4T
CAP CER 8.2PF 25V NP0 0201 ±0.25pF
15
C914
1
1nF
Murata
GRM033R71C102KA01D
Ceramic capacitor, SMD 0201, X7R, 16V, 0.1
16
J303
1
1310-1205SNS073R1
WCON Hardware
Electronics Co., Ltd
1310-1205SNS073R1
2x5 pin header, 1.27mm pitch, THM
17
J901
1
SMA Edge Mount
Cinch Connectivity
Solutions Johnson
142-0771-831
Cinch Connectivity Solutions Johnson 50 Ohms,
SMA Edge Mount Jack Receptacle
18
L300
1
BLM15AG121SN1D
Murata
BLM15AG121SN1D
Chip Bead, 120ohm@100Mhz, 0.55A, 0402,
Rdc 0.19ohm
19
L900
1
2.2nH
Murata
LQW15AN2N2C10D
FIXED IND 2.2NH 1A 27 MOHM SMD, +-0.2nH,
0201
20
L901, L902, L907,
L909
4
10nH
Murata
LQP03TN10NH02D
FIXED IND 10NH 250MA 700 MOHM, +-3%,
0201
21
L903, L905
2
33nH
Johanson Technology
Inc.
L-05B33NJV6T
RF Inductor, 33nH, +/-5%, Irms=0.2A,
Q=5@100Mhz, DCR=2.3(Max), SMD, 0201
22
L904
1
10nH
TDK Corporation
MLK0603L10NJT000
RF Inductor, 10nH, +/-5%, Irms=0.2A,
Q=6@300Mhz, DCR=0.8(Max), SMD, 0201
23
L906
1
11nH
Murata
LQP03HQ11NH02
FIXED IND 11NH 300MA 500 MOHM 0201
+/-3%
24
R300
1
100k
ASJ
CR10-1003-FK
Thick film resistor, SMD 0402, 1/16W, 1%
25
U300
1
SAMR34J18B
Microchip Technology
Inc.
ATSAMR34J18BT-I/7JX
SAMR34 BGA-64
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 32
SAM R34/R35
Application Schematic Introduction
...........continued
Sl. No. Designator
Quantity Value
Manufacturer
MPN
Description
26
U900
1
SKY13373-460LF
Skyworks Solutions
SKY13373-460LF
0.1-6.0GHZ SPT3 SWITCH
27
XC1
1
32MHz TCXO
Taitien
TYETBCSANF-32.000000 32MHz TCXO, 2.8 ~ 3.3V, Clipped sine wave
10kOhm/10pF, 2 x 1.6 mm SMD
28
Y301
1
ABS05-32.768KHZ-9-T —
© 2019 Microchip Technology Inc.
—
Datasheet
CRYSTAL 32.768KHz 9pF SMD ABS05
DS70005356C-page 33
SAM R34/R35
Transceiver Circuit Description
9.
Transceiver Circuit Description
Note: The SAM R34/R35 incorporates a LoRa transceiver.
The integrated Sub-GHz transceiver supports LoRa technology spread spectrum modulation, combining
ultra-long range communications and high interference immunity with extremely low current consumption.
Receive sensitivities of over -148 dBm can be achieved in narrowband modes, and -136 dBm in
LoRaWAN protocol compliant modes, using a low cost crystal and bill of materials.
The transmit section offers two integrated power amplifiers. The highly efficient RFO port delivers up to
+13 dBm for European regions and battery conservation. The high powered PA_BOOST port delivers a
regulated output of +17 dBm with low EMI across the entire working voltage range or, up to +20 dBm of
raw RF power with high-voltage supplies. This combination of high power and high RX sensitivity yields
industry leading link budget, making it ideal for any application requiring long range low-data-rate
communications. LoRa technology also provides significant advantages in both blocking and selectivity
over conventional modulation techniques, solving the traditional design compromise between range,
interference robustness and energy consumption. For maximum flexibility, the user may decide on the
spread spectrum modulation bandwidth (BW), spreading factor (SF), and forward error correction rate
(CR). Another benefit of the spread spectrum modulation is that each spreading factor is orthogonal, thus
multiple transmitted signals can occupy the same channel without interfering.
The SAM R34/R35 also supports high performance (G)FSK, (G)MSK, and OOK modes for systems
including WMBus and IEEE802.15.4g.
This transceiver offers bandwidth options ranging from 7.8 kHz to 500 kHz with spreading factors ranging
from 6 to 12, and covering all available frequency bands from 137 to 1020 MHz.
9.1
Transceiver Pin Description
Table 9-1. Description of Transceiver Signals Available Outside the Package
Name
Type
Description
RFI_LF
I
RF Input for Bands 2 and 3
RFO_LF
O
RF Output for Bands 2 and 3
VR_ANA
Supply
Regulated Supply Voltage for Analog Circuitry
VBAT_ANA
Supply
Supply Voltage for Analog Circuitry
VR_DIG
Supply
Regulated Supply Voltage for Digital Blocks
VBAT_DIG
Supply
Supply Voltage for Digital Blocks
XTA
I/O
XTAL Connection or TCXO Input
XTB
I/O
XTAL Connection
RXTX
O
RX/TX Switch Control: High in TX
RFI_HF
I
RF Input for Band 1
RFO_HF
O
RF Output for Band 1
VBAT_RF
Supply
Supply Voltage for RF Blocks
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 34
SAM R34/R35
Transceiver Circuit Description
...........continued
9.2
Name
Type
Description
VR_PA
Supply
Restricted Supply for the PA
PA_BOOST
O
Optional High Power PA Output, All Frequency Bands
Transceiver Validation
The SAM R34 transceiver has been extensively tested using LoRa modulation and FSK for European
and North American regions.
Validation of the SAM R34 device was performed at frequencies typically used in LoRa applications. The
test boards exhibited regulatory compliance for European and North American regions. ETSI 868MHz
ISM band was tested using the RFO_HF port. FCC 902-928MHz ISM band was tested using both the
RFO_HF and PA_BOOST ports. These configurations use the transceiver’s synthesizer in band 1.
At the time of publication of this data sheet, the RFO_LF port or SAM R34 is known to be functional but
has not been validated. RFO_LF transmits on 137-175MHz and 410-525MHz bands (synthesizer band 2
and band 3).
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 35
SAM R34/R35
Microcontroller Interface
10.
Microcontroller Interface
This section describes the transceiver to microcontroller interface. The interface is comprised of a slave
SPI and additional control signals. This interface is connected to a SAM L21 master interface as shown
below. The SERCOM4 and GPIO signals dedicated to the CPU-TRX interface are not externally exposed
and may not be used for any other purposes.
CAUTION
Do not use CPU OFF mode. The internal SPI connections do not have pull-up resistors and the
CPU OFF mode puts the SPI bus in a high-impedance state. The resulting metastable signals
may cause unpredictable transceiver behavior and increase the current consumption.
Figure 10-1. Microcontroller to Transceiver Interface
Transceiver
SAML21
SERCOM4
PAD2
PAD0
PAD3
PB31
/SEL
PB30
MOSI
PC19
MISO
PC18
SCK
PB17
DIO3
SPI SLAVE
EXTERNAL
INTERRUPT
CONTROLLER
EXTINT(1)
EXTINT (10)
EXTINT (0)
EXTINT (0)
EXTINT (11)
EXTINT (12)
PA10
DIO4
PB00
DIO5
PB16
DIO0
PA11
DIO1/DCLK
PA12
DIO2/DATA
PB15
nRST
CONTROL
LOGIC
SERCOM2
PAD0
PAD3
PORT
The SPI is used for register, Frame Buffer, and SRAM access. The additional control signals are
connected to the GPIO/IRQ interface of the microcontroller. The table below introduces the radio
transceiver I/O signals and their functionalities.
Table 10-1. Microcontroller Interface Signal Description
TRX Signal
CPU Signal Name
Description
/SEL
PB31
SPI select signal, active-low
MOSI
PB30
SPI data (master output slave input) signal
MISO
PC19
SPI data (master input slave output) signal
SCLK
PC18
SPI clock signal
nRST
PB15
Transceiver Reset signal, Active-low
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 36
SAM R34/R35
Microcontroller Interface
...........continued
TRX Signal
CPU Signal Name
Description
DIO0
PB16
Digital I/O, software configured
DIO1
PA11
Digital I/O, software configured
DIO2
PA12
Digital I/O, software configured
DIO3
PB17
Digital I/O, software configured
DIO4
PA10
Digital I/O, software configured
DIO5
PB00
Digital I/O, software configured
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 37
SAM R34/R35
Electrical Characteristics
11.
Electrical Characteristics
Note: All the specifications are typical (TYP), unless otherwise stated.
11.1
Absolute Maximum Ratings
Stresses beyond those listed in following table may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 11-1. Absolute Maximum Ratings
Symbol Description
Min.
Max.
Units
VDD
Power supply voltage
0
3.8
V
VPIN
Pin voltage with respect to GND and VDD
GND-0.6V VDD+0.6V V
VDD MAX=3.6V
PRF
Input RF level
-
+10
dBm
Tstorage
Storage temperature
-50
150
°C
TLEAD
T=10s
-
260
°C
(soldering profile compliant with IPC/JEDEC J STD 020B)
CAUTION
11.2
This device is sensitive to electrostatic discharges (ESD). Improper handling may lead to
permanent performance degradation or malfunctioning. Handle the device following best
practice ESD protection rules: Be aware that the human body can accumulate charges large
enough to impair functionality or destroy the device.
General Operating Conditions
The device must operate within the ratings listed in the following table in order for all other electrical
characteristics and typical characteristics of the device to be valid.
For unused pins, the default state of the pins gives the lowest current leakage. Thus, specific
configuration is not required for the unused pins in order to lower the power consumption.
Table 11-2. General Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Units
VDDIN
Power supply voltage
1.8
3.3
3.63
V
VDDIO
IO Supply Voltage
1.8
3.3
3.63
V
VDDANA
Analog supply voltage
1.8
3.3
3.63
V
TA
Temperature range
-40
25
85
°C
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 38
SAM R34/R35
Electrical Characteristics
...........continued
Symbol
Description
Min.
Typ.
Max.
Units
TJ
Junction temperature
-
-
100
°C
CAUTION
11.3
In debugger Cold-Plugging mode, NVM erase operations are not protected by the BOD33 and
BOD12. NVM erase operation at supply voltages below specified minimum can cause
corruption of NVM areas that are mandatory for correct device behavior.
Performance Characteristics
The following data shows SAM R34/R35 performance as a combined system including both the SAML21
and the transceiver under the following conditions:
• Modulation = LoRa
• VCC = 3.3 VDC
• Temperature = 25°C
• FRF_XTA = 32.000000 MHz +/- 1 ppm (TCXO)
•
•
•
•
•
•
•
•
•
DFLL = 48 MHz
BW = 125 kHz
SF = 12
EC = 4/6
PER = 1%
CRC = ENABLED
Payload = 64 Bytes
Preamble = 12 symbols
Matched Impedance
Estimates for ACTIVE state of the SAML21 are derived using the CoreMark benchmarking algorithm, a
48 MHz DFLL clock and 3.3 VDC supply. These are intended to show a conservative estimate of power
consumption. Results are related to CPU activity, clock speed and temperature and may be improved
with optimization.
11.3.1
Method of Derivation
Combined specifications in this data sheet are derived from the published data sheets of the components.
See Reference Documents [1] and [5]. For example, the Line Current in TX Mode entry for RFO_HF +13
dBm is 32.5 mA. This is calculated using the IDDT_L current in LoRa Receiver Specification Table 10 of
[5] and the Active Current Consumption Table 46-7 of [1] for the operational conditions shown below.
Table 11-3. TRX TX Current Derivation
Condition
Value
Unit
Bandwidth
125
kHz
Carrier Frequency
868
MHz
CRC
ENABLED
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 39
SAM R34/R35
Electrical Characteristics
...........continued
Condition
Value
Unit
Error Correction Code
4/6
Fxosc
32
Impedances
MATCHED
Packet Error rate
1
%
Payload Length
64
Bytes
Preamble Length
12
Symbols
RF Output Power
+13
dBm
RF Port
RFO_HF
Spreading Factor
12
Supply Voltage
3.3
VDC
Temperature
25
Celsius
IDDT_L
28
mA (TYP)
Condition
Value
Unit
Bandwidth
125
kHz
Carrier Frequency
868
MHz
CRC
ENABLED
Error Correction Code
4/6
Fxosc
32
Impedances
MATCHED
LNA Boost
OFF
Packet Error rate
1
%
Payload Length
64
Bytes
Preamble Length
12
Symbols
RF Port
RFI_HF
Spreading Factor
12
Supply Voltage
3.3
VDC
Temperature
25
Celsius
IDDR_L
10.3
mA (TYP)
MHz
Table 11-4. TRX RX Current Derivation
© 2019 Microchip Technology Inc.
Datasheet
MHz
DS70005356C-page 40
SAM R34/R35
Electrical Characteristics
Table 11-5. CPU Current Derivation
CPU Contribution
Conditions
Value
Unit
Clock
DFLL 48
MHz
Benchmark Algorithm
COREMARK
-
Current/MHz
95
uA/MHz
Mode
ACTIVE
-
PL
PL2
-
Regulator
LDO
-
Supply Voltage (VDC)
3.3
V
I_CPU
4.5
mA (TYP)
Using the contributions above the total combined current consumption is calculated as follows:
• I_TOTALTX = IDDT_L + I_CPU = 28 + 4.5 mA = 32.5 mA
• I_TOTALRX = IDDR_L + I_CPU = 10.3 + 4.5 mA = 14.8 mA
11.3.2
Line Current in TX Mode
Table 11-6. Line Current in Tx Mode
11.3.3
Output Mode
I_CPU
IDDT_L
I_TOTAL
Unit
RFO_LF +13 dBm
4.5
28
32.5
mA (TYP)
PA_BOOST +17 dBm
4.5
90
94.5
mA (TYP)
Line Current in Receive Mode
Table 11-7. Line Current in Receive Mode
11.3.4
Frequency MHz
I_CPU
IDDR_L
I_TOTAL
Unit
915
4.5
10.3
14.8
mA (TYP)
868
4.5
10.3
14.8
mA (TYP)
433
4.5
11.5
15.8
mA (TYP)
Line Current in Low-Power Modes
Table 11-8. Line Current in Low-Power Modes
State
CPU Mode
I_CPU
TRX Mode
IDDSL
TOTAL
Units
IDLE
ACTIVE
4.5
SLEEP
0.0002
4.5
mA (TYP)
STANDBY
STANDBY
1.2
SLEEP
0.2
1.4
µA (TYP)
SLEEP
BACKUP
590
SLEEP
200
790
nA (TYP)
1.
Do Not Use CPU OFF mode. See 10. Microcontroller Interface for details.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 41
SAM R34/R35
Electrical Characteristics
11.3.5
11.3.6
11.3.7
Transmitter Output Power
Table 11-9. Transmitter Output Power in LoRa Mode
Frequency (MHz)
Output Port
Typical Output Power (dBm)
915
PA_BOOST
17
915
RFO_HF
13
868
PA_BOOST
17
868
RFO_HF
13
433
PA_BOOST
17
433
RFO_LF
13
Transmitter Phase Noise
Table 11-10. Phase Noise
Offset
Phase Noise (dBc/Hz)
10k
-103
50k
-103
400k
-115
1M
-122
Receiver Sensitivity
Table 11-11. Receiver Sensitivity in LoRa Mode
Frequency (MHz)
BW (kHz)
SF
Sensitivity
Unit
915
125
11
-133
dBm
868
125
11
-133
dBm
433
7.8
12
-148
dBm
Note: The above results are obtained with TCXO.
11.3.8
Blocking
Table 11-12. Blocking
11.3.9
Frequency (MHz)
1 MHz
2 MHz
10 MHz
Unit
915
71
76
84
dB (TYP)
868
71
76
84
dB (TYP)
433
71
72
78
dB (TYP)
Transmitter High Power Operation
To operate in the +20 dBm High-Power mode high voltage must be supplied to VDDANA. For some
regions, additional EMI filtering may be needed at high power.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 42
SAM R34/R35
Electrical Characteristics
Table 11-13. High-Power Operational Parameters
Parameter
Value
RF Output Power
+20 dBm MAX
Output Port
PA_BOOST F1
VDDANA (Min.)
2.4 VDC
VDDANA (Max.)
3.6 VDC
Typical Line Current
120 mA
Max. Duty Cycle
1% MAX
VSWR
3:1 MAX
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 43
SAM R34/R35
SAM R34/R35 Package Information
12.
SAM R34/R35 Package Information
12.1
Package Drawings
Figure 12-1. Package Drawings of SAM R34/R35
64-Lead Thin, Fine Pitch Ball Grid Array Package (7JX) - 6x6 mm Body [TFBGA]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
6.00
NOTE 1
A
B
6.00
(DATUM B)
(DATUM A)
2X
0.15 C
2X
TOP VIEW
0.15 C
0.20 C
C
SEATING
PLANE
A2
A
64X
A1
SIDE VIEW
0.10 C
(L)
e
A1 BALL PAD CORNER
(L)
64X Øb
0.15
0.08
e
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-443A Sheet 1 of 2
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 44
SAM R34/R35
SAM R34/R35 Package Information
12.2
SAM R34/R35 Land Pattern
PCB layout pattern for SAM R34/R35 64-Pin BGA is shown below.
Figure 12-2. SAM R34/R35 Land Pattern
64-Lead Thin, Fine Pitch Ball Grid Array Package (7JX) - 6x6 mm Body [TFBGA]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
C2
SILK SCREEN
ØX
E
G
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Diameter (X64)
X
Space Between Pads
G
MIN
MILLIMETERS
NOM
0.65 BSC
4.55
4.55
MAX
0.40
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2433A
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 45
SAM R34/R35
Best Practices for Designers
13.
13.1
Best Practices for Designers
Introduction
This chapter outlines best practices for design and review of SAM R34/R35 designs. This chapter
illustrates the recommended power supply connections, how to connect external analog references,
programmer, debugger, oscillator, and crystal.
13.1.1
Electromagnetic Compliance
Best practices for RF designs are beyond the scope of this document. There are several good application
notes listed in the Reference Documentation section. Actual results may vary because of system factors
like enclosures, PCBA design, incidental resonant structures, co-existence with other RF energy sources,
regulatory and regional requirements. The designer must balance these factors and verify with laboratory
measurements. Testing emissions early in the design cycle is strongly encouraged. Typical best practices
include 4-layer PCB construction, generous ground planes and stitching vias for noise suppression and
counterpoise, separation of RF and digital ground-domains, controlled-impedance transmission lines and
passive components rated for radio frequency operation. Baseband techniques include placing
decoupling capacitors very close to the power pins and an RC-filter on the RESET pin; in addition, a pullup resistor on the SWCLK pin is critical for reliable operations.
13.1.2
Operation in Noisy Environment
If the device is operating in an environment with much electromagnetic noise, it must be protected from
the noise to ensure reliable operation. In particular, placing decoupling capacitors very close to the power
pins, a RC-filter on the RESET pin, and a pull-up resistor on the SWCLK pin is critical for reliable
operations. It is also relevant to eliminate or attenuate noise in order to avoid that it reaches supply pins,
I/O pins and crystals.
13.2
Power Supply
The SAM R34/R35 supports a single or dual power supply from 1.8 to 3.6 VDC. The same voltage must
be applied to both VDDIN and VDDANA.
The internal voltage regulator has three different modes:
• Linear mode: this mode does not require any external inductor. This is the default mode when CPU
and peripherals are running
• Low Power (LP) mode: This is the default mode used when the chip is in Standby mode
• Shutdown mode: When the chip is in Backup mode, the internal regulator is turned off
13.2.1
Power Supply Connections
The following figures show the recommended power supply connections for Switched/Linear mode,
Linear mode only and with battery backup.
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 46
SAM R34/R35
Best Practices for Designers
Figure 13-1. Power Supply Connection for Linear Mode Only
Close to device
(for every pin)
IO Supply
(1.62V — 3.63V)
SAM R34
VBAT (PB03)
VDDIO
Main Supply
(1.8V — 3.6VDC)
VDDANA
VDDIN
100nF
10µF
10µF
100nF
VSW
100nF
10µF
VDDCORE
1µF
100nF
GND
GNDANA
Figure 13-2. Power Supply Connection for Battery Backup
Close to device
(for every pin)
IO Supply
(1.62V — 3.63V)
SAM R34
VDDIO
VBAT (PB03)
Main Supply
(1.62V — 3.63V)
VDDANA
VDDIN
100nF
10µH
100nF
100nF
10µF
10µF
VSW
10µF
VDDCORE
1µF
100nF
GND
GNDANA
© 2019 Microchip Technology Inc.
Datasheet
DS70005356C-page 47
SAM R34/R35
Best Practices for Designers
Table 13-1. Power Supply Connections, VDDCORE or VSW From Internal Regulator
Signal Name Recommended Pin Connection
Description
VDDIO
Digital supply voltage
1.8 to 3.6 VDC
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Decoupling/filtering inductor 10µH(1)(3)
VDDANA
1.8 to 3.6 VDC
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Analog supply voltage
Ferrite bead(4) prevents the VDD noise interfering with
VDDANA
VDDIN
1.8 to 3.6 VDC
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Digital supply voltage
Decoupling/filtering inductor 10µH(1)(3)
VBAT
1.8 to 3.5 VDC when connected
External battery supply input
VDDCORE
0.9V to 1.2V typical
Decoupling/filtering capacitors 100nF(1)(2) and 1µF(1)
Linear Regulator mode: Core
supply voltage output/ external
decoupling pin
Switched Regulator mode:
Core supply voltage input, must
be connected to VSW via
inductor
VSW
Switching Regulator mode: 10 µH inductor with
saturation current above 150mA and DCR
工商网监
湘ICP备2023018690号
