SAM E70/S70/V70/V71
32-bit Arm Cortex-M7 MCUs with FPU, Audio and Graphics
Interfaces, High-Speed USB, Ethernet, and Advanced
Analog
Features
Core
• Arm® Cortex®-M7 running at up to 300 MHz
• 16 Kbytes of I-Cache and 16 Kbytes of D-Cache with Error Code Correction (ECC)
• Single-precision and double-precision HW Floating Point Unit (FPU)
• Memory Protection Unit (MPU) with 16 zones
• DSP Instructions, Thumb®-2 Instruction Set
• Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU)
Memories
• Up to 2048 Kbytes embedded Flash with unique identifier and user signature for user-defined data
• Up to 384 Kbytes embedded Multi-port SRAM
• Tightly Coupled Memory (TCM)
• 16 Kbytes ROM with embedded Bootloader routines (UART0, USB) and IAP routines
• 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR and NAND Flash
with on-the-fly scrambling
System
• Embedded voltage regulator for single-supply operation
• Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog for safe operation
• Quartz or ceramic resonator oscillators: 3 MHz to 20 MHz main oscillator with failure detection, 12 MHz or 16
MHz needed for USB operations. Optional low-power 32.768 kHz for RTC or device clock
• RTC with Gregorian calendar mode, waveform generation in low-power modes
• RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency variations
• 32-bit low-power Real-time Timer (RTT)
• High-precision Main RC oscillator with 12 MHz default frequency
• 32.768 kHz crystal oscillator or Slow RC oscillator as source of low-power mode device clock (SLCK)
• One 500 MHz PLL for system clock, one 480 MHz PLL for USB high-speed operations
• Temperature Sensor
• One dual-port 24-channel central DMA Controller (XDMAC)
Low-Power Features
• Low-power sleep, wait and backup modes, with typical power consumption down to 1.1 μA in Backup mode with
RTC, RTT and wakeup logic enabled
• Ultra low-power RTC and RTT
• 1 Kbyte of backup RAM (BRAM) with dedicated regulator
Peripherals
• One Ethernet MAC (GMAC) 10/100 Mbps in MII mode and RMII with dedicated DMA. IEEE® 1588 PTP
frames and 802.3az Energy-efficiency support. Ethernet AVB support with IEEE802.1AS Timestamping and
IEEE802.1Qav credit-based traffic-shaping hardware support.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 1
SAM E70/S70/V70/V71
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
USB 2.0 Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-Kbyte FIFO, up to 10 bidirectional endpoints,
dedicated DMA
12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
Two host Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes,
time-triggered and event-triggered transmission
MediaLB® device with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks
Three USARTs, USART0, USART1, USART2, support LIN mode, ISO7816, IrDA®, RS-485, SPI, Manchester
and Modem modes; USART1 supports LON mode.
Five 2-wire UARTs with SleepWalking™ support
Three Two-Wire Interfaces (TWIHS) (I2C-compatible) with SleepWalking support
Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256 MB Flash and with eXecute-In-Place and
on-the-fly scrambling
Two Serial Peripheral Interfaces (SPI)
One Serial Synchronous Controller (SSC) with I2S and TDM support
Two Inter-IC Sound Controllers (I2SC)
One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
Four Three-Channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare and PWM modes, constant
on time. Quadrature decoder logic and 2-bit Gray Up/Down Counter for stepper motor
Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM
for motor control, two external triggers to manage power factor correction (PFC), DC-DC and lighting control
Two Analog Front-End Controllers (AFEC), each supporting up to 12 channels with differential input mode
and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7 Msps. Offset and gain error
correction feature.
One 2-channel, 12-bit, 1 Msps-per-channel Digital-to-Analog Controller (DAC) with Differential and Over
Sampling modes
One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis
Cryptography
• True Random Number Generator (TRNG)
• AES: 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications
• Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and SHA256.
I/O
• Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering and
On-die Series Resistor Termination
• Five Parallel Input/Output Controllers (PIO)
Voltage
• Single supply voltage from 3.0V to 3.6V for Qualification AEC - Q100 Grade 2 Devices
• Single Supply voltage from 1.7V to 3.6V for Industrial Temperature Devices
Packages
• LQFP144, 144-lead LQFP, 20x20 mm, pitch 0.5 mm
• LFBGA144, 144-ball LFBGA, 10x10 mm, pitch 0.8 mm
• TFBGA144, 144-ball TFBGA, 10x10 mm, pitch 0.8 mm
• UFBGA144, 144-ball UFBGA, 6x6 mm, pitch 0.4 mm
• LQFP100, 100-lead LQFP, 14x14 mm, pitch 0.5 mm
• TFBGA100, 100-ball TFBGA, 9x9 mm, pitch 0.8 mm
• VFBGA100, 100-ball VFBGA, 7x7 mm, pitch 0.65 mm
• LQFP64, 64-lead LQFP, 10x10 mm, pitch 0.5 mm
• QFN64, 64-pad QFN 9x9 mm, pitch 0.5 mm with wettable flanks
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 2
SAM E70/S70/V70/V71
Table of Contents
Features......................................................................................................................................................... 1
1.
Configuration Summary........................................................................................................................ 13
2.
Ordering Information............................................................................................................................. 15
3.
Block Diagram.......................................................................................................................................16
4.
Signal Description................................................................................................................................. 20
5.
Automotive Quality Grade..................................................................................................................... 27
6.
Package and Pinout.............................................................................................................................. 28
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
7.
Power Considerations........................................................................................................................... 43
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
8.
Power Supplies.......................................................................................................................... 43
Power Constraints...................................................................................................................... 43
Voltage Regulator.......................................................................................................................44
Backup SRAM Power Switch..................................................................................................... 44
Active Mode................................................................................................................................45
Low-power Modes...................................................................................................................... 45
Wakeup Sources........................................................................................................................ 47
Fast Startup................................................................................................................................47
Input/Output Lines.................................................................................................................................48
8.1.
8.2.
8.3.
8.4.
9.
144-lead Packages.....................................................................................................................28
144-lead Package Pinout........................................................................................................... 29
100-lead Packages.....................................................................................................................35
100-lead Package Pinout........................................................................................................... 36
64-lead Package........................................................................................................................ 39
64-lead Package Pinout............................................................................................................. 39
General-Purpose I/O Lines.........................................................................................................48
System I/O Lines........................................................................................................................ 48
NRST Pin................................................................................................................................... 50
ERASE Pin................................................................................................................................. 50
Interconnect.......................................................................................................................................... 51
10. Product Mapping................................................................................................................................... 52
11. Memories.............................................................................................................................................. 53
11.1. Embedded Memories................................................................................................................. 53
11.2. External Memories..................................................................................................................... 59
12. Event System........................................................................................................................................ 60
12.1. Embedded Characteristics......................................................................................................... 60
12.2. Real-time Event Mapping........................................................................................................... 60
13. System Controller..................................................................................................................................64
13.1. System Controller and Peripherals Mapping..............................................................................64
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 3
SAM E70/S70/V70/V71
13.2. Power-on-Reset, Brownout and Supply Monitor........................................................................ 64
13.3. Reset Controller......................................................................................................................... 64
14. Peripherals............................................................................................................................................ 65
14.1. Peripheral Identifiers.................................................................................................................. 65
14.2. Peripheral Signal Multiplexing on I/O Lines................................................................................67
15. Arm Cortex-M7 .....................................................................................................................................68
15.1. Arm Cortex-M7 Configuration.....................................................................................................68
16. Debug and Test Features......................................................................................................................69
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
Description................................................................................................................................. 69
Embedded Characteristics......................................................................................................... 69
Associated Documents...............................................................................................................69
Debug and Test Block Diagram..................................................................................................70
Debug and Test Pin Description................................................................................................. 70
Application Examples................................................................................................................. 71
Functional Description................................................................................................................72
17. SAM-BA Boot Program......................................................................................................................... 76
17.1.
17.2.
17.3.
17.4.
17.5.
17.6.
Description................................................................................................................................. 76
Embedded Characteristics......................................................................................................... 76
Hardware and Software Constraints.......................................................................................... 76
Flow Diagram............................................................................................................................. 76
Device Initialization.....................................................................................................................77
SAM-BA Monitor.........................................................................................................................77
18. Fast Flash Programming Interface (FFPI).............................................................................................81
18.1. Description................................................................................................................................. 81
18.2. Embedded Characteristics......................................................................................................... 81
18.3. Parallel Fast Flash Programming............................................................................................... 81
19. Bus Matrix (MATRIX).............................................................................................................................89
19.1.
19.2.
19.3.
19.4.
Description................................................................................................................................. 89
Embedded Characteristics......................................................................................................... 89
Functional Description................................................................................................................91
Register Summary......................................................................................................................95
20. USB Transmitter Macrocell Interface (UTMI)...................................................................................... 112
20.1. Description................................................................................................................................112
20.2. Embedded Characteristics....................................................................................................... 112
20.3. Register Summary....................................................................................................................113
21. Chip Identifier (CHIPID).......................................................................................................................116
21.1. Description................................................................................................................................116
21.2. Embedded Characteristics....................................................................................................... 116
21.3. Register Summary....................................................................................................................118
22. Enhanced Embedded Flash Controller (EEFC).................................................................................. 123
22.1. Description............................................................................................................................... 123
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 4
SAM E70/S70/V70/V71
22.2.
22.3.
22.4.
22.5.
Embedded Characteristics....................................................................................................... 123
Product Dependencies............................................................................................................. 123
Functional Description..............................................................................................................123
Register Summary....................................................................................................................141
23. Supply Controller (SUPC)................................................................................................................... 149
23.1.
23.2.
23.3.
23.4.
23.5.
Description............................................................................................................................... 149
Embedded Characteristics....................................................................................................... 149
Block Diagram.......................................................................................................................... 150
Functional Description..............................................................................................................151
Register Summary....................................................................................................................162
24. Watchdog Timer (WDT).......................................................................................................................173
24.1.
24.2.
24.3.
24.4.
24.5.
Description............................................................................................................................... 173
Embedded Characteristics....................................................................................................... 173
Block Diagram.......................................................................................................................... 173
Functional Description..............................................................................................................174
Register Summary....................................................................................................................176
25. Reinforced Safety Watchdog Timer (RSWDT).................................................................................... 181
25.1.
25.2.
25.3.
25.4.
25.5.
Description............................................................................................................................... 181
Embedded Characteristics....................................................................................................... 181
Block Diagram.......................................................................................................................... 182
Functional Description..............................................................................................................182
Register Summary....................................................................................................................184
26. Reset Controller (RSTC)..................................................................................................................... 189
26.1.
26.2.
26.3.
26.4.
Description............................................................................................................................... 189
Embedded Characteristics....................................................................................................... 189
Block Diagram.......................................................................................................................... 189
Functional Description..............................................................................................................190
27. Real-time Clock (RTC)........................................................................................................................ 200
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
Description............................................................................................................................... 200
Embedded Characteristics....................................................................................................... 200
Block Diagram.......................................................................................................................... 200
Product Dependencies............................................................................................................. 201
Functional Description..............................................................................................................201
Register Summary....................................................................................................................209
28. Real-time Timer (RTT)........................................................................................................................ 227
28.1.
28.2.
28.3.
28.4.
28.5.
Description............................................................................................................................... 227
Embedded Characteristics....................................................................................................... 227
Block Diagram.......................................................................................................................... 227
Functional Description..............................................................................................................227
Register Summary....................................................................................................................230
29. General Purpose Backup Registers (GPBR)...................................................................................... 236
29.1. Description............................................................................................................................... 236
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 5
SAM E70/S70/V70/V71
29.2. Embedded Characteristics....................................................................................................... 236
29.3. Register Summary....................................................................................................................237
30. Clock Generator.................................................................................................................................. 239
30.1.
30.2.
30.3.
30.4.
30.5.
30.6.
30.7.
Description............................................................................................................................... 239
Embedded Characteristics....................................................................................................... 239
Block Diagram.......................................................................................................................... 240
Slow Clock................................................................................................................................240
Main Clock................................................................................................................................241
PLLA Clock...............................................................................................................................245
UTMI PLL Clock....................................................................................................................... 246
31. Power Management Controller (PMC)................................................................................................ 247
31.1. Description............................................................................................................................... 247
31.2. Embedded Characteristics....................................................................................................... 247
31.3. Block Diagram.......................................................................................................................... 248
31.4. Host Clock Controller............................................................................................................... 248
31.5. Processor Clock Controller.......................................................................................................248
31.6. SysTick External Clock.............................................................................................................248
31.7. USB Full-speed Clock Controller..............................................................................................249
31.8. Core and Bus Independent Clocks for Peripherals.................................................................. 249
31.9. Peripheral and Generic Clock Controller..................................................................................249
31.10. Asynchronous Partial Wakeup................................................................................................ 250
31.11. Free-running Processor Clock.................................................................................................252
31.12. Programmable Clock Output Controller.................................................................................. 252
31.13. Fast Startup.............................................................................................................................252
31.14. Startup from Embedded Flash................................................................................................ 254
31.15. Main Crystal Oscillator Failure Detection................................................................................ 254
31.16. 32.768 kHz Crystal Oscillator Frequency Monitor...................................................................255
31.17. Recommended Programming Sequence................................................................................ 255
31.18. Clock Switching Details...........................................................................................................257
31.19. Register Write Protection........................................................................................................ 260
31.20. Register Summary.................................................................................................................. 262
32. Parallel Input/Output Controller (PIO)................................................................................................. 314
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
Description............................................................................................................................... 314
Embedded Characteristics....................................................................................................... 314
Block Diagram.......................................................................................................................... 315
Product Dependencies............................................................................................................. 316
Functional Description..............................................................................................................316
Register Summary....................................................................................................................329
33. External Bus Interface.........................................................................................................................390
33.1.
33.2.
33.3.
33.4.
33.5.
Description............................................................................................................................... 390
Embedded Characteristics....................................................................................................... 390
EBI Block Diagram................................................................................................................... 391
I/O Lines Description................................................................................................................ 391
Application Example.................................................................................................................392
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 6
SAM E70/S70/V70/V71
34. Static Memory Controller (SMC)......................................................................................................... 396
34.1. Description............................................................................................................................... 396
34.2. Embedded Characteristics....................................................................................................... 396
34.3. I/O Lines Description................................................................................................................ 396
34.4. Multiplexed Signals.................................................................................................................. 397
34.5. Product Dependencies............................................................................................................. 397
34.6. External Memory Mapping....................................................................................................... 397
34.7. Connection to External Devices............................................................................................... 398
34.8. Application Example.................................................................................................................401
34.9. Standard Read and Write Protocols.........................................................................................403
34.10. Scrambling/Unscrambling Function........................................................................................ 410
34.11. Automatic Wait States............................................................................................................. 411
34.12. Data Float Wait States............................................................................................................ 414
34.13. External Wait...........................................................................................................................417
34.14. Slow Clock Mode.................................................................................................................... 421
34.15. Asynchronous Page Mode...................................................................................................... 423
34.16. Register Summary.................................................................................................................. 426
35. DMA Controller (XDMAC)................................................................................................................... 438
35.1.
35.2.
35.3.
35.4.
35.5.
35.6.
35.7.
35.8.
35.9.
Description............................................................................................................................... 438
Embedded Characteristics....................................................................................................... 438
Block Diagram.......................................................................................................................... 439
DMA Controller Peripheral Connections.................................................................................. 439
Functional Description..............................................................................................................441
Linked List Descriptor Operation.............................................................................................. 444
XDMAC Maintenance Software Operations............................................................................. 449
XDMAC Software Requirements..............................................................................................449
Register Summary....................................................................................................................451
36. Image Sensor Interface.......................................................................................................................496
36.1.
36.2.
36.3.
36.4.
36.5.
36.6.
Description............................................................................................................................... 496
Embedded Characteristics....................................................................................................... 497
Block Diagram.......................................................................................................................... 497
Product Dependencies............................................................................................................. 497
Functional Description..............................................................................................................498
Register Summary....................................................................................................................507
37. GMAC - Ethernet MAC........................................................................................................................541
37.1.
37.2.
37.3.
37.4.
37.5.
37.6.
37.7.
37.8.
Description............................................................................................................................... 541
Embedded Characteristics....................................................................................................... 541
Block Diagram.......................................................................................................................... 542
Signal Interface........................................................................................................................ 542
Product Dependencies............................................................................................................. 543
Functional Description..............................................................................................................543
Programming Interface.............................................................................................................569
Register Summary....................................................................................................................574
38. USB High-Speed Interface (USBHS).................................................................................................. 713
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 7
SAM E70/S70/V70/V71
38.1.
38.2.
38.3.
38.4.
38.5.
38.6.
38.7.
Description............................................................................................................................... 713
Embedded Characteristics....................................................................................................... 713
Block Diagram.......................................................................................................................... 714
Signal Description.................................................................................................................... 714
Product Dependencies............................................................................................................. 714
Functional Description..............................................................................................................715
Register Summary....................................................................................................................737
39. High-Speed Multimedia Card Interface (HSMCI)................................................................................ 885
39.1. Description............................................................................................................................... 885
39.2. Embedded Characteristics....................................................................................................... 885
39.3. Block Diagram.......................................................................................................................... 886
39.4. Application Block Diagram....................................................................................................... 886
39.5. Pin Name List........................................................................................................................... 887
39.6. Product Dependencies............................................................................................................. 887
39.7. Bus Topology............................................................................................................................887
39.8. High-Speed Multimedia Card Operations.................................................................................889
39.9. SD/SDIO Card Operation......................................................................................................... 898
39.10. CE-ATA Operation...................................................................................................................898
39.11. HSMCI Boot Operation Mode..................................................................................................899
39.12. HSMCI Transfer Done Timings............................................................................................... 900
39.13. Register Write Protection........................................................................................................ 901
39.14. Register Summary.................................................................................................................. 902
40. Serial Peripheral Interface (SPI)......................................................................................................... 931
40.1.
40.2.
40.3.
40.4.
40.5.
40.6.
40.7.
40.8.
Description............................................................................................................................... 931
Embedded Characteristics....................................................................................................... 931
Block Diagram.......................................................................................................................... 932
Application Block Diagram....................................................................................................... 932
Signal Description.................................................................................................................... 933
Product Dependencies............................................................................................................. 933
Functional Description..............................................................................................................933
Register Summary....................................................................................................................946
41. Quad Serial Peripheral Interface (QSPI).............................................................................................963
41.1.
41.2.
41.3.
41.4.
41.5.
41.6.
41.7.
Description............................................................................................................................... 963
Embedded Characteristics....................................................................................................... 963
Block Diagram.......................................................................................................................... 964
Signal Description.................................................................................................................... 964
Product Dependencies............................................................................................................. 964
Functional Description..............................................................................................................965
Register Summary....................................................................................................................981
42. Two-wire Interface (TWIHS)..............................................................................................................1003
42.1.
42.2.
42.3.
42.4.
42.5.
Description............................................................................................................................. 1003
Embedded Characteristics..................................................................................................... 1003
List of Abbreviations............................................................................................................... 1004
Block Diagram........................................................................................................................ 1004
I/O Lines Description.............................................................................................................. 1004
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 8
SAM E70/S70/V70/V71
42.6. Product Dependencies........................................................................................................... 1005
42.7. Functional Description............................................................................................................1005
42.8. Register Summary..................................................................................................................1042
43. Synchronous Serial Controller (SSC)................................................................................................1069
43.1.
43.2.
43.3.
43.4.
43.5.
43.6.
43.7.
43.8.
43.9.
Description............................................................................................................................. 1069
Embedded Characteristics..................................................................................................... 1069
Block Diagram........................................................................................................................ 1070
Application Block Diagram..................................................................................................... 1070
SSC Application Examples.....................................................................................................1070
Pin Name List......................................................................................................................... 1072
Product Dependencies........................................................................................................... 1072
Functional Description............................................................................................................1073
Register Summary..................................................................................................................1084
44. Inter-IC Sound Controller (I2SC)....................................................................................................... 1112
44.1.
44.2.
44.3.
44.4.
44.5.
44.6.
44.7.
44.8.
Description..............................................................................................................................1112
Embedded Characteristics......................................................................................................1112
Block Diagram.........................................................................................................................1113
I/O Lines Description...............................................................................................................1113
Product Dependencies............................................................................................................1113
Functional Description............................................................................................................ 1114
I2SC Application Examples.....................................................................................................1118
Register Summary..................................................................................................................1122
45. Universal Synchronous Asynchronous Receiver Transceiver (USART)........................................... 1137
45.1.
45.2.
45.3.
45.4.
45.5.
45.6.
45.7.
Description..............................................................................................................................1137
Features................................................................................................................................. 1137
Block Diagram........................................................................................................................ 1139
I/O Lines Description.............................................................................................................. 1139
Product Dependencies........................................................................................................... 1140
Functional Description............................................................................................................ 1140
Register Summary..................................................................................................................1188
46. Universal Asynchronous Receiver Transmitter (UART).................................................................... 1260
46.1.
46.2.
46.3.
46.4.
46.5.
46.6.
Description............................................................................................................................. 1260
Embedded Characteristics..................................................................................................... 1260
Block Diagram........................................................................................................................ 1260
Product Dependencies........................................................................................................... 1261
Functional Description............................................................................................................1261
Register Summary..................................................................................................................1270
47. Media Local Bus (MLB).....................................................................................................................1284
47.1.
47.2.
47.3.
47.4.
47.5.
47.6.
Description............................................................................................................................. 1284
Embedded Characteristics..................................................................................................... 1285
Block Diagram........................................................................................................................ 1285
Signal Description.................................................................................................................. 1286
Product Dependencies........................................................................................................... 1286
Functional Description............................................................................................................1287
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 9
SAM E70/S70/V70/V71
47.7. Register Summary..................................................................................................................1328
48. Controller Area Network (MCAN)......................................................................................................1362
48.1.
48.2.
48.3.
48.4.
48.5.
48.6.
Description............................................................................................................................. 1362
Embedded Characteristics..................................................................................................... 1362
Block Diagram........................................................................................................................ 1363
Product Dependencies........................................................................................................... 1363
Functional Description............................................................................................................1364
Register Summary..................................................................................................................1389
49. Timer Counter (TC)........................................................................................................................... 1449
49.1.
49.2.
49.3.
49.4.
49.5.
49.6.
49.7.
Description............................................................................................................................. 1449
Embedded Characteristics..................................................................................................... 1449
Block Diagram........................................................................................................................ 1450
Pin List....................................................................................................................................1451
Product Dependencies........................................................................................................... 1451
Functional Description............................................................................................................1451
Register Summary..................................................................................................................1473
50. Pulse Width Modulation Controller (PWM)........................................................................................1505
50.1.
50.2.
50.3.
50.4.
50.5.
50.6.
50.7.
Description............................................................................................................................. 1505
Embedded Characteristics..................................................................................................... 1505
Block Diagram........................................................................................................................ 1507
I/O Lines Description.............................................................................................................. 1507
Product Dependencies........................................................................................................... 1508
Functional Description............................................................................................................1509
Register Summary..................................................................................................................1549
51. Analog Front-End Controller (AFEC)................................................................................................ 1613
51.1.
51.2.
51.3.
51.4.
51.5.
51.6.
51.7.
Description............................................................................................................................. 1613
Embedded Characteristics..................................................................................................... 1613
Block Diagram........................................................................................................................ 1614
Signal Description.................................................................................................................. 1614
Product Dependencies........................................................................................................... 1615
Functional Description............................................................................................................1615
Register Summary..................................................................................................................1631
52. Digital-to-Analog Converter Controller (DACC).................................................................................1665
52.1.
52.2.
52.3.
52.4.
52.5.
52.6.
52.7.
Description............................................................................................................................. 1665
Embedded Characteristics..................................................................................................... 1665
Block Diagram........................................................................................................................ 1666
Signal Description.................................................................................................................. 1666
Product Dependencies........................................................................................................... 1667
Functional Description............................................................................................................1667
Register Summary..................................................................................................................1673
53. Analog Comparator Controller (ACC)............................................................................................... 1689
53.1. Description............................................................................................................................. 1689
53.2. Embedded Characteristics..................................................................................................... 1689
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 10
SAM E70/S70/V70/V71
53.3.
53.4.
53.5.
53.6.
53.7.
Block Diagram........................................................................................................................ 1689
Signal Description.................................................................................................................. 1690
Product Dependencies........................................................................................................... 1690
Functional Description............................................................................................................1690
Register Summary..................................................................................................................1692
54. Integrity Check Monitor (ICM)........................................................................................................... 1703
54.1.
54.2.
54.3.
54.4.
54.5.
54.6.
Description............................................................................................................................. 1703
Embedded Characteristics..................................................................................................... 1704
Block Diagram........................................................................................................................ 1704
Product Dependencies........................................................................................................... 1705
Functional Description............................................................................................................1705
Register Summary..................................................................................................................1718
55. True Random Number Generator (TRNG)........................................................................................1737
55.1.
55.2.
55.3.
55.4.
55.5.
55.6.
Description............................................................................................................................. 1737
Embedded Characteristics..................................................................................................... 1737
Block Diagram........................................................................................................................ 1737
Product Dependencies........................................................................................................... 1737
Functional Description............................................................................................................1738
Register Summary..................................................................................................................1739
56. Advanced Encryption Standard (AES).............................................................................................. 1746
56.1.
56.2.
56.3.
56.4.
56.5.
Description............................................................................................................................. 1746
Embedded Characteristics..................................................................................................... 1746
Product Dependencies........................................................................................................... 1746
Functional Description............................................................................................................1747
Register Summary..................................................................................................................1758
57. Electrical Characteristics for SAM V70/V71...................................................................................... 1778
57.1. Absolute Maximum Ratings....................................................................................................1778
57.2. DC Characteristics................................................................................................................. 1779
57.3. Power Consumption............................................................................................................... 1784
57.4. Oscillator Characteristics........................................................................................................1788
57.5. PLLA Characteristics..............................................................................................................1792
57.6. PLLUSB Characteristics.........................................................................................................1792
57.7. USB Transceiver Characteristics............................................................................................1793
57.8. AFE Characteristics................................................................................................................1793
57.9. Analog Comparator Characteristics....................................................................................... 1801
57.10. Temperature Sensor..............................................................................................................1801
57.11. 12-bit DAC Characteristics.................................................................................................... 1802
57.12. Embedded Flash Characteristics.......................................................................................... 1804
57.13. Timings .................................................................................................................................1805
58. Electrical Characteristics for SAM E70/S70...................................................................................... 1825
58.1.
58.2.
58.3.
58.4.
Absolute Maximum Ratings....................................................................................................1825
DC Characteristics................................................................................................................. 1826
Power Consumption............................................................................................................... 1831
Oscillator Characteristics........................................................................................................1835
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 11
SAM E70/S70/V70/V71
58.5. PLLA Characteristics..............................................................................................................1839
58.6. PLLUSB Characteristics.........................................................................................................1839
58.7. USB Transceiver Characteristics............................................................................................1840
58.8. AFE Characteristics................................................................................................................1840
58.9. Analog Comparator Characteristics....................................................................................... 1848
58.10. Temperature Sensor..............................................................................................................1848
58.11. 12-bit DAC Characteristics.................................................................................................... 1849
58.12. Embedded Flash Characteristics.......................................................................................... 1851
58.13. Timings..................................................................................................................................1852
59. Schematic Checklist..........................................................................................................................1873
59.1. Power Supplies...................................................................................................................... 1873
59.2. General Hardware Recommendations................................................................................... 1879
59.3. Boot Program Hardware Constraints..................................................................................... 1890
60. Marking............................................................................................................................................. 1891
61. Packaging Information...................................................................................................................... 1892
61.1. LQFP144, 144-lead LQFP......................................................................................................1892
61.2. LFBGA144, 144-ball LFBGA.................................................................................................. 1893
61.3. TFBGA144, 144-ball TFBGA..................................................................................................1896
61.4. UFBGA144, 144-ball UFBGA.................................................................................................1898
61.5. LQFP100, 100-lead LQFP......................................................................................................1900
61.6. TFBGA100, 100-ball TFBGA..................................................................................................1901
61.7. VFBGA100, 100-ball VFBGA................................................................................................. 1903
61.8. LQFP64, 64-lead LQFP..........................................................................................................1904
61.9. QFN64, 64-pad QFN ............................................................................................................. 1905
61.10. Soldering Profile....................................................................................................................1905
62. Revision History................................................................................................................................ 1907
The Microchip Website.............................................................................................................................1941
Product Change Notification Service........................................................................................................1941
Customer Support.................................................................................................................................... 1941
Microchip Devices Code Protection Feature............................................................................................ 1941
Legal Notice............................................................................................................................................. 1941
Trademarks.............................................................................................................................................. 1942
Quality Management System................................................................................................................... 1942
Worldwide Sales and Service...................................................................................................................1943
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 12
SAM E70/S70/V70/V71
Configuration Summary
1.
Configuration Summary
The SAM E70/S70/V70/V71 devices differ in memory size, package and features. The following tables summarize
the different configurations.
Table 1-1. SAM V71 Family Features (With CAN-FD, Ethernet AVB and Media LB)
Analog
USART/UART
QSPI
USART/SPI
TWIHS
HSMCI port/bits
CAN-FD
Ethernet AVB
Media LB
Image Sensor Interface (ISI)
SPI0
SPI1
External Bus Interface (EBI)
DMA Channels
SSC
ETM
Timer Counter Channels
Timer Counter Channels I/O
I2SC
I/O Pins
12-bit ADC Channels
Analog Comparators
DAC (Channels)
256
USB (see Note)
512
1024
Packages
Multi-port SRAM Memory (KB)
ATSAMV71Q19
ATSAMV71Q20
Device
Pins
Flash Memory (KB)
Digital Peripherals
144
LQFP,
TFBGA
HS
3/5
Y
3
3
1/4
2
MII,
RMII
Y
12 bit
Y
Y
Y
24
Y
Y
12
36
2
114
24
Y
2
100
LQFP,
TFBGA
HS
3/5
Y
3
3
1/4
2
MII,
RMII
Y
12 bit
Y
N
N
24
Y
Y
12
9
1
75
10
Y
2
64
LQFP
-
2/3
SPI
only
0
2
N
1
RMII
Y
8-bit
N
N
N
24
Y
Y
12
3
0
44
5
Y
1
384
ATSAMV71Q21
2048
ATSAMV71N19
512
ATSAMV71N20
1024
256
384
ATSAMV71N21
2048
ATSAMV71J19
512
ATSAMV71J20
1024
256
384
ATSAMV71J21
2048
Note: HS = High-Speed and FS = Full-Speed.
Table 1-2. SAM E70 Family Features (With CAN-FD and Ethernet AVB)
Analog
USART/SPI
TWIHS
HSMCI port/bits
CAN-FD
Ethernet AVB
Image Sensor Interface (ISI)
SPI0
SPI1
External Bus Interface (EBI)
DMA Channels
SSC
ETM
Timer Counter Channels
Timer Counter Channels I/O
I2SC
I/O Pins
12-bit ADC Channels
Analog Comparators
DAC (Channels)
1024
QSPI
ATSAME70Q20
USART/UART
256
USB (see Note)
512
Packages
Multi-port SRAM Memory (KB)
ATSAME70Q19
Pins
Device
Flash Memory (KB)
Digital Peripherals
144
LQFP,
LFBGA,
UFBGA
HS
3/5
Y
3
3
1/4
2
MII,
RMII
12 bit
Y
Y
Y
24
Y
Y
12
36
2
114
24
Y
2
100
LQFP,
TFBGA
HS
3/5
Y
3
3
1/4
2
MII,
RMII
12 bit
Y
N
N
24
Y
Y
12
9
1
75
10
Y
2
64
LQFP
-
2/3
SPI
only
0
2
N
1
RMII
8-bit
N
N
N
24
Y
Y
12
3
0
44
5
Y
1
384
ATSAME70Q21
2048
ATSAME70N19
512
ATSAME70N20
1024
256
384
ATSAME70N21
2048
ATSAME70J19
512
ATSAME70J20
1024
256
384
ATSAME70J21
2048
Note: HS = High-Speed and FS = Full-Speed.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 13
SAM E70/S70/V70/V71
Configuration Summary
Table 1-3. SAM V70 Family Features (With CAN-FD, Without Ethernet Control)
Analog
SPI0
SPI1
External Bus Interface (EBI)
DMA Channels
SSC
ETM
Timer Counter Channels
Timer Counter Channels I/O
I2SC
I/O Pins
12-bit ADC Channels
Analog Comparators
DAC (Channels)
384
Image Sensor Interface (ISI)
256
1024
CAN-FD
512
ATSAMV70J20
Media LB
ATSAMV70J19
HSMCI port/bits
384
TWIHS
256
1024
USART/SPI
512
ATSAMV70N20
QSPI
ATSAMV70N19
USART/UART
256
384
USB (see Note
512
1024
Packages
ATSAMV70Q19
ATSAMV70Q20
Pins
Device
Multi-port SRAM Memory (KB)
Flash Memory (KB)
Digital Peripherals
144
LQFP,
TFBGA
HS
3/5
Y
3
3
1/4
Y
2
12 bit
Y
Y
Y
24
Y
Y
12
36
2
114
24
Y
2
100
LQFP,
TFBGA
HS
3/5
Y
3
3
1/4
Y
2
12 bit
Y
N
N
24
Y
Y
12
9
1
75
10
Y
2
64
LQFP
-
2/3
SPI
only
0
2
N
N
1
8-bit
N
N
N
24
Y
Y
12
3
0
44
5
Y
1
Note: HS = High-Speed and FS = Full-Speed.
Table 1-4. SAM S70 Family Features (Without CAN-FD, Ethernet AVB and Media LB)
Analog
USART/SPI
TWIHS
HSMCI port/bits
Image Sensor Interface (ISI)
SPI0
SPI1
External Bus Interface (EBI)
DMA Channels
SSC
ETM
Timer Counter Channels
Timer Counter Channels I/O
I2SC
I/O Pins
12-bit ADC Channels
Analog Comparators
DAC Channels
1024
QSPI
ATSAMS70Q20
USART/UART
256
USB (see Note)
512
Packages
Multi-port SRAM Memory (KB)
ATSAMS70Q19
Pins
Device
Flash Memory (KB)
Digital Peripherals
144
LQFP,
LFBGA,
UFBGA
HS
3/5
Y
3
3
1/4
12 bit
Y
Y
Y
24
Y
Y
12
36
2
114
24
Y
2
100
LQFP,
TFBGA,
VFBGA
HS
3/5
Y
3
3
1/4
12 bit
Y
N
N
24
Y
Y
12
9
1
75
10
Y
2
64
LQFP, QFN
HS (for
QFN
only)
0/5
SPI
only
0
2
N
8-bit
N
N
N
24
Y
Y
12
3
0
44
5
Y
1
384
ATSAMS70Q21
2048
ATSAMS70N19
512
ATSAMS70N20
1024
256
384
ATSAMS70N21
2048
ATSAMS70J19
512
ATSAMS70J20
1024
256
384
ATSAMS70J21
2048
Note: HS = High-Speed and FS = Full-Speed.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 14
SAM E70/S70/V70/V71
Ordering Information
2.
Ordering Information
ATSAM V71 Q 21 B - ANB
Product Family
Package Carrier (If Applicable)
SAM = SMART ARM Microcontroller
Product Series
T = Tape and Reel
Temperature Operating Range
N = Industrial (-40 - +105°C)
B = Grade 2 (-40 - +105°C)
V71 = Cortex-M7 + Advanced Feature Set
+ Ethernet + up to 2 CAN-FD + Media LB
V70 = Cortex-M7 + Advanced Feature Set
+ up to 2 CAN-FD + Media LB
E70 = Cortex-M7 + Advanced Feature Set
+ Ethernet + up to 2 CAN-FD
S70 = Cortex-M7 + Advanced Feature Set
Package Type
A = LQFP
AA = LQFP (1)
C = LFBGA/TFBGA
CF = UFBGA/VFBGA
M = QFN
Pin Count
J = 64 pins
N = 100 pins
Q = 144 pins
Device Variant
Flash Memory Density
A = Revision A, legacy version
B = Revision B, current variant
21 = 2048 KB
20 = 1024 KB
19 = 512 KB
Note:
1. LQFP package type for Grade 2 variants.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 15
SAM E70/S70/V70/V71
Block Diagram
Block Diagram
Refer to the table 1. Configuration Summary for detailed configurations of memory size, package and features of the
SAM E70/S70/V70/V71 devices.
C
YN
IS
I_
IS D[1
I_ 1
PC :0
K, ]
IS
I_
M
IS
C
I_
K
H
SY
N
C
,I
SI
_V
S
O
IO
VD
D
VD
D
U
T
JT
C
AG LK
SE
L
D
IO
AC
ES
SW
TC
K/
R
SW
/T
S/
TD
O
TM
TD
I
TR
AC
TR EC
AC LK
ED
0.
.3
W
O
A[
23
:
N 0],
W D
N AIT [15
AN , N :0
D CS ]
O 0
E, ..
N 3,
A2
AN N
1
DW RD
A2 /NA
,
E NW
2/ ND
A0 NA AL
E
/N ND E
A1 LB CL
6, , N E
U
A1 B
7
Q
SC
Q K,
M Q
O
Q S CS
M I/Q
Q ISO IO
IO /Q 0
2. IO
.3 1
H
SD
H M
SD
P
Figure 3-1. SAM S70 144-pin Block Diagram
System Controller
TST
XIN
XOUT
Voltage
Regulator
3-20 MHz
Crystal
Oscillator
PCK0..2
Serial Wire Debug/JTAG Boundary Scan
4/8/12 MHz
RC Oscillator
PMC
Transceiver
UPLL
ETM
NVIC
PLLA
ERASE
WKUP0..13
Cortex-M7 Processor
fMAX 300 MHz
16 Kbytes DCache + ECC
SUPC
32 kHz
Crystal
Oscillator
XIN32
XOUT32
Backup RAM
1 Kbyte
32 kHz
RC Oscillator
Immediate Clear
256-bit SRAM
(GPBR)
RTCOUT0
RTCOUT1
RTC
RTT
VDDIO
POR
ITCM
DTCM
Flash
Unique ID
External Bus Interface
TCM SRAM
USBHS
ISI
XIP
DMA
DMA
XDMA
M
M
24-channel
XDMA
AXI Bridge
M
M
M
S
S
ROM
S
S
S
S
M
M
DMA
12-layer Bus Matrix
fMAX 150 MHz
S
Boot
Program
NRST
WDT
S
RSWDT
Peripheral Bridge
SM
QSPI
NAND Flash Logic
2048 Kbytes
1024 Kbytes
512 Kbytes
128–384 Kbytes
0–256 Kbytes
AHBS
AXIM
Static Memory Controller (SMC)
Flash
0–256 Kbytes
System RAM
16 Kbytes ICache + ECC
AHBP
RSTC
VDDPLL
VDDCORE
TCM
Interface
FPU
MPU
Backup
Multi-port
SRAM
In-Circuit Emulator
TPIU
M
ICM/SHA
PIOA/B/C/D/E
XDMA
3x
TWIHS
XDMA
5x
UART
XDMA
3x
USART
XDMA
PIO
XDMA
XDMA
2x
SPI
SSC
XDMA
HSMCI
XDMA
2x
I2SC
XDMA
4x
TC
XDMA
2x
PWM
XDMA
XDMA
2x
12-bit
AFE
ACC
12-bit
DAC
XDMA
AES
TRNG
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DA
C
0
DA ..1
TR
G
EF
N
VR
EF
P
VR
SP
I
SP x_M
Ix IS
S _M O
SP PIx O
Ix _S SI
_N P
PC CK
S0
..3
M
C
M CK
C
M CD
C
DA A
I2
SC 0..3
x
I2 _M
S C
I2 Cx_ K
SC C
x K
I2 _W
SC S
I2 x
SC _D
x_ I
D
O
TC
L
TI K0.
O .1
A
TI 0. 1
O .1
PW
B0 1
M
..1
1
PW Cx_
M PW
PW PW Cx M
M M _PW H0.
C C
x_ x_ M .3
PW PW L0
.
M M .3
EX FI
AF TR 0..2
E G
AF x_A 0..1
Ex D
_A TR
D G
0.
.1
1
TD
R
D
TK
R
K
TF
R
F
R
X
U D0
TX ..
D 4
0.
.4
SC
K
TX 0..
D 2
R 0.
XD .2
R 0..
D
TS 2
SR
R 0. CT 0..2
I0 .2 S
..2 , D 0
, D T ..2
C R0
D ..2
0
P ..2
PI IO
O DC
D 0
C ..
E 7
PI N1
O
.
D .2
C
C
LK
U
0.
.
K0 2
..2
Temp Sensor
TW
TW D
C
3.
DS60001527G-page 16
SAM E70/S70/V70/V71
Block Diagram
IS
I_
IS D[1
I_ 1
IS PC :0]
I_ K
H ,I
SY S
I_
G
TX NC MC
G CK , IS K
T ,
I_
G XE GR VS
C R X
Y
R ,
G S, GT CK NC
R G X ,
X
G
G ER CO DV RE
R , L
FC
G X0 GR , G
K
M ..3 X C
D
R
G C, , G DV SD
TS G TX
V
U M 0.
C D .3
O IO
C
M
A
P
C NR
AN X0
TX ..1
0.
.1
U
IO
O
D
VD
D
K/
TC
VD
SW
T
JT
C
LK
AG
SE
L
ES
/T
R
S/
SW
O
I
TM
TD
TD
D
AC
AC
TR EC
AC LK
ED
0.
.3
TR
IO
W
O
A[
23
:
N 0],
W D
N AIT [15
AN ,
:0
D NC ]
O S
E, 0.
N .3,
A2
AN N
1/
DW RD
A2 NA
E , NW
2 N
A0 /NA DAL
E
/N ND E
A1 LB CL
,
6, N E
A1 UB
7
Q
SC
Q K,
M Q
O
Q S CS
M I/Q
Q ISO IO
IO /Q 0
2. IO
.3 1
H
SD
H M
SD
P
Figure 3-2. SAM E70 144-pin Block Diagram
System Controller
TST
XIN
XOUT
Voltage
Regulator
3-20 MHz
Crystal
Oscillator
PCK0..2
Serial Wire Debug/JTAG Boundary Scan
4/8/12 MHz
RC Oscillator
PMC
Transceiver
ERASE
MPU
Backup
SUPC
32 kHz
Crystal
Oscillator
32 kHz
RC Oscillator
RTCOUT0
RTCOUT1
RTC
VDDIO
POR
Backup RAM
1 Kbyte
ITCM
DTCM
TCM SRAM
0–256 Kbytes
System RAM
16 Kbytes ICache + ECC
AHBP
AXIM
Immediate Clear
256-bit SRAM
(GPBR)
Flash
Unique ID
External Bus Interface
Static Memory Controller (SMC)
Flash
2048 Kbytes
1024 Kbytes
512 Kbytes
USBHS
ISI
DMA
DMA
M
M
GMAC
MII/RMII
2x
MCAN
FIFO
XIP
XDMA
128–384 Kbytes
0–256 Kbytes
AHBS
QSPI
NAND Flash Logic
DMA
DMA
AXI Bridge
RTT
M
M
M
S
S
S
ROM
RSTC
S
S
WDT
S
RSWDT
Peripheral Bridge
SM
S
M
M M
DMA
M
PIOA/B/C/D/E
XDMA
3x
TWIHS
XDMA
5x
UART
XDMA
3x
USART
XDMA
PIO
XDMA
XDMA
2x
I2SC
SSC
XDMA
HSMCI
XDMA
XDMA
2x
SPI
4x
TC
XDMA
2x
PWM
XDMA
XDMA
2x
12-bit
AFE
ACC
12-bit
DAC
XDMA
AES
TRNG
and its subsidiaries
DA
C
0
DA ..1
TR
G
EF
N
VR
EF
P
VR
SC
x
I2 _M
S C
I2 Cx_ K
SC C
x K
I2 _W
S
I2 Cx S
SC _D
x_ I
D
M O
C
M CK
C
M CD
C
DA A
0.
.3
SP
I
SP x_M
Ix IS
SP _M O
SP Ix O
Ix _S SI
_N P
PC CK
S0
..3
TC
LK
TI 0.
O .1
TI A0. 1
O .1
PW
B0 1
M
..1
1
PW Cx_
P
M
W
PW PW Cx M
M M _PW H0.
C C
x_ x_ M .3
PW PW L0
.
M M .3
EX FI
0
AF TR ..2
E G0
AF x_A ..1
Ex D
_A TR
D G
0.
.1
1
I2
TD
R
D
TK
R
K
TF
R
F
R
X
U D0
TX ..
D 4
0.
.4
SC
K
TX 0..
D 2
R 0.
XD .2
RT 0..
D
SR
S 2
R 0. CT 0..2
I0 .2 S
..2 , D 0
, D T ..2
R
C 0
D ..2
0
P ..2
PI IOD
O C
D 0
C ..
EN 7
PI
O 1..2
D
C
C
LK
U
TW
TW D
0
C ..2
K0
..2
Temp Sensor
© 2022 Microchip Technology Inc.
Complete Data Sheet
24-channel
XDMA
M
12-layer Bus Matrix
fMAX 150 MHz
S
Boot
Program
NRST
VDDPLL
VDDCORE
TCM
Interface
FPU
16 Kbytes DCache + ECC
WKUP0..13
XIN32
XOUT32
Cortex-M7 Processor
fMAX 300 MHz
ETM
NVIC
PLLA
Multi-port
SRAM
In-Circuit Emulator
TPIU
UPLL
DS60001527G-page 17
ICM/SHA
SAM E70/S70/V70/V71
Block Diagram
YN
C
M
L
M BC
L L
M BS K
LB IG
DA
T
IS
I_
IS D[1
I_ 1
IS PC :0]
I_ K
H ,I
SY S
N I_M
C
IS K
I_
VS
U
O
D
VD
D
TC
K/
VD
SW
IO
T
JT
C
LK
AG
SE
L
ES
IO
D
R
AC
/T
S/
SW
TM
TD
O
TD
I
TR
AC
TR EC
AC LK
ED
0.
.3
W
O
A[
23
:
N 0],
W D
N AIT [15
AN ,
:0
D NC ]
O S
E, 0.
N .3,
A2
AN N
1/
DW RD
A2 NA
E , NW
2 N
A0 /NA DAL
E
/N ND E
A1 LB CL
,
6, N E
A1 UB
7
Q
SC
Q K,
M Q
O
Q S CS
M I/Q
Q ISO IO
IO /Q 0
2. IO
.3 1
H
SD
H M
SD
P
Figure 3-3. SAM V70 144-pin Block Diagram
System Controller
TST
XIN
XOUT
Voltage
Regulator
3-20 MHz
Crystal
Oscillator
PCK0..2
Serial Wire Debug/JTAG Boundary Scan
4/8/12 MHz
RC Oscillator
PMC
Transceiver
ERASE
Backup
16 Kbytes DCache + ECC
SUPC
32 kHz
Crystal
Oscillator
32 kHz
RC Oscillator
RTCOUT0
RTCOUT1
RTC
VDDIO
POR
Backup RAM
AHBP
1 Kbyte
ITCM
DTCM
TCM SRAM
0–256 Kbytes
Flash
Unique ID
External Bus Interface
Static Memory Controller (SMC)
Flash
1024 Kbytes
512 Kbytes
QSPI
XIP
XDMA
128–384 Kbytes
0–256 Kbytes
AHBS
USBHS
ISI
MLB
DMA
DMA
DMA
M
M
NAND Flash Logic
System RAM
16 Kbytes ICache + ECC
AXIM
Immediate Clear
256-bit SRAM
(GPBR)
AXI Bridge
RTT
M
M
M
S
S
S
ROM
RSTC
S
S
M
M
M
S
RSWDT
Peripheral Bridge
DMA
PIOA/B/C/D/E
XDMA
3x
TWIHS
XDMA
5x
UART
XDMA
3x
USART
XDMA
PIO
XDMA
XDMA
2x
I2SC
SSC
XDMA
HSMCI
XDMA
2x
SPI
XDMA
4x
TC
XDMA
2x
PWM
XDMA
XDMA
2x
12-bit
AFE
ACC
12-bit
DAC
XDMA
AES
TRNG
and its subsidiaries
DA
C
0
DA ..1
TR
G
EF
N
VR
EF
P
VR
SC
x
I2 _M
S C
I2 Cx_ K
SC C
x K
I2 _W
S
I2 Cx S
SC _D
x_ I
D
M O
C
M CK
C
M CD
C
DA A
0.
.3
SP
I
SP x_M
Ix IS
SP _M O
SP Ix O
Ix _S SI
_N P
PC CK
S0
..3
TC
L
TI K0.
O .1
TI A0. 1
O .1
PW
B0 1
M
..1
1
PW Cx_
P
M
W
PW PW Cx M
M M _PW H0.
C C
x_ x_ M .3
PW PW L0
.
M M .3
EX FI
AF TR 0..2
Ex G0
AF _A ..1
Ex D
_A TR
D G
0.
.1
1
I2
TD
R
D
TK
R
K
TF
R
F
TW
TW D
0
C ..2
K0
..2
Temp Sensor
© 2022 Microchip Technology Inc.
Complete Data Sheet
24-channel
XDMA
M
M
WDT
SM
S
12-layer Bus Matrix
fMAX 150 MHz
S
Boot
Program
NRST
VDDPLL
VDDCORE
TCM
Interface
FPU
R
X
U D0
TX ..
D 4
0.
.4
SC
K
TX 0..
D 2
R 0.
XD .2
RT 0..
D
SR
S 2
R 0. CT 0..2
I0 .2 S
..2 , D 0
, D T ..2
R
C 0
D ..2
0
P ..2
PI IOD
O C
D 0
C ..
EN 7
PI
O 1..2
D
C
C
LK
XIN32
XOUT32
MPU
U
WKUP0..13
Cortex-M7 Processor
fMAX 300 MHz
ETM
NVIC
PLLA
Multi-port
SRAM
In-Circuit Emulator
TPIU
UPLL
DS60001527G-page 18
ICM/SHA
SAM E70/S70/V70/V71
Block Diagram
IS
I_
IS D[1
I_ 1
IS PC :0]
I_ K
H ,I
SY S
I_
G
TX NC MC
G CK , IS K
T ,
I_
G XE GR VS
C R X
Y
R ,
G S, GT CK NC
R G X ,
X
G
G ER CO DV RE
R , L
FC
G X0 GR , G
K
M ..3 X C
D
R
G C, , G DV SD
TS G TX
V
U M 0.
C D .3
O IO
C
M
A
P
C NR
AN X0
TX ..1
0.
.1
M
L
M BC
L L
M BS K
LB IG
DA
T
IO
O
D
VD
VD
D
U
T
D
TC
IO
K/
SW
JT
C
L
AG
K
SE
L
SW
/T
R
TM
TD
O
TD
I
TR
S/
AC
TR EC
AC LK
ED
0.
.3
AC
ES
W
O
A[
23
:
N 0],
W D
N AIT [15
AN ,
:0
D NC ]
O S
E, 0.
N .3,
A2
AN N
1/
DW RD
A2 NA
E , NW
2 N
A0 /NA DAL
E
/N ND E
A1 LB CL
,
6, N E
A1 UB
7
Q
SC
Q K,
M Q
O
Q S CS
M I/Q
Q ISO IO
IO /Q 0
2. IO
.3 1
H
SD
H M
SD
P
Figure 3-4. SAM V71 144-pin Block Diagram
System Controller
TST
XIN
XOUT
Voltage
Regulator
3-20 MHz
Crystal
Oscillator
PCK0..2
Serial Wire Debug/JTAG Boundary Scan
4/8/12 MHz
RC Oscillator
PMC
Transceiver
Backup
16 Kbytes DCache + ECC
SUPC
32 kHz
Crystal
Oscillator
32 kHz
RC Oscillator
RTCOUT0
RTCOUT1
RTC
VDDIO
POR
Backup RAM
AHBP
1 Kbyte
ITCM
DTCM
Flash
Unique ID
TCM SRAM
0–256 Kbytes
System RAM
16 Kbytes ICache + ECC
External Bus Interface
Static Memory Controller (SMC)
Flash
QSPI
HSUSB
ISI
NAND Flash Logic
2048 Kbytes
1024 Kbytes
512 Kbytes
GMAC
MII/RMII
2x
MCAN
MLB
DMA
DMA
FIFO
XIP
XDMA
128–384 Kbytes
0–256 Kbytes
AHBS
AXIM
Immediate Clear
256-bit SRAM
(GPBR)
DMA
DMA
M
M
DMA
AXI Bridge
RTT
M
M
M
S
S
S
ROM
RSTC
S
S
M M
M
M
RSWDT
Peripheral Bridge
PIOA/B/C/D/E
XDMA
3x
TWIHS
XDMA
5x
UART
XDMA
3x
USART
XDMA
PIO
XDMA
XDMA
2x
I2SC
SSC
XDMA
HSMCI
XDMA
2x
SPI
XDMA
4x
TC
XDMA
2x
PWM
XDMA
2x
12-bit
AFE
XDMA
ACC
12-bit
DAC
XDMA
AES
TRNG
and its subsidiaries
DA
C
0
DA ..1
TR
G
VR
EF
N
VR
EF
P
SC
x
I2 _M
S C
I2 Cx_ K
SC C
x K
I2 _W
S
I2 Cx S
SC _D
x_ I
D
M O
C
M CK
C
M CD
C
DA A
0.
.3
SP
I
SP x_M
Ix IS
SP _M O
SP Ix O
Ix _S SI
_N P
PC CK
S0
..3
TC
LK
TI 0.
O .1
TI A0. 1
O .1
PW
B0 1
M
..1
1
PW Cx_
P
M
W
PW PW Cx M
M M _PW H0.
C C
x_ x_ M .3
PW PW L0
.
M M .3
EX FI
AF TR 0..2
E G
AF x_A 0..1
Ex D
_A TR
D G
0.
.1
1
I2
TD
R
D
TK
R
K
TF
R
F
R
X
U D0
TX ..
D 4
0.
.4
SC
K
TX 0..
D 2
R 0.
XD .2
RT 0..
D
SR
S 2
R 0. CT 0..2
I0 .2 S
..2 , D 0
, D T ..2
R
C 0
D ..2
0
P ..2
PI IOD
O C
D 0
C ..
EN 7
PI
O 1..2
D
C
C
LK
U
TW
TW D
0
C ..2
K0
..2
Temp Sensor
© 2022 Microchip Technology Inc.
Complete Data Sheet
24-channel
XDMA
M
M
WDT
S
SM
S
12-layer Bus Matrix
fMAX 150 MHz
S
Boot
Program
NRST
VDDPLL
VDDCORE
TCM
Interface
Multi-port
SRAM
FPU
MPU
ERASE
XIN32
XOUT32
Cortex-M7 Processor
fMAX 300 MHz
ETM
NVIC
PLLA
WKUP0..13
In-Circuit Emulator
TPIU
UPLL
DS60001527G-page 19
DMA
ICM/SHA
SAM E70/S70/V70/V71
Signal Description
4.
Signal Description
The following table provides details on signal names classified by peripherals.
Table 4-1. Signal Description List
Signal Name
Function
Type
Active
Level
Voltage
Reference
Comments
Power Supplies
VDDIO
Peripherals I/O Lines
Power Supply
Power
–
–
–
VDDIN
Voltage Regulator Input,
AFE, DAC, and Analog
Comparator Power
Supply(1)
Power
–
–
–
VDDOUT
Voltage Regulator
Output
Power
–
–
–
VDDPLL
PLLA Power Supply
Power
–
–
–
VDDPLLUSB
USB PLL and Oscillator
Power Supply
Power
–
–
–
VDDCORE
Powers the core, the
embedded memories
and the peripherals
Power
–
–
–
GND, GNDPLL,
GNDPLLUSB,
GNDANA,
GNDUTMI
Ground
Ground
–
–
–
VDDUTMII
USB Transceiver Power
Supply
Power
–
–
–
VDDUTMIC
USB Core Power Supply
Power
–
–
–
GNDUTMI
USB Ground
Ground
–
–
–
Clocks, Oscillators, and PLLs
XIN
Main Oscillator Input
Input
–
XOUT
Main Oscillator Output
Output
–
XIN32
Slow Clock Oscillator
Input
Input
–
XOUT32
Slow Clock Oscillator
Output
Output
–
PCK0–PCK2
Programmable Clock
Output
Output
–
VDDIO
If any signal is not
used, its PIO pin
should be setup as an
output, driven low, and
attached to a dedicated
trace on the board in
order to reduce current
consumption.
–
Real Time Clock
RTCOUT0
Programmable RTC
Waveform Output
Output
–
RTCOUT1
Programmable RTC
Waveform Output
Output
–
© 2022 Microchip Technology Inc.
and its subsidiaries
–
VDDIO
Complete Data Sheet
–
DS60001527G-page 20
SAM E70/S70/V70/V71
Signal Description
...........continued
Signal Name
Function
Type
Active
Level
Voltage
Reference
Comments
Serial Wire Debug/JTAG Boundary Scan
SWCLK/TCK
Serial Wire Clock/Test
Clock (Boundary scan
mode only)
Input
–
–
TDI
Test Data In (Boundary
scan mode only)
Input
–
–
TDO/TRACESWO
Test Data Out (Boundary
scan mode only)
Output
–
SWDIO/TMS
Serial Wire Input/
Output /Test Mode
Select (Boundary scan
mode only)
I/O / Input
–
–
JTAGSEL
JTAG Selection
Input
High
–
VDDIO
–
Trace Debug Port
TRACECLK
Trace Clock
Output
–
TRACED0–
TRACED3
Trace Data
Output
–
PCK3 is used for ETM
VDDIO
–
Flash Memory
ERASE
Flash and NVM
Configuration Bits Erase
Command
Input
High
VDDIO
–
Reset/Test
NRST
Synchronous
Microcontroller Reset
I/O
Low
TST
Test Select
Input
–
VDDIO
–
–
Universal Asynchronous Receiver Transceiver - UART(x=[0:4])
URXDx
UART Receive Data
Input
–
–
UTXDx
UART Transmit Data
Output
–
–
PCK4 can be used to
generate the baud rate
PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE
PA0–PA31
Parallel I/O Controller A
I/O
–
–
PB0–PB9, PB12–
PB13
Parallel I/O Controller B
I/O
–
PC0– PC31
Parallel I/O Controller C
I/O
–
PD0–PD31
Parallel I/O Controller D
I/O
–
–
–
PE0–PE5
Parallel I/O Controller E
I/O
–
–
–
VDDIO
–
–
PIO Controller - Parallel Capture Mode
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 21
SAM E70/S70/V70/V71
Signal Description
...........continued
Signal Name
Function
Type
Active
Level
PIODC0–PIODC7
Parallel Capture Mode
Data
Input
–
PIODCCLK
Parallel Capture Mode
Clock
Input
–
PIODCEN1–
PIODCEN2
Parallel Capture Mode
Enable
Input
–
Voltage
Reference
Comments
–
VDDIO
–
–
External Bus Interface
D[15:0]
Data Bus
I/O
–
–
–
A[23:0]
Address Bus
Output
–
–
–
NWAIT
External Wait Signal
Input
Low
–
–
Static Memory Controller (SMC)
NCS0–NCS3
Chip Select Lines
Output
Low
–
–
NRD
Read Signal
Output
Low
–
–
NWE
Write Enable
Output
Low
–
–
NWR0–NWR1
Write Signal
Output
Low
–
–
NBS0–NBS1
Byte Mask Signal
Output
Low
–
–
NAND Flash Logic
NANDOE
NAND Flash Output
Enable
Output
Low
–
–
NANDWE
NAND Flash Write
Enable
Output
Low
–
–
High-Speed Multimedia Card Interface (HSMCI)
MCCK
Multimedia Card Clock
O
–
–
–
MCCDA
Multimedia Card Slot A
Command
I/O
–
–
–
MCDA0–MCDA3
Multimedia Card Slot A
Data
I/O
–
–
–
Universal Synchronous Asynchronous Receiver Transmitter (USART(x=[0:2]))
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 22
SAM E70/S70/V70/V71
Signal Description
...........continued
Signal Name
Function
Type
Active
Level
Voltage
Reference
SCKx
USARTx Serial Clock
I/O
–
–
TXDx
USARTx Transmit Data
I/O
–
–
RXDx
USARTx Receive Data
Input
–
–
RTSx
USARTx Request To
Send
Output
–
–
CTSx
USARTx Clear To Send
Input
–
–
DTRx
USARTx Data Terminal
Ready
Output
–
–
DSRx
USARTx Data Set
Ready
Input
–
–
DCDx
USARTx Data Carrier
Detect
Input
–
–
RIx
USARTx Ring Indicator
Input
–
–
LONCOL1
LON Collision Detection
Input
–
–
Comments
PCK4 can be used to
generate the baud rate
Synchronous Serial Controller (SSC)
TD
SSC Transmit Data
Output
–
–
–
RD
SSC Receive Data
Input
–
–
–
TK
SSC Transmit Clock
I/O
–
–
–
RK
SSC Receive Clock
I/O
–
–
–
TF
SSC Transmit Frame
Sync
I/O
–
–
–
RF
SSC Receive Frame
Sync
I/O
–
–
–
Inter-IC Sound Controller (I2SC[1..0])
I2SCx_MCK
Host Clock
Output
–
VDDIO
I2SCx_CK
Serial Clock
I/O
–
VDDIO
I2SCx_WS
I2S Word Select
I/O
–
VDDIO
I2SCx_DI
Serial Data Input
Input
–
VDDIO
I2SCx_DO
Serial Data Output
Output
–
VDDIO
GCLK[PID] can be used
to generate the baud
rate
Image Sensor Interface (ISI)
ISI_D0–ISI_D11
Image Sensor Data
Input
–
–
–
ISI_MCK
Image sensor Reference
clock.
No dedicated signal,
PCK1 can be used.
Output
–
–
–
ISI_HSYNC
Image Sensor Horizontal
Synchro
Input
–
–
–
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 23
SAM E70/S70/V70/V71
Signal Description
...........continued
Signal Name
Function
Type
Active
Level
Voltage
Reference
Comments
ISI_VSYNC
Image Sensor Vertical
Synchro
Input
–
–
–
ISI_PCK
Image Sensor Data
clock
Input
–
–
–
Timer Counter (TC(x=[0:11]))
TCLKx
TC Channel x External
Clock Input
Input
–
–
TIOAx
TC Channel x I/O Line A
I/O
–
–
TIOBx
TC Channel x I/O Line B
I/O
–
–
PCK6 can be used as an
input clock
PCK7 can be used as an
input clock for TC0.Ch0
only
Pulse-Width Modulation Controller (PWMC(x=[0..1]))
PWMCx_PWMH0–
PWMCx_PWMH3
Waveform Output High
for Channel 0–3
PWMCx_PWML0–
PWMCx_PWML3
Waveform Output Low
for Channel 0–3
Output
PWMCx_PWMFI0–
PWMCx_PWMFI2
Fault Input
PWMCx_PWMEXT
RG0–
PWMCx_PWMEXT
RG1
External Trigger Input
Output
–
–
–
–
–
Only output in
complementary mode
when dead time
insertion is enabled.
Input
–
–
–
Input
–
–
–
Serial Peripheral Interface (SPI(x=[0..1]))
SPIx_MISO
Host In Client Out
I/O
–
–
–
SPIx_MOSI
Host Out Client In
I/O
–
–
–
SPIx_SPCK
SPI Serial Clock
I/O
–
–
–
SPIx_NPCS0
SPI Peripheral Chip
Select 0
I/O
Low
–
–
SPIx_NPCS1–
SPIx_NPCS3
SPI Peripheral Chip
Select
Output
Low
–
–
Quad I/O SPI (QSPI)
QSCK
QSPI Serial Clock
Output
–
–
–
QCS
QSPI Chip Select
Output
–
–
–
QIO0–QIO3
QSPI I/O
QIO0 is QMOSI Host
Out Client In
I/O
–
–
–
QIO1 is QMISO Host In
Client Out
Two-Wire Interface (TWIHS (x=0..2))
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 24
SAM E70/S70/V70/V71
Signal Description
...........continued
Signal Name
Function
Type
Active
Level
Voltage
Reference
Comments
TWDx
TWIx Two-wire Serial
Data
I/O
–
–
–
TWCKx
TWIx Two-wire Serial
Clock
I/O
–
–
–
Analog
VREFP
ADC, DAC and Analog
Comparator Positive
Reference
Analog
–
–
–
VREFN
ADC, DAC and Analog
Comparator Negative
Reference Must be
connected to GND or
GNDANA.
Analog
–
–
–
12-bit Analog Front End - (x=[0..1])
AFEx_AD0–
AFEx_AD11 (2)
Analog Inputs
Analog,
Digital
–
–
–
AFEx_ADTRG
ADC Trigger
Input
–
VDDIO
–
12-bit Digital-to-Analog Converter (DAC)
DAC0–DAC1
Analog Output
Analog,
Digital
–
–
–
DATRG
DAC Trigger
Input
–
VDDIO
–
Fast Flash Programming Interface (FFPI)
PGMEN0–
PGMEN1
Programming Enabling
Input
–
PGMM0–PGMM3
Programming Mode
Input
–
–
PGMD0–PGMD15
Programming Data
I/O
–
–
PGMRDY
Programming Ready
Output
High
PGMNVALID
Data Direction
Output
Low
PGMNOE
Programming Read
Input
Low
–
PGMNCMD
Programming Command
Input
Low
–
VDDIO
VDDIO
–
–
–
USB High Speed (USBHS)
HSDM
USB High -Speed Data -
HSDP
USB High-Speed Data +
VBG
Bias Voltage Reference
for USB
Analog,
Digital
–
Analog
–
–
VDDUTMII
–
–
–
–
Ethernet MAC 10/100 - GMAC
GREFCK
Reference Clock
Input
–
–
RMII only
GTXCK
Transmit Clock
Input
–
–
MII only
GRXCK
Receive Clock
Input
–
–
MII only
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 25
SAM E70/S70/V70/V71
Signal Description
...........continued
Signal Name
Function
Type
Active
Level
Voltage
Reference
Comments
GTXEN
Transmit Enable
Output
–
–
–
GTX0 - GTX3
Transmit Data
Output
–
–
GTX0–GTX1 only in
RMII
GTXER
Transmit Coding Error
Output
–
–
MII only
GRXDV
Receive Data Valid
Input
–
–
MII only
GRX0 - GRX3
Receive Data
Input
–
–
GRX0–GRX1 only in
RMII
GRXER
Receive Error
Input
–
–
–
GCRS
Carrier Sense
Input
–
–
MII only
GCOL
Collision Detected
Input
–
–
MII only
GMDC
Management Data Clock
Output
–
–
–
GMDIO
Management Data Input/
Output
I/O
–
–
–
GTSUCOMP
TSU timer comparison
valid
Output
–
–
Active Low
–
CANRX1 is available on
PD28 for 100-pin only
CANRX1 is available on
PC12 for 144-pin only
–
PCK5 can be used for
CAN clock
PCK6 and PCK7 can
be used for CAN
timestamping
Controller Area Network - MCAN (x=[0:1])
CANRXx
CANTXx
CAN Receive
CAN Transmit
Input
Output
–
–
MediaLB - (MLB)
MLBCLK
MLB Clock
input
–
–
–
MLBSIG
MLB Signal
I/O
–
–
–
MLBDAT
MLB Data
I/O
–
–
–
Notes:
1. Refer to the Active Mode section in the Power Considerations chapter for restrictions on the voltage range of
analog cells.
2. AFE0_AD11 is not an actual pin but is connected to a temperature sensor.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 26
SAM E70/S70/V70/V71
Automotive Quality Grade
5.
Automotive Quality Grade
The SAM V70 and SAM V71 devices are developed and manufactured according to the most stringent requirements
of the international standard ISO-TS-16949. This data sheet contains limited values extracted from the results of
extensive characterization (temperature and voltage).
The quality and reliability of the SAM V70 and SAM V71 has been verified during regular product qualification as per
AEC-Q100 grade 2 (–40°C to +105°C).
Table 5-1. Temperature Grade Identification for Automotive Products
Temperature (°C)
Temperature Identifier
Comments
–40°C to +105°C
B
AEC-Q100 Grade 2
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 27
SAM E70/S70/V70/V71
Package and Pinout
6.
Package and Pinout
In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics.
•
“PIO” “/” signal
Indicates whether the PIO Line resets in I/O mode or in peripheral mode. If “PIO” is mentioned, the PIO line is
maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the
register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address
lines, which require the pin to be driven as soon as the reset is released.
•
“I” / ”O”
Indicates whether the signal is input or output state.
•
“PU” / “PD”
Indicates whether pullup, pulldown, or nothing is enabled.
•
“ST”
Indicates if Schmitt Trigger is enabled.
6.1
144-lead Packages
6.1.1
144-pin LQFP Package Outline
Figure 6-1. Orientation of the 144-pin LQFP Package
144
1
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 28
SAM E70/S70/V70/V71
Package and Pinout
6.1.2
144-ball LFBGA/TFBGA Package Outline
Figure 6-2. Orientation of the 144-ball LFBGA/TFBGA Package
6.1.3
144-ball UFBGA Package Outline
Figure 6-3. Orientation of the 144-ball UFBGA Package
6.2
144-lead Package Pinout
Table 6-1. 144-lead Package Pinout
LQFP Pin
LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
102
C11
E11
VDDIO
GPIO_AD
PA0
I/O
WKUP0(1)
I
PWMC0_
PWMH0
O
TIOA0
I/O
A17
O
I2SC0_M
CK
O
PIO, I, PU,
ST
99
D12
F11
VDDIO
GPIO_AD
PA1
I/O
WKUP1(1)
I
PWMC0_
PWML0
O
TIOB0
I/O
A18
O
I2SC0_C K
I/O
PIO, I, PU,
ST
93
E12
G12
VDDIO
GPIO
PA2
I/O
WKUP2(1)
I
PWMC0_
PWMH1
O
–
–
DATRG
I
–
–
PIO, I, PU,
ST
91
F12
G11
VDDIO
GPIO_AD
PA3
I/O
PIODC0(2)
I
TWD0
I/O
LONCOL 1
I
PCK2
O
–
–
PIO, I, PU,
ST
77
K12
L12
VDDIO
GPIO
PA4
I/O
WKUP3/P
IODC1(3)
I
TWCK0
O
TCLK0
I
UTXD1
O
–
–
PIO, I, PU,
ST
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 29
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
73
M11
N13
VDDIO
GPIO_AD
PA5
I/O
WKUP4/P
IODC2(3)
I
PWMC1_
PWML3
O
ISI_D4
I
URXD1
I
–
–
PIO, I, PU,
ST
114
B9
B11
VDDIO
GPIO_AD
PA6
I/O
–
–
–
–
PCK0
O
UTXD1
O
–
–
PIO, I, PU,
ST
35
L2
N1
VDDIO
CLOCK
PA7
I/O
XIN32(4)
I
–
–
PWMC0_
PWMH3
O
–
–
–
–
PIO, HiZ
36
M2
N2
VDDIO
CLOCK
PA8
I/O
XOUT32(4)
O
PWMC1_
PWMH3
O
AFE0_ADT
RG
I
–
–
–
–
PIO, HiZ
75
M12
L11
VDDIO
GPIO_AD
PA9
I/O
WKUP6/P
IODC3(3)
I
URXD0
I
ISI_D3
I
PWMC0_
PWMFI0
I
–
–
PIO, I, PU,
ST
66
L9
M10
VDDIO
GPIO_AD
PA10
I/O
PIODC4(2)
I
UTXD0
O
PWMC0_
PWMEXTR
G0
I
RD
I
–
–
PIO, I, PU,
ST
64
J9
N10
VDDIO
GPIO_AD
PA11
I/O
WKUP7/P
IODC5(3)
I
QCS
O
PWMC0_
PWMH0
O
PWMC1_
PWML0
O
–
–
PIO, I, PU,
ST
68
L10
N11
VDDIO
GPIO_AD
PA12
I/O
PIODC6(2)
I
QIO1
I/O
PWMC0_
PWMH1
O
PWMC1_
PWMH0
O
–
–
PIO, I, PU,
ST
42
M3
M4
VDDIO
GPIO_AD
PA13
I/O
PIODC7(2)
I
QIO0
I/O
PWMC0_
PWMH2
O
PWMC1_
PWML1
O
–
–
PIO, I, PU,
ST
51
K6
M6
VDDIO
GPIO_CL
K
PA14
I/O
WKUP8/P
IODCEN1(
3)
I
QSCK
O
PWMC0_
PWMH3
O
PWMC1_
PWMH1
O
–
–
PIO, I, PU,
ST
49
L5
N6
VDDIO
GPIO_AD
PA15
I/O
–
–
D14
I/O
TIOA1
I/O
PWMC0_
PWML3
O
I2SC0_W
S
I/O
PIO, I, PU,
ST
45
K5
L4
VDDIO
GPIO_AD
PA16
I/O
–
–
D15
I/O
TIOB1
I/O
PWMC0_
PWML2
O
I2SC0_DI
I
PIO, I, PU,
ST
25
J1
J4
VDDIO
GPIO_AD
PA17
I/O
AFE0_AD6
(5)
I
QIO2
I/O
PCK1
O
PWMC0_
PWMH3
O
–
–
PIO, I, PU,
ST
24
H2
J3
VDDIO
GPIO_AD
PA18
I/O
AFE0_AD7
(5)
I
PWMC1_
PWMEXTR
G1
I
PCK2
O
A14
O
–
–
PIO, I, PU,
ST
23
H1
J2
VDDIO
GPIO_AD
PA19
I/O
AFE0_AD8
/WKUP9(6)
I
–
–
PWMC0_
PWML0
O
A15
O
I2SC1_M
CK
O
PIO, I, PU,
ST
22
H3
J1
VDDIO
GPIO_AD
PA20
I/O
AFE0_AD9
/
WKUP10(6
)
I
–
–
PWMC0_
PWML1
O
A16
O
I2SC1_C K
I/O
PIO, I, PU,
ST
32
K2
M1
VDDIO
GPIO_AD
PA21
I/O
AFE0_AD1
/ PIODCEN
2(8)
I
RXD1
I
PCK1
O
PWMC1_
PWMFI0
I
–
–
PIO, I, PU,
ST
37
K3
M2
VDDIO
GPIO_AD
PA22
I/O
PIODCCL
K(2)
I
RK
I/O
PWMC0_
PWMEXTR
G1
I
NCS2
O
–
–
PIO, I, PU,
ST
46
L4
N5
VDDIO
GPIO_AD
PA23
I/O
–
–
SCK1
I/O
PWMC0_
PWMH0
O
A19
O
PWMC1_
PWML2
O
PIO, I, PU,
ST
56
L7
N8
VDDIO
GPIO_AD
PA24
I/O
–
–
RTS1
O
PWMC0_
PWMH1
O
A20
O
ISI_PCK
I
PIO, I, PU,
ST
59
K8
L8
VDDIO
GPIO_AD
PA25
I/O
–
–
CTS1
I
PWMC0_
PWMH2
O
A23
O
MCCK
O
PIO, I, PU,
ST
62
J8
M9
VDDIO
GPIO
PA26
I/O
–
–
DCD1
I
TIOA2
O
MCDA2
I/O
PWMC1_
PWMFI1
I
PIO, I, PU,
ST
70
J10
N12
VDDIO
GPIO_AD
PA27
I/O
–
–
DTR1
O
TIOB2
I/O
MCDA3
I/O
ISI_D7
I
PIO, I, PU,
ST
112
C9
C11
VDDIO
GPIO
PA28
I/O
–
–
DSR1
I
TCLK1
I
MCCDA
I/O
PWMC1_
PWMFI2
I
PIO, I, PU,
ST
129
A6
A7
VDDIO
GPIO
PA29
I/O
–
–
RI1
I
TCLK2
I
–
–
–
–
PIO, I, PU,
ST
116
A10
A11
VDDIO
GPIO
PA30
I/O
WKUP11(1
)
I
PWMC0_
PWML2
O
PWMC1_
PWMEXTR
G0
I
MCDA0
I/O
I2SC0_D O
O
PIO, I, PU,
ST
118
C8
C10
VDDIO
GPIO_AD
PA31
I/O
–
–
SPI0_NP
CS1
I/O
PCK2
O
MCDA1
I/O
PWMC1_
PWMH2
O
PIO, I, PU,
ST
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 30
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
21
H4
H2
VDDIO
GPIO
PB0
I/O
AFE0_AD1
0/
RTCOUT
0(7)
I
PWMC0_
PWMH0
O
–
–
RXD0
I
TF
I/O
PIO, I, PU,
ST
20
G3
H1
VDDIO
GPIO
PB1
I/O
AFE1_AD0
/ RTCOUT
1(7)
I
PWMC0_
PWMH1
O
GTSUCO
MP
O
TXD0
I/O
TK
I/O
PIO, I, PU,
ST
26
J2
K1
VDDIO
GPIO
PB2
I/O
AFE0_AD5
(5)
I
CANTX0
O
–
–
CTS0
I
SPI0_NP
CS0
I/O
PIO, I, PU,
ST
31
J3
L1
VDDIO
GPIO_AD
PB3
I/O
AFE0_AD2
/
WKUP12(6
)
I
CANRX0
I
PCK2
O
RTS0
O
ISI_D2
I
PIO, I, PU,
ST
105
A12
C13
VDDIO
GPIO_ML
B
PB4
I/O
TDI(9)
I
TWD1
I/O
PWMC0_
PWMH2
O
MLBCLK
I
TXD1
I/O
PIO, I, PU,
ST
109
C10
C12
VDDIO
GPIO_ML
B
PB5
I/O
TDO/TRA
CESWO/
WKUP13(9
)
O
TWCK1
O
PWMC0_
PWML0
O
MLBDAT
I/O
TD
O
O, PU
79
J11
K11
VDDIO
GPIO
PB6
I/O
SWDIO/T
MS(9)
I
–
–
–
–
–
–
–
–
PIO,I,ST
89
F9
H13
VDDIO
GPIO
PB7
I/O
SWCLK/
TCK(9)
I
–
–
–
–
–
–
–
–
PIO,I,ST
141
A3
B2
VDDIO
CLOCK
PB8
I/O
XOUT(10)
O
–
–
–
–
–
–
–
–
PIO, HiZ
142
A2
A2
VDDIO
CLOCK
PB9
I/O
XIN(10)
I
–
–
–
–
–
–
–
–
PIO, HiZ
87
G12
J10
VDDIO
GPIO
PB12
I/O
ERASE(9)
I
PWMC0_
PWML1
O
GTSUCO
MP
O
–
–
PCK0
O
PIO, I, PD,
ST
144
B2
A1
VDDIO
GPIO_AD
PB13
I/O
DAC0(11)
O
PWMC0_
PWML2
O
PCK0
O
SCK0
I/O
–
–
PIO, I, PU,
ST
11
E4
F2
VDDIO
GPIO_AD
PC0
I/O
AFE1_AD9
(5)
I
D0
I/O
PWMC0_
PWML0
O
–
–
–
–
PIO, I, PU,
ST
38
J4
M3
VDDIO
GPIO_AD
PC1
I/O
–
–
D1
I/O
PWMC0_
PWML1
O
–
–
–
–
PIO, I, PU,
ST
39
K4
N3
VDDIO
GPIO_AD
PC2
I/O
–
–
D2
I/O
PWMC0_
PWML2
O
–
–
–
–
PIO, I, PU,
ST
40
L3
N4
VDDIO
GPIO_AD
PC3
I/O
–
–
D3
I/O
PWMC0_
PWML3
O
–
–
–
–
PIO, I, PU,
ST
41
J5
L3
VDDIO
GPIO_AD
PC4
I/O
–
–
D4
I/O
–
–
–
–
–
–
PIO, I, PU,
ST
58
L8
M8
VDDIO
GPIO_AD
PC5
I/O
–
–
D5
I/O
TIOA6
I/O
–
–
–
–
PIO, I, PU,
ST
54
K7
L7
VDDIO
GPIO_AD
PC6
I/O
–
–
D6
I/O
TIOB6
I/O
–
–
–
–
PIO, I, PU,
ST
48
M4
L5
VDDIO
GPIO_AD
PC7
I/O
–
–
D7
I/O
TCLK6
I
–
–
–
–
PIO, I, PU,
ST
82
J12
K13
VDDIO
GPIO_AD
PC8
I/O
–
–
NWR0/N
WE
O
TIOA7
I/O
–
–
–
–
PIO, I, PU,
ST
86
G11
J11
VDDIO
GPIO_AD
PC9
I/O
–
–
NANDOE
O
TIOB7
I/O
–
–
–
–
PIO, I, PU,
ST
90
F10
H12
VDDIO
GPIO_AD
PC10
I/O
–
–
NANDWE
O
TCLK7
I
–
–
–
–
PIO, I, PU,
ST
94
F11
F13
VDDIO
GPIO_AD
PC11
I/O
–
–
NRD
O
TIOA8
I/O
–
–
–
–
PIO, I, PU,
ST
17
F4
G2
VDDIO
GPIO_AD
PC12
I/O
AFE1_AD3
(5)
I
NCS3
O
TIOB8
I/O
CANRX1
I
–
–
PIO, I, PU,
ST
19
G2
H3
VDDIO
GPIO_AD
PC13
I/O
AFE1_AD1
(5)
I
NWAIT
I
PWMC0_
PWMH3
O
–
O
–
–
PIO, I, PU,
ST
97
E10
F12
VDDIO
GPIO_AD
PC14
I/O
–
–
NCS0
O
TCLK8
I
CANTX1
O
–
–
PIO, I, PU,
ST
18
G1
H4
VDDIO
GPIO_AD
PC15
I/O
AFE1_AD2
(5)
I
NCS1/SD
CS
O
PWMC0_
PWML3
O
–
–
–
–
PIO, I, PU,
ST
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 31
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
100
D11
E12
VDDIO
GPIO_AD
PC16
I/O
–
–
A21/NAN
DALE
O
–
–
–
–
–
–
PIO, I, PU,
ST
103
B12
E10
VDDIO
GPIO_AD
PC17
I/O
–
–
A22/NAN
DCLE
O
–
–
–
–
–
–
PIO, I, PU,
ST
111
B10
B12
VDDIO
GPIO_AD
PC18
I/O
–
–
A0/NBS0
O
PWMC0_
PWML1
O
–
–
–
–
PIO, I, PU,
ST
117
D8
B10
VDDIO
GPIO_AD
PC19
I/O
–
–
A1
O
PWMC0_
PWMH2
O
–
–
–
–
PIO, I, PU,
ST
120
A9
C9
VDDIO
GPIO_AD
PC20
I/O
–
–
A2
O
PWMC0_
PWML2
O
–
–
–
–
PIO, I, PU,
ST
122
A7
A9
VDDIO
GPIO_AD
PC21
I/O
–
–
A3
O
PWMC0_
PWMH3
O
–
–
–
–
PIO, I, PU,
ST
124
C7
A8
VDDIO
GPIO_AD
PC22
I/O
–
–
A4
O
PWMC0_
PWML3
O
–
–
–
–
PIO, I, PU,
ST
127
C6
C7
VDDIO
GPIO_AD
PC23
I/O
–
–
A5
O
TIOA3
I/O
–
–
–
–
PIO, I, PU,
ST
130
B6
D7
VDDIO
GPIO_AD
PC24
I/O
–
–
A6
O
TIOB3
I/O
SPI1_SP
CK
O
–
–
PIO, I, PU,
ST
133
C5
C6
VDDIO
GPIO_AD
PC25
I/O
–
–
A7
O
TCLK3
I
SPI1_NP
CS0
I/O
–
–
PIO, I, PU,
ST
13
F2
F4
VDDIO
GPIO_AD
PC26
I/O
AFE1_AD7
(5)
I
A8
O
TIOA4
I/O
SPI1_MIS
O
I
–
–
PIO, I, PU,
ST
12
E2
F3
VDDIO
GPIO_AD
PC27
I/O
AFE1_AD8
(5)
I
A9
O
TIOB4
I/O
SPI1_MO
SI
O
–
–
PIO, I, PU,
ST
76
L12
L13
VDDIO
GPIO_AD
PC28
I/O
–
–
A10
O
TCLK4
I
SPI1_NP
CS1
I/O
–
–
PIO, I, PU,
ST
16
F3
G1
VDDIO
GPIO_AD
PC29
I/O
AFE1_AD4
(5)
I
A11
O
TIOA5
I/O
SPI1_NP
CS2
O
–
–
PIO, I, PU,
ST
15
F1
G3
VDDIO
GPIO_AD
PC30
I/O
AFE1_AD5
(5)
I
A12
O
TIOB5
I/O
SPI1_NP
CS3
O
–
–
PIO, I, PU,
ST
14
E1
G4
VDDIO
GPIO_AD
PC31
I/O
AFE1_AD6
(5)
I
A13
O
TCLK5
I
–
–
–
–
PIO, I, PU,
ST
1
D4
B1
VDDIO
GPIO_AD
PD0
I/O
DAC1(11)
I
GTXCK
I
PWMC1_
PWML0
O
SPI1_NP
CS1
I/O
DCD0
I
PIO, I, PU,
ST
132
B5
B6
VDDIO
GPIO
PD1
I/O
–
–
GTXEN
O
PWMC1_
PWMH0
O
SPI1_NP
CS2
I/O
DTR0
O
PIO, I, PU,
ST
131
A5
A6
VDDIO
GPIO
PD2
I/O
–
–
GTX0
O
PWMC1_
PWML1
O
SPI1_NP
CS3
I/O
DSR0
I
PIO, I, PU,
ST
128
B7
B7
VDDIO
GPIO
PD3
I/O
–
–
GTX1
O
PWMC1_
PWMH1
O
UTXD4
O
RI0
I
PIO, I, PU,
ST
126
D6
C8
VDDIO
GPIO_CL
K
PD4
I/O
–
–
GRXDV
I
PWMC1_
PWML2
O
TRACED 0
O
DCD2
I
PIO, I, PU,
ST
125
D7
B8
VDDIO
GPIO_CL
K
PD5
I/O
–
–
GRX0
I
PWMC1_
PWMH2
O
TRACED 1
O
DTR2
O
PIO, I, PU,
ST
121
A8
B9
VDDIO
GPIO_CL
K
PD6
I/O
–
–
GRX1
I
PWMC1_
PWML3
O
TRACED 2
O
DSR2
I
PIO, I, PU,
ST
119
B8
A10
VDDIO
GPIO_CL
K
PD7
I/O
–
–
GRXER
I
PWMC1_
PWMH3
O
TRACED 3
O
RI2
I
PIO, I, PU,
ST
113
E9
A12
VDDIO
GPIO_CL
K
PD8
I/O
–
–
GMDC
O
PWMC0_
PWMFI1
I
–
–
TRACEC
LK
O
PIO, I, PU,
ST
110
D9
A13
VDDIO
GPIO_CL
K
PD9
I/O
–
–
GMDIO
I/O
PWMC0_
PWMFI2
I
AFE1_AD
TRG
I
–
–
PIO, I, PU,
ST
101
C12
D13
VDDIO
GPIO_ML
B
PD10
I/O
–
–
GCRS
I
PWMC0_
PWML0
O
TD
O
MLBSIG
I/O
PIO, I, PD,
ST
98
E11
E13
VDDIO
GPIO_AD
PD11
I/O
–
–
GRX2
I
PWMC0_
PWMH0
O
GTSUCO
MP
O
ISI_D5
I
PIO, I, PU,
ST
92
G10
G13
VDDIO
GPIO_AD
PD12
I/O
–
–
GRX3
I
CANTX1
O
SPI0_NP
CS2
O
ISI_D6
I
PIO, I, PU,
ST
88
G9
H11
VDDIO
GPIO_CL
K
PD13
I/O
–
–
GCOL
I
–
–
–
O
–
–
PIO, I, PU,
ST
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 32
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
84
H10
J12
VDDIO
GPIO_AD
PD14
I/O
–
–
GRXCK
I
–
–
–
O
–
–
PIO, I, PU,
ST
106
A11
D11
VDDIO
GPIO_AD
PD15
I/O
–
–
GTX2
O
RXD2
I
NWR1/N
BS1
O
–
–
PIO, I, PU,
ST
78
K11
K10
VDDIO
GPIO_AD
PD16
I/O
–
–
GTX3
O
TXD2
I/O
–
O
–
–
PIO, I, PU,
ST
74
L11
M13
VDDIO
GPIO_AD
PD17
I/O
–
–
GTXER
O
SCK2
I/O
–
O
–
–
PIO, I, PU,
ST
69
M10
M11
VDDIO
GPIO_AD
PD18
I/O
–
–
NCS1/SD
CS
O
RTS2
O
URXD4
I
–
–
PIO, I, PU,
ST
67
M9
L10
VDDIO
GPIO_AD
PD19
I/O
–
–
NCS3
O
CTS2
I
UTXD4
O
–
–
PIO, I, PU,
ST
65
K9
K9
VDDIO
GPIO
PD20
I/O
–
–
PWMC0_
PWMH0
O
SPI0_MIS
O
I/O
GTSUCO
MP
O
–
–
PIO, I, PU,
ST
63
H9
L9
VDDIO
GPIO_AD
PD21
I/O
–
–
PWMC0_
PWMH1
O
SPI0_MO
SI
I/O
TIOA11
I/O
ISI_D1
I
PIO, I, PU,
ST
60
M8
N9
VDDIO
GPIO_AD
PD22
I/O
–
–
PWMC0_
PWMH2
O
SPI0_SP
CK
O
TIOB11
I/O
ISI_D0
I
PIO, I, PU,
ST
57
M7
N7
VDDIO
GPIO_CL
K
PD23
I/O
–
–
PWMC0_
PWMH3
O
–
–
–
O
–
–
PIO, I, PU,
ST
55
M6
K7
VDDIO
GPIO_AD
PD24
I/O
–
–
PWMC0_
PWML0
O
RF
I/O
TCLK11
I
ISI_HSYN
C
I
PIO, I, PU,
ST
52
M5
L6
VDDIO
GPIO_AD
PD25
I/O
–
–
PWMC0_
PWML1
O
SPI0_NP
CS1
I/O
URXD2
I
ISI_VSYN
C
I
PIO, I, PU,
ST
53
L6
M7
VDDIO
GPIO
PD26
I/O
–
–
PWMC0_
PWML2
O
TD
O
UTXD2
O
UTXD1
O
PIO, I, PU,
ST
47
J6
M5
VDDIO
GPIO_AD
PD27
I/O
–
–
PWMC0_
PWML3
O
SPI0_NP
CS3
O
TWD2
O
ISI_D8
I
PIO, I, PU,
ST
71
K10
M12
VDDIO
GPIO_AD
PD28
I/O
WKUP5(1)
I
URXD3
I
-
I
TWCK2
O
ISI_D9
I
PIO, I, PU,
ST
108
D10
B13
VDDIO
GPIO_AD
PD29
I/O
–
–
–
–
–
–
–
O
–
–
PIO, I, PU,
ST
34
M1
L2
VDDIO
GPIO_AD
PD30
I/O
AFE0_AD
0(5)
I
UTXD3
O
–
–
–
–
ISI_D10
I
PIO, I, PU,
ST
2
D3
C3
VDDIO
GPIO_AD
PD31
I/O
–
–
QIO3
I/O
UTXD3
O
PCK2
O
ISI_D11
I
PIO, I, PU,
ST
4
C2
C2
VDDIO
GPIO_AD
PE0
I/O
AFE1_AD
11(5)
I
D8
I/O
TIOA9
I/O
I2SC1_W
S
I/O
–
–
PIO, I, PU,
ST
6
A1
D2
VDDIO
GPIO_AD
PE1
I/O
–
–
D9
I/O
TIOB9
I/O
I2SC1_D O
O
–
–
PIO, I, PU,
ST
7
B1
D1
VDDIO
GPIO_AD
PE2
I/O
–
–
D10
I/O
TCLK9
I
I2SC1_DI
I
–
–
PIO, I, PU,
ST
10
E3
F1
VDDIO
GPIO_AD
PE3
I/O
AFE1_AD
10(5)
I
D11
I/O
TIOA10
I/O
–
–
–
–
PIO, I, PU,
ST
27
K1
K2
VDDIO
GPIO_AD
PE4
I/O
AFE0_AD
4(5)
I
D12
I/O
TIOB10
I/O
–
–
–
–
PIO, I, PU,
ST
28
L1
K3
VDDIO
GPIO_AD
PE5
I/O
AFE0_AD
3(5)
I
D13
I/O
TCLK10
I/O
–
–
–
–
PIO, I, PU,
ST
3
C3
E4
VDDOUT
Power
VDDOUT
–
–
–
–
–
–
–
–
–
–
–
–
5
C1
C1
VDDIN
Power
VDDIN
–
–
–
–
–
–
–
–
–
–
–
–
8
D2
E2
GND
Reference
VREFN
I
–
–
–
–
–
–
–
–
–
–
–
9
D1
E1
VDDIO
Reference
VREFP
I
–
–
–
–
–
–
–
–
–
–
–
83
H12
K12
VDDIO
RST
NRST
I/O
–
–
–
–
–
–
–
–
–
–
I, PU
85
H11
J13
VDDIO
TEST
TST
I
–
–
–
–
–
–
–
–
–
–
I, PD
30,43,72,8
0,96
G8,H6,H7
D6,F10,K6
VDDIO
Power
VDDIO
–
–
–
–
–
–
–
–
–
–
–
–
104
B11
D12
VDDIO
TEST
JTAGSEL
I
–
–
–
–
–
–
–
–
–
–
I, PD
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 33
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
LFBGA/
TFBGA
Ball
UFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO
Peripheral
A
PIO
Peripheral
B
PIO
Peripheral
C
PIO
Peripheral
D
Reset
State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
29,33,50,8
1,107
E8,H5,H8
D5, G10,
K5
VDDCOR
E
Power
VDDCOR
E
–
–
–
–
–
–
–
–
–
–
–
–
123
J7
D8
VDDPLL
Power
VDDPLL
–
–
–
–
–
–
–
–
–
–
–
–
134
E7
B4
VDDUTMI I
Power
VDDUTMI I
–
–
–
–
–
–
–
–
–
–
–
–
136
B4
A5
VDDUTMI I
USBHS
HSDM
I/O
–
–
–
–
–
–
–
–
–
–
–
137
A4
A4
VDDUTMI I
USBHS
HSDP
I/O
–
–
–
–
–
–
–
–
–
–
–
44,61,95,1
15,135,138
F5, F6, G4,
G5, G6, G7
C5, D3,
D10, H10,
K4, K8
GND
Ground
GND
–
–
–
–
–
–
–
–
–
–
–
–
--
D5
E3
GNDANA
Ground
GNDANA
–
–
–
–
–
–
–
–
–
–
–
–
-
E5
B5
GNDUTM I
Ground
GNDUTM I
–
–
–
–
–
–
–
–
–
–
–
–
-
E6
B3
GNDPLL
USB
Ground
GNDPLL
USB
–
–
–
–
–
–
–
–
–
–
–
–
-
F7
D9
GNDPLL
Ground
GNDPLL
–
–
–
–
–
–
–
–
–
–
–
–
139
B3
C4
VDDUTMI
C
Power
VDDUTMI
C
–
–
–
–
–
–
–
–
–
–
–
–
140
C4
A3
–
VBG
VBG
I
–
–
–
–
–
–
–
–
–
–
–
143
F8
D4
VDDPLL
USB
Power
VDDPLL
USB
–
–
–
–
–
–
–
–
–
–
–
–
Notes:
1. WKUPx can be used if the PIO Controller defines the I/O line as “input”.
2. To select this extra function, refer to the 32.5.14. Parallel Capture Mode section in the Parallel Input/Output
Controller (PIO) chapter.
3. PIODCEN1/PIODCx has priority over WKUPx. Refer to the 32.5.14. Parallel Capture Mode section in the PIO
chapter.
4. Refer to the 23.4.2. Slow Clock Generator section in the Supply Controller (SUPC) chapter.
5. To select this extra function, refer to the 33.5.2.1. I/O Lines section in the External Bus Interface (EBI) chapter.
This selection is independent of the PIO line configuration. PIO lines must be configured according to required
settings (PU or PD).
6. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines section in
the EBI chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”.
7. Analog input has priority over RTCOUTx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines
section in the EBI chapter. Refer to the 27.5.8. Waveform Generation section in the Real-Time Clock (RTC)
chapter to select RTCOUTx.
8. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines section in
the EBI chapter. To select PIODCEN2, refer to the 32.5.14. Parallel Capture Mode in the PIO chapter.
9. Refer to the System I/O Configuration Register (19.4.7. CCFG_SYSIO) in the Bus Matrix (MATRIX) chapter.
10. Refer to the 30.5.3. Main Crystal Oscillator section in the Clock Generator chapter. This selection is
independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx
(O).
11. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. Refer to
the DACC Channel Enable Register in the Digital-to-Analog Converter Controller (DACC) chapter.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 34
SAM E70/S70/V70/V71
Package and Pinout
6.3
100-lead Packages
6.3.1
100-pin LQFP Package Outline
Figure 6-4. Orientation of the 100-lead LQFP Package
75
51
76
50
100
26
1
6.3.2
25
100-ball TFBGA Package Outline
The 100-ball TFBGA package has a 0.8 mm ball pitch and respects Green standards. Its dimensions are 9 x 9 x 1.1
mm. The figure below shows the orientation of the 100-ball TFBGA Package.
Figure 6-5. Orientation of the 100-ball TFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
BALL A1
6.3.3
A
B
C
D
E
F
G
H
J
K
100-ball VFBGA Package Outline
100-ball VFBGA Package Outline
The 100-ball VFBGA package has a 0.65 mm ball pitch and respects Green standards. The dimensions are 7mm x
7mm x 1.0 mm.
The following figure shows the orientation of the 100-ball VFBGA Package.
Figure 6-6. 100-ball VFBGA Package Outline
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 35
SAM E70/S70/V70/V71
Package and Pinout
6.4
100-lead Package Pinout
Table 6-2. 100-lead Package Pinout
LQFP Pin
VFBGA
Ball
TFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO Peripheral A
PIO Peripheral B
PIO Peripheral C
PIO Peripheral D
Reset State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir, PU,
PD, HiZ, ST
72
D8
D8
VDDIO
GPIO_AD
PA0
I/O
WKUP0(1)
I
PWMC0_PWMH0
O
TIOA0
I/O
A17
O
I2SC0_MCK
–
PIO, I, PU, ST
70
C10
C10
VDDIO
GPIO_AD
PA1
I/O
WKUP1(1)
I
PWMC0_PWML0
O
TIOB0
I/O
A18
O
I2SC0_CK
–
PIO, I, PU, ST
66
D10
D10
VDDIO
GPIO
PA2
I/O
WKUP2(1)
I
PWMC0_PWMH1
O
–
–
DATRG
I
–
–
PIO, I, PU, ST
64
F9
F9
VDDIO
GPIO_AD
PA3
I/O
PIODC0(2)
I
TWD0
I/O
LONCOL1
I
PCK2
O
–
–
PIO, I, PU, ST
55
H10
H10
VDDIO
GPIO
PA4
I/O
WKUP3/
PIODC1(3)
I
TWCK0
O
TCLK0
I
UTXD1
O
–
–
PIO, I, PU, ST
52
H9
H9
VDDIO
GPIO_AD
PA5
I/O
WKUP4/
PIODC2(3)
I
PWMC1_PWML3
O
ISI_D4
I
URXD1
I
–
–
PIO, I, PU, ST
24
J2
J2
VDDIO
CLOCK
PA7
I/O
XIN32(4)
I
–
–
PWMC0_PWMH3
–
–
–
–
–
PIO, HiZ
25
K2
K2
VDDIO
CLOCK
PA8
I/O
XOUT32(4)
O
PWMC1_PWMH3
O
AFE0_ADTRG
I
–
–
–
–
PIO, HiZ
54
J9
J9
VDDIO
GPIO_AD
PA9
I/O
WKUP6/
PIODC3(3)
I
URXD0
I
ISI_D3
I
PWMC0_PWMFI0
I
–
–
PIO, I, PU, ST
46
K9
K9
VDDIO
GPIO_AD
PA10
I/O
PIODC4(2)
I
UTXD0
O
PWMC0_PWMEXTRG0
I
RD
I
–
–
PIO, I, PU, ST
44
J8
J8
VDDIO
GPIO_AD
PA11
I/O
WKUP7/
PIODC5(3)
I
QCS
O
PWMC0_PWMH0
O
PWMC1_PWML0
O
–
–
PIO, I, PU, ST
48
K10
K10
VDDIO
GPIO_AD
PA12
I/O
PIODC6(2)
I
QIO1
I/O
PWMC0_PWMH1
O
PWMC1_PWMH0
O
–
–
PIO, I, PU, ST
27
G5
G5
VDDIO
GPIO_AD
PA13
I/O
PIODC7(2)
I
QIO0
I/O
PWMC0_PWMH2
O
PWMC1_PWML1
O
–
–
PIO, I, PU, ST
34
H6
H6
VDDIO
GPIO_CLK
PA14
I/O
WKUP8/
PIODCEN1(3)
I
QSCK
O
PWMC0_PWMH3
O
PWMC1_PWMH1
O
–
–
PIO, I, PU, ST
33
J6
J6
VDDIO
GPIO_AD
PA15
I/O
–
I
D14
I/O
TIOA1
I/O
PWMC0_PWML3
O
I2SC0_WS
–
PIO, I, PU, ST
30
J5
J5
VDDIO
GPIO_AD
PA16
I/O
–
I
D15
I/O
TIOB1
I/O
PWMC0_PWML2
O
I2SC0_DI
–
PIO, I, PU, ST
16
G1
G1
VDDIO
GPIO_AD
PA17
I/O
AFE0_AD6(5)
I
QIO2
I/O
PCK1
O
PWMC0_PWMH3
O
–
–
PIO, I, PU, ST
15
G2
G2
VDDIO
GPIO_AD
PA18
I/O
AFE0_AD7(5)
I
PWMC1_PWMEXTRG1
I
PCK2
O
A14
O
–
–
PIO, I, PU, ST
14
F1
F1
VDDIO
GPIO_AD
PA19
I/O
AFE0_AD8/
WKUP9(6)
I
–
–
PWMC0_PWML0
O
A15
O
I2SC1_MCK
–
PIO, I, PU, ST
13
F2
F2
VDDIO
GPIO_AD
PA20
I/O
AFE0_AD9/
WKUP10(6)
I
–
–
PWMC0_PWML1
O
A16
O
I2SC1_CK
–
PIO, I, PU, ST
21
J1
J1
VDDIO
GPIO_AD
PA21
I/O
AFE0_AD1/
PIODCEN2(8)
I
RXD1
I
PCK1
O
PWMC1_PWMFI0
I
–
–
PIO, I, PU, ST
26
J3
J3
VDDIO
GPIO_AD
PA22
I/O
PIODCCLK(2)
I
RK
I/O
PWMC0_PWMEXTRG1
I
NCS2
O
–
–
PIO, I, PU, ST
31
K5
K5
VDDIO
GPIO_AD
PA23
I/O
–
–
SCK1
I/O
PWMC0_PWMH0
O
A19
O
PWMC1_PWML2
O
PIO, I, PU, ST
38
K7
K7
VDDIO
GPIO_AD
PA24
I/O
–
–
RTS1
O
PWMC0_PWMH1
O
A20
O
ISI_PCK
I
PIO, I, PU, ST
40
H7
H7
VDDIO
GPIO_AD
PA25
I/O
–
–
CTS1
I
PWMC0_PWMH2
O
A23
O
MCCK
O
PIO, I, PU, ST
42
K8
K8
VDDIO
GPIO
PA26
I/O
–
–
DCD1
I
TIOA2
O
MCDA2
I/O
PWMC1_PWMFI1
I
PIO, I, PU, ST
50
H8
H8
VDDIO
GPIO_AD
PA27
I/O
–
–
DTR1
O
TIOB2
I/O
MCDA3
I/O
ISI_D7
79
A9
A9
VDDIO
GPIO
PA28
I/O
–
–
DSR1
I
TCLK1
I
MCCDA
I/O
PWMC1_PWMFI2
I
PIO, I, PU, ST
82
C7
C7
VDDIO
GPIO
PA30
I/O
WKUP11(1)
I
PWMC0_PWML2
O
PWMC1_PWMEXTRG0
I
MCDA0
I/O
I2SC0_D0
–
PIO, I, PU, ST
83
A7
A7
VDDIO
GPIO_AD
PA31
I/O
–
–
SPI0_NPCS1
I/O
PCK2
O
MCDA1
I/O
PWMC1_PWMH2
O
PIO, I, PU, ST
12
E1
E1
VDDIO
GPIO
PB0
I/O
AFE0_AD10/
RTCOUT0(7)
I
PWMC0_PWMH0
O
–
–
RXD0
I
TF
I/O
PIO, I, PU, ST
11
E2
E2
VDDIO
GPIO
PB1
I/O
AFE1_AD0/
RTCOUT1(7)
I
PWMC0_PWMH1
O
GTSUCOMP
O
TXD0
I/O
TK
I/O
PIO, I, PU, ST
17
H1
H1
VDDIO
GPIO
PB2
I/O
AFE0_AD5(5)
I
CANTX0–
O–
–
–
CTS0
I
SPI0_NPCS0
I/O
PIO, I, PU, ST
20
H2
H2
VDDIO
GPIO_AD
PB3
I/O
AFE0_AD2/
WKUP12(6)
I
CANRX0–
I–
PCK2
O
RTS0
O
ISI_D2
I
PIO, I, PU, ST
74
B9
B9
VDDIO
GPIO_MLB
PB4
I/O
TDI(9)
I
TWD1
I/O
PWMC0_PWMH2
O
MLBCLK–
I–
TXD1
I/O
PIO, I, PD, ST
77
C8
C8
VDDIO
GPIO_MLB
PB5
I/O
TDO/
TRACESWO/
WKUP13(9)
O
TWCK1
O
PWMC0_PWML0
O
MLBDAT–
I/O–
TD
O
O, PU
57
G8
G8
VDDIO
GPIO
PB6
I/O
SWDIO/TMS(9)
I
–
–
–
–
–
–
–
–
PIO,I,ST
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
PIO, I, PU, ST
DS60001527G-page 36
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
63
VFBGA
Ball
E9
TFBGA
Ball
E9
Power Rail
VDDIO
I/O Type
GPIO
Primary
Alternate
PIO Peripheral A
PIO Peripheral B
PIO Peripheral C
PIO Peripheral D
Reset State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir, PU,
PD, HiZ, ST
PB7
I/O
SWCLK/TCK(9)
I
–
–
–
–
–
–
–
–
PIO,I,ST
98
A2
A2
VDDIOP
CLOCK
PB8
I/O
XOUT(10)
O
–
–
–
–
–
–
–
–
PIO, HiZ
99
A1
A1
VDDIOP
CLOCK
PB9
I/O
XIN(10)
I
–
–
–
–
–
–
–
–
PIO, HiZ
61
F8
F8
VDDIO
GPIO
PB12
I/O
ERASE(9)
I
PWMC0_PWML1
O
GTSUCOMP
O
–
–
PCK0
O
PIO, I, PD, ST
100
B2
B2
VDDIO
GPIO_AD
PB13
I/O
DAC0(11)
O
PWMC0_PWML2
O
PCK0
O
SCK0
I/O
–
–
PIO, I, PU, ST
1
B1
C1
VDDIO
GPIO_AD
PD0
I/O
DAC1(11)
I
GTXCK
I
PWMC1_PWML0
O
SPI1_NPCS1
DCD0
I
PIO, I, PU, ST
92
D3
D2
VDDIO
GPIO
PD1
I/O
–
–
GTXEN
O
PWMC1_PWMH0
O
SPI1_NPCS2
I/O
DTR0
O
PIO, I, PU, ST
91
E3
E3
VDDIO
GPIO
PD2
I/O
–
–
GTX0
O
PWMC1_PWML1
O
SPI1_NPCS3
I/O
DSR0
I
PIO, I, PU, ST
89
B5
B5
VDDIO
GPIO
PD3
I/O
–
–
GTX1
O
PWMC1_PWMH1
O
UTXD4
O
RI0
I
PIO, I, PU, ST
88
A5
A5
VDDIO
GPIO_CLK
PD4
I/O
–
–
GRXDV
I
PWMC1_PWML2
O
TRACED0
O
DCD2
I
PIO, I, PU, ST
87
D5
D5
VDDIO
GPIO_CLK
PD5
I/O
–
–
GRX0
I
PWMC1_PWMH2
O
TRACED1
O
DTR2
O
PIO, I, PU, ST
85
B6
B6
VDDIO
GPIO_CLK
PD6
I/O
–
–
GRX1
I
PWMC1_PWML3
O
TRACED2
O
DSR2
I
PIO, I, PU, ST
84
A8
A6
VDDIO
GPIO_CLK
PD7
I/O
–
–
GRXER
I
PWMC1_PWMH3
O
TRACED3
O
RI2
I
PIO, I, PU, ST
80
B7
B7
VDDIO
GPIO_CLK
PD8
I/O
–
–
GMDC
O
PWMC0_PWMFI1
I
–
–
TRACECLK
O
PIO, I, PU, ST
78
B8
B8
VDDIO
GPIO_CLK
PD9
I/O
–
–
GMDIO
I/O
PWMC0_PWMFI2
AFE1_ADTRG
I
–
O
PIO, I, PU, ST
71
C9
C9
VDDIO
GPIO_MLB
PD10
I/O
–
–
GCRS
I
PWMC0_PWML0
O
TD
O
MLBSIG–
I/O–
PIO, I, PD, ST
69
D9
D9
VDDIO
GPIO_AD
PD11
I/O
–
–
GRX2
I
PWMC0_PWMH0
O
GTSUCOMP
O
ISI_D5
I
PIO, I, PU, ST
65
E10
E10
VDDIO
GPIO_AD
PD12
I/O
–
–
GRX3
I
CANTX1–
O–
SPI0_NPCS2
O
ISI_D6
I
PIO, I, PU, ST
62
E8
E8
VDDIO
GPIO_AD
PD13
I/O
–
–
GCOL
I
–
–
–
O
–
–
PIO, I, PU, ST
59
F10
F10
VDDIO
GPIO_AD
PD14
I/O
–
–
GRXCK
I
–
–
–
O
–
–
PIO, I, PU, ST
75
B10
B10
VDDIO
GPIO_AD
PD15
I/O
–
–
GTX2
O
RXD2
I
NWR1/NBS1
O
–
–
PIO, I, PU, ST
56
G9
G9
VDDIO
GPIO_AD
PD16
I/O
–
–
GTX3
O
53
J10
J10
VDDIO
GPIO_AD
PD17
I/O
–
–
GTXER
49
K6
K6
VDDIO
GPIO_AD
PD18
I/O
–
–
NCS1
O
RTS2
47
K4
K4
VDDIO
GPIO_AD
PD19
I/O
–
–
NCS3
O
CTS2
45
K3
K3
VDDIO
GPIO
PD20
I/O
–
–
PWMC0_PWMH0
O
SPI0_MISO
43
H5
H5
VDDIO
GPIO_AD
PD21
I/O
–
–
PWMC0_PWMH1
O
SPI0_MOSI
41
J4
J4
VDDIO
GPIO_AD
PD22
I/O
–
–
PWMC0_PWMH2
O
37
G4
G4
VDDIO
GPIO_AD
PD24
I/O
–
–
PWMC0_PWML0
35
H3
H3
VDDIO
GPIO_AD
PD25
I/O
–
–
36
G3
G3
VDDIO
GPIO
PD26
I/O
–
–
32
H4
H4
VDDIO
GPIO_AD
PD27
I/O
–
–
51
J7
J7
VDDIO
GPIO_AD
PD28
I/O
WKUP5(1)
TXD2
I/O
–
O
–
–
PIO, I, PU, ST
SCK2
I/O
–
O
–
–
PIO, I, PU, ST
O
URXD4
I
–
–
PIO, I, PU, ST
I
UTXD4
O
–
–
PIO, I, PU, ST
I/O
GTSUCOMP
O
–
–
PIO, I, PU, ST
I/O
TIOA11
I/O
ISI_D1
I
PIO, I, PU, ST
SPI0_SPCK
O
TIOB11
I/O
ISI_D0
I
PIO, I, PU, ST
O
RF
I/O
TCLK11
I
ISI_HSYNC
I
PIO, I, PU, ST
PWMC0_PWML1
O
SPI0_NPCS1
I/O
URXD2
I
ISI_VSYNC
I
PIO, I, PU, ST
PWMC0_PWML2
O
TD
O
UTXD2
O
UTXD1
O
PIO, I, PU, ST
PWMC0_PWML3
O
SPI0_NPCS3
O
TWD2
O
ISI_D8
I
PIO, I, PU, ST
URXD3
I
CANRX1
I–
TWCK2
O
ISI_D9
I
PIO, I, PU, ST
23
K1
K1
VDDIO
GPIO_AD
PD30
I/O
AFE0_AD0(5)
I
UTXD3
0
–
–
–
–
ISI_D10
I
PIO, I, PU, ST
2
C1
B1
VDDIO
GPIO_AD
PD31
I/O
–
–
QIO3
I/O
UTXD3
O
PCK2
O
ISI_D11
I
PIO, I, PU, ST
4
C3
C3
VDDOUT
Power
VDDOUT
I
–
–
–
–
–
–
–
–
–
–
–
5
C2
C2
VDDIN
Power
VDDIN
I
–
–
–
–
–
–
–
–
–
–
–
6
D2
D3
GND
Ground
VREFN
I
–
–
–
–
–
–
–
–
–
–
–
9
D1
D1
VDDIO
Power
VREFP
I
–
–
–
–
–
–
–
–
–
–
–
58
G10
G10
VDDIO
RST
NRST
I
–
–
–
–
–
–
–
–
–
–
PIO, I, PU
60
F7
F7
VDDIO
TEST
TST
I
–
–
–
–
–
–
–
–
–
–
I, PD
19, 28,
68, 81
C5, F3, G7
C5, F3, G7
VDDIO
Power
VDDIO
I
–
–
–
–
–
–
–
–
–
–
–
73
A10
A10
VDDIO
TEST
JTAGSEL
I
–
–
–
–
–
–
–
–
–
–
I, PD
18, 22,
39, 76
C6, D6, G6
C6, D6, G6
VDDCORE
Power
VDDCORE
I
–
–
–
–
–
–
–
–
–
–
–
86
D7
D7
VDDPLL
Power
VDDPLL
I
–
–
–
–
–
–
–
–
–
–
–
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 37
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
VFBGA
Ball
TFBGA
Ball
Power Rail
I/O Type
Primary
Alternate
PIO Peripheral A
PIO Peripheral B
PIO Peripheral C
PIO Peripheral D
Reset State
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir, PU,
PD, HiZ, ST
93
E5
E5
VDDUTMII
Power
VDDUTMII
I
–
–
–
–
–
–
–
–
–
–
–
94
A4
A4
VDDUTMII
USBHS
HSDM
I/O
–
–
–
–
–
–
–
–
–
–
–
95
B4
B4
VDDUTMII
USBHS
HSDP
I/O
–
–
–
–
–
–
–
–
–
–
–
3, 7, 8,
10, 29, 67
E7, F4, F5,
F6
E7, F4, F5,
F6
GND
Ground
GND
I
–
–
–
–
–
–
–
–
–
–
–
D4
D4
GNDANA
Ground
GNDANA
I
–
–
–
–
–
–
–
–
–
–
–
A6
A8
GNDUTMI
Ground
GNDUTMI
I
–
–
–
–
–
–
–
–
–
–
–
C4
C4
GNDPLLU
SB
Ground
GNDPLLU
SB
I
–
–
–
–
–
–
–
–
–
–
–
E6
E4
GNDPLL
Ground
GNDPLL
I
–
–
–
–
–
–
–
–
–
–
–
96
B3
B3
VDDUTMI
C
Power
VDDUTMI
C
I
–
–
–
–
–
–
–
–
–
–
–
97
A3
A3
–
VBG
VBG
I
–
–
–
–
–
–
–
–
–
–
–
90
E4
E6
VDDPLLU
SB
Power
VDDPLLU
SB
I
–
–
–
–
–
–
–
–
–
–
–
Notes:
1. WKUPx can be used if the PIO Controller defines the I/O line as “input”.
2. To select this extra function, refer to the 32.5.14. Parallel Capture Mode section in the “Parallel Input/Output
Controller (PIO)” chapter.
3. PIODCEN1/PIODCx has priority over WKUPx. Refer to the 32.5.14. Parallel Capture Mode section in the
“PIO” chapter.
4. Refer to the 23.4.2. Slow Clock Generator section in the “Supply Controller (SUPC)” chapter.
5. To select this extra function, refer to the 33.5.2.1. I/O Lines section in the “External Bus Interface (EBI)”
chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to
required settings (PU or PD).
6. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines section in
the “EBI” chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”.
7. Analog input has priority over RTCOUTx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines
section in the “EBI” chapter. Refer to the 27.5.8. Waveform Generation section in the “Real-Time Clock (RTC)”
chapter to select RTCOUTx.
8. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines section in
the “EBI” chapter. To select PIODCEN2, refer to the 32.5.14. Parallel Capture Mode in the “PIO” chapter.
9. Refer to the System I/O Configuration Register (19.4.7. CCFG_SYSIO) in the “Bus Matrix (MATRIX)” chapter.
10. Refer to the 30.5.3. Main Crystal Oscillator section in the “Clock Generator” chapter. This selection is
independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx
(O).
11. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. Refer to
the DACC Channel Enable Register in the “Digital-to-Analog Converter Controller (DACC)” chapter.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 38
SAM E70/S70/V70/V71
Package and Pinout
6.5
64-lead Package
6.5.1
64-lead QFN Wettable Flanks Package Outline
Figure 6-7. Orientation of the 64-lead QFN Wettable Flanks Package
6.5.2
64-pin LQFP Package Outline
Figure 6-8. Orientation of the 64-pin LQFP Package
33
48
49
32
64
17
16
1
6.6
64-lead Package Pinout
Table 6-3. 64-lead Package Pinout
LQFP Pin
QFN Pin
(11)
Power Rail
I/O Type
Primary
PIO Peripheral A
PIO Peripheral B
PIO Peripheral CDir
PIO Peripheral DDir
Reset State
Signal
Dir
Alternate
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
40
40
VDDIO
GPIO_AD
PA3
I/O
PIODC0(1)
I
TWD0(2)
I/O
LONCOL1
I
PCK2
O
–
–
PIO, I, PU,
ST
34
34
VDDIO
GPIO
PA4
I/O
WKUP3/
PIODC1(2)
I
TWCK0
O
TCLK0
I
UTXD1
O
–
–
PIO, I, PU,
ST
32
32
VDDIO
GPIO_AD
PA5
I/O
WKUP4/
PIODC2(2)
I
PWMC1_P
WML3
O
ISI_D4
I
URXD1
I
–
–
PIO, I, PU,
ST
15
15
VDDIO
CLOCK
PA7
I/O
XIN32(3)
I
–
–
PWMC0_P
WMH3
–
–
–
–
–
PIO, HiZ
16
16
VDDIO
CLOCK
PA8
I/O
XOUT32(3)
O
PWMC1_P
WMH3
O
AFE0_ADT
RG
I
–
–
–
–
PIO, HiZ
33
33
VDDIO
GPIO_AD
PA9
I/O
WKUP6/
PIODC3(2)
I
URXD0
I
ISI_D3
I
PWMC0_P
WM FI0
I
–
–
PIO, I, PU,
ST
28
28
VDDIO
GPIO_AD
PA10
I/O
PIODC4(1)
I
UTXD0
O
PWMC0_P
WMEXT
RG0
I
RD
I
–
–
PIO, I, PU,
ST
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 39
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
QFN Pin
(11)
Power Rail
I/O Type
Primary
PIO Peripheral A
PIO Peripheral B
PIO Peripheral CDir
PIO Peripheral DDir
Reset State
Signal
Dir
Alternate
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
27
27
VDDIO
GPIO_AD
PA11
I/O
WKUP7/
PIODC5(2)
I
QCS
O
PWMC0_P
WMH0
O
PWMC1_P
WM L0
O
–
–
PIO, I, PU,
ST
29
29
VDDIO
GPIO_AD
PA12
I/O
PIODC6(1)
I
QIO1
I/O
PWMC0_P
WMH1
O
PWMC1_P
WM H0
O
–
–
PIO, I, PU,
ST
18
18
VDDIO
GPIO_AD
PA13
I/O
PIODC7(1)
I
QIO0
I/O
PWMC0_P
WMH2
O
PWMC1_P
WM L1
O
–
–
PIO, I, PU,
ST
19
19
VDDIO
GPIO_CLK
PA14
I/O
WKUP8/
PIODCEN
1(2)
I
QSCK
O
PWMC0_P
WMH3
O
PWMC1_P
WM H1
O
–
–
PIO, I, PU,
ST
12
12
VDDIO
GPIO_AD
PA21
I/O
AFE0_AD1/
PIODCEN2(
7)
I
RXD1
I
PCK1
O
PWMC1_P
WM FI0
I
–
–
PIO, I, PU,
ST
17
17
VDDIO
GPIO_AD
PA22
I/O
PIODCCLK(
1)
I
RK
I/O
PWMC0_P
WMEXT
RG1
I
–
O
–
–
PIO, I, PU,
ST
23
23
VDDIO
GPIO_AD
PA24
I/O
–
–
RTS1
O
PWMC0_P
WMH1
O
A20
O
ISI_PCK
I
PIO, I, PU,
ST
30
30
VDDIO
GPIO_AD
PA27
I/O
–
–
DTR1
O
TIOB2
I/O
–
I/O
ISI_D7
I
PIO, I, PU,
ST
8
8
VDDIO
GPIO
PB0
I/O
AFE0_AD10
/
RTCOUT0(
6)
I
PWMC0_P
WMH0
O
–
–
RXD0
I
TF
I/O
PIO, I, PU,
ST
7
7
VDDIO
GPIO
PB1
I/O
AFE1_AD0/
RTCOUT1(
6)
I
PWMC0_P
WMH1
O
GTSUCOM
P
O
TXD0
I/O
TK
I/O
PIO, I, PU,
ST
9
9
VDDIO
GPIO
PB2
I/O
AFE0_AD5(
4)
I
CANTX0
O
–
–
CTS0
I
–
I/O
PIO, I, PU,
ST
11
11
VDDIO
GPIO_AD
PB3
I/O
AFE0_AD2/
WKUP
12(6)
I
CANRX0
I
PCK2
O
RTS0
O
ISI_D2
I
PIO, I, PU,
ST
46
46
VDDIO
GPIO_MLB
PB4
I/O
TDI(8)
I
TWD1
I/O
PWMC0_P
WMH2
O
MLBCLK
I
TXD1
I/O
-
-
PIO, I, PD,
ST
PWMC0_P
WML0
O
MLBDAT
I/O
TD
O
O, PU
-
-
47
47
VDDIO
GPIO_MLB
PB5
I/O
TDO/
TRACESW
O/
WKUP13(8)
O
TWCK1
O
35
35
VDDIO
GPIO
PB6
I/O
SWDIO/
TMS(8)
I
–
–
–
–
–
–
–
–
PIO,I,ST
39
39
VDDIO
GPIO
PB7
I/O
SWCLK/
TCK(8)
I
–
–
–
–
–
–
–
–
PIO,I,ST
62
63
VDDIO
CLOCK
PB8
I/O
XOUT(9)
O
–
–
–
–
–
–
–
–
PIO, HiZ
63
64
VDDIO
CLOCK
PB9
I/O
XIN(9)
I
–
–
–
–
–
–
–
–
PIO, HiZ
I
PWMC0_P
WML1
O
GTSUCOM
P
O
–
–
PCK0
O
PIO, I, PD,
ST
38
38
VDDIO
GPIO
PB12
I/O
ERASE(8)
1
2
VDDIO
GPIO_AD
PD0
I/O
DAC1(11)
I
GTXCK
I
PWMC1_P
WML0
O
–
I/O
DCD0
I
PIO, I, PU,
ST
57
57
VDDIO
GPIO
PD1
I/O
–
–
GTXEN
O
PWMC1_P
WMH0
O
–
I/O
DTR0
O
PIO, I, PU,
ST
56
56
VDDIO
GPIO
PD2
I/O
–
–
GTX0
O
PWMC1_P
WML1
O
–
I/O
DSR0
I
PIO, I, PU,
ST
55
55
VDDIO
GPIO
PD3
I/O
–
–
GTX1
O
PWMC1_P
WMH1
O
UTXD4
O
RI0
I
PIO, I, PU,
ST
54
54
VDDIO
GPIO_CLK
PD4
I/O
–
–
GRXDV
I
PWMC1_P
WML2
O
TRACED0
O
–
–
PIO, I, PU,
ST
53
53
VDDIO
GPIO_CLK
PD5
I/O
–
–
GRX0
I
PWMC1_P
WMH2
O
TRACED1
O
–
–
PIO, I, PU,
ST
51
51
VDDIO
GPIO_CLK
PD6
I/O
–
–
GRX1
I
PWMC1_P
WML3
O
TRACED2
O
–
–
PIO, I, PU,
ST
50
50
VDDIO
GPIO_CLK
PD7
I/O
–
–
GRXER
I
PWMC1_P
WMH3
O
TRACED3
O
–
–
PIO, I, PU,
ST
49
49
VDDIO
GPIO_CLK
PD8
I/O
–
–
GMDC
O
PWMC0_P
WMFI1
I
–
–
TRACECLK
O
PIO, I, PU,
ST
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 40
SAM E70/S70/V70/V71
Package and Pinout
...........continued
LQFP Pin
QFN Pin
(11)
Power Rail
I/O Type
Primary
PIO Peripheral A
PIO Peripheral B
PIO Peripheral CDir
PIO Peripheral DDir
Reset State
Signal
Dir
Alternate
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal
Dir
Signal, Dir,
PU, PD,
HiZ, ST
48
48
VDDIO
GPIO_CLK
PD9
I/O
–
–
GMDIO
I/O
PWMC0_P
WMFI2
I
AFE1_ADT
RG
I
–
–
PIO, I, PU,
ST
44
44
VDDIO
GPIO_MLB
PD10
I/O
–
–
GCRS
I
PWMC0_P
WML0
O
TD
O
MLBSIG
I/O
-
-
PIO, I, PD,
ST
43
43
VDDIO
GPIO_AD
PD11
I/O
–
–
GRX2
I
PWMC0_P
WMH0
O
GTSUCOM
P
O
ISI_D5
I
PIO, I, PU,
ST
41
41
VDDIO
GPIO_AD
PD12
I/O
–
–
GRX3
I
–
O
–
O
ISI_D6
I
PIO, I, PU,
ST
26
26
VDDIO
GPIO_AD
PD21
I/O
–
–
PWMC0_P
WMH1
O
–
I/O
TIOA11
I/O
ISI_D1
I
PIO, I, PU,
ST
25
25
VDDIO
GPIO_AD
PD22
I/O
–
–
PWMC0_P
WMH2
O
–
O
TIOB11
I/O
ISI_D0
I
PIO, I, PU,
ST
22
22
VDDIO
GPIO_AD
PD24
I/O
–
–
PWMC0_P
WML0
O
RF
I/O
TCLK11
I
ISI_HSYNC
I
PIO, I, PU,
ST
20
20
VDDIO
GPIO_AD
PD25
I/O
–
–
PWMC0_P
WML1
O
–
I/O
URXD2
I
ISI_VSYNC
I
PIO, I, PU,
ST
21
21
VDDIO
GPIO
PD26
I/O
–
–
PWMC0_P
WML2
O
TD
O
UTXD2
O
UTXD1
O
PIO, I, PU,
ST
2
3
VDDIO
GPIO_AD
PD31
I/O
–
–
QIO3
I/O
UTXD3
O
PCK2
O
ISI_D11
I
PIO, I, PU,
ST
3
4
VDDOUT
Power
VDDOUT
–
–
–
–
–
–
–
–
–
–
–
–
4
5
VDDIN
Power
VDDIN
–
–
–
–
–
–
–
–
–
–
–
–
5
6
VDDIO
Reference
VREFP
I
–
–
–
–
–
–
–
–
–
–
–
36
36
VDDIO
RST
NRST
I/O
–
–
–
–
–
–
–
–
–
–
PIO, I, PU
37
37
VDDIO
TEST
TST
I
–
–
–
–
–
–
–
–
–
–
I, PD
10, 42, 58
10,42,58
VDDIO
Power
VDDIO
–
–
–
–
–
–
–
–
–
–
–
–
45
45
VDDIO
TEST
JTAGSEL
I
–
–
–
–
–
–
–
–
–
–
I, PD
13, 24, 61
13,24,61
VDDCORE
Power
VDDCOR E
–
–
–
–
–
–
–
–
–
–
–
–
52
52
VDDPLL
Power
VDDPLL
–
–
–
–
–
–
–
–
–
–
–
–
59
59
VDDUTMII
USBHS
DM
I/O
–
–
–
–
–
–
–
–
–
–
–
60
60
VDDUTMII
USBHS
DP
I/O
–
–
–
–
–
–
–
–
–
–
–
14, 31
14,31
GND
Ground
GND
–
–
–
–
–
–
–
–
–
–
–
–
6
-
GND
Ground
GND
-
–
–
–
-
–
-
–
–
–
–
–
64
1
VDDPLLUS
B
Power
VDDPLLU
SB
–
–
–
–
–
–
–
–
–
–
–
–
--
62
--
VBG
VBG
I
–
–
–
–
–
-
–
–
–
–
–
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 41
SAM E70/S70/V70/V71
Package and Pinout
Notes:
1. To select this extra function, refer to the 32.5.14. Parallel Capture Mode section in the “Parallel Input/Output
Controller (PIO)” chapter.
2. PIODCEN1/PIODCx has priority over WKUPx. Refer to the 32.5.14. Parallel Capture Mode section in the
“PIO” chapter.
3. Refer to the 23.4.2. Slow Clock Generator section in the “Supply Controller (SUPC)” chapter.
4. To select this extra function, refer to the 33.5.2.1. I/O Lines section in the “External Bus Interface (EBI)”
chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to
required settings (PU or PD).
5. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines section in
the “EBI” chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”.
6. Analog input has priority over RTCOUTx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines
section in the “EBI” chapter. Refer to the 27.5.8. Waveform Generation section in the “Real-Time Clock (RTC)”
chapter to select RTCOUTx.
7. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1. I/O Lines section in
the “EBI” chapter. To select PIODCEN2, refer to the 32.5.14. Parallel Capture Mode in the “PIO” chapter.
8. Refer to the System I/O Configuration Register (19.4.7. CCFG_SYSIO) in the “Bus Matrix (MATRIX)” chapter.
9. Refer to the 30.5.3. Main Crystal Oscillator section in the Clock Generator chapter. This selection is
independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx
(O).
10. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. Refer to
the DACC Channel Enable Register in the “Digital-to-Analog Converter Controller (DACC)” chapter.
11. The exposed pad of the QFN64 package MUST be connected to ground.
Note: Pinout limitations prevent full support of USART functionality. The following table lists which USART functions
are available.
Table 6-4. USART Functions
Availability
USART Pins
Function
Description
Pin Name
USART0
USART1
SCK
n
n
SCK
Serial Clock
TXD
Transmit Data
UTXDx
y
y
RXD
Receive Data
URXDx
y
y
RTS
Request to Send
RTSx
y
y
CTS
Clear To Send
CTSx
y
n
DTR
Data Terminal Ready
DTRx
y
y
DSR
Data Set Ready
DSRx
y
n
DCD
Data Carrier Detect
DCDx
y
n
RIx
y
n
LONCOLx
n
y
RI
LCOL
Ring Indicator
LON Collision Detection
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 42
SAM E70/S70/V70/V71
Power Considerations
7.
Power Considerations
7.1
Power Supplies
The following table defines the power supply rails of the SAM E70/S70/V70/V71 .
Table 7-1. Power Supplies
Name
Powers
GND
Core, embedded memories and
peripherals.
VDDIO
GND
Peripheral I/O lines (Input/Output
Buffers), backup part, 1 Kbytes
of backup SRAM, 32 kHz crystal
oscillator, oscillator pads. For USB
operations, VDDIO voltage range
must be between 3.0V and 3.6V.
VDDIN
GND, GNDANA
Voltage regulator input. Supplies also
the ADC, DAC, and analog voltage
comparator.
VDDPLL
GND, GNDPLL
PLLA and the fast RC oscillator.
VDDPLLUSB
GND, GNDPLLUSB
UTMI PLL and 3 MHz to 20 MHz
oscillator.
VDDUTMII
GNDUTMI
USB transceiver interface. Must be
connected to VDDIO.
VDDUTMIC
GNDUTMI
USB transceiver core.
VDDCORE
7.2
Associated Ground
Power Constraints
The following power constraints are apply to SAM E70/S70/V70/V71 devices. Deviating from these constraints may
lead to unpredictable results.
•
•
•
•
7.2.1
VDDIN and VDDIO must have the same level
VDDIN and VDDIO must always be higher than or equal to VDDCORE
VDDCORE, VDDPLL and VDDUTMIC voltage levels must not vary by more than 0.6V
For the USB to be operational, VDDUTMII, VDDPLLUSB, VDDIN and VDDIO must be higher than or equal to
3.0V
Powerup
VDDIO and VDDIN must rise simultaneously, prior to VDDCORE, VDDPLL and VDDUTMIC rising. This is respected
if VDDCORE, VDDPLL and VDDUTMIC are supplied by the embedded voltage regulator.
If VDDCORE is powered by an external voltage regulator, VDDIO and VDDIN must reach their minimum operating
voltage before VDDCORE has reached VDDCOREmin. The minimum slope for VDDCORE is defined by:
VDDCOREmin − VT+min / tRESmin
If VDDCORE rises at the same time as VDDIO and VDDIN, the minimum and maximum rising slopes of VDDIO and
VDDIN must be respected. Refer to the section “DC Characteristics”.
In order to prevent any overcurrent at powerup, it is required that VREFP rises simultaneously with VDDIO and
VDDIN.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 43
SAM E70/S70/V70/V71
Power Considerations
Figure 7-1. Powerup Sequence
Supply (V)
VDDIO
VDDIN
VDDPLLUSB
VDDUTMII
VDDx(min)
VDDCORE
VDDPLL
VDDUTMIC
VDDy(min)
VT+
tRST
Time (t)
Related Links
57.2. DC Characteristics
23.4.6. Backup Power Supply Reset
23.4.6.1. Raising the Backup Power Supply
7.2.2
Powerdown
If VDDCORE, VDDPLL and VDDUTMIC are not supplied by the embedded voltage regulator, VDDIO, VDDIN,
VDDPLLUSB and VDDUTMII should fall simultaneously, prior to VDDCORE, VDDPLL and VDDUTMIC falling. The
VDDCORE falling slope must not be faster than 20V/ms.
In order to prevent any overcurrent at powerdown, it is required that VREFP falls simultaneously with VDDIO and
VDDIN.
Figure 7-2. Powerdown Sequence
Supply (V)
VDDIO
VDDIN
VDDPLLUSB
VDDUTMII
VDDx(min)
VDDCORE
VDDPLL
VDDUTMIC
VDDy(min)
Time (t)
7.3
Voltage Regulator
The SAM E70/S70/V70/V71 embeds a voltage regulator that is managed by the Supply Controller.
For adequate input and output power supply decoupling/bypassing, refer to 57.2. DC Characteristics in the Electrical
Characteristics chapter.
7.4
Backup SRAM Power Switch
The SAM E70/S70/V70/V71 embeds a power switch to supply the 1 Kbyte of backup SRAM. It is activated only when
VDDCORE is switched off to ensure retention of the contents of the backup SRAM. When VDDCORE is switched on,
the backup SRAM is powered with VDDCORE.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 44
SAM E70/S70/V70/V71
Power Considerations
To save the power consumption of the backup SRAM, the user can disable the backup SRAM power switch by
clearing the bit SRAMON in the Supply Controller Mode Register (SUPC_MR). By default, after VDDIO rises, the
backup SRAM power switch is enabled.
7.5
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLLA. The Power Management Controller can be used to adapt the core, bus and peripheral
frequencies and to enable and/or disable the peripheral clocks.
7.6
Low-power Modes
The SAM E70/S70/V70/V71 features the following three Low-Power modes:
•
•
•
7.6.1
Backup mode
Wait mode
Sleep mode
Backup Mode
The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is performing
periodic wakeups to perform tasks but not requiring fast startup time.
The Supply Controller, zero-power Power-On Reset (POR), RTT, RTC, backup SRAM, backup registers and 32 kHz
oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the
core supply are off.
Backup mode is based on the Cortex-M7 Deep-Sleep mode with the voltage regulator disabled.
Wakeup from Backup mode is done through WKUP0–13 pins, the supply monitor (SM), the RTT, or an RTC wakeup
event.
Backup mode is entered by using the VROFFbit in the Supply Controller Control Register (SUPC_CR) and the
SLEEPDEEP bit in the Cortex-M7 System Control Register set to 1. Refer to information on Power Management in
the" ARM Cortex-M7 documentation", which is available for download at www.arm.com.
To enter Backup mode, follow these steps:
1.
2.
Set the SLEEPDEEP bit of the Cortex-M7 processor.
Set the VROFF bit of SUPC_CR.
Exit from Backup mode occurs as a result of one of the following enabled wakeup events:
•
•
•
•
WKUP0–13 pins (level transition, configurable debouncing)
Supply Monitor alarm
RTC alarm
RTT alarm
Notes: If PLLA is enabled with the Main Crystal Oscillator as the clock source for Main Clock (MAINCK), the
following sequence must be followed before entering into backup mode:
1. Switch Main Clock (MAINCK) to Slow Clock (SLCK) by using PMC_MCKR.CSS.
2. Disable the PLLA by writing MUL = 0 or DIV = 0.
3. Disable the Main Crystal Oscillator.
4. Add Wait time in the range of milliseconds.
5. Enter backup mode.
7.6.2
Wait Mode
The purpose of Wait mode is to achieve very low-power consumption while maintaining the whole device in a
powered state for a startup time of less than 10 μs.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 45
SAM E70/S70/V70/V71
Power Considerations
In Wait mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered.
Wait mode is entered when the WAITMODE bit is set in CKGR_MOR and the field FLPM is configured to 00 or 01 in
the PMC Fast Startup Mode register (PMC_FSMR).
The Cortex-M is able to handle external events or internal events to wake up the core. This is done by configuring
the external lines WKUP0–13 as fast startup wake-up pins (refer to the “Fast Startup” section). RTC or RTT alarms
or USB wake-up events can be used to wake up the processor. Resume from Wait mode is also achieved when a
debug request occurs and the bit CDBGPWRUPREQ is set in the processor.
To enter Wait mode, first, select the Main RC oscillator as Main Clock and perform the following steps:
1.
2.
3.
4.
5.
Configure the FLPM field in the PMC_FSMR.
Set Flash Wait State at 0.
Set HCLK = MCK by configuring MDIV to 0 in the PMC Host Clock register (PMC_MCKR).
Set the WAITMODE bit in the PMC Clock Generator Main Oscillator register (CKGR_MOR).
Wait for MCKRDY = 1 in the PMC Status register (PMC_SR).
Note: Internal main clock resynchronization cycles are necessary between writing the MOSCRCEN bit and the entry
in Wait mode. Depending on the user application, waiting for the MOSCRCEN bit to be cleared is recommended to
ensure that the core will not execute undesired instructions.
7.6.3
Sleep Mode
The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode,
only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is
application-dependent.
This mode is entered using the instruction Wait for Interrupt (WFI).
Processor wakeup is triggered by an interrupt if the WFI instruction of the Cortex-M processor is used.
7.6.4
Low-Power Mode Summary Table
The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake
up sources can be individually configured. The following table provides a summary of the configurations of the
low-power modes.
Table 7-2. Low-power Mode Configuration Summary
Mode
SUPC, 32 kHz
Oscillator,
RTC, RTT
Backup SRAM
(BRAM),
Backup
Registers
(GPBR),
POR
(Backup Area)
Regulator
Core
Memory
Peripherals
Mode Entry Configuration
Potential
Wakeup
Sources
Core at
Wakeup
PIO State while
in Low-Power
Mode
PIO State at
Wakeup
Wakeup Time
(see Note 2)
Backup Mode
ON
OFF
OFF
(Not powered)
SUPC_CR.VROFF = 1
SLEEPDEEP = 1 (see Note 1)
WKUP0–13 pins
Supply Monitor
Reset
Previous state
maintained
PIOA, PIOB,
PIOC, PIOD &
PIOE
inputs with
pullups
< 2 ms
Clocked back
(see Note 3)
Previous state
maintained
Unchanged
< 10 μs
RTC alarm
RTT alarm
Wait Mode w/
Flash in Deep
Power-down
Mode
ON
ON
Powered
(Not clocked)
PMC_MCKR.MDIV = 0
, CKGR_MOR.WAITMODE =1
, SLEEPDEEP = 0
, PMC_FSMR.LPM = 1
, PMC_FSMR.FLPM = 1 (see Note 1)
WKUP0–13 pins
RTC
RTT
USBHS
Processor debug (see Note 6)
GMAC Wake on LAN event
Wakeup from CAN (see Note
7)
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 46
SAM E70/S70/V70/V71
Power Considerations
...........continued
Mode
SUPC, 32 kHz
Oscillator,
RTC, RTT
Backup SRAM
(BRAM),
Backup
Registers
(GPBR),
POR
(Backup Area)
Regulator
Core
Memory
Peripherals
Mode Entry Configuration
Potential
Wakeup
Sources
Core at
Wakeup
PIO State while
in Low-Power
Mode
PIO State at
Wakeup
Wakeup Time
(see Note 2)
Wait Mode w/
Flash in
Standby Mode
ON
ON
Powered
(Not clocked)
PMC_MCKR.MDIV = 0
, CKGR_MOR.WAITMODE =1
, SLEEPDEEP = 0
, PMC_FSMR.LPM = 1
, PMC_FSMR.FLPM = 0 (see Note 1)
WKUP0–13 pins
RTC
Clocked back
(see Note 3)
Previous state
maintained
Unchanged
< 10 μs
Clocked back
Previous state
maintained
Unchanged
(see Note 5)
RTT
USBHS
Processor debug (see Note 6)
GMAC Wake on LAN
Wakeup from CAN (see Note
7)
Sleep Mode
ON
ON
Powered
(Not clocked) (see
Note 4)
WFI
SLEEPDEEP = 0
PMC_FSMR.LPM = 0 (see Note 1)
Any enabled Interrupt
Notes:
1. The bit SLEEPDEEP is in the Cortex-M7 System Control Register.
2. When considering wakeup time, the time required to start the PLL is not taken into account. Once started,
the device works with the Main RC oscillator. The user has to add the PLL startup time if it is needed in the
system. The wakeup time is defined as the time taken for wakeup until the first instruction is fetched.
3. HCLK = MCK. The user may need to revert back to the previous clock configuration.
4. Depends on MCK frequency.
5. In this mode, the core is supplied and not clocked. Some peripherals can be clocked.
6. Resume from Wait mode if a debug request occurs (CDBGPWRUPREQ is set in the processor).
7. CAN wake-up requires the use of any WKUP0–13 pin.
7.7
Wakeup Sources
Wakeup events allow the device to exit Backup mode. When a wakeup event is detected, the Supply Controller
performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are
not already enabled.
7.8
Fast Startup
The SAM E70/S70/V70/V71 allows the processor to restart in a few microseconds while the processor is in Wait
mode or in Sleep mode. A fast startup can occur upon detection of a low level on any of the following wake-up
sources:
•
•
•
•
•
•
•
WKUP0 to WKUP13 pins
Supply Monitor
RTC alarm
RTT alarm
USBHS interrupt line (WAKEUP)
Processor debug request (CDBGPWRUPREQ)
GMAC wake on LAN event
Note: CAN wake-up requires the use of any WKUP0–13 pin.
The fast restart circuitry is fully asynchronous and provides a fast startup signal to the Power Management Controller.
As soon as the fast startup signal is asserted, the PMC automatically restarts the Main RC oscillator, switches the
Host clock on this clock and re-enables the processor clock.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 47
SAM E70/S70/V70/V71
Input/Output Lines
8.
Input/Output Lines
The SAM E70/S70/V70/V71 features both general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate
functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used, whether in I/O
mode or by the multiplexed peripherals. System I/Os include pins such as test pins, oscillators, erase or analog
inputs.
8.1
General-Purpose I/O Lines
General-purpose I/O (GPIO) lines are managed by PIO Controllers. All I/Os have several input or output modes,
such as pull up or pull down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change
interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user
interface. For additional information, refer to the 32. Parallel Input/Output Controller (PIO).
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM E70/S70/V70/V71devices embed high-speed pads capable of handling high-speed clocks for HSMCI, SPI
and QSPI (MCK/2). Refer to the 57. Electrical Characteristics for SAM V70/V71 for additional information. Typical
pull-up and pull-down value is 100 kΩ for all I/Os.
Each I/O line also embeds a RSERIAL (On-die Serial Resistor), as shown in the following figure. It consists of an
internal series resistor termination scheme for impedance matching between the driver output (SAM E70/S70/V70/
V71) and the PCB trace impedance preventing signal reflection. The series resistor helps to reduce I/Os switching
current (di/dt). thereby reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance
of interconnect between devices or between boards. Finally, RSERIAL helps diminish signal integrity issues. The
following figure illustrates the On-Die Termination (ODT).
Note: Refer to the DC Characteristics tables in the Electrical Characteristics chapter.
Figure 8-1. On-Die Termination
Z0 ~ ZOUT + RODT
On-die Serial Resistor
RSERIAL
Receiver
Driver with
ZOUT ~ 10 Ohms
8.2
PCB Trace
Z0 ~ 50 Ohms
System I/O Lines
System I/O lines are pins used by oscillators, Test mode, reset, JTAG and other features. The following table lists the
SAM E70/S70/V70/V71 system I/O lines shared with PIO lines.
These pins are software-configurable as general-purpose I/Os or system pins. At startup, the default function of these
pins is always used.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 48
SAM E70/S70/V70/V71
Input/Output Lines
Table 8-1. System I/O Configuration Pin List
CCFG_SYSIO Default Function
Bit Number
After Reset
Other
Function
Constraints for
Normal Start
Configuration
In Matrix User Interface Registers
(Refer to the 19.4.7. CCFG_SYSIO
register)
12
ERASE
PB12
Low Level at
startup (see Note
1)
7
TCK/SWCLK
PB7
–
6
TMS/SWDIO
PB6
–
5
TDO/TRACESWO
PB5
–
4
TDI
PB4
–
–
PA7
XIN32
–
–
PA8
XOUT32
–
–
PB9
XIN
–
–
PB8
XOUT
–
(see Note 2 and 4)
(see Note 3 and 4)
Notes:
1. If the PB12 pin is used as PIO input in user applications, a low level must be ensured at start up to prevent
Flash erase before the user application sets the PB12 pin into PIO mode.
2. Refer to 23.4.2. Slow Clock Generator.
3. Refer to 30.5.3. Main Crystal Oscillator.
4. If not used then the corresponding PIO pin must be setup as an output and attached to a dedicated trace on
the board to reduce current consumption.
8.2.1
Serial Wire Debug Port (SW-DP) Pins
The SW-DP pins, SWCLK and SWDIO, are commonly provided on a standard 20-pin JTAG connector defined by
ARM. For additional information about voltage reference and reset state, refer to the Table 4-1.
At startup, the SW-DP pins are configured in SW-DP mode to allow connection with debugging probe. For more
details, refer to 16. Debug and Test Features.
The SW-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port
is not needed in the end application. Mode selection between SW-DP mode (System IO mode) and general IO mode
is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up,
triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent
pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
The JTAG Debug Port TDI, TDO, TMS and TCK is inactive. It is provided for Boundary Scan Manufacturing Test
purpose only.
8.2.2
Embedded Trace Module (ETM) Pins
The Embedded Trace Module (ETM) depends on the Trace Port Interface Unit (TPIU) to export data out of the
system.
The TPUI features the following pins:
•
•
TRACECLK is always exported to enable synchronization with the data.
TRACED0–TRACED3 is the instruction trace stream.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 49
SAM E70/S70/V70/V71
Input/Output Lines
8.3
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip Reset Controller (RSTC) and can be driven low to provide
a reset signal to the external components or asserted low externally to reset the microcontroller. It resets the core and
the peripherals, with the exception of the Backup area (RTC, RTT, Backup SRAM and Supply Controller). The NRST
pin integrates a permanent pullup resistor to VDDIO of about 100 kΩ.
By default, the pin is configured as an input.
8.4
ERASE Pin
The ERASE pin is used to perform hardware erase of the on-chip Flash and the NVM bits including GPNVM bits,
Lock bits and the Security Bit. The hardware erase sequence will first erase the entire Flash and afterwards the NVM
bits in order to fully secure the content of the on-chip Flash. The ERASE pin integrates a pull-down resistor of about
100 kΩ to GND, hence it can be left unconnected for normal operations.
The ERASE pin is a system I/O pin that can be used as a standard I/O. At startup, this system I/O pin defaults to
the ERASE function. This pin is debounced by SLCK to improve the glitch tolerance. To avoid unexpected erase at
power-up due to glitches, a minimum ERASE pin assertion time is required. This time is defined in Table 57-49.
The erase operation cannot be performed when the system is in Wait mode.
If the ERASE pin is used as a standard I/O in Input or Output mode, note the following considerations and behavior:
•
•
I/O Input mode: At startup of the device, the logic level of the pin must be low to prevent unwanted erasing until
the user application has reconfigured this system I/O pin to a standard I/O pin.
I/O Output mode: asserting the pin to low does not erase the Flash.
During software application development, a faulty software may put the device into a deadlock. This may be due to:
•
•
•
Programming an incorrect clock switching sequence.
Using this system I/O pin as a standard I/O pin.
Entering Wait mode without any wakeup events programmed.
To recover normal behavior is to erase the Flash by following these steps:
1.
2.
3.
4.
Apply a logic “1” level on the ERASE pin.
Apply a logic “0” level on the NRST pin.
Power down and then power up the device.
Maintain the ERASE pin to logic “1” level for at least the minimum assertion time after releasing the NRST pin
to logic “1” level.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 50
SAM E70/S70/V70/V71
Interconnect
9.
Interconnect
The system architecture is based on the ARM Cortex-M7 processor connected to the main AHB Bus Matrix, the
embedded Flash, the multi-port SRAM and the ROM.
The 32-bit AHBP interface is a single 32-bit wide interface that accesses the peripherals connected on the main
Bus Matrix. It is used only for data access. Instruction fetches are never performed on the AHBP interface. The bus,
AHBP or AXIM, accessing the peripheral memory area [0x40000000 to 0x60000000] is selected in the AHBP control
register.
The 32-bit AHBS interface provides system access to the ITCM, D1TCM, and D0TCM. It is connected on the main
Bus Matrix and allows the XDMA to transfer from memory or peripherals to the instruction or data TCMs.
The 64-bit AXIM interface is a single 64-bit wide interface connected through two ports of the AXI Bridge to the main
AHB Bus Matrix and to two ports of the multi-port SRAM. The AXIM interface allows:
•
•
•
•
Instruction fetches
Data cache linefills and evictions
Non-cacheable normal-type memory data accesses
Device and strongly-ordered type data accesses, generally to peripherals
The interleaved multi-port SRAM optimizes the Cortex-M7 accesses to the internal SRAM.
The interconnect of the other Hosts and Clients is described in 19. Bus Matrix (MATRIX).
The figure below shows the connections of the different Cortex-M7 ports.
Figure 9-1. Interconnect Block Diagram
In-Circuit Emulator
TPIU
Cortex-M7 Processor
fMAX 300 MHz
ETM
NVIC
MPU
Multi-Port SRAM
ITCM
TCM
Interface
64-bit
DTCM
FPU
16 Kbytes
DCache + ECC
Flash
ROM
S
S
2 x 32-bit
16 Kbytes
ICache + ECC
AHBP
TCM SRAM
AHBS
AXIM
System SRAM
64-bit
32-bit
32-bit
AXI Bridge
32-bit
M
M
© 2022 Microchip Technology Inc.
and its subsidiaries
32-bit
M
32-bit
S
S
32-bit
S
12-layer AHB Bus Matrix
fMAX 150 MHz
Complete Data Sheet
DS60001527G-page 51
SAM E70/S70/V70/V71
Product Mapping
10.
Product Mapping
Figure 10-1. SAM E70/S70/V70/V71 Product Mapping
0x00000000
Address memory space
0x00000000
Code
ITCM or Boot Memory
Code
0x00400000
Internal SRAM
EBI Chip Select 0
ROM
0x61000000
Reserved
0x62000000
EBI Chip Select 1
0x00C00000
EBI Chip Select 2
0x1FFFFFFF
0x40000000
Peripherals
0x60000000
0x20000000
memories
0x60000000
Internal Flash
0x00800000
0x20000000
0x63000000
Internal SRAM
EBI Chip Select 3
DTCM
0x70000000
SRAM
0x7FFFFFFF
Reserved
0x20400000
Memories
0x20C00000
Reserved
0x3FFFFFFF
0x80000000
QSPI MEM
0x40000000
Peripherals
0x40060000
HSMCI
0xA0000000
18
0x40004000
22
0x40008000
0x4000C000
0xA0100000
23
+0x40
0x40068000
MLB
0x4006C000
24
+0x80
25
0x40010000
26
+0x40
System
+0x80
28
0x40014000
+0x40
XDMAC
block
peripheral
ID
(+ : wired-or)
48
+0x80
0x40080000
0x40018000
0x4001C000
0x40090000
20
0x40024000
13
0x4002C000
15
MCAN0
0x40034000
MCAN1
0x40038000
35
37
34
29
30
0x40048000
45
46
0x400E2000
Reserved
0x5FFFFFFF
69
7
CHIPID
0x400E0A00
UART1
8
0x400E0C00
EFC
6
0x400E0E00
PIOA
10
0x400E1000
PIOB
11
0x400E1200
PIOC
12
0x400E1400
PIOD
16
0x400E1600
ACC
33
63
44
5
0x400E0940
DACC
0x40044000
WDT1
UART0
AFEC0
0x40040000
SYSC
GPBR
PMC
0x400E0800
USBHS
0x4003C000
2
SYSC
0x400E0600
USART2
0x40030000
RTC
UTMI
USART1
14
4
SYSC
70
0x400E0400
USART0
0x40028000
WDT0
I2SC1
PWM0
31
RTT
3
SYSC
UART4
62
I2SC0
SYSC
SUPC
UART3
0x4008C000
TWIHS1
0x40020000
0x400E1E00
MATRIX
TWIHS0
19
0x400E1C00
9
Reserved
0x40088000
RSTC
1
SYSC
UART2
43
SMC
0x40084000
Peripherals
SYSC
0x400E1A00
QSPI
TC2_CH2
49
58
0x4007C000
TC2_CH1
offset
+0x90
+0x100
0x40078000
TC2_CH0
47
+0x60
BRAM
TC1_CH2
0xFFFFFFFF
+0x50
57
0x40074000
TC1_CH1
27
53
TRNG
TC1_CH0
0xE0000000
+0x30
56
0x40070000
TC0_CH2
Reserved
40
AES
TC0_CH1
0xA0200000
+0x10
AFEC1
TC0_CH0
USBHS RAM
41
0x40064000
SPI0
21
0x400E1800
TWIHS2
SSC
Reserved
Peripherals
PIOE
0x400E1800
17
ICM
32
0x4004C000
ISI
59
0x40050000
GMAC
39
0x40054000
TC3_CH0
50
+0x40
TC3_CH1
51
+0x80
TC3_CH2
52
0x40058000
SPI1
42
0x4005C000
PWM1
60
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 52
SAM E70/S70/V70/V71
Memories
11.
Memories
11.1
Embedded Memories
11.1.1
Internal SRAM
SAM E70/S70/V70/V71 devices embed 384 Kbytes or 256 Kbytes of high-speed SRAM.
The SRAM is accessible over the system Cortex-M bus at address 0x2040 0000.
SAM E70/S70/V70/V71 devices embed a Multi-Port SRAM with four ports to optimize the bandwidth and latency. The
priorities, defined in the Bus Matrix for each SRAM port Client are propagated, for each request, up to the SRAM
Clients.
The Bus Matrix supports four priority levels: Normal, Bandwidth-sensitive, Latency-sensitive and Latency-critical in
order to increase the overall processor performance while securing the high-priority latency-critical requests from the
peripherals.
The SRAM controller manages interleaved addressing of SRAM blocks to minimize access latencies. It uses Bus
Matrix priorities to give the priority to the most urgent request. The less urgent request is performed no later than the
next cycle.
Two SRAM Client ports are dedicated to the Cortex-M7 while two ports are shared by the AHB Hosts.
11.1.2
Tightly Coupled Memory (TCM) Interface
SAM E70/S70/V70/V71 devices embed Tightly Coupled Memory (TCM) running at processor speed.
•
•
ITCM is a single 64-bit interface, based at 0x0000 0000 (code region).
DTCM is composed of dual 32-bit interfaces interleaved, based at 0x2000 0000 (data region).
ITCM and DTCM are enabled/disabled in the ITCMR and DTCMR registers in ARM SCB.
DTCM is enabled by default at reset. ITCM is disabled by default at reset.
There are four TCM configurations controlled by software. When enabled, ITCM is located at 0x0000 0000,
overlapping ROM or Flash depending on the general-purpose NVM bit 1 (GPNVM). The configuration is done with
GPNVM bits [8:7].
Table 11-1. TCM Configurations in Kbytes
ITCM
DTCM
SRAM for 384K RAM-based
SRAM for 256K RAM-based
GPNVM Bits [8:7]
0
0
384
256
0
32
32
320
192
1
64
64
256
128
2
128
128
128
0
3
Accesses made to TCM regions when the relevant TCM is disabled and accesses made to the Code and SRAM
region above the TCM size limit are performed on the AHB matrix, i.e., on internal Flash or on ROM depending on
remap GPNVM bit.
Accesses made to the SRAM above the size limit will not generate aborts.
The Memory Protection Unit (MPU) can to be used to protect these areas.
11.1.3
Internal ROM
The SAM E70/S70/V70/V71 embeds an Internal ROM for the SAM Boot Assistant (SAM-BA®), In Application
Programming functions (IAP) and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 53
SAM E70/S70/V70/V71
Memories
The ROM may also be mapped at 0x00000000 depending on GPNVM bit setting and ITCM use.
11.1.4
Backup SRAM
The SAM E70/S70/V70/V71 embeds 1 Kbytes of backup SRAM located at 0x4007 4000.
The backup SRAM is accessible in 32-bit words only. Byte or half-word accesses are not supported.
The backup SRAM is supplied by VDDCORE in Normal mode.
In Backup mode, the backup SRAM supply is automatically switched to VDDIO through the backup SRAM power
switch when VDDCORE falls. For more details, see the “Backup SRAM Power Switch” section.
11.1.5
Flash Memories
SAM E70/S70/V70/V71 devices embed 512 Kbytes, 1024 Kbytes, or 2084 Kbytes of internal Flash mapped at
address 0x40 0000.
The devices feature a Quad SPI (QSPI) interface, mapped at address 0x80000000, that extends the Flash size by
adding an external SPI or QSPI Flash.
When accessed by the Cortex-M7 processor for programming operations, the QSPI and internal Flash address
spaces must be defined in the Cortex-M7 memory protection unit (MPU) with the attribute 'Device' or 'Strongly
Ordered'. For fetch or read operations, the attribute ‘Normal memory’ must be set to benefit from the internal cache.
For additional information, refer to the ARM Cortex-M7 Technical Reference Manual (ARM DDI 0489), which is
available for download at www.arm.com.
Some precautions must be taken when the accesses are performed by the central DMA. Refer to the 22. Enhanced
Embedded Flash Controller (EEFC) and 41. Quad Serial Peripheral Interface (QSPI).
11.1.5.1 Embedded Flash Overview
The memory is organized in sectors and each sector has a size of 128 Kbytes. The first sector is divided into three
smaller sectors which are organized in two sectors of 8 Kbytes and one sector of 112 Kbytes, see figure below.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 54
SAM E70/S70/V70/V71
Memories
Figure 11-1. Global Flash Organization
Address
Sector size
Sector Name
8 Kbytes
Small Sector 0
8 Kbytes
Small Sector 1
112 Kbytes
Larger Sector
128 Kbytes
Sector 1
128 Kbytes
Sector n
0x000
Sector 0
Each sector is organized in pages of 512 bytes.
For sector 0:
•
•
•
The smaller sector 0 has 16 pages of 512 bytes
The smaller sector 1 has 16 pages of 512 bytes
The larger sector has 224 pages of 512 bytes
The rest of the array is composed of 128-Kbyte sectors of 256 pages of 512 bytes each, see image below.
Figure 11-2. Flash Sector Organization
Sector size is 128 Kbytes
Sector 0
16 pages of 512 bytes
Smaller sector 0
16 pages of 512 bytes
Smaller sector 1
224 pages of 512 bytes
Sector n
Larger sector
256 pages of 512 bytes
The figure below illustrates the organization of the Flash depending on its size.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 55
SAM E70/S70/V70/V71
Memories
Figure 11-3. Flash Size
Flash 2 Mbytes
Flash 1 Mbyte
Flash 512 Kbytes
2 * 8 Kbytes
2 * 8 Kbytes
2 * 8 Kbytes
1 * 112 Kbytes
1 * 112 Kbytes
1 * 112 Kbytes
15 * 128 Kbytes
7 * 128 Kbytes
3 * 128 Kbytes
Erasing the memory can be performed:
•
•
•
•
Chip Erase
By block of 8 Kbytes
By sector of 128 Kbytes
By 512-byte page
– Erase memory by page is possible only in an 8 Kbyte sector
– EWP and EWPL commands can be only used in 8 Kbyte sectors
The memory has one additional reprogrammable page that can be used as page signature by the user. It is
accessible through specific modes, for erase, write and read operations. Erase pin assertion will not erase the User
Signature page.
11.1.5.2 Enhanced Embedded Flash Controller
Each Enhanced Embedded Flash Controller manages accesses performed by the hosts of the system. It enables
reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
11.1.5.3 Flash Speed
The user must set the number of wait states depending on the system frequency.
For more details, refer to Embedded Flash Characteristics.
11.1.5.4 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several
consecutive pages, and each lock region has its associated lock bit.
Table 11-2. Flash Lock Bits
Flash Size (Kbytes)
Number of Lock Bits
Lock Region Size
2048
128
16 Kbytes
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 56
SAM E70/S70/V70/V71
Memories
...........continued
Flash Size (Kbytes)
Number of Lock Bits
Lock Region Size
1024
64
16 Kbytes
512
32
16 Kbytes
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
11.1.5.5 Security Bit Feature
The SAM E70/S70/V70/V71 features a security bit based on the GPNVM bit 0. When security is enabled, any access
to the Flash, SRAM, core registers and internal peripherals, either through the SW-DP, the ETM interface or the Fast
Flash Programming Interface, is blocked. This ensures the confidentiality of the code programmed in the Flash.
This security bit can only be enabled through the command “Set General-purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash
erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal
Peripherals are permitted.
11.1.5.6 Unique Identifier
The device contains a unique identifier of 2 pages of 512 bytes. These 2 pages are read-only and cannot be erased
even by the ERASE pin.
The sequence to read the unique identifier area is described in 22.4.3.8. Unique Identifier Area.
The mapping is as follows:
•
•
Bytes [0..15]: 128 bits for unique identifier
Bytes[16..1023]: Reserved
11.1.5.7 User Signature
Each device contains a user signature of 512 bytes that is available to the user. The user signature can be used to
store information such as trimming, keys, etc., that the user does not want to be erased by asserting the ERASE pin
or by software ERASE command. Read, write and erase of this area is allowed.
11.1.5.8 Fast Flash Programming Interface (FFPI)
The Fast Flash Programming Interface (FFPI) allows programming the device through a multiplexed fullyhandshaked parallel port. It allows gang programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
The FFPI is enabled and the Fast Programming mode is entered when TST and PA3 and PA4 are tied low.
Table 11-3. FFPI on PIO Controller A (PIOA)
I/O Line
System Function
PD10
PGMEN0
PD11
PGMEN1
PB0
PGMM0
PB1
PGMM1
PB2
PGMM2
PB3
PGMM3
PA3
PGMNCMD
PA4
PGMRDY
PA5
PGMNOE
PA21
PGMNVALID
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 57
SAM E70/S70/V70/V71
Memories
...........continued
I/O Line
System Function
PA7
PGMD0
PA8
PGMD1
PA9
PGMD2
PA10
PGMD3
PA11
PGMD4
PA12
PGMD5
PA13
PGMD6
PA14
PGMD7
PD0
PGMD8
PD1
PGMD9
PD2
PGMD10
PD3
PGMD11
PD4
PGMD12
PD5
PGMD13
PD6
PGMD14
PD7
PGMD15
11.1.5.9 SAM-BA Boot
The SAM-BA Boot is a default boot program which provides an easy way to program in-situ the on-chip Flash
memory.
The SAM-BA Boot Assistant supports serial communication via the UART0 and USB.
The SAM-BA Boot provides an interface with SAM-BA computer application.
The SAM-BA Boot is in ROM at address 0x0 when the bit GPNVM1 is set to 0.
11.1.5.10 General-purpose NVM (GPNVM) Bits
All SAM E70/S70/V70/V71 devices feature nine general-purpose NVM (GPNVM) bits that can be cleared or set,
through the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC User Interface.
The GPNVM0 bit is the security bit.
The GPNVM1bit is used to select the Boot mode (Boot always at 0x00) on ROM or Flash.
Table 11-4. General-purpose Non volatile Memory Bits
GPNVM Bit
Function
0
Security bit
1
Boot mode selection
0: ROM (default)
1: Flash
5:2
Free
6
Reserved
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 58
SAM E70/S70/V70/V71
Memories
...........continued
GPNVM Bit
Function
8:7
TCM configuration
00: 0 Kbytes DTCM + 0 Kbytes ITCM (default)
01: 32 Kbytes DTCM + 32 Kbytes ITCM
10: 64 Kbytes DTCM + 64 Kbytes ITCM
11: 128 Kbytes DTCM + 128 Kbytes ITCM
Note: After programming, reboot must be done.
11.1.6
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed
using GPNVM bits.
A GPNVM bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set, respectively, through the commands “Clear General-purpose NVM Bit” and
“Set General-purpose NVM Bit” of the EEFC User Interface.
Setting the bit GPNVM1 selects boot from the Flash. Clearing it selects boot from the ROM. Asserting ERASE resets
the bit GPNVM1 and thus selects boot from ROM.
11.2
External Memories
The SAM E70/S70/V70/V71 features one External Bus Interface to provide an interface to a wide range of external
memories and to any parallel peripheral.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 59
SAM E70/S70/V70/V71
Event System
12.
Event System
The events generated by peripherals (source) are designed to be directly routed to peripherals (destination) using
these events without processor intervention. The trigger source can be programmed in the destination peripheral.
12.1
Embedded Characteristics
•
•
•
•
•
•
12.2
Timers, PWM, I/Os and peripherals generate event triggers which are directly routed to destination peripherals,
such as AFEC or DACC to start measurement/conversion without processor intervention.
UART, USART, QSPI, SPI, TWI, PWM, HSMCI, AES, AFEC, DACC, PIO, TC (Capture mode) also generate
event triggers directly connected to the DMA Controller for data transfer without processor intervention.
Parallel capture logic is directly embedded in the PIO and generates trigger events to the DMA Controller to
capture data without processor intervention.
PWM safety events (faults) are in combinational form and directly routed from event generators (AFEC, ACC,
PMC, TC) to the PWM module.
PWM output comparators (OCx) generate events directly connected to the TC.
PMC safety event (clock failure detection) can be programmed to switch the MCK on reliable main RC internal
clock without processor intervention.
Real-time Event Mapping
Table 12-1. Real-time Event Mapping List
Function
Application
Description
Event Source
Event
Destination
Safety
Generalpurpose
Automatic switch to reliable main RC
oscillator in case of main crystal clock
failure (see Note 1)
Power Management
Controller (PMC)
PMC
Generalpurpose,
motor control,
power factor
correction
(PFC)
Puts the PWM outputs in Safe mode
in case of main crystal clock failure
(see Notes 1, 2)
PMC
Pulse Width
Modulation 0
and 1
(PWM0 and
PWM1)
Motor control,
PFC
Puts the PWM outputs in Safe
mode (overcurrent detection, etc.)
(see Notes 2, 3)
Analog Comparator
Controller (ACC)
PWM0 and
PWM1
Motor control,
PFC
Puts the PWM outputs in Safe mode
(overspeed, overcurrent detection,
etc.) (see Notes 2, 4)
Analog Front-End
Controller (AFEC0)
PWM0 and
PWM1
AFEC1
PWM0 and
PWM1
Puts the PWM outputs in Safe mode
(overspeed detection through timer
quadrature decoder) (see Notes 2, 6)
TC0.Ch0
PWM0
TC0.Ch1
PWM1
PIO PA9, PD8, PD9
PWM0
PIO PA21, PA26, PA28
PWM1
Motor control
Generalpurpose,
motor control,
power factor
correction
(PFC)
© 2022 Microchip Technology Inc.
and its subsidiaries
Puts the PWM outputs in Safe mode
(general-purpose fault inputs) (see
Note 2)
Complete Data Sheet
DS60001527G-page 60
SAM E70/S70/V70/V71
Event System
...........continued
Function
Application
Description
Event Source
Event
Destination
Security
Generalpurpose
Immediate GPBR clear
(asynchronous) on tamper detection
through WKUP0/1 IO pins (see Note
5)
PIO WKUP0/1
GPBR
Measurement
trigger
Power factor
correction
(DC-DC,
lighting, etc.)
Duty cycle output waveform
correction
Trigger source selection in PWM (see
Notes 7, 8)
ACC
PWM0
PIO PA10, PA22
PWM0
ACC
PWM1
PIO PA30, PA18
PWM1
Generalpurpose
Conversion
trigger
Image capture
AFEC0
AFEC0
TC0.Ch1 (TIOA1)
AFEC0
TC0.Ch2 (TIOA2)
AFEC0
ACC
AFEC0
PWM0 Event Line 0 and
1
AFEC0
Motor control
ADC-PWM synchronization (see
Notes 12, 14) Trigger source
selection in AFEC (see Note 9)
Generalpurpose
Trigger source selection in AFEC (see PIO AFE1_ADTRG
Note 9)
TC1.Ch0 (TIOA3)
AFEC1
AFEC1
TC1.Ch1 (TIOA4)
AFEC1
TC1.Ch2 (TIOA5)
AFEC1
ACC
AFEC1
Motor control
ADC-PWM synchronization (see
PWM1 Event Line
Notes 12, 14)
0 and 1
Trigger source selection in AFEC (see
Note 9)
AFEC1
Generalpurpose
Temperature sensor
Low-speed measurement (see Notes
10, 11)
RTC RTCOUT0
AFEC0 and
AFEC1
Generalpurpose
Trigger source selection in DACC
(Digital-to-Analog Converter
Controller) (see Note 13)
TC0.Ch0-2 (TIOA0,
TIOA1, TIOA2)
DACC
PIO DATRG
DACC
PWM0 Event Line 0 and
1(14)
DACC
PWM1 Event Line 0 and
1(14)
DACC
PIO
PA3/4/5/9/10/11/12/13,
PA22, PA14, PA21
DMA
Low-cost
image sensor
© 2022 Microchip Technology Inc.
and its subsidiaries
Trigger source selection in AFEC (see PIO AFE0_ADTRG
Note 9)
TC0.Ch0 (TIOA0)
Direct image transfer from sensor to
system memory via DMA(15)
Complete Data Sheet
DS60001527G-page 61
SAM E70/S70/V70/V71
Event System
...........continued
Function
Application
Description
Event Source
Event
Destination
Delay
measurement
Motor control
Propagation delay of external
components (IOs, power transistor
bridge driver, etc.) See Notes 16, 17)
PWM0 Comparator
Output OC0
TC0.Ch0
TIOA0 and
TIOB0
PWM0 Comparator
Output OC1
TC0.Ch1
TIOA1 and
TIOB1
PWM0 Comparator
Output OC2
TC0.Ch2
TIOA2 and
TIOB2
PWM1 Comparator
Output OC0
TC1.Ch0
TIOA3 and
TIOB3
PWM1 Comparator
Output OC1
TC1.Ch1
TIOA4 and
TIOB4
PWM1 Comparator
Output OC2
TC1.Ch2
TIOA5 and
TIOB5
PWM0 Comparator
Output OC0
TC2.Ch0
TIOA6 and
TIOB6
PWM0 Comparator
Output OC1
TC2.Ch1
TIOA7 and
TIOB7
PWM0 Comparator
Output OC2
TC2.Ch2
TIOA8 and
TIOB8
PWM1 Comparator
Output OC0
TC3.Ch0
TIOA9 and
TIOB9
PWM1 Comparator
Output OC1
TC3.Ch1
TIOA10 and
TIOB10
Audio clock
recovery from
Ethernet
Audio
GMAC GTSUCOMP signal adaptation GMAC
via TC (TC3.TC_EMR.TRIGSRCB) in GTSUCOMP
order to drive the clock reference of
the external PLL for the audio clock
TC3.Ch2
TIOB11
Direct Memory
Access
Generalpurpose
Peripheral trigger event generation to
transfer data to/from system memory
(see Note 18)
XDMA
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
USART, UART, TWIHS,
SPI, QSPI, AFEC, TC
(Capture), SSC, HSMCI,
DAC, AES, PWM, PIO,
I2SC
DS60001527G-page 62
SAM E70/S70/V70/V71
Event System
Notes:
1. Refer to 31.15. Main Crystal Oscillator Failure Detection.
2. Refer to 50.5.4. Fault Inputs and 50.6.2.7. Fault Protection.
3. Refer to 53.6.4. Fault Mode.
4. Refer to 53.5.4. Fault Output.
5. Refer to 23.4.9.2. Low-power Tamper Detection and Anti-Tampering and 29.3.1. SYS_GPBRx.
6. Refer to 49.6.18. Fault Mode.
7. Refer to 50.7.49. PWM_ETRGx.
8. Refer to 50.6.5. PWM External Trigger Mode.
9. Refer to 51.6.6. Conversion Triggers and 51.7.2. AFEC_MR.
10. Refer to 57.10. Temperature Sensor.
11. Refer to 27.5.8. Waveform Generation.
12. Refer to 50.7.36. PWM_CMPVx and 50.6.4. PWM Event Lines.
13. Refer to 52.7.3. DACC_TRIGR.
14. Refer to 50.6.3. PWM Comparison Units and 50.6.4. PWM Event Lines.
15. Refer to 32.5.14. Parallel Capture Mode.
16. Refer to 50.6.2.2. Comparator.
17. Refer to 49.6.14. Synchronization with PWM.
18. Refer to 35. DMA Controller (XDMAC).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 63
SAM E70/S70/V70/V71
System Controller
13.
System Controller
The System Controller is a set of peripherals that handles key elements of the system, such as power, resets, clocks,
time, interrupts, watchdog, and so on..
13.1
System Controller and Peripherals Mapping
Refer to the “Product Mapping” section.
13.2
Power-on-Reset, Brownout and Supply Monitor
The SAM E70/S70/V70/V71 embeds three features to monitor, warn and/or reset the chip:
•
•
•
•
13.2.1
Power-on-Reset (POR) on VDDIO
POR on VDDCORE
Brown-out-Detector (BOD) on VDDCORE
Supply Monitor on VDDIO
Power-on-Reset
The Power-on-Reset (POR) monitors VDDIO and VDDCORE. It is always activated and monitors voltage at start up
but also during power down. If VDDIO or VDDCORE goes below the threshold voltage, the entire chip is Reset. For
more information, refer to 57. Electrical Characteristics for SAM V70/V71.
13.2.2
Brownout Detector on VDDCORE
The Brown-out-Detector(BOD) monitors VDDCORE. It is active by default. It can be deactivated by software through
the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes, such as wait
or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to
23. Supply Controller (SUPC) and 57. Electrical Characteristics for SAM V70/V71.
13.2.3
Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully
programmable with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller
(SUPC). A sample mode is possible, which allows the supply monitor power consumption to be divided by a factor of
up to 2048. For more information, refer to 23. Supply Controller (SUPC) and 57. Electrical Characteristics for SAM
V70/V71.
13.3
Reset Controller
The Reset Controller is based on two POR cells, one on VDDIO and one on VDDCORE, and a Supply Monitor on
VDDIO.
The Reset Controller returns the source of the last reset to the software. This may be a general reset, a wakeup
reset, a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the pin input/output. It can shape a reset signal for
the external devices, simplifying the connection of a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDIO.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 64
SAM E70/S70/V70/V71
Peripherals
14.
Peripherals
14.1
Peripheral Identifiers
The following table defines the peripheral identifiers of the SAM E70/S70/V70/V71 devices. A peripheral identifier is
required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and control of the
peripheral clock with the Power Management Controller.
Table 14-1. Peripheral Identifiers
Instance ID
Instance Name
NVIC Interrupt
0
SUPC
X
–
Supply Controller
1
RSTC
X
–
Reset Controller
2
RTC
X
–
Real Time Clock
3
RTT
X
–
Real Time Timer
4
WDT
X
–
Watchdog Timer
5
PMC
X
–
Power Management Controller
6
EFC
X
–
Enhanced Embedded Flash Controller
7
UART0
X
X
Universal Asynchronous Receiver/Transmitter
8
UART1
X
X
Universal Asynchronous Receiver/Transmitter
9
SMC
–
X
Static Memory Controller
10
PIOA
X
X
Parallel I/O Controller A
11
PIOB
X
X
Parallel I/O Controller B
12
PIOC
X
X
Parallel I/O Controller C
13
USART0
X
X
Universal Synchronous/Asynchronous Receiver/
Transmitter
14
USART1
X
X
Universal Synchronous/Asynchronous Receiver/
Transmitter
15
USART2
X
X
Universal Synchronous/Asynchronous Receiver/
Transmitter
16
PIOD
X
X
Parallel I/O Controller D
17
PIOE
X
X
Parallel I/O Controller E
18
HSMCI
X
X
Multimedia Card Interface
19
TWIHS0
X
X
Two-wire Interface (I2C-compatible)
20
TWIHS1
X
X
Two-wire Interface (I2C-compatible)
21
SPI0
X
X
Serial Peripheral Interface
22
SSC
X
X
Synchronous Serial Controller
23
TC0_CHANNEL0
X
X
16-bit Timer Counter 0, Channel 0
24
TC0_CHANNEL1
X
X
16-bit Timer Counter 0, Channel 1
25
TC0_CHANNEL2
X
X
16-bit Timer Counter 0, Channel 2
© 2022 Microchip Technology Inc.
and its subsidiaries
PMC
Description
Clock Control
Complete Data Sheet
DS60001527G-page 65
SAM E70/S70/V70/V71
Peripherals
...........continued
Instance ID
Instance Name
NVIC Interrupt
26
TC1_CHANNEL0
X
X
16-bit Timer Counter 1, Channel 0
27
TC1_CHANNEL1
X
X
16-bit Timer Counter 1, Channel 1
28
TC1_CHANNEL2
X
X
16-bit Timer Counter 1, Channel 2
29
AFEC0
X
X
Analog Front-End Controller
30
DACC
X
X
Digital-to-Analog Converter
31
PWM0
X
X
Pulse-Width Modulation Controller
32
ICM
X
X
Integrity Check Monitor
33
ACC
X
X
Analog Comparator Controller
34
USBHS
X
X
USB Host/Device Controller
35
MCAN0
X
X
CAN IRQ Line 0
36
MCAN0
INT1
–
CAN IRQ Line 1
37
MCAN1
X
X
CAN IRQ Line 0
38
MCAN1
INT1
–
CAN IRQ Line 1
39
GMAC
X
X
Ethernet MAC
40
AFEC1
X
X
Analog Front End Controller
41
TWIHS2
X
X
Two-wire Interface
42
SPI1
X
X
Serial Peripheral Interface
43
QSPI
X
X
Quad I/O Serial Peripheral Interface
44
UART2
X
X
Universal Asynchronous Receiver/Transmitter
45
UART3
X
X
Universal Asynchronous Receiver/Transmitter
46
UART4
X
X
Universal Asynchronous Receiver/Transmitter
47
TC2_CHANNEL0
X
X
16-bit Timer Counter 2, Channel 0
48
TC2_CHANNEL1
X
X
16-bit Timer Counter 2, Channel 1
49
TC2_CHANNEL2
X
X
16-bit Timer Counter 2, Channel 2
50
TC3_CHANNEL0
X
X
16-bit Timer Counter 3, Channel 0
51
TC3_CHANNEL1
X
X
16-bit Timer Counter 3, Channel 1
52
TC3_CHANNEL2
X
X
16-bit Timer Counter 3, Channel 2
53
MLB
X
X
MediaLB IRQ 0
54
MLB
X
–
MediaLB IRQ 1
55
–
X
–
Reserved
56
AES
X
X
Advanced Encryption Standard
57
TRNG
X
X
True Random Number Generator
58
XDMAC
X
X
DMA Controller
59
ISI
X
X
Image Sensor Interface
© 2022 Microchip Technology Inc.
and its subsidiaries
PMC
Description
Clock Control
Complete Data Sheet
DS60001527G-page 66
SAM E70/S70/V70/V71
Peripherals
...........continued
Instance ID
14.2
Instance Name
NVIC Interrupt
PMC
Description
Clock Control
60
PWM1
X
X
Pulse-Width Modulation Controller
61
ARM
FPU
–
Arm Floating Point Unit interrupt associated with
OFC, UFC, IOC, DZC and IDC bits.
62
Reserved
–
–
–
63
RSWDT
X
–
Reinforced Safety Watchdog Timer
64
ARM
CCW
–
Arm Cache ECC Warning
65
ARM
CCF
–
Arm Cache ECC Fault
66
GMAC
Q1
–
GMAC Queue 1 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 1.
67
GMAC
Q2
–
GMAC Queue 2 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 2.
68
ARM
IXC
–
Floating Point Unit Interrupt IXC associated with
FPU cumulative exception bit.
69
I2SC0
X
X
Inter-IC Sound Controller
70
I2SC1
X
X
Inter-IC Sound Controller
71
GMAC
Q3
–
GMAC Queue 3 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 3
72
GMAC
Q4
–
GMAC Queue 4 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 4
73
GMAC
Q5
–
GMAC Queue 5 Interrupt signal toggled on a
DMA write to the first word of each DMA data
buffer associated with queue 5
Peripheral Signal Multiplexing on I/O Lines
The SAM E70/S70/V70/V71 features
•
•
•
Two PIO controllers on 64-pin versions (PIOA and PIOB)
Three PIO controllers on the 100-pin version (PIOA, PIOB and PIOD)
Five PIO controllers on the 144-pin version (PIOA, PIOB, PIOC, PIOD and PIOE), that multiplex the I/O lines of
the peripheral set.
The SAM E70/S70/V70/V71 PIO Controllers control up to 32 lines and each line can be assigned to one of four
peripheral functions: A, B, C or D.
For more information on multiplexed signals, refer to the “Package and Pinout” chapter.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 67
SAM E70/S70/V70/V71
Arm Cortex-M7
15.
Arm Cortex-M7
Refer to Arm reference documents Cortex-M7 Processor User Guide (ARM DUI 0644) and Cortex-M7 Technical
Reference Manual (ARM DDI 0489), which are available for download at www.arm.com.
15.1
Arm Cortex-M7 Configuration
The following table provides the configuration for the Arm Cortex-M7 processor in SAM E70/S70/V70/V71 devices.
Table 15-1. Arm Cortex-M7 Configuration
Features
Configuration
Debug
Comparator set
Full comparator set: 4 DWT and 8 FPB comparators
ETM support
Instruction ETM interface
Internal Trace support (ITM)
ITM and DWT trace functionality implemented
CTI and WIC
Not embedded
TCM
ITCM max size
128 KB
DTCM max size
256 KB
Cache
Cache size
16 KB for instruction cache, 16 KB for data cache
Number of sets
256 for instruction cache, 128 for data cache
Number of ways
2 for instruction cache, 4 for data cache
Number of words per cache line
8 words (32 bytes)
ECC on Cache
Embedded
NVIC
IRQ number
74
IRQ priority levels
8
MPU
Number of regions
16
FPU
FPU precision
Single and double precision
AHB Port
AHBP addressing size
© 2022 Microchip Technology Inc.
and its subsidiaries
512 MB
Complete Data Sheet
DS60001527G-page 68
SAM E70/S70/V70/V71
Debug and Test Features
16.
Debug and Test Features
16.1
Description
The device features a number of complementary debug and test capabilities. The Serial Wire Debug Port (SW-DP)
is used for standard debugging functions, such as downloading code and single-stepping through programs. It also
embeds a serial wire trace.
16.2
Embedded Characteristics
•
•
•
•
•
•
•
16.3
Debug access to all memory and registers in the system, including Cortex-M register bank, when the core is
running, halted, or held in reset.
Serial Wire Debug Port (SW-DP) debug access (ADIv5.1 with no multidrop mode support).
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.
Instrumentation Trace Macrocell (ITM) for support of printf style debugging.
6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight™ Trace Port Interface
Unit (TPIU).
IEEE1149.1 JTAG Boundary scan on All Digital Pins.
Associated Documents
The SAM E70/S70/V70/V71 implements the standard Arm CoreSight macrocell. For information on CoreSight, the
following reference documents are available from the Arm web site (www.arm.com):
•
•
•
•
•
•
Cortex-M7 User Guide Reference Manual (ARM DUI 0644)
Cortex-M7 Technical Reference Manual (ARM DDI 0489)
CoreSight Technology System Design Guide (ARM DGI 0012)
CoreSight Components Technical Reference Manual (ARM DDI 0314)
ARM Debug Interface v5 Architecture Specification (Doc. ARM IHI 0031)
ARMv7-M Architecture Reference Manual (ARM DDI 0403)
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 69
SAM E70/S70/V70/V71
Debug and Test Features
16.4
Debug and Test Block Diagram
Figure 16-1. Debug and Test Block Diagram
TMS/SWDIO
TCK/SWCLK
TDI
Boundary
Test Access Port
(TAP)
JTAGSEL
Serial Wire Debug Port
TDO/TRACESWO
POR
Reset
and
Test
Embedded
Trace
Macrocell
TRACED0–3
PIO
Cortex-M7
TST
TRACECLK
PCK3
16.5
Debug and Test Pin Description
Table 16-1. Debug and Test Signal List
Signal Name
Function
Type
Active Level
NRST
Microcontroller Reset
Input/Output
Low
TST
Test Select
Input
–
Reset/Test
Serial Wire Debug Port/JTAG Boundary Scan
TCK/SWCLK
Test Clock/Serial Wire Clock
Input
–
TDI
Test Data In
Input
–
TDO/TRACESWO
Test Data Out/Trace Asynchronous Data Out
Output
–
TMS/SWDIO
Test Mode Select/Serial Wire Input/Output
Input
–
JTAGSEL
JTAG Selection
Input
High
TRACECLK
Trace Clock
Output
–
TRACED0–3
Trace Data
Output
–
Trace Debug Port
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 70
SAM E70/S70/V70/V71
Debug and Test Features
16.6
16.6.1
Application Examples
Debug Environment
The figure below shows a complete debug environment example. The SW-DP interface is used for standard
debugging functions, such as downloading code and single-stepping through the program and viewing core and
peripheral registers.
Figure 16-2. Application Debug Environment Example
Host Debugger
PC
Serial Wire
Debug Port
Emulator/Probe
Serial Wire
Debug Port
Connector
Microchip MCU
Cortex-M7-based Application Board
16.6.2
Test Environment
The figure below shows a test environment example (JTAG Boundary scan). Test vectors are sent and interpreted by
the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices
can be connected to form a single scan chain.
Figure 16-3. Application Test Environment Example
Test Adaptor
Tester
JTAG
Probe
JTAG
Connector
Chip n
Microchip MCU
Chip 2
Chip 1
Cortex-M7-based Application Board In Test
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 71
SAM E70/S70/V70/V71
Debug and Test Features
16.7
Functional Description
16.7.1
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash Programming mode. The TST pin
integrates a permanent pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal
operations. To enable Fast Flash Programming mode, refer to 18. Fast Flash Programming Interface (FFPI).
16.7.2
Debug Architecture
Figure 16-4 shows the debug architecture used. The Cortex-M7 embeds six functional units for debug:
•
•
•
•
•
•
Serial Wire Debug Port (SW-DP) debug access
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
6-pin Embedded Trace Macrocell (ETM) for instruction trace stream, including CoreSight Trace Port Interface
Unit (TPIU)
IEEE1149.1 JTAG Boundary scan on all digital pins
The debug architecture information that follows is mainly dedicated to developers of SW-DP Emulators/Probes and
debugging tool vendors for Cortex-M7-based microcontrollers. For further details on SW-DP, see the Cortex - M7
Technical Reference Manual.
Figure 16-4. Debug Architecture
Data Watchpoint and Trace
Flash Patch Breakpoint
4 Watchpoints
6 Breakpoints
PC Sampler
Instrumentation Trace Macrocell
Serial Wire Debug Port
Serial Wire Debug
Data Address Sampler
Software Trace
32 channels
Serial Wire Output
Trace
Time Stamping
Data Sampler
Embedded Trace Macrocell
Interrupt Trace
CPU Statistics
16.7.3
Instruction Trace
Trace Port
Time Stamping
Serial Wire Debug Port (SW-DP) Pins
The SW-DP pins SWCLK and SWDIO are commonly provided on a standard 20-pin JTAG connector defined by
ARM. For more details on voltage reference and reset state, refer to the "Signal Description" chapter.
At startup, SW-DP pins are configured in SW-DP mode to allow connection with debugging probe.
SW-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port
is not needed in the end application. Mode selection between SW-DP mode (System I/O mode) and general I/O
mode is performed through the AHB Matrix Chip Configuration registers (CCFG_SYSIO). Configuration of the pad for
pullup, triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent
pulldown resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
The JTAG debug ports TDI, TDO, TMS and TCK are inactive. They are provided for Boundary Scan Manufacturing
Test purposes only. By default the SW-DP is active; TDO/TRACESWO can be used for trace.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 72
SAM E70/S70/V70/V71
Debug and Test Features
Table 16-2. SW-DP Pin List
Pin Name
JTAG Boundary Scan
Serial Wire Debug Port
TMS/SWDIO
TMS
SWDIO
TCK/SWCLK
TCK
SWCLK
TDI
TDI
–
TDO/TRACESWO
TDO
TRACESWO (optional: trace)
SW-DP is selected when JTAGSEL is low. It is not possible to switch directly between SW-DP and JTAG boundary
scan operations. A chip reset must be performed after JTAGSEL is changed.
16.7.4
Embedded Trace Module (ETM) Pins
The Embedded Trace Module (ETM) uses the Trace Port Interface Unit (TPIU) to export data out of the system.
The TPUI features the pins:
•
•
16.7.5
TRACECLK–always exported to enable synchronization back with the data. PCK3 is used internally.
TRACED0–3–the instruction trace stream.
Flash Patch Breakpoint (FPB)
The FPB implements hardware breakpoints.
16.7.6
Data Watchpoint and Trace (DWT)
The DWT contains four comparators which can be configured to generate:
•
•
•
PC sampling packets at set intervals
PC or Data watchpoint packets
Watchpoint event to halt core
The DWT contains counters for:
•
•
•
•
•
•
16.7.7
Clock cycle (CYCCNT)
Folded instructions
Load Store Unit (LSU) operations
Sleep cycles
CPI (all instruction cycles except for the first cycle)
Interrupt overhead
Instrumentation Trace Macrocell (ITM)
The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS)
and application events, and emits diagnostic system information. The ITM emits trace information as packets which
can be generated by three different sources with several priority levels:
•
•
•
Software trace: Software can write directly to ITM stimulus registers. This can be done using the printf
function. For more information, refer to 16.7.5. Flash Patch Breakpoint (FPB).
Hardware trace: The ITM emits packets generated by the DWT.
Timestamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the
timestamp.
16.7.7.1 How to Configure the ITM
The following example describes how to output trace data in asynchronous trace mode.
Configure the TPIU for asynchronous trace mode. Refer to 16.7.7.3. How to Configure the TPIU.
1.
2.
Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register
(Address: 0xE0000FB0)
Write 0x00010015 into the Trace Control register:
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 73
SAM E70/S70/V70/V71
Debug and Test Features
3.
4.
5.
– Enable ITM.
– Enable Synchronization packets.
– Enable SWO behavior.
– Fix the ATB ID to 1.
Write 0x1 into the Trace Enable register:
– Enable the Stimulus port 0.
Write 0x1 into the Trace Privilege register:
– Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the
corresponding stimulus port being accessible in user mode.)
Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
16.7.7.2 Asynchronous Mode
The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The
TRACESWO signal is multiplexed with the TDO signal. As a consequence, asynchronous trace mode is only
available when the Serial Wire Debug mode is selected.
Two encoding formats are available for the single pin output:
•
•
Manchester encoded stream. This is the reset value.
NRZ_based UART byte structure
16.7.7.3 How to Configure the TPIU
This example only concerns the asynchronous trace mode.
Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace
and debug blocks.
1.
2.
3.
16.7.8
Write 0x2 into the Selected Pin Protocol Register.
– Select the Serial Wire output – NRZ
Write 0x100 into the Formatter and Flush Control Register.
Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the
asynchronous output (this can be done automatically by the debugging tool).
IEEE1149.1 JTAG Boundary Scan
IEEE1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE1149.1 JTAG Boundary Scan is enabled when TST is tied to high, PD0 tied to low, and JTAGSEL tied to high
during powerup. These pins must be maintained in their respective states for the duration of the boundary scan
operation. The SAMPLE, EXTEST and BYPASS functions are implemented. In Serial Wire Debug mode, the ARM
processor responds with a non-JTAG chip ID that identifies the processor. This is not IEEE1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must
be performed after JTAGSEL is changed.
A Boundary Scan Descriptor Language (BSDL) file to set up the test is provided on www.microchip.com.
16.7.8.1 JTAG Boundary Scan Register
The Boundary Scan Register (BSR) contains a number of bits which correspond to active pins and associated control
signals.
Each input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on
the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction
of the pad.
For more information, refer to BDSL files available on www.microchip.com.
16.7.9
ID Code Register
Access: Read-only
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 74
SAM E70/S70/V70/V71
Debug and Test Features
31
30
29
28
27
26
25
24
18
17
16
10
9
8
VERSION
23
22
21
PART NUMBER
20
19
PART NUMBER
15
14
13
12
11
PART NUMBER
7
6
5
MANUFACTURER IDENTITY
4
3
2
MANUFACTURER IDENTITY
•
VERSION[31:28]: Product Version Number
Set to 0x0.
•
PART NUMBER[27:12]: Product Part Number
Set to 0x0.
1
0
1
PART NUMBER
0x5B3D
•
MANUFACTURER IDENTITY[11:1]: Manufacturer ID
Set to 0x01F.
•
Bit[0]: Required by IEEE Std. 1149.1
Set to 0x1.
JTAG ID Code
0x5B3D_D03F
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 75
SAM E70/S70/V70/V71
SAM-BA Boot Program
17.
SAM-BA Boot Program
17.1
Description
The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different
memories of the product.
17.2
Embedded Characteristics
•
•
•
17.3
Default Boot program
Interface with SAM-BA graphic user interface (GUI)
SAM-BA Boot
– Supports several communication media:
• Serial Communication on UART0
• USB device port communication up to 1Mbyte/s
– USB Requirements:
• External crystal or external clock with frequency of 12 MHz or 16 MHz
Hardware and Software Constraints
•
•
•
SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available bytes
can be used for the user code.
USB requirements:
– External crystal or external clock (see Note below) with frequency of 12 MHz or 16 MHz
Note: Must be 2500 ppm and VDDIO square wave signal.
UART0 requirements:
– None. If accurate external clock source is not available, the internal 12 MHz RC meets RS-232 standards
at room temperature.
Table 17-1. Pins Driven during Boot Program Execution
17.4
Peripheral
Pin
PIO Line
UART0
URXD0
PA9
UART0
UTXD0
PA10
Flow Diagram
The boot program implements the algorithm below.
Figure 17-1. Boot Program Algorithm Flow Diagram
No
Device
Setup
USB Enumeration
Successful ?
No
Yes
Run SAM-BA Monitor
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
Character # received
from UART0?
Yes
Run SAM-BA Monitor
DS60001527G-page 76
SAM E70/S70/V70/V71
SAM-BA Boot Program
The SAM-BA boot program looks for a source clock, either from the embedded main oscillator with external crystal
(main oscillator enabled) or from a supported frequency signal applied to the XIN pin (Main oscillator in bypass
mode).
If a clock is supplied by one of the two sources, the boot program checks that the frequency is one of the supported
external frequencies. If the frequency is supported, USB activation is allowed. If no clock is supplied, or if a clock is
supplied but the frequency is not a supported external frequency, the internal 12 MHz RC oscillator is used as the
main clock. In this case, the USB is not activated due to the frequency drift of the 12 MHz RC oscillator.
17.5
Device Initialization
Initialization by the boot program follows the steps described below:
Stack setup.
1.
2.
3.
Embedded Flash Controller setup.
External clock (crystal or external clock on XIN) detection.
External crystal or clock with supported frequency supplied.
a. If yes, USB activation is allowed.
b. If no, USB activation is not allowed. The internal 12 MHz RC oscillator is used.
4. Host clock switch to main oscillator.
5. C variable initialization.
6. PLLA setup: PLLA is initialized to generate a 48 MHz clock.
7. Watchdog disable.
8. Initialization of UART0 (115200 bauds, 8, N, 1).
9. Initialization of the USB Device Port (only if USB activation is allowed; see Step 4.).
10. Wait for one of the following events:
a. Check if USB device enumeration has occurred.
b. Check if characters have been received in UART0.
11. Jump to SAM-BA Monitor (refer to 17.6. SAM-BA Monitor)
17.6
SAM-BA Monitor
Once the communication interface is identified, the monitor runs in an infinite loop, waiting for different commands, as
shown in the following table.
Table 17-2. Commands Available through the SAM-BA Boot
Command
Action
Arguments
Example
N
Set Normal mode
No argument
N#
T
Set Terminal mode
No argument
T#
O
Write a byte
Address, Value#
O200001,CA#
o
Read a byte
Address,#
o200001,#
H
Write a half word
Address, Value#
H200002,CAFE#
h
Read a half word
Address,#
h200002,#
W
Write a word
Address, Value#
W200000,CAFEDECA#
w
Read a word
Address,#
w200000,#
S
Send a file
Address,#
S200000,#
R
Receive a file
Address, NbOfBytes#
R200000,1234#
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 77
SAM E70/S70/V70/V71
SAM-BA Boot Program
...........continued
Command
Action
Arguments
Example
G
Go
Address#
G200200#
V
Display version
No argument
V#
•
•
•
•
•
•
•
17.6.1
Mode commands:
– Normal mode configures SAM-BA Monitor to send/receive data in binary format
– Terminal mode configures SAM-BA Monitor to send/receive data in ASCII format
Write commands: Write a byte (O), a halfword (H) or a word (W) to the target
– Address: Address in hexadecimal
– Value: Byte, halfword or word to write in hexadecimal
Read commands: Read a byte (o), a halfword (h) or a word (w) from the target
– Address: Address in hexadecimal
– Output: The byte, halfword or word read in hexadecimal
Send a file (S): Send a file to a specified address
– Address: Address in hexadecimal
Note: There is a timeout on this command which is reached when the prompt ‘>’ appears before the end
of the command execution.
Receive a file (R): Receive data into a file from a specified address
– Address: Address in hexadecimal
– NbOfBytes: Number of bytes in hexadecimal to receive
Go (G): Jump to a specified address and execute the code
– Address: Address to jump in hexadecimal
Get Version (V): Return the SAM-BA boot version
Note: In Terminal mode, when the requested command is performed, SAM-BA Monitor adds the following
prompt sequence to its answer: ++'>'.
UART0 Serial Port
Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this
protocol can be used to send the application file to the target. The size of the binary file to send depends on
the SRAM size embedded in the product. In all cases, the size of the binary file must be smaller than the SRAM
size because the Xmodem protocol requires some SRAM memory to work. Refer to the "Hardware and Software
Constraints" section.
17.6.2
Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to
guarantee detection of a maximum bit error.
The Xmodem protocol with CRC is accurate if both sender and receiver report successful transmission. Each block of
the transfer has the following format:
in which:
•
•
•
•
= 01 hex
= binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
= 1’s complement of the blk#.
= 2 bytes CRC16
The figure below shows a transmission using this protocol.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 78
SAM E70/S70/V70/V71
SAM-BA Boot Program
Figure 17-2. Xmodem Transfer Example
Host
Device
C
SOH 01 FE Data[128] CRC CRC
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
17.6.3
USB Device Port
The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232
software to talk over the USB. The CDC class is implemented in all releases of Windows®, beginning with Windows
98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems
and virtual COM ports.
The Vendor ID (VID) is the Atmel vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are
used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the
correspondence between vendor ID and product ID.
For more details on VID/PID for end product/systems, refer to the Vendor ID form available from the USB
Implementers Forum found at http://www.usb.org/.
WARNING
Unauthorized use of assigned or unassigned USB Vendor ID Numbers and associated Product ID
Numbers is strictly prohibited.
17.6.3.1 Enumeration Process
The USB protocol is a Host/Client protocol. This is the host that starts the enumeration sending requests to the
device through the control endpoint. The device handles standard requests as defined in the USB Specification.
Table 17-3. Handled Standard Requests
Request
Definition
GET_DESCRIPTOR
Returns the current device configuration value.
SET_ADDRESS
Sets the device address for all future device access.
SET_CONFIGURATION
Sets the device configuration.
GET_CONFIGURATION
Returns the current device configuration value.
GET_STATUS
Returns status for the specified recipient.
SET_FEATURE
Set or Enable a specific feature.
CLEAR_FEATURE
Clear or Disable a specific feature.
The device also handles some class requests defined in the CDC class.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 79
SAM E70/S70/V70/V71
SAM-BA Boot Program
Table 17-4. Handled Class Requests
Request
Definition
SET_LINE_CODING
Configures DTE rate, stop bits, parity and number of character bits.
GET_LINE_CODING
Requests current DTE rate, stop bits, parity and number of character bits.
SET_CONTROL_LINE_STATE
RS-232 signal used to tell the DCE device the DTE device is now present.
Unhandled requests are STALLed.
17.6.3.2 Communication Endpoints
There are two communication endpoints. Endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte
Bulk OUT endpoint. Endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through
endpoint 1. If required, the message is split by the host into several data payloads by the host driver.
If the command requires a response, the host can send IN transactions to pick up the response.
17.6.4
In Application Programming (IAP) Feature
The IAP feature is a function located in ROM that can be called by any software application.
When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready
(looping while the FRDY bit is not set in the MC_FSR register).
Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code
running in Flash.
The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008).
This function takes two arguments as parameters:
•
•
the index of the Flash bank to be programmed: 0 for EEFC0, 1 for EEFC1. For devices with only one bank, this
parameter has no effect and can be either 0 or 1, only EEFC0 will be accessed.
the command to be sent to the EEFC Command register.
This function returns the value of the EEFC_FSR register.
An example of IAP software code follows:
// Example: How to write data in page 200 of the flash memory using ROM IAP function
flash_page_num = 200
flash_cmd = 0
flash_status = 0
eefc_index = 0 (0 for EEFC0, 1 for EEFC1)
// Initialize the function pointer (retrieve function address from NMI vector)*/
iap_function_address = 0x00800008
// Fill the Flash page buffer at address 200 with the data to be written
for i=0, i < page_size, i++ do
flash_sector_200_address[i] = your_data[i]
// Prepare the command to be sent to the EEFC Command register: key, page number and
write command
flash_cmd = (0x5A programming period reduced
=> Only 1 word programmed => programming period reduced
32 bits wide
FF
4 x 32 bits
4 x 32 bits
FF
FF
FF
FF
FF
32 bits wide
FF
0xX1C
FF
FF
FF
FF
FF
FF
FF
FF
FF
0xX1C
0xX18
FF
FF
FF
0xX14
FF
0xX10
0xX18
CA
FE
CA
FE
0xX14
FF
CA
CA
FE
FE
CA
CA
FE
FE
0xX10
FF
FF
FF
0xX0C
CA
FE
CA
FE
0xX0C
CA
FE
CA
FE
0xX08
CA
FE
CA
FE
0xX08
FF
FF
FF
FF
0xX04
CA
FE
CA
FE
0xX04
FF
FF
FF
FF
0xX00
CA
FE
CA
FE
0xX00
Case 3: 4 x 32 bits modified across 128-bit boundary
Case 4: 4 x 32 bits modified, not crossing 128-bit boundary
User programs WP, Flash Controller sends WP
User programs WP, Flash Controller sends Write Word
=> Whole page programmed
=> Only 1 word programmed => programming period reduced
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 134
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
Figure 22-11. Programming Bytes in the Flash
32 bits wide
4 x 32 bits =
1 Flash word
4 x 32 bits =
1 Flash word
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
xx
xx
xx
xx
xx
xx
32 bits wide
FF
FF
FF
FF
0xX1C
xx
xx
xx
xx
0xX1C
0xX18
xx
xx
xx
0xX18
0xX14
xx
xx
xx
xx
0xX14
FF
address space
for
Page N
0xX10
xx
xx
xx
xx
55
0xX10
xx
xx
0xX0C
xx
xx
xx
xx
0xX0C
xx
xx
0xX08
xx
xx
xx
xx
0xX08
xx
xx
xx
0xX04
xx
xx
xx
xx
0xX04
xx
xx
AA
0xX00
xx
xx
xx
AA
0xX00
Step 1: Flash array after programming first byte (0xAA)
Step 2: Flash array after programming second byte (0x55)
128-bit used at address 0xX00 (write latch buffer + WP)
128-bit used at address 0xX10 (write latch buffer + WP)
Note: The byte location shown here is for example only, it can be any byte location within a 64-bit word
22.4.3.3 Erase Commands
Erase commands are allowed only on unlocked regions. Depending on the Flash memory, several commands can be
used to erase the Flash:
•
•
•
Erase All Memory (EA): All memory is erased. The processor must not fetch code from the Flash memory.
Erase Pages (EPA): 4, 8, 16, or 32 pages are erased in the Flash sector selected. The first page to be erased
is specified in the FARG[15:2] field of the EEFC_FCR. The first page number must be a multiple of 8, 16, or 32
depending on the number of pages to erase simultaneously.
Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory.
EEFC_FCR.FARG must be set with a page number that is in the sector to be erased.
Note: If one sub-sector is locked within the first sector, the Erase Sector (ES) command cannot be processed on
non-locked sub-sectors of the first sector. All the lock bits of the first sector must be cleared prior to issuing an ES
command on the first sector. After the ES command has been issued, the first sector lock bits must be reverted to the
state before clearing them.
If the processor is fetching code from the Flash memory while the EPA or ES command is being executed, the
processor accesses are stalled until the EPA command is completed. To avoid stalling the processor, the code can be
run out of internal SRAM.
The following are the erase sequence:
1.
Erase starts immediately one of the erase commands and the FARG field are written in EEFC_FCR.
For the EPA command, the two lowest bits of the FARG field define the number of pages to be erased
(FARG[1:0]), see table below.
Table 22-3. EEFC_FCR.FARG Field for EPA Command
FARG[1:0]
Number of pages to be erased with EPA command
0
4 pages (only valid for small 8-KB sectors)
1
8 pages (only valid for small 8-KB sectors)
2
16 pages
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 135
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
...........continued
FARG[1:0]
Number of pages to be erased with EPA command
3
32 pages (not valid for small 8-KB sectors)
2.
When erasing is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the
EEFC_FMR.FRDY bit, the interrupt line of the interrupt controller is activated.
Three errors can be detected in EEFC_FSR after an erasing sequence:
•
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Lock Error: At least one page to be erased belongs to a locked region. The erase command has been refused,
no page has been erased. A command must be run previously to unlock the corresponding region.
Flash Error: At the end of the erase period, the EraseVerify test of the Flash memory has failed. After a first
programming pulse, a Verify is applied. The memory is read, to compare both programmed and expected
values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse
number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set
high.
22.4.3.4 Lock Bit Protection
Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the
embedded Flash memory plane. They prevent writing/erasing protected pages.
The following are lock sequence:
1.
2.
3.
Execute the ‘Set Lock Bit’ command by writing the EEFC_FCR.FCMD bit with the SLB command and
EEFC_FCR.FARG with a page number to be protected.
When the locking completes, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the bit
EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
The result of the SLB command can be checked running a ‘Get Lock Bit’ (GLB) command.
Note: The value of the FARG argument passed together with SLB command must not exceed the higher lock
bit index available in the product.
The following two errors can be detected in EEFC_FSR after a programming sequence:
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and
expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum
pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is
set high.
It is possible to clear lock bits previously set. After the lock bits are cleared, the locked region can be erased or
programmed. The unlock sequence is the following:
1.
2.
Execute the ‘Clear Lock Bit’ command by writing the EEFC_FCR.FCMD bit with the CLB command and the
EEFC_FCR.FARG bit with a page number to be unprotected.
When the unlock completes, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting the
EEFC_FMR.FRDY bit, the interrupt line of the interrupt controller is activated.
Note: The value of the FARG argument passed together with CLB command must not exceed the higher lock
bit index available in the product.
Two errors can be detected in EEFC_FSR after a programming sequence:
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and
expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum
pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is
set high.
The status of lock bits can be returned by the EEFC. The ‘Get Lock Bit’ sequence is the following:
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 136
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
1.
2.
Execute the ‘Get Lock Bit’ command by writing EEFC_FCR.FCMD with the GLB command. Field
EEFC_FCR.FARG is meaningless.
Lock bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32
first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to EEFC_FRR
return 0.
For example, if the third bit of the first word read in EEFC_FRR is set, the third lock region is locked.
Two errors can be detected in EEFC_FSR after a programming sequence:
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and
expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum
pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is
set high.
Note: Access to the Flash in read is permitted when a ‘Set Lock Bit’, ‘Clear Lock Bit’ or ‘Get Lock Bit’ command
is executed.
22.4.3.5 GPNVM Bit
The GPNVM bits do not interfere with the embedded Flash memory plane. For more details, refer to the “Memories”
chapter.
The ‘Set GPNVM Bit’ sequence is the following:
1.
2.
3.
Execute the ‘Set GPNVM Bit’ command by writing EEFC_FCR.FCMD with the SGPB command and
EEFC_FCR.FARG with the number of GPNVM bits to be set.
When the GPNVM bit is set, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by setting the bit
EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
The result of the SGPB command can be checked by running a ‘Get GPNVM Bit’ (GGPB) command.
Note: The value of the FARG argument passed together with SGPB command must not exceed the higher GPNVM
index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is
detected only if FARG is greater than 8.
Two errors can be detected in EEFC_FSR after a programming sequence:
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and
expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum
pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is
set high.
It is possible to clear GPNVM bits previously set. The ‘Clear GPNVM Bit’ sequence is the following:
1.
2.
Execute the ‘Clear GPNVM Bit’ command by writing EEFC_FCR.FCMD with the CGPB command and
EEFC_FCR.FARG with the number of GPNVM bits to be cleared.
When the clear completes, the bit EEFC_FSR.FRDY rises. If an interrupt has been enabled by setting the bit
EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note: The value of the FARG argument passed together with CGPB command must not exceed the higher GPNVM
index available in the product. Flash data content is not altered if FARG exceeds the limit. Command Error is
detected only if FARG is greater than 8.
Two errors can be detected in EEFC_FSR after a programming sequence:
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
After a first programming pulse, a Verify is applied. The memory is read, to compare both programmed and
expected values. If that comparison fails, a second programming pulse is applied, and so on, until a maximum
pulse number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is
set high.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 137
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
The status of GPNVM bits can be returned by the EEFC. The sequence is the following:
1.
2.
Execute the ‘Get GPNVM Bit’ command by writing EEFC_FCR.FCMD with the GGPB command. Field
EEFC_FCR.FARG is meaningless.
GPNVM bits can be read by the software application in EEFC_FRR. The first word read corresponds to the 32
first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads to
EEFC_FRR return 0.
For example, if the third bit of the first word read in EEFC_FRR is set, the third GPNVM bit is active.
One error can be detected in EEFC_FSR after a programming sequence:
•
Command Error: A bad keyword has been written in EEFC_FCR.
Note: Access to the Flash in read is permitted when a ‘Set GPNVM Bit’, ‘Clear GPNVM Bit’ or ‘Get GPNVM Bit’
command is executed.
Related Links
11. Memories
22.4.3.6 Calibration Bit
Calibration bits do not interfere with the embedded Flash memory plane.
The calibration bits cannot be modified.
The status of calibration bits are returned by the EEFC. The sequence is as follows:
1.
2.
Execute the ‘Get CALIB Bit’ command by writing EEFC_FCR.FCMD with the GCALB command. Field
EEFC_FCR.FARG is meaningless.
Calibration bits can be read by the software application in EEFC_FRR. The first word read corresponds to
the first 32 calibration bits. The following reads provide the next 32 calibration bits as long as it is meaningful.
Extra reads to EEFC_FRR return 0.
The 8/12 MHz internal RC oscillator is calibrated in production. This calibration can be read through the GCALB
command. Table 22-4 shows the bit implementation.
The RC calibration for the 4 MHz is set to ‘1000000’.
Table 22-4. Calibration Bit Indexes
Description
EEFC_FRR Bits
8 MHz RC calibration output
[28–22]
12 MHz RC calibration output
[38–32]
22.4.3.7 Security Bit Protection
When the security bit is enabled, the Embedded Trace Macrocell (ETM) is disabled and access to the Flash through
the SWD interface or through the Fast Flash Programming interface is forbidden. This ensures the confidentiality of
the code programmed in the Flash.
The security bit is GPNVM0.
Disabling the security bit can only be achieved by asserting the ERASE signal at ‘1’, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash are permitted.
22.4.3.8 Unique Identifier Area
Each device is programmed with a 128-bit unique identifier area .
See “Flash Memory Areas”.
The sequence to read the unique identifier area is the following:
1.
2.
Execute the ‘Start Read Unique Identifier’ command by writing EEFC_FCR.FCMD with the STUI command.
Field EEFC_FCR.FARG is meaningless.
Wait until the bit EEFC_FSR.FRDY falls to read the unique identifier area. The unique identifier field is located
in the first 128 bits of the Flash memory mapping. The ‘Start Read Unique Identifier’ command reuses some
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 138
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
3.
4.
addresses of the memory plane for code, but the unique identifier area is physically different from the memory
plane for code.
To stop reading the unique identifier area, execute the ‘Stop Read Unique Identifier’ command by writing
EEFC_FCR.FCMD with the SPUI command. Field EEFC_FCR.FARG is meaningless.
When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by
setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note: During the sequence, the software cannot be fetched from the Flash.
22.4.3.9 User Signature Area
Each product contains a user signature area of 512 bytes. It can be used for storage. Read, write, and erase of this
area is allowed. Refer to “Flash Memory Areas”.
The sequence to read the user signature area is as follows:
1.
2.
3.
4.
Execute the ‘Start Read User Signature’ command by writing EEFC_FCR.FCMD with the STUS command.
Field EEFC_FCR.FARG is meaningless.
Wait until the EEFC_FSR.FRDY bit falls to read the user signature area. The user signature area is located
in the first 512 bytes of the Flash memory mapping. The ‘Start Read User Signature’ command reuses some
addresses of the memory plane but the user signature area is physically different from the memory plane
To stop reading the user signature area, execute the ‘Stop Read User Signature’ command by writing
EEFC_FCR.FCMD with the SPUS command. Field EEFC_FCR.FARG is meaningless.
When the SPUI command has been executed, the bit EEFC_FSR.FRDY rises. If an interrupt was enabled by
setting the bit EEFC_FMR.FRDY, the interrupt line of the interrupt controller is activated.
Note: During the sequence, the software cannot be fetched from the Flash or from the second plane in case of dual
plane.
One error can be detected in EEFC_FSR after this sequence:
•
Command Error: A bad keyword has been written in EEFC_FCR.
The sequence to write the user signature area is as follows:
1.
2.
3.
Write the full page, at any page address, within the internal memory area address space.
Execute the ‘Write User Signature’ command by writing EEFC_FCR.FCMD with the WUS command. Field
EEFC_FCR.FARG is meaningless.
When programming is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting
the EEFC_FMR.FRDY bit, the corresponding interrupt line of the interrupt controller is activated.
The following two errors can be detected in EEFC_FSR after this sequence:
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the WriteVerify test of the Flash memory has failed. After a first
programming pulse, a Verify is applied. The memory is read, to compare what is programmed with what is
expected. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse
number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set
high.
The sequence to erase the user signature area is as follows:
1.
2.
Execute the ‘Erase User Signature’ command by writing EEFC_FCR.FCMD with the EUS command. Field
EEFC_FCR.FARG is meaningless.
When programming is completed, the EEFC_FSR.FRDY bit rises. If an interrupt has been enabled by setting
the EEFC_FMR.FRDY bit, the corresponding interrupt line of the interrupt controller is activated.
Two errors can be detected in EEFC_FSR after this sequence:
•
•
Command Error: A bad keyword has been written in EEFC_FCR.
Flash Error: At the end of the programming, the EraseVerify test of the Flash memory has failed. After a first
programming pulse, a Verify is applied. The memory is read, to compare what is programmed with what is
expected. If that comparison fails, a second programming pulse is applied, and so on, until a maximum pulse
number is reached. At this time, if the memory is still not containing what is expected, the FLERR flag is set
high.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 139
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
22.4.3.10 ECC Errors and Corrections
The Flash embeds an ECC module able to correct one unique error and able to detect two errors. The errors are
detected while a read access is performed into memory array and stored in EEFC_FSR (see “EEFC Flash Status
Register”). The error report is kept until EEFC_FSR is read.
There is one flag for a unique error on lower half part of the Flash word (64 LSB) and one flag for the upper half part
(MSB). The multiple errors are reported in the same way.
Due to the anticipation technique to improve bandwidth throughput on instruction fetch, a reported error can be
located in the next sequential Flash word compared to the location of the instruction being executed, which is located
in the previously fetched Flash word.
If a software routine processes the error detection independently from the main software routine, the entire Flash
located software must be rewritten because there is no storage of the error location.
If only a software routine is running to program and check pages by reading EEFC_FSR, the situation differs from
the previous case. Performing a check for ECC unique errors just after page programming completion involves a read
of the newly programmed page. This read sequence is viewed as data accesses and is not optimized by the Flash
controller. Thus, in case of unique error, only the current page must be reprogrammed.
22.4.4
Register Write Protection
To prevent any single software error from corrupting EEFC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the “EEFC Write Protection Mode Register” (EEFC_WPMR).
The following register can be write-protected:
•
“EEFC Flash Mode Register”
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 140
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
22.5
Register Summary
Offset
Name
0x00
EEFC_FMR
0x04
EEFC_FCR
0x08
EEFC_FSR
0x0C
EEFC_FRR
0x10
...
0xE3
Reserved
0xE4
EEFC_WPMR
Bit Pos.
7
6
5
4
3
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
FVALUE[7:0]
FVALUE[15:8]
FVALUE[23:16]
FVALUE[31:24]
7:0
15:8
23:16
31:24
WPKEY[7:0]
WPKEY[15:8]
WPKEY[23:16]
© 2022 Microchip Technology Inc.
and its subsidiaries
2
1
0
FRDY
FWS[3:0]
SCOD
CLOE
FCMD[7:0]
FARG[7:0]
FARG[15:8]
FKEY[7:0]
FLERR
FLOCKE
MECCEMSB UECCEMSB
FCMDE
FRDY
MECCELSB
UECCELSB
WPEN
Complete Data Sheet
DS60001527G-page 141
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
22.5.1
EEFC Flash Mode Register
Name:
Offset:
Property:
EEFC_FMR
0x00
Read/Write
This register can only be written if the WPEN bit is cleared in the “EEFC Write Protection Mode Register” .
Bit
31
30
29
28
27
26
CLOE
R/W
25
24
23
22
21
20
19
18
17
16
SCOD
R/W
15
14
13
12
11
10
9
8
Access
Reset
Bit
Access
Reset
Bit
FWS[3:0]
Access
Reset
Bit
7
6
5
4
R/W
R/W
R/W
R/W
3
2
1
0
FRDY
R/W
Access
Reset
Bit 26 – CLOE Code Loop Optimization Enable
No Flash read should be done during change of this field.
Value
Description
0
The opcode loop optimization is disabled.
1
The opcode loop optimization is enabled.
Bit 16 – SCOD Sequential Code Optimization Disable
No Flash read should be done during change of this field.
Value
Description
0
The sequential code optimization is enabled.
1
The sequential code optimization is disabled.
Bits 11:8 – FWS[3:0] Flash Wait State
This field defines the number of wait states for read and write operations:
FWS = Number of cycles for Read/Write operations - 1
Bit 0 – FRDY Flash Ready Interrupt Enable
Value
Description
0
Flash ready does not generate an interrupt.
1
Flash ready (to accept a new command) generates an interrupt.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 142
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
22.5.2
EEFC Flash Command Register
Name:
Offset:
Reset:
Property:
Bit
EEFC_FCR
0x04
–
Write-only
31
30
29
28
27
26
25
24
W
–
W
–
W
–
W
–
19
18
17
16
W
–
W
–
W
–
W
–
11
10
9
8
W
–
W
–
W
–
W
–
3
2
1
0
W
–
W
–
W
–
W
–
FKEY[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bit
23
22
21
20
FARG[15:8]
Access
Reset
W
–
W
–
W
–
W
–
Bit
15
14
13
12
FARG[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bit
7
6
5
4
FCMD[7:0]
Access
Reset
W
–
W
–
W
–
W
–
Bits 31:24 – FKEY[7:0] Flash Write Protection Key
Value
Name
Description
0x5A
PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is
written with a different value, the write is not performed and no action is started.
Bits 23:8 – FARG[15:0] Flash Command Argument
GETD, GLB,
GGPB, STUI,
SPUI, GCALB,
WUS, EUS,
STUS, SPUS,
EA
ES
EPA
Commands requiring
no argument,
including Erase all
command
FARG is meaningless, must be written with 0
Erase sector
command
Erase pages
command
FARG must be written with any page number within the sector to be
erased
FARG[1:0] defines the number of pages to be erased
The start page must be written in FARG[15:2].
FARG[1:0] = 0: Four pages to be erased. FARG[15:2] = Page_Number /
4
FARG[1:0] = 1: Eight pages to be erased. FARG[15:3] = Page_Number /
8, FARG[2]=0
FARG[1:0] = 2: Sixteen pages to be erased. FARG[15:4] =
Page_Number / 16, FARG[3:2]=0
FARG[1:0] = 3: Thirty-two pages to be erased. FARG[15:5] =
Page_Number / 32, FARG[4:2]=0
Refer to “EEFC_FCR.FARG Field for EPA Command”.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 143
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
WP, WPL, EWP,
EWPL
SLB, CLB
SGPB, CGPB
Programming
commands
Lock bit commands
GPNVM commands
Bits 7:0 – FCMD[7:0] Flash Command
Value
Name
0x00
GETD
0x01
WP
0x02
WPL
0x03
EWP
0x04
EWPL
0x05
EA
0x07
EPA
0x08
SLB
0x09
CLB
0x0A
GLB
0x0B
SGPB
0x0C
CGPB
0x0D
GGPB
0x0E
STUI
0x0F
SPUI
0x10
GCALB
0x11
ES
0x12
WUS
0x13
EUS
0x14
STUS
0x15
SPUS
© 2022 Microchip Technology Inc.
and its subsidiaries
FARG must be written with the page number to be programmed
FARG defines the page number to be locked or unlocked
FARG defines the GPNVM number to be programmed
Description
Get Flash descriptor
Write page
Write page and lock
Erase page and write page
Erase page and write page then lock
Erase all
Erase pages
Set lock bit
Clear lock bit
Get lock bit
Set GPNVM bit
Clear GPNVM bit
Get GPNVM bit
Start read unique identifier
Stop read unique identifier
Get CALIB bit
Erase sector
Write user signature
Erase user signature
Start read user signature
Stop read user signature
Complete Data Sheet
DS60001527G-page 144
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
22.5.3
EEFC Flash Status Register
Name:
Offset:
Property:
Bit
EEFC_FSR
0x08
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
MECCEMSB
R
18
UECCEMSB
R
17
MECCELSB
R
16
UECCELSB
R
15
14
13
12
11
10
9
8
7
6
5
4
3
FLERR
R
2
FLOCKE
R
1
FCMDE
R
0
FRDY
R
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 19 – MECCEMSB Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
Value
Description
0
No multiple error detected on 64 MSB part of the Flash memory data bus since the last read of
EEFC_FSR.
1
Multiple errors detected and NOT corrected on 64 MSB part of the Flash memory data bus since the
last read of EEFC_FSR.
Bit 18 – UECCEMSB Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
Value
Description
0
No unique error detected on 64 MSB data bus of the Flash memory since the last read of EEFC_FSR.
1
One unique error detected but corrected on 64 MSB data bus of the Flash memory since the last read
of EEFC_FSR.
Bit 17 – MECCELSB Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
Value
Description
0
No multiple error detected on 64 LSB part of the Flash memory data bus since the last read of
EEFC_FSR.
1
Multiple errors detected and NOT corrected on 64 LSB part of the Flash memory data bus since the
last read of EEFC_FSR.
Bit 16 – UECCELSB Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
Value
Description
0
No unique error detected on 64 LSB data bus of the Flash memory since the last read of EEFC_FSR.
1
One unique error detected but corrected on 64 LSB data bus of the Flash memory since the last read
of EEFC_FSR.
Bit 3 – FLERR Flash Error Status (cleared when a programming operation starts)
Value
Description
0
No Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has
passed).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 145
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
Value
1
Description
A Flash memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed).
Bit 2 – FLOCKE Flash Lock Error Status (cleared on read)
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
Value
Description
0
No programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
1
Programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
Bit 1 – FCMDE Flash Command Error Status (cleared on read or by writing EEFC_FCR)
Value
Description
0
No invalid commands and no bad keywords were written in EEFC_FMR.
1
An invalid command and/or a bad keyword was/were written in EEFC_FMR.
Bit 0 – FRDY Flash Ready Status (cleared when Flash is busy)
When set, this flag triggers an interrupt if the FRDY flag is set in EEFC_FMR.
This flag is automatically cleared when the EEFC is busy.
Value
Description
0
The EEFC is busy.
1
The EEFC is ready to start a new command.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 146
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
22.5.4
EEFC Flash Result Register
Name:
Offset:
Property:
EEFC_FRR
0x0C
Read-only
Bit
31
30
29
28
27
FVALUE[31:24]
R
R
26
25
24
Access
Reset
R
R
R
R
R
R
Bit
23
22
21
20
19
FVALUE[23:16]
R
R
18
17
16
Access
Reset
R
R
R
R
R
R
Bit
15
14
13
10
9
8
R
12
11
FVALUE[15:8]
R
R
Access
Reset
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
R
R
R
R
FVALUE[7:0]
Access
Reset
R
R
R
R
Bits 31:0 – FVALUE[31:0] Flash Result Value
The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, the next
resulting value is accessible at the next register read.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 147
SAM E70/S70/V70/V71
Enhanced Embedded Flash Controller (EEFC)
22.5.5
EEFC Write Protection Mode Register
Name:
Offset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
EEFC_WPMR
0xE4
Read/Write
31
30
29
R/W
R/W
R/W
23
22
21
R/W
R/W
R/W
15
14
13
R/W
R/W
R/W
7
6
5
28
27
WPKEY[23:16]
R/W
R/W
20
19
WPKEY[15:8]
R/W
R/W
12
11
WPKEY[7:0]
R/W
R/W
4
3
26
25
24
R/W
R/W
R/W
18
17
16
R/W
R/W
R/W
10
9
8
R/W
R/W
R/W
2
1
0
WPEN
R/W
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key
See “Register Write Protection” for the list of registers that can be protected.
Value
Name
Description
0x454643 PASSWD
Writing any other value in this field aborts the write operation.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
See “Register Write Protection” for the list of registers that can be protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x454643 (EFC in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x454643 (EFC in ASCII).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 148
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.
Supply Controller (SUPC)
23.1
Description
The Supply Controller (SUPC) controls the supply voltages of the system and manages the Backup mode. In this
mode, current consumption is reduced to a few microamps for backup power retention. Exit from this mode is
possible on multiple wakeup sources. The SUPC also generates the slow clock by selecting either the slow RC
oscillator or the 32.768 kHz crystal oscillator.
23.2
Embedded Characteristics
•
•
•
•
•
•
•
Management of the Core Power Supply VDDCORE and Backup Mode via the Embedded Voltage Regulator
Supply Monitor Detection on VDDIO or a Brownout Detection on VDDCORE Triggers a Core Reset
Generates the Slow Clock SLCK by selecting either the 22-42 kHz Slow RC Oscillator or the 32.768 kHz Crystal
Oscillator
Backup SRAM
Low-power Tamper Detection on Two Inputs
Anti-tampering by Immediate Clear of the General-purpose Backup Registers
Support of Multiple Wakeup Sources for Exit from Backup Mode
– 14 Wakeup Inputs with Programmable Debouncing
– Real-Time Clock Alarm
– Real-Time Timer Alarm
– Supply Monitor Detection on VDDIO, with Programmable Scan Period and Voltage Threshold
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 149
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.3
Block Diagram
Figure 23-1. Supply Controller Block Diagram
Supply Controller
Power-On Reset
VDDCORE
bod_out
Brown-Out
Detector
VDDCORE
SMRSTEN
SMIEN
Reset
Controller
Supply
Monitor
Controller
sm_out
Zero-Power
Power-On Reset
VDDIO
NRST
proc_nreset
periph_nreset
ice_nreset
por_io_out
SLCK
XTALSEL
OSCBYPASS
XOUT32
vddcore_nreset
SMTH
Programmable
Supply Monitor
VDDIO
XIN32
Interrupt
Controller
BODRSTEN
BODDIS
SMSMPL
supc_irq
por_core_out
Slow
Clock
Controller
32.768 kHz
Crystal Oscillator
SLCK
Real-Time
Timer
Slow RC Oscillator
rtt_alarm
sm_out
SMEN
RTTEN
Real-Time
Clock
WKUP0-WKUP13
Wakeup
Controller
LPDBC
LPDBCEN0
LPDBCEN1
rtc_alarm
RTCEN
RTCOUT0
RTCOUT1
LPDBCCLR
WKUPEN0..15
clear
WKUPT0..15
General-Purpose
Backup Registers
WKUPDBC
BKUPRETON
VDDIO
Power Switch
Backup
Mode
Backup
SRAM
1
ONREG
VDDCORE
Backup Area
VROFF
0
VDDIN
wake_up
Voltage Regulator
Controller
on/off
Core Voltage
Regulator
VDDOUT
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 150
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.4
Functional Description
23.4.1
Overview
The device is divided into two power supply areas:
•
•
VDDIO power supply: includes the Supply Controller, part of the Reset Controller, the slow clock switch, the
general-purpose backup registers, the supply monitor and the clock which includes the Real-time Timer and the
Real-time Clock.
Core power supply: includes part of the Reset Controller, the Brownout Detector, the processor, the SRAM
memory, the Flash memory and the peripherals.
The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC intervenes when the
VDDIO power supply rises (when the system is starting) or when Backup mode is entered.
The SUPC also integrates the slow clock generator, which is based on a 32.768 kHz crystal oscillator, and a slow
RC oscillator. The slow clock defaults to the slow RC oscillator, but the software can enable the 32.768 kHz crystal
oscillator and select it as the slow clock source.
The SUPC and the VDDIO power supply have a reset circuitry based on a zero-power power-on reset cell. The
zero-power power-on reset allows the SUPC to start correctly as soon as the VDDIO voltage becomes valid.
At startup of the system, once the backup voltage VDDIO is valid and the slow RC oscillator is stabilized, the SUPC
starts up the core by sequentially enabling the internal voltage regulator. The SUPC waits until the core voltage
VDDCORE is valid, then releases the reset signal of the core vddcore_nreset signal.
Once the system has started, the user should program a supply monitor and/or a brownout detector. If the
supply monitor detects a voltage level on VDDIO that is too low, the SUPC asserts the reset signal of the core
vddcore_nreset signal until VDDIO is valid. Likewise, if the brownout detector detects a core voltage level VDDCORE
that is too low, the SUPC asserts the reset signal vddcore_nreset until VDDCORE is valid.
When Backup mode is entered, the SUPC sequentially asserts the reset signal of the core power supply
vddcore_nreset and disables the voltage regulator, in order to supply only the VDDIO power supply. Current
consumption is reduced to a few microamps for the backup part retention. Exit from this mode is possible on multiple
wakeup sources including an event on WKUP pins, or a clock alarm. To exit this mode, the SUPC operates in the
same way as system startup.
23.4.2
Slow Clock Generator
The SUPC embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the VDDIO
is supplied, both the 32.768 kHz crystal oscillator and the slow RC oscillator are powered up, but only the slow RC
oscillator is enabled. When the slow RC oscillator is selected as the slow clock source, the slow clock stabilizes more
quickly than when the 32.768 kHz crystal oscillator is selected.
The user can select the 32.768 kHz crystal oscillator to be the source of the slow clock, as it provides a more
accurate frequency than the slow RC oscillator. The 32.768 kHz crystal oscillator is selected by setting the XTALSEL
bit in the SUPC Control register (SUPC_CR). The following sequence must be used to switch from the slow RC
oscillator to the 32.768 kHz crystal oscillator:
1.
2.
3.
4.
5.
The PIO lines multiplexed with XIN32 and XOUT32 are configured to be driven by the oscillator.
The 32.768 kHz crystal oscillator is enabled.
A number of slow RC oscillator clock periods is counted to cover the startup time of the 32.768 kHz crystal
oscillator. Refer to the section “Electrical Characteristics” for information on the 32.768 kHz crystal oscillator
startup time.
The slow clock is switched to the output of the 32.768 kHz crystal oscillator.
The slow RC oscillator is disabled to save power.
The switching time may vary depending on the slow RC oscillator clock frequency range. The switch of the slow clock
source is glitch-free. The OSCSEL bit of the SUPC Status register (SUPC_SR) indicates when the switch sequence
is finished.
Reverting to the slow RC oscillator as a slow clock source is only possible by shutting down the VDDIO power supply.
If the user does not need the 32.768 kHz crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 151
SAM E70/S70/V70/V71
Supply Controller (SUPC)
The user can also set the 32.768 kHz crystal oscillator in Bypass mode instead of connecting a crystal. In this case,
the user has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in
the section “Electrical Characteristics”. To enter Bypass mode, the OSCBYPASS bit in the Mode register (SUPC_MR)
must be set before setting XTALSEL.
Related Links
57. Electrical Characteristics for SAM V70/V71
58. Electrical Characteristics for SAM E70/S70
23.4.3
Core Voltage Regulator Control/Backup Low-power Mode
The SUPC controls the embedded voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. Refer to the
section “Electrical Characteristics”.
The user can switch off the voltage regulator, and thus put the device in Backup mode, by writing a ‘1’ to
SUPC_CR.VROFF.
This asserts the vddcore_nreset signal after the write resynchronization time, which lasts two slow clock cycles (worst
case). Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock
cycle before the core power supply shuts off.
When the internal voltage regulator is not used and VDDCORE is supplied by an external supply, the voltage
regulator can be disabled by writing a ‘0’ to SUPC_MR.ONREG.
Related Links
57. Electrical Characteristics for SAM V70/V71
58. Electrical Characteristics for SAM E70/S70
23.4.4
Using Backup Batteries/Backup Supply
When backup batteries or, more generally, a separate backup supply is used, only VDDIO is present in Backup
mode. No other external supply is applied.
Figure 23-2. Separate Backup Supply Powering Scheme
VDDUTMII
Main Supply
USB
Transceivers
VDDIO
ADC, DAC
Analog Comp.
VDDIN
VDDOUT
VDDCORE Supply
VDDCORE
Voltage
Regulator
VDDPLL
VDDUTMIC
Note: Restrictions
With main supply < 3.0V, USB is not usable.
With main supply < 2.7V, MediaLB is not usable.
With main supply < 2.0V, ADC, DAC and Analog comparator are not usable.
With main supply and VDDIN > 3V, all peripherals are usable.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 152
SAM E70/S70/V70/V71
Supply Controller (SUPC)
When no separate backup supply for VDDIO is used, since the external voltage applied on VDDIO is kept, all of the
I/O configurations (i.e., WKUP pin configuration) are maintained in Backup mode. When not using backup batteries,
VDDIORDY is set so the user does not need to program it.
Figure 23-3. No Separate Backup Supply Powering Scheme
VDDUTMII
USB
Transceivers
VDDIO
Main Supply
ADC, DAC
Analog Comp.
VDDIN
VDDOUT
Voltage
Regulator
VDDCORE
VDDPLL
VDDUTMIC
Note: Restrictions
with main supply < 2.0 V, USB and ADC/DAC and analog comparator are not usable.
With main supply > 2.0V and < 3V, USB is not usable.
With main supply < 2.7V, MediaLB is not usable.
With main supply > 3V, all peripherals are usable.
The following figure illustrates an example of the powering scheme when using a backup battery. Since the PIO state
is preserved when in Backup mode, any free PIO line can be used to switch off the external regulator by driving the
PIO line at low level (PIO is input, pull-up enabled after backup reset). System wakeup can be performed using a
wakeup pin (WKUPx). See the "Wakeup Sources" section for further details.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 153
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Figure 23-4. Battery Backup
VDDUTMII
Backup
Battery
USB
Transceivers
VDDIO
+
ADC, DAC
Analog Comp.
VDDIN
Main Supply
IN
OUT
LDO
Regulator
VDDOUT
Voltage
Regulator
VDDCORE
ON/OFF
VDDPLL
VDDUTMIC
External Wakeup Signal
WKUPx
PIOx (Output)
Note: The two diodes provide a “switchover circuit” between the backup battery
and the main supply when the system is put in Backup mode.
23.4.5
Supply Monitor
The SUPC embeds a supply monitor located in the VDDIO power supply and which monitors VDDIO power supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state if the main power
supply drops below a certain level.
Note: The supply monitor is disabled by default.
The threshold of the supply monitor is programmable in the SMTH field of the Supply Monitor Mode register
(SUPC_SMMR). Refer to the section “Electrical Characteristics”.
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow
clock periods, depending on the user selection. This is configured in the SUPC_SMMR.SMSMPL.
Enabling the supply monitor for such reduced times divides the typical supply monitor power consumption by factors
of 2, 16 and 128, respectively, if continuous monitoring of the VDDIO power supply is not required.
A supply monitor detection generates either a reset of the core power supply or a wakeup of the core power supply.
Generating a core reset when a supply monitor detection occurs is enabled by setting SUPC_SMMR.SMRSTEN.
Waking up the core power supply when a supply monitor detection occurs can be enabled by setting the SMEN bit in
the Wakeup Mode register (SUPC_WUMR).
The SUPC provides two status bits in the SUPC_SR for the supply monitor that determine whether the last wakeup
was due to the supply monitor:
•
•
SUPC_SR.SMOS provides real-time information, updated at each measurement cycle or updated at each slow
clock cycle, if the measurement is continuous.
SUPC_SR.SMS provides saved information and shows a supply monitor detection has occurred since the last
read of SUPC_SR.
The SMS flag generates an interrupt if SUPC_SMMR.SMIEN is set.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 154
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Figure 23-5. Supply Monitor Status Bit and Associated Interrupt
Continuous Sampling (SMSMPL = 1)
Supply Monitor ON
Periodic Sampling
3.3 V
Threshold
0V
Read SUPC_SR
SMS and SUPC Interrupt
Related Links
57. Electrical Characteristics for SAM V70/V71
58. Electrical Characteristics for SAM E70/S70
23.4.6
Backup Power Supply Reset
23.4.6.1 Raising the Backup Power Supply
When the backup voltage VDDIO rises, the slow RC oscillator is powered up and the zero-power power-on reset cell
maintains its output low as long as VDDIO has not reached its target voltage. During this period, the SUPC is reset.
When the VDDIO voltage becomes valid and the zero-power power-on reset signal is released, a counter is started
for five slow clock cycles. This is the time required for the slow RC oscillator to stabilize.
After this time, the voltage regulator is enabled. The core power supply rises and the brownout detector provides the
bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset signal
to the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock
cycle.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 155
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Figure 23-6. Raising the VDDIO Power Supply
TON Voltage
7 x Slow Clock Cycles
(5 for startup slow RC + 2 for synchro.) Regulator
3 x Slow Clock 2 x Slow Clock
Cycles
Cycles
6.5 x Slow Clock
Cycles
Zero-Power POR
Backup Power Supply
Zero-Power Power-On
Reset Cell output
22 - 42 kHz Slow RC
Oscillator output
vr_on
Core Power Supply
Fast RC
Oscillator output
bodcore_in
vddcore_nreset
RSTC.ERSTL
default = 2
NRST
(no ext. drive assumed)
periph_nreset
proc_nreset
Note: After “proc_nreset” rising, the core starts fetching instructions from Flash.
23.4.7
Core Reset
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described in the "Backup
Power Supply Reset" section. The vddcore_nreset signal is normally asserted before shutting down the core power
supply and released as soon as the core power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
•
•
a supply monitor detection
a brownout detection
23.4.7.1 Supply Monitor Reset
The supply monitor is capable of generating a reset of the system. This is enabled by setting
SUPC_SMMR.SMRSTEN.
If SUPC_SMMR.SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately
activated for a minimum of one slow clock cycle.
23.4.7.2 Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC. This signal indicates that the voltage regulation
is operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is
enabled, the SUPC asserts vddcore_nreset if SUPC_MR.BODRSTEN is written to ‘1’.
If SUPC_MR.BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the
vddcore_nreset signal is asserted for a minimum of one slow clock cycle and then released if bodcore_in has been
reactivated. SUPC_SR.BODRSTS indicates the source of the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 156
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.4.8
Controlling the SRAM Power Supply
The SUPC can be used to switch on or off the power supply of the backup SRAM by opening or closing the SRAM
power switch. This power switch is controlled by SUPC_MR.BKUPRETON. However, the battery backup SRAM is
automatically switched on when the core power supply is enabled, as the processor requires the SRAM as data
memory space.
•
•
23.4.9
If SUPC_MR.BKUPRETON is written to ‘1’, there is no immediate effect, but the SRAM will be left powered
when the SUPC enters Backup mode, thus retaining its content.
If SUPC_MR.BKUPRETON is written to ‘0’, there is no immediate effect, but the SRAM will be switched off when
the SUPC enters Backup mode. The SRAM is automatically switched on when Backup mode is exited.
Wakeup Sources
The wakeup events allow the device to exit Backup mode. When a wakeup event is detected, the SUPC performs a
sequence that automatically reenables the core power supply.
Figure 23-7. Wakeup Sources
SMEN
sm_out
RTCEN
rtc_alarm
RTTEN
rtt_alarm
Low-power
Tamper Detection
Logic
LPDBC
WKUPT1
RTCOUT0
Debouncer
WKUPT0
LPDBC
LPDBCEN0
RTCOUT0
Falling/Rising
Edge Detect
WKUPT0
WKUP0
LPDBCS1
LPDBCEN1
Falling/Rising
Edge Detect
WKUPEN0
Debouncer
WKUPIS0
WKUPDBC
Falling/Rising
Edge Detect
WKUPT1
LPDBCS0
Core
Supply
Restart
SLCK
WKUPEN1
WKUPS
WKUPIS1
Debouncer
WKUP1
Falling/Rising
Edge Detect
LPDBCS1
LPDBCS0
WKUPT13
WKUP13
WKUPEN13
GPBR Clear
LPDBCCLR
WKUPIS13
Falling/Rising
Edge Detect
23.4.9.1 Wakeup Inputs
The wakeup inputs, WKUPx, can be programmed to perform a wakeup of the core power supply. Each input can
be enabled by writing a ‘1’ to the corresponding bit, WKUPENx, in the Wakeup Inputs register (SUPC_WUIR). The
wakeup level can be selected with the corresponding polarity bit, WKUPTx, also located in SUPC_WUIR.
The resulting signals are wired-ORed to trigger a debounce counter, which is programmed with
SUPC_WUMR.WKUPDBC. This field selects a debouncing period of 3, 32, 512, 4,096 or 32,768 slow clock cycles.
The duration of these periods corresponds, respectively, to about 100 μs, about 1 ms, about 16 ms, about 128 ms
and about 1 second (for a typical slow clock frequency of 32 kHz). Programming SUPC_WUMR.WKUPDBC to 0
selects an immediate wakeup, i.e., an enabled WKUP pin must be active according to its polarity during a minimum
of one slow clock period to wake up the core power supply.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 157
SAM E70/S70/V70/V71
Supply Controller (SUPC)
If an enabled WKUP pin is asserted for a duration longer than the debouncing period, a wakeup of the core power
supply is started and the signals, WKUP0 to WKUPx as shown in “Wakeup Sources”, are latched in SUPC_SR.
This allows the user to identify the source of the wakeup. However, if a new wakeup condition occurs, the primary
information is lost. No new wakeup can be detected since the primary wakeup condition has disappeared.
Before instructing the system to enter Backup mode, if the field SUPC_WUMR.WKUPDBC > 0, it must be checked
that none of the WKUPx pins that are enabled for a wakeup (exit from Backup mode) holds an active polarity. This is
checked by reading the pin status in the PIO Controller. If SUPC_WUIR.WKUPENx=1 and the pin WKUPx holds an
active polarity, the system must not be instructed to enter Backup mode.
Figure 23-8. Entering and Exiting Backup Mode with a WKUP Pin
WKUPDBC > 0
WKUPTx=0
Edge detect +
debounce time
WKUPx
Edge detect +
debounce time
VROFF=1
VROFF=1
System
Active
BACKUP
Active
BACKUP
active runtime
Active
BACKUP
Check
WKUPx
status
active runtime
Check
WKUPx
status
23.4.9.2 Low-power Tamper Detection and Anti-Tampering
Low-power debouncer inputs (WKUP0, WKUP1) can be used for tamper detection. If the tamper sensor is biased
through a resistor and constantly driven by the power supply, this leads to power consumption as long as the tamper
detection switch is in its active state. To prevent power consumption when the switch is in active state, the tamper
sensor circuitry must be intermittently powered, and thus a specific waveform must be applied to the sensor circuitry.
The waveform is generated using RTCOUTx in all modes including Backup mode. Refer to the section “Real-Time
Clock (RTC)” for waveform generation.
Separate debouncers are embedded, one for WKUP0 input, one for WKUP1 input.
The WKUP0 and/or WKUP1 inputs perform a system wakeup upon tamper detection. This is enabled by setting
SUPC_WUMR.LPDBCEN0/1.
WKUP0 and/or WKUP1 inputs can also be used when VDDCORE is powered to detect a tamper.
When SUPC_WUMR.LPDBCENx is written to ‘1’, WKUPx pins must not be configured to act as a debouncing source
for the WKUPDBC counter (WKUPENx must be cleared in SUPC_WUIR).
Low-power tamper detection or debounce requires RTC output (RTCOUTx) to be configured to generate a duty cycle
programmable pulse (i.e., OUT0 = 0x7 in RTC_MR) in order to create the sampling points of both debouncers. The
sampling point is the falling edge of the RTCOUTx waveform.
The following figure shows an example of an application where two tamper switches are used. RTCOUTx powers the
external pull-up used by the tamper sensor circuitry.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 158
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Figure 23-9. Low-power Debouncer (Push-to-Make Switch, Pull-up Resistors)
MCU
RTCOUTx
Pull-up
Resistor
WKUP0
Pull-up
Resistor
GND
WKUP1
GND
GND
Figure 23-10. Low-power Debouncer (Push-to-Break Switch, Pull-down Resistors)
MCU
RTCOUTx
WKUP0
WKUP1
Pull-down
Resistors
GND
GND
GND
The debouncing period duration is configurable. The period is set for all debouncers (i.e., the duration cannot be
adjusted for each debouncer). The number of successive identical samples to wake up the system can be configured
from 2 up to 8 in SUPC_WUMR.LPDBC. The period of time between two samples can be configured by programming
RTC_MR.TPERIOD. Power parameters can be adjusted by modifying the period of time in RTC_MR.THIGH.
The wakeup polarity of the inputs can be independently configured by writing SUPC_WUMR.WKUPT0 and/ or
SUPC_WUMR.WKUPT1.
In order to determine which wakeup/tamper pin triggers the system wakeup, a status flag is associated for each
low-power debouncer. These flags are read in SUPC_SR.
A debounce event (tamper detection) can perform an immediate clear (0 delay) on the first half the general-purpose
backup registers (GPBR). SUPC_WUMR.LPDBCCLR bit must be set.
Note that it is not mandatory to use the RTCOUTx pin when using the WKUP0/WKUP1 pins as tampering inputs
in any mode. Using the RTCOUTx pin provides a “sampling mode” to further reduce the power consumption
of the tamper detection circuitry. If RTCOUTx is not used, the RTC must be configured to create an internal
sampling point for the debouncer logic. The period of time between two samples can be configured by programming
RTC_MR.TPERIOD.
The following figure illustrates the use of WKUPx without the RTCOUTx pin.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 159
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Figure 23-11. Using WKUP Pins Without RTCOUTx Pins
VDDIO
MCU
Pull-up
Resistor
WKUP0
Pull-up
Resistor
GND
WKUP1
GND
GND
Related Links
27. Real-time Clock (RTC)
23.4.9.3 Clock Alarms
The RTC and the RTT alarms can generate a wakeup of the core power supply. This can be enabled by setting,
respectively, SUPC_WUMR.RTCEN and SUPC_WUMR.RTTEN.
The Supply Controller does not provide any status as the information is available in the user interface of either the
Real-Time Timer or the Real-Time Clock.
23.4.9.4 Supply Monitor Detection
The supply monitor can generate a wakeup of the core power supply. See "Supply Monitor".
23.4.10 Register Write Protection
To prevent any single software error from corrupting SYSC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the ”System Controller Write Protection Mode Register” (SYSC_WPMR).
The following registers can be write-protected:
•
•
•
•
•
•
•
•
•
•
•
•
•
RSTC Mode Register(1)
RTT Mode Register(2)
RTT Alarm Register(2)
RTC Control Register(3)
RTC Mode Register(3)
RTC Time Alarm Register(3)
RTC Calendar Alarm Register(3)
General Purpose Backup Registers(4)
Supply Controller Control Register
Supply Controller Supply Monitor Mode Register
Supply Controller Mode Register
Supply Controller Wakeup Mode Register
Supply Controller Wakeup Inputs Register
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 160
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Notes:
1. See the section "Reset Controller (RSTC)".
2. See the section "Real Time Timer (RTT)".
3. See the section "Real Time Clock (RTC)".
4. See the section "General Purpose Backup Registers (GPBR)".
23.4.11 Register Bits in Backup Domain (VDDIO)
The following configuration registers, or certain bits of the registers, are physically located in the product backup
domain:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RSTC Mode Register (all bits)(1)
RTT Mode Register (all bits)(2)
RTT Alarm Register (all bits)(2)
RTC Control Register (all bits)(3)
RTC Mode Register (all bits)(3)
RTC Time Alarm Register (all bits)(3)
RTC Calendar Alarm Register (all bits)(3)
General Purpose Backup Registers (all bits)(4)
Supply Controller Control Register (see register description for details)
Supply Controller Supply Monitor Mode Register (all bits)
Supply Controller Mode Register (see register description for details)
Supply Controller Wakeup Mode Register (all bits)
Supply Controller Wakeup Inputs Register (all bits)
Supply Controller Status Register (all bits)
Notes:
1. See the section "Reset Controller (RSTC)".
2. See the section "Real Time Timer (RTT)".
3. See the section "Real Time Clock (RTC)".
4. See the section "General Purpose Backup Registers (GPBR)".
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 161
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5
Register Summary
Offset
Name
0x00
SUPC_CR
0x04
SUPC_SMMR
0x08
SUPC_MR
0x0C
SUPC_WUMR
0x10
SUPC_WUIR
0x14
0x18
...
0xD3
0xD4
SUPC_SR
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7
6
5
4
3
2
1
XTALSEL
VROFF
0
KEY[7:0]
SMIEN
ONREG
LPDBCCLR
SMTH[3:0]
SMSMPL[2:0]
SMRSTEN
BODDIS
BODRSTEN
OSCBYPASS
KEY[7:0]
LPDBCEN1 LPDBCEN0
RTCEN
WKUPDBC[2:0]
BKUPRETON
RTTEN
SMEN
LPDBC[2:0]
WKUPEN[7:0]
WKUPEN[13:8]
WKUPT[7:0]
OSCSEL
SMOS
LPDBCS1
SMS
LPDBCS0
SMRSTS
WKUPT[13:8]
BODRSTS
SMWS
WKUPS
WKUPIS[7:0]
WKUPIS[13:8]
Reserved
SYSC_WPMR
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
WPEN
WPKEY[7:0]
WPKEY[15:8]
WPKEY[23:16]
Complete Data Sheet
DS60001527G-page 162
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5.1
Supply Controller Control Register
Name:
Offset:
Property:
Bit
31
SUPC_CR
0x00
Write-only
30
29
28
27
26
25
24
KEY[7:0]
Access
Reset
W
W
W
W
W
W
W
W
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
XTALSEL
W
2
VROFF
W
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:24 – KEY[7:0] Password
Value
Name
0xA5
PASSWD
Description
Writing any other value in this field aborts the write operation.
Bit 3 – XTALSEL Crystal Oscillator Select
Note: This bit is located in the VDDIO domain.
Value
Description
0
(NO_EFFECT): No effect.
1
(CRYSTAL_SEL): If KEY is correct, XTALSEL switches the slow clock on the 32.768 kHz crystal
oscillator output.
Bit 2 – VROFF Voltage Regulator Off
Note: This bit is located in the VDDIO domain.
Value
Description
0
(NO_EFFECT): No effect.
1
(STOP_VREG): If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 163
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5.2
Supply Controller Supply Monitor Mode Register
Name:
Offset:
Reset:
Property:
SUPC_SMMR
0x04
0x00000000
Read/Write
This register is located in the VDDIO domain.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
SMIEN
R/W
0
12
SMRSTEN
R/W
0
11
10
9
SMSMPL[2:0]
R/W
0
8
R/W
0
5
4
3
1
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
R/W
0
2
SMTH[3:0]
Access
Reset
R/W
0
R/W
0
Bit 13 – SMIEN Supply Monitor Interrupt Enable
Value
Description
0
(NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs.
1
(ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs.
Bit 12 – SMRSTEN Supply Monitor Reset Enable
Value
Description
0
(NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a supply monitor detection
occurs.
1
(ENABLE): The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
Bits 10:8 – SMSMPL[2:0] Supply Monitor Sampling Period
Value
Name
Description
0x0
SMD
Supply Monitor disabled
0x1
CSM
Continuous Supply Monitor
0x2
32SLCK
Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3
256SLCK
Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4
2048SLCK
Supply Monitor enabled one SLCK period every 2,048 SLCK periods
Bits 3:0 – SMTH[3:0] Supply Monitor Threshold
Selects the threshold voltage of the supply monitor. Refer to the section “Electrical Characteristics” for voltage values.
Related Links
57. Electrical Characteristics for SAM V70/V71
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 164
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5.3
Supply Controller Mode Register
Name:
Offset:
Reset:
Property:
Bit
31
SUPC_MR
0x08
0x00005A00
Read/Write
30
29
28
27
26
25
24
KEY[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
OSCBYPASS
R/W
0
19
18
17
BKUPRETON
R/W
0
16
15
14
ONREG
R/W
1
13
BODDIS
R/W
0
12
BODRSTEN
R/W
1
11
10
9
8
7
6
5
4
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 31:24 – KEY[7:0] Password Key
Value
Name
Description
0xA5
PASSWD
Writing any other value in this field aborts the write operation.
Bit 20 – OSCBYPASS Oscillator Bypass
Note: This bit is located in the VDDIO domain.
Value
0
1
Description
(NO_EFFECT): No effect. Clock selection depends on the value of SUPC_CR.XTALSEL.
(BYPASS): The 32.768 kHz crystal oscillator is bypassed if SUPC_CR.XTALSEL is set. OSCBYPASS
must be set prior to setting XTALSEL.
Bit 17 – BKUPRETON SRAM On In Backup Mode
Value
Description
0
SRAM (Backup) switched off in Backup mode.
1
SRAM (Backup) switched on in Backup mode.
Note: This bit is located in the VDDIO domain.
Bit 14 – ONREG Voltage Regulator Enable
Note: This bit is located in the VDDIO domain.
Value
0
1
Description
(ONREG_UNUSED): Internal voltage regulator is not used (external power supply is used).
(ONREG_USED): Internal voltage regulator is used.
Bit 13 – BODDIS Brownout Detector Disable
Note: This bit is located in the VDDIO domain.
Value
0
Description
(ENABLE): The core brownout detector is enabled.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 165
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Value
1
Description
(DISABLE): The core brownout detector is disabled.
Bit 12 – BODRSTEN Brownout Detector Reset Enable
Note: This bit is located in the VDDIO domain.
Value
0
1
Description
(NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a brownout detection
occurs.
(ENABLE): The core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 166
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5.4
Supply Controller Wakeup Mode Register
Name:
Offset:
Reset:
Property:
SUPC_WUMR
0x0C
0x00000000
Read/Write
This register is located in the VDDIO domain.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
16
R/W
0
17
LPDBC[2:0]
R/W
0
R/W
0
11
10
9
8
3
RTCEN
R/W
0
2
RTTEN
R/W
0
1
SMEN
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
7
LPDBCCLR
R/W
0
14
R/W
0
13
WKUPDBC[2:0]
R/W
0
6
LPDBCEN1
R/W
0
5
LPDBCEN0
R/W
0
12
R/W
0
4
Bits 18:16 – LPDBC[2:0] Low-power Debouncer Period
Value
Name
Description
0
DISABLE
Disables the low-power debouncers.
1
2_RTCOUT
WKUP0/1 in active state for at least 2 RTCOUTx clock periods
2
3_RTCOUT
WKUP0/1 in active state for at least 3 RTCOUTx clock periods
3
4_RTCOUT
WKUP0/1 in active state for at least 4 RTCOUTx clock periods
4
5_RTCOUT
WKUP0/1 in active state for at least 5 RTCOUTx clock periods
5
6_RTCOUT
WKUP0/1 in active state for at least 6 RTCOUTx clock periods
6
7_RTCOUT
WKUP0/1 in active state for at least 7 RTCOUTx clock periods
7
8_RTCOUT
WKUP0/1 in active state for at least 8 RTCOUTx clock periods
Bits 14:12 – WKUPDBC[2:0] Wakeup Inputs Debouncer Period
Value
Name
Description
0
IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
1
3_SLCK
WKUPx shall be in its active state for at least 3 SLCK periods
2
32_SLCK
WKUPx shall be in its active state for at least 32 SLCK periods
3
512_SLCK
WKUPx shall be in its active state for at least 512 SLCK periods
4
4096_SLCK
WKUPx shall be in its active state for at least 4,096 SLCK periods
5
32768_SLCK
WKUPx shall be in its active state for at least 32,768 SLCK periods
Bit 7 – LPDBCCLR Low-power Debouncer Clear
Value
Description
0
(NOT_ENABLE): A low-power debounce event does not create an immediate clear on the first half of
GPBR registers.
1
(ENABLE): A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the
first half of GPBR registers.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 167
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Bit 6 – LPDBCEN1 Low-power Debouncer Enable WKUP1
Value
Description
0
(NOT_ENABLE): The WKUP1 input pin is not connected to the low-power debouncer.
1
(ENABLE): The WKUP1 input pin is connected to the low-power debouncer and forces a system
wakeup.
Bit 5 – LPDBCEN0 Low-power Debouncer Enable WKUP0
Value
Description
0
(NOT_ENABLE): The WKUP0 input pin is not connected to the low-power debouncer.
1
(ENABLE): The WKUP0 input pin is connected to the low-power debouncer and forces a system
wakeup.
Bit 3 – RTCEN Real-time Clock Wakeup Enable
Value
Description
0
(NOT_ENABLE): The RTC alarm signal has no wakeup effect.
1
(ENABLE): The RTC alarm signal forces the wakeup of the core power supply.
Bit 2 – RTTEN Real-time Timer Wakeup Enable
Value
Description
0
(NOT_ENABLE): The RTT alarm signal has no wakeup effect.
1
(ENABLE): The RTT alarm signal forces the wakeup of the core power supply.
Bit 1 – SMEN Supply Monitor Wakeup Enable
Value
Description
0
(NOT_ENABLE): The supply monitor detection has no wakeup effect.
1
(ENABLE): The supply monitor detection forces the wakeup of the core power supply.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 168
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5.5
Supply Controller Wakeup Inputs Register
Name:
Offset:
Reset:
Property:
SUPC_WUIR
0x10
0x00000000
Read/Write
This register is located in the VDDIO domain. This register can only be written if the WPEN bit is cleared in the
System Controller Write Protection Mode Register (SYSC_WPMR).
Bit
31
30
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
28
R/W
0
R/W
0
20
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
R/W
0
R/W
0
4
Access
Reset
Bit
29
7
6
5
R/W
0
R/W
0
R/W
0
27
26
WKUPT[13:8]
R/W
R/W
0
0
19
WKUPT[7:0]
R/W
R/W
0
0
25
24
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
–
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
–
11
10
WKUPEN[13:8]
R/W
R/W
0
0
3
WKUPEN[7:0]
R/W
R/W
0
0
Bits 29:16 – WKUPT[13:0] Wakeup Input Type ('x' = 0-13)
Value
Description
0
(LOW): A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding
wakeup input forces the wakeup of the core power supply.
1
(HIGH): A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding
wakeup input forces the wakeup of the core power supply.
Bits 13:0 – WKUPEN[13:0] Wakeup Input Enablex ('x' = 0-13)
Value
Description
0
(DISABLE): The corresponding wakeup input has no wakeup effect.
1
(ENABLE): The corresponding wakeup input is enabled for a wakeup of the core power supply.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 169
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5.6
Supply Controller Status Register
Name:
Offset:
Reset:
Property:
SUPC_SR
0x14
0x00000000
Read-only
Note: Because of the asynchronism between the Slow Clock (SLCK) and the System Clock (MCK), the status
register flag reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR.
This register is located in the VDDIO domain.
Bit
31
30
Access
Reset
Bit
23
22
29
28
R
0
R
0
21
20
27
26
WKUPIS[13:8]
R
R
0
0
25
24
R
0
R
0
19
18
17
16
WKUPIS[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
15
14
LPDBCS1
R
0
13
LPDBCS0
R
0
12
11
10
9
8
7
OSCSEL
R
0
6
SMOS
R
0
5
SMS
R
0
4
SMRSTS
R
0
3
BODRSTS
R
0
2
SMWS
R
0
1
WKUPS
R
0
0
Access
Reset
Bit
Access
Reset
Bits 29:16 – WKUPIS[13:0] WKUPx ('x' = 0-13) Input Status (cleared on read)
Value
Description
0
(DIS): The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered
a wakeup event.
1
(EN): The corresponding wakeup input was active at the time the debouncer triggered a wakeup event
since the last read of SUPC_SR.
Bit 14 – LPDBCS1 Low-power Debouncer Wakeup Status on WKUP1 (cleared on read)
Value
Description
0
(NO): No wakeup due to the assertion of the WKUP1 pin has occurred since the last read of
SUPC_SR.
1
(PRESENT): At least one wakeup due to the assertion of the WKUP1 pin has occurred since the last
read of SUPC_SR.
Bit 13 – LPDBCS0 Low-power Debouncer Wakeup Status on WKUP0 (cleared on read)
Value
Description
0
(NO): No wakeup due to the assertion of the WKUP0 pin has occurred since the last read of
SUPC_SR.
1
(PRESENT): At least one wakeup due to the assertion of the WKUP0 pin has occurred since the last
read of SUPC_SR.
Bit 7 – OSCSEL 32-kHz Oscillator Selection Status
Value
Description
0
(RC): The slow clock, SLCK, is generated by the slow RC oscillator.
1
(CRYST): The slow clock, SLCK, is generated by the 32.768 kHz crystal oscillator.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 170
SAM E70/S70/V70/V71
Supply Controller (SUPC)
Bit 6 – SMOS Supply Monitor Output Status
Value
Description
0
(HIGH): The supply monitor detected VDDIO higher than its threshold at its last measurement.
1
(LOW): The supply monitor detected VDDIO lower than its threshold at its last measurement.
Bit 5 – SMS Supply Monitor Status (cleared on read)
Value
Description
0
(NO): No supply monitor detection since the last read of SUPC_SR.
1
(PRESENT): At least one supply monitor detection since the last read of SUPC_SR.
Bit 4 – SMRSTS Supply Monitor Reset Status (cleared on read)
Value
Description
0
(NO): No supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1
(PRESENT): At least one supply monitor detection has generated a core reset since the last read of
the SUPC_SR.
Bit 3 – BODRSTS Brownout Detector Reset Status (cleared on read)
When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout
detection cell. The rising edge event occurs only when there is a voltage transition below the threshold.
Value
Description
0
(NO): No core brownout rising edge event has been detected since the last read of the SUPC_SR.
1
(PRESENT): At least one brownout output rising edge event has been detected since the last read of
the SUPC_SR.
Bit 2 – SMWS Supply Monitor Detection Wakeup Status (cleared on read)
Value
Description
0
(NO): No wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR.
1
(PRESENT): At least one wakeup due to a supply monitor detection has occurred since the last read of
SUPC_SR.
Bit 1 – WKUPS WKUP Wakeup Status (cleared on read)
Value
Description
0
(NO): No wakeup due to the assertion of the WKUP pins has occurred since the last read of
SUPC_SR.
1
(PRESENT): At least one wakeup due to the assertion of the WKUP pins has occurred since the last
read of SUPC_SR.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 171
SAM E70/S70/V70/V71
Supply Controller (SUPC)
23.5.7
System Controller Write Protection Mode Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
SYSC_WPMR
0xD4
0x00000000
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
28
27
WPKEY[23:16]
R/W
R/W
0
0
20
19
WPKEY[15:8]
R/W
R/W
0
0
12
11
WPKEY[7:0]
R/W
R/W
0
0
4
3
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
WPEN
R?W
0
Access
Reset
Bits 31:8 – WPKEY[23:0] Write Protection Key.
Value
Name
Description
0x525443 PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.
Always reads as 0.
Bit 0 – WPEN Write Protection Enable
See "Register Write Protection" for the list of registers that can be write-protected.
Value
Description
0
Disables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
1
Enables the write protection if WPKEY corresponds to 0x525443 (“RTC” in ASCII).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 172
SAM E70/S70/V70/V71
Watchdog Timer (WDT)
24.
24.1
Watchdog Timer (WDT)
Description
The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped in a deadlock. It
features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock around 32 kHz). It can
generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in Debug
mode or Sleep mode (Idle mode).
24.2
Embedded Characteristics
•
•
•
•
24.3
12-bit Key-protected Programmable Counter
Watchdog Clock is Independent from Processor Clock
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped while the Processor is in Debug State or in Idle Mode
Block Diagram
Figure 24-1. Watchdog Timer Block Diagram
write WDT_MR
WDT_MR
WDV
WDT_CR
WDRSTT
reload
1
0
12-bit Down
Counter
WDT_MR
WDD
reload
Current
Value
1/128
96 and the IP Stretch Enable bit in the Network Configuration Register (GMAC_NCFGR.IPGSEN) is
written to '1', RESULT is used for the transmit inter-packet-gap.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 622
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.27 GMAC Stacked VLAN Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
GMAC_SVLAN
0x0C0
0x00000000
-
31
ESVLAN
0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
12
11
VLAN_TYPE[15:8]
R/W
R/W
0
0
4
3
VLAN_TYPE[7:0]
R/W
R/W
0
0
Bit 31 – ESVLAN Enable Stacked VLAN Processing Mode
0: Disable the stacked VLAN processing mode
1: Enable the stacked VLAN processing mode
Value
Description
0
Stacked VLAN Processing disabled
1
Stacked VLAN Processing enabled
Bits 15:0 – VLAN_TYPE[15:0] User Defined VLAN_TYPE Field
When Stacked VLAN is enabled (ESVLAN=1), the first VLAN tag in a received frame will only be accepted if the
VLAN type field is equal to this user defined VLAN_TYPE, OR equal to the standard VLAN type (0x8100).
Note: The second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals
0x8100.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 623
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.28 GMAC Transmit PFC Pause Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TPFCP
0x0C4
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
PQ[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PEV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – PQ[7:0] Pause Quantum
When the Remove FCS bit in the GMAC Network Configuration register (GMAC_NCFGR.RFCS) is written to '1', and
one or more bits in this bit field are written to '0', the associated PFC pause frame's pause quantum field value is
taken from the Transmit Pause Quantum register (GMAC_TPQ).
For each entry equal to '1' in this bit field, the pause quantum associated with that entry will be zero.
Bits 7:0 – PEV[7:0] Priority Enable Vector
When the Remove FCS bit in the GMAC Network Configuration register (GMAC_NCFGR.RFCS) is written to '1', the
priority enable vector of the PFC priority-based pause frame is set to the value stored in this bit field.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 624
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.29 GMAC Specific Address 1 Mask Bottom
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
GMAC_SAMB1
0x0C8
0x00000000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
ADDR[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
ADDR[23:16]
R/W
R/W
0
0
12
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – ADDR[31:0] Specific Address 1 Mask
Setting a bit to '1' masks the corresponding bit in the Specific Address 1 Bottom register (GMAC_SAB1).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 625
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.30 GMAC Specific Address Mask 1 Top
Name:
Offset:
Reset:
Property:
Bit
GMAC_SAMT1
0x0CC
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADDR[15:0] Specific Address 1 Mask
Setting a bit to '1' masks the corresponding bit in the Specific Address 1 register GMAC_SAT1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 626
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.31 GMAC 1588 Timer Nanosecond Comparison Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_NSC
0x0DC
0x00000000
-
31
30
29
28
23
22
21
20
R/W
0
R/W
0
27
26
25
24
17
16
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
19
18
NANOSEC[21:16]
R/W
R/W
0
0
12
11
NANOSEC[15:8]
R/W
R/W
0
0
4
3
NANOSEC[7:0]
R/W
R/W
0
0
Bits 21:0 – NANOSEC[21:0] 1588 Timer Nanosecond Comparison Value
Value is compared to the bits [45:24] of the TSU timer count value (upper 22 bits of nanosecond value).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 627
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.32 GMAC 1588 Timer Second Comparison Low Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_SCL
0x0E0
0x00000000
-
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
SEC[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
SEC[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
SEC[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
SEC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – SEC[31:0] 1588 Timer Second Comparison Value
Value is compared to seconds value bits [31:0] of the TSU timer count value.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 628
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.33 GMAC 1588 Timer Second Comparison High Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_SCH
0x0E4
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
SEC[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
SEC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – SEC[15:0] 1588 Timer Second Comparison Value
Value is compared to the top 16 bits (most significant 16 bits [47:32] of seconds value) of the TSU timer count value.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 629
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.34 GMAC PTP Event Frame Transmitted Seconds High Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_EFTSH
0x0E8
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – RUD[15:0] Register Update
The register is updated with the value that the IEEE 1588 timer seconds register held when the SFD of a PTP
transmit primary event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 630
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.35 GMAC PTP Event Frame Received Seconds High Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_EFRSH
0x0EC
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – RUD[15:0] Register Update
The register is updated with the value that the IEEE 1588 timer seconds register held when the SFD of a PTP
transmit primary event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 631
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.36 GMAC PTP Peer Event Frame Transmitted Seconds High Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PEFTSH
0x0F0
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – RUD[15:0] Register Update
The register is updated with the value that the IEEE 1588 timer seconds register held when the SFD of a PTP
transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 632
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.37 GMAC PTP Peer Event Frame Received Seconds High Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PEFRSH
0x0F4
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – RUD[15:0] Register Update
The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer
event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 633
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.38 GMAC Octets Transmitted Low Register
Name:
Offset:
Reset:
Property:
GMAC_OTLO
0x100
0x00000000
-
When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32]
to ensure reliable operation.
Bit
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
TXO[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
TXO[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
TXO[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
TXO[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – TXO[31:0] Transmitted Octets
Transmitted octets in valid frames of any type without errors, bits [31:0]. This counter is 48-bits, and is read through
two registers. This count does not include octets from automatically generated pause frames.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 634
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.39 GMAC Octets Transmitted High Register
Name:
Offset:
Reset:
Property:
GMAC_OTHI
0x104
0x00000000
-
When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32]
to ensure reliable operation.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
TXO[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
TXO[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – TXO[15:0] Transmitted Octets
Transmitted octets in valid frames of any type without errors, bits [47:32]. This counter is 48-bits, and is read through
two registers. This count does not include octets from automatically generated pause frames.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 635
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.40 GMAC Frames Transmitted
Name:
Offset:
Reset:
Property:
Bit
GMAC_FT
0x108
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
FTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
FTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
FTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
FTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – FTX[31:0] Frames Transmitted without Error
Frames transmitted without error. This register counts the number of frames successfully transmitted, i.e., no
underrun and not too many retries. Excludes pause frames.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 636
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.41 GMAC Broadcast Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_BCFT
0x10C
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
BFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
BFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
BFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
BFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – BFTX[31:0] Broadcast Frames Transmitted without Error
This register counts the number of broadcast frames successfully transmitted without error, i.e., no underrun and not
too many retries. Excludes pause frames.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 637
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.42 GMAC Multicast Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_MFT
0x110
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
MFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
MFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
MFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
MFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – MFTX[31:0] Multicast Frames Transmitted without Error
This register counts the number of multicast frames successfully transmitted without error, i.e., no underrun and not
too many retries. Excludes pause frames.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 638
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.43 GMAC Pause Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PFT
0x114
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
PFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
PFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – PFTX[15:0] Pause Frames Transmitted Register
This register counts the number of pause frames transmitted. Only pause frames triggered by the register interface or
through the external pause pins are counted as pause frames. Pause frames received through the FIFO interface are
counted in the frames transmitted counter.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 639
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.44 GMAC 64 Byte Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
31
GMAC_BFT64
0x118
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFTX[31:0] 64 Byte Frames Transmitted without Error
This register counts the number of 64 byte frames successfully transmitted without error, i.e., no underrun and not too
many retries. Excludes pause frames.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 640
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.45 GMAC 65 to 127 Byte Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFT127
0x11C
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFTX[31:0] 65 to 127 Byte Frames Transmitted without Error
This register counts the number of 65 to 127 byte frames successfully transmitted without error, i.e., no underrun and
not too many retries. Excludes pause frames.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 641
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.46 GMAC 128 to 255 Byte Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFT255
0x120
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFTX[31:0] 128 to 255 Byte Frames Transmitted without Error
This register counts the number of 128 to 255 byte frames successfully transmitted without error, i.e., no underrun
and not too many retries.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 642
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.47 GMAC 256 to 511 Byte Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFT511
0x124
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFTX[31:0] 256 to 511 Byte Frames Transmitted without Error
This register counts the number of 256 to 511 byte frames successfully transmitted without error, i.e., no underrun
and not too many retries.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 643
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.48 GMAC 512 to 1023 Byte Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFT1023
0x128
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFTX[31:0] 512 to 1023 Byte Frames Transmitted without Error
This register counts the number of 512 to 1023 byte frames successfully transmitted without error, i.e., no underrun
and not too many retries.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 644
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.49 GMAC 1024 to 1518 Byte Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFT1518
0x12C
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFTX[31:0] 1024 to 1518 Byte Frames Transmitted without Error
This register counts the number of 1024 to 1518 byte frames successfully transmitted without error, i.e., no underrun
and not too many retries.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 645
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.50 GMAC Greater Than 1518 Byte Frames Transmitted Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_GTBFT1518
0x130
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFTX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFTX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFTX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFTX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFTX[31:0] Greater than 1518 Byte Frames Transmitted without Error
This register counts the number of 1518 or above byte frames successfully transmitted without error i.e., no underrun
and not too many retries.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 646
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.51 GMAC Transmit Underruns Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TUR
0x134
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
TXUNR[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
TXUNR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – TXUNR[9:0] Transmit Underruns
This register counts the number of frames not transmitted due to a transmit underrun. If this register is incremented
then no other statistics register is incremented.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 647
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.52 GMAC Single Collision Frames Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_SCF
0x138
0x00000000
-
31
30
29
28
27
26
25
23
22
21
20
19
18
17
24
Access
Reset
Bit
16
SCOL[17:16]
Access
Reset
Bit
15
14
13
12
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
SCOL[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
SCOL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 17:0 – SCOL[17:0] Single Collision
This register counts the number of frames experiencing a single collision before being successfully transmitted i.e.,
no underrun.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 648
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.53 GMAC Multiple Collision Frames Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_MCF
0x13C
0x00000000
-
31
30
29
28
27
26
25
23
22
21
20
19
18
17
24
Access
Reset
Bit
16
MCOL[17:16]
Access
Reset
Bit
15
14
13
12
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
MCOL[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
MCOL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 17:0 – MCOL[17:0] Multiple Collision
This register counts the number of frames experiencing between two and fifteen collisions prior to being successfully
transmitted, i.e., no underrun and not too many retries.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 649
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.54 GMAC Excessive Collisions Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_EC
0x140
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
XCOL[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
XCOL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – XCOL[9:0] Excessive Collisions
This register counts the number of frames that failed to be transmitted because they experienced 16 collisions.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 650
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.55 GMAC Late Collisions Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_LC
0x144
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
LCOL[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
LCOL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – LCOL[9:0] Late Collisions
This register counts the number of late collisions occurring after the slot time (512 bits) has expired. In 10/100 mode,
late collisions are counted twice i.e., both as a collision and a late collision. In gigabit mode, a late collision causes
the transmission to be aborted, thus the single and multi collision registers are not updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 651
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.56 GMAC Deferred Transmission Frames Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_DTF
0x148
0x00000000
Read-only
31
30
29
28
27
26
25
23
22
21
20
19
18
17
24
Access
Reset
Bit
16
DEFT[17:16]
Access
Reset
Bit
15
14
13
12
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
DEFT[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
DEFT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 17:0 – DEFT[17:0] Deferred Transmission
This register counts the number of frames experiencing deferral due to carrier sense being active on their first
attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit
underrun.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 652
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.57 GMAC Carrier Sense Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_CSE
0x14C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
CSR[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
CSR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – CSR[9:0] Carrier Sense Error
This register counts the number of frames transmitted with carrier sense was not seen during transmission or
where carrier sense was deasserted after being asserted in a transmit frame without collision (no underrun). Only
incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of
the other statistics registers is unaffected by the detection of a carrier sense error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 653
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.58 GMAC Octets Received Low Register
Name:
Offset:
Reset:
Property:
GMAC_ORLO
0x150
0x00000000
-
When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32]
to ensure reliable operation.
Bit
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RXO[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
RXO[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RXO[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RXO[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RXO[31:0] Received Octets
Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This
counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is
only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 654
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.59 GMAC Octets Received High Register
Name:
Offset:
Reset:
Property:
GMAC_ORHI
0x154
0x00000000
-
When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to
ensure reliable operation.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
RXO[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RXO[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – RXO[15:0] Received Octets
Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This
counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is
only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 655
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.60 GMAC Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_FR
0x158
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
FRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
FRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
FRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
FRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – FRX[31:0] Frames Received without Error
This bit field counts the number of frames successfully received, excluding pause frames. It is only incremented if the
frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 656
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.61 GMAC Broadcast Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
31
GMAC_BCFR
0x15C
0x00000000
Read-only
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
BFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
BFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
BFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
BFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – BFRX[31:0] Broadcast Frames Received without Error
Broadcast frames received without error. This bit field counts the number of broadcast frames successfully received.
This excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 657
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.62 GMAC Multicast Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_MFR
0x160
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
MFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
MFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
MFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
MFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – MFRX[31:0] Multicast Frames Received without Error
This register counts the number of multicast frames successfully received without error, excluding pause frames, and
is only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 658
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.63 GMAC Pause Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PFR
0x164
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
PFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
PFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – PFRX[15:0] Pause Frames Received Register
This register counts the number of pause frames received without error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 659
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.64 GMAC 64 Byte Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_BFR64
0x168
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFRX[31:0] 64 Byte Frames Received without Error
This bit field counts the number of 64 byte frames successfully received without error. Excludes pause frames, and is
only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 660
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.65 GMAC 65 to 127 Byte Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFR127
0x16C
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFRX[31:0] 65 to 127 Byte Frames Received without Error
This bit field counts the number of 65 to 127 byte frames successfully received without error. Excludes pause frames,
and is only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 661
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.66 GMAC 128 to 255 Byte Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFR255
0x170
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFRX[31:0] 128 to 255 Byte Frames Received without Error
This bit field counts the number of 128 to 255 byte frames successfully received without error. Excludes pause
frames, and is only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 662
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.67 GMAC 256 to 511 Byte Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFR511
0x174
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFRX[31:0] 256 to 511 Byte Frames Received without Error
This bit fields counts the number of 256 to 511 byte frames successfully received without error. Excludes pause
frames, and is only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 663
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.68 GMAC 512 to 1023 Byte Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFR1023
0x178
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFRX[31:0] 512 to 1023 Byte Frames Received without Error
This bit field counts the number of 512 to 1023 byte frames successfully received without error. Excludes pause
frames, and is only incremented if the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 664
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.69 GMAC 1024 to 1518 Byte Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TBFR1518
0x17C
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFRX[31:0] 1024 to 1518 Byte Frames Received without Error
This bit field counts the number of 1024 to 1518 byte frames successfully received without error, i.e., no underrun and
not too many retries.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 665
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.70 GMAC 1519 to Maximum Byte Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TMXBFR
0x180
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
NFRX[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
NFRX[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
NFRX[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
NFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – NFRX[31:0] 1519 to Maximum Byte Frames Received without Error
This bit field counts the number of 1519 Byte or above frames successfully received without error. Maximum frame
size is determined by the Maximum Frame Size bit (MAXFS, 1536 Bytes) or Jumbo Frame Size bit (JFRAME, 10240
Bytes) in the Network Configuration Register (GMAC_NCFGR). Excludes pause frames, and is only incremented if
the frame is successfully filtered and copied to memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 666
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.71 GMAC Undersized Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_UFR
0x184
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
UFRX[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
UFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – UFRX[9:0] Undersize Frames Received
This bit field counts the number of frames received less than 64 bytes in length (10/100 mode or gigabit mode, full
duplex) that do not have either a CRC error or an alignment error.
In gigabit mode, half duplex, this bit field counts either frames not conforming to the minimum slot time of 512 bytes
or frames not conforming to the minimum frame size once bursting is active.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 667
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.72 GMAC Oversized Frames Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_OFR
0x188
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
OFRX[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
OFRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – OFRX[9:0] Oversized Frames Received
This pit field counts the number of frames received exceeding 1518 Bytes in length (1536 Bytes if
GMAC_NCFGR.MAXFS is written to '1', 10240 Bytes if GMAC_NCFGR.JFRAME=1) but do not have either a CRC
error, an alignment error, nor a receive symbol error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 668
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.73 GMAC Jabbers Received Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_JR
0x18C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
JRX[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
JRX[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – JRX[9:0] Jabbers Received
This bit field counts the number of frames received exceeding 1518 Bytes in length (1536 Bytes if
GMAC_NCFGR.MAXFS is written to '1', 10240 Bytes if GMAC_NCFGR.JFRAME=1) and have either a CRC error, an
alignment error or a receive symbol error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 669
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.74 GMAC Frame Check Sequence Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_FCSE
0x190
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
FCKR[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
FCKR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – FCKR[9:0] Frame Check Sequence Errors
The register counts frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes
in length (1536 Bytes if GMAC_NCFGR.MAXFS is written to '1', 10240 Bytes if GMAC_NCFGR.JFRAME=1). This
register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number
of bytes.
This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore
FCS mode (enabled by writing GMAC_NCFGR.IRXFCS=1).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 670
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.75 GMAC Length Field Frame Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_LFFE
0x194
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
LFER[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
LFER[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – LFER[9:0] Length Field Frame Errors
This bit field counts the number of frames received that have a measured length shorter than that extracted from the
length field (Bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the
frame is not of excessive length and checking is enabled by writing a '1' to the Length Field Error Frame Discard bit in
the Network Configuration Register (GMAC_NCFGR.LFERD).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 671
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.76 GMAC Receive Symbol Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_RSE
0x198
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
RXSE[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RXSE[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – RXSE[9:0] Receive Symbol Errors
This bit field counts the number of frames that had GRXER asserted during reception. For 10/100 mode symbol
errors are counted regardless of frame length checks. For gigabit mode the frame must satisfy slot time requirements
in order to count a symbol error. Additionally, in gigabit half duplex mode, carrier extension errors are also recorded.
Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 Bytes
(1536 Bytes if GMAC_NCFGR.MAXFS=1, 10240 Bytes if GMAC_NCFGR.JFRAME=1). If the frame is larger it will be
recorded as a jabber error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 672
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.77 GMAC Alignment Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_AE
0x19C
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
AER[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
AER[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – AER[9:0] Alignment Errors
This bit field counts the frames that are not an integral number of bytes long and have bad CRC when their
length is truncated to an integral number of Bytes and are between 64 and 1518 Bytes in length (1536 if
GMAC_NCFGR.MAXFS=1, 10240 Bytes if GMAC_NCFGR.JFRAME=1). This register is also incremented if a
symbol error is detected and the frame is of valid length and does not have an integral number of bytes.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 673
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.78 GMAC Receive Resource Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_RRE
0x1A0
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RXRER[17:16]
R
R
0
0
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
RXRER[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RXRER[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 17:0 – RXRER[17:0] Receive Resource Errors
This bit field counts frames that are not an integral number of bytes long and have bad CRC when their
length is truncated to an integral number of Bytes and are between 64 and 1518 Bytes in length (1536 if
GMAC_NCFGR.MAXFS=1, 10240 Bytes if GMAC_NCFGR.JFRAME=1). This bit field is also incremented if a symbol
error is detected and the frame is of valid length and does not have an integral number of Bytes.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 674
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.79 GMAC Receive Overruns Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_ROE
0x1A4
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Access
Reset
Bit
Access
Reset
Bit
8
RXOVR[9:8]
Access
Reset
Bit
7
6
5
4
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RXOVR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 9:0 – RXOVR[9:0] Receive Overruns
This bit field counts the number of frames that are address recognized but were not copied to memory due to a
receive overrun.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 675
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.80 GMAC IP Header Checksum Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_IHCE
0x1A8
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
HCKER[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – HCKER[7:0] IP Header Checksum Errors
This register counts the number of frames discarded due to an incorrect IP header checksum, but are between 64
and 1518 Bytes (1536 Bytes if GMAC_NCFGR.MAXFS=1 or 10240 Bytes if GMAC_NCFGR.JFRAME=1) and do not
have a CRC error, an alignment error, nor a symbol error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 676
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.81 GMAC TCP Checksum Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TCE
0x1AC
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
TCKER[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – TCKER[7:0] TCP Checksum Errors
This register counts the number of frames discarded due to an incorrect TCP checksum, but are between 64 and
1518 Bytes (1536 Bytes if GMAC_NCFGR.MAXFS=1 or 10240 Bytes if GMAC_NCFGR.JFRAME=1) and do not
have a CRC error, an alignment error, nor a symbol error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 677
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.82 GMAC UDP Checksum Errors Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_UCE
0x1B0
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
UCKER[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – UCKER[7:0] UDP Checksum Errors
This register counts the number of frames discarded due to an incorrect UDP checksum, but are between 64 and
1518 Bytes (1536 Bytes if GMAC_NCFGR.MAXFS=1 or 10240 Bytes if GMAC_NCFGR.JFRAME=1) and do not
have a CRC error, an alignment error, nor a symbol error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 678
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.83 GMAC 1588 Timer Increment Sub-nanoseconds Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TISUBN
0x1BC
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
11
LSBTIR[15:8]
R/W
R/W
0
0
4
3
LSBTIR[7:0]
R/W
R/W
0
0
Bits 15:0 – LSBTIR[15:0] Lower Significant Bits of Timer Increment Register
Lower significant bits of Timer Increment Register [15:0], giving a 24-bit timer_increment counter. These bits are the
sub-ns value which the 1588 timer will be incremented each clock cycle. Bit n = 2(n-16) ns giving a resolution of
approximately 15.2E-15 sec.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 679
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.84 GMAC 1588 Timer Seconds High Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TSH
0x1C0
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
TCS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TCS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TCS[15:0] Timer Count in Seconds
This register is writable. It increments by 1 when the IEEE 1588 nanoseconds counter counts to one second. It may
also be incremented when the Timer Adjust Register is written.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 680
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.85 GMAC 1588 Timer Seconds Low Register
Name:
Offset:
Reset:
Property:
Bit
31
GMAC_TSL
0x1D0
0x00000000
-
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TCS[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
TCS[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
TCS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TCS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – TCS[31:0] Timer Count in Seconds
This register is writable. It increments by 1 when the IEEE 1588 nanoseconds counter counts to one second. It may
also be incremented when the Timer Adjust Register is written.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 681
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.86 GMAC 1588 Timer Nanoseconds Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TN
0x1D4
0x00000000
-
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TNS[29:24]
Access
Reset
Bit
23
22
R/W
0
R/W
0
21
20
TNS[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
TNS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TNS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 29:0 – TNS[29:0] Timer Count in Nanoseconds
This register is writable. It can also be adjusted by writes to the IEEE 1588 Timer Adjust Register. It increments by the
value of the IEEE 1588 Timer Increment Register each clock cycle.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 682
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.87 GMAC 1588 Timer Adjust Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
GMAC_TA
0x1D8
0x00000000
-
31
ADJ
W
0
30
23
22
29
28
27
26
25
24
W
0
W
0
W
0
W
0
19
18
17
16
W
0
W
0
W
0
W
0
11
10
9
8
W
0
W
0
W
0
W
0
3
2
1
0
W
0
W
0
W
0
W
0
ITDT[29:24]
W
0
W
0
21
20
ITDT[23:16]
Access
Reset
W
0
W
0
W
0
W
0
Bit
15
14
13
12
ITDT[15:8]
Access
Reset
W
0
W
0
W
0
W
0
Bit
7
6
5
4
ITDT[7:0]
Access
Reset
W
0
W
0
W
0
W
0
Bit 31 – ADJ Adjust 1588 Timer
Write as '1' to subtract from the 1588 timer. Write as '0' to add to it.
Bits 29:0 – ITDT[29:0] Increment/Decrement
The number of nanoseconds to increment or decrement the IEEE 1588 Timer Nanoseconds Register. If necessary,
the IEEE 1588 Seconds Register will be incremented or decremented.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 683
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.88 GMAC IEEE 1588 Timer Increment Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_TI
0x1DC
0x00000000
-
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
NIT[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
ACNS[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:16 – NIT[7:0] Number of Increments
The number of increments after which the alternative increment is used.
Bits 15:8 – ACNS[7:0] Alternative Count Nanoseconds
Alternative count of nanoseconds by which the 1588 Timer Nanoseconds Register will be incremented each clock
cycle.
Bits 7:0 – CNS[7:0] Count Nanoseconds
A count of nanoseconds by which the IEEE 1588 Timer Nanoseconds Register will be incremented each clock cycle.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 684
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.89 GMAC PTP Event Frame Transmitted Seconds Low Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_EFTSL
0x1E0
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RUD[31:0] Register Update
The register is updated with the value that the IEEE 1588 Timer Seconds Register holds when the SFD of a PTP
transmit primary event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 685
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.90 GMAC PTP Event Frame Transmitted Nanoseconds Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_EFTN
0x1E4
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[29:24]
Access
Reset
Bit
23
22
R
0
R
0
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 29:0 – RUD[29:0] Register Update
The register is updated with the value that the IEEE 1588 Timer Nanoseconds Register holds when the SFD of a PTP
transmit primary event crosses the MII interface. An interrupt is issued when the bit field is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 686
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.91 GMAC PTP Event Frame Received Seconds Low Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_EFRSL
0x1E8
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RUD[31:0] Register Update
The register is updated with the value that the IEEE 1588 Timer Seconds Register holds when the SFD of a PTP
receive primary event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 687
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.92 GMAC PTP Event Frame Received Nanoseconds Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_EFRN
0x1EC
0x00000000
Read-only
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[29:24]
Access
Reset
Bit
23
22
R
0
R
0
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 29:0 – RUD[29:0] Register Update
The register is updated with the value that the IEEE 1588 Timer Nanoseconds Register holds when the SFD of a PTP
receive primary event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 688
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.93 GMAC PTP Peer Event Frame Transmitted Seconds Low Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PEFTSL
0x1F0
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RUD[31:0] Register Update
The register is updated with the value that the IEEE 1588 Timer Seconds Register holds when the SFD of a PTP
transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 689
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.94 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PEFTN
0x1F4
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[29:24]
Access
Reset
Bit
23
22
R
0
R
0
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 29:0 – RUD[29:0] Register Update
The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP
transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 690
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.95 GMAC PTP Peer Event Frame Received Seconds Low Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PEFRSL
0x1F8
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – RUD[31:0] Register Update
The register is updated with the value that the IEEE 1588 Timer Seconds Register holds when the SFD of a PTP
receive primary event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 691
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.96 GMAC PTP Peer Event Frame Received Nanoseconds Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_PEFRN
0x1FC
0x00000000
-
31
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RUD[29:24]
Access
Reset
Bit
23
22
R
0
R
0
21
20
RUD[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
RUD[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RUD[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 29:0 – RUD[29:0] Register Update
The register is updated with the value that the IEEE 1588 Timer Nanoseconds Register holds when the SFD of a PTP
receive primary event crosses the MII interface. An interrupt is issued when the register is updated.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 692
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.97 GMAC Received LPI Transitions
Name:
Offset:
Reset:
Property:
Bit
GMAC_RXLPI
0x270
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
COUNT[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
COUNT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – COUNT[15:0] Count of Received LPI Transitions
A count of the number of times there is a transition from receiving normal idle to receiving low power idle.
Cleared on read.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 693
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.98 GMAC Received LPI Time
Name:
Offset:
Reset:
Property:
Bit
GMAC_RXLPITIME
0x274
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
LPITIME[23:16]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
LPITIME[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
LPITIME[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 23:0 – LPITIME[23:0] Time in LPI
This field increments once every 16 MCK cycles when the bit RXLPIS (LPI Indication (bit 7)) is set in the
GMAC_NSR.
Cleared on read.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 694
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.99 GMAC Transmit LPI Transitions
Name:
Offset:
Reset:
Property:
Bit
GMAC_TXLPI
0x278
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
COUNT[23:16]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
COUNT[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
COUNT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 23:0 – COUNT[23:0] Count of LIP Transitions
A count of the number of times the bit TXLPIEN (Enable LPI Transmission (bit 19)) goes from low to high in the
GMAC_NCR.
Cleared on read.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 695
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.100 GMAC Transmit LPI Time
Name:
Offset:
Reset:
Property:
Bit
GMAC_TXLPITIME
0x27C
0x00000000
Read-only
31
30
29
28
27
26
25
24
Bit
23
22
21
18
17
16
Access
Reset
R
0
R
0
R
0
20
19
LPITIME[23:16]
R
R
0
0
R
0
R
0
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
LPITIME[15:8]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
LPITIME[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 23:0 – LPITIME[23:0] Time in LPI
This field increments once every 16 MCK cycles when the bit TXLPIEN (Enable LPI Transmission (bit 19)) is set in
GMAC_NCR.
Cleared on read.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 696
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.101 GMAC Interrupt Status Register Priority Queue x
Name:
Offset:
Reset:
Property:
Bit
GMAC_ISRPQx
0x0400 + (x-1)*0x04 [x=1..2]
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
HRESP
R/W
0
10
ROVR
R/W
0
9
8
7
TCOMP
R/W
0
6
TFC
R/W
0
5
RLEX
R/W
0
4
3
2
RXUBR
R/W
0
1
RCOMP
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – HRESP HRESP Not OK
Bit 10 – ROVR Receive Overrun
Bit 7 – TCOMP Transmit Complete
Bit 6 – TFC Transmit Frame Corruption Due to AHB Error
Transmit frame corruption due to AHB error—set if an error occurs whilst midway through reading transmit frame
from the AHB, including HRESP errors and buffers exhausted mid frame.
Bit 5 – RLEX Retry Limit Exceeded or Late Collision
Bit 2 – RXUBR RX Used Bit Read
Bit 1 – RCOMP Receive Complete
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 697
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.102 GMAC Transmit Buffer Queue Base Address Register Priority Queue x
Name:
Offset:
Reset:
Property:
GMAC_TBQBAPQx
0x0440 + (x-1)*0x04 [x=1..2]
0x00000000
Read/Write
These registers hold the start address of the transmit buffer queues (transmit buffers descriptor lists) for the additional
queues and must be initialized to the address of valid descriptors, even if the priority queues are not used.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
28
27
TXBQBA[29:22]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
20
19
TXBQBA[21:14]
R/W
R/W
0
0
12
11
TXBQBA[13:6]
R/W
R/W
0
0
4
TXBQBA[5:0]
R/W
R/W
0
0
Bits 31:2 – TXBQBA[29:0] Transmit Buffer Queue Base Address
Contains the address of the start of the transmit queue.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 698
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.103 GMAC Receive Buffer Queue Base Address Register Priority Queue x
Name:
Offset:
Reset:
Property:
GMAC_RBQBAPQx
0x0480 + (x-1)*0x04 [x=1..2]
0x00000000
Read/Write
These registers hold the start address of the receive buffer queues (receive buffers descriptor lists) for the additional
queues used when priority queues are employed.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
28
27
RXBQBA[29:22]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
20
19
RXBQBA[21:14]
R/W
R/W
0
0
12
11
RXBQBA[13:6]
R/W
R/W
0
0
4
RXBQBA[5:0]
R/W
R/W
0
0
Bits 31:2 – RXBQBA[29:0] Receive Buffer Queue Base Address
Holds the address of the start of the receive queue.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 699
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.104 GMAC Receive Buffer Size Register Priority Queue x
Name:
Offset:
Reset:
Property:
Bit
GMAC_RBSRPQx
0x04A0 + (x-1)*0x04 [x=1..2]
0x00000002
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
1
R/W
0
Access
Reset
Bit
Access
Reset
Bit
RBS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
RBS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – RBS[15:0] Receive Buffer Size
DMA receive buffer size in AHB system memory. The value defined by these bits determines the size of buffer to use
in main AHB system memory when writing received data.
The value is defined in multiples of 64 Bytes such that a value of 0x01 corresponds to buffers of 64 Bytes, 0x02
corresponds to 128 Bytes etc.
Examples:
• 0x18: 1536 Bytes (1 × max length frame/buffer)
• 0xA0: 10240 Bytes (1 × 10K jumbo frame/buffer)
Note: This value should never be written as zero.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 700
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.105 GMAC Credit-Based Shaping Control Register
Name:
Offset:
Reset:
Property:
Bit
GMAC_CBSCR
0x4BC
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
QAE
R/W
0
0
QBE
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 1 – QAE Queue A CBS Enable
Value
Description
0
Credit-based shaping on the second highest priority queue (queue A) is disabled.
1
Credit-based shaping on the second highest priority queue (queue A) is enabled.
Bit 0 – QBE Queue B CBS Enable
Value
Description
0
Credit-based shaping on the highest priority queue (queue B) is disabled.
1
Credit-based shaping on the highest priority queue (queue B) is enabled.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 701
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.106 GMAC Credit-Based Shaping IdleSlope Register for Queue A
Name:
Offset:
Reset:
Property:
GMAC_CBSISQA
0x4C0
0x00000000
Read/Write
Credit-based shaping must be disabled in the GMAC_CBSCR before updating this register.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IS[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
IS[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
IS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
IS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – IS[31:0] IdleSlope
IdleSlope value for queue A in Bytes per second.
The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not
exceed the port transmit rate which is dependent on the speed of operation, e.g., 100 Mb/second = 32'h017D7840.
If 50% of bandwidth was to be allocated to a particular queue in 100 Mb/second mode, then the IdleSlope value for
that queue would be calculated as 32'h017D7840 / 2.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 702
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.107 GMAC Credit-Based Shaping IdleSlope Register for Queue B
Name:
Offset:
Reset:
Property:
GMAC_CBSISQB
0x4C4
0x00000000
Read/Write
Credit-based shaping must be disabled in the GMAC_CBSCR before updating this register.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IS[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
IS[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
IS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
IS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – IS[31:0] IdleSlope
IdleSlope value for queue B in bytes/second.
The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not
exceed the port transmit rate which is dependent on the speed of operation, e.g., 100 Mb/second = 32'h017D7840.
If 50% of bandwidth was to be allocated to a particular queue in 100 Mb/sec mode, then the IdleSlope value for that
queue would be calculated as 32'h017D7840 / 2
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 703
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.108 GMAC Screening Type 1 Register x Priority Queue
Name:
Offset:
Reset:
Property:
GMAC_ST1RPQx
0x0500 + x*0x04 [x=0..1]
0x00000000
Read/Write
Screening type 1 registers are used to allocate up to priority queues to received frames based on certain IP or UDP
fields of incoming frames.
Bit
31
30
Access
Reset
Bit
Access
Reset
Bit
29
UDPE
R/W
0
28
DSTCE
R/W
0
20
23
22
21
R/W
0
R/W
0
R/W
0
15
14
27
R/W
0
19
UDPM[11:4]
R/W
R/W
0
0
13
12
11
R/W
0
R/W
0
R/W
0
4
3
UDPM[3:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
7
6
R/W
0
5
DSTCM[3:0]
R/W
R/W
0
0
R/W
0
26
25
UDPM[15:12]
R/W
R/W
0
0
24
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
DSTCM[7:4]
R/W
R/W
0
0
2
R/W
0
1
QNB[2:0]
R/W
0
8
R/W
0
0
R/W
0
Bit 29 – UDPE UDP Port Match Enable
When this bit is written to '1', the UDP Destination Port of the received UDP frame is matched against the value
stored in the bit field UDPM.
Bit 28 – DSTCE Differentiated Services or Traffic Class Match Enable
When this bit is written to '1', the DS (differentiated services) field of the received IPv4 header or TC field (traffic
class) of IPv6 headers are matched against the value stored in bit field DSTCM.
Bits 27:12 – UDPM[15:0] UDP Port Match
When UDP port match enable is set (UDPME=1), the UDP Destination Port of the received UDP frame is matched
against this bit field.
Bits 11:4 – DSTCM[7:0] Differentiated Services or Traffic Class Match
When DS/TC match enable is set (DSTCE), the DS (differentiated services) field of the received IPv4 header or TC
field (traffic class) of IPv6 headers are matched against this bit field.
Bits 2:0 – QNB[2:0] Queue Number
If a match is successful, then the queue value programmed in this bit field is allocated to the frame.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 704
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.109 GMAC Screening Type 2 Register x Priority Queue
Name:
Offset:
Reset:
Property:
GMAC_ST2RPQx
0x0540 + x*0x04 [x=0..1]
0x00000000
Read/Write
Screening type 2 registers are used to allocate up to 2 priority queues to received frames based on the VLAN priority
field of received Ethernet frames.
Bit
31
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
30
COMPCE
R/W
0
23
22
R/W
0
R/W
0
15
R/W
0
14
COMPA[2:0]
R/W
0
7
6
Access
Reset
R/W
0
29
28
R/W
0
R/W
0
27
COMPC[4:0]
R/W
0
21
COMPB[4:0]
R/W
0
20
19
R/W
0
R/W
0
12
ETHE
R/W
0
11
R/W
0
10
I2ETH[2:0]
R/W
0
4
3
2
13
R/W
0
5
VLANP[2:0]
R/W
0
R/W
0
26
25
R/W
0
R/W
0
18
COMPAE
R/W
0
17
R/W
0
24
COMPBE
R/W
0
16
COMPA[4:3]
R/W
R/W
0
0
9
R/W
0
1
QNB[2:0]
R/W
0
8
VLANE
R/W
0
0
R/W
0
Bit 30 – COMPCE Compare C Enable
Value
Description
0
Compare C is disabled.
1
Comparison via the register designated by index COMPC is enabled.
Bits 29:25 – COMPC[4:0] Index of Screening Type 2 Compare Word 0/Word 1 register x
COMPC is a pointer to the compare registers GMAC_ST2CW0x and GMAC_ST2CW1x. When COMPCE=1, the
compare is true if the data at the frame offset ANDed with the value MASKVAL is equal to the value of COMPVAL
ANDed with the value of MASKVAL.
Bit 24 – COMPBE Compare B Enable
Value
Description
0
Compare B is disabled.
1
Comparison via the register designated by index COMPB is enabled.
Bits 23:19 – COMPB[4:0] Index of Screening Type 2 Compare Word 0/Word 1 register x
COMPB is a pointer to the compare registers GMAC_ST2CW0x and GMAC_ST2CW1x. When COMPBE=1, the
compare is true if the data at the frame offset ANDed with the value MASKVAL is equal to the value of COMPVAL
ANDed with the value of MASKVAL.
Bit 18 – COMPAE Compare A Enable
Value
Description
0
Compare A is disabled.
1
Comparison via the register designated by index COMPA is enabled.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 705
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
Bits 17:13 – COMPA[4:0] Index of Screening Type 2 Compare Word 0/Word 1 register x
COMPA is a pointer to the compare registers GMAC_ST2CW0x and GMAC_ST2CW1x. When COMPAE=1, the
compare is true if the data at the frame offset ANDed with the value MASKVAL is equal to the value of COMPVAL
ANDed with the value of MASKVAL.
Bit 12 – ETHE EtherType Enable
Value
Description
0
EtherType match is disabled
1
EtherType match with bits [15:0] of the register designated by the value in I2ETH is enabled
Bits 11:9 – I2ETH[2:0] Index of Screening Type 2 EtherType register x
When EtherType is enabled (ETHE=1), the EtherType field (last EtherType in the header if the frame is VLANtagged) is compared with bits [15:0] in the register designated by the value of this bit field.
Bit 8 – VLANE VLAN Enable
Value
Description
0
VLAN match disabled
1
VLAN match is enabled
Bits 6:4 – VLANP[2:0] VLAN Priority
When VLAN match is enabled (VLANE=1), the VLAN Priority field of the received frame is matched against the value
of this bit field.
Bits 2:0 – QNB[2:0] Queue Number
If a match is successful, then the queue value programmed in QNB is allocated to the frame.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 706
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.110 GMAC Interrupt Enable Register Priority Queue x
Name:
Offset:
Reset:
Property:
GMAC_IERPQx
0x0600 + (x-1)*0x04 [x=1..2]
–
Write-only
The following values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
HRESP
W
–
10
ROVR
W
–
9
8
7
TCOMP
W
–
6
TFC
W
–
5
RLEX
W
–
4
3
2
RXUBR
W
–
1
RCOMP
W
–
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – HRESP HRESP Not OK
Bit 10 – ROVR Receive Overrun
Bit 7 – TCOMP Transmit Complete
Bit 6 – TFC Transmit Frame Corruption Due to AHB Error
Bit 5 – RLEX Retry Limit Exceeded or Late Collision
Bit 2 – RXUBR RX Used Bit Read
Bit 1 – RCOMP Receive Complete
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 707
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.111 GMAC Interrupt Disable Register Priority Queue x
Name:
Offset:
Reset:
Property:
GMAC_IDRPQx
0x0620 + (x-1)*0x04 [x=1..2]
–
Write-only
The following values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
HRESP
W
–
10
ROVR
W
–
9
8
7
TCOMP
W
–
6
TFC
W
–
5
RLEX
W
–
4
3
2
RXUBR
W
–
1
RCOMP
W
–
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – HRESP HRESP Not OK
Bit 10 – ROVR Receive Overrun
Bit 7 – TCOMP Transmit Complete
Bit 6 – TFC Transmit Frame Corruption Due to AHB Error
Bit 5 – RLEX Retry Limit Exceeded or Late Collision
Bit 2 – RXUBR RX Used Bit Read
Bit 1 – RCOMP Receive Complete
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 708
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.112 GMAC Interrupt Mask Register Priority Queue x
Name:
Offset:
Reset:
Property:
GMAC_IMRPQx
0x0640 + (x-1)*0x04 [x=1..2]
0x00000000
Read/Write
A read of this register returns the value of the receive complete interrupt mask.
A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an
interrupt to be generated if a '1' is written.
The following values are valid for all listed bit names of this register:
0: Corresponding interrupt is enabled.
1: Corresponding interrupt is disabled.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
HRESP
R/W
0
10
ROVR
R/W
0
9
8
7
TCOMP
R/W
0
6
AHB
R/W
0
5
RLEX
R/W
0
4
3
2
RXUBR
R/W
0
1
RCOMP
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 11 – HRESP HRESP Not OK
Bit 10 – ROVR Receive Overrun
Bit 7 – TCOMP Transmit Complete
Bit 6 – AHB AHB Error
Bit 5 – RLEX Retry Limit Exceeded or Late Collision
Bit 2 – RXUBR RX Used Bit Read
Bit 1 – RCOMP Receive Complete
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 709
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.113 GMAC Screening Type 2 EtherType Register x
Name:
Offset:
Reset:
Property:
Bit
GMAC_ST2ERx
0x06E0 + x*0x04 [x=0..3]
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
12
11
COMPVAL[15:8]
R/W
R/W
0
0
4
3
COMPVAL[7:0]
R/W
R/W
0
0
Bits 15:0 – COMPVAL[15:0] EtherType Compare Value
When the bit GMAC_ST2RPQ.ETHE is written to '1', the EtherType (last EtherType in the header if the frame is
VLAN tagged) is compared with bits [15:0] in the register designated by GMAC_ST2RPQ.I2ETH.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 710
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.114 GMAC Screening Type 2 Compare Word 0 Register x
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
GMAC_ST2CW0x
0x0700 + x*0x08 [x=0..1]
0x00000000
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
COMPVAL[15:8]
R/W
R/W
0
0
20
19
COMPVAL[7:0]
R/W
R/W
0
0
12
11
MASKVAL[15:8]
R/W
R/W
0
0
4
3
MASKVAL[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:16 – COMPVAL[15:0] Compare Value
The byte stored in bits [23:16] is compared against the first byte of the 2 bytes extracted from the frame.
The byte stored in bits [31:24] is compared against the second byte of the 2 bytes extracted from the frame.
Bits 15:0 – MASKVAL[15:0] Mask Value
The value of MASKVAL ANDed with the 2 bytes extracted from the frame is compared to the value of MASKVAL
ANDed with the value of COMPVAL.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 711
SAM E70/S70/V70/V71
GMAC - Ethernet MAC
37.8.115 GMAC Screening Type 2 Compare Word 1 Register x
Name:
Offset:
Reset:
Property:
Bit
GMAC_ST2CW1x
0x0704 + x*0x08 [x=0..1]
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OFFSSTRT[1]
R/W
0
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
3
OFFSVAL[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
OFFSSTRT[0]
Access
R/W
Reset
0
Bits 8:7 – OFFSSTRT[1:0] Ethernet Frame Offset Start
Value
Name
Description
0
FRAMESTART
Offset from the start of the frame
1
ETHERTYPE
Offset from the byte after the EtherType field
2
IP
Offset from the byte after the IP header field
3
TCP_UDP
Offset from the byte after the TCP/UDP header field
Bits 6:0 – OFFSVAL[6:0] Offset Value in Bytes
The value of OFFSVAL ranges from 0 to 127 bytes, and is counted from either the start of the frame, the byte after
the EtherType field (last EtherType in the header if the frame is VLAN tagged), the byte after the IP header (IPv4 or
IPv6) or the byte after the TCP/UDP header.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 712
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.
USB High-Speed Interface (USBHS)
38.1
Description
The USB High-Speed Interface (USBHS) complies with the Universal Serial Bus (USB) 2.0 specification. (1)
Each pipe/endpoint can be configured in one of several USB transfer types. It can be associated with one, two or
three banks of a DPRAM used to store the current data payload. If two or three banks are used, then one DPRAM
bank is read or written by the CPU or the DMA, while the other is read or written by the USBHS core. This feature is
mandatory for isochronous pipes/endpoints.
The following table describes the hardware configuration of the USB MCU device.
Table 38-1. Description of USB Pipes/Endpoints
Pipe/Endpoint Mnemonic Max. Number
Banks
DMA High Band
Width
Max. Pipe/
Endpoint Size
Type
0
PEP_0
1
N
N
64
Control
1
PEP_1
3
Y
Y
1024
Isochronous/Bulk/Interrupt/
Control
2
PEP_2
3
Y
Y
1024
Isochronous/Bulk/Interrupt/
Control
3
PEP_3
2
Y
Y
1024
Isochronous/Bulk/Interrupt/
Control
4
PEP_4
2
Y
Y
1024
Isochronous/Bulk/Interrupt/
Control
5
PEP_5
2
Y
Y
1024
Isochronous/Bulk/Interrupt/
Control
6
PEP_6
2
Y
Y
1024
Isochronous/Bulk/Interrupt/
Control
7
PEP_7
2
Y
Y
1024
Isochronous/Bulk/Interrupt/
Control
8
PEP_8
2
N
Y
1024
Isochronous/Bulk/Interrupt/
Control
9
PEP_9
2
N
Y
1024
Isochronous/Bulk/Interrupt/
Control
Note:
1. High-bandwidth isochronous transfers supported in device but not host mode.
38.2
Embedded Characteristics
•
•
•
•
•
•
•
Compatible with the USB 2.0 Specification
Supports High-Speed (480 Mbps), Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) Communication
9 Pipes/Endpoints
4096 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
Up to 3 Memory Banks per Pipe/Endpoint (not for Control Pipe/Endpoint)
Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels
On-chip UTMI Transceiver including Pull-ups/Pull-downs
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 713
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.3
Block Diagram
The USBHS provides a hardware device to interface a USB link to a data flow stored in a dual-port RAM (DPRAM).
In normal operation (SPDCONF = 0), the UTMI transceiver requires the UTMI PLL (480 MHz). In case of full-speed or
low-speed only, for a lower consumption (SPDCONF = 1), the UTMI transceiver only requires 48 MHz.
Figure 38-1. USBHS Block Diagram
APB Interface
APB Bus
ctrl
status
AHB1
AHB Bus
HSDP/DP
Rd/Wr/Ready
UTMI
DMA
HSDM/DM
AHB0
USB2.0
CORE
AHB Bus
Host
AHB
Multiplexer
Client
Local
AHB
Client
interface
PEP
Alloc
32 bits
MCK
PMC
DPRAM
System Clock
Domain
16/8 bits
USB Clock
Domain
USB_48M Clock (needed only when SPDCONF=1)
USB_480M Clock (needed only when SPDCONF=0)
38.4
Signal Description
Table 38-2. Signal Description
Name
Description
Type
HSDM/DM
HS/FS Differential Data Line -
Input/Output
HSDP/DP
HS/FS Differential Data Line +
Input/Output
38.5
Product Dependencies
38.5.1
I/O Lines
A regular PIO line must be used to control VBUS. This is configured in the I/O Controller.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 714
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.5.2
Clocks
The clock for the USBHS bus interface is generated by the Power Management Controller. This clock can be enabled
or disabled in the Power Management Controller. It is recommended to disable the USBHS before disabling the
clock, to avoid freezing the USBHS in an undefined state.
Before enabling the USB clock in the Power Management Controller, the USBHS must be enabled (by writing a one
to the USBHS_CTRL.USBE bit and a zero to the USBHS_CTRL.FRZCLK bit).
The USBHS can work in two modes:
•
•
Normal mode (SPDCONF = 0) where High speed, Full speed and Low speed are available.
Low-power mode (SPDCONF = 1) where Full speed and Low speed are available.
To ensure successful startup, follow the sequences below:
- In Normal mode:
1.
2.
3.
4.
Enable the USBHS peripheral clock. This is done via the register PMC_PCER.
Enable the USBHS (UIMOD, USBE = 1, FRZCLK = 0).
Enable the UPLL 480 MHz.
Wait for the UPLL 480 MHz to be considered as locked by the PMC.
- In Low-power mode:
1.
2.
3.
4.
5.
As USB_48M must be set to 48 MHz (refer to the section “Power Management Controller (PMC)”), select
either the PLLA or the UPLL (previously set to ON), and program the PMC_USB register (source selection and
divider).
Enable the USBHS peripheral clock (PMC_PCER).
Put the USBHS in Low-power mode (SPDCONF = 1).
Enable the USBHS (UIMOD, USBE = 1, FRZCLK = 0).
Enable the USBCK bit (PMC_SCER).
Related Links
31. Power Management Controller (PMC)
38.5.3
Interrupt Sources
The USBHS interrupt request line is connected to the interrupt controller. Using the USBHS interrupt requires the
interrupt controller to be programmed first.
38.5.4
USB Pipe/Endpoint x FIFO Data Register (USBFIFOxDATA)
The application has access to each pipe/endpoint FIFO through its reserved 32 KB address space. The application
can access a 64-KB buffer linearly or fixedly as the DPRAM address increment is fully handled by hardware. Byte,
half-word and word accesses are supported. Data should be accessed in a big-endian way.
Disabling the USBHS (by writing a zero to the USBHS_CTRL.USBE bit) does not reset the DPRAM.
38.6
Functional Description
38.6.1
USB General Operation
38.6.1.1 Power-On and Reset
The following figure describes the USBHS general states.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 715
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Figure 38-2. General States
Macro off:
USBHS_CTRL.USBE = 0
Clock stopped:
USBHS_CTRL.FRZCLK = 1
USBHS_CTRL.USBE = 0
Reset
HW
RESET
USBHS_CTRL.USBE = 1
USBHS_CTRL.UIMOD = 1
USBHS_CTRL.USBE = 0
USBHS_CTRL.USBE = 1
USBHS_CTRL.UIMOD = 0
Device
USBHS_CTRL_USBE = 0
Host
After a hardware reset, the USBHS is in Reset state. In this state:
•
•
•
•
•
The USBHS is disabled. The USBHS Enable bit in the General Control register (USBHS_CTRL.USBE) is zero.
The USBHS clock is stopped in order to minimize power consumption. The Freeze USB Clock bit
(USBHS_CTRL.FRZCLK) is set.
The UTMI is in Suspend mode.
The internal states and registers of the Device and Host modes are reset.
The DPRAM is not cleared and is accessible.
After writing a one to USBHS_CTRL.USBE, the USBHS enters the Device or the Host mode in idle state.
The USBHS can be disabled at any time by writing a zero to USBHS_CTRL.USBE. This acts as a hardware reset,
except that the USBHS_CTRL.FRZCLK, USBHS_CTRL.UIMOD and USBHS_DEVCTRL.LS bits are not reset.
38.6.1.2 Interrupts
One interrupt vector is assigned to the USB interface. The following figure shows the structure of the USB interrupt
system.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 716
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Figure 38-3. Interrupt System
& = Logical AND
USBHS_DEVEPTISRx.TXINI
USBHS_DEVEPTIMRx.TXINE
USBHS_SR.RDERRI
USBHS_DEVEPTISRx.RXOUTI
USB General
Interrupt
USBHS_CTRL.RDERRE
USBHS_DEVEPTIMRx.RXOUTE
USBHS_DEVEPTISRx.RXSTPI
USBHS_DEVEPTIMRx.RXSTPE
USBHS_DEVEPTISRx.UNDERFI
USBHS_DEVEPTIMRx.UNDERFE
USBHS_DEVEPTISRx.NAKOUTI
USBHS_DEVEPTISRx.HBISOINERRI
USBHS_DEVEPTIMRx.NAKOUTE
USBHS_DEVEPTIMRx.HBISOINERRE
USBHS_DEVEPTISRx.NAKINI
USBHS_DEVEPTIMRx.NAKINE
USBHS_DEVEPTISRx.HBISOFLUSHI
USBHS_DEVEPTISRx.OVERFI
USBHS_DEVEPTIMRx.HBISOFLUSHE
USB Device
Endpoint X
Interrupt
USBHS_DEVEPTIMRx.OVERFE
USBHS_DEVEPTISRx.STALLEDI
USBHS_DEVEPTIMRx.STALLEDE
USBHS_DEVEPTISRx.CRCERRI
USBHS_DEVEPTIMRx.CRCERRE
USBHS_DEVEPTISRx.SHORTPACKET
USBHS_DEVEPTIMRx.SHORTPACKETE
USBHS_DEVIMR.MSOF
USBHS_DEVEPTIMRx.MDATAE
USBHS_DEVIMR.SUSP
USBHS_DEVEPTIMRx.DATAXE
USBHS_DEVIMR.SOF
USBHS_DEVEPTISRx.DTSEQ=MDATA & UESTAX.RXOUTI
USBHS_DEVIMR.MSOFE
USBHS_DEVEPTISRx.DTSEQ=DATAX & UESTAX.RXOUTI
USBHS_DEVIMR.SUSPE
USBHS_DEVEPTISRx.TRANSERR
USBHS_DEVIMR.SOFE
USBHS_DEVEPTIMRx.TRANSERRE
USBHS_DEVIMR.EORST
USBHS_DEVEPTISRx.NBUSYBK
USB
Interrupt
USBHS_DEVIMR.EORSTE
USBHS_DEVEPTIMRx.NBUSYBKE
USBHS_DEVIMR.WAKEUP
USB Device
Interrupt
USBHS_DEVIMR.WAKEUPE
USBHS_DEVIMR.EORSM
USBHS_DEVIMR.EORSME
USBHS_DEVIMR.UPRSM
USBHS_DEVIMR.UPRSME
USBHS_DEVDMASTATUSx.EOT_STA
USBHS_DEVIMR.EPXINT
UDDMAX_CONTROL.EOT_IRQ_EN
USBHS_DEVDMASTATUSx.EOCH_BUFF_STA
UDDMAX_CONTROL.EOBUFF_IRQ_EN
USBHS_DEVDMASTATUSx.DESC_LD_STA
UDDMAX_CONTROL.DESC_LD_IRQ_EN
USBHS_DEVIMR.EPXINTE
USBHS_DEVIMR.DMAXINT
USB Device
DMA Channel X
Interrupt
USBHS_DEVIMR.DMAXINTE
USBHS_HSTPIPISRx.RXINI
USBHS_HSTPIPIMRx.RXINE
USBHS_HSTPIPISRx.TXOUTI
USBHS_HSTPIPIMRx.TXOUTE
USBHS_HSTPIPISRx.TXSTPI
USBHS_HSTPIPIMRx.TXSTPE
USBHS_HSTPIPISRx.UNDERFI
USBHS_HSTPIPIMRx.UNDERFIE
USBHS_HSTPIPISRx.PERRI
USBHS_HSTISR.DCONNI
USBHS_HSTPIPIMRx.PERRE
USBHS_HSTPIPISRx.NAKEDI
USBHS_HSTIMR.DCONNIE
USBHS_HSTISR.DDISCI
USBHS_HSTPIPIMRx.NAKEDE
USBHS_HSTPIPISRx.OVERFI
USBHS_HSTIMR.DDISCIE
USBHS_HSTISR.RSTI
USBHS_HSTPIPIMRx.OVERFIE
USBHS_HSTPIPISRx.RXSTALLDI
USBHS_HSTIMR.RSTIE
USBHS_HSTPIPIMRx.RXSTALLDE
USBHS_HSTPIPISRx.CRCERRI
USBHS_HSTPIPIMRx.CRCERRE
USBHS_HSTPIPISRx.SHORTPACKETI
USB Host
Pipe X
Interrupt
USBHS_HSTISR.RSMEDI
USBHS_HSTIMR.RSMEDIE
USBHS_HSTISR.RXRSMI
USBHS_HSTIMR.RXRSMIE
USBHS_HSTPIPIMRx.SHORTPACKETIE
USBHS_HSTISR.HSOFI
USBHS_HSTPIPIMRx.NBUSYBKE
USBHS_HSTISR.HWUPI
USBHS_HSTPIPISRx.NBUSYBK
USB Host
Interrupt
USBHS_HSTIMR.HSOFIE
USBHS_HSTIMR.HWUPIE
USBHS_HSTDMASTATUSx.EOT_STA
USBHS_HSTISR.PXINT
USBHS_HSTDMACONTROLx.EOT_IRQ_EN
USBHS_HSTDMASTATUSx.EOCH_BUFF_STA
USBHS_HSTDMACONTROLx.EOBUFF_IRQ_EN
USBHS_HSTDMASTATUSx.DESC_LD_STA
USBHS_HSTDMACONTROLx.DESC_LD_IRQ_EN
USBHS_HSTIMR.PXINTE
USBHS_HSTISR.DMAXINT
USB Host
DMA Channel X
Interrupt
USBHS_HSTIMR.DMAXINTE
Asynchronous interrupt source
See Interrupts in the Device Operation section and Interrupts in the Host Operation section for further details about
device and host interrupts.
There are two kinds of general interrupts: processing, i.e., their generation is part of the normal processing, and
exception, i.e., errors (not related to CPU exceptions).
38.6.1.3 MCU Power Modes
USB Suspend Mode
In Peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt Status register (USBHS_DEVISR.SUSP)
indicates that the USB line is in Suspend mode. In this case, the transceiver is automatically set in Suspend mode to
reduce consumption.
Clock Frozen
The USBHS can be frozen when the USB line is in the Suspend mode, by writing a one to the
USBHS_CTRL.FRZCLK bit, which reduces power consumption.
In this case, it is still possible to access the following:
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 717
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
•
USBHS_CTRL.FRZCLK, USBHS_CTRL.USBE and USBHS_DEVCTRL.LS bits
Moreover, when USBHS_CTRL.FRZCLK = 1, only the asynchronous interrupt sources can trigger the USB interrupt:
•
•
Wakeup Interrupt (USBHS_DEVISR.WAKEUP)
Host Wakeup Interrupt (USBHS_HSTISR.HWUPI)
38.6.1.4 Speed Control
Device Mode
When the USB interface is in Device mode, the speed selection (Full-speed or High-speed) is performed
automatically by the USBHS during the USB reset according to the host speed capability. At the end of the USB
reset, the USBHS enables or disables high-speed terminations and pull-up.
It is possible to set the USBHS_DEVCTRL.SPDCONF.
Host Mode
When the USB interface is in Host mode, internal pull-down resistors are connected on both D+ and D- and the
interface detects the speed of the connected device, which is reflected by the Speed Status (USBHS_SR.SPEED)
field.
38.6.1.5 DPRAM Management
Pipes and endpoints can only be allocated in ascending order, from pipe/endpoint 0 to the last pipe/endpoint to be
allocated. The user should therefore configure them in the same order.
The allocation of a pipe/endpoint x starts when the Endpoint Memory Allocate bit in the Endpoint x Configuration
register (USBHS_DEVEPTCFGx.ALLOC) is written to one. Then, the hardware allocates a memory area in the
DPRAM and inserts it between the x - 1 and x+ 1 pipes/endpoints. The x+ 1 pipe/endpoint memory window slides up
and its data is lost. Note that the following pipe/endpoint memory windows (from x+ 2) do not slide.
Disabling a pipe, by writing a zero to the Pipe x Enable bit in the Host Pipe register (USBHS_HSTPIP.PENx),
or disabling an endpoint, by writing a zero to the Endpoint x Enable bit in the Device Endpoint
register (USBHS_DEVEPT.EPENx), does not reset the USBHS_DEVEPTCFGx.ALLOC bit or the Pipe/Endpoint
configuration:
•
•
Pipe Configuration
– Pipe Banks (USBHS_HSTPIPCFGx.PBK)
– Pipe Size (USBHS_HSTPIPCFGx.PSIZE)
– Pipe Token (USBHS_HSTPIPCFGx.PTOKEN)
– Pipe Type (USBHS_HSTPIPCFGx.PTYPE)
– Pipe Endpoint Number (USBHS_HSTPIPCFGx.PEPNUM)
– Pipe Interrupt Request Frequency (USBHS_HSTPIPCFGx.INTFRQ)
Endpoint Configuration
– Endpoint Banks (USBHS_DEVEPTCFGx.EPBK)
– Endpoint Size (USBHS_DEVEPTCFGx. EPSIZE)
– Endpoint Direction (USBHS_DEVEPTCFGx.EPDIR)
– Endpoint Type (USBHS_DEVEPTCFGx.EPTYPE)
To free endpoint memory, the user must write a zero to the USBHS_DEVEPTCFGx.ALLOC bit. The x+ 1 pipe/
endpoint memory window then slides down and its data is lost. Note that the following pipe/endpoint memory
windows (from x + 2) do not slide.
The following figure illustrates the allocation and reorganization of the DPRAM in a typical example.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 718
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Figure 38-4. Allocation and Reorganization of the DPRAM
Free Memory
Free Memory
Free Memory
Free Memory
PEP5
PEP5
PEP5
PEP5
PEP4
PEP4
PEP4 Lost Memory
PEP3
PEP3
(ALLOC stays at 1)
PEP4
PEP2
PEP2
PEP2
PEP2
PEP1
PEP1
PEP1
PEP1
PEP0
PEP0
PEP0
PEP0
Conflict
PEP4
Device:
USBHS_DEVEPT.EPENx = 1
USBHS_DEVEPTCFGx.ALLOC = 1
Device:
USBHS_DEVEPT.EPEN3 = 0
Device:
USBHS_DEVEPTCFG3.ALLOC = 0
Device:
USBHS_DEVEPT.EPEN3 = 1
USBHS_DEVEPTCFG3.ALLOC = 1
Host:
USBHS_HSTPIP.EPENx = 1
USBHS_HSTPIPCFGx.ALLOC = 1
Host:
USBHS_HSTPIP.EPEN3 = 0
Host:
USBHS_HSTPIPCFG3.ALLOC = 0
Host:
USBHS_HSTPIP.EPEN3 = 1
USBHS_HSTPIPCFG3.ALLOC = 1
Pipes/Endpoints 0..5
Activated
1.
2.
3.
4.
PEP3 (larger size)
Pipe/Endpoint 3
Disabled
Pipe/Endpoint 3
Memory Freed
Pipe/Endpoint 3
Activated
Pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order. Each pipe/endpoint then
owns a memory area in the DPRAM.
Pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller.
In order to free its memory, its USBHS_DEVEPTCFGx.ALLOC bit is written to zero. The pipe/endpoint 4
memory window slides down, but pipe/endpoint 5 does not move.
If the user chooses to reconfigure pipe/endpoint 3 with a larger size, the controller allocates a memory area
after the pipe/endpoint 2 memory area and automatically slides up the pipe/endpoint 4 memory window. Pipe/
endpoint 5 does not move and a memory conflict appears as the memory windows of pipes/endpoints 4 and 5
overlap. The data of these pipes/endpoints is potentially lost.
Note: 1. The data of pipe or endpoint 0 cannot be lost (except if it is de-allocated) as the memory allocation
and de-allocation may affect only higher pipes/endpoints.
Note: 2. Deactivating then reactivating the same pipe/endpoint with the same configuration only modifies
temporarily the controller DPRAM pointer and size for this pipe/endpoint. Nothing changes in the DPRAM.
Higher endpoints seem not to have been moved and their data is preserved as long as nothing has been
written or received into them while changing the allocation state of the first pipe/endpoint.
Note: 3. When the user writes a one to the USBHS_DEVEPTCFGx.ALLOC bit, the Configuration OK Status
bit (USBHS_DEVEPTISRx.CFGOK) is set only if the configured size and number of banks are correct as
compared to the endpoint maximum allowed values and to the maximum FIFO size (i.e., the DPRAM size).
The USBHS_DEVEPTISRx.CFGOK value does not consider memory allocation conflicts.
38.6.1.6 Pad Suspend
Figure 38-5 shows the pad behavior.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 719
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Figure 38-5. Pad Behavior
| = Logical OR
& = Logical AND
USBHS_CTRL.USBE = 1
& USBHS_DEVCTRL.DETACH = 0
& Suspend
Idle
USBHS_CTRL.USBE = 0
| USBHS_DEVCTRL.DETACH = 1
| Suspend
•
•
Active
In Idle state, the pad is put in Low-power mode, i.e., the differential receiver of the USB pad is off, and internal
pull-downs with a strong value (15 K) are set in HSDP/D and HSDM/DM to avoid floating lines.
In Active state, the pad is working.
Figure 38-6 illustrates the pad events leading to a PAD state change.
Figure 38-6. Pad Events
USBHS_DEVISR.SUSP
Suspend detected
USBHS_DEVISR.WAKEUP
Cleared on wakeup
Wakeup detected
Cleared by software to acknowledge the interrupt
PAD State
Active
Idle
Active
The USBHS_DEVISR.SUSP bit is set and the Wakeup Interrupt (USBHS_DEVISR.WAKEUP) bit is cleared when a
USB “Suspend” state has been detected on the USB bus. This event automatically puts the USB pad in Idle state.
The detection of a non-idle event sets USBHS_DEVISR.WAKEUP, clears USBHS_DEVISR.SUSP and wakes up the
USB pad.
The pad goes to the Idle state if the USBHS is disabled or if the USBHS_DEVCTRL.DETACH bit = 1. It returns to the
Active state when USBHS_CTRL.USBE = 1 and USBHS_DEVCTRL.DETACH = 0.
38.6.2
USB Device Operation
38.6.2.1 Introduction
In Device mode, the USBHS supports high-, full- and low-speed data transfers.
In addition to the default control endpoint, 9 endpoints are provided, which can be configured with an isochronous,
bulk or interrupt type, as described in Table 38-1.
As the Device mode starts in Idle state, the pad consumption is reduced to the minimum.
38.6.2.2 Power-On and Reset
The following figure describes the USBHS Device mode main states.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 720
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Figure 38-7. Device Mode Main States
| = Logical OR
& = Logical AND
USBHS_CTRL.USBE = 0
| USBHS_CTRL.UIMOD = 0
USBHS_CTRL.USBE = 0
| USBHS_CTRL.UIMOD = 0
Reset
Idle
USBHS_CTRL.USBE = 1
and USBHS_CTRL.UIMOD = 1
HW
USBHS_HSTCTRL.RESET
After a hardware reset, the USBHS Device mode is in Reset state. In this state:
•
•
•
•
the USBHS clock is stopped to minimize power consumption (USBHS_CTRL.FRZCLK = 1),
the internal registers of the Device mode are reset,
the endpoint banks are de-allocated,
neither D+ nor D- is pulled up (USBHS_DEVCTRL.DETACH = 1).
D+ or D- is pulled up according to the selected speed as soon as the USBHS_DEVCTRL.DETACH bit is written to
zero. See “Device Mode” for further details.
When the USBHS is enabled (USBHS_CTRL.USBE = 1) in Device mode (USBHS_CTRL.UIMOD = 1), its Device
mode state enters Idle state with minimal power consumption. This does not require the USB clock to be activated.
The USBHS Device mode can be disabled and reset at any time by disabling the USBHS (by writing a zero to
USBHS_CTRL.USBE) or when the Host mode is enabled (USBHS_CTRL.UIMOD = 0).
38.6.2.3 USB Reset
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the controller:
•
•
•
•
•
All endpoints are disabled, except the default control endpoint.
The default control endpoint is reset (see 38.6.2.4. Endpoint Reset for more details).
The data toggle sequence of the default control endpoint is cleared.
At the end of the reset process, the End of Reset (USBHS_DEVISR.EORST) bit is set.
During a reset, the USBHS automatically switches to High-speed mode if the host is High-speed-capable (the
reset is called High-speed reset). The user should observe the USBHS_SR.SPEED field to know the speed
running at the end of the reset (USBHS_DEVISR.EORST = 1).
38.6.2.4 Endpoint Reset
An endpoint can be reset at any time by writing a one to the Endpoint x Reset bit USBHS_DEVEPT.EPRSTx. This
is recommended before using an endpoint upon hardware reset or when a USB bus reset has been received. This
resets:
•
•
•
the internal state machine of the endpoint,
the receive and transmit bank FIFO counters,
all registers of this endpoint (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, the Endpoint x
Control (USBHS_DEVEPTIMRx) register), except its configuration (USBHS_DEVEPTCFGx.ALLOC,
USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR,
USBHS_DEVEPTCFGx.EPTYPE) and the Data Toggle Sequence (USBHS_DEVEPTISRx.DTSEQ) field.
Note: The interrupt sources located in USBHS_DEVEPTISRx are not cleared when a USB bus reset has been
received.
The endpoint configuration remains active and the endpoint is still enabled.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 721
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to the
CLEAR_FEATURE USB request. This can be achieved by writing a one to the Reset Data Toggle Set bit (RSTDTS)
in the Device Endpoint x Control Set register (this sets the Reset Data Toggle bit USBHS_DEVEPTIMRx.RSTDT).
In the end, the user has to write a zero to the USBHS_DEVEPT.EPRSTx bit to complete the reset operation and to
start using the FIFO.
38.6.2.5 Endpoint Activation
The endpoint is maintained inactive and reset (see "Endpoint Reset" for more information) as long as it is disabled
(USBHS_DEVEPT.EPENx = 0). USBHS_DEVEPTISRx.DTSEQ is also reset.
The algorithm represented in the following figure must be followed to activate an endpoint.
Figure 38-8. Endpoint Activation Algorithm
Endpoint
Activation
Enable the endpoint.
USBHS_DEVEPT.EPENx = 1
Configure the endpoint:
- type
- direction
- size
- number of banks
Allocate the configured DPRAM banks.
USBHS_DEVEPTCFGx
.EPTYPE
.EPDIR
.EPSIZE
.EPBK
.ALLOC
USBHS_HSTPIPISRx.CFCFGOK == 1?
Test if the endpoint configuration is correct.
No
Yes
Endpoint
Activated
ERROR
As long as the endpoint is not correctly configured (USBHS_HSTPIPISRx.CFGOK = 0), the controller does not
acknowledge the packets sent by the host to this endpoint.
The USBHS_HSTPIPISRx.CFGOK bit is set provided that the configured size and number of banks are correct as
compared to the endpoint maximal allowed values (see the Description of USB Pipes/Endpoints table) and to the
maximal FIFO size (i.e., the DPRAM size).
See "DPRAM Management" for additional information.
38.6.2.6 Address Setup
The USB device address is set up according to the USB protocol.
•
•
•
•
•
After all kinds of resets, the USB device address is 0.
The host starts a SETUP transaction with a SET_ADDRESS (addr) request.
The user writes this address to the USB Address (USBHS_DEVCTRL.UADD) field, and writes a zero to the
Address Enable (USBHS_DEVCTRL.ADDEN) bit, so the actual address is still 0.
The user sends a zero-length IN packet from the control endpoint.
The user enables the recorded USB device address by writing a one to USBHS_DEVCTRL.ADDEN.
Once the USB device address is configured, the controller filters the packets to accept only those targeting the
address stored in USBHS_DEVCTRL.UADD.
USBHS_DEVCTRL.UADD and USBHS_DEVCTRL.ADDEN must not be written all at once.
USBHS_DEVCTRL.UADD and USBHS_DEVCTRL.ADDEN are cleared:
•
•
•
on a hardware reset,
when the USBHS is disabled (USBHS_CTRL.USBE = 0),
when a USB reset is detected.
When USBHS_DEVCTRL.UADD or USBHS_DEVCTRL.ADDEN is cleared, the default device address 0 is used.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 722
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.6.2.7 Suspend and Wakeup
When an idle USB bus state has been detected for 3 ms, the controller sets the Suspend (USBHS_DEVISR.SUSP)
interrupt bit. The user may then write a one to the USBHS_CTRL.FRZCLK bit to reduce power consumption.
To recover from the Suspend mode, the user should wait for the Wakeup (USBHS_DEVISR.WAKEUP) interrupt bit,
which is set when a non-idle event is detected, then write a zero to USBHS_CTRL.FRZCLK.
As the USBHS_DEVISR.WAKEUP interrupt bit is set when a non-idle event is detected, it can occur whether the
controller is in the Suspend mode or not. The USBHS_DEVISR.SUSP and USBHS_DEVISR.WAKEUP interrupts are
thus independent, except that one bit is cleared when the other is set.
38.6.2.8 Detach
The reset value of the USBHS_DEVCTRL.DETACH bit is one.
It is possible to initiate a device re-enumeration by simply writing a one, and then a zero, to
USBHS_DEVCTRL.DETACH.
USBHS_DEVCTRL.DETACH acts on the pull-up connections of the D+ and D- pads. See “Device Mode” for further
details.
38.6.2.9 Remote Wakeup
The Remote Wakeup request (also known as Upstream Resume) is the only one the device may send without a
host invitation, assuming a host command allowing the device to send such a request was previously issued. The
sequence is the following:
1.
2.
3.
4.
5.
The USBHS must have detected a “Suspend” state on the bus, i.e., the Remote Wakeup request can only be
sent after a USBHS_DEVISR.SUSP interrupt has been set.
The user writes a one to the Remote Wakeup (USBHS_DEVCTRL.RMWKUP) bit to send an upstream resume
to the host for a remote wakeup. This will automatically be done by the controller after 5 ms of inactivity on the
USB bus.
When the controller sends the upstream resume, the Upstream Resume (USBHS_DEVISR.UPRSM) interrupt
is set and USBHS_DEVISR.SUSP is cleared.
USBHS_DEVCTRL.RMWKUP is cleared at the end of the upstream resume.
When the controller detects a valid “End of Resume” signal from the host, the End of Resume
(USBHS_DEVISR.EORSM) interrupt is set.
38.6.2.10 STALL Request
For each endpoint, the STALL management is performed using:
•
•
the STALL Request (USBHS_DEVEPTIMRx.STALLRQ) bit to initiate a STALL request,
the STALLed Interrupt (USBHS_DEVEPTISRx.STALLEDI) bit, which is set when a STALL handshake has been
sent.
To answer the next request with a STALL handshake, USBHS_DEVEPTIMRx.STALLRQ has to be set
by writing a one to the STALL Request Set (USBHS_DEVEPTIERx.STALLRQS) bit. All following requests
are discarded (USBHS_DEVEPTISRx.RXOUTI, etc. is not be set) and handshaked with a STALL until the
USBHS_DEVEPTIMRx.STALLRQ bit is cleared, which is done when a new SETUP packet is received (for control
endpoints) or when the STALL Request Clear (USBHS_DEVEPTIMRx.STALLRQC) bit is written to one.
Each time a STALL handshake is sent, the USBHS_DEVEPTISRx.STALLEDI bit is set by the USBHS and the PEP_x
interrupt is set.
Special Considerations for Control Endpoints
If a SETUP packet is received into a control endpoint for which a STALL is requested, the Received
SETUP Interrupt (USBHS_DEVEPTISRx.RXSTPI) bit is set and USBHS_DEVEPTIMRx.STALLRQ and
USBHS_DEVEPTISRx.STALLEDI are cleared. The SETUP has to be ACKed.
This simplifies the enumeration process management. If a command is not supported or contains an error, the user
requests a STALL and can return to the main task, waiting for the next SETUP request.
STALL Handshake and Retry Mechanism
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
USBHS_DEVEPTIMRx.STALLRQ bit is set and if no retry is required.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 723
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.6.2.11 Management of Control Endpoints
Overview
A SETUP request is always ACKed. When a new SETUP packet is received, the USBHS_DEVEPTISRx.RXSTPI is
set; the Received OUT Data Interrupt (USBHS_DEVEPTISRx.RXOUTI) bit is not.
The FIFO Control (USBHS_DEVEPTIMRx.FIFOCON) bit and the Read/Write Allowed
(USBHS_DEVEPTISRx.RWALL) bit are irrelevant for control endpoints. The user never uses them on these
endpoints. When read, their values are always zero.
Control endpoints are managed using:
•
•
•
the USBHS_DEVEPTISRx.RXSTPI bit, which is set when a new SETUP packet is received and which is cleared
by firmware to acknowledge the packet and to free the bank;
the USBHS_DEVEPTISRx.RXOUTI bit, which is set when a new OUT packet is received and which is cleared
by firmware to acknowledge the packet and to free the bank;
the Transmitted IN Data Interrupt (USBHS_DEVEPTISRx.TXINI) bit, which is set when the current bank is ready
to accept a new IN packet and which is cleared by firmware to send the packet.
Control Write
Figure 38-9 shows a control write transaction. During the status stage, the controller does not necessarily send a
NAK on the first IN token:
•
•
if the user knows the exact number of descriptor bytes that must be read, it can then anticipate the status stage
and send a zero-length packet after the next IN token, or
it can read the bytes and wait for the NAKed IN Interrupt (USBHS_DEVEPTISRx.NAKINI), which acknowledges
that all the bytes have been sent by the host and that the transaction is now in the status stage.
Figure 38-9. Control Write
SETUP
USB Bus
DATA
SETUP
OUT
HW
USBHS_DEVEPTISRx.RXSTPI
STATUS
OUT
IN
IN
NAK
SW
USBHS_DEVEPTISRx.RXOUTI
HW
SW
HW
SW
USBHS_DEVEPTISRx.TXINI
SW
Control Read
Figure 38-10 shows a control read transaction. The USBHS has to manage the simultaneous write requests from the
CPU and the USB host.
Figure 38-10. Control Read
SETUP
USB Bus
USBHS_DEVEPTISRxRXSTPI
DATA
SETUP
HW
IN
STATUS
IN
OUT
SW
USBHS_DEVEPTISRx.RXOUTI
USBHS_DEVEPTISRx.TXINI
OUT
NAK
HW
SW
HW
SW
SW
Wr Enable
HOST
Wr Enable
CPU
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all data written by the CPU is lost and clearing
USBHS_DEVEPTISRx.TXINI has no effect.
The user checks if the transmission or the reception is complete.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 724
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
The OUT retry is always ACKed. This reception sets USBHS_DEVEPTISRx.RXOUTI and
USBHS_DEVEPTISRx.TXINI. Handle this with the following software algorithm:
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
Once the OUT status stage has been received, the USBHS waits for a SETUP request. The SETUP request has
priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO
reset when a SETUP is received.
The user has to consider that the byte counter is reset when a zero-length OUT packet is received.
38.6.2.12 Management of IN Endpoints
Overview
IN packets are sent by the USB device controller upon IN requests from the host. All data which acknowledges or not
the bank can be written when it is full.
The endpoint must be configured first.
The USBHS_DEVEPTISRx.TXINI bit is set at the same time as USBHS_DEVEPTIMRx.FIFOCON when
the current bank is free. This triggers a PEP_x interrupt if the Transmitted IN Data Interrupt Enable
(USBHS_DEVEPTIMRx.TXINE) bit is one.
USBHS_DEVEPTISRx.TXINI is cleared by software (by writing a one to the Transmitted IN Data Interrupt Clear bit
(USBHS_DEVEPTIDRx.TXINIC) to acknowledge the interrupt, which has no effect on the endpoint FIFO.
The user then writes into the FIFO and writes a one to the FIFO Control Clear (USBHS_DEVEPTIDRx.FIFOCONC)
bit to clear the USBHS_DEVEPTIMRx.FIFOCON bit. This allows the USBHS to send the data. If the IN endpoint
is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.TXINI and
USBHS_DEVEPTIMRx.FIFOCON bits are updated in accordance with the status of the next bank.
USBHS_DEVEPTISRx.TXINI is always cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
The USBHS_DEVEPTISRx.RWALL bit is set when the current bank is not full, i.e., when the software can write
further data into the FIFO.
Figure 38-11. Example of an IN Endpoint with one Data Bank
NAK
DATA
(bank 0)
IN
ACK
IN
HW
USBHS_DEVEPTISRx.TXINI
SW
SW
write data to CPU
BANK 0
USBHS_DEVEPTIMRx.FIFOCON
write data to CPU
BANK 0
SW
SW
Figure 38-12. Example of an IN Endpoint with two Data Banks
DATA
(bank 0)
IN
ACK
IN
DATA
(bank 1)
ACK
HW
USBHS_DEVEPTISRx.TXINI
USBHS_DEVEPTIMRx.FIFOCON
© 2022 Microchip Technology Inc.
and its subsidiaries
SW
write data to CPU
BANK 0
SW
SW
write data to CPU
BANK 1
Complete Data Sheet
SW
SW
write data to CPU
BANK0
DS60001527G-page 725
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Detailed Description
The data is written as follows:
•
•
•
•
When the bank is empty, USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON are set, which
triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.TXINE = 1.
The user acknowledges the interrupt by clearing USBHS_DEVEPTISRx.TXINI.
The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data (USBFIFOnDATA)
register, until all the data frame is written or the bank is full (in which case USBHS_DEVEPTISRx.RWALL is
cleared and the Byte Count (USBHS_DEVEPTISRx.BYCT) field reaches the endpoint size).
The user allows the controller to send the bank and switches to the next bank (if any) by clearing
USBHS_DEVEPTIMRx.FIFOCON.
If the endpoint uses several banks, the current one can be written while the previous one is being read by the
host. Then, when the user clears USBHS_DEVEPTIMRx.FIFOCON, the following bank may already be free and
USBHS_DEVEPTISRx.TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN stage of a control or
isochronous IN transaction. The Kill IN Bank (USBHS_DEVEPTIMRx.KILLBK) bit is used to kill the last written bank.
The best way to manage this abort is to apply the algorithm represented in the following figure.
Figure 38-13. Abort Algorithm
Endpoint
Abort
Disable the USBHS_DEVEPTISRx.TXINI interrupt.
USBHS_DEVEPTIDRx.TXINEC = 1
USBHS_DEVEPTISRx.NBUSYBK == 0?
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
No
Yes
USBHS_DEVEPT. EPRSTx = 1
Yes
USBHS_DEVEPTIERx.KILLBKS = 1
Kill the last written bank.
USBHS_DEVEPTIMRx.KILLBK == 1?
Wait for the end of the
procedure
No
Abort Done
38.6.2.13 Management of OUT Endpoints
Overview
OUT packets are sent by the host. All data which acknowledges or not the bank can be read when it is empty.
The endpoint must be configured first.
The USBHS_DEVEPTISRx.RXOUTI bit is set at the same time as USBHS_DEVEPTIMRx.FIFOCON when
the current bank is full. This triggers a PEP_x interrupt if the Received OUT Data Interrupt Enable
(USBHS_DEVEPTIMRx.RXOUTE) bit is one.
USBHS_DEVEPTISRx.RXOUTI is cleared by software (by writing a one to the Received OUT Data Interrupt Clear
(USBHS_DEVEPTICRx.RXOUTIC) bit to acknowledge the interrupt, which has no effect on the endpoint FIFO.
The user then reads from the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the OUT
endpoint is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.RXOUTI
and USBHS_DEVEPTIMRx.FIFOCON bits are updated in accordance with the status of the next bank.
USBHS_DEVEPTISRx.RXOUTI is always cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 726
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
The USBHS_DEVEPTISRx.RWALL bit is set when the current bank is not empty, i.e., when the software can read
further data from the FIFO.
Figure 38-14. Example of an OUT Endpoint with one Data Bank
OUT
DATA
(bank 0)
NAK
ACK
DATA
(bank 0)
OUT
ACK
HW
HW
USBHS_DEVEPTISRx.RXOUTI
SW
SW
read data from CPU
BANK 0
USBHS_DEVEPTIMRx.FIFOCON
read data from CPU
BANK 0
SW
Figure 38-15. Example of an OUT Endpoint with two Data Banks
OUT
DATA
(bank 0)
ACK
OUT
DATA
(bank 1)
ACK
HW
USBHS_DEVEPTISRx.RXOUTI
USBHS_DEVEPTIMRx.FIFOCON
HW
SW
SW
read data from CPU
BANK 0
SW
read data from CPU
BANK 1
Detailed Description
The data is read as follows:
•
•
•
•
•
When the bank is full, USBHS_DEVEPTISRx.RXOUTI and USBHS_DEVEPTIMRx.FIFOCON are set, which
triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.
The user acknowledges the interrupt by writing a one to USBHS_DEVEPTICRx.RXOUTIC in order to clear
USBHS_DEVEPTISRx.RXOUTI.
The user can read the byte count of the current bank from USBHS_DEVEPTISRx.BYCT to know how many
bytes to read, rather than polling USBHS_DEVEPTISRx.RWALL.
The user reads the data from the current bank by using the USBFIFOnDATA register, until all the expected
data frame is read or the bank is empty (in which case USBHS_DEVEPTISRx.RWALL is cleared and
USBHS_DEVEPTISRx.BYCT reaches zero).
The user frees the bank and switches to the next bank (if any) by clearing USBHS_DEVEPTIMRx.FIFOCON.
If the endpoint uses several banks, the current one can be read while the following one is being written by the
host. Then, when the user clears USBHS_DEVEPTIMRx.FIFOCON, the following bank can already be read and
USBHS_DEVEPTISRx.RXOUTI is set immediately.
In High-speed mode, the PING and NYET protocols are handled by the USBHS.
•
•
For a single bank, a NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the
current packet is acknowledged but there is no room for the next one.
For a double bank, the USBHS responds to the OUT/DATA transaction with an ACK handshake when the
endpoint accepted the data successfully and has room for another data payload (the second bank is free).
38.6.2.14 Underflow
This error only exists for isochronous IN/OUT endpoints. It sets the Underflow Interrupt
(USBHS_DEVEPTISRx.UNDERFI) bit, which triggers a PEP_x interrupt if the Underflow Interrupt Enable
(USBHS_DEVEPTIMRx.UNDERFE) bit is one.
•
An underflow can occur during the IN stage if the host attempts to read from an empty bank. A zero-length
packet is then automatically sent by the USBHS.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 727
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
•
•
•
An underflow cannot occur during the OUT stage on a CPU action, since the user may only read if the bank is
not empty (USBHS_DEVEPTISRx.RXOUTI = 1 or USBHS_DEVEPTISRx.RWALL = 1).
An underflow can also occur during the OUT stage if the host sends a packet while the bank is already full.
Typically, the CPU is not fast enough. The packet is lost.
An underflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is not
full (USBHS_DEVEPTISRx.TXINI = 1or USBHS_DEVEPTISRx.RWALL = 1).
38.6.2.15 Overflow
This error exists for all endpoint types. It sets the Overflow interrupt (USBHS_DEVEPTISRx.OVERFI) bit, which
triggers a PEP_x interrupt if the Overflow Interrupt Enable (USBHS_DEVEPTIMRx.OVERFE) bit is one.
•
•
An overflow can occur during the OUT stage if the host attempts to write into a bank which is too small for the
packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
An overflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is not
full (USBHS_DEVEPTISRx.TXINI = 1 or USBHS_DEVEPTISRx.RWALL = 1).
38.6.2.16 HB IsoIn Error
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the microframe, if at least one packet has been sent to the host and fewer banks than expected have
been validated (by clearing the USBHS_DEVEPTIMRx.USBHS_DEVEPTIMRx.FIFOCON) for this microframe, it sets
the USBHS_DEVEPTISRx.HBISOINERRORI bit, which triggers a PEP_x interrupt if the High Bandwidth Isochronous
IN Error Interrupt Enable (HBISOINERRORE) bit is one.
For example, if the Number of Transactions per MicroFrame for Isochronous Endpoint (NBTRANS) field in
USBHS_DEVEPTCFGx is three (three transactions per microframe), only two banks are filled by the CPU (three
expected) for the current microframe. Then, the HBISOINERRI interrupt is generated at the end of the microframe.
Note that an UNDERFI interrupt is also generated (with an automatic zero-length-packet), except in the case of a
missing IN token.
38.6.2.17 HB IsoFlush
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the microframe, if at least one packet has been sent to the host and there is a missing IN token during
this microframe, the bank(s) destined to this microframe is/are flushed out to ensure a good data synchronization
between the host and the device.
For example, if NBTRANS is three (three transactions per microframe) and if only the first IN token (among three) is
well received by the USBHS, the last two banks are discarded.
38.6.2.18 CRC Error
This error only exists for isochronous OUT endpoints. It sets the CRC Error Interrupt
(USBHS_DEVEPTISRx.CRCERRI) bit, which triggers a PEP_x interrupt if the CRC Error Interrupt Enable
(USBHS_DEVEPTIMRx.CRCERRE) bit is one.
A CRC error can occur during the OUT stage if the USBHS detects a corrupted received packet. The OUT packet is
stored in the bank as if no CRC error had occurred (USBHS_DEVEPTISRx.RXOUTI is set).
38.6.2.19 Interrupts
See the structure of the USB device interrupt system in Figure 38-3.
There are two kinds of device interrupts: processing, i.e., their generation is part of the normal processing, and
exception, i.e., errors (not related to CPU exceptions).
Global Interrupts
The processing device global interrupts are:
•
•
•
Suspend (USBHS_DEVISR.SUSP)
Start of Frame (USBHS_DEVISR.SOF) interrupt with no frame number CRC error - the Frame Number CRC
Error (USBHS_DEVFNUM.FNCERR) bit is zero.
Micro Start of Frame (USBHS_DEVISR.MSOF) with no CRC error
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 728
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
•
•
•
•
•
•
End of Reset (USBHS_DEVISR.EORST)
Wakeup (USBHS_DEVISR.WAKEUP)
End of Resume (USBHS_DEVISR.EORSM)
Upstream Resume (USBHS_DEVISR.UPRSM)
Endpoint x (USBHS_DEVISR.PEP_x)
DMA Channel x (USBHS_DEVISR.DMA_x)
The exception device global interrupts are:
•
•
Start of Frame (USBHS_DEVISR.SOF) with a frame number CRC error (USBHS_DEVFNUM.FNCERR = 1)
Micro Start of Frame (USBHS_DEVFNUM.FNCERR.MSOF) with a CRC error
Endpoint Interrupts
The processing device endpoint interrupts are:
•
•
•
•
•
•
•
Transmitted IN Data (USBHS_DEVEPTISRx.TXINI)
Received OUT Data (USBHS_DEVEPTISRx.RXOUTI)
Received SETUP (USBHS_DEVEPTISRx.RXSTPI)
Short Packet (USBHS_DEVEPTISRx.SHORTPACKET)
Number of Busy Banks (USBHS_DEVEPTISRx.NBUSYBK)
Received OUT Isochronous Multiple Data (DTSEQ = MDATA & USBHS_DEVEPTISRx.RXOUTI)
Received OUT Isochronous DataX (DTSEQ = DATAX & USBHS_DEVEPTISRx.RXOUTI)
The exception device endpoint interrupts are:
•
•
•
•
•
•
•
•
•
Underflow (USBHS_DEVEPTISRx.UNDERFI)
NAKed OUT (USBHS_DEVEPTISRx.NAKOUTI)
High-Bandwidth Isochronous IN Error (USBHS_DEVEPTISRx.HBISOINERRI)
NAKed IN (USBHS_DEVEPTISRx.NAKINI)
High-Bandwidth Isochronous IN Flush error (USBHS_DEVEPTISRx.HBISOFLUSHI)
Overflow (USBHS_DEVEPTISRx.OVERFI)
STALLed (USBHS_DEVEPTISRx.STALLEDI)
CRC Error (USBHS_DEVEPTISRx.CRCERRI)
Transaction Error (USBHS_DEVEPTISRx.ERRORTRANS)
DMA Interrupts
The processing device DMA interrupts are:
•
•
•
End of USB Transfer Status (USBHS_DEVDMASTATUSx.END_TR_ST)
End of Channel Buffer Status (USBHS_DEVDMASTATUSx.END_BF_ST)
Descriptor Loaded Status (USBHS_DEVDMASTATUSx.DESC_LDST)
There is no exception device DMA interrupt.
38.6.2.20 Test Modes
When written to one, the USBHS_DEVCTRL.TSTPCKT bit switches the USB device controller to a “Test-packet”
mode:
The transceiver repeatedly transmits the packet stored in the current bank. USBHS_DEVCTRL.TSTPCKT must be
written to zero to exit the Test-packet mode. The endpoint is reset by software after a Test-packet mode.
This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic waveform specifications.
The flow control used to send the packets is as follows:
•
•
•
USBHS_DEVCTRL.TSTPCKT = 1;
Store data in an endpoint bank
Write a zero to the USBHS_DEVEPTIDRx.FIFOCON bit
To stop the Test-packet mode, write a zero to the USBHS_DEVCTRL.TSTPCKT bit.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 729
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.6.3
USB Host Operation
38.6.3.1 Description of Pipes
For the USBHS in Host mode, the term “pipe” is used instead of “endpoint” (used in Device mode). A host pipe
corresponds to a device endpoint, as described in Figure 38-16 (from the USB Specification).
Figure 38-16. USB Communication Flow
In Host mode, the USBHS associates a pipe to a device endpoint, considering the device configuration descriptors.
38.6.3.2 Power-On and Reset
The following figure describes the USBHS Host mode main states.
Figure 38-17. Host Mode Main States
Device
Disconnection
Macro off
Clock stopped
Idle
Device
Connection
Device
Disconnection
Ready
SOFE = 0
SOFE = 1
Suspend
After a hardware reset, the USBHS Host mode is in the Reset state.
When the USBHS is enabled (USBHS_CTRL.USBE = 1) in Host mode (USBHS_CTRL.UIMOD = 0), it goes to the
Idle state. In this state, the controller waits for a device connection with a minimal power consumption. The USB pad
should be in the Idle state. Once a device is connected, the USBHS enters the Ready state, which does not require
the USB clock to be activated.
The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when the Host mode does
not generate the “Start of Frame (SOF)”. In this state, the USB consumption is minimal. The Host mode exits the
Suspend state when starting to generate the SOF over the USB line.
38.6.3.3 Device Detection
A device is detected by the USBHS Host mode when D+ or D- is no longer tied low, i.e., when the device D+ or Dpull-up resistor is connected. The bit USBHS_SFR.VBUSRQS must be set to ‘1’ to enable this detection.
Note: The VBUS supply is not managed by the USBHS interface. It must be generated on-board.
The device disconnection is detected by the host controller when both D+ and D- are pulled down.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 730
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.6.3.4 USB Reset
The USBHS sends a USB bus reset when the user writes a one to the Send USB Reset bit in the Host General
Control register (USBHS_HSTCTRL.RESET). The USB Reset Sent Interrupt bit in the Host Global Interrupt Status
register (USBHS_HSTISR.RSTI) is set when the USB reset has been sent. In this case, all pipes are disabled and
de-allocated.
If the bus was previously in a “Suspend” state (the Start of Frame Generation Enable (USBHS_HSTCTRL.SOFE)
bit is zero), the USBHS automatically switches to the “Resume” state, the Host Wakeup Interrupt
(USBHS_HSTISR.HWUPI) bit is set and the USBHS_HSTCTRL.SOFE bit is set in order to generate SOFs or micro
SOFs immediately after the USB reset.
At the end of the reset, the user should check the USBHS_SR.SPEED field to know the speed running according to
the peripheral capability (LS.FS/HS).
38.6.3.5 Pipe Reset
A pipe can be reset at any time by writing a one to the Pipe x Reset (USBHS_HSTPIP.PRSTx) bit. This is
recommended before using a pipe upon hardware reset or when a USB bus reset has been sent. This resets:
•
•
•
the internal state machine of the pipe,
the receive and transmit bank FIFO counters,
all the registers of the pipe (USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), except
its configuration (USBHS_HSTPIPCFGx.ALLOC, USBHS_HSTPIPCFGx.PBK, USBHS_HSTPIPCFGx.PSIZE,
USBHS_HSTPIPCFGx.PTOKEN, USBHS_HSTPIPCFGx.PTYPE, USBHS_HSTPIPCFGx.PEPNUM,
USBHS_HSTPIPCFGx.INTFRQ) and its Data Toggle Sequence field (USBHS_HSTPIPISRx.DTSEQ).
The pipe configuration remains active and the pipe is still enabled.
The pipe reset may be associated with a clear of the data toggle sequence. This can be achieved by setting the
Reset Data Toggle bit in the Pipe x Control register (USBHS_HSTPIPIMRx.RSTDT) (by writing a one to the Reset
Data Toggle Set bit in the Pipe x Control Set register (USBHS_HSTPIPIERx.RSTDTS)).
In the end, the user has to write a zero to the USBHS_HSTPIP.PRSTx bit to complete the reset operation and to start
using the FIFO.
38.6.3.6 Pipe Activation
The pipe is maintained inactive and reset (see "Pipe Reset" for more details) as long as it is disabled
(USBHS_HSTPIP.PENx = 0). The Data Toggle Sequence field (USBHS_HSTPIPISRx.DTSEQ) is also reset.
The algorithm represented in the following figure must be followed to activate a pipe.
Figure 38-18. Pipe Activation Algorithm
Pipe
Activation
USBHS_HSTPIP.PENx = 1
Enable the pipe.
USBHS_HSTPIPPCFGx
Configure the pipe:
- interrupt request frequency
- endpoint number
- type
- size
- number of banks
Allocate the configured DPRAM banks.
.INTFRQ
.PEPNUM
.PTYPE
.PTOKEN
.PSIZE
.PBK
.ALLOC
USBHS_HSTPIPISRx.CFGOK == 1?
No
Test if the pipe configuration is correct.
Yes
Pipe Activated
ERROR
As long as the pipe is not correctly configured (USBHS_HSTPIPISRx.CFGOK = 0), the controller cannot send
packets to the device through this pipe.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 731
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
The USBHS_HSTPIPISRx.CFGOK bit is only set if the configured size and number of banks are correct as compared
to their maximal allowed values for the pipe (see the Description of USB Pipes/Endpoints table) and to the maximal
FIFO size (i.e., the DPRAM size).
See "DPRAM Management" for additional information.
Once the pipe is correctly configured (USBHS_HSTPIPISRx.CFGOK = 1), only the USBHS_HSTPIPCFGx.PTOKEN
and USBHS_HSTPIPCFGx.INTFRQ fields can be written by software. USBHS_HSTPIPCFGx.INTFRQ is
meaningless for non-interrupt pipes.
When starting an enumeration, the user gets the device descriptor by sending a GET_DESCRIPTOR USB request.
This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0) and the
user reconfigures the size of the default control pipe with this size parameter.
38.6.3.7 Address Setup
Once the device has answered the first host requests with the default device address 0, the host assigns a new
address to the device. The host controller has to send a USB reset to the device and to send a SET_ADDRESS
(addr) SETUP request with the new address to be used by the device. Once this SETUP transaction is over, the
user writes the new address into the USB Host Address for Pipe x field in the USB Host Device Address register
(HSTADDR.HSTADDRPx). All the following requests on all pipes are then performed using this new address.
When the host controller sends a USB reset, the HSTADDRPx field is reset by hardware and the following host
requests are performed using the default device address 0.
38.6.3.8 Remote Wakeup
The controller Host mode enters the Suspend state when the USBHS_HSTCTRL.SOFE bit is written to zero. No
more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3 ms later.
The device awakes the host by sending an Upstream Resume (Remote Wakeup feature). When the host controller
detects a non-idle state on the USB bus, it sets the Host Wakeup interrupt (USBHS_HSTISR.HWUPI) bit. If the
non-idle bus state corresponds to an Upstream Resume (K state), the Upstream Resume Received Interrupt
(USBHS_HSTISR.RXRSMI) bit is set. The user has to generate a Downstream Resume within 1 ms and for at
least 20 ms by writing a one to the Send USB Resume (USBHS_HSTCTRL.RESUME) bit. It is mandatory to write
a one to USBHS_HSTCTRL.SOFE before writing a one to USBHS_HSTCTRL.RESUME to enter the Ready state,
otherwise USBHS_HSTCTRL.RESUME has no effect.
38.6.3.9 Management of Control Pipes
A control transaction is composed of three stages:
•
•
•
SETUP
Data (IN or OUT)
Status (OUT or IN)
The user has to change the pipe token according to each stage.
For the control pipe only, each token is assigned a specific initial data toggle sequence:
•
•
•
SETUP: Data0
IN: Data1
OUT: Data1
38.6.3.10 Management of IN Pipes
IN packets are sent by the USB device controller upon IN requests from the host. All data which acknowledges or not
the bank can be read when it is empty.
The pipe must be configured first.
When the host requires data from the device, the user has to first select the IN Request mode with the IN Request
Mode bit in the Pipe x IN Request register (USBHS_HSTPIPINRQx.INMODE):
•
•
When USBHS_HSTPIPINRQx.INMODE = 0, the USBHS performs (INRQ + 1) IN requests before freezing the
pipe.
When USBHS_HSTPIPINRQx.INMODE = 1, the USBHS performs IN requests endlessly when the pipe is not
frozen by the user.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 732
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (USBHS_HSTPIPIMRx.PFREEZE)
field in USBHS_HSTPIPIMRx is zero).
The Received IN Data Interrupt (USBHS_HSTPIPISRx.RXINI) bit is set at the same time as the FIFO Control
(USBHS_HSTPIPIMRx.FIFOCON) bit when the current bank is full. This triggers a PEP_x interrupt if the Received IN
Data Interrupt Enable (USBHS_HSTPIPIMRx.RXINE) bit is one.
USBHS_HSTPIPISRx.RXINI is cleared by software (by writing a one to the Received IN Data Interrupt Clear bit in the
Host Pipe x Clear register (USBHS_HSTPIPIDRx.RXINIC)) to acknowledge the interrupt, which has no effect on the
pipe FIFO.
The user then reads from the FIFO and clears the USBHS_HSTPIPIMRx.FIFOCON bit (by writing a one to the FIFO
Control Clear (USBHS_HSTPIPIDRx.FIFOCONC) bit) to free the bank. If the IN pipe is composed of multiple banks,
this also switches to the next bank. The USBHS_HSTPIPISRx.RXINI and USBHS_HSTPIPIMRx.FIFOCON bits are
updated in accordance with the status of the next bank.
USBHS_HSTPIPISRx.RXINI is always cleared before clearing USBHS_HSTPIPIMRx.FIFOCON.
The Read/Write Allowed (USBHS_HSTPIPISRx.RWALL) bit is set when the current bank is not empty, i.e., when the
software can read further data from the FIFO.
Figure 38-19. Example of an IN Pipe with one Data Bank
IN
DATA
(bank 0)
ACK
DATA
(bank 0)
IN
HW
ACK
HW
SW
USBHS_HSTPIPISRx.RXINI
SW
read data from CPU
BANK 0
USBHS_HSTPIPIMRx.FIFOCON
read data from CPU
BANK 0
SW
Figure 38-20. Example of an IN Pipe with two Data Banks
IN
DATA
(bank 0)
ACK
IN
DATA
(bank 1)
HW
USBHS_HSTPIPISRx.RXINI
USBHS_HSTPIPIMRx.FIFOCON
ACK
HW
SW
SW
read data from CPU
BANK 0
SW
read data from CPU
BANK 1
38.6.3.11 Management of OUT Pipes
OUT packets are sent by the host. All data which acknowledges or not the bank can be written when it is full.
The pipe must be configured and unfrozen first.
The Transmitted OUT Data Interrupt (USBHS_HSTPIPISRx.TXOUTI) bit is set at the same time as
USBHS_HSTPIPIMRx.FIFOCON when the current bank is free. This triggers a PEP_x interrupt if the Transmitted
OUT Data Interrupt Enable (USBHS_HSTPIPIMRx.TXOUTE) bit is one.
USBHS_HSTPIPISRx.TXOUTI is cleared by software (by writing a one to the Transmitted OUT Data Interrupt Clear
(USBHS_HSTPIPIDRx.TXOUTIC) bit to acknowledge the interrupt, which has no effect on the pipe FIFO.
The user then writes into the FIFO and clears the USBHS_HSTPIPIDRx.FIFOCON bit to allow the USBHS
to send the data. If the OUT pipe is composed of multiple banks, this also switches to the next bank. The
USBHS_HSTPIPISRx.TXOUTI and USBHS_HSTPIPIMRx.FIFOCON bits are updated in accordance with the status
of the next bank.
USBHS_HSTPIPISRx.TXOUTI is always cleared before clearing USBHS_HSTPIPIMRx.FIFOCON.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 733
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
The USBHS_HSTPIPISRx.RWALL bit is set when the current bank is not full, i.e., when the software can write further
data into the FIFO.
Notes:
1. If the user decides to switch to the Suspend state (by writing a zero to the USBHS_HSTCTRL.SOFE bit) while
a bank is ready to be sent, the USBHS automatically exits this state and the bank is sent.
2. In High-speed operating mode, the host controller automatically manages the PING protocol to maximize the
USB bandwidth. The user can tune the PING protocol by handling the Ping Enable (PINGEN) bit and the
bInterval Parameter for the Bulk-Out/Ping Transaction (BINTERVAL) field in USBHS_HSTPIPCFGx. See the
Host Pipe x Configuration Register for additional information.
Figure 38-21. Example of an OUT Pipe with one Data Bank
DATA
(bank 0)
OUT
ACK
OUT
HW
USBHS_HSTPIPISRx.TXOUTI
SW
SW
write data to CPU
BANK 0
USBHS_HSTPIPIMRx.FIFOCON
write data to CPU
BANK 0
SW
SW
Figure 38-22. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
OUT
DATA
(bank 0)
ACK
OUT
DATA
(bank 1)
ACK
HW
SW
USBHS_HSTPIPISRx.TXOUTI
SW
write data to CPU SW
BANK 0
USBHS_HSTPIPIMRx.FIFOCON
SW
write data to CPU
BANK 1
write data to CPU
BANK0
SW
Figure 38-23. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
OUT
DATA
(bank 0)
ACK
OUT
DATA
(bank 1)
ACK
HW
USBHS_HSTPIPISRx.TXOUTI
USBHS_HSTPIPIMRx.FIFOCON
SW
SW
write data to CPU
BANK 0
SW
SW
write data to CPU
BANK 1
SW
write data to CPU
BANK0
38.6.3.12 CRC Error
This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt (USBHS_HSTPIPISRx.CRCERRI) bit,
which triggers a PEP_x interrupt if then the CRC Error Interrupt Enable (USBHS_HSTPIPIMRx.CRCERRE) bit is
one.
A CRC error can occur during IN stage if the USBHS detects a corrupted received packet. The IN packet is stored in
the bank as if no CRC error had occurred (USBHS_HSTPIPISRx.RXINI is set).
38.6.3.13 Interrupts
See the structure of the USB host interrupt system on Figure 38-3.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 734
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
There are two kinds of host interrupts: processing, i.e., their generation is part of the normal processing, and
exception, i.e., errors (not related to CPU exceptions).
Global Interrupts
The processing host global interrupts are:
•
•
•
•
•
•
•
•
•
Device Connection (USBHS_HSTISR.DCONNI)
Device Disconnection (USBHS_HSTISR.DDISCI)
USB Reset Sent (USBHS_HSTISR.RSTI)
Downstream Resume Sent (USBHS_HSTISR.RSMEDI)
Upstream Resume Received (USBHS_HSTISR.RXRSMI)
Host Start of Frame (USBHS_HSTISR.HSOFI)
Host Wakeup (USBHS_HSTISR.HWUPI)
Pipe x (USBHS_HSTISR.PEP_x)
DMA Channel x (USBHS_HSTISR.DMAxINT)
There is no exception host global interrupt.
Pipe Interrupts
The processing host pipe interrupts are:
•
•
•
•
•
Received IN Data (USBHS_HSTPIPISRx.RXINI)
Transmitted OUT Data (USBHS_HSTPIPISRx.TXOUTI)
Transmitted SETUP (USBHS_HSTPIPISRx.TXSTPI)
Short Packet (USBHS_HSTPIPISRx.SHORTPACKETI)
Number of Busy Banks (USBHS_HSTPIPISRx.NBUSYBK)
The exception host pipe interrupts are:
•
•
•
•
•
•
Underflow (USBHS_HSTPIPISRx.UNDERFI)
Pipe Error (USBHS_HSTPIPISRx.PERRI)
NAKed (USBHS_HSTPIPISRx.NAKEDI)
Overflow (USBHS_HSTPIPISRx.OVERFI)
Received STALLed (USBHS_HSTPIPISRx.RXSTALLDI)
CRC Error (USBHS_HSTPIPISRx.CRCERRI)
DMA Interrupts
The processing host DMA interrupts are:
•
•
•
The End of USB Transfer Status (USBHS_HSTDMASTATUSx.END_TR_ST)
The End of Channel Buffer Status (USBHS_HSTDMASTATUSx.END_BF_ST)
The Descriptor Loaded Status (USBHS_HSTDMASTATUSx.DESC_LDST)
There is no exception host DMA interrupt.
38.6.4
USB DMA Operation
USB packets of any length may be transferred when required by the USBHS. These transfers always feature
sequential addressing. Such characteristics mean that in case of high USBHS throughput, both AHB ports benefit
from “incrementing burst of unspecified length” since the average access latency of AHB Clients can then be
reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data transfers and channel
descriptor loading. A burst may last on the AHB busses for the duration of a whole USB packet transfer, unless
otherwise broken by the AHB arbitration or the AHB 1-Kbyte boundary crossing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance
boost with paged memories. This prevents large AHB bursts from being broken in case of conflict with other
AHB bus Hosts, thus avoiding access latencies due to memory row changes. This means up to 128 words
single cycle unbroken AHB bursts for bulk pipes/endpoints and 256 words single cycle unbroken bursts for
isochronous pipes/endpoints. This maximal burst length is then controlled by the lowest programmed USB
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 735
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Pipe/Endpoint Size (USBHS_HSTPIPCFGx.PSIZE / USBHS_DEVEPTCFGx.EPSIZE) and the Buffer Byte Length
(USBHS_HSTDMACONTROLx.BUFF_LENGTH / USBHS_DEVDMACONTROLx.BUFF_LENGTH) fields.
The USBHS average throughput can reach nearly 480 Mbps. Its average access latency decreases as burst length
increases due to the zero wait-state side effect of unchanged pipe/endpoint. Word access allows reducing the AHB
bandwidth required for the USB by four, as compared to native byte access. If at least 0 wait-state word burst
capability is also provided by the other DMA AHB bus Clients, each DMA AHB bus needs less than 60% bandwidth
allocation for full USB bandwidth usage at 33 MHz, and less than 30% at 66 MHz.
Figure 38-24. Example of a DMA Chained List
Transfer Descriptor
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
Next Descriptor Address
AHB Address
Transfer Descriptor
Control
Next Descriptor Address
AHB Address
Control
AHB Address
Transfer Descriptor
Control
Next Descriptor Address
AHB Address
Status
Control
NULL
Memory Area
Data Buffer 1
Data Buffer 2
Data Buffer 3
38.6.5
USB DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory. The following structures apply:
Offset 0:
•
•
The address must be aligned: 0xXXXX0
Next Descriptor Address Register: USBHS_xxxDMANXTDSCx
Offset 4:
•
•
The address must be aligned: 0xXXXX4
DMA Channelx Address Register: USBHS_xxxDMAADDRESSx
Offset 8:
•
•
The address must be aligned: 0xXXXX8
DMA Channelx Control Register: USBHS_xxxDMACONTROLx
To use the DMA channel transfer descriptor, fill the structures with the correct values (as described in the following
pages), then write directly in USBHS_xxxDMANXTDSCx the address of the descriptor to be used first.
Then write 1 in the USBHS_xxxDMACONTROLx.LDNXT_DSC bit (load next channel transfer descriptor). The
descriptor is automatically loaded upon pipe x / endpoint x request for packet transfer.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 736
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7
Register Summary
Offset
Name
0x00
USBHS_DEVCTRL
0x04
0x08
0x0C
0x10
0x14
0x18
Bit Pos.
7
6
5
4
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
ADDEN
TSTPCKT
TSTK
TSTJ
LS
UPRSM
PEP_2
DMA_5
UPRSMC
EORSM
PEP_1
PEP_9
DMA_4
EORSMC
WAKEUP
PEP_0
PEP_8
DMA_3
WAKEUPC
EORST
PEP_3
UPRSMS
EORSMS
DMA_5
UPRSME
PEP_2
USBHS_DEVISR
USBHS_DEVICR
USBHS_DEVIFR
USBHS_DEVIMR
USBHS_DEVIDR
USBHS_DEVIER
0x1C
USBHS_DEVEPT
0x20
USBHS_DEVFNUM
0x24
...
0xFF
Reserved
0x0100
USBHS_DEVEPTC
FG0
0x0104
USBHS_DEVEPTC
FG1
0x0108
USBHS_DEVEPTC
FG2
0x010C
USBHS_DEVEPTC
FG3
DMA_6
DMA_6
PEP_3
DMA_5
UPRSMES
PEP_2
DMA_6
EPEN7
DMA_5
EPEN6
DMA_4
EORSME
PEP_1
PEP_9
DMA_4
EORSMEC
PEP_1
PEP_9
DMA_4
EORSMES
PEP_1
PEP_9
DMA_4
EPEN5
EPRST7
EPRST6
EPRST5
PEP_3
DMA_6
PEP_3
DMA_6
1
0
2
RMWKUP
DETACH
OPMODE2
SOF
MSOF
SUSP
PEP_7
DMA_2
EORSTC
PEP_6
DMA_1
SOFC
PEP_5
DMA_0
MSOFC
PEP_4
SUSPC
WAKEUPS
EORSTS
SOFS
MSOFS
SUSPS
DMA_3
WAKEUPE
PEP_0
PEP_8
DMA_3
WAKEUPEC
PEP_0
PEP_8
DMA_3
WAKEUPES
PEP_0
PEP_8
DMA_3
EPEN4
DMA_2
EORSTE
DMA_1
SOFE
DMA_0
MSOFE
SUSPE
PEP_7
DMA_2
EORSTEC
PEP_6
DMA_1
SOFEC
PEP_5
DMA_0
MSOFEC
PEP_7
DMA_2
EORSTES
PEP_6
DMA_1
SOFES
PEP_5
DMA_0
MSOFES
PEP_7
DMA_2
EPEN3
PEP_6
DMA_1
EPEN2
EPRST4
EPRST3
EPRST2
PEP_5
DMA_0
EPEN1
EPEN9
EPRST1
EPRST9
MFNUM[2:0]
UADD[6:0]
SPDCONF[1:0]
FNUM[4:0]
FNCERR
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
DMA_5
UPRSMEC
PEP_2
3
PEP_4
SUSPEC
PEP_4
SUSPES
PEP_4
EPEN0
EPEN8
EPRST0
EPRST8
FNUM[10:5]
EPSIZE[2:0]
NBTRANS[1:0]
EPTYPE[1:0]
EPBK[1:0]
EPSIZE[2:0]
NBTRANS[1:0]
EPTYPE[1:0]
EPSIZE[2:0]
NBTRANS[1:0]
EPTYPE[1:0]
EPSIZE[2:0]
NBTRANS[1:0]
EPTYPE[1:0]
EPBK[1:0]
EPBK[1:0]
EPBK[1:0]
Complete Data Sheet
ALLOC
AUTOSW
EPDIR
ALLOC
AUTOSW
EPDIR
ALLOC
AUTOSW
EPDIR
ALLOC
AUTOSW
EPDIR
DS60001527G-page 737
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0110
USBHS_DEVEPTC
FG4
0x0114
USBHS_DEVEPTC
FG5
0x0118
USBHS_DEVEPTC
FG6
0x011C
USBHS_DEVEPTC
FG7
0x0120
USBHS_DEVEPTC
FG8
0x0124
...
0x012F
Reserved
Bit Pos.
0x0130
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
15:8
23:16
31:24
7:0
0x0130
USBHS_DEVEPTIS
R0 (ISOENPT)
6
7:0
15:8
7:0
USBHS_DEVEPTIS
R0
7
SHORTPACK
ET
0x0134
15:8
23:16
31:24
7:0
0x0134
USBHS_DEVEPTIS
R1 (ISOENPT)
0x0138
15:8
23:16
31:24
7:0
0x0138
USBHS_DEVEPTIS
R2 (ISOENPT)
EPTYPE[1:0]
EPSIZE[2:0]
NBTRANS[1:0]
EPTYPE[1:0]
EPSIZE[2:0]
NBTRANS[1:0]
EPTYPE[1:0]
EPSIZE[2:0]
NBTRANS[1:0]
EPTYPE[1:0]
OVERFI
1
0
ALLOC
AUTOSW
EPDIR
ALLOC
AUTOSW
EPDIR
ALLOC
AUTOSW
EPDIR
ALLOC
AUTOSW
EPDIR
ALLOC
AUTOSW
EPDIR
RXSTPI
RXOUTI
TXINI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
EPBK[1:0]
EPBK[1:0]
EPBK[1:0]
EPBK[1:0]
EPBK[1:0]
NAKOUTI
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
UNDERFI
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
RXOUTI
TXINI
DTSEQ[1:0]
RWALL
BYCT[10:4]
SHORTPACK
STALLEDI
OVERFI
NAKINI
ET
CURRBK[1:0]
NBUSYBK[1:0]
BYCT[3:0]
NAKOUTI
RXSTPI
RXOUTI
TXINI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
BYCT[10:4]
SHORTPACK
ET
CRCERRI
OVERFI
CURRBK[1:0]
HBISOFLUSH
HBISOINERRI
I
UNDERFI
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
BYCT[3:0]
RXOUTI
TXINI
DTSEQ[1:0]
RWALL
BYCT[10:4]
SHORTPACK
STALLEDI
OVERFI
NAKINI
ET
CURRBK[1:0]
NBUSYBK[1:0]
BYCT[3:0]
SHORTPACK
ET
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
EPSIZE[2:0]
NBTRANS[1:0]
2
BYCT[3:0]
23:16
31:24
USBHS_DEVEPTIS
R2
EPTYPE[1:0]
CURRBK[1:0]
15:8
7:0
3
EPSIZE[2:0]
NBTRANS[1:0]
CRCERRI
23:16
31:24
USBHS_DEVEPTIS
R1
4
SHORTPACK
STALLEDI
OVERFI
NAKINI
ET
CURRBK[1:0]
NBUSYBK[1:0]
BYCT[3:0]
15:8
7:0
5
CRCERRI
OVERFI
CURRBK[1:0]
NAKOUTI
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
RXSTPI
RXOUTI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
UNDERFI
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
BYCT[3:0]
RXOUTI
TXINI
TXINI
DTSEQ[1:0]
RWALL
BYCT[10:4]
Complete Data Sheet
DS60001527G-page 738
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x013C
USBHS_DEVEPTIS
R3
Bit Pos.
7
6
5
4
3
2
1
0
7:0
SHORTPACK
ET
STALLEDI
OVERFI
NAKINI
NAKOUTI
RXSTPI
RXOUTI
TXINI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
15:8
23:16
31:24
7:0
0x013C
USBHS_DEVEPTIS
R3 (ISOENPT)
CURRBK[1:0]
SHORTPACK
ET
15:8
CRCERRI
0x0140
USBHS_DEVEPTIS
R4
15:8
23:16
31:24
7:0
0x0140
USBHS_DEVEPTIS
R4 (ISOENPT)
0x0144
15:8
23:16
31:24
7:0
0x0144
USBHS_DEVEPTIS
R5 (ISOENPT)
SHORTPACK
ET
CRCERRI
0x0148
15:8
23:16
31:24
7:0
0x0148
USBHS_DEVEPTIS
R6 (ISOENPT)
0x014C
15:8
23:16
31:24
7:0
0x014C
USBHS_DEVEPTIS
R7 (ISOENPT)
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
TXINI
DTSEQ[1:0]
RWALL
RXSTPI
RXOUTI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
UNDERFI
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
SHORTPACK
STALLEDI
OVERFI
NAKINI
ET
CURRBK[1:0]
NBUSYBK[1:0]
BYCT[3:0]
SHORTPACK
ET
CRCERRI
OVERFI
CURRBK[1:0]
NAKOUTI
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
RXOUTI
TXINI
TXINI
DTSEQ[1:0]
RWALL
RXSTPI
RXOUTI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
UNDERFI
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
BYCT[3:0]
RXOUTI
TXINI
TXINI
DTSEQ[1:0]
RWALL
BYCT[10:4]
SHORTPACK
STALLEDI
OVERFI
NAKINI
ET
CURRBK[1:0]
NBUSYBK[1:0]
BYCT[3:0]
SHORTPACK
ET
CRCERRI
OVERFI
CURRBK[1:0]
NAKOUTI
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
RXSTPI
RXOUTI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
UNDERFI
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
BYCT[3:0]
RXOUTI
TXINI
TXINI
DTSEQ[1:0]
RWALL
BYCT[10:4]
SHORTPACK
STALLEDI
OVERFI
NAKINI
ET
CURRBK[1:0]
NBUSYBK[1:0]
BYCT[3:0]
SHORTPACK
ET
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
RXOUTI
BYCT[10:4]
15:8
7:0
NAKOUTI
BYCT[3:0]
23:16
31:24
USBHS_DEVEPTIS
R7
OVERFI
CURRBK[1:0]
23:16
31:24
USBHS_DEVEPTIS
R6
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
SHORTPACK
STALLEDI
OVERFI
NAKINI
ET
CURRBK[1:0]
NBUSYBK[1:0]
BYCT[3:0]
15:8
7:0
UNDERFI
BYCT[10:4]
15:8
7:0
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
BYCT[3:0]
23:16
31:24
USBHS_DEVEPTIS
R5
OVERFI
CURRBK[1:0]
23:16
31:24
7:0
NBUSYBK[1:0]
BYCT[3:0]
CRCERRI
OVERFI
CURRBK[1:0]
NAKOUTI
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
RXSTPI
RXOUTI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
UNDERFI
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
BYCT[3:0]
RXOUTI
TXINI
TXINI
DTSEQ[1:0]
RWALL
BYCT[10:4]
Complete Data Sheet
DS60001527G-page 739
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0150
USBHS_DEVEPTIS
R8
Bit Pos.
7
6
5
4
3
2
1
0
7:0
SHORTPACK
ET
STALLEDI
OVERFI
NAKINI
NAKOUTI
RXSTPI
RXOUTI
TXINI
CFGOK
DTSEQ[1:0]
CTRLDIR
RWALL
15:8
23:16
31:24
7:0
0x0150
USBHS_DEVEPTIS
R8 (ISOENPT)
CURRBK[1:0]
SHORTPACK
ET
15:8
USBHS_DEVEPTIC
R0
USBHS_DEVEPTIC
R0 (ISOENPT)
USBHS_DEVEPTIC
R1
USBHS_DEVEPTIC
R1 (ISOENPT)
USBHS_DEVEPTIC
R2
USBHS_DEVEPTIC
R2 (ISOENPT)
USBHS_DEVEPTIC
R3
0x016C
0x0170
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
NAKOUTIC
RXSTPIC
RXOUTIC
TXINIC
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
RXOUTIC
TXINIC
NAKINIC
NAKOUTIC
RXSTPIC
RXOUTIC
TXINIC
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
RXOUTIC
TXINIC
NAKINIC
NAKOUTIC
RXSTPIC
RXOUTIC
TXINIC
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
RXOUTIC
TXINIC
NAKINIC
NAKOUTIC
RXSTPIC
RXOUTIC
TXINIC
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
RXOUTIC
TXINIC
NAKINIC
NAKOUTIC
RXSTPIC
RXOUTIC
TXINIC
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
NAKINIC
15:8
23:16
31:24
7:0
USBHS_DEVEPTIC
R4
OVERFIC
15:8
23:16
31:24
7:0
USBHS_DEVEPTIC
R3 (ISOENPT)
SHORTPACK
STALLEDIC
ETC
15:8
23:16
31:24
7:0
0x016C
RWALL
BYCT[10:4]
15:8
23:16
31:24
7:0
0x0168
DTSEQ[1:0]
15:8
23:16
31:24
7:0
0x0168
BYCT[3:0]
TXINI
15:8
23:16
31:24
7:0
0x0164
ERRORTRAN
S
CFGOK
NBUSYBK[1:0]
RXOUTI
15:8
23:16
31:24
7:0
0x0164
UNDERFI
15:8
23:16
31:24
7:0
0x0160
OVERFI
BYCT[10:4]
HBISOFLUSH
HBISOINERRI
I
Reserved
7:0
0x0160
CRCERRI
CURRBK[1:0]
23:16
31:24
0x0154
...
0x015F
NBUSYBK[1:0]
BYCT[3:0]
Complete Data Sheet
DS60001527G-page 740
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0170
USBHS_DEVEPTIC
R4 (ISOENPT)
0x0174
USBHS_DEVEPTIC
R5
0x0174
USBHS_DEVEPTIC
R5 (ISOENPT)
0x0178
USBHS_DEVEPTIC
R6
0x0178
USBHS_DEVEPTIC
R6 (ISOENPT)
0x017C
USBHS_DEVEPTIC
R7
0x017C
USBHS_DEVEPTIC
R7 (ISOENPT)
0x0180
USBHS_DEVEPTIC
R8
0x0180
USBHS_DEVEPTIC
R8 (ISOENPT)
0x0184
...
0x018F
Reserved
Bit Pos.
7:0
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIC
ETC
OVERFIC
SHORTPACK
CRCERRIC
ETC
OVERFIC
SHORTPACK
STALLEDIS
ETS
OVERFIS
2
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
1
0
RXOUTIC
TXINIC
NAKINIC
NAKOUTIC
RXSTPIC
RXOUTIC
TXINIC
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
RXOUTIC
TXINIC
NAKINIC
NAKOUTIC
RXSTPIC
RXOUTIC
TXINIC
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
RXOUTIC
TXINIC
RXOUTIC
TXINIC
RXOUTIC
TXINIC
RXOUTIC
TXINIC
RXOUTIC
TXINIC
RXOUTIS
TXINIS
RXOUTIS
TXINIS
15:8
23:16
31:24
7:0
NAKINIC
NAKOUTIC
RXSTPIC
15:8
23:16
31:24
7:0
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
15:8
23:16
31:24
7:0
NAKINIC
NAKOUTIC
RXSTPIC
15:8
23:16
31:24
7:0
HBISOFLUSH HBISOINERRI
UNDERFIC
IC
C
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
NAKINIS
NAKOUTIS
RXSTPIS
NBUSYBKS
SHORTPACK
CRCERRIS
ETS
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
3
15:8
23:16
31:24
7:0
0x0190
SHORTPACK
CRCERRIC
ETC
4
15:8
23:16
31:24
7:0
USBHS_DEVEPTIF
R0 (ISOENPT)
5
15:8
23:16
31:24
7:0
0x0190
6
15:8
23:16
31:24
7:0
USBHS_DEVEPTIF
R0
7
OVERFIS
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
Complete Data Sheet
DS60001527G-page 741
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0194
USBHS_DEVEPTIF
R1
0x0194
USBHS_DEVEPTIF
R1 (ISOENPT)
0x0198
USBHS_DEVEPTIF
R2
0x0198
USBHS_DEVEPTIF
R2 (ISOENPT)
0x019C
USBHS_DEVEPTIF
R3
0x019C
USBHS_DEVEPTIF
R3 (ISOENPT)
0x01A0
USBHS_DEVEPTIF
R4
0x01A0
USBHS_DEVEPTIF
R4 (ISOENPT)
0x01A4
USBHS_DEVEPTIF
R5
0x01A4
USBHS_DEVEPTIF
R5 (ISOENPT)
0x01A8
USBHS_DEVEPTIF
R6
Bit Pos.
7:0
7
SHORTPACK
STALLEDIS
ETS
5
4
3
2
1
0
OVERFIS
NAKINIS
NAKOUTIS
RXSTPIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
15:8
23:16
31:24
7:0
NBUSYBKS
SHORTPACK
CRCERRIS
ETS
OVERFIS
SHORTPACK
STALLEDIS
ETS
OVERFIS
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
SHORTPACK
CRCERRIS
ETS
OVERFIS
SHORTPACK
STALLEDIS
ETS
OVERFIS
15:8
23:16
31:24
7:0
SHORTPACK
CRCERRIS
ETS
OVERFIS
SHORTPACK
STALLEDIS
ETS
OVERFIS
15:8
23:16
31:24
7:0
SHORTPACK
CRCERRIS
ETS
OVERFIS
SHORTPACK
STALLEDIS
ETS
OVERFIS
15:8
23:16
31:24
7:0
RXSTPIS
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
NAKINIS
NAKOUTIS
RXSTPIS
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
NAKINIS
NAKOUTIS
RXSTPIS
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
NAKINIS
NAKOUTIS
RXSTPIS
NBUSYBKS
SHORTPACK
CRCERRIS
ETS
OVERFIS
SHORTPACK
STALLEDIS
ETS
OVERFIS
15:8
23:16
31:24
7:0
NAKOUTIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKINIS
NBUSYBKS
15:8
23:16
31:24
7:0
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
NBUSYBKS
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
6
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
NAKINIS
NAKOUTIS
RXSTPIS
NBUSYBKS
Complete Data Sheet
DS60001527G-page 742
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x01A8
USBHS_DEVEPTIF
R6 (ISOENPT)
0x01AC
USBHS_DEVEPTIF
R7
0x01AC
USBHS_DEVEPTIF
R7 (ISOENPT)
0x01B0
USBHS_DEVEPTIF
R8
0x01B0
USBHS_DEVEPTIF
R8 (ISOENPT)
0x01B4
...
0x01BF
Reserved
Bit Pos.
7:0
SHORTPACK
STALLEDIS
ETS
OVERFIS
SHORTPACK
CRCERRIS
ETS
OVERFIS
SHORTPACK
STALLEDIS
ETS
OVERFIS
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NAKINIS
NAKOUTIS
NAKINIS
NAKOUTIS
OVERFIS
0x01C4
SHORTPACK
ETE
STALLEDE
OVERFE
NAKINE
FIFOCON
KILLBK
NBUSYBKE
SHORTPACK
ETE
0x01C4
USBHS_DEVEPTIM
R1 (ISOENPT)
SHORTPACK
ETE
15:8
23:16
31:24
7:0
SHORTPACK
ETE
15:8
0x01C8
USBHS_DEVEPTIM
R2
SHORTPACK
ETE
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
1
0
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
RXOUTIS
TXINIS
CRCERRE
OVERFE
FIFOCON
KILLBK
NAKOUTE
RXSTPE
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
UNDERFE
RXOUTE
TXINE
HBISOFLUSH HBISOINERR
E
E
ERRORTRAN
SE
RSTDT
NBUSYBKE
STALLEDE
OVERFE
NAKINE
FIFOCON
KILLBK
NBUSYBKE
CRCERRE
OVERFE
FIFOCON
KILLBK
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
UNDERFE
RXOUTE
TXINE
DATAXE
MDATAE
ERRORTRAN
SE
RSTDT
NBUSYBKE
OVERFE
NAKINE
FIFOCON
KILLBK
NBUSYBKE
MDATAE
EPDISHDMA
RXSTPE
HBISOFLUSH HBISOINERR
E
E
STALLEDE
DATAXE
NAKOUTE
23:16
31:24
7:0
RXSTPIS
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
23:16
31:24
USBHS_DEVEPTIM
R1
RXSTPIS
HBISOFLUSH HBISOINERRI
UNDERFIS
IS
S
NBUSYBKS
SHORTPACK
CRCERRIS
ETS
15:8
7:0
2
NBUSYBKS
15:8
23:16
31:24
7:0
3
NBUSYBKS
15:8
23:16
31:24
7:0
4
NBUSYBKS
15:8
23:16
31:24
7:0
USBHS_DEVEPTIM
R0 (ISOENPT)
OVERFIS
15:8
23:16
31:24
7:0
0x01C0
SHORTPACK
CRCERRIS
ETS
5
15:8
23:16
31:24
7:0
0x01C0
6
15:8
23:16
31:24
7:0
USBHS_DEVEPTIM
R0
7
EPDISHDMA
NAKOUTE
RXSTPE
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
Complete Data Sheet
DS60001527G-page 743
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
0x01C8
Name
Bit Pos.
7
6
5
7:0
SHORTPACK
ETE
CRCERRE
OVERFE
FIFOCON
KILLBK
USBHS_DEVEPTIM
R2 (ISOENPT)
15:8
4
3
HBISOFLUSH HBISOINERR
E
E
USBHS_DEVEPTIM
0x01CC
R3
15:8
23:16
31:24
7:0
0x01CC
USBHS_DEVEPTIM
R3 (ISOENPT)
SHORTPACK
ETE
SHORTPACK
ETE
15:8
STALLEDE
OVERFE
NAKINE
FIFOCON
KILLBK
NBUSYBKE
CRCERRE
OVERFE
FIFOCON
KILLBK
7:0
0x01D0
15:8
23:16
31:24
7:0
0x01D0
USBHS_DEVEPTIM
R4 (ISOENPT)
SHORTPACK
ETE
SHORTPACK
ETE
15:8
NAKINE
FIFOCON
KILLBK
NBUSYBKE
CRCERRE
OVERFE
FIFOCON
KILLBK
0x01D4
USBHS_DEVEPTIM
R5
15:8
23:16
31:24
7:0
0x01D4
USBHS_DEVEPTIM
R5 (ISOENPT)
SHORTPACK
ETE
SHORTPACK
ETE
15:8
NAKINE
FIFOCON
KILLBK
NBUSYBKE
CRCERRE
OVERFE
FIFOCON
KILLBK
7:0
0x01D8
15:8
23:16
31:24
7:0
0x01D8
USBHS_DEVEPTIM
R6 (ISOENPT)
SHORTPACK
ETE
EPDISHDMA
UNDERFE
RXOUTE
TXINE
DATAXE
MDATAE
ERRORTRAN
SE
RSTDT
RXSTPE
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
UNDERFE
RXOUTE
TXINE
DATAXE
MDATAE
ERRORTRAN
SE
RSTDT
SHORTPACK
ETE
15:8
NAKINE
FIFOCON
KILLBK
NBUSYBKE
CRCERRE
OVERFE
FIFOCON
KILLBK
RXSTPE
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
UNDERFE
RXOUTE
TXINE
DATAXE
MDATAE
ERRORTRAN
SE
RSTDT
USBHS_DEVEPTIM
0x01DC
R7
SHORTPACK
ETE
RXSTPE
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
UNDERFE
RXOUTE
TXINE
DATAXE
MDATAE
HBISOFLUSH HBISOINERR
E
E
ERRORTRAN
SE
RSTDT
NBUSYBKE
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
STALLEDE
OVERFE
NAKINE
FIFOCON
KILLBK
NBUSYBKE
EPDISHDMA
NAKOUTE
23:16
31:24
7:0
EPDISHDMA
NAKOUTE
NBUSYBKE
OVERFE
EPDISHDMA
NAKOUTE
HBISOFLUSH HBISOINERR
E
E
STALLEDE
EPDISHDMA
NYETDIS
23:16
31:24
USBHS_DEVEPTIM
R6
MDATAE
RSTDT
NBUSYBKE
OVERFE
DATAXE
STALLRQ
HBISOFLUSH HBISOINERR
E
E
STALLEDE
TXINE
TXINE
23:16
31:24
7:0
RXOUTE
RXOUTE
NBUSYBKE
OVERFE
UNDERFE
RXSTPE
HBISOFLUSH HBISOINERR
E
E
STALLEDE
0
NAKOUTE
23:16
31:24
USBHS_DEVEPTIM
R4
1
ERRORTRAN
SE
RSTDT
NBUSYBKE
23:16
31:24
7:0
2
EPDISHDMA
NAKOUTE
RXSTPE
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
Complete Data Sheet
DS60001527G-page 744
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
0x01DC
Name
Bit Pos.
7
6
5
7:0
SHORTPACK
ETE
CRCERRE
OVERFE
FIFOCON
KILLBK
USBHS_DEVEPTIM
R7 (ISOENPT)
15:8
4
3
HBISOFLUSH HBISOINERR
E
E
0x01E0
USBHS_DEVEPTIM
R8
15:8
23:16
31:24
7:0
0x01E0
USBHS_DEVEPTIM
R8 (ISOENPT)
SHORTPACK
ETE
SHORTPACK
ETE
15:8
STALLEDE
OVERFE
NAKINE
FIFOCON
KILLBK
NBUSYBKE
CRCERRE
OVERFE
FIFOCON
KILLBK
UNDERFE
RXOUTE
TXINE
DATAXE
MDATAE
EPDISHDMA
RXSTPE
RXOUTE
TXINE
STALLRQ
RSTDT
NYETDIS
EPDISHDMA
UNDERFE
RXOUTE
TXINE
DATAXE
MDATAE
HBISOFLUSH HBISOINERR
E
E
ERRORTRAN
SE
RSTDT
NBUSYBKE
EPDISHDMA
Reserved
7:0
0x01F0
0
NAKOUTE
23:16
31:24
0x01E4
...
0x01EF
1
ERRORTRAN
SE
RSTDT
NBUSYBKE
23:16
31:24
7:0
2
USBHS_DEVEPTIE
R0
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
OVERFES
NAKINES
KILLBKS
NBUSYBKES
23:16
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
DATAXES
MDATAES
31:24
0x01F0
USBHS_DEVEPTIE
R0 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
EPDISHDMA
S
RSTDTS
31:24
7:0
0x01F4
USBHS_DEVEPTIE
R1
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
OVERFES
NAKINES
KILLBKS
NBUSYBKES
23:16
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
31:24
0x01F4
USBHS_DEVEPTIE
R1 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
DATAXES
MDATAES
EPDISHDMA
S
RSTDTS
31:24
7:0
0x01F8
USBHS_DEVEPTIE
R2
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
OVERFES
NAKINES
KILLBKS
NBUSYBKES
23:16
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
DATAXES
MDATAES
31:24
0x01F8
USBHS_DEVEPTIE
R2 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
RSTDTS
EPDISHDMA
S
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 745
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
0x01FC
Name
Bit Pos.
USBHS_DEVEPTIE
R3
7
6
7:0
SHORTPACK
STALLEDES
ETES
15:8
FIFOCONS
5
4
3
2
1
0
OVERFES
NAKINES
NAKOUTES
RXSTPES
RXOUTES
TXINES
KILLBKS
NBUSYBKES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
DATAXES
MDATAES
23:16
31:24
0x01FC
USBHS_DEVEPTIE
R3 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
EPDISHDMA
S
RSTDTS
31:24
7:0
0x0200
USBHS_DEVEPTIE
R4
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
OVERFES
NAKINES
KILLBKS
NBUSYBKES
23:16
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
DATAXES
MDATAES
31:24
0x0200
USBHS_DEVEPTIE
R4 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
EPDISHDMA
S
RSTDTS
31:24
7:0
0x0204
USBHS_DEVEPTIE
R5
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
OVERFES
NAKINES
KILLBKS
NBUSYBKES
23:16
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
DATAXES
MDATAES
31:24
0x0204
USBHS_DEVEPTIE
R5 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
EPDISHDMA
S
RSTDTS
31:24
7:0
0x0208
USBHS_DEVEPTIE
R6
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
OVERFES
NAKINES
KILLBKS
NBUSYBKES
23:16
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
DATAXES
MDATAES
31:24
0x0208
USBHS_DEVEPTIE
R6 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
EPDISHDMA
S
RSTDTS
31:24
7:0
0x020C
USBHS_DEVEPTIE
R7
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
23:16
OVERFES
NAKINES
KILLBKS
NBUSYBKES
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 746
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
0x020C
Name
Bit Pos.
USBHS_DEVEPTIE
R7 (ISOENPT)
7
6
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
5
OVERFES
KILLBKS
4
3
2
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
SES
NBUSYBKES
23:16
1
0
RXOUTES
TXINES
DATAXES
MDATAES
EPDISHDMA
S
RSTDTS
31:24
7:0
0x0210
USBHS_DEVEPTIE
R8
15:8
SHORTPACK
STALLEDES
ETES
FIFOCONS
OVERFES
NAKINES
KILLBKS
NBUSYBKES
23:16
NAKOUTES
RXSTPES
RXOUTES
TXINES
STALLRQS
RSTDTS
NYETDISS
EPDISHDMA
S
RXOUTES
TXINES
DATAXES
MDATAES
31:24
0x0210
USBHS_DEVEPTIE
R8 (ISOENPT)
7:0
SHORTPACK
CRCERRES
ETES
15:8
FIFOCONS
OVERFES
KILLBKS
HBISOFLUSH HBISOINERR
UNDERFES
ES
ES
ERRORTRAN
NBUSYBKES
SES
23:16
EPDISHDMA
S
RSTDTS
31:24
0x0214
...
0x021F
Reserved
7:0
0x0220
USBHS_DEVEPTID
R0
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x0220
USBHS_DEVEPTID
R0 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
DATAXEC
MDATEC
EPDISHDMA
C
23:16
31:24
7:0
0x0224
USBHS_DEVEPTID
R1
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
DATAXEC
MDATEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x0224
USBHS_DEVEPTID
R1 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
EPDISHDMA
C
23:16
31:24
7:0
0x0228
USBHS_DEVEPTID
R2
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
23:16
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
NBUSYBKEC
STALLRQC
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 747
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
0x0228
Name
Bit Pos.
USBHS_DEVEPTID
R2 (ISOENPT)
7
6
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
5
OVERFEC
4
3
2
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
SEC
NBUSYBKEC
1
0
RXOUTEC
TXINEC
DATAXEC
MDATEC
EPDISHDMA
C
23:16
31:24
7:0
0x022C
USBHS_DEVEPTID
R3
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
DATAXEC
MDATEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x022C
USBHS_DEVEPTID
R3 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
EPDISHDMA
C
23:16
31:24
7:0
0x0230
USBHS_DEVEPTID
R4
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
DATAXEC
MDATEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x0230
USBHS_DEVEPTID
R4 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
EPDISHDMA
C
23:16
31:24
7:0
0x0234
USBHS_DEVEPTID
R5
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
DATAXEC
MDATEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x0234
USBHS_DEVEPTID
R5 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
EPDISHDMA
C
23:16
31:24
7:0
0x0238
USBHS_DEVEPTID
R6
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
DATAXEC
MDATEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x0238
USBHS_DEVEPTID
R6 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
EPDISHDMA
C
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 748
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
0x023C
Name
Bit Pos.
USBHS_DEVEPTID
R7
7
6
7:0
SHORTPACK
STALLEDEC
ETEC
15:8
FIFOCONC
5
4
3
2
1
0
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
DATAXEC
MDATEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x023C
USBHS_DEVEPTID
R7 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
EPDISHDMA
C
23:16
31:24
7:0
0x0240
USBHS_DEVEPTID
R8
15:8
SHORTPACK
STALLEDEC
ETEC
FIFOCONC
OVERFEC
NAKINEC
NAKOUTEC
RXSTPEC
RXOUTEC
TXINEC
NYETDISC
EPDISHDMA
C
RXOUTEC
TXINEC
DATAXEC
MDATEC
NBUSYBKEC
23:16
STALLRQC
31:24
0x0240
USBHS_DEVEPTID
R8 (ISOENPT)
7:0
SHORTPACK
CRCERREC
ETEC
15:8
FIFOCONC
OVERFEC
HBISOFLUSH HBISOINERR
UNDERFEC
EC
EC
ERRORTRAN
NBUSYBKEC
SEC
EPDISHDMA
C
23:16
31:24
0x0244
...
0x02FF
Reserved
0x0300
USBHS_DEVDMAN
XTDSC1
0x0304
USBHS_DEVDMAA
DDRESS1
0x0308
USBHS_DEVDMAC
ONTROL1
0x030C
USBHS_DEVDMAS
TATUS1
0x0310
USBHS_DEVDMAN
XTDSC2
0x0314
USBHS_DEVDMAA
DDRESS2
0x0318
USBHS_DEVDMAC
ONTROL2
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
© 2022 Microchip Technology Inc.
and its subsidiaries
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
Complete Data Sheet
DS60001527G-page 749
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x031C
USBHS_DEVDMAS
TATUS2
0x0320
USBHS_DEVDMAN
XTDSC3
0x0324
USBHS_DEVDMAA
DDRESS3
0x0328
USBHS_DEVDMAC
ONTROL3
0x032C
USBHS_DEVDMAS
TATUS3
0x0330
USBHS_DEVDMAN
XTDSC4
0x0334
USBHS_DEVDMAA
DDRESS4
0x0338
USBHS_DEVDMAC
ONTROL4
0x033C
USBHS_DEVDMAS
TATUS4
0x0340
USBHS_DEVDMAN
XTDSC5
0x0344
USBHS_DEVDMAA
DDRESS5
0x0348
USBHS_DEVDMAC
ONTROL5
0x034C
USBHS_DEVDMAS
TATUS5
0x0350
USBHS_DEVDMAN
XTDSC6
Bit Pos.
7
5
4
3
7:0
15:8
DESC_LDST END_BF_ST END_TR_ST
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
© 2022 Microchip Technology Inc.
and its subsidiaries
6
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
2
1
0
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
Complete Data Sheet
DS60001527G-page 750
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0354
USBHS_DEVDMAA
DDRESS6
0x0358
USBHS_DEVDMAC
ONTROL6
0x035C
USBHS_DEVDMAS
TATUS6
0x0360
USBHS_DEVDMAN
XTDSC7
0x0364
USBHS_DEVDMAA
DDRESS7
0x0368
USBHS_DEVDMAC
ONTROL7
0x036C
USBHS_DEVDMAS
TATUS7
0x0370
...
0x03FF
Reserved
0x0400
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
Bit Pos.
USBHS_HSTCTRL
USBHS_HSTISR
USBHS_HSTICR
USBHS_HSTIFR
USBHS_HSTIMR
USBHS_HSTIDR
USBHS_HSTIER
7
5
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
4
3
2
1
0
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
END_TR_EN LDNXT_DSC CHANN_ENB
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
CHANN_ACT CHANN_ENB
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
SPDCONF[1:0]
RSMEDI
PEP_3
RSTI
PEP_2
DCONNI
PEP_0
PEP_8
DCONNIC
DCONNIS
DMA_4
DMA_3
DMA_2
HSOFIC
RXRSMIC
RSMEDIC
DMA_1
RSTIC
HWUPIS
HSOFIS
RXRSMIS
RSMEDIS
RSTIS
DDISCIS
DMA_5
HWUPIE
PEP_6
DMA_4
HSOFIE
PEP_5
DMA_3
RXRSMIE
PEP_4
DMA_2
RSMEDIE
PEP_3
DMA_1
RSTIE
PEP_2
DMA_5
HWUPIEC
PEP_6
DMA_4
HSOFIEC
PEP_5
DMA_3
RXRSMIEC
PEP_4
DMA_2
RSMEDIEC
PEP_3
DMA_1
RSTIEC
PEP_2
PEP_7
DMA_5
HWUPIES
PEP_6
DMA_4
HSOFIES
PEP_5
DMA_3
RXRSMIES
PEP_4
DMA_2
RSMEDIES
PEP_3
DMA_1
RSTIES
PEP_2
DMA_6
DMA_5
DMA_4
DMA_3
DMA_2
DMA_1
DMA_0
DDISCIE
PEP_1
PEP_9
DMA_0
DDISCIEC
PEP_1
PEP_9
DMA_0
DDISCIES
PEP_1
PEP_9
DMA_0
PEP_7
DMA_6
PEP_7
DMA_6
RXRSMI
PEP_4
SOFE
DMA_5
DMA_6
HSOFI
PEP_5
RESET
HWUPIC
DMA_6
HWUPI
PEP_6
RESUME
DDISCI
PEP_1
PEP_9
DMA_0
DDISCIC
PEP_7
© 2022 Microchip Technology Inc.
and its subsidiaries
6
Complete Data Sheet
DCONNIE
PEP_0
PEP_8
DCONNIEC
PEP_0
PEP_8
DCONNIES
PEP_0
PEP_8
DS60001527G-page 751
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x041C
USBHS_HSTPIP
0x0420
USBHS_HSTFNUM
0x0424
USBHS_HSTADDR
1
0x0428
USBHS_HSTADDR
2
0x042C
USBHS_HSTADDR
3
0x0430
...
0x04FF
Reserved
0x0500
USBHS_HSTPIPCF
G0
0x0500
USBHS_HSTPIPCF
G0 (HSBOHSCP)
0x0504
USBHS_HSTPIPCF
G1
0x0504
USBHS_HSTPIPCF
G1 (HSBOHSCP)
0x0508
USBHS_HSTPIPCF
G2
0x0508
USBHS_HSTPIPCF
G2 (HSBOHSCP)
0x050C
USBHS_HSTPIPCF
G3
0x050C
USBHS_HSTPIPCF
G3 (HSBOHSCP)
0x0510
USBHS_HSTPIPCF
G4
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
PEN7
PEN6
PEN5
PEN4
PEN3
PEN2
PEN1
PEN0
PEN8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
PRST7
PRST6
PRST5
PRST4
PRST3
PRST2
PRST1
PRST0
PRST8
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
FNUM[4:0]
MFNUM[2:0]
FNUM[10:5]
FLENHIGH[7:0]
HSTADDRP0[6:0]
HSTADDRP1[6:0]
HSTADDRP2[6:0]
HSTADDRP3[6:0]
HSTADDRP4[6:0]
HSTADDRP5[6:0]
HSTADDRP6[6:0]
HSTADDRP7[6:0]
HSTADDRP8[6:0]
HSTADDRP9[6:0]
PSIZE[2:0]
PTYPE[1:0]
PBK[1:0]
ALLOC
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
Complete Data Sheet
DS60001527G-page 752
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0510
USBHS_HSTPIPCF
G4 (HSBOHSCP)
0x0514
USBHS_HSTPIPCF
G5
0x0514
USBHS_HSTPIPCF
G5 (HSBOHSCP)
0x0518
USBHS_HSTPIPCF
G6
0x0518
USBHS_HSTPIPCF
G6 (HSBOHSCP)
0x051C
USBHS_HSTPIPCF
G7
0x051C
USBHS_HSTPIPCF
G7 (HSBOHSCP)
0x0520
USBHS_HSTPIPCF
G8
0x0520
USBHS_HSTPIPCF
G8 (HSBOHSCP)
0x0524
...
0x052F
Reserved
Bit Pos.
7:0
15:8
0x0530
15:8
23:16
31:24
7:0
0x0530
USBHS_HSTPIPIS
R0 (INTPIPES)
15:8
23:16
31:24
7:0
0x0530
USBHS_HSTPIPIS
R0 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0534
USBHS_HSTPIPIS
R1
15:8
23:16
31:24
5
4
3
2
PBK[1:0]
AUTOSW
PINGEN
BINTERVAL[7:0]
PSIZE[2:0]
PTYPE[1:0]
1
0
ALLOC
PTOKEN[1:0]
PEPNUM[3:0]
PBK[1:0]
ALLOC
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PEPNUM[3:0]
INTFRQ[7:0]
PSIZE[2:0]
PBK[1:0]
ALLOC
PTYPE[1:0]
AUTOSW
PTOKEN[1:0]
PINGEN
PEPNUM[3:0]
BINTERVAL[7:0]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
© 2022 Microchip Technology Inc.
and its subsidiaries
6
PSIZE[2:0]
PTYPE[1:0]
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
USBHS_HSTPIPIS
R0
7
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
Complete Data Sheet
DS60001527G-page 753
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0534
USBHS_HSTPIPIS
R1 (INTPIPES)
Bit Pos.
7:0
0x0534
15:8
23:16
31:24
7:0
0x0538
USBHS_HSTPIPIS
R2
15:8
23:16
31:24
7:0
0x0538
USBHS_HSTPIPIS
R2 (INTPIPES)
15:8
23:16
31:24
7:0
0x0538
USBHS_HSTPIPIS
R2 (ISOPIPES)
15:8
23:16
31:24
7:0
0x053C
USBHS_HSTPIPIS
R3
15:8
23:16
31:24
7:0
0x053C
USBHS_HSTPIPIS
R3 (INTPIPES)
15:8
23:16
31:24
7:0
0x053C
USBHS_HSTPIPIS
R3 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0540
USBHS_HSTPIPIS
R4
15:8
23:16
31:24
7:0
0x0540
USBHS_HSTPIPIS
R4 (INTPIPES)
15:8
23:16
31:24
7:0
0x0540
USBHS_HSTPIPIS
R4 (ISOPIPES)
15:8
23:16
31:24
5
4
3
2
1
0
OVERFI
NAKEDI
PERRI
UNDERFI
TXOUTI
RXINI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
CFGOK
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
© 2022 Microchip Technology Inc.
and its subsidiaries
6
SHORTPACK
RXSTALLDI
ETI
15:8
23:16
31:24
7:0
USBHS_HSTPIPIS
R1 (ISOPIPES)
7
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
Complete Data Sheet
DS60001527G-page 754
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0544
USBHS_HSTPIPIS
R5
Bit Pos.
7:0
0x0544
15:8
23:16
31:24
7:0
0x0544
USBHS_HSTPIPIS
R5 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0548
USBHS_HSTPIPIS
R6
15:8
23:16
31:24
7:0
0x0548
USBHS_HSTPIPIS
R6 (INTPIPES)
15:8
23:16
31:24
7:0
0x0548
USBHS_HSTPIPIS
R6 (ISOPIPES)
15:8
23:16
31:24
7:0
0x054C
USBHS_HSTPIPIS
R7
15:8
23:16
31:24
7:0
0x054C
USBHS_HSTPIPIS
R7 (INTPIPES)
15:8
23:16
31:24
7:0
0x054C
USBHS_HSTPIPIS
R7 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0550
USBHS_HSTPIPIS
R8
15:8
23:16
31:24
7:0
0x0550
USBHS_HSTPIPIS
R8 (INTPIPES)
15:8
23:16
31:24
5
4
3
2
1
0
OVERFI
NAKEDI
PERRI
TXSTPI
TXOUTI
RXINI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
CFGOK
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
CRCERRI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
PERRI
TXSTPI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
SHORTPACK
RXSTALLDI
OVERFI
NAKEDI
ETI
CURRBK[1:0]
NBUSYBK[1:0]
PBYCT[3:0]
© 2022 Microchip Technology Inc.
and its subsidiaries
6
SHORTPACK
RXSTALLDI
ETI
15:8
23:16
31:24
7:0
USBHS_HSTPIPIS
R5 (INTPIPES)
7
PERRI
UNDERFI
CFGOK
TXOUTI
RXINI
DTSEQ[1:0]
RWALL
PBYCT[10:4]
Complete Data Sheet
DS60001527G-page 755
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0550
USBHS_HSTPIPIS
R8 (ISOPIPES)
0x0554
...
0x055F
Bit Pos.
7
6
5
4
3
2
1
0
7:0
SHORTPACK
ETI
CRCERRI
OVERFI
NAKEDI
PERRI
UNDERFI
TXOUTI
RXINI
15:8
23:16
31:24
USBHS_HSTPIPIC
R0
USBHS_HSTPIPIC
R0 (INTPIPES)
USBHS_HSTPIPIC
R0 (ISOPIPES)
USBHS_HSTPIPIC
R1
USBHS_HSTPIPIC
R1 (INTPIPES)
0x0564
0x0568
0x0568
0x0568
0x056C
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
TXSTPIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
TXSTPIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
TXSTPIC
TXOUTIC
RXINIC
15:8
23:16
31:24
7:0
USBHS_HSTPIPIC
R3
TXOUTIC
15:8
23:16
31:24
7:0
USBHS_HSTPIPIC
R2 (ISOPIPES)
TXSTPIC
15:8
23:16
31:24
7:0
USBHS_HSTPIPIC
R2 (INTPIPES)
NAKEDIC
15:8
23:16
31:24
7:0
USBHS_HSTPIPIC
R2
OVERFIC
15:8
23:16
31:24
7:0
USBHS_HSTPIPIC
R1 (ISOPIPES)
SHORTPACK
RXSTALLDIC
ETIC
15:8
23:16
31:24
7:0
0x0564
PBYCT[10:4]
15:8
23:16
31:24
7:0
0x0564
DTSEQ[1:0]
RWALL
15:8
23:16
31:24
7:0
0x0560
CFGOK
15:8
23:16
31:24
7:0
0x0560
NBUSYBK[1:0]
PBYCT[3:0]
Reserved
7:0
0x0560
CURRBK[1:0]
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 756
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x056C
USBHS_HSTPIPIC
R3 (INTPIPES)
0x056C
USBHS_HSTPIPIC
R3 (ISOPIPES)
0x0570
USBHS_HSTPIPIC
R4
0x0570
USBHS_HSTPIPIC
R4 (INTPIPES)
0x0570
USBHS_HSTPIPIC
R4 (ISOPIPES)
0x0574
USBHS_HSTPIPIC
R5
0x0574
USBHS_HSTPIPIC
R5 (INTPIPES)
0x0574
USBHS_HSTPIPIC
R5 (ISOPIPES)
0x0578
USBHS_HSTPIPIC
R6
0x0578
USBHS_HSTPIPIC
R6 (INTPIPES)
0x0578
USBHS_HSTPIPIC
R6 (ISOPIPES)
Bit Pos.
7:0
7
5
4
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
SHORTPACK
CRCERRIC
ETIC
3
2
1
0
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
TXSTPIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
TXSTPIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
TXSTPIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
6
Complete Data Sheet
DS60001527G-page 757
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x057C
USBHS_HSTPIPIC
R7
0x057C
USBHS_HSTPIPIC
R7 (INTPIPES)
0x057C
USBHS_HSTPIPIC
R7 (ISOPIPES)
0x0580
USBHS_HSTPIPIC
R8
0x0580
USBHS_HSTPIPIC
R8 (INTPIPES)
0x0580
USBHS_HSTPIPIC
R8 (ISOPIPES)
0x0584
...
0x058F
Reserved
Bit Pos.
7:0
TXSTPIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
TXSTPIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
CRCERRIC
ETIC
OVERFIC
NAKEDIC
UNDERFIC
TXOUTIC
RXINIC
SHORTPACK
RXSTALLDIS
ETIS
OVERFIS
NAKEDIS
PERRIS
TXSTPIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
NBUSYBKS
SHORTPACK
RXSTALLDIS
ETIS
NAKEDIS
NBUSYBKS
SHORTPACK
CRCERRIS
ETIS
OVERFIS
NAKEDIS
NBUSYBKS
SHORTPACK
RXSTALLDIS
ETIS
OVERFIS
NAKEDIS
NBUSYBKS
SHORTPACK
CRCERRIS
ETIS
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
OVERFIS
15:8
23:16
31:24
7:0
0x0594
NAKEDIC
15:8
23:16
31:24
7:0
USBHS_HSTPIPIF
R1 (ISOPIPES)
OVERFIC
15:8
23:16
31:24
7:0
0x0594
0
15:8
23:16
31:24
7:0
USBHS_HSTPIPIF
R1 (INTPIPES)
1
15:8
23:16
31:24
7:0
0x0590
2
15:8
23:16
31:24
7:0
USBHS_HSTPIPIF
R0 (ISOPIPES)
SHORTPACK
RXSTALLDIC
ETIC
3
15:8
23:16
31:24
7:0
0x0590
4
15:8
23:16
31:24
7:0
USBHS_HSTPIPIF
R0 (INTPIPES)
5
15:8
23:16
31:24
7:0
0x0590
6
15:8
23:16
31:24
7:0
USBHS_HSTPIPIF
Rx
7
OVERFIS
NAKEDIS
NBUSYBKS
Complete Data Sheet
DS60001527G-page 758
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0598
USBHS_HSTPIPIF
R2 (INTPIPES)
0x0598
USBHS_HSTPIPIF
R2 (ISOPIPES)
0x059C
USBHS_HSTPIPIF
R3 (INTPIPES)
0x059C
USBHS_HSTPIPIF
R3 (ISOPIPES)
0x05A0
USBHS_HSTPIPIF
R4 (INTPIPES)
0x05A0
USBHS_HSTPIPIF
R4 (ISOPIPES)
0x05A4
USBHS_HSTPIPIF
R5 (INTPIPES)
0x05A4
USBHS_HSTPIPIF
R5 (ISOPIPES)
0x05A8
USBHS_HSTPIPIF
R6 (INTPIPES)
0x05A8
USBHS_HSTPIPIF
R6 (ISOPIPES)
0x05AC
USBHS_HSTPIPIF
R7 (INTPIPES)
Bit Pos.
7:0
7
SHORTPACK
RXSTALLDIS
ETIS
5
4
3
2
1
0
OVERFIS
NAKEDIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
15:8
23:16
31:24
7:0
NBUSYBKS
SHORTPACK
CRCERRIS
ETIS
OVERFIS
15:8
23:16
31:24
7:0
SHORTPACK
RXSTALLDIS
ETIS
OVERFIS
SHORTPACK
CRCERRIS
ETIS
OVERFIS
SHORTPACK
RXSTALLDIS
ETIS
OVERFIS
SHORTPACK
CRCERRIS
ETIS
OVERFIS
SHORTPACK
RXSTALLDIS
ETIS
OVERFIS
SHORTPACK
CRCERRIS
ETIS
OVERFIS
SHORTPACK
RXSTALLDIS
ETIS
OVERFIS
NAKEDIS
NBUSYBKS
SHORTPACK
CRCERRIS
ETIS
OVERFIS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
15:8
23:16
31:24
7:0
NAKEDIS
NBUSYBKS
SHORTPACK
RXSTALLDIS
ETIS
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
6
OVERFIS
NAKEDIS
NBUSYBKS
Complete Data Sheet
DS60001527G-page 759
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x05AC
USBHS_HSTPIPIF
R7 (ISOPIPES)
0x05B0
USBHS_HSTPIPIF
R8 (INTPIPES)
0x05B0
USBHS_HSTPIPIF
R8 (ISOPIPES)
0x05B4
...
0x05BF
Reserved
Bit Pos.
7:0
15:8
23:16
31:24
7:0
0x05C0
15:8
23:16
31:24
7:0
0x05C0
USBHS_HSTPIPIM
R0 (ISOPIPES)
0x05C4
15:8
23:16
31:24
7:0
0x05C4
USBHS_HSTPIPIM
R1 (INTPIPES)
15:8
23:16
31:24
7:0
0x05C4
USBHS_HSTPIPIM
R1 (ISOPIPES)
0x05C8
15:8
23:16
31:24
7:0
0x05C8
USBHS_HSTPIPIM
R2 (INTPIPES)
SHORTPACK
RXSTALLDIS
ETIS
SHORTPACK
CRCERRIS
ETIS
1
0
OVERFIS
NAKEDIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRIS
UNDERFIS
TXOUTIS
RXINIS
PERRE
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
OVERFIS
15:8
23:16
31:24
NAKEDIS
OVERFIS
NAKEDIS
NBUSYBKS
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
ETIE
CRCERRE
OVERFIE
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
ETIE
CRCERRE
OVERFIE
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
NAKEDE
NBUSYBKE
FIFOCON
© 2022 Microchip Technology Inc.
and its subsidiaries
2
NBUSYBKS
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R2
3
NBUSYBKS
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R1
4
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R0 (INTPIPES)
SHORTPACK
CRCERRIS
ETIS
5
15:8
23:16
31:24
7:0
0x05C0
6
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R0
7
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
Complete Data Sheet
DS60001527G-page 760
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x05C8
USBHS_HSTPIPIM
R2 (ISOPIPES)
Bit Pos.
7
6
5
4
3
2
1
0
7:0
SHORTPACK
ETIE
CRCERRE
OVERFIE
NAKEDE
PERRE
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
15:8
23:16
31:24
7:0
0x05CC
USBHS_HSTPIPIM
R3
15:8
23:16
31:24
7:0
0x05CC
USBHS_HSTPIPIM
R3 (INTPIPES)
15:8
23:16
31:24
7:0
0x05CC
USBHS_HSTPIPIM
R3 (ISOPIPES)
0x05D0
15:8
23:16
31:24
7:0
0x05D0
USBHS_HSTPIPIM
R4 (INTPIPES)
15:8
23:16
31:24
7:0
0x05D0
USBHS_HSTPIPIM
R4 (ISOPIPES)
0x05D4
15:8
23:16
31:24
7:0
0x05D4
USBHS_HSTPIPIM
R5 (INTPIPES)
15:8
23:16
31:24
7:0
0x05D4
USBHS_HSTPIPIM
R5 (ISOPIPES)
0x05D8
SHORTPACK
ETIE
15:8
23:16
31:24
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
ETIE
OVERFIE
CRCERRE
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
ETIE
CRCERRE
OVERFIE
PERRE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
NAKEDE
NBUSYBKE
FIFOCON
© 2022 Microchip Technology Inc.
and its subsidiaries
CRCERRE
NBUSYBKE
FIFOCON
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R6
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R5
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R4
FIFOCON
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
Complete Data Sheet
DS60001527G-page 761
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x05D8
USBHS_HSTPIPIM
R6 (INTPIPES)
Bit Pos.
7:0
0x05D8
0x05DC
15:8
23:16
31:24
7:0
0x05DC
USBHS_HSTPIPIM
R7 (INTPIPES)
15:8
23:16
31:24
7:0
0x05DC
USBHS_HSTPIPIM
R7 (ISOPIPES)
0x05E0
15:8
23:16
31:24
7:0
0x05E0
USBHS_HSTPIPIM
R8 (INTPIPES)
15:8
23:16
31:24
7:0
0x05E0
0x05E4
...
0x05EF
USBHS_HSTPIPIM
R8 (ISOPIPES)
USBHS_HSTPIPIE
R0
2
1
0
OVERFIE
NAKEDE
PERRE
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
CRCERRE
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
UNDERFIE
TXOUTE
RXINE
RSTDT
PFREEZE
PDISHDMA
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
NBUSYBKE
OVERFIE
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
ETIE
CRCERRE
OVERFIE
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
SHORTPACK
ETIE
CRCERRE
PERRE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
FIFOCON
SHORTPACK
RXSTALLDE
ETIE
FIFOCON
NAKEDE
NBUSYBKE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
NAKEDE
PERRE
NBUSYBKE
OVERFIE
FIFOCON
NAKEDE
PERRE
NBUSYBKE
USBHS_HSTPIPIE
R0 (INTPIPES)
USBHS_HSTPIPIE
R0 (ISOPIPES)
SHORTPACK
RXSTALLDES OVERFIES
ETIES
15:8
23:16
31:24
SHORTPACK
RXSTALLDES OVERFIES
ETIES
PERRES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
CRCERRES
ETIES
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
NAKEDES
NBUSYBKES
15:8
23:16
31:24
7:0
0x05F0
3
Reserved
7:0
0x05F0
4
FIFOCON
15:8
23:16
31:24
7:0
0x05F0
SHORTPACK
ETIE
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R8
5
FIFOCON
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R7
6
SHORTPACK
RXSTALLDE
ETIE
15:8
23:16
31:24
7:0
USBHS_HSTPIPIM
R6 (ISOPIPES)
7
OVERFIES
NAKEDES
PERRES
NBUSYBKES
Complete Data Sheet
DS60001527G-page 762
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x05F4
USBHS_HSTPIPIE
R1
Bit Pos.
7:0
0x05F4
0x05F4
0x05F8
0x05F8
0x05F8
0x05FC
0x05FC
0x05FC
0x0600
0x0600
SHORTPACK
RXSTALLDES OVERFIES
ETIES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
0
NAKEDES
PERRES
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
NAKEDES
PERRES
NAKEDES
PERRES
NAKEDES
PERRES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
CRCERRES
ETIES
OVERFIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
CRCERRES
ETIES
OVERFIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
1
NBUSYBKES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R4 (INTPIPES)
2
NBUSYBKES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R4
OVERFIES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R3 (ISOPIPES)
SHORTPACK
CRCERRES
ETIES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R3 (INTPIPES)
3
NBUSYBKES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R3
SHORTPACK
RXSTALLDES OVERFIES
ETIES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R2 (ISOPIPES)
4
NBUSYBKES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R2 (INTPIPES)
SHORTPACK
RXSTALLDES OVERFIES
ETIES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R2
5
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R1 (ISOPIPES)
6
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R1 (INTPIPES)
7
NAKEDES
PERRES
NBUSYBKES
Complete Data Sheet
DS60001527G-page 763
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0600
USBHS_HSTPIPIE
R4 (ISOPIPES)
Bit Pos.
7:0
0x0604
0x0604
0x0604
0x0608
0x0608
0x0608
0x060C
0x060C
0x060C
0x0610
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
CRCERRES
ETIES
OVERFIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
CRCERRES
ETIES
OVERFIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
CRCERRES
ETIES
OVERFIES
NAKEDES
PERRES
NBUSYBKES
SHORTPACK
RXSTALLDES OVERFIES
ETIES
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
PERRES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R8
NAKEDES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R7 (ISOPIPES)
OVERFIES
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R7 (INTPIPES)
0
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R7
1
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R6 (ISOPIPES)
2
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R6 (INTPIPES)
3
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R6
4
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R5 (ISOPIPES)
SHORTPACK
CRCERRES
ETIES
5
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R5 (INTPIPES)
6
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R5
7
NAKEDES
PERRES
NBUSYBKES
Complete Data Sheet
DS60001527G-page 764
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0610
USBHS_HSTPIPIE
R8 (INTPIPES)
Bit Pos.
7:0
0x0610
0x0614
...
0x061F
USBHS_HSTPIPID
R0
15:8
23:16
31:24
USBHS_HSTPIPID
R0 (INTPIPES)
15:8
23:16
31:24
7:0
0x0620
USBHS_HSTPIPID
R0 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0624
USBHS_HSTPIPID
R1
15:8
23:16
31:24
7:0
0x0624
USBHS_HSTPIPID
R1 (INTPIPES)
15:8
23:16
31:24
7:0
0x0624
USBHS_HSTPIPID
R1 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0628
USBHS_HSTPIPID
R2
15:8
23:16
31:24
7:0
0x0628
USBHS_HSTPIPID
R2 (INTPIPES)
15:8
23:16
31:24
7:0
0x0628
SHORTPACK
RXSTALLDES OVERFIES
ETIES
4
3
2
1
0
NAKEDES
PERRES
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
UNDERFIES
TXOUTES
RXINES
RSTDTS
PFREEZES
PDISHDMAS
TXSTPEC
TXOUTEC
RXINEC
NBUSYBKES
SHORTPACK
CRCERRES
ETIES
OVERFIES
NAKEDES
PERRES
NBUSYBKES
Reserved
7:0
0x0620
5
15:8
23:16
31:24
7:0
0x0620
6
15:8
23:16
31:24
7:0
USBHS_HSTPIPIE
R8 (ISOPIPES)
7
USBHS_HSTPIPID
R2 (ISOPIPES)
15:8
23:16
31:24
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
© 2022 Microchip Technology Inc.
and its subsidiaries
PERREC
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
Complete Data Sheet
DS60001527G-page 765
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x062C
USBHS_HSTPIPID
R3
Bit Pos.
7:0
0x062C
15:8
23:16
31:24
7:0
0x062C
USBHS_HSTPIPID
R3 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0630
USBHS_HSTPIPID
R4
15:8
23:16
31:24
7:0
0x0630
USBHS_HSTPIPID
R4 (INTPIPES)
15:8
23:16
31:24
7:0
0x0630
USBHS_HSTPIPID
R4 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0634
USBHS_HSTPIPID
R5
15:8
23:16
31:24
7:0
0x0634
USBHS_HSTPIPID
R5 (INTPIPES)
15:8
23:16
31:24
7:0
0x0634
USBHS_HSTPIPID
R5 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0638
USBHS_HSTPIPID
R6
15:8
23:16
31:24
7:0
0x0638
USBHS_HSTPIPID
R6 (INTPIPES)
4
3
2
1
0
SHORTPACK
RXSTALLDEC OVERFIEC
ETIEC
NAKEDEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
FIFOCONC
NBUSYBKEC
15:8
23:16
31:24
7:0
USBHS_HSTPIPID
R3 (INTPIPES)
7
15:8
23:16
31:24
5
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
© 2022 Microchip Technology Inc.
and its subsidiaries
6
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
Complete Data Sheet
DS60001527G-page 766
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0638
USBHS_HSTPIPID
R6 (ISOPIPES)
Bit Pos.
7:0
0x063C
15:8
23:16
31:24
7:0
0x063C
USBHS_HSTPIPID
R7 (INTPIPES)
15:8
23:16
31:24
7:0
0x063C
USBHS_HSTPIPID
R7 (ISOPIPES)
15:8
23:16
31:24
7:0
0x0640
USBHS_HSTPIPID
R8
15:8
23:16
31:24
7:0
0x0640
USBHS_HSTPIPID
R8 (INTPIPES)
15:8
23:16
31:24
7:0
0x0640
USBHS_HSTPIPID
R8 (ISOPIPES)
0x0644
...
0x064F
Reserved
0x0650
USBHS_HSTPIPIN
RQ0
0x0654
USBHS_HSTPIPIN
RQ1
0x0658
USBHS_HSTPIPIN
RQ2
0x065C
USBHS_HSTPIPIN
RQ3
0x0660
USBHS_HSTPIPIN
RQ4
15:8
23:16
31:24
5
4
3
2
1
0
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
FIFOCONC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
TXSTPEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
RXSTALLDEC OVERFIEC
NAKEDEC
ETIEC
FIFOCONC
NBUSYBKEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
PFREEZEC PDISHDMAC
SHORTPACK
CRCERREC
ETIEC
FIFOCONC
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
6
SHORTPACK
CRCERREC
ETIEC
15:8
23:16
31:24
7:0
USBHS_HSTPIPID
R7
7
OVERFIEC
NAKEDEC
PERREC
UNDERFIEC
TXOUTEC
RXINEC
NBUSYBKEC
PFREEZEC PDISHDMAC
INRQ[7:0]
INMODE
INRQ[7:0]
INMODE
INRQ[7:0]
INMODE
INRQ[7:0]
INMODE
INRQ[7:0]
INMODE
Complete Data Sheet
DS60001527G-page 767
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0664
USBHS_HSTPIPIN
RQ5
0x0668
USBHS_HSTPIPIN
RQ6
0x066C
USBHS_HSTPIPIN
RQ7
0x0670
USBHS_HSTPIPIN
RQ8
0x0674
...
0x067F
Reserved
0x0680
USBHS_HSTPIPER
R0
0x0684
USBHS_HSTPIPER
R1
0x0688
USBHS_HSTPIPER
R2
0x068C
USBHS_HSTPIPER
R3
0x0690
USBHS_HSTPIPER
R4
0x0694
USBHS_HSTPIPER
R5
0x0698
USBHS_HSTPIPER
R6
0x069C
USBHS_HSTPIPER
R7
0x06A0
USBHS_HSTPIPER
R8
0x06A4
...
0x06FF
Reserved
Bit Pos.
7
5
7:0
15:8
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
4
3
2
1
0
INRQ[7:0]
INMODE
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
6
INRQ[7:0]
INMODE
INRQ[7:0]
INMODE
INRQ[7:0]
INMODE
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
COUNTER[1:0]
CRC16
TIMEOUT
PID
DATAPID
DATATGL
Complete Data Sheet
DS60001527G-page 768
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0700
USBHS_HSTDMAN
XTDSC1
0x0704
USBHS_HSTDMAA
DDRESSx
0x0708
USBHS_HSTDMAC
ONTROLx
0x070C
USBHS_HSTDMAS
TATUSx
0x0710
USBHS_HSTDMAN
XTDSC2
0x0714
USBHS_HSTDMAA
DDRESSx
0x0718
USBHS_HSTDMAC
ONTROLx
0x071C
USBHS_HSTDMAS
TATUSx
0x0720
USBHS_HSTDMAN
XTDSC3
0x0724
USBHS_HSTDMAA
DDRESSx
0x0728
USBHS_HSTDMAC
ONTROLx
0x072C
USBHS_HSTDMAS
TATUSx
0x0730
USBHS_HSTDMAN
XTDSC4
0x0734
USBHS_HSTDMAA
DDRESSx
Bit Pos.
7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
5
4
3
2
1
0
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
© 2022 Microchip Technology Inc.
and its subsidiaries
6
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
Complete Data Sheet
DS60001527G-page 769
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0738
USBHS_HSTDMAC
ONTROLx
0x073C
USBHS_HSTDMAS
TATUSx
0x0740
USBHS_HSTDMAN
XTDSC5
0x0744
USBHS_HSTDMAA
DDRESSx
0x0748
USBHS_HSTDMAC
ONTROLx
0x074C
USBHS_HSTDMAS
TATUSx
0x0750
USBHS_HSTDMAN
XTDSC6
0x0754
USBHS_HSTDMAA
DDRESSx
0x0758
USBHS_HSTDMAC
ONTROLx
0x075C
USBHS_HSTDMAS
TATUSx
0x0760
USBHS_HSTDMAN
XTDSC7
0x0764
USBHS_HSTDMAA
DDRESSx
0x0768
USBHS_HSTDMAC
ONTROLx
0x076C
USBHS_HSTDMAS
TATUSx
0x0770
...
0x07FF
Reserved
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7
5
4
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT
3
END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
2
1
0
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
NXT_DSC_ADD[7:0]
NXT_DSC_ADD[15:8]
NXT_DSC_ADD[23:16]
NXT_DSC_ADD[31:24]
BUFF_ADD[7:0]
BUFF_ADD[15:8]
BUFF_ADD[23:16]
BUFF_ADD[31:24]
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN
© 2022 Microchip Technology Inc.
and its subsidiaries
6
BUFF_LENGTH[7:0]
BUFF_LENGTH[15:8]
DESC_LDST END_BF_ST END_TR_ST
END_TR_EN LDNXT_DSC CHANN_ENB
CHANN_ACT CHANN_ENB
BUFF_COUNT[7:0]
BUFF_COUNT[15:8]
Complete Data Sheet
DS60001527G-page 770
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
...........continued
Offset
Name
0x0800
USBHS_CTRL
0x0804
USBHS_SR
0x0808
USBHS_SCR
0x080C
Bit Pos.
7
6
7:0
15:8
USBE
FRZCLK
USBHS_SFR
4
3
2
1
0
RDERRE
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2022 Microchip Technology Inc.
and its subsidiaries
5
VBUSHWC
UIMOD
CLKUSABLE
UID
RDERRI
SPEED[1:0]
RDERRIC
RDERRIS
VBUSRQS
Complete Data Sheet
DS60001527G-page 771
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.1
General Control Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_CTRL
0x0800
0x03004000
Read/Write
31
30
29
28
27
26
25
UIMOD
R/W
1
24
UID
R/W
1
23
22
21
20
19
18
17
16
15
USBE
R/W
0
14
FRZCLK
R/W
1
13
12
11
10
9
8
VBUSHWC
R/W
0
7
6
5
4
RDERRE
R/W
0
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 25 – UIMOD USBHS Mode
0 (HOST): The module is in USB Host mode.
1 (DEVICE): The module is in USB Device mode.
This bit can be written even if USBE = 0 or FRZCLK = 1. Disabling the USBHS (by writing a zero to the USBE bit)
does not reset this bit.
Bit 24 – UID UID Pin Enable
Must be set to ‘0’.
Bit 15 – USBE USBHS Enable
Writing a zero to this bit resets the USBHS, disables the USB transceiver, and disables the USBHS clock inputs.
Unless explicitly stated, all registers then become read-only and are reset.
This bit can be written even if FRZCLK = 1
Value
Description
0
The USBHS is disabled.
1
The USBHS is enabled.
Bit 14 – FRZCLK Freeze USB Clock
This bit can be written even if USBE = 0. Disabling the USBHS (by writing a zero to the USBE bit) does not reset this
bit, but it freezes the clock inputs whatever its value.
Value
Description
0
The clock inputs are enabled.
1
The clock inputs are disabled (the resume detection is still active). This reduces the power
consumption. Unless explicitly stated, all registers then become read-only.
Bit 8 – VBUSHWC VBUS Hardware Control
Must be set to ‘1’.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 772
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
0
1
Description
The hardware control over the VBOF output pin is enabled. The USBHS resets the VBOF output pin
when a VBUS problem occurs.
The hardware control over the VBOF output pin is disabled.
The hardware control over the PIO line is enabled. The USBHS resets the PIO output pin when a
VBUS problem occurs.
The hardware control over the PIO line is disabled.
Bit 4 – RDERRE Remote Device Connection Error Interrupt Enable
Value
Description
0
The Remote Device Connection Error Interrupt (USBHS_SR.RDERRI) is disabled.
1
The Remote Device Connection Error Interrupt (USBHS_SR.RDERRI) is enabled.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 773
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.2
General Status Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_SR
0x0804
0x00000400
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
CLKUSABLE
R
0
13
12
11
10
9
8
R
0
R
0
6
5
4
RDERRI
R
0
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
SPEED[1:0]
Bit 14 – CLKUSABLE UTMI Clock Usable
Value
Description
0
Cleared when the UTMI 30 MHz is not usable.
1
Set when the UTMI 30 MHz is usable.
Bits 13:12 – SPEED[1:0] Remote Device Speed Status
This field is set according to the connected device speed mode.
Value
Name
Description
0
FULL_SPEED
Full-Speed mode
1
HIGH_SPEED
High-Speed mode
2
LOW_SPEED
Low-Speed mode
3
Reserved
Bit 4 – RDERRI Remote Device Connection Error Interrupt (Host mode only)
Value
Description
0
Cleared when USBHS_SCR.RDERRIC = 1.
1
Set when an error occurs during the remote device connection. This triggers a USB interrupt if
USBHS_CTRL.RDERRE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 774
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.3
General Status Clear Register
Name:
Offset:
Property:
USBHS_SCR
0x0808
Write-only
This register always reads as zero.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
RDERRIC
W
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – RDERRIC Remote Device Connection Error Interrupt Clear
Value
Description
0
No effect.
1
Clears the RDERRI bit in USBHS_SR.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 775
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.4
General Status Set Register
Name:
Offset:
Property:
USBHS_SFR
0x080C
Write-only
This register always reads as zero.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
VBUSRQS
W
8
7
6
5
4
RDERRIS
W
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 9 – VBUSRQS VBUS Request Set
Must be set to ‘1’.
Value
Description
0
No effect.
1
Sets the VBUSRQ bit in USBHS_SR.
Bit 4 – RDERRIS Remote Device Connection Error Interrupt Set
Value
Description
0
No effect.
1
Sets the RDERRI bit in USBHS_SR, which may be useful for test or debug purposes.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 776
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.5
Device General Control Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_DEVCTRL
0x0000
0x00000100
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OPMODE2
R/W
0
15
TSTPCKT
R/W
0
14
TSTK
R/W
0
13
TSTJ
R/W
0
12
LS
R/W
0
9
RMWKUP
R/W
0
8
DETACH
R/W
1
7
ADDEN
R/W
0
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
11
10
SPDCONF[1:0]
R/W
R/W
0
0
3
UADD[6:0]
R/W
0
Bit 16 – OPMODE2 Specific Operational mode
Value
Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver is in the “Disable bit stuffing and NRZI encoding” operational mode for test
purposes.
Bit 15 – TSTPCKT Test packet mode
Value
Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver generates test packets for test purposes.
Bit 14 – TSTK Test mode K
Value
Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver generates high-speed K state for test purposes.
Bit 13 – TSTJ Test mode J
Value
Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver generates high-speed J state for test purposes.
Bit 12 – LS Low-Speed Mode Force
This bit can be written even if USBHS_CTRL.USBE = 0 or USBHS_CTRL.FRZCLK = 1. Disabling the USBHS (by
writing a zero to the USBHS_CTRL.USBE bit) does not reset this bit.
Value
Description
0
The Full-speed mode is active.
1
The Low-speed mode is active.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 777
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bits 11:10 – SPDCONF[1:0] Mode Configuration
This field contains the peripheral speed:
Value
Name
Description
0
NORMAL
The peripheral starts in Full-speed mode and performs a high-speed reset to switch to
High-speed mode if the host is high-speed-capable.
1
LOW_POWER For a better consumption, if high speed is not needed.
2
HIGH_SPEED Forced high speed.
3
FORCED_FS The peripheral remains in Full-speed mode whatever the host speed capability.
Bit 9 – RMWKUP Remote Wakeup
This bit is cleared when the USBHS receives a USB reset or once the upstream resume has been sent.
Value
Description
0
No effect.
1
Sends an upstream resume to the host for a remote wakeup.
Bit 8 – DETACH Detach
Value
Description
0
Reconnects the device.
1
Physically detaches the device (disconnects the internal pull-up resistor from D+ and D-).
Bit 7 – ADDEN Address Enable
This bit is cleared when a USB reset is received.
Value
Description
0
No effect.
1
Activates the UADD field (USB address).
Bits 6:0 – UADD[6:0] USB Address
This field contains the device address.
This field is cleared when a USB reset is received.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 778
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.6
Device Global Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
USBHS_DEVISR
0x0004
0x00000000
Read-only
31
DMA_6
R
0
30
DMA_5
R
0
29
DMA_4
R
0
28
DMA_3
R
0
27
DMA_2
R
0
26
DMA_1
R
0
25
DMA_0
R
0
24
23
22
21
PEP_9
R
0
20
PEP_8
R
0
19
PEP_7
R
0
18
PEP_6
R
0
17
PEP_5
R
0
16
PEP_4
R
0
15
PEP_3
R
0
14
PEP_2
R
0
13
PEP_1
R
0
12
PEP_0
R
0
11
10
9
8
7
6
UPRSM
R
0
5
EORSM
R
0
4
WAKEUP
R
0
3
EORST
R
0
2
SOF
R
0
1
MSOF
R
0
0
SUSP
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt
Value
Description
0
Cleared when the USBHS_DEVDMASTATUSx interrupt source is cleared.
1
Set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if DMA_x = 1.
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_ Endpoint x Interrupt
Value
Description
0
Cleared when the interrupt source is serviced.
1
Set when an interrupt is triggered by endpoint x (USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx). This
triggers a USB interrupt if USBHS_DEVIMR.PEP_x = 1.
Bit 6 – UPRSM Upstream Resume Interrupt
Value
Description
0
Cleared when the USBHS_DEVICR.UPRSMC bit is written to one to acknowledge the interrupt (USB
clock inputs must be enabled before).
1
Set when the USBHS sends a resume signal called “Upstream Resume”. This triggers a USB interrupt
if USBHS_DEVIMR.UPRSME = 1.
Bit 5 – EORSM End of Resume Interrupt
Value
Description
0
Cleared when the USBHS_DEVICR.EORSMC bit is written to one to acknowledge the interrupt.
1
Set when the USBHS detects a valid “End of Resume” signal initiated by the host. This triggers a USB
interrupt if USBHS_DEVIMR.EORSME = 1.
Bit 4 – WAKEUP Wakeup Interrupt
This interrupt is generated even if the clock is frozen by the USBHS_CTRL.FRZCLK bit.
Value
Description
0
Cleared when the USBHS_DEVICR.WAKEUPC bit is written to one to acknowledge the interrupt (USB
clock inputs must be enabled before), or when the Suspend (SUSP) interrupt bit is set.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 779
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
1
Description
Set when the USBHS is reactivated by a filtered non-idle signal from the lines (not by an upstream
resume). This triggers an interrupt if USBHS_DEVIMR.WAKEUPE = 1.
Bit 3 – EORST End of Reset Interrupt
Value
Description
0
Cleared when the USBHS_DEVICR.EORSTC bit is written to one to acknowledge the interrupt.
1
Set when a USB “End of Reset” has been detected. This triggers a USB interrupt if
USBHS_DEVIMR.EORSTE = 1.
Bit 2 – SOF Start of Frame Interrupt
Value
Description
0
Cleared when the USBHS_DEVICR.SOFC bit is written to one to acknowledge the interrupt.
1
Set when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB
interrupt if SOFE = 1. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared.
Bit 1 – MSOF Micro Start of Frame Interrupt
Value
Description
0
Cleared when the USBHS_DEVICR.MSOFC bit is written to one to acknowledge the interrupt.
1
Set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every
125 μs). This triggers a USB interrupt if MSOFE = 1. The MFNUM field is updated. The FNUM field is
unchanged.
Bit 0 – SUSP Suspend Interrupt
Value
Description
0
Cleared when the USBHS_DEVICR.SUSPC bit is written to one to acknowledge the interrupt, or when
the Wakeup (WAKEUP) interrupt bit is set.
1
Set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms).
This triggers a USB interrupt if USBHS_DEVIMR.SUSPE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 780
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.7
Device Global Interrupt Clear Register
Name:
Offset:
Property:
USBHS_DEVICR
0x0008
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVISR.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
UPRSMC
W
5
EORSMC
W
4
WAKEUPC
W
3
EORSTC
W
2
SOFC
W
1
MSOFC
W
0
SUSPC
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 6 – UPRSMC Upstream Resume Interrupt Clear
Bit 5 – EORSMC End of Resume Interrupt Clear
Bit 4 – WAKEUPC Wakeup Interrupt Clear
Bit 3 – EORSTC End of Reset Interrupt Clear
Bit 2 – SOFC Start of Frame Interrupt Clear
Bit 1 – MSOFC Micro Start of Frame Interrupt Clear
Bit 0 – SUSPC Suspend Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 781
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.8
Device Global Interrupt Set Register
Name:
Offset:
Property:
USBHS_DEVIFR
0x000C
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVISR.
Bit
Access
Reset
Bit
31
DMA_6
W
30
DMA_5
W
29
DMA_4
W
28
DMA_3
W
27
DMA_2
W
26
DMA_1
W
25
DMA_0
W
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
UPRSMS
W
5
EORSMS
W
4
WAKEUPS
W
3
EORSTS
W
2
SOFS
W
1
MSOFS
W
0
SUSPS
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Set
Bit 6 – UPRSMS Upstream Resume Interrupt Set
Bit 5 – EORSMS End of Resume Interrupt Set
Bit 4 – WAKEUPS Wakeup Interrupt Set
Bit 3 – EORSTS End of Reset Interrupt Set
Bit 2 – SOFS Start of Frame Interrupt Set
Bit 1 – MSOFS Micro Start of Frame Interrupt Set
Bit 0 – SUSPS Suspend Interrupt Set
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 782
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.9
Device Global Interrupt Mask Register
Name:
Offset:
Reset:
Property:
USBHS_DEVIMR
0x0010
0x00000000
Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Bit
Access
Reset
Bit
31
DMA_6
R
0
30
DMA_5
R
0
29
DMA_4
R
0
28
DMA_3
R
0
27
DMA_2
R
0
26
DMA_1
R
0
25
DMA_0
R
0
24
23
22
21
PEP_9
R
0
20
PEP_8
R
0
19
PEP_7
R
0
18
PEP_6
R
0
17
PEP_5
R
0
16
PEP_4
R
0
15
PEP_3
R
0
14
PEP_2
R
0
13
PEP_1
R
0
12
PEP_0
R
0
11
10
9
8
7
6
UPRSME
R
0
5
EORSME
R
0
4
WAKEUPE
R
0
3
EORSTE
R
0
2
SOFE
R
0
1
MSOFE
R
0
0
SUSPE
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Mask
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_ Endpoint x Interrupt Mask
Bit 6 – UPRSME Upstream Resume Interrupt Mask
Bit 5 – EORSME End of Resume Interrupt Mask
Bit 4 – WAKEUPE Wakeup Interrupt Mask
Bit 3 – EORSTE End of Reset Interrupt Mask
Bit 2 – SOFE Start of Frame Interrupt Mask
Bit 1 – MSOFE Micro Start of Frame Interrupt Mask
Bit 0 – SUSPE Suspend Interrupt Mask
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 783
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.10 Device Global Interrupt Disable Register
Name:
Offset:
Property:
USBHS_DEVIDR
0x0014
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVIMR.
Bit
Access
Reset
Bit
31
DMA_6
W
30
DMA_5
W
29
DMA_4
W
28
DMA_3
W
27
DMA_2
W
26
DMA_1
W
25
DMA_0
W
24
23
22
21
PEP_9
W
20
PEP_8
W
19
PEP_7
W
18
PEP_6
W
17
PEP_5
W
16
PEP_4
W
15
PEP_3
W
14
PEP_2
W
13
PEP_1
W
12
PEP_0
W
11
10
9
8
7
6
UPRSMEC
W
5
EORSMEC
W
4
WAKEUPEC
W
3
EORSTEC
W
2
SOFEC
W
1
MSOFEC
W
0
SUSPEC
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Disable
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_ Endpoint x Interrupt Disable
Bit 6 – UPRSMEC Upstream Resume Interrupt Disable
Bit 5 – EORSMEC End of Resume Interrupt Disable
Bit 4 – WAKEUPEC Wakeup Interrupt Disable
Bit 3 – EORSTEC End of Reset Interrupt Disable
Bit 2 – SOFEC Start of Frame Interrupt Disable
Bit 1 – MSOFEC Micro Start of Frame Interrupt Disable
Bit 0 – SUSPEC Suspend Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 784
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.11 Device Global Interrupt Enable Register
Name:
Offset:
Property:
USBHS_DEVIER
0x0018
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVIMR.
Bit
Access
Reset
Bit
31
DMA_6
W
30
DMA_5
W
29
DMA_4
W
28
DMA_3
W
27
DMA_2
W
26
DMA_1
W
25
DMA_0
W
24
23
22
21
PEP_9
W
20
PEP_8
W
19
PEP_7
W
18
PEP_6
W
17
PEP_5
W
16
PEP_4
W
15
PEP_3
W
14
PEP_2
W
13
PEP_1
W
12
PEP_0
W
11
10
9
8
7
6
UPRSMES
W
5
EORSMES
W
4
WAKEUPES
W
3
EORSTES
W
2
SOFES
W
1
MSOFES
W
0
SUSPES
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Enable
Bits 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 – PEP_ Endpoint x Interrupt Enable
Bit 6 – UPRSMES Upstream Resume Interrupt Enable
Bit 5 – EORSMES End of Resume Interrupt Enable
Bit 4 – WAKEUPES Wakeup Interrupt Enable
Bit 3 – EORSTES End of Reset Interrupt Enable
Bit 2 – SOFES Start of Frame Interrupt Enable
Bit 1 – MSOFES Micro Start of Frame Interrupt Enable
Bit 0 – SUSPES Suspend Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 785
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.12 Device Endpoint Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_DEVEPT
0x001C
0x00000000
Read/Write
31
30
29
28
27
26
25
EPRST9
R/W
0
24
EPRST8
R/W
0
23
EPRST7
R/W
0
22
EPRST6
R/W
0
21
EPRST5
R/W
0
20
EPRST4
R/W
0
19
EPRST3
R/W
0
18
EPRST2
R/W
0
17
EPRST1
R/W
0
16
EPRST0
R/W
0
15
14
13
12
11
10
9
EPEN9
R/W
0
8
EPEN8
R/W
0
7
EPEN7
R/W
0
6
EPEN6
R/W
0
5
EPEN5
R/W
0
4
EPEN4
R/W
0
3
EPEN3
R/W
0
2
EPEN2
R/W
0
1
EPEN1
R/W
0
0
EPEN0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 – EPRST Endpoint x Reset
The whole endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle
Sequence field (USBHS_DEVEPTISRx.DTSEQ), which can be cleared by setting the USBHS_DEVEPTIMRx.RSTDT
bit (by writing a one to the USBHS_DEVEPTIERx.RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
This bit is cleared upon receiving a USB reset.
Value
Description
0
Completes the reset operation and starts using the FIFO.
1
Resets the endpoint x FIFO prior to any other operation, upon hardware reset
or when a USB bus reset has been received. This resets the endpoint x
registers (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx, USBHS_DEVEPTIMRx) but not
the endpoint configuration (USBHS_DEVEPTCFGx.ALLOC, USBHS_DEVEPTCFGx.EPBK,
USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR, USBHS_DEVEPTCFGx.EPTYPE).
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 – EPEN Endpoint x Enable
Value
Description
0
Endpoint x is disabled, forcing the endpoint x state to inactive (no answer to USB
requests) and resetting the endpoint x registers (USBHS_DEVEPTCFGx, USBHS_DEVEPTISRx,
USBHS_DEVEPTIMRx) but not the endpoint configuration (USBHS_DEVEPTCFGx.ALLOC,
USBHS_DEVEPTCFGx.EPBK, USBHS_DEVEPTCFGx.EPSIZE, USBHS_DEVEPTCFGx.EPDIR,
USBHS_DEVEPTCFGx.EPTYPE).
1
Endpoint x is enabled.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 786
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.13 Device Frame Number Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_DEVFNUM
0x0020
0x00000000
Read-only
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FNCERR
R
0
14
13
12
11
10
9
8
Bit
7
6
Access
Reset
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
FNUM[10:5]
R
0
R
0
R
0
R
0
R
0
R
0
5
FNUM[4:0]
R
0
4
3
2
0
R
0
R
0
R
0
1
MFNUM[2:0]
R
0
R
0
Bit 15 – FNCERR Frame Number CRC Error
Value
Description
0
Cleared upon receiving a USB reset.
1
Set when a corrupted frame number (or microframe number) is received. This bit and the SOF (or
MSOF) interrupt bit are updated at the same time.
Bits 13:3 – FNUM[10:0] Frame Number
This field contains the 11-bit frame number information. It is provided in the last received SOF packet.
This field is cleared upon receiving a USB reset.
FNUM is updated even if a corrupted SOF is received.
Bits 2:0 – MFNUM[2:0] Micro Frame Number
This field contains the 3-bit micro frame number information. It is provided in the last received MSOF packet.
This field is cleared at the beginning of each start of frame (SOF interrupt) or upon receiving a USB reset.
MFNUM is updated even if a corrupted MSOF is received.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 787
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.14 Device Endpoint x Configuration Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_DEVEPTCFGx
0x0100 + x*0x04 [x=0..8]
0
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
10
9
AUTOSW
R/W
0
8
EPDIR
R/W
0
2
1
ALLOC
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
15
Access
Reset
Bit
7
Access
Reset
14
13
NBTRANS[1:0]
R/W
R/W
0
0
6
R/W
0
5
EPSIZE[2:0]
R/W
0
12
11
EPTYPE[1:0]
R/W
R/W
0
0
4
3
EPBK[1:0]
R/W
0
R/W
0
R/W
0
Bits 14:13 – NBTRANS[1:0] Number of transactions per microframe for isochronous endpoint
This field should be written with the number of transactions per microframe to perform high-bandwidth isochronous
transfer.
It can be written only for endpoints that have this capability (see USBHS_FEATURES.ENHBISOx bit). Otherwise, this
field is 0.
This field is irrelevant for non-isochronous endpoints.
Value
Name
Description
0
0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability.
1
1_TRANS Default value: one transaction per microframe.
2
2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank.
3
3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank.
Bits 12:11 – EPTYPE[1:0] Endpoint Type
This field should be written to select the endpoint type:
This field is cleared upon receiving a USB reset.
Value
Name
0
CTRL
1
ISO
2
BLK
3
INTRPT
Description
Control
Isochronous
Bulk
Interrupt
Bit 9 – AUTOSW Automatic Switch
This bit is cleared upon receiving a USB reset.
Value
Description
0
The automatic bank switching is disabled.
1
The automatic bank switching is enabled.
Bit 8 – EPDIR Endpoint Direction
This bit is cleared upon receiving a USB reset.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 788
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
0 (OUT): The endpoint direction is OUT.
1 (IN): The endpoint direction is IN (nor for control endpoints).
Bits 6:4 – EPSIZE[2:0] Endpoint Size
This field should be written to select the size of each endpoint bank:
This field is cleared upon receiving a USB reset (except for endpoint 0).
Value
Name
Description
0
8_BYTE
8 bytes
1
16_BYTE
16 bytes
2
32_BYTE
32 bytes
3
64_BYTE
64 bytes
4
128_BYTE
128 bytes
5
256_BYTE
256 bytes
6
512_BYTE
512 bytes
7
1024_BYTE
1024 bytes
Bits 3:2 – EPBK[1:0] Endpoint Banks
This field should be written to select the number of banks for the endpoint:
For control endpoints, a single-bank endpoint (0b00) should be selected.
This field is cleared upon receiving a USB reset (except for endpoint 0).
Value
Name
Description
0
1_BANK
Single-bank endpoint
1
2_BANK
Double-bank endpoint
2
3_BANK
Triple-bank endpoint
3
Reserved
Bit 1 – ALLOC Endpoint Memory Allocate
This bit is cleared upon receiving a USB reset (except for endpoint 0).
Value
Description
0
Frees the endpoint memory.
1
Allocates the endpoint memory. The user should check the USBHS_DEVEPTISRx.CFGOK bit to know
whether the allocation of this endpoint is correct.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 789
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.15 Device Endpoint Interrupt Status Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTISRx
0x0130 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint x Configuration Register”.
Bit
31
Access
Reset
Bit
23
30
29
28
R/W
0
R/W
0
R/W
0
27
BYCT[10:4]
R/W
0
21
20
R/W
0
R/W
0
22
26
25
24
R/W
0
R/W
0
R/W
0
19
18
CFGOK
R/W
0
17
CTRLDIR
R/W
0
16
RWALL
R/W
0
11
10
9
BYCT[3:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
15
14
CURRBK[1:0]
R/W
R/W
0
0
Bit
7
SHORTPACKE
T
Access
R/W
Reset
0
13
12
NBUSYBK[1:0]
R/W
R/W
0
0
8
DTSEQ[1:0]
R/W
R/W
0
0
6
STALLEDI
5
OVERFI
4
NAKINI
3
NAKOUTI
2
RXSTPI
1
RXOUTI
0
TXINI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 30:20 – BYCT[10:0] Byte Count
This field is set with the byte count of the FIFO.
For IN endpoints, the field is incremented after each byte written by the software into the endpoint and decremented
after each byte sent to the host.
For OUT endpoints, the field is incremented after each byte received from the host and decremented after each byte
read by the software from the endpoint.
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt bit.
Bit 18 – CFGOK Configuration OK Status
This bit is updated when USBHS_DEVEPTCFGx.ALLOC = 1.
This bit is set if the endpoint x number of banks (USBHS_DEVEPTCFGx.EPBK) and size
(USBHS_DEVEPTCFGx.EPSIZE) are correct compared to the maximal allowed number of banks and size for this
endpoint and to the maximal FIFO size (i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values to the USBHS_DEVEPTCFGx.EPBK and
USBHS_DEVEPTCFGx.EPSIZE fields.
Bit 17 – CTRLDIR Control Direction
Value
Description
0
Cleared after a SETUP packet to indicate that the following packet is an OUT packet.
1
Set after a SETUP packet to indicate that the following packet is an IN packet.
Bit 16 – RWALL Read/Write Allowed
This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.
This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the
FIFO.
This bit is never set if USBHS_DEVEPTIMRx.STALLRQ = 1 or in case of error.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 790
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
This bit is cleared otherwise.
This bit should not be used for control endpoints.
Bits 15:14 – CURRBK[1:0] Current Bank
This bit is set for non-control endpoints, to indicate the current bank:
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt bit.
Value
Name
Description
0
BANK0
Current bank is bank0
1
BANK1
Current bank is bank1
2
BANK2
Current bank is bank2
3
Reserved
Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks
This field is set to indicate the number of busy banks:
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are
free, this triggers a PEP_x interrupt if NBUSYBKE = 1.
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are
busy, this triggers a PEP_x interrupt if NBUSYBKE = 1.
When the USBHS_DEVEPTIMRx.FIFOCON bit is cleared (by writing a one to the
USBHS_DEVEPTIMRx.FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to
calculate the address of the next bank.
A PEP_x interrupt is triggered if:
Value
Name
Description
0
0_BUSY 0 busy bank (all banks free)
1
1_BUSY 1 busy bank
2
2_BUSY 2 busy banks
3
3_BUSY 3 busy banks
• for IN endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are free;
• for OUT endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are busy.
Bits 9:8 – DTSEQ[1:0] Data Toggle Sequence
This field is set to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that should be used for the next packet to be sent. This is not
relative to the current bank.
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default, DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle
sequence should be Data0.
Value
Name
Description
0
DATA0
Data0 toggle sequence
1
DATA1
Data1 toggle sequence
2
DATA2
Reserved for high-bandwidth isochronous endpoint
3
MDATA
Reserved for high-bandwidth isochronous endpoint
Bit 7 – SHORTPACKET Short Packet Interrupt
Value
Description
0
Cleared when SHORTPACKETC = 1. This acknowledges the interrupt.
1
Set for non-control OUT endpoints, when a short packet has been received. This triggers a PEP_x
interrupt if USBHS_DEVEPTIMRx.SHORTPACKETE = 1.
Bit 6 – STALLEDI STALLed Interrupt
Value
Description
0
Cleared when STALLEDIC = 1. This acknowledges the interrupt.
1
Set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ
bit (by writing a one to the STALLRQS bit). This triggers a PEP_x interrupt if STALLEDE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 791
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 5 – OVERFI Overflow Interrupt
For all endpoint types, an overflow can occur during the OUT stage if the host attempts to write into a bank that is too
small for the packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow
had occurred. The bank is filled with all the first bytes of the packet that fit in.
Value
Description
0
Cleared when the OVERFIC bit is written to one. This acknowledges the interrupt.
1
Set when an overflow error occurs. This triggers a PEP_x interrupt if OVERFE = 1.
Bit 4 – NAKINI NAKed IN Interrupt
Value
Description
0
Cleared when NAKINIC = 1. This acknowledges the interrupt.
1
Set when a NAK handshake has been sent in response to an IN request from the host. This triggers a
PEP_x interrupt if NAKINE = 1.
Bit 3 – NAKOUTI NAKed OUT Interrupt
Value
Description
0
Cleared when NAKOUTIC = 1. This acknowledges the interrupt.
1
Set when a NAK handshake has been sent in response to an OUT request from the host. This triggers
a PEP_x interrupt if NAKOUTE = 1.
Bit 2 – RXSTPI Received SETUP Interrupt
This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers
a PEP_x interrupt if RXSTPE = 1.
It is cleared by writing a one to the RXSTPIC bit. This acknowledges the interrupt and frees the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints.
Bit 1 – RXOUTI Received OUT Data Interrupt
For control endpoints:
0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt and frees the bank.
1: Set when the current bank contains a bulk OUT packet (data or status stage). This triggers a PEP_x interrupt if
USBHS_DEVEPTIMRx.RXOUTE = 1.
For bulk and interrupt OUT endpoints:
0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt, which has no effect on the endpoint
FIFO. USBHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is full. This triggers a PEP_x
interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.
The user reads from the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the OUT
endpoint is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.RXOUTI
and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank.
This bit is inactive (cleared) for bulk and interrupt IN endpoints.
Bit 0 – TXINI Transmitted IN Data Interrupt
For control endpoints:
0: Cleared when TXINIC = 1. This acknowledges the interrupt and sends the packet.
1: Set when the current bank is ready to accept a new IN packet. This triggers a PEP_x interrupt if TXINE = 1.
For bulk and interrupt IN endpoints:
0: Cleared when TXINIC = 1. This acknowledges the interrupt, which has no effect on the endpoint FIFO.
USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is free. This triggers a PEP_x
interrupt if TXINE = 1.
The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the USBHS to
send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The
USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the
status of the next bank.
This bit is inactive (cleared) for bulk and interrupt OUT endpoints.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 792
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.16 Device Endpoint Interrupt Status Register (Isochronous Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTISRx (ISOENPT)
0x0130 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x1 in the ”Device Endpoint x Configuration Register”.
Bit
31
Access
Reset
Bit
23
30
29
28
R/W
0
R/W
0
R/W
0
27
BYCT[10:4]
R/W
0
21
20
R/W
0
R/W
0
22
26
25
24
R/W
0
R/W
0
R/W
0
19
18
CFGOK
R/W
0
17
16
RWALL
R/W
0
11
10
ERRORTRANS
R/W
0
9
BYCT[3:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
15
14
CURRBK[1:0]
R/W
R/W
0
0
7
SHORTPACKE
T
Access
R/W
Reset
0
13
12
NBUSYBK[1:0]
R/W
R/W
0
0
6
CRCERRI
5
OVERFI
R/W
0
R/W
0
4
3
HBISOFLUSHI HBISOINERRI
R/W
0
R/W
0
8
DTSEQ[1:0]
R/W
R/W
0
0
2
UNDERFI
1
RXOUTI
0
TXINI
R/W
0
R/W
0
R/W
0
Bits 30:20 – BYCT[10:0] Byte Count
This field is set with the byte count of the FIFO.
For IN endpoints, the field is incremented after each byte written by the software into the endpoint and decremented
after each byte sent to the host.
For OUT endpoints, the field is incremented after each byte received from the host and decremented after each byte
read by the software from the endpoint.
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt bit.
Bit 18 – CFGOK Configuration OK Status
This bit is updated when USBHS_DEVEPTCFGx.ALLOC = 1.
This bit is set if the endpoint x number of banks (USBHS_DEVEPTCFGx.EPBK) and size
(USBHS_DEVEPTCFGx.EPSIZE) are correct compared to the maximal allowed number of banks and size for this
endpoint and to the maximal FIFO size (i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values to the USBHS_DEVEPTCFGx.EPBK and
USBHS_DEVEPTCFGx.EPSIZE fields.
Bit 16 – RWALL Read/Write Allowed
This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.
This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the
FIFO.
This bit is never set in case of error.
This bit is cleared otherwise.
Bits 15:14 – CURRBK[1:0] Current Bank
This field is used to indicate the current bank. It may be updated one clock cycle after the RWALL bit changes, so the
user should not poll this field as an interrupt bit.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 793
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
2
3
Name
BANK0
BANK1
BANK2
Reserved
Description
Current bank is bank0
Current bank is bank1
Current bank is bank2
Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks
This field is set to indicate the number of busy banks:
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are
free, this triggers a PEP_x interrupt if NBUSYBKE = 1.
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are
busy, this triggers a PEP_x interrupt if NBUSYBKE = 1.
When the USBHS_DEVEPTIMRx.FIFOCON bit is cleared (by writing a one to the
USBHS_DEVEPTIMRx.FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to
calculate the address of the next bank.
A PEP_x interrupt is triggered if:
Value
Name
Description
0
0_BUSY 0 busy bank (all banks free)
1
1_BUSY 1 busy bank
2
2_BUSY 2 busy banks
3
3_BUSY 3 busy banks
• For IN endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are free.
• For OUT endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are busy.
Bit 10 – ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt
This bit is set when a transaction error occurs during the current microframe (the data toggle sequencing is not
compliant with the USB 2.0 standard). This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.ERRORTRANSE =
1.
This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n = 1, 2 or 3) transferred
during the microframe. It is cleared by software by clearing (at least once) the USBHS_DEVEPTIMRx.FIFOCON bit
to switch to the bank that belongs to the next n-transactions (next microframe).
Bits 9:8 – DTSEQ[1:0] Data Toggle Sequence
This field is set to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that should be used for the next packet to be sent. This is not
relative to the current bank.
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default, DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle
sequence should be Data0.
For high-bandwidth isochronous endpoint, a PEP_x interrupt is triggered if:
Value
Name Description
0
DATA0 Data0 toggle sequence
1
DATA1 Data1 toggle sequence
2
DATA2 Data2 toggle sequence (for high-bandwidth isochronous endpoint)
3
MDATA MData toggle sequence (for high-bandwidth isochronous endpoint)
• USBHS_DEVEPTIMRx.MDATAE = 1 and a MData packet has been received (DTSEQ =
MData and USBHS_DEVEPTISRx.RXOUTI = 1).
• USBHS_DEVEPTISRx.DATAXE = 1 and a Data0/1/2 packet has been received (DTSEQ =
Data0/1/2 and USBHS_DEVEPTISRx.RXOUTI = 1).
Bit 7 – SHORTPACKET Short Packet Interrupt
Value
Description
0
Cleared when SHORTPACKETC = 1. This acknowledges the interrupt.
1
Set for non-control OUT endpoints, when a short packet has been received. This triggers a PEP_x
interrupt if USBHS_DEVEPTIMRx.SHORTPACKETE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 794
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 6 – CRCERRI CRC Error Interrupt
Value
Description
0
Cleared when CRCERRIC = 1. This acknowledges the interrupt.
1
Set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is
stored in the bank as if no CRC error had occurred. This triggers a PEP_x interrupt if CRCERRE = 1.
Bit 5 – OVERFI Overflow Interrupt
Value
Description
0
Cleared when OVERFIC = 1. This acknowledges the interrupt.
1
Set when an overflow error occurs. This triggers a PEP_x interrupt if OVERFE = 1. For all endpoint
types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no
overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.
Bit 4 – HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt
Value
Description
0
Cleared when the HBISOFLUSHIC bit is written to one. This acknowledges the interrupt.
1
Set for High-bandwidth isochronous IN endpoint (with NBTRANS = 2 or 3) at the end of the
microframe, if less than N transactions have been completed by the USBHS without underflow error.
This may occur in case of a missing IN token. In this case, the banks are flushed out to ensure the data
synchronization between the host and the device. This triggers a PEP_x interrupt if HBISOFLUSHE =
1.
Bit 3 – HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt
Value
Description
0
Cleared when the HBISOINERRIC bit is written to one. This acknowledges the interrupt.
1
Set for High-bandwidth isochronous IN endpoint (with NBTRANS = 2 or 3) at the end of the
microframe, if less than N banks were written by the CPU within this microframe. This triggers a PEP_x
interrupt if HBISOINERRE = 1.
Bit 2 – UNDERFI Underflow Interrupt
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers a PEP_x interrupt if
UNDERFE = 1.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then
automatically sent by the USBHS.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the
CPU is not fast enough. The packet is lost.
It is cleared by writing a one to the UNDERFIC bit. This acknowledges the interrupt.
Bit 1 – RXOUTI Received OUT Data Interrupt
For control endpoints:
0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt and frees the bank.
1: Set when the current bank contains a bulk OUT packet (data or status stage). This triggers a PEP_x interrupt if
USBHS_DEVEPTIMRx.RXOUTE = 1.
For OUT endpoints:
0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt, which has no effect on the endpoint
FIFO. USBHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is full. This triggers a PEP_x
interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.
The user reads from the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the OUT
endpoint is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.RXOUTI
and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank.
This bit is inactive (cleared) for IN endpoints.
Bit 0 – TXINI Transmitted IN Data Interrupt
For control endpoints:
0: Cleared when TXINIC = 1. This acknowledges the interrupt and sends the packet.
1: Set when the current bank is ready to accept a new IN packet. This triggers a PEP_x interrupt if TXINE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 795
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
For IN endpoints:
0: Cleared when TXINIC = 1. This acknowledges the interrupt, which has no effect on the endpoint FIFO.
USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is free. This triggers a PEP_x
interrupt if TXINE = 1.
The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the USBHS to
send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The
USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the
status of the next bank.
This bit is inactive (cleared) for OUT endpoints.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 796
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.17 Device Endpoint Interrupt Clear Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTICRx
0x0160 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTISRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
6
STALLEDIC
5
OVERFIC
4
NAKINIC
3
NAKOUTIC
2
RXSTPIC
1
RXOUTIC
0
TXINIC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TC
Access
R/W
Reset
0
Bit 7 – SHORTPACKETC Short Packet Interrupt Clear
Bit 6 – STALLEDIC STALLed Interrupt Clear
Bit 5 – OVERFIC Overflow Interrupt Clear
Bit 4 – NAKINIC NAKed IN Interrupt Clear
Bit 3 – NAKOUTIC NAKed OUT Interrupt Clear
Bit 2 – RXSTPIC Received SETUP Interrupt Clear
Bit 1 – RXOUTIC Received OUT Data Interrupt Clear
Bit 0 – TXINIC Transmitted IN Data Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 797
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.18 Device Endpoint Interrupt Clear Register (Isochronous Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTICRx (ISOENPT)
0x0160 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Status Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTISRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
6
CRCERRIC
5
OVERFIC
2
UNDERFIC
1
RXOUTIC
0
TXINIC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TC
Access
R/W
Reset
0
4
3
HBISOFLUSHI HBISOINERRIC
C
R/W
R/W
0
0
Bit 7 – SHORTPACKETC Short Packet Interrupt Clear
Bit 6 – CRCERRIC CRC Error Interrupt Clear
Bit 5 – OVERFIC Overflow Interrupt Clear
Bit 4 – HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear
Bit 3 – HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear
Bit 2 – UNDERFIC Underflow Interrupt Clear
Bit 1 – RXOUTIC Received OUT Data Interrupt Clear
Bit 0 – TXINIC Transmitted IN Data Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 798
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.19 Device Endpoint Interrupt Set Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIFRx
0x0190 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)”.This register
always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVEPTISRx, which may be useful for test or debug purposes.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
NBUSYBKS
R/W
0
11
10
9
8
6
STALLEDIS
5
OVERFIS
4
NAKINIS
3
NAKOUTIS
2
RXSTPIS
1
RXOUTIS
0
TXINIS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TS
Access
R/W
Reset
0
Bit 12 – NBUSYBKS Number of Busy Banks Interrupt Set
Bit 7 – SHORTPACKETS Short Packet Interrupt Set
Bit 6 – STALLEDIS STALLed Interrupt Set
Bit 5 – OVERFIS Overflow Interrupt Set
Bit 4 – NAKINIS NAKed IN Interrupt Set
Bit 3 – NAKOUTIS NAKed OUT Interrupt Set
Bit 2 – RXSTPIS Received SETUP Interrupt Set
Bit 1 – RXOUTIS Received OUT Data Interrupt Set
Bit 0 – TXINIS Transmitted IN Data Interrupt Set
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 799
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.20 Device Endpoint Interrupt Set Register (Isochronous Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIFRx (ISOENPT)
0x0190 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Status Register (Isochronous Endpoints)”.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVEPTISRx, which may be useful for test or debug purposes.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
NBUSYBKS
R/W
0
11
10
9
8
6
CRCERRIS
5
OVERFIS
2
UNDERFIS
1
RXOUTIS
0
TXINIS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TS
Access
R/W
Reset
0
4
3
HBISOFLUSHI HBISOINERRIS
S
R/W
R/W
0
0
Bit 12 – NBUSYBKS Number of Busy Banks Interrupt Set
Bit 7 – SHORTPACKETS Short Packet Interrupt Set
Bit 6 – CRCERRIS CRC Error Interrupt Set
Bit 5 – OVERFIS Overflow Interrupt Set
Bit 4 – HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set
Bit 3 – HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set
Bit 2 – UNDERFIS Underflow Interrupt Set
Bit 1 – RXOUTIS Received OUT Data Interrupt Set
Bit 0 – TXINIS Transmitted IN Data Interrupt Set
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 800
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.21 Device Endpoint Interrupt Mask Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIMRx
0x01C0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
STALLRQ
R/W
0
18
RSTDT
R/W
0
17
NYETDIS
R/W
0
16
EPDISHDMA
R/W
0
15
14
FIFOCON
R/W
0
13
KILLBK
R/W
0
12
NBUSYBKE
R/W
0
11
10
9
8
6
STALLEDE
5
OVERFE
4
NAKINE
3
NAKOUTE
2
RXSTPE
1
RXOUTE
0
TXINE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TE
Access
R/W
Reset
0
Bit 19 – STALLRQ STALL Request
Value
Description
0
Cleared when a new SETUP packet is received or when USBHS_DEVEPTIDRx.STALLRQC = 0.
1
Set when USBHS_DEVEPTIERx.STALLRQS = 1. This requests to send a STALL handshake to the
host.
Bit 18 – RSTDT Reset Data Toggle
This bit is set when USBHS_DEVEPTIERx.RSTDTS = 1. This clears the data toggle sequence, i.e., sets to Data0 the
data toggle sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is cleared instantaneously.
The user does not have to wait for this bit to be cleared.
Bit 17 – NYETDIS NYET Token Disable
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.NYETDISC = 1. This enables the USBHS to handle the highspeed handshake following the USB 2.0 standard.
1
Set when USBHS_DEVEPTIERx.NYETDISS = 1. This sends a ACK handshake instead of a NYET
handshake in High-speed mode.
Bit 16 – EPDISHDMA Endpoint Interrupts Disable HDMA Request
This bit is set when USBHS_DEVEPTIERx.EPDISHDMAS = 1. This pauses the on-going DMA channel x transfer on
any Endpoint x interrupt (PEP_x), whatever the state of the Endpoint x Interrupt Enable bit (PEP_x).
The user then has to acknowledge or to disable the interrupt source (e.g. USBHS_DEVEPTISRx.RXOUTI) or to clear
the EPDISHDMA bit (by writing a one to the USBHS_DEVEPTIDRx.EPDISHDMAC bit) in order to complete the DMA
transfer.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 801
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
In Ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA
transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but
the new-packet DMA transfer does not start (not requested).
If the interrupt is not associated to a new system-bank packet (USBHS_DEVEPTISRx.NAKINI, NAKOUTI, etc.), then
the request cancellation may occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to
complete a DMA transfer by software after reception of a short packet, etc.
Bit 14 – FIFOCON FIFO Control
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. Therefore, the software never uses them on these endpoints. When
read, their value is always 0.
For IN endpoints:
0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to the
next bank.
1: Set when the current bank is free, at the same time as USBHS_DEVEPTISRx.TXINI.
For OUT endpoints:
0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to free the current bank and to switch to
the next bank.
1: Set when the current bank is full, at the same time as USBHS_DEVEPTISRx.RXOUTI.
Bit 13 – KILLBK Kill IN Bank
This bit is set when the USBHS_DEVEPTIERx.KILLBKS bit is written to one. This kills the last written bank.
This bit is cleared when the bank is killed.
CAUTION
The bank is really cleared when the “kill packet” procedure is accepted by the USBHS core. This bit is
automatically cleared after the end of the procedure.
The bank is really killed: USBHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared but sent (IN transfer): USBHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared because it was empty.
The user should wait for this bit to be cleared before trying to kill another packet.
This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent
on the USB line. If at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is
coming. Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
Bit 12 – NBUSYBKE Number of Busy Banks Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.NBUSYBKEC = 0. This disables the Number of Busy Banks
interrupt (USBHS_DEVEPTISRx.NBUSYBK).
1
Set when the USBHS_DEVEPTIERx.NBUSYBKES = 1. This enables the Number of Busy Banks
interrupt (USBHS_DEVEPTISRx.NBUSYBK).
Bit 7 – SHORTPACKETE Short Packet Interrupt
If this bit is set for non-control IN endpoints, a short packet transmission is guaranteed upon ending a DMA transfer,
thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, provided that the End of DMA Buffer
Output Enable (END_B_EN) bit and the Automatic Switch (AUTOSW) = 1.
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHORTPACKET).
1
Set when USBHS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHORTPACKET).
Bit 6 – STALLEDE STALLed Interrupt
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 802
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
Description
Cleared when USBHS_DEVEPTIDRx.STALLEDEC = 1. This disables the STALLed interrupt
(USBHS_DEVEPTISRx.STALLEDI).
Set when USBHS_DEVEPTIERx.STALLEDES = 1. This enables the STALLed interrupt
(USBHS_DEVEPTISRx.STALLEDI).
Bit 5 – OVERFE Overflow Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.OVERFEC = 1. This disables the Overflow interrupt
(USBHS_DEVEPTISRx.OVERFI).
1
Set when USBHS_DEVEPTIERx.OVERFES = 1. This enables the Overflow interrupt
(USBHS_DEVEPTISRx.OVERFI).
Bit 4 – NAKINE NAKed IN Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.NAKINEC = 1. This disables the NAKed IN interrupt
(USBHS_DEVEPTISRx.NAKINI).
1
Set when USBHS_DEVEPTIERx.NAKINES = 1. This enables the NAKed IN interrupt
(USBHS_DEVEPTISRx.NAKINI).
Bit 3 – NAKOUTE NAKed OUT Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.NAKOUTEC = 1. This disables the NAKed OUT interrupt
(USBHS_DEVEPTISRx.NAKOUTI).
1
Set when USBHS_DEVEPTIERx.NAKOUTES = 1. This enables the NAKed OUT interrupt
(USBHS_DEVEPTISRx.NAKOUTI).
Bit 2 – RXSTPE Received SETUP Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIERx.RXSTPEC = 1. This disables the Received SETUP interrupt
(USBHS_DEVEPTISRx.RXSTPI).
1
Set when USBHS_DEVEPTIERx.RXSTPES = 1. This enables the Received SETUP interrupt
(USBHS_DEVEPTISRx.RXSTPI).
Bit 1 – RXOUTE Received OUT Data Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.RXOUTEC = 1. This disables the Received OUT Data interrupt
(USBHS_DEVEPTISRx.RXOUTI).
1
Set when USBHS_DEVEPTIERx.RXOUTES = 1. This enables the Received OUT Data interrupt
(USBHS_DEVEPTISRx.RXOUTI).
Bit 0 – TXINE Transmitted IN Data Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.TXINEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_DEVEPTISRx.TXINI).
1
Set when USBHS_DEVEPTIERx.TXINES = 1. This enables the Transmitted IN Data interrupt
(USBHS_DEVEPTISRx.TXINI).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 803
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.22 Device Endpoint Interrupt Mask Register (Isochronous Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIMRx (ISOENPT)
0x01C0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDT
R/W
0
17
16
EPDISHDMA
R/W
0
15
14
FIFOCON
13
KILLBK
12
NBUSYBKE
11
9
DATAXE
8
MDATAE
R/W
0
R/W
0
R/W
0
10
ERRORTRANS
E
R/W
0
R/W
0
R/W
0
6
CRCERRE
5
OVERFE
2
UNDERFE
1
RXOUTE
0
TXINE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TE
Access
R/W
Reset
0
4
3
HBISOFLUSHE HBISOINERRE
R/W
0
R/W
0
Bit 18 – RSTDT Reset Data Toggle
This bit is set when USBHS_DEVEPTIERx.RSTDTS = 1. This clears the data toggle sequence, i.e., sets to Data0 the
data toggle sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is cleared instantaneously.
The user does not have to wait for this bit to be cleared.
Bit 16 – EPDISHDMA Endpoint Interrupts Disable HDMA Request
This bit is set when USBHS_DEVEPTIERx.EPDISHDMAS = 1. This pauses the on-going DMA channel x transfer on
any Endpoint x interrupt (PEP_x), whatever the state of the Endpoint x Interrupt Enable bit (PEP_x).
The user then has to acknowledge or to disable the interrupt source (e.g. USBHS_DEVEPTISRx.RXOUTI) or to clear
the EPDISHDMA bit (by writing a one to the USBHS_DEVEPTIDRx.EPDISHDMAC bit) in order to complete the DMA
transfer.
In Ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA
transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but
the new-packet DMA transfer does not start (not requested).
If the interrupt is not associated to a new system-bank packet (USBHS_DEVEPTISRx.NAKINI, NAKOUTI, etc.), then
the request cancellation may occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to
complete a DMA transfer by software after reception of a short packet, etc.
Bit 14 – FIFOCON FIFO Control
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. Therefore, the software never uses them on these endpoints. When
read, their value is always 0.
For IN endpoints:
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 804
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to the
next bank.
1: Set when the current bank is free, at the same time as USBHS_DEVEPTISRx.TXINI.
For OUT endpoints:
0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to free the current bank and to switch to
the next bank.
1: Set when the current bank is full, at the same time as USBHS_DEVEPTISRx.RXOUTI.
Bit 13 – KILLBK Kill IN Bank
CAUTION
The bank is really cleared when the “kill packet” procedure is accepted by the USBHS core. This bit is
automatically cleared after the end of the procedure.
The bank is really killed: USBHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared but sent (IN transfer): USBHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared because it was empty.
The user should wait for this bit to be cleared before trying to kill another packet.
This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent
on the USB line. If at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is
coming. Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
Value
Description
0
Cleared when the bank is killed.
1
Set when USBHS_DEVEPTIERx.KILLBKS = 1. This kills the last written bank.
Bit 12 – NBUSYBKE Number of Busy Banks Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.NBUSYBKEC = 0. This disables the Number of Busy Banks
interrupt (USBHS_DEVEPTISRx.NBUSYBK).
1
Set when USBHS_DEVEPTIERx.NBUSYBKES = 1. This enables the Number of Busy Banks interrupt
(USBHS_DEVEPTISRx.NBUSYBK).
Bit 10 – ERRORTRANSE Transaction Error Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.ERRORTRANSEC = 1. This disables the transaction error
interrupt (USBHS_DEVEPTISRx.ERRORTRANS).
1
Set when USBHS_DEVEPTIERx.ERRORTRANSES = 1. This enables the transaction error interrupt
(USBHS_DEVEPTISRx.ERRORTRANS).
Bit 9 – DATAXE DataX Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.DATAXEC = 1. This disables the DATAX interrupt.
1
Set when the USBHS_DEVEPTIERx.DATAXES = 1. This enables the DATAX interrupt (see DTSEQ
bits).
Bit 8 – MDATAE MData Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.MDATAEC = 1. This disables the Multiple DATA interrupt.
1
Set when the USBHS_DEVEPTIERx.MDATAES = 1. This enables the Multiple DATA interrupt (see
DTSEQ bits).
Bit 7 – SHORTPACKETE Short Packet Interrupt
If this bit is set for non-control IN endpoints, a short packet transmission is guaranteed upon ending a DMA transfer,
thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, provided that the End of DMA Buffer
Output Enable (END_B_EN) bit and the Automatic Switch (AUTOSW) bit = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 805
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
Description
Cleared when USBHS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHORTPACKET).
Set when USBHS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHORTPACKET).
Bit 6 – CRCERRE CRC Error Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.CRCERREC = 1. This disables the CRC Error interrupt
(USBHS_DEVEPTISRx.CRCERRI).
1
Set when USBHS_DEVEPTIERx.CRCERRES = 1. This enables the CRC Error interrupt
(USBHS_DEVEPTISRx.CRCERRI).
Bit 5 – OVERFE Overflow Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.OVERFEC = 1. This disables the Overflow interrupt
(USBHS_DEVEPTISRx.OVERFI).
1
Set when USBHS_DEVEPTIERx.OVERFES = 1. This enables the Overflow interrupt
(USBHS_DEVEPTISRx.OVERFI).
Bit 4 – HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt
Value
Description
0
Cleared when the USBHS_DEVEPTIDRx.HBISOFLUSHEC bit disables the HBISOFLUSHI interrupt.
1
Set when USBHS_DEVEPTIERx.HBISOFLUSHES = 1. This enables the HBISOFLUSHI interrupt.
Bit 3 – HBISOINERRE High Bandwidth Isochronous IN Error Interrupt
Value
Description
0
Cleared when the USBHS_DEVEPTIDRx.HBISOINERREC bit disables the HBISOINERRI interrupt.
1
Set when USBHS_DEVEPTIERx.HBISOINERRES = 1. This enables the HBISOINERRI interrupt.
Bit 2 – UNDERFE Underflow Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.UNDERFEC = 1. This disables the Underflow interrupt
(USBHS_DEVEPTISRx.UNDERFI).
1
Set when USBHS_DEVEPTIERx.UNDERFES = 1. This enables the Underflow interrupt
(USBHS_DEVEPTISRx.UNDERFI).
Bit 1 – RXOUTE Received OUT Data Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.RXOUTEC = 1. This disables the Received OUT Data interrupt
(USBHS_DEVEPTISRx.RXOUTI).
1
Set when USBHS_DEVEPTIERx.RXOUTES = 1. This enables the Received OUT Data interrupt
(USBHS_DEVEPTISRx.RXOUTI).
Bit 0 – TXINE Transmitted IN Data Interrupt
Value
Description
0
Cleared when USBHS_DEVEPTIDRx.TXINEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_DEVEPTISRx.TXINI).
1
Set when USBHS_DEVEPTIERx.TXINES = 1. This enables the Transmitted IN Data interrupt
(USBHS_DEVEPTISRx.TXINI).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 806
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.23 Device Endpoint Interrupt Disable Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIDRx
0x0220 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
STALLRQC
R/W
0
18
17
NYETDISC
R/W
0
16
EPDISHDMAC
R/W
0
15
14
FIFOCONC
R/W
0
13
12
NBUSYBKEC
R/W
0
11
10
9
8
6
STALLEDEC
5
OVERFEC
4
NAKINEC
3
NAKOUTEC
2
RXSTPEC
1
RXOUTEC
0
TXINEC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TEC
Access
R/W
Reset
0
Bit 19 – STALLRQC STALL Request Clear
Bit 17 – NYETDISC NYET Token Disable Clear
Bit 16 – EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear
Bit 14 – FIFOCONC FIFO Control Clear
Bit 12 – NBUSYBKEC Number of Busy Banks Interrupt Clear
Bit 7 – SHORTPACKETEC Shortpacket Interrupt Clear
Bit 6 – STALLEDEC STALLed Interrupt Clear
Bit 5 – OVERFEC Overflow Interrupt Clear
Bit 4 – NAKINEC NAKed IN Interrupt Clear
Bit 3 – NAKOUTEC NAKed OUT Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 807
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 2 – RXSTPEC Received SETUP Interrupt Clear
Bit 1 – RXOUTEC Received OUT Data Interrupt Clear
Bit 0 – TXINEC Transmitted IN Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 808
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.24 Device Endpoint Interrupt Disable Register (Isochronous Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIDRx (ISOENPT)
0x0220 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EPDISHDMAC
R/W
0
15
14
FIFOCONC
13
12
NBUSYBKEC
11
10
ERRORTRANS
EC
R/W
0
9
DATAXEC
8
MDATEC
R/W
0
R/W
0
2
UNDERFEC
1
RXOUTEC
0
TXINEC
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TEC
Access
R/W
Reset
0
R/W
0
R/W
0
6
CRCERREC
5
OVERFEC
R/W
0
R/W
0
4
3
HBISOFLUSHE HBISOINERRE
C
C
R/W
R/W
0
0
Bit 16 – EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear
Bit 14 – FIFOCONC FIFO Control Clear
Bit 12 – NBUSYBKEC Number of Busy Banks Interrupt Clear
Bit 10 – ERRORTRANSEC Transaction Error Interrupt Clear
Bit 9 – DATAXEC DataX Interrupt Clear
Bit 8 – MDATEC MData Interrupt Clear
Bit 7 – SHORTPACKETEC Shortpacket Interrupt Clear
Bit 6 – CRCERREC CRC Error Interrupt Clear
Bit 5 – OVERFEC Overflow Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 809
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 4 – HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear
Bit 3 – HBISOINERREC High Bandwidth Isochronous IN Error Interrupt Clear
Bit 2 – UNDERFEC Underflow Interrupt Clear
Bit 1 – RXOUTEC Received OUT Data Interrupt Clear
Bit 0 – TXINEC Transmitted IN Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 810
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.25 Device Endpoint Interrupt Enable Register (Control, Bulk, Interrupt Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIERx
0x01F0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_DEVEPTIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
STALLRQS
R/W
0
18
RSTDTS
R/W
0
17
NYETDISS
R/W
0
16
EPDISHDMAS
R/W
0
15
14
FIFOCONS
R/W
0
13
KILLBKS
R/W
0
12
NBUSYBKES
R/W
0
11
10
9
8
6
STALLEDES
5
OVERFES
4
NAKINES
3
NAKOUTES
2
RXSTPES
1
RXOUTES
0
TXINES
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TES
Access
R/W
Reset
0
Bit 19 – STALLRQS STALL Request Enable
Bit 18 – RSTDTS Reset Data Toggle Enable
Bit 17 – NYETDISS NYET Token Disable Enable
Bit 16 – EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable
Bit 14 – FIFOCONS FIFO Control
Bit 13 – KILLBKS Kill IN Bank
Bit 12 – NBUSYBKES Number of Busy Banks Interrupt Enable
Bit 7 – SHORTPACKETES Short Packet Interrupt Enable
Bit 6 – STALLEDES STALLed Interrupt Enable
Bit 5 – OVERFES Overflow Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 811
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 4 – NAKINES NAKed IN Interrupt Enable
Bit 3 – NAKOUTES NAKed OUT Interrupt Enable
Bit 2 – RXSTPES Received SETUP Interrupt Enable
Bit 1 – RXOUTES Received OUT Data Interrupt Enable
Bit 0 – TXINES Transmitted IN Data Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 812
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.26 Device Endpoint Interrupt Enable Register (Isochronous Endpoints)
Name:
Offset:
Reset:
Property:
USBHS_DEVEPTIERx (ISOENPT)
0x01F0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_DEVEPTIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDTS
R/W
0
17
16
EPDISHDMAS
R/W
0
15
14
FIFOCONS
13
KILLBKS
12
NBUSYBKES
11
9
DATAXES
8
MDATAES
R/W
0
R/W
0
R/W
0
10
ERRORTRANS
ES
R/W
0
R/W
0
R/W
0
6
CRCERRES
5
OVERFES
2
UNDERFES
1
RXOUTES
0
TXINES
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TES
Access
R/W
Reset
0
4
3
HBISOFLUSHE HBISOINERRE
S
S
R/W
R/W
0
0
Bit 18 – RSTDTS Reset Data Toggle Enable
Bit 16 – EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable
Bit 14 – FIFOCONS FIFO Control
Bit 13 – KILLBKS Kill IN Bank
Bit 12 – NBUSYBKES Number of Busy Banks Interrupt Enable
Bit 10 – ERRORTRANSES Transaction Error Interrupt Enable
Bit 9 – DATAXES DataX Interrupt Enable
Bit 8 – MDATAES MData Interrupt Enable
Bit 7 – SHORTPACKETES Short Packet Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 813
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 6 – CRCERRES CRC Error Interrupt Enable
Bit 5 – OVERFES Overflow Interrupt Enable
Bit 4 – HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable
Bit 3 – HBISOINERRES High Bandwidth Isochronous IN Error Interrupt Enable
Bit 2 – UNDERFES Underflow Interrupt Enable
Bit 1 – RXOUTES Received OUT Data Interrupt Enable
Bit 0 – TXINES Transmitted IN Data Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 814
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.27 Device DMA Channel x Next Descriptor Address Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
USBHS_DEVDMANXTDSCx
0x0300 + (x-1)*0x10 [x=1..7]
0
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
NXT_DSC_ADD[31:24]
R/W
R/W
0
0
20
19
NXT_DSC_ADD[23:16]
R/W
R/W
0
0
12
11
NXT_DSC_ADD[15:8]
R/W
R/W
0
0
4
3
NXT_DSC_ADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – NXT_DSC_ADD[31:0] Next Descriptor Address
This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to
3 of the address must be equal to zero.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 815
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.28 Device DMA Channel x Address Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
USBHS_DEVDMAADDRESSx
0x0304 + (x-1)*0x10 [x=1..7]
0
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
BUFF_ADD[31:24]
R/W
R/W
0
0
20
19
BUFF_ADD[23:16]
R/W
R/W
0
0
12
11
BUFF_ADD[15:8]
R/W
R/W
0
0
4
3
BUFF_ADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – BUFF_ADD[31:0] Buffer Address
This field determines the AHB bus starting address of a DMA channel transfer.
Channel start and end addresses may be aligned on any byte boundary.
The firmware can write this field only when the USBHS_DEVDMASTATUS.CHANN_ENB bit is clear.
This field is updated at the end of the address phase of the current access to the AHB bus. It is incremented by
the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not
aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the
channel buffer. The packet end address is either the channel end address or the latest channel address accessed in
the channel buffer.
The channel start address is written by software or loaded from the descriptor. The channel end address
is either determined by the end of buffer or the USB device, or by the USB end of transfer if the
USBHS_DEVDMACONTROLx.END_TR_EN bit is set.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 816
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.29 Device DMA Channel x Control Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
USBHS_DEVDMACONTROLx
0x0308 + (x-1)*0x10 [x=1..7]
0
Read/Write
31
30
29
28
27
BUFF_LENGTH[15:8]
R/W
R/W
0
0
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
6
DESC_LD_IT
R/W
0
5
END_BUFFIT
R/W
0
4
END_TR_IT
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
3
END_B_EN
R/W
0
2
END_TR_EN
R/W
0
1
LDNXT_DSC
R/W
0
0
CHANN_ENB
R/W
0
20
19
BUFF_LENGTH[7:0]
R/W
R/W
0
0
Access
Reset
Bit
7
BURST_LCK
Access
R/W
Reset
0
Bits 31:16 – BUFF_LENGTH[15:0] Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size
(32 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0,
but the transfer end may occur earlier under USB device control.
When this field is written, the USBHS_DEVDMASTATUSx.BUFF_COUNT field is updated with the write value.
Note: 1. Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
Note: 2. For reliability, it is recommended to wait for both the USBHS_DEVDMASTATUSx.CHAN_ACT and the
USBHS_DEVDMASTATUSx.CHAN_ENB flags to be at 0, thus ensuring the channel has been stopped before issuing
a command other than “Stop Now”.
Bit 7 – BURST_LCK Burst Lock Enable
Value
Description
0
The DMA never locks bus access.
1
USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and
maximization of fly-by AHB burst duration.
Bit 6 – DESC_LD_IT Descriptor Loaded Interrupt Enable
Value
Description
0
USBHS_DEVDMASTATUSx.DESC_LDST rising does not trigger any interrupt.
1
An interrupt is generated when a descriptor has been loaded from the bus.
Bit 5 – END_BUFFIT End of Buffer Interrupt Enable
Value
Description
0
USBHS_DEVDMA_STATUSx.END_BF_ST rising does not trigger any interrupt.
1
An interrupt is generated when USBHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.
Bit 4 – END_TR_IT End of Transfer Interrupt Enable
Use when the receive size is unknown.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 817
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
Description
USBHS device-initiated buffer transfer completion does not trigger any interrupt at
USBHS_DEVDMASTATUSx.END_TR_ST rising.
An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer
transfer.
Bit 3 – END_B_EN End of Buffer Enable Control
This is mainly for short packet IN validations initiated by the DMA reaching end of buffer, but can be used for OUT
packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
Value
Description
0
DMA Buffer End has no impact on USB packet transfer.
1
The endpoint can validate the packet (according to the values programmed in the
USBHS_DEVEPTCFGx.AUTOSW and USBHS_DEVEPTIERx.SHORTPACKETES fields) at DMA
Buffer End, i.e., when USBHS_DEVDMASTATUS.BUFF_COUNT reaches 0.
Bit 2 – END_TR_EN End of Transfer Enable Control (OUT transfers only)
When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX)
closes the current buffer and the USBHS_DEVDMASTATUSx.END_TR_ST flag is raised.
This is intended for a USBHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS
microframe data buffer closure.
Value
Description
0
The USB end of transfer is ignored.
1
The USBHS device can put an end to the current buffer transfer.
Bit 1 – LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command
If the CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request.
DMA Channel Control Command Summary:
Value LDNXT_DSC
0
0
1
1
Value
0
1
Value CHANN_ENB
0
1
0
1
Name
STOP_NOW
RUN_AND_STOP
LOAD_NEXT_DESC
RUN_AND_LINK
Description
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
Description
No channel register is loaded after the end of the channel transfer.
The channel controller loads the next descriptor after the end of the current transfer, i.e., when the
USBHS_DEVDMASTATUS.CHANN_ENB bit is reset.
Bit 0 – CHANN_ENB Channel Enable Command
Value
Description
0
The DMA channel is disabled at end of transfer and no transfer occurs upon request. This bit is also
cleared by hardware when the channel source bus is disabled at end of buffer.
If the LDNXT_DSC bit has been cleared by descriptor loading, the firmware must set the corresponding
CHANN_ENB bit to start the described transfer, if needed.
If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read
and/or written reliably as soon as both USBHS_DEVDMASTATUS.CHANN_ENB and CHANN_ACT
flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it
is empty, then the USBHS_DEVDMASTATUS.CHANN_ENB bit is cleared.
1
If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped
(no data transfer occurs) and the next descriptor is immediately loaded.
The USBHS_DEVDMASTATUS.CHANN_ENB bit is set, thus enabling the DMA channel data transfer.
Then, any pending request starts the transfer. This may be used to start or resume any requested
transfer.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 818
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.30 Device DMA Channel x Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
USBHS_DEVDMASTATUSx
0x030C + (x-1)*0x10 [x=1..7]
0
Read/Write
31
30
29
28
27
BUFF_COUNT[15:8]
R/W
R/W
0
0
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
7
6
DESC_LDST
R/W
0
5
END_BF_ST
R/W
0
4
END_TR_ST
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
3
2
1
CHANN_ACT
R/W
0
0
CHANN_ENB
R/W
0
20
19
BUFF_COUNT[7:0]
R/W
R/W
0
0
Access
Reset
Bit
Access
Reset
Bits 31:16 – BUFF_COUNT[15:0] Buffer Byte Count
This field determines the current number of bytes still to be transferred for this buffer.
This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word
boundary.
At the end of buffer, the DMA accesses the USBHS device only for the number of bytes needed to complete it.
Note: For OUT endpoints, if the receive buffer byte length (BUFF_LENGTH) has been defaulted to zero because
the USB transfer length is unknown, the actual buffer byte length received is 0x10000-BUFF_COUNT.
Bit 6 – DESC_LDST Descriptor Loaded Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when a descriptor has been loaded from the system bus.
Bit 5 – END_BF_ST End of Channel Buffer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when the BUFF_COUNT count-down reaches zero.
Bit 4 – END_TR_ST End of Channel Transfer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when the last packet transfer is complete, if the USBHS device has ended the
transfer.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 819
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – CHANN_ACT Channel Active Status
When a packet transfer is ended, this bit is automatically reset.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel
descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor.
Value
Description
0
The DMA channel is no longer trying to source the packet data.
1
The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority
requesting channel.
Bit 0 – CHANN_ENB Channel Enable Status
When any transfer is ended either due to an elapsed byte count or to completion of a USBHS device-initiated
transfer, this bit is automatically reset.
This bit is normally set or cleared by writing into the USBHS_DEVDMACONTROLx.CHANN_ENB bit field either by
software or descriptor loading.
If a channel request is currently serviced when the USBHS_DEVDMACONTROLx.CHANN_ENB bit is cleared, the
DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
Value
Description
0
If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the
USBHS_DEVDMACONTROLx.LDNXT_DSC bit is set.
1
If set, the DMA channel is currently enabled and transfers data upon request.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 820
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.31 Host General Control Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_HSTCTRL
0x0400
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
11
10
RESUME
R/W
0
9
RESET
R/W
0
8
SOFE
R/W
0
7
6
3
2
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
13
12
SPDCONF[1:0]
R/W
R/W
0
0
5
4
Access
Reset
Bits 13:12 – SPDCONF[1:0] Mode Configuration
This field contains the host speed capability:.
Value
Name
Description
0
NORMAL
The host starts in Full-speed mode and performs a high-speed reset to switch to
High-speed mode if the downstream peripheral is high-speed capable.
1
LOW_POWER For a better consumption, if high speed is not needed.
2
HIGH_SPEED Forced high speed.
3
FORCED_FS The host remains in Full-speed mode whatever the peripheral speed capability.
Bit 10 – RESUME Send USB Resume
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
This bit should be written to one only when the start of frame generation is enabled (SOFE = 1).
Value
Description
0
No effect.
1
Generates a USB Resume on the USB bus.
Bit 9 – RESET Send USB Reset
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (USBHS_HSTISR.DDISCI = 1)
whereas a USB Reset is being sent.
Value
Description
0
No effect.
1
Generates a USB Reset on the USB bus.
Bit 8 – SOFE Start of Frame Generation Enable
This bit is set when a USB reset is requested or an upstream resume interrupt is detected
(USBHS_HSTISR.TXRSMI).
Value
Description
0
Disables the SOF generation and leaves the USB bus in idle state.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 821
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
1
Description
Generates SOF on the USB bus in Full- or High-speed mode and sends “keep alive” signals in
Low-speed mode.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 822
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.32 Host Global Interrupt Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
USBHS_HSTISR
0x0404
0x00000000
Read-only
31
DMA_6
R
0
30
DMA_5
R
0
29
DMA_4
R
0
28
DMA_3
R
0
27
DMA_2
R
0
26
DMA_1
R
0
25
DMA_0
R
0
24
23
22
21
20
19
18
17
PEP_9
R
0
16
PEP_8
R
0
15
PEP_7
R
0
14
PEP_6
R
0
13
PEP_5
R
0
12
PEP_4
R
0
11
PEP_3
R
0
10
PEP_2
R
0
9
PEP_1
R
0
8
PEP_0
R
0
7
6
HWUPI
R
0
5
HSOFI
R
0
4
RXRSMI
R
0
3
RSMEDI
R
0
2
RSTI
R
0
1
DDISCI
R
0
0
DCONNI
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt
Value
Description
0
Cleared when the USBHS_HSTDMASTATUSx interrupt source is cleared.
1
Set when an interrupt is triggered by the DMA channel x. This triggers a USB interrupt if the
corresponding bit in USBHS_HSTIMR = 1.
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PEP_ Pipe x Interrupt
Value
Description
0
Cleared when the interrupt source is served.
1
Set when an interrupt is triggered by pipe x (USBHS_HSTPIPISRx). This triggers a USB interrupt if the
corresponding bit in USBHS_HSTIMR = 1.
Bit 6 – HWUPI Host Wakeup Interrupt
This bit is set when the host controller is in Suspend mode (SOFE = 0) and an upstream resume from the peripheral
is detected.
This bit is set when the host controller is in Suspend mode (SOFE = 0) and a peripheral disconnection is detected.
This interrupt is generated even if the clock is frozen by the USBHS_CTRL.FRZCLK bit.
Bit 5 – HSOFI Host Start of Frame Interrupt
Value
Description
0
Cleared when USBHS_HSTICR.HSOFIC = 1.
1
Set when a SOF is issued by the host controller. This triggers a USB interrupt when HSOFE = 1. When
using the host controller in Low-speed mode, this bit is also set when a keep-alive is sent.
Bit 4 – RXRSMI Upstream Resume Received Interrupt
Value
Description
0
Cleared when USBHS_HSTICR.RXRSMIC = 1.
1
Set when an Upstream Resume has been received from the device.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 823
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 3 – RSMEDI Downstream Resume Sent Interrupt
Value
Description
0
Cleared when USBHS_HSTICR.RSMEDIC = 1.
1
Set when a Downstream Resume has been sent to the device.
Bit 2 – RSTI USB Reset Sent Interrupt
Value
Description
0
Cleared when USBHS_HSTICR.RSTIC = 1.
1
Set when a USB Reset has been sent to the device.
Bit 1 – DDISCI Device Disconnection Interrupt
Value
Description
0
Cleared when USBHS_HSTICR.DDISCIC = 1.
1
Set when the device has been removed from the USB bus.
Bit 0 – DCONNI Device Connection Interrupt
Value
Description
0
Cleared when USBHS_HSTICR.DCONNIC = 1.
1
Set when a new device has been connected to the USB bus.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 824
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.33 Host Global Interrupt Clear Register
Name:
Offset:
Property:
USBHS_HSTICR
0x0408
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTISR.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
HWUPIC
W
5
HSOFIC
W
4
RXRSMIC
W
3
RSMEDIC
W
2
RSTIC
W
1
DDISCIC
W
0
DCONNIC
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 6 – HWUPIC Host Wakeup Interrupt Clear
Bit 5 – HSOFIC Host Start of Frame Interrupt Clear
Bit 4 – RXRSMIC Upstream Resume Received Interrupt Clear
Bit 3 – RSMEDIC Downstream Resume Sent Interrupt Clear
Bit 2 – RSTIC USB Reset Sent Interrupt Clear
Bit 1 – DDISCIC Device Disconnection Interrupt Clear
Bit 0 – DCONNIC Device Connection Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 825
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.34 Host Global Interrupt Set Register
Name:
Offset:
Property:
USBHS_HSTIFR
0x040C
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTISR, which may be useful for test or debug purposes.
Bit
Access
Reset
Bit
31
DMA_6
W
30
DMA_5
W
29
DMA_4
W
28
DMA_3
W
27
DMA_2
W
26
DMA_1
W
25
DMA_0
W
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
HWUPIS
W
5
HSOFIS
W
4
RXRSMIS
W
3
RSMEDIS
W
2
RSTIS
W
1
DDISCIS
W
0
DCONNIS
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Set
Bit 6 – HWUPIS Host Wakeup Interrupt Set
Bit 5 – HSOFIS Host Start of Frame Interrupt Set
Bit 4 – RXRSMIS Upstream Resume Received Interrupt Set
Bit 3 – RSMEDIS Downstream Resume Sent Interrupt Set
Bit 2 – RSTIS USB Reset Sent Interrupt Set
Bit 1 – DDISCIS Device Disconnection Interrupt Set
Bit 0 – DCONNIS Device Connection Interrupt Set
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 826
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.35 Host Global Interrupt Mask Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
USBHS_HSTIMR
0x0410
0x00000000
Read-only
31
DMA_6
R
0
30
DMA_5
R
0
29
DMA_4
R
0
28
DMA_3
R
0
27
DMA_2
R
0
26
DMA_1
R
0
25
DMA_0
R
0
24
23
22
21
20
19
18
17
PEP_9
R
0
16
PEP_8
R
0
15
PEP_7
R
0
14
PEP_6
R
0
13
PEP_5
R
0
12
PEP_4
R
0
11
PEP_3
R
0
10
PEP_2
R
0
9
PEP_1
R
0
8
PEP_0
R
0
7
6
HWUPIE
R
0
5
HSOFIE
R
0
4
RXRSMIE
R
0
3
RSMEDIE
R
0
2
RSTIE
R
0
1
DDISCIE
R
0
0
DCONNIE
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Enable
Value
Description
0
Cleared when the corresponding bit in USBHS_HSTIDR = 1. This disables the DMA Channel x
Interrupt (USBHS_HSTISR.DMA_x).
1
Set when the corresponding bit in USBHS_HSTIER = 1. This enables the DMA Channel x Interrupt
(USBHS_HSTISR.DMA_x).
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PEP_ Pipe x Interrupt Enable
Value
Description
0
Cleared when PEP_x = 1. This disables the Pipe x Interrupt (PEP_x).
1
Set when the corresponding bit in USBHS_HSTIER = 1. This enables the Pipe x Interrupt
(USBHS_HSTISR.PEP_x).
Bit 6 – HWUPIE Host Wakeup Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTIDR.HWUPIEC = 1. This disables the Host Wakeup Interrupt
(USBHS_HSTISR.HWUPI).
1
Set when USBHS_HSTIER.HWUPIES = 1. This enables the Host Wakeup Interrupt
(USBHS_HSTISR.HWUPI).
Bit 5 – HSOFIE Host Start of Frame Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTIDR.HSOFIEC = 1. This disables the Host Start of Frame interrupt
(USBHS_HSTISR.HSOFI).
1
Set when USBHS_HSTIER.HSOFIES= 1. This enables the Host Start of Frame interrupt
(USBHS_HSTISR.HSOFI).
Bit 4 – RXRSMIE Upstream Resume Received Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 827
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
Description
Cleared when USBHS_HSTIDR.RXRSMIEC= 1. This disables the Downstream Resume interrupt
(USBHS_HSTISR.RXRSMI).
Set when USBHS_HSTIER.RXRSMIES = 1. This enables the Upstream Resume Received interrupt
(USBHS_HSTISR.RXRSMI).
Bit 3 – RSMEDIE Downstream Resume Sent Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTIDR.RSMEDIEC = 1. This disables the Downstream Resume interrupt
(USBHS_HSTISR.RSMEDI).
1
Set when USBHS_HSTIER.RSMEDIES = 1. This enables the Downstream Resume interrupt
(USBHS_HSTISR.RSMEDI).
Bit 2 – RSTIE USB Reset Sent Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTIDR.RSTIEC = 1. This disables the USB Reset Sent interrupt
(USBHS_HSTISR.RSTI).
1
Set when USBHS_HSTIER.RSTIES = 1. This enables the USB Reset Sent interrupt
(USBHS_HSTISR.RSTI).
Bit 1 – DDISCIE Device Disconnection Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTIDR.DDISCIEC = 1. This disables the Device Disconnection interrupt
(USBHS_HSTISR.DDISCI).
1
Set when USBHS_HSTIER.DDISCIES = 1. This enables the Device Disconnection interrupt
(USBHS_HSTISR.DDISCI).
Bit 0 – DCONNIE Device Connection Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTIDR.DCONNIEC = 1. This disables the Device Connection interrupt
(USBHS_HSTISR.DCONNI).
1
Set when USBHS_HSTIER.DCONNIES = 1. This enables the Device Connection interrupt
(USBHS_HSTISR.DCONNI).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 828
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.36 Host Global Interrupt Disable Register
Name:
Offset:
Property:
USBHS_HSTIDR
0x0414
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTIMR.
Bit
Access
Reset
Bit
31
DMA_6
W
30
DMA_5
W
29
DMA_4
W
28
DMA_3
W
27
DMA_2
W
26
DMA_1
W
25
DMA_0
W
24
23
22
21
20
19
18
17
PEP_9
W
16
PEP_8
W
15
PEP_7
W
14
PEP_6
W
13
PEP_5
W
12
PEP_4
W
11
PEP_3
W
10
PEP_2
W
9
PEP_1
W
8
PEP_0
W
7
6
HWUPIEC
W
5
HSOFIEC
W
4
RXRSMIEC
W
3
RSMEDIEC
W
2
RSTIEC
W
1
DDISCIEC
W
0
DCONNIEC
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Disable
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PEP_ Pipe x Interrupt Disable
Bit 6 – HWUPIEC Host Wakeup Interrupt Disable
Bit 5 – HSOFIEC Host Start of Frame Interrupt Disable
Bit 4 – RXRSMIEC Upstream Resume Received Interrupt Disable
Bit 3 – RSMEDIEC Downstream Resume Sent Interrupt Disable
Bit 2 – RSTIEC USB Reset Sent Interrupt Disable
Bit 1 – DDISCIEC Device Disconnection Interrupt Disable
Bit 0 – DCONNIEC Device Connection Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 829
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.37 Host Global Interrupt Enable Register
Name:
Offset:
Property:
USBHS_HSTIER
0x0418
Write-only
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTISR.
Bit
Access
Reset
Bit
31
DMA_6
W
30
DMA_5
W
29
DMA_4
W
28
DMA_3
W
27
DMA_2
W
26
DMA_1
W
25
DMA_0
W
24
23
22
21
20
19
18
17
PEP_9
W
16
PEP_8
W
15
PEP_7
W
14
PEP_6
W
13
PEP_5
W
12
PEP_4
W
11
PEP_3
W
10
PEP_2
W
9
PEP_1
W
8
PEP_0
W
7
6
HWUPIES
W
5
HSOFIES
W
4
RXRSMIES
W
3
RSMEDIES
W
2
RSTIES
W
1
DDISCIES
W
0
DCONNIES
W
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 25, 26, 27, 28, 29, 30, 31 – DMA_ DMA Channel x Interrupt Enable
Bits 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 – PEP_ Pipe x Interrupt Enable
Bit 6 – HWUPIES Host Wakeup Interrupt Enable
Bit 5 – HSOFIES Host Start of Frame Interrupt Enable
Bit 4 – RXRSMIES Upstream Resume Received Interrupt Enable
Bit 3 – RSMEDIES Downstream Resume Sent Interrupt Enable
Bit 2 – RSTIES USB Reset Sent Interrupt Enable
Bit 1 – DDISCIES Device Disconnection Interrupt Enable
Bit 0 – DCONNIES Device Connection Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 830
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.38 Host Frame Number Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_HSTFNUM
0x0420
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
9
8
R/W
0
R/W
0
R/W
0
R/W
0
5
FNUM[4:0]
R/W
0
4
3
2
1
MFNUM[2:0]
R/W
0
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
R/W
0
R/W
0
20
19
FLENHIGH[7:0]
R/W
R/W
0
0
11
10
FNUM[10:5]
R/W
R/W
0
0
R/W
0
Bits 23:16 – FLENHIGH[7:0] Frame Length
In High-speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30 MHz, the
counter length is 3750 to ensure a SOF generation every 125 μs).
Bits 13:3 – FNUM[10:0] Frame Number
This field contains the current SOF number.
This field can be written. In this case, the MFNUM field is reset to zero.
Bits 2:0 – MFNUM[2:0] Micro Frame Number
This field contains the current microframe number (can vary from 0 to 7), updated every 125 μs.
When operating in Full-speed mode, this field is tied to zero.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 831
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.39 Host Address 1 Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_HSTADDR1
0x0424
0x00000000
Read/Write
31
Access
Reset
Bit
23
Access
Reset
Bit
15
Access
Reset
Bit
7
Access
Reset
30
29
28
R/W
0
R/W
0
R/W
0
22
21
20
R/W
0
R/W
0
R/W
0
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
27
HSTADDRP3[6:0]
R/W
0
19
HSTADDRP2[6:0]
R/W
0
11
HSTADDRP1[6:0]
R/W
0
3
HSTADDRP0[6:0]
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 30:24 – HSTADDRP3[6:0] USB Host Address
This field contains the address of the Pipe3 of the USB device.
This field is cleared when a USB reset is requested.
Bits 22:16 – HSTADDRP2[6:0] USB Host Address
This field contains the address of the Pipe2 of the USB device.
This field is cleared when a USB reset is requested.
Bits 14:8 – HSTADDRP1[6:0] USB Host Address
This field contains the address of the Pipe1 of the USB device.
This field is cleared when a USB reset is requested.
Bits 6:0 – HSTADDRP0[6:0] USB Host Address
This field contains the address of the Pipe0 of the USB device.
This field is cleared when a USB reset is requested.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 832
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.40 Host Address 2 Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_HSTADDR2
0x0428
0x00000000
Read/Write
31
Access
Reset
Bit
23
Access
Reset
Bit
15
Access
Reset
Bit
7
Access
Reset
30
29
28
R/W
0
R/W
0
R/W
0
22
21
20
R/W
0
R/W
0
R/W
0
14
13
12
R/W
0
R/W
0
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
27
HSTADDRP7[6:0]
R/W
0
19
HSTADDRP6[6:0]
R/W
0
11
HSTADDRP5[6:0]
R/W
0
3
HSTADDRP4[6:0]
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 30:24 – HSTADDRP7[6:0] USB Host Address
This field contains the address of the Pipe7 of the USB device.
This field is cleared when a USB reset is requested.
Bits 22:16 – HSTADDRP6[6:0] USB Host Address
This field contains the address of the Pipe6 of the USB device.
This field is cleared when a USB reset is requested.
Bits 14:8 – HSTADDRP5[6:0] USB Host Address
This field contains the address of the Pipe5 of the USB device.
This field is cleared when a USB reset is requested.
Bits 6:0 – HSTADDRP4[6:0] USB Host Address
This field contains the address of the Pipe4 of the USB device.
This field is cleared when a USB reset is requested.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 833
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.41 Host Address 3 Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_HSTADDR3
0x042C
0x00000000
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
10
9
8
R/W
0
R/W
0
R/W
0
11
HSTADDRP9[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
3
HSTADDRP8[6:0]
R/W
0
Bits 14:8 – HSTADDRP9[6:0] USB Host Address
This field contains the address of the Pipe9 of the USB device.
This field is cleared when a USB reset is requested.
Bits 6:0 – HSTADDRP8[6:0] USB Host Address
This field contains the address of the Pipe8 of the USB device.
This field is cleared when a USB reset is requested.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 834
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.42 Host Pipe Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_HSTPIP
0x0041C
0x00000000
Read/Write
31
30
29
28
27
26
25
24
PRST8
R/W
0
23
PRST7
R/W
0
22
PRST6
R/W
0
21
PRST5
R/W
0
20
PRST4
R/W
0
19
PRST3
R/W
0
18
PRST2
R/W
0
17
PRST1
R/W
0
16
PRST0
R/W
0
15
14
13
12
11
10
9
8
PEN8
R/W
0
7
PEN7
R/W
0
6
PEN6
R/W
0
5
PEN5
R/W
0
4
PEN4
R/W
0
3
PEN3
R/W
0
2
PEN2
R/W
0
1
PEN1
R/W
0
0
PEN0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24 – PRST Pipe x Reset
Value
Description
0
Completes the reset operation and allows to start using the FIFO.
1
Resets the Pipe x FIFO. This resets the pipe x registers (USBHS_HSTPIPCFGx,
USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), but not the pipe configuration (ALLOC, PBK, PSIZE,
PTOKEN, PTYPE, PEPNUM, INTFRQ). The whole pipe mechanism (FIFO counter, reception,
transmission, etc.) is reset, apart from the Data Toggle management. The pipe configuration remains
active and the pipe is still enabled.
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8 – PEN Pipe x Enable
Value
Description
0
Disables Pipe x, which forces the Pipe x state to inactive and resets the pipe x registers
(USBHS_HSTPIPCFGx, USBHS_HSTPIPISRx, USBHS_HSTPIPIMRx), but not the pipe configuration
(USBHS_HSTPIPCFGx.ALLOC, USBHS_HSTPIPCFGx.PBK, USBHS_HSTPIPCFGx.PSIZE).
1
Enables Pipe x.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 835
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.43 Host Pipe x Configuration Register
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPCFGx
0x0500 + x*0x04 [x=0..8]
0
Read/Write
For High-speed Bulk-out Pipe, see ”Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control
Pipe)”.
Bit
Access
Reset
Bit
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
28
27
INTFRQ[7:0]
R/W
R/W
0
0
20
Access
Reset
Bit
19
14
13
12
11
Bit
7
Access
Reset
6
0
R/W
0
R/W
0
5
PSIZE[2:0]
0
4
24
R/W
0
R/W
0
R/W
0
10
AUTOSW
R/W
0
PTYPE[1:0]
Access
Reset
25
18
17
PEPNUM[3:0]
R/W
R/W
0
0
R/W
0
15
26
3
2
PBK[1:0]
0
R/W
0
R/W
0
16
R/W
0
9
8
PTOKEN[1:0]
R/W
R/W
0
0
1
ALLOC
R/W
0
0
Bits 31:24 – INTFRQ[7:0] Pipe Interrupt Request Frequency
This field contains the maximum value in milliseconds of the polling period for an Interrupt Pipe.
This value has no effect for a non-Interrupt Pipe.
This field is cleared upon sending a USB reset.
Bits 19:16 – PEPNUM[3:0] Pipe Endpoint Number
This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 9.
This field is cleared upon sending a USB reset.
Bits 13:12 – PTYPE[1:0] Pipe Type
This field contains the pipe type.
This field is cleared upon sending a USB reset.
Value
Name
0
CTRL
1
ISO
2
BLK
3
INTRPT
Description
Control
Isochronous
Bulk
Interrupt
Bit 10 – AUTOSW Automatic Switch
This bit is cleared upon sending a USB reset.
Value
Description
0
The automatic bank switching is disabled.
1
The automatic bank switching is enabled.
Bits 9:8 – PTOKEN[1:0] Pipe Token
This field contains the pipe token.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 836
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
2
3
Name
SETUP
IN
OUT
-
Bits 6:4 – PSIZE[2:0] Pipe Size
This field contains the size of each pipe bank.
This field is cleared upon sending a USB reset.
Value
Name
0
8_BYTE
1
16_BYTE
2
32_BYTE
3
64_BYTE
4
128_BYTE
5
256_BYTE
6
512_BYTE
7
1024_BYTE
Description
SETUP
IN
OUT
Reserved
Description
8 bytes
16 bytes
32 bytes
64 bytes
128 bytes
256 bytes
512 bytes
1024 bytes
Bits 3:2 – PBK[1:0] Pipe Banks
This field contains the number of banks for the pipe.
For control pipes, a single-bank pipe (0b00) should be selected.
This field is cleared upon sending a USB reset.
Value
Name
Description
0
1_BANK
Single-bank pipe
1
2_BANK
Double-bank pipe
2
3_BANK
Triple-bank pipe
3
Reserved
Bit 1 – ALLOC Pipe Memory Allocate
This bit is cleared when a USB Reset is requested.
Refer to ”DPRAM Management” for more details.
Value
Description
0
Frees the pipe memory.
1
Allocates the pipe memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 837
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.44 Host Pipe x Configuration Register (High-speed Bulk-out or High-speed Control Pipe)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPCFGx (HSBOHSCP)
0x0500 + x*0x04 [x=0..8]
0
Read/Write
This configuration is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
Bit
Access
Reset
Bit
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
28
27
BINTERVAL[7:0]
R/W
R/W
0
0
Access
Reset
Bit
15
14
20
PINGEN
R/W
0
R/W
0
12
11
13
19
Bit
7
Access
Reset
6
R/W
0
R/W
0
R/W
0
5
PSIZE[2:0]
R/W
0
4
25
24
R/W
0
R/W
0
R/W
0
18
17
PEPNUM[3:0]
R/W
R/W
0
0
10
AUTOSW
R/W
0
PTYPE[1:0]
Access
Reset
26
3
2
PBK[1:0]
R/W
0
R/W
0
R/W
0
16
R/W
0
9
8
PTOKEN[1:0]
R/W
R/W
0
0
1
ALLOC
R/W
0
0
Bits 31:24 – BINTERVAL[7:0] bInterval Parameter for the Bulk-Out/Ping Transaction
This field contains the Ping/Bulk-out period.
• If BINTERVAL > 0 and PINGEN = 1, one PING token is sent every bInterval microframe until it is ACKed by the
peripheral.
• If BINTERVAL = 0 and PINGEN = 1, multiple consecutive PING tokens are sent in the same microframe until they
are ACKed.
• If BINTERVAL > 0 and PINGEN = 0, one OUT token is sent every bInterval microframe until it is ACKed by the
peripheral.
• If BINTERVAL = 0 and PINGEN = 0, multiple consecutive OUT tokens are sent in the same microframe until they
are ACKed.
This value must be in the range from 0 to 255.
Bit 20 – PINGEN Ping Enable
This bit is relevant for High-speed Bulk-out transaction only (including the control data stage and the control status
stage).
This bit is cleared upon sending a USB reset.
Value
Description
0
Disables the ping protocol.
1
Enables the ping mechanism according to the USB 2.0 Standard.
Bits 19:16 – PEPNUM[3:0] Pipe Endpoint Number
This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 9.
This field is cleared upon sending a USB reset.
Bits 13:12 – PTYPE[1:0] Pipe Type
This field contains the pipe type.
This field is cleared upon sending a USB reset.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 838
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
2
3
Name
CTRL
Reserved
BLK
Reserved
Description
Control
Bulk
Bit 10 – AUTOSW Automatic Switch
This bit is cleared upon sending a USB reset.
Value
Description
0
The automatic bank switching is disabled.
1
The automatic bank switching is enabled.
Bits 9:8 – PTOKEN[1:0] Pipe Token
This field contains the pipe token.
Value
Name
0
SETUP
1
IN
2
OUT
3
Reserved
Bits 6:4 – PSIZE[2:0] Pipe Size
This field contains the size of each pipe bank.
This field is cleared upon sending a USB reset.
Value
Name
0
8_BYTE
1
16_BYTE
2
32_BYTE
3
64_BYTE
4
128_BYTE
5
256_BYTE
6
512_BYTE
7
1024_BYTE
Description
SETUP
IN
OUT
Description
8 bytes
16 bytes
32 bytes
64 bytes
128 bytes
256 bytes
512 bytes
1024 bytes
Bits 3:2 – PBK[1:0] Pipe Banks
This field contains the number of banks for the pipe.
For control pipes, a single-bank pipe (0b00) should be selected.
This field is cleared upon sending a USB reset.
Value
Name
Description
0
1_BANK
Single-bank pipe
1
2_BANK
Double-bank pipe
2
3_BANK
Triple-bank pipe
3
Reserved
Bit 1 – ALLOC Pipe Memory Allocate
This bit is cleared when a USB Reset is requested.
Refer to ”DPRAM Management” for more details.
Value
Description
0
Frees the pipe memory.
1
Allocates the pipe memory.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 839
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.45 Host Pipe x Status Register (Control, Bulk Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPISRx
0x0530 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
Bit
31
Access
Reset
Bit
23
30
29
28
R/W
0
R/W
0
R/W
0
27
PBYCT[10:4]
R/W
0
21
20
R/W
0
R/W
0
22
26
25
24
R/W
0
R/W
0
R/W
0
19
18
CFGOK
R/W
0
17
16
RWALL
R/W
0
11
10
9
PBYCT[3:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
15
14
CURRBK[1:0]
R/W
R/W
0
0
7
SHORTPACKE
TI
Access
R/W
Reset
0
13
12
NBUSYBK[1:0]
R/W
R/W
0
0
8
DTSEQ[1:0]
R/W
R/W
0
0
6
RXSTALLDI
5
OVERFI
4
NAKEDI
3
PERRI
2
TXSTPI
1
TXOUTI
0
RXINI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 30:20 – PBYCT[10:0] Pipe Byte Count
This field contains the byte count of the FIFO.
For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after
each byte sent to the peripheral.
For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte
read by the user from the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt bit.
Bit 18 – CFGOK Configuration OK Status
This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set.
This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE)
are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size
(i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx
register.
Bit 16 – RWALL Read/Write Allowed
For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the
FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALLDI or the PERRI bit = 1.
Bits 15:14 – CURRBK[1:0] Current Bank
For non-control pipe, this field indicates the number of the current bank.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 840
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
2
3
Name
BANK0
BANK1
BANK2
Reserved
Description
Current bank is bank0
Current bank is bank1
Current bank is bank2
Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks
This field indicates the number of busy banks.
For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for OUT transfer. When all
banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the Device. When all banks
are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
Value
Name
Description
0
0_BUSY
0 busy bank (all banks free)
1
1_BUSY
1 busy bank
2
2_BUSY
2 busy banks
3
3_BUSY
3 busy banks
Bits 9:8 – DTSEQ[1:0] Data Toggle Sequence
This field indicates the data PID of the current bank.
For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent.
For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
Value
Name
Description
0
DATA0
Data0 toggle sequence
1
DATA1
Data1 toggle sequence
2
Reserved
3
Reserved
Bit 7 – SHORTPACKETI Short Packet Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1.
1
Set when a short packet is received by the host controller (packet length inferior to the PSIZE
programmed field).
Bit 6 – RXSTALLDI Received STALLed Interrupt
This bit is set when a STALL handshake has been received on the current bank of the pipe. The pipe is automatically
frozen. This triggers an interrupt if USBHS_HSTPIPIMR.RXSTALLE = 1.
Value
Description
0
Cleared when USBHS_HSTPIPICR.RXSTALLDIC = 1.
Bit 5 – OVERFI Overflow Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.OVERFIC = 1.
1
Set when the current pipe has received more data than the maximum length of the current pipe. An
interrupt is triggered if USBHS_HSTPIPIMR.OVERFIE = 1.
Bit 4 – NAKEDI NAKed Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.NAKEDIC = 1.
1
Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if
USBHS_HSTPIPIMR.NAKEDE = 1.
Bit 3 – PERRI Pipe Error Interrupt
Value
Description
0
Cleared when the error source bit is cleared.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 841
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
1
Description
Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the
source of the error.
Bit 2 – TXSTPI Transmitted SETUP Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.TXSTPIC = 1.
1
Set, for control pipes, when the current SETUP bank is free and can be filled. This triggers an interrupt
if USBHS_HSTPIPIMR.TXSTPE = 1.
Bit 1 – TXOUTI Transmitted OUT Data Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.TXOUTIC = 1.
1
Set when the current OUT bank is free and can be filled. This triggers an interrupt if
USBHS_HSTPIPIMR.TXOUTE = 1.
Bit 0 – RXINI Received IN Data Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.RXINIC = 1.
1
Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if
USBHS_HSTPIPIMR.RXINE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 842
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.46 Host Pipe x Status Register (Interrupt Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPISRx (INTPIPES)
0x0530 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
Bit
31
Access
Reset
Bit
23
30
29
28
R/W
0
R/W
0
R/W
0
27
PBYCT[10:4]
R/W
0
21
20
R/W
0
R/W
0
22
26
25
24
R/W
0
R/W
0
R/W
0
19
18
CFGOK
R/W
0
17
16
RWALL
R/W
0
11
10
9
PBYCT[3:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
15
14
CURRBK[1:0]
R/W
R/W
0
0
7
SHORTPACKE
TI
Access
R/W
Reset
0
13
12
NBUSYBK[1:0]
R/W
R/W
0
0
8
DTSEQ[1:0]
R/W
R/W
0
0
6
RXSTALLDI
5
OVERFI
4
NAKEDI
3
PERRI
2
UNDERFI
1
TXOUTI
0
RXINI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 30:20 – PBYCT[10:0] Pipe Byte Count
This field contains the byte count of the FIFO.
For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after
each byte sent to the peripheral.
For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte
read by the user from the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt bit.
Bit 18 – CFGOK Configuration OK Status
This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set.
This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE)
are correct compared to the maximal allowed number of banks and size for this pipe, and to the maximal FIFO size
(i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx
register.
Bit 16 – RWALL Read/Write Allowed
For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the
FIFO.
This bit is cleared otherwise.
This bit is also cleared when RXSTALLDI or PERRI = 1.
Bits 15:14 – CURRBK[1:0] Current Bank
For a non-control pipe, this field indicates the number of the current bank.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 843
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
2
3
Name
BANK0
BANK1
BANK2
Reserved
Description
Current bank is bank0
Current bank is bank1
Current bank is bank2
Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks
This field indicates the number of busy banks.
For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for an OUT transfer. When all
banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the device. When all banks
are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
Value
Name
Description
0
0_BUSY
0 busy bank (all banks free)
1
1_BUSY
1 busy bank
2
2_BUSY
2 busy banks
3
3_BUSY
3 busy banks
Bits 9:8 – DTSEQ[1:0] Data Toggle Sequence
This field indicates the data PID of the current bank.
For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent.
For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
Value
Name
Description
0
DATA0
Data0 toggle sequence
1
DATA1
Data1 toggle sequence
2
Reserved
3
Reserved
Bit 7 – SHORTPACKETI Short Packet Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1.
1
Set when a short packet is received by the host controller (packet length inferior to the PSIZE
programmed field).
Bit 6 – RXSTALLDI Received STALLed Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.RXSTALLDIC = 1.
1
Set when a STALL handshake has been received on the current bank of the pipe. The pipe is
automatically frozen. This triggers an interrupt if USBHS_HSTPIPIMR.RXSTALLE = 1.
Bit 5 – OVERFI Overflow Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.OVERFIC = 1.
1
Set when the current pipe has received more data than the maximum length of the current pipe. An
interrupt is triggered if the USBHS_HSTPIPIMR.OVERFIE bit = 1.
Bit 4 – NAKEDI NAKed Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.NAKEDIC = 1.
1
Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.NAKEDE bit = 1.
Bit 3 – PERRI Pipe Error Interrupt
Value
Description
0
Cleared when the error source bit is cleared.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 844
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
1
Description
Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the
source of the error.
Bit 2 – UNDERFI Underflow Interrupt
This bit is set, for an isochronous and interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if
UNDERFIE = 1.
This bit is set, for an isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe (the
pipe cannot send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) is
sent instead.
This bit is set, for an isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe, i.e, the
current bank of the pipe is not free while a new IN USB packet is received. This packet is not stored in the bank. For
an interrupt pipe, the overflowed packet is ACKed to comply with the USB standard.
This bit is cleared when USBHS_HSTPIPICR.UNDERFIEC = 1.
Bit 1 – TXOUTI Transmitted OUT Data Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.TXOUTIC = 1.
1
Set when the current OUT bank is free and can be filled. This triggers an interrupt if
USBHS_HSTPIPIMR.TXOUTE = 1.
Bit 0 – RXINI Received IN Data Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.RXINIC = 1.
1
Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.RXINE bit = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 845
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.47 Host Pipe x Status Register (Isochronous Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPISRx (ISOPIPES)
0x0530 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
Bit
31
Access
Reset
Bit
23
30
29
28
R/W
0
R/W
0
R/W
0
27
PBYCT[10:4]
R/W
0
21
20
R/W
0
R/W
0
22
26
25
24
R/W
0
R/W
0
R/W
0
19
18
CFGOK
R/W
0
17
16
RWALL
R/W
0
11
10
9
PBYCT[3:0]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
15
14
CURRBK[1:0]
R/W
R/W
0
0
7
SHORTPACKE
TI
Access
R/W
Reset
0
13
12
NBUSYBK[1:0]
R/W
R/W
0
0
8
DTSEQ[1:0]
R/W
R/W
0
0
6
CRCERRI
5
OVERFI
4
NAKEDI
3
PERRI
2
UNDERFI
1
TXOUTI
0
RXINI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 30:20 – PBYCT[10:0] Pipe Byte Count
This field contains the byte count of the FIFO.
For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after
each byte sent to the peripheral.
For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte
read by the user from the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an
interrupt bit.
Bit 18 – CFGOK Configuration OK Status
This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set.
This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE)
are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size
(i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx
register.
Bit 16 – RWALL Read/Write Allowed
For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the
FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALLDI or the PERRI bit = 1.
Bits 15:14 – CURRBK[1:0] Current Bank
For a non-control pipe, this field indicates the number of the current bank.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 846
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
2
3
Name
BANK0
BANK1
BANK2
Reserved
Description
Current bank is bank0
Current bank is bank1
Current bank is bank2
Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks
This field indicates the number of busy banks.
For an OUT pipe, this field indicates the number of busy banks, filled by the user, ready for an OUT transfer. When all
banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the device. When all banks
are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
Value
Name
Description
0
0_BUSY
0 busy bank (all banks free)
1
1_BUSY
1 busy bank
2
2_BUSY
2 busy banks
3
3_BUSY
3 busy banks
Bits 9:8 – DTSEQ[1:0] Data Toggle Sequence
This field indicates the data PID of the current bank.
For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent.
For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
Value
Name
Description
0
DATA0
Data0 toggle sequence
1
DATA1
Data1 toggle sequence
2
Reserved
3
Reserved
Bit 7 – SHORTPACKETI Short Packet Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1.
1
Set when a short packet is received by the host controller (packet length inferior to the PSIZE
programmed field).
Bit 6 – CRCERRI CRC Error Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.CRCERRIC = 1.
1
Set when a CRC error occurs on the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.TXSTPE bit = 1.
Bit 5 – OVERFI Overflow Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.OVERFIC = 1.
1
Set when the current pipe has received more data than the maximum length of the current pipe. An
interrupt is triggered if the USBHS_HSTPIPIMR.OVERFIE bit = 1.
Bit 4 – NAKEDI NAKed Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.NAKEDIC = 1.
1
Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.NAKEDE bit = 1.
Bit 3 – PERRI Pipe Error Interrupt
Value
Description
0
Cleared when the error source bit is cleared.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 847
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
1
Description
Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the
source of the error.
Bit 2 – UNDERFI Underflow Interrupt
This bit is set, for an isochronous and interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if
the UNDERFIE bit = 1.
This bit is set, for an isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe (the
pipe cannot send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) is
sent instead.
This bit is set, for an isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe, i.e, the
current bank of the pipe is not free while a new IN USB packet is received. This packet is not stored in the bank. For
an interrupt pipe, the overflowed packet is ACKed to comply with the USB standard.
This bit is cleared when USBHS_HSTPIPICR.UNDERFIEC = 1.
Bit 1 – TXOUTI Transmitted OUT Data Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.TXOUTIC = 1.
1
Set when the current OUT bank is free and can be filled. This triggers an interrupt if
USBHS_HSTPIPIMR.TXOUTE = 1.
Bit 0 – RXINI Received IN Data Interrupt
Value
Description
0
Cleared when USBHS_HSTPIPICR.RXINIC = 1.
1
Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if
USBHS_HSTPIPIMR.RXINE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 848
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.48 Host Pipe x Clear Register (Control, Bulk Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPICRx
0x0560 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTPIPISRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
5
OVERFIC
4
NAKEDIC
3
2
TXSTPIC
1
TXOUTIC
0
RXINIC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDIC
TIC
Access
R/W
R/W
Reset
0
0
Bit 7 – SHORTPACKETIC Short Packet Interrupt Clear
Bit 6 – RXSTALLDIC Received STALLed Interrupt Clear
Bit 5 – OVERFIC Overflow Interrupt Clear
Bit 4 – NAKEDIC NAKed Interrupt Clear
Bit 2 – TXSTPIC Transmitted SETUP Interrupt Clear
Bit 1 – TXOUTIC Transmitted OUT Data Interrupt Clear
Bit 0 – RXINIC Received IN Data Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 849
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.49 Host Pipe x Clear Register (Interrupt Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPICRx (INTPIPES)
0x0560 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Interrupt Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTPIPISRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
5
OVERFIC
4
NAKEDIC
3
2
UNDERFIC
1
TXOUTIC
0
RXINIC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDIC
TIC
Access
R/W
R/W
Reset
0
0
Bit 7 – SHORTPACKETIC Short Packet Interrupt Clear
Bit 6 – RXSTALLDIC Received STALLed Interrupt Clear
Bit 5 – OVERFIC Overflow Interrupt Clear
Bit 4 – NAKEDIC NAKed Interrupt Clear
Bit 2 – UNDERFIC Underflow Interrupt Clear
Bit 1 – TXOUTIC Transmitted OUT Data Interrupt Clear
Bit 0 – RXINIC Received IN Data Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 850
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.50 Host Pipe x Clear Register (Isochronous Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPICRx (ISOPIPES)
0x0560 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Isochronous Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTPIPISRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
6
CRCERRIC
5
OVERFIC
4
NAKEDIC
3
2
UNDERFIC
1
TXOUTIC
0
RXINIC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TIC
Access
R/W
Reset
0
Bit 7 – SHORTPACKETIC Short Packet Interrupt Clear
Bit 6 – CRCERRIC CRC Error Interrupt Clear
Bit 5 – OVERFIC Overflow Interrupt Clear
Bit 4 – NAKEDIC NAKed Interrupt Clear
Bit 2 – UNDERFIC Underflow Interrupt Clear
Bit 1 – TXOUTIC Transmitted OUT Data Interrupt Clear
Bit 0 – RXINIC Received IN Data Interrupt Clear
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 851
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.51 Host Pipe x Set Register (Control, Bulk Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIFRx
0x0590
0
Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
NBUSYBKS
R/W
0
11
10
9
8
5
OVERFIS
4
NAKEDIS
3
PERRIS
2
TXSTPIS
1
TXOUTIS
0
RXINIS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDIS
TIS
Access
R/W
R/W
Reset
0
0
Bit 12 – NBUSYBKS Number of Busy Banks Set
Bit 7 – SHORTPACKETIS Short Packet Interrupt Set
Bit 6 – RXSTALLDIS Received STALLed Interrupt Set
Bit 5 – OVERFIS Overflow Interrupt Set
Bit 4 – NAKEDIS NAKed Interrupt Set
Bit 3 – PERRIS Pipe Error Interrupt Set
Bit 2 – TXSTPIS Transmitted SETUP Interrupt Set
Bit 1 – TXOUTIS Transmitted OUT Data Interrupt Set
Bit 0 – RXINIS Received IN Data Interrupt Set
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 852
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.52 Host Pipe x Set Register (Interrupt Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIFRx (INTPIPES)
0x0590 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Interrupt Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
NBUSYBKS
R/W
0
11
10
9
8
5
OVERFIS
4
NAKEDIS
3
PERRIS
2
UNDERFIS
1
TXOUTIS
0
RXINIS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDIS
TIS
Access
R/W
R/W
Reset
0
0
Bit 12 – NBUSYBKS Number of Busy Banks Set
Bit 7 – SHORTPACKETIS Short Packet Interrupt Set
Bit 6 – RXSTALLDIS Received STALLed Interrupt Set
Bit 5 – OVERFIS Overflow Interrupt Set
Bit 4 – NAKEDIS NAKed Interrupt Set
Bit 3 – PERRIS Pipe Error Interrupt Set
Bit 2 – UNDERFIS Underflow Interrupt Set
Bit 1 – TXOUTIS Transmitted OUT Data Interrupt Set
Bit 0 – RXINIS Received IN Data Interrupt Set
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 853
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.53 Host Pipe x Set Register (Isochronous Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIFRx (ISOPIPES)
0x0590 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Isochronous Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
NBUSYBKS
R/W
0
11
10
9
8
6
CRCERRIS
5
OVERFIS
4
NAKEDIS
3
PERRIS
2
UNDERFIS
1
TXOUTIS
0
RXINIS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TIS
Access
R/W
Reset
0
Bit 12 – NBUSYBKS Number of Busy Banks Set
Bit 7 – SHORTPACKETIS Short Packet Interrupt Set
Bit 6 – CRCERRIS CRC Error Interrupt Set
Bit 5 – OVERFIS Overflow Interrupt Set
Bit 4 – NAKEDIS NAKed Interrupt Set
Bit 3 – PERRIS Pipe Error Interrupt Set
Bit 2 – UNDERFIS Underflow Interrupt Set
Bit 1 – TXOUTIS Transmitted OUT Data Interrupt Set
Bit 0 – RXINIS Received IN Data Interrupt Set
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 854
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.54 Host Pipe x Mask Register (Control, Bulk Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIMRx
0x05C0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDT
R/W
0
17
PFREEZE
R/W
0
16
PDISHDMA
R/W
0
15
14
FIFOCON
R/W
0
13
12
NBUSYBKE
R/W
0
11
10
9
8
6
RXSTALLDE
5
OVERFIE
4
NAKEDE
3
PERRE
2
TXSTPE
1
TXOUTE
0
RXINE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TIE
Access
R/W
Reset
0
Bit 18 – RSTDT Reset Data Toggle
Value
Description
0
No reset of the Data Toggle is ongoing.
0
Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the
current pipe.
Bit 17 – PFREEZE Pipe Freeze
This freezes the pipe request generation.
Value
Description
0
Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation.
1
Set when one of the following conditions is met:
• USBHS_HSTPIPIER.PFREEZES=
• The pipe is not configured.
• A STALL handshake has been received on the pipe.
• An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1).
• (INRQ+1) In requests have been processed.
• A Pipe Reset (USBHS_HSTPIP.PRSTx rising) has occurred.
• A Pipe Enable (USBHS_HSTPIP.PEN rising) has occurred.
Bit 16 – PDISHDMA Pipe Interrupts Disable HDMA Request Enable
See the USBHS_DEVEPTIMR.EPDISHDMA bit description.
Bit 14 – FIFOCON FIFO Control
For OUT and SETUP pipes:
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 855
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank.
1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI.
For an IN pipe:
0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank.
1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
Bit 12 – NBUSYBKE Number of Busy Banks Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
1
Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
Bit 7 – SHORTPACKETIE Short Packet Interrupt Enable
If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending
a DMA transfer, thus signaling an end of transfer, provided that End of DMA Buffer Output Enable
(USBHS_HSTDMACONTROL.END_B_EN) and Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) = 1.
Value
Description
0
Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted IN Data IT
(USBHS_HSTPIPIMR.SHORTPACKETE).
1
Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data IT
(USBHS_HSTPIPIMR.SHORTPACKETIE).
Bit 6 – RXSTALLDE Received STALLed Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.RXSTALLDEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXSTALLDE).
1
Set when USBHS_HSTPIPIER.RXSTALLDES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXSTALLDE).
Bit 5 – OVERFIE Overflow Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
1
Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
Bit 4 – NAKEDE NAKed Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
1
Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
Bit 3 – PERRE Pipe Error Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
1
Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
Bit 2 – TXSTPE Transmitted SETUP Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.TXSTPEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXSTPE).
1
Set when USBHS_HSTPIPIER.TXSTPES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXSTPE).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 856
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTE Transmitted OUT Data Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXOUTE).
1
Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXOUTE).
Bit 0 – RXINE Received IN Data Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.RXINEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXINE).
1
Set when USBHS_HSTPIPIER.RXINES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXINE).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 857
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.55 Host Pipe x Mask Register (Interrupt Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIMRx (INTPIPES)
0x05C0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDT
R/W
0
17
PFREEZE
R/W
0
16
PDISHDMA
R/W
0
15
14
FIFOCON
R/W
0
13
12
NBUSYBKE
R/W
0
11
10
9
8
6
RXSTALLDE
5
OVERFIE
4
NAKEDE
3
PERRE
2
UNDERFIE
1
TXOUTE
0
RXINE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TIE
Access
R/W
Reset
0
Bit 18 – RSTDT Reset Data Toggle
Value
Description
0
0: No reset of the Data Toggle is ongoing.
1
Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the
current pipe.
Bit 17 – PFREEZE Pipe Freeze
This freezes the pipe request generation.
Value
Description
0
Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation.
1
Set when one of the following conditions is met:
• USBHS_HSTPIPIER.PFREEZES = 1
• The pipe is not configured.
• A STALL handshake has been received on the pipe.
• An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1).
• (INRQ+1) in requests have been processed.
• A Pipe Reset (USBHS_HSTPIP.PRSTx rising) has occurred.
• A Pipe Enable (USBHS_HSTPIP.PEN rising) has occurred.
Bit 16 – PDISHDMA Pipe Interrupts Disable HDMA Request Enable
See the USBHS_DEVEPTIMR.EPDISHDMA bit description.
Bit 14 – FIFOCON FIFO Control
For OUT and SETUP pipes:
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 858
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank.
1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI.
For IN pipes:
0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank.
1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
Bit 12 – NBUSYBKE Number of Busy Banks Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
1
Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
Bit 7 – SHORTPACKETIE Short Packet Interrupt Enable
If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a
DMA transfer, thus signaling an end of transfer, provided that the End of DMA Buffer Output Enable
(USBHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) bit = 1.
Value
Description
0
Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted IN Data
interrupt (USBHS_HSTPIPIMR.SHORTPACKETE).
1
Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data
interrupt (USBHS_HSTPIPIMR.SHORTPACKETIE).
Bit 6 – RXSTALLDE Received STALLed Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.RXSTALLDEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXSTALLDE).
1
Set when USBHS_HSTPIPIER.RXSTALLDES= 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXSTALLDE).
Bit 5 – OVERFIE Overflow Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
1
Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
Bit 4 – NAKEDE NAKed Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
1
Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
Bit 3 – PERRE Pipe Error Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
1
Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
Bit 2 – UNDERFIE Underflow Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.UNDERFIEC= 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.UNDERFIE).
1
Set when USBHS_HSTPIPIER.UNDERFIES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.UNDERFIE).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 859
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTE Transmitted OUT Data Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXOUTE).
1
Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXOUTE).
Bit 0 – RXINE Received IN Data Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.RXINEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXINE).
1
Set when USBHS_HSTPIPIER.RXINES= 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXINE).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 860
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.56 Host Pipe x Mask Register (Isochronous Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIMRx (ISOPIPES)
0x05C0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDT
R/W
0
17
PFREEZE
R/W
0
16
PDISHDMA
R/W
0
15
14
FIFOCON
R/W
0
13
12
NBUSYBKE
R/W
0
11
10
9
8
6
CRCERRE
5
OVERFIE
4
NAKEDE
3
PERRE
2
UNDERFIE
1
TXOUTE
0
RXINE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TIE
Access
R/W
Reset
0
Bit 18 – RSTDT Reset Data Toggle
Value
Description
0
No reset of the Data Toggle is ongoing.
1
Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the
current pipe.
Bit 17 – PFREEZE Pipe Freeze
This freezes the pipe request generation.
Value
Description
0
Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation.
1
Set when one of the following conditions is met:
• USBHS_HSTPIPIER.PFREEZES = 1.
• The pipe is not configured.
• A STALL handshake has been received on the pipe.
• An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1).
• (INRQ+1) In requests have been processed.
• A Pipe Reset (USBHS_HSTPIP.PRSTx rising) has occurred.
• A Pipe Enable (USBHS_HSTPIP.PEN rising) has occurred.
Bit 16 – PDISHDMA Pipe Interrupts Disable HDMA Request Enable
See the USBHS_DEVEPTIMR.EPDISHDMA bit description.
Bit 14 – FIFOCON FIFO Control
For OUT and SETUP pipes:
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 861
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank.
1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI.
For IN pipes:
0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank.
1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
Bit 12 – NBUSYBKE Number of Busy Banks Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
1
Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
Bit 7 – SHORTPACKETIE Short Packet Interrupt Enable
If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a
DMA transfer, thus signaling an end of transfer, provided that the End of DMA Buffer Output Enable
(USBHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) bit = 1.
Value
Description
0
Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted interrupt
Data IT (USBHS_HSTPIPIMR.SHORTPACKETE).
1
Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data
interrupt (USBHS_HSTPIPIMR.SHORTPACKETIE).
Bit 6 – CRCERRE CRC Error Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.CRCERREC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.CRCERRE).
1
Set when USBHS_HSTPIPIER.CRCERRES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.CRCERRE).
Bit 5 – OVERFIE Overflow Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
1
Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
Bit 4 – NAKEDE NAKed Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
1
Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
Bit 3 – PERRE Pipe Error Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
1
Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
Bit 2 – UNDERFIE Underflow Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.UNDERFIEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.UNDERFIE).
1
Set when USBHS_HSTPIPIER.UNDERFIES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.UNDERFIE).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 862
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTE Transmitted OUT Data Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.TXOUTEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXOUTE).
1
Set when USBHS_HSTPIPIER.TXOUTES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.TXOUTE).
Bit 0 – RXINE Received IN Data Interrupt Enable
Value
Description
0
Cleared when USBHS_HSTPIPIDR.RXINEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXINE).
1
Set when USBHS_HSTPIPIER.RXINES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.RXINE).
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 863
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.57 Host Pipe x Disable Register (Control, Bulk Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIDRx
0x0620 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTPIPIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PFREEZEC
R/W
0
16
PDISHDMAC
R/W
0
15
14
FIFOCONC
R/W
0
13
12
NBUSYBKEC
R/W
0
11
10
9
8
5
OVERFIEC
4
NAKEDEC
3
PERREC
2
TXSTPEC
1
TXOUTEC
0
RXINEC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDEC
TIEC
Access
R/W
R/W
Reset
0
0
Bit 17 – PFREEZEC Pipe Freeze Disable
Bit 16 – PDISHDMAC Pipe Interrupts Disable HDMA Request Disable
Bit 14 – FIFOCONC FIFO Control Disable
Bit 12 – NBUSYBKEC Number of Busy Banks Disable
Bit 7 – SHORTPACKETIEC Short Packet Interrupt Disable
Bit 6 – RXSTALLDEC Received STALLed Interrupt Disable
Bit 5 – OVERFIEC Overflow Interrupt Disable
Bit 4 – NAKEDEC NAKed Interrupt Disable
Bit 3 – PERREC Pipe Error Interrupt Disable
Bit 2 – TXSTPEC Transmitted SETUP Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 864
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTEC Transmitted OUT Data Interrupt Disable
Bit 0 – RXINEC Received IN Data Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 865
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.58 Host Pipe x Disable Register (Interrupt Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIDRx (INTPIPES)
0x0620 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Interrupt Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTPIPIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PFREEZEC
R/W
0
16
PDISHDMAC
R/W
0
15
14
FIFOCONC
R/W
0
13
12
NBUSYBKEC
R/W
0
11
10
9
8
5
OVERFIEC
4
NAKEDEC
3
PERREC
2
UNDERFIEC
1
TXOUTEC
0
RXINEC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDEC
TIEC
Access
R/W
R/W
Reset
0
0
Bit 17 – PFREEZEC Pipe Freeze Disable
Bit 16 – PDISHDMAC Pipe Interrupts Disable HDMA Request Disable
Bit 14 – FIFOCONC FIFO Control Disable
Bit 12 – NBUSYBKEC Number of Busy Banks Disable
Bit 7 – SHORTPACKETIEC Short Packet Interrupt Disable
Bit 6 – RXSTALLDEC Received STALLed Interrupt Disable
Bit 5 – OVERFIEC Overflow Interrupt Disable
Bit 4 – NAKEDEC NAKed Interrupt Disable
Bit 3 – PERREC Pipe Error Interrupt Disable
Bit 2 – UNDERFIEC Underflow Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 866
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTEC Transmitted OUT Data Interrupt Disable
Bit 0 – RXINEC Received IN Data Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 867
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.59 Host Pipe x Disable Register (Isochronous Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIDRx (ISOPIPES)
0x0620 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Isochronous Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding bit in USBHS_HSTPIPIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PFREEZEC
R/W
0
16
PDISHDMAC
R/W
0
15
14
FIFOCONC
R/W
0
13
12
NBUSYBKEC
R/W
0
11
10
9
8
6
CRCERREC
5
OVERFIEC
4
NAKEDEC
3
PERREC
2
UNDERFIEC
1
TXOUTEC
0
RXINEC
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TIEC
Access
R/W
Reset
0
Bit 17 – PFREEZEC Pipe Freeze Disable
Bit 16 – PDISHDMAC Pipe Interrupts Disable HDMA Request Disable
Bit 14 – FIFOCONC FIFO Control Disable
Bit 12 – NBUSYBKEC Number of Busy Banks Disable
Bit 7 – SHORTPACKETIEC Short Packet Interrupt Disable
Bit 6 – CRCERREC CRC Error Interrupt Disable
Bit 5 – OVERFIEC Overflow Interrupt Disable
Bit 4 – NAKEDEC NAKed Interrupt Disable
Bit 3 – PERREC Pipe Error Interrupt Disable
Bit 2 – UNDERFIEC Underflow Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 868
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTEC Transmitted OUT Data Interrupt Disable
Bit 0 – RXINEC Received IN Data Interrupt Disable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 869
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.60 Host Pipe x Enable Register (Control, Bulk Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIERx
0x05F0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTPIPIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDTS
R/W
0
17
PFREEZES
R/W
0
16
PDISHDMAS
R/W
0
15
14
13
12
NBUSYBKES
R/W
0
11
10
9
8
5
OVERFIES
4
NAKEDES
3
PERRES
2
TXSTPES
1
TXOUTES
0
RXINES
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDES
TIES
Access
R/W
R/W
Reset
0
0
Bit 18 – RSTDTS Reset Data Toggle Enable
Bit 17 – PFREEZES Pipe Freeze Enable
Bit 16 – PDISHDMAS Pipe Interrupts Disable HDMA Request Enable
Bit 12 – NBUSYBKES Number of Busy Banks Enable
Bit 7 – SHORTPACKETIES Short Packet Interrupt Enable
Bit 6 – RXSTALLDES Received STALLed Interrupt Enable
Bit 5 – OVERFIES Overflow Interrupt Enable
Bit 4 – NAKEDES NAKed Interrupt Enable
Bit 3 – PERRES Pipe Error Interrupt Enable
Bit 2 – TXSTPES Transmitted SETUP Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 870
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTES Transmitted OUT Data Interrupt Enable
Bit 0 – RXINES Received IN Data Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 871
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.61 Host Pipe x Enable Register (Interrupt Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIERx (INTPIPES)
0x05F0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Interrupt Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTPIPIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDTS
R/W
0
17
PFREEZES
R/W
0
16
PDISHDMAS
R/W
0
15
14
13
12
NBUSYBKES
R/W
0
11
10
9
8
5
OVERFIES
4
NAKEDES
3
PERRES
2
UNDERFIES
1
TXOUTES
0
RXINES
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
SHORTPACKE RXSTALLDES
TIES
Access
R/W
R/W
Reset
0
0
Bit 18 – RSTDTS Reset Data Toggle Enable
Bit 17 – PFREEZES Pipe Freeze Enable
Bit 16 – PDISHDMAS Pipe Interrupts Disable HDMA Request Enable
Bit 12 – NBUSYBKES Number of Busy Banks Enable
Bit 7 – SHORTPACKETIES Short Packet Interrupt Enable
Bit 6 – RXSTALLDES Received STALLed Interrupt Enable
Bit 5 – OVERFIES Overflow Interrupt Enable
Bit 4 – NAKEDES NAKed Interrupt Enable
Bit 3 – PERRES Pipe Error Interrupt Enable
Bit 2 – UNDERFIES Underflow Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 872
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTES Transmitted OUT Data Interrupt Enable
Bit 0 – RXINES Received IN Data Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 873
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.62 Host Pipe x Enable Register (Isochronous Pipes)
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPIERx (ISOPIPES)
0x05F0 + x*0x04 [x=0..8]
0
Read/Write
This register view is relevant only if PTYPE = 0x1 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Isochronous Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Sets the corresponding bit in USBHS_HSTPIPIMRx.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
RSTDTS
R/W
0
17
PFREEZES
R/W
0
16
PDISHDMAS
R/W
0
15
14
13
12
NBUSYBKES
R/W
0
11
10
9
8
6
CRCERRES
5
OVERFIES
4
NAKEDES
3
PERRES
2
UNDERFIES
1
TXOUTES
0
RXINES
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
SHORTPACKE
TIES
Access
R/W
Reset
0
Bit 18 – RSTDTS Reset Data Toggle Enable
Bit 17 – PFREEZES Pipe Freeze Enable
Bit 16 – PDISHDMAS Pipe Interrupts Disable HDMA Request Enable
Bit 12 – NBUSYBKES Number of Busy Banks Enable
Bit 7 – SHORTPACKETIES Short Packet Interrupt Enable
Bit 6 – CRCERRES CRC Error Interrupt Enable
Bit 5 – OVERFIES Overflow Interrupt Enable
Bit 4 – NAKEDES NAKed Interrupt Enable
Bit 3 – PERRES Pipe Error Interrupt Enable
Bit 2 – UNDERFIES Underflow Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 874
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – TXOUTES Transmitted OUT Data Interrupt Enable
Bit 0 – RXINES Received IN Data Interrupt Enable
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 875
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.63 Host Pipe x IN Request Register
Name:
Offset:
Reset:
Property:
Bit
USBHS_HSTPIPINRQx
0x0650 + x*0x04 [x=0..8]
0
Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
INMODE
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
INRQ[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 8 – INMODE IN Request Mode
Value
Description
0
Performs a pre-defined number of IN requests. This number is the INRQ field.
1
Enables the USBHS to perform infinite IN requests when the pipe is not frozen.
Bits 7:0 – INRQ[7:0] IN Request Number before Freeze
This field contains the number of IN transactions before the USBHS freezes the pipe. The USBHS performs
(INRQ+1) IN requests before freezing the pipe. This counter is automatically decreased by 1 each time an IN request
has been successfully performed.
This register has no effect when INMODE = 1.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 876
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.64 Host Pipe x Error Register
Name:
Offset:
Reset:
Property:
USBHS_HSTPIPERRx
0x0680 + x*0x04 [x=0..8]
0
Read/Write
Writing a zero in a bit/field in this register clears the bit/field. Writing a one has no effect.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
4
CRC16
R/W
0
3
TIMEOUT
R/W
0
2
PID
R/W
0
1
DATAPID
R/W
0
0
DATATGL
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
6
5
COUNTER[1:0]
R/W
R/W
0
0
Access
Reset
Bits 6:5 – COUNTER[1:0] Error Counter
This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL).
This field is cleared when receiving a USB packet free of error.
When this field reaches 3 (i.e., 3 consecutive errors), this pipe is automatically frozen
(USBHS_HSTPIPIMRx.PFREEZE is set).
Bit 4 – CRC16 CRC16 Error
Value
Description
0
No CRC16 error occurred since last clear of this bit.
1
This bit is automatically set when a CRC16 error has been detected.
Bit 3 – TIMEOUT Time-Out Error
Value
Description
0
No Time-Out error occurred since last clear of this bit.
1
This bit is automatically set when a Time-Out error has been detected.
Bit 2 – PID PID Error
Value
0
1
Description
No PID error occurred since last clear of this bit.
This bit is automatically set when a PID error has been detected.
Bit 1 – DATAPID Data PID Error
Value
Description
0
No Data PID error occurred since last clear of this bit.
1
This bit is automatically set when a Data PID error has been detected.
Bit 0 – DATATGL Data Toggle Error
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 877
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
Description
No Data Toggle error occurred since last clear of this bit.
This bit is automatically set when a Data Toggle error has been detected.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 878
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.65 Host DMA Channel x Next Descriptor Address Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
USBHS_HSTDMANXTDSCx
0x0700 + (x-1)*0x10 [x=1..7]
0
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
NXT_DSC_ADD[31:24]
R/W
R/W
0
0
20
19
NXT_DSC_ADD[23:16]
R/W
R/W
0
0
12
11
NXT_DSC_ADD[15:8]
R/W
R/W
0
0
4
3
NXT_DSC_ADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – NXT_DSC_ADD[31:0] Next Descriptor Address
This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to
3 of the address must be equal to zero.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 879
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.66 Host DMA Channel x Address Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
USBHS_HSTDMAADDRESSx
0x0704 + x*0x10 [x=0..6]
0
Read/Write
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
BUFF_ADD[31:24]
R/W
R/W
0
0
20
19
BUFF_ADD[23:16]
R/W
R/W
0
0
12
11
BUFF_ADD[15:8]
R/W
R/W
0
0
4
3
BUFF_ADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – BUFF_ADD[31:0] Buffer Address
This field determines the AHB bus starting address of a DMA channel transfer.
Channel start and end addresses may be aligned on any byte boundary.
The firmware can write this field only when the USBHS_HSTDMASTATUS.CHANN_ENB bit is cleared.
This field is updated at the end of the address phase of the current access to the AHB bus. It is incremented by
the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not
aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the
channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel
buffer.
The channel start address is written by software or loaded from the descriptor. The channel end address
is either determined by the end of buffer or the USB device, or by the USB end of transfer if the
USBHS_HSTDMACONTROLx.END_TR_EN bit is set.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 880
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.67 Host DMA Channel x Control Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
USBHS_HSTDMACONTROLx
0x0708 + x*0x10 [x=0..6]
0
Read/Write
31
30
29
28
27
BUFF_LENGTH[15:8]
R/W
R/W
0
0
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
6
DESC_LD_IT
R/W
0
5
END_BUFFIT
R/W
0
4
END_TR_IT
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
3
END_B_EN
R/W
0
2
END_TR_EN
R/W
0
1
LDNXT_DSC
R/W
0
0
CHANN_ENB
R/W
0
20
19
BUFF_LENGTH[7:0]
R/W
R/W
0
0
Access
Reset
Bit
7
BURST_LCK
Access
R/W
Reset
0
Bits 31:16 – BUFF_LENGTH[15:0] Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size
(32 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0,
but the transfer end may occur earlier under USB device control.
When this field is written, the USBHS_HSTDMASTATUSx.BUFF_COUNT field is updated with the write value.
Notes: 1. Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
2. For reliability, it is highly recommended to wait for both the USBHS_HSTDMASTATUSx.CHAN_ACT and the
CHAN_ENB flags to be at 0, thus ensuring the channel has been stopped before issuing a command other than
“Stop Now”.
Bit 7 – BURST_LCK Burst Lock Enable
Value
Description
0
The DMA never locks the bus access.
1
USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and
maximization of fly-by AHB burst duration.
Bit 6 – DESC_LD_IT Descriptor Loaded Interrupt Enable
Value
Description
0
USBHS_HSTDMASTATUSx.DESC_LDST rising does not trigger any interrupt.
1
An interrupt is generated when a descriptor has been loaded from the bus.
Bit 5 – END_BUFFIT End of Buffer Interrupt Enable
Value
Description
0
USBHS_HSTDMASTATUSx.END_BF_ST rising does not trigger any interrupt.
1
An interrupt is generated when USBHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.
Bit 4 – END_TR_IT End of Transfer Interrupt Enable
Use when the receive size is unknown.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 881
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Value
0
1
Description
Completion of a USBHS device-initiated buffer transfer does not trigger any interrupt at
USBHS_HSTDMASTATUSx.END_TR_ST rising.
An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer
transfer.
Bit 3 – END_B_EN End of Buffer Enable Control
This is mainly for short packet OUT validations initiated by the DMA reaching the end of buffer, but could be used for
IN packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
Value
Description
0
DMA Buffer End has no impact on USB packet transfer.
1
The pipe can validate the packet (according to the values programmed in the
USBHS_HSTPIPCFGx.AUTOSW and USBHS_HSTPIPIMRx.SHORTPACKETIE fields) at DMA Buffer
End, i.e., when USBHS_HSTDMASTATUS.BUFF_COUNT reaches 0.
Bit 2 – END_TR_EN End of Transfer Enable Control (OUT transfers only)
When set, a BULK or INTERRUPT short packet closes the current buffer and the
USBHS_HSTDMASTATUSx.END_TR_ST flag is raised.
This is intended for a USBHS non-prenegotiated USB transfer size.
Value
Description
0
USB end of transfer is ignored.
1
The USBHS device can put an end to the current buffer transfer.
Bit 1 – LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command
If the CHANN_ENB bit is cleared, the next descriptor is loaded immediately upon transfer request.
DMA Channel Control Command Summary:
Value LDNXT_DSC
0
0
1
1
Value
0
1
Value CHANN_ENB
0
1
0
1
Name
STOP_NOW
RUN_AND_STOP
LOAD_NEXT_DESC
RUN_AND_LINK
Description
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
Description
No channel register is loaded after the end of the channel transfer.
The channel controller loads the next descriptor after the end of the current transfer, i.e., when the
USBHS_HSTDMASTATUS.CHANN_ENB bit is reset.
Bit 0 – CHANN_ENB Channel Enable Command
If the LDNXT_DSC bit has been cleared by descriptor loading, the firmware has to set the corresponding
CHANN_ENB bit to start the described transfer, if needed.
If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written
reliably as soon as both the USBHS_HSTDMASTATUS.CHANN_ENB and the CHANN_ACT flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty,
then the USBHS_HSTDMASTATUS.CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set or after it has been cleared, the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
Value
Description
0
The DMA channel is disabled and no transfer occurs upon request. This bit is also cleared by hardware
when the channel source bus is disabled at the end of the buffer.
1
The USBHS_HSTDMASTATUS.CHANN_ENB bit is set, enabling DMA channel data transfer. Then,
any pending request starts the transfer. This may be used to start or resume any requested transfer.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 882
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
38.7.68 Host DMA Channel x Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
USBHS_HSTDMASTATUSx
0x070C + x*0x10 [x=0..6]
0
Read/Write
31
30
29
28
27
BUFF_COUNT[15:8]
R/W
R/W
0
0
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
12
7
6
DESC_LDST
R/W
0
5
END_BF_ST
R/W
0
4
END_TR_ST
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
3
2
1
CHANN_ACT
R/W
0
0
CHANN_ENB
R/W
0
20
19
BUFF_COUNT[7:0]
R/W
R/W
0
0
Access
Reset
Bit
Access
Reset
Bits 31:16 – BUFF_COUNT[15:0] Buffer Byte Count
This field determines the current number of bytes still to be transferred for this buffer.
This field is decremented from the AHB source bus access byte width at the end of this bus address phase.
The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word
boundary.
At the end of buffer, the DMA accesses the USBHS device only for the number of bytes needed to complete it.
Note: For IN pipes, if the receive buffer byte length (USBHS_HSTDMACONTROL.BUFF_LENGTH) has been
defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received is 0x10000BUFF_COUNT.
Bit 6 – DESC_LDST Descriptor Loaded Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when a descriptor has been loaded from the system bus.
Bit 5 – END_BF_ST End of Channel Buffer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when the BUFF_COUNT count-down reaches zero.
Bit 4 – END_TR_ST End of Channel Transfer Status
Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.
Value
Description
0
Cleared automatically when read by software.
1
Set by hardware when the last packet transfer is complete, if the USBHS device has ended the
transfer.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 883
SAM E70/S70/V70/V71
USB High-Speed Interface (USBHS)
Bit 1 – CHANN_ACT Channel Active Status
When a packet transfer is ended, this bit is automatically reset.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel
descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor.
Value
Description
0
The DMA channel is no longer trying to source the packet data.
1
The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority
requesting channel.
Bit 0 – CHANN_ENB Channel Enable Status
When any transfer is ended either due to an elapsed byte count or to completion of a USBHS device-initiated
transfer, this bit is automatically reset.
This bit is normally set or cleared by writing into the USBHS_HSTDMACONTROLx.CHANN_ENB bit field either by
software or descriptor loading.
If a channel request is currently serviced when the USBHS_HSTDMACONTROLx.CHANN_ENB bit is cleared, the
DMA FIFO buffer is drained until it is empty, then this status bit is cleared.
Value
Description
0
If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the
USBHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
1
If set, the DMA channel is currently enabled and transfers data upon request.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 884
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
39.
39.1
High-Speed Multimedia Card Interface (HSMCI)
Description
The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD
Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
The HSMCI includes a command register, response registers, data registers, timeout counters and error detection
logic that automatically handle the transmission of commands and, when required, the reception of the associated
responses and data with a limited processor overhead.
The HSMCI operates at a rate of up to Host Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot
may be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. A bit
field in the SD Card Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power
lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and
one reserved for future use).
The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences
between SD and High Speed MultiMedia Cards are the initialization process and the bus topology.
HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes
dedicated hardware to issue the command completion signal and capture the host command completion signal
disable.
39.2
Embedded Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compatible with MultiMedia Card Specification Version 4.3
Compatible with SD Memory Card Specification Version 2.0
Compatible with SDIO Specification Version 2.0
Compatible with CE-ATA Specification 1.1
Cards Clock Rate Up to Host Clock Divided by 2
Boot Operation Mode Support
High Speed Mode Support
Embedded Power Management to Slow Down Clock Rate When Not Used
Supports 1 Multiplexed Slot(s)
– Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card
Support for Stream, Block and Multi-block Data Read and Write
– Minimizes Processor Intervention for Large Buffer Transfers
Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access
Support for CE-ATA Completion Signal Disable Command
Protection Against Unexpected Modification On-the-Fly of the Configuration Registers
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 885
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
39.3
Block Diagram
Figure 39-1. Block Diagram (4-bit configuration)
APB Bridge
DMAC
APB
MCCK(1)
MCCDA(1)
PMC
MCK
MCDA0(1)
HSMCI Interface
PIO
MCDA1(1)
MCDA2(1)
MCDA3(1)
Interrupt Control
HSMCI Interrupt
Note:
1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
39.4
Application Block Diagram
Figure 39-2. Application Block Diagram
Application Layer
ex: File System, Audio, Security, etc.
Physical Layer
HSMCI Interface
1 2 3 4 5 6 7
1 2 3 4 5 6 78
9
9 10 11
1213 8
MMC
© 2022 Microchip Technology Inc.
and its subsidiaries
SDCard
Complete Data Sheet
DS60001527G-page 886
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
39.5
Pin Name List
Table 39-1. I/O Lines Description for 4-bit Configuration
Pin Name(1)
Pin Description
Type(2)
Comments
MCCDA
Command/response
I/O/PP/OD
CMD of an MMC or SDCard/SDIO
MCCK
Clock
O
CLK of an MMC or SD Card/SDIO
MCDA0–MCDA3
Data 0..3 of Slot A
I/O/PP
DAT[0..3] of an MMC
DAT[0..3] of an SD Card/SDIO
Note: 1. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
Note: 2. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
39.6
Product Dependencies
39.6.1
I/O Lines
The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The
programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins.
39.6.2
Power Management
The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the
PMC to enable the HSMCI clock.
39.6.3
Interrupt Sources
The HSMCI has an interrupt line connected to the interrupt controller.
Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI.
39.7
Bus Topology
Figure 39-3. High Speed MultiMedia Memory Card Bus Topology
1 2 3 4 5 6 7
9 10 11
1213 8
MMC
The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three
communication lines and four supply lines.
Table 39-2. Bus Topology
Pin Number
Name
Type(1)
Description
HSMCI Pin Name(2)
(Slot z)
1
DAT[3]
I/O/PP
Data
MCDz3
2
CMD
I/O/PP/OD
Command/response
MCCDz
3
VSS1
S
Supply voltage ground
VSS
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 887
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
...........continued
Pin Number
Name
Type(1)
Description
HSMCI Pin Name(2)
(Slot z)
4
VDD
S
Supply voltage
VDD
5
CLK
O
Clock
MCCK
6
VSS2
S
Supply voltage ground
VSS
7
DAT[0]
I/O/PP
Data 0
MCDz0
8
DAT[1]
I/O/PP
Data 1
MCDz1
9
DAT[2]
I/O/PP
Data 2
MCDz2
Notes:
1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain, S: Supply
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
Figure 39-4. MMC Bus Connections (One Slot)
HSMCI
MCDA0
MCCDA
MCCK
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
9 10 11
9 10 11
9 10 11
1213 8
MMC1
1213 8
MMC2
1213 8
MMC3
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA MCDAy to HSMCIx_DAy.
Figure 39-5. SD Memory Card Bus Topology
1 2 3 4 56 78
9
SD CARD
The SD Memory Card bus includes the signals listed in the table below.
Table 39-3. SD Memory Card Bus Signals
Pin Number
Name
Type(1)
Description
HSMCI Pin Name(2)
(Slot z)
1
CD/DAT[3]
I/O/PP
Card detect/ Data line Bit 3
MCDz3
2
CMD
PP
Command/response
MCCDz
3
VSS1
S
Supply voltage ground
VSS
4
VDD
S
Supply voltage
VDD
5
CLK
O
Clock
MCCK
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 888
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
...........continued
Pin Number
Name
Type(1)
Description
HSMCI Pin Name(2)
(Slot z)
6
VSS2
S
Supply voltage ground
VSS
7
DAT[0]
I/O/PP
Data line Bit 0
MCDz0
8
DAT[1]
I/O/PP
Data line Bit 1 or Interrupt
MCDz1
9
DAT[2]
I/O/PP
Data line Bit 2
MCDz2
Notes:
1. I: input, O: output, PP: Push Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
1 2 3 4 5 6 78
Figure 39-6. SD Card Bus Connections with One Slot
MCDA0 - MCDA3
MCCK
9
MCCDA
SD CARD
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA MCDAy to HSMCIx_DAy.
When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the
HSMCI_SDCR. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the
width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can
be used as independent PIOs.
39.8
High-Speed Multimedia Card Operations
After a power-on reset, the cards are initialized by a special message-based High-Speed Multimedia Card bus
protocol. Each message is represented by one of the following tokens:
•
•
•
Command—A command is a token that starts an operation. A command is sent from the host either to a single
card (addressed command) or to all connected cards (broadcast command). A command is transferred serially
on the CMD line.
Response—A response is a token which is sent from an addressed card or (synchronously) from all connected
cards to the host as an answer to a previously received command. A response is transferred serially on the
CMD line.
Data—Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.
Card addressing is implemented using a session address assigned during the initialization phase by the bus
controller to all currently connected cards. Their unique CID number identifies individual cards.
The structure of commands, responses and data blocks is described in the High-Speed Multimedia Card System
Specification. See Table 39-4 for additional information.
High-Speed Multimedia Card bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a response token.
In addition, some operations have a data token; the others transfer their information directly within the command or
response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are
transferred synchronous to the clock HSMCI clock.
Two types of data transfer commands are defined:
•
Sequential commands—These commands initiate a continuous data stream. They are terminated only when a
stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 889
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
•
Block-oriented commands—These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple block transmission is
terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block
transmission has a predefined block count (see “Data Transfer Operation”).
The HSMCI provides a set of registers to perform the entire range of High-Speed Multimedia Card operations.
39.8.1
Command - Response Operation
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR.
The PWSEN bit saves power by dividing the HSMCI clock by 2PWSDIV + 1 when the bus is inactive.
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI
clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI
Command Register (HSMCI_CMDR). The HSMCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
Host Command
CMD
S
T
Content
NID Cycles
CRC
E
Z
******
Z
Response
High Impedance State
S
Z
T
CID Content
Z
Z
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in the following two
tables.
Table 39-4. ALL_SEND_CID Command Description
CMD Index Type Argument
CMD2
bcr(1)
Response Abbreviation
[31:0] stuff bits R2
Command Description
ALL_SEND_CID Asks all cards to send their CID numbers on the
CMD line
Note: 1. bcr means broadcast command with response.
Table 39-5. Fields and Values for HSMCI_CMDR
Field
Value
CMDNB (command number)
2 (CMD2)
RSPTYP (response type)
2 (R2: 136 bits response)
SPCMD (special command)
0 (not a special command)
OPCMD (open drain command)
1
MAXLAT (max latency for command to response)
0 (NID cycles ==> 5 cycles)
TRCMD (transfer command)
0 (No transfer)
TRDIR (transfer direction)
X (available only in transfer command)
TRTYP (transfer type)
X (available only in transfer command)
IOSPCMD (SDIO special command)
0 (not a special command)
The HSMCI_ARGR contains the argument field of the command.
To send a command, the user must perform the following steps:
1.
2.
Fill the argument register (HSMCI_ARGR) with the command argument.
Set the command register (HSMCI_CMDR).
The command is sent immediately after writing the command register.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 890
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example),
a new command shall not be sent. The NOTBUSY flag in the Status Register (HSMCI_SR) is asserted when the card
releases the busy indication.
If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The response
size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detection to
prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if needed. In this
example, the status register bits are polled but setting the appropriate bits in the HSMCI Interrupt Enable Register
(HSMCI_IER) allows using an interrupt method.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 891
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
Figure 39-7. Command/Response Functional Flow Diagram
Set the command argument
HSMCI_ARGR = Argument(1)
Set the command
HSMCI_CMDR = Command
Read HSMCI_SR
Wait for command
ready status flag
0
CMDRDY
1
Check error bits in the
status register (1)
Yes
Status error flags?
RETURN ERROR
(1)
Read response if required
Does the command involve
a busy indication?
No
RETURN OK
Read HSMCI_SR
0
NOTBUSY
1
RETURN OK
Note: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High
Speed MultiMedia Card specification) .
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 892
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
39.8.2
Data Transfer Operation
The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.).
These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register
(HSMCI_CMDR).
In all cases, the block length (BLKLEN field) must be defined either in the HSMCI Mode Register (HSMCI_MR) or in
the HSMCI Block Register (HSMCI_BLKR). This field determines the size of the data block.
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host
can use either one at any time):
•
•
39.8.3
Open-ended/Infinite Multiple block read (or write):
The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously
transfer (or program) data blocks until a stop transmission command is received.
Multiple block read (or write) with predefined block count (since version 3.1 and higher):
The card will transfer (or program) the requested number of data blocks and terminate the transaction. The
stop command is not required at the end of this type of multiple block read (or write), unless terminated with
an error. In order to start a multiple block read (or write) with predefined block count, the host must correctly
program the HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple block
read. The BCNT field of the HSMCI_BLKR defines the number of blocks to transfer (from 1 to 65535 blocks).
Programming the value 0 in the BCNT field corresponds to an infinite block transfer.
Read Operation
The following flowchart shows how to read a single block with or without use of DMAC facilities. In this example,
a polling method is used to wait for the end of read. Similarly, the user can configure the HSMCI Interrupt Enable
Register (HSMCI_IER) to trigger an interrupt at the end of read.
© 2022 Microchip Technology Inc.
and its subsidiaries
Complete Data Sheet
DS60001527G-page 893
SAM E70/S70/V70/V71
High-Speed Multimedia Card Interface (HSMCI)
Figure 39-8. Read Functional Flow Diagram
Send SELECT/DESELECT_CARD
command(1) to select the card
Send SET_BLOCKLEN command(1)
No
Yes
Read with DMAC
Reset the DMAEN bit
HSMCI_DMA &= ~DMAEN
Set the block length (in bytes)
HSMCI_BLKR l= (BlockLength
工商网监
湘ICP备2023018690号
