ATSENSE101A-SU

ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) Multi-Channel Sigma-Delta Analog Front End DATASHEET Description ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) are multi-channel analog front end devices which integrate three, four or seven simultaneously sampled Sigma-Delta A/D converters, a high-precision voltage reference with up to 10 ppm/°C temperature stability (H-versions), a programmable current signal amplification, a temperature sensor and an SPI interface. When used in data acquisition and energy measurement applications in combination with the Atmel® ATSAM4C device family that features a dedicated Cortex ® -M4 processor and metrology library and a variety of sensors i n c l u d i n g S h u n t , C T a n d R o g o w s k i c oi l s , t h e A T S E N S E - 1 0 1 / A T S E N S E 201(H)/ATSENSE-301(H) exceeds ANSI C12.20-2002 and IEC 62053-22 metering accuracy classes of up to 0.2% over 3000:1 current range. Features   Analog Front End  Single-phase (ATSENSE-101), Dual-phase (ATSENSE-201(H)) or Polyphase (ATSENSE-301(H)) Energy Metering Analog Front End Suitable for Atmel MCUs and Metrology Library  Compliant with Class 0.2 Standards (ANSI C12.20-2002 and IEC 6205322)  Three, Four or Seven Sigma-Delta ADC Measurement Channels: One, Two or Three Voltages, Two or Four Currents, 102 dB Dynamic Range  Current Channels with Pre-Gain (x1, x2, x4, x8)  Supports Shunt, Current Transformer and Rogowski Coils  Dedicated Current Channel for Anti-tamper Measurement  Integrated SINC Decimation Filters. Output Data Rate: 16 kSps typical  Integrated 2.8V LDO Regulator to Supply Analog Functions  3.0V to 3.6V Operation, Ultra Low Power: < 2.5 mW typical/Channel @ 3.3V  Specified for TJ = [-40°C; +100°C] Precision Voltage Reference  Standard 1.2V Output Voltage with Possible External Bypass  Temperature Drift: 50 ppm typical (ATSENSE-101/ATSENSE201/ATSENSE-301)  Temperature Drift: 10 ppm typical (ATSENSE-201H/ATSENSE-301H)  Factory-measured Temperature Drift and Die Temperature Sensor to Perform Software Correction 11219B–ATSENSE–20-Feb-14   Digital Interface  8 MHz Serial Peripheral Interface (SPI) Compatible Mode 1 (8-bit) for ADC Data and AFE Controls  Interrupt Output Line Signaling ADC End-of-Conversion, Underrun and Overrun Package  32-lead TQFP, 7 x 7 x 1.4 mm  20-lead SOIC, 12.8 x 7.5 x 2.3 mm ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 2 Block Diagrams VD D G A N D VR A EF ATSENSE-301(H) Functional Block Diagram VDDA VP3 ΣΔ ADC VN VD D G A N D VR A EF Decimator VDDIN Decimator ΣΔ ADC PGA 2.8V LDO ADCI3 IP3 IN3 GNDA ADCV3 Die Temperature sensor VREF Voltage Reference 500Ω VD D G A N D VR A EF GNDREF VTEMP VP2 ΣΔ ADC VN VD D G A N D VR A EF Decimator IN2 SPCK Serial Peripheral Interface ADCI2 IP2 Decimator ΣΔ ADC PGA ADCV2 NPCS MISO MOSI Control Registers D G A N D VR A EF Interrupt Controller VP1 ΣΔ ADC VN D G A N D VR A EF Decimator VD PGA ITOUT ROM (Calibration Data) ADCI1 IP1 IN1 ADCV1 Decimator ΣΔ ADC VDDT VDDIO FS_CLK (MCLK/OSR) ADC_CLK (MCLK/2) D G A N D VR A EF IP0 VD Figure 1-1. VD 1. PGA ΣΔ ADC GNDD MCLK ADCI0 IN0 DIFF MUX 2:1 Power Clock Generator On Reset Decimator VTEMP ATSENSE-301(H) ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 3 ATSENSE-201(H) Functional Block Diagram VDDIN 2.8V LDO VDDA Die Temperature sensor Voltage Reference GNDA 500Ω VD D G A N D VR A EF VTEMP VP2 ΣΔ ADC Decimator VREF GNDREF ADCV2 VN SPCK VD D G A N D VR A EF Serial Peripheral Interface VP1 ΣΔ ADC VN Decimator VD D G A N D VR A EF PGA MISO MOSI Control Registers ADCI1 IP1 IN1 ADCV1 NPCS Decimator ΣΔ ADC Interrupt Controller ITOUT ROM (Calibration Data) IP0 VD D G A N D VR A EF Figure 1-2. VDDT ADCI0 IN0 DIFF MUX 2:1 PGA ΣΔ ADC Decimator VDDIO FS_CLK (MCLK/OSR) ADC_CLK (MCLK/2) Power Clock Generator On Reset GNDD VTEMP MCLK ATSENSE-201(H) ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 4 ATSENSE-101 Functional Block Diagram VDDIN 2.8V LDO VDDA Die Temperature sensor Voltage Reference GNDA 500Ω VREF VTEMP GNDREF VD D G A N D VR A EF SPCK VP1 ΣΔ ADC VN Decimator VD D G A N D VR A EF ADCI1 IP1 PGA IN1 Serial Peripheral Interface ADCV1 NPCS MISO MOSI Control Registers Decimator ΣΔ ADC Interrupt Controller IP0 VDDT ADCI0 IN0 DIFF MUX 2:1 VTEMP PGA ΣΔ ADC ITOUT ROM (Calibration Data) VD D G A N D VR A EF Figure 1-3. Decimator VDDIO FS_CLK (MCLK/OSR) ADC_CLK (MCLK/2) Power Clock Generator On Reset GNDD MCLK ATSENSE-101 ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 5 2. Package and Pinout 2.1 ATSENSE-201(H) / ATSENSE-301(H) Table 2-1. 24 23 22 21 20 19 18 17 GNDD VDDIO - - - - - - 32-lead LQFP Package 25 ITOUT 26 SPCK 27 MOSI 28 MISO 29 NPCS 30 MCLK 31 VDDT 32 VDDIN VP2 VP1 VN VREF GNDREF GNDA VDDA ATSENSE-201(H) ATSENSE-301(H) VP3 Figure 2-1. 1 2 3 4 5 6 7 8 IP0 16 IN0 15 IP1 14 IN1 13 IP2 12 IN2 11 IP3 10 IN3 9 ATSENSE-201(H) / ATSENSE-301(H) Pin Description Pin Name I/O Pin Number Type (1) Function VP3 Input 1 Analog Voltage channel 3, positive input VP2 Input 2 Analog Voltage channel 2, positive input VP1 Input 3 Analog Voltage channel 1, positive input VN Input 4 Analog Voltage channels negative input VREF In / Out 5 Analog Voltage reference output and ADCs reference buffer input GNDREF Ground 6 Ground Voltage reference ground pin GNDA Ground 7 Ground Ground pin for low noise analog circuits and low noise negative ADC reference VDDA In / Out 8 Analog 2.8V LDO output and analog circuits power supply input (1) Input 9 Analog Current channel 3, negative input (1) Input 10 Analog Current channel 3, positive input (1) IN2 Input 11 Analog Current channel 2, negative input IP2(1) Input 12 Analog Current channel 2, positive input IN1 Input 13 Analog Current channel 1, negative input IP1 Input 14 Analog Current channel 1, positive input IN0 Input 15 Analog Current channel 0 (Tamper), negative input IP0 Input 16 Analog Current channel 0 (Tamper), positive input - 17 .. 22 - VDDIO Input 23 Power Power supply input pin for digital I/O and digital core circuits GNDD Ground 24 Ground Ground pin for digital I/O and digital core circuits IN3 IP3 - Not connected. Connect to ground ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 6 Table 2-1. Pin Name ATSENSE-201(H) / ATSENSE-301(H) Pin Description (Continued) I/O Pin Number Type Function ITOUT Output 25 Digital Interrupt output line. Open-drain SPCK Input 26 Digital SPI port: serial clock MOSI Input 27 Digital SPI port: master output slave input MISO Output 28 Digital SPI port: master input slave output NPCS Input 29 Digital SPI port: active-low chip select MCLK Input 30 Digital Master clock input VDDT Input 31 Power Pin reserved for test. Connect to VDDIN / VDDIO plane VDDIN Input 32 Power 2.8V LDO power supply input pin Note: 1. Only in ATSENSE-301(H) devices. In ATSENSE-201(H) devices, these pins are not internally connected and Atmel recommends to connect them to ground. ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 7 ATSENSE-101 17 13 12 11 IP1 18 14 IP0 15 19 IN0 16 20 MOSI 17 SPCK 18 ITOUT 19 VDDIO 20 GNDD 20-lead SOIC Package MISO Figure 2-2. NPCS 2.2 Table 2-2. Pin Name MCLK VDDT VDDIN VP1 VN VREF GNDREF GNDA VDDA IN1 ATSENSE-101 1 2 3 4 5 6 7 8 9 10 ATSENSE-101 Pin Description I/O Pin Number Type Function MCLK Input 1 Digital Master clock Input VDDT Input 2 Power Pin reserved for test. Connect to VDDIN / VDDIO plane VDDIN Input 3 Power 2.8V LDO Power supply input pin VP1 Input 4 Analog Voltage channel 1, positive input VN Input 5 Analog Voltage channel negative input VREF In / Out 6 Analog Voltage reference output and ADCs reference buffer input GNDREF Ground 7 Ground Voltage reference ground pin GNDA Ground 8 Ground Ground pin for low noise analog circuits and low noise negative ADC reference VDDA In / Out 9 Analog 2.8V LDO output and analog circuits power supply input IN1 Input 10 Analog Current channel 1, negative input IP1 Input 11 Analog Current channel 1, positive input IN0 Input 12 Analog Current channel 0 (Tamper), negative input IP0 Input 13 Analog Current channel 0 (Tamper), positive input MOSI Input 14 Digital SPI port: master output slave input SPCK Input 15 Digital SPI port: serial clock ITOUT Output 16 Digital Interrupt output line. open drain VDDIO Input 17 Power Power supply input pin for digital I/O and digital core circuits GNDD Ground 18 Ground Ground pin for digital I/O and digital core circuits MISO Output 19 Digital SPI port: master input slave output NPCS Input 20 Digital SPI port: active-low chip select ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 8 C.T 2000:1 C.T 2000:1 L2 C.T 2000:1 L3 N Shunt 150μR 3k 3k 3.3nF 3.3nF 3.3nF 1.5 3k 3.3nF 1.5 3k 165k (x10) 1k 3.3nF 3k 3.3nF 1.5 1k 1.5 3k 165k (x10) 3.3nF 3k 3.3nF 1.5 1k 1.5 3k 165k (x10) 2.2k 2.2k 2.2k 3.3nF 3.3nF 3.3nF IN0 IP0 IN1 IP1 VN VP1 IN2 IP2 VN VP2 IN3 IP3 VN VP3 VTEMP A A D ND EF VD G VR DIFF MUX 2:1 PGA A A D ND EF VD G VR A A D ND EF VD G VR ΣΔ ADC A A D ND EF VD G VR Decimator Decimator Decimator Decimator Decimator Decimator Decimator ADCI0 ADCI1 ADCV1 ADCI2 ADCV2 ADCI3 ADCV3 FS_CLK (MCLK/2) ADC_CLK (MCLK/OSR) Interrupt Controller Control Registers Serial Peripheral Interface Voltage Reference VREF VDDIN VDDT MCLK GNDD VDDIO ATSENSE-301(H) Power Clock Generator On Reset ITOUT MOSI MISO NPCS SPCK GNDREF 500Ω ROM (Calibration Data) VTEMP Die Temperature sensor 2.8V LDO VDDA GNDA 1μF 1μF Typical 200A (Imax), 3-phase, 4-Wire Smart Meter based on Atmel Metrology Solution PGA ΣΔ ADC A A D ND EF VD G VR ΣΔ ADC ΣΔ ADC PGA A A D ND EF VD G VR ΣΔ ADC ΣΔ ADC PGA ΣΔ ADC A A D ND EF VD G VR 1μF VARh 100 PIOs SPI Wh 100 32.768kHz Atmel MCU VDDIO VDD 3.3V Figure 3-1. L1 3. Application Block Diagram ATSENSE-301(H) Typical Application Block Diagram ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 9 C.T 2000:1 C.T 2000:1 L2 N 3.3nF 1.5 3.3k 3.3nF 1.5 3.3k 3.3nF 1.5 3.3k 3.3nF 1.5 3.3k 165k (x10) 165k (x10) 2.2k 1k 2.2k 1k 3.3nF 3.3nF IN0 IP0 IN1 IP1 VN VP1 VN VP2 VTEMP VD D G A ΣΔ ADC N D VR A EF DIFF MUX 2:1 PGA N D VR A EF VD D G A ΣΔ ADC Decimator Decimator Decimator Decimator 2.8V LDO VDDIN ADCI0 ADCI1 ADCV1 ADCV2 FS_CLK Clock Power Generator On Reset MCLK GNDD VDDIO VDDT ITOUT MOSI MISO NPCS SPCK GNDREF ATSENSE-201(H) (MCLK/2) ADC_CLK GNDA VDDA 500Ω VREF ROM (Calibration Data) Interrupt Controller Control Registers Serial Peripheral Interface Voltage Reference (MCLK/OSR) VTEMP Die Temperature sensor Typical 100A (Imax), Dual-phase Smart Meter based on Atmel Metrology Solution PGA ΣΔ ADC ΣΔ ADC VD D G A N D VR A EF L1 VD D G A N D VR A EF 1μF 1μF 1μF VARh 100 PIOs SPI Wh 100 32.768 kHz Atmel MCU VDDIO VDD 3.3V Figure 3-2. ATSENSE-201(H) Typical Application Block Diagram ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 10 C.T 2000:1 L N Shunt 150uR 3.3k 3.3k 3.3nF 3.3nF 3.3nF 1.5 3.3k 3.3nF 1.5 3.3k 165k (x10) 2.2k 1k 3.3nF IN0 IP0 IN1 IP1 VN VP1 PGA ΣΔ ADC A A D ND EF VD G VR ΣΔ ADC A A D ND EF VD G VR Decimator Decimator Decimator ADCI0 ADCI1 ADCV1 FS_CLK (MCLK/2) ADC_CLK 500Ω VREF SPCK MCLK GNDD VDDIO VDDT ITOUT MOSI MISO NPCS ATSENSE-101 Power Clock Generator On Reset VDDA GNDA GNDREF ROM (Calibration Data) Interrupt Controller Control Registers Serial Peripheral Interface Voltage Reference (MCLK/OSR) VTEMP Die Temperature sensor 1μF 1μF 1μF VARh 100 PIOs SPI Typical 100A (Imax), Single-phase with anti-tamper Smart Meter based on Atmel Metrology Solution VTEMP DIFF MUX 2:1 PGA ΣΔ ADC A A D ND EF VD G VR 2.8V LDO VDDIN Wh 100 32.768 kHz Atmel MCU VDDIO VDD 3.3V Figure 3-3. ATSENSE-101 Typical Application Block Diagram ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 11 4. Functional Description 4.1 Conversion Channels ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) devices feature three types of acquisition channels:  Voltage channels  Current channels  Tamper and temperature channels All these channels are built around the same Sigma-Delta A/D converter. The voltage reference of this converter is the VREF pin voltage referred to ground (GNDA pin). This reference voltage can be internally or externally sourced. The converter sampling rate is MCLK/4, typically 1.024 MHz. An external low-pass filter, typically a passive R-C network, is required at each ADC input to reject frequency images around this sampling frequency (anti-alias). ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) analog inputs are designed to sample 0V centered signals. As these inputs have internal ESD protection devices connected to GNDA, the maximum input signal level defined in the electrical characteristics, typically ±0.25V, must be respected to avoid leakage in these devices. Refer to Figure 4-1, "Analog Inputs: Recommended Input Range". Figure 4-1. Analog Inputs: Recommended Input Range VDDA +0.25V E.S.D IPx V(IPx,GND) (0.5Vpp) E.S.D -0.25V GNDA +0.5V V(IPx,VINx) (1Vpp) VDDA +0.25V -0.5V “Current” Acquisition Channel E.S.D INx V(INx,GND) (0.5Vpp) E.S.D -0.25V GNDA VDDA +0.25V E.S.D VPx V(VPx,GND) (0.5Vpp) E.S.D -0.25V GNDA +0.25V V(VPx,VN) (0.5Vpp) VDDA -0.25V “Voltage” Acquisition Channel E.S.D VN GND E.S.D GNDA Voltage channels have single-ended inputs referred to the VN pin. The VN pin must be connected to a low noise ground. The user must take care that no voltage drop on the ground net is sampled by the ADC by non-optimum connection of the VN pin. Current channels and the tamper channel have a programmable gain amplifier (PGA) to accommodate low input signals. The PGA improves the dynamic range of the channel as the input referred noise is reduced when gain increases. The PGA does not introduce any delay or bandwidth limitation on the current channels compared to the voltage channels. The channels (voltage or current) are always sampled synchronously. The input impedance of the PGA depends on the programmed gain. The tamper channel features an input multiplexer to perform both the neutral current measurement and the die temperature measurement. The tamper channel has a PGA to accommodate low output level current sensors. Programmed gain can be changed when switching from the tamper to the die temperature sensor source. ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) [DATASHEET] 11219B–ATSENSE–20-Feb-14 12 4.2 Voltage Reference, Die Temperature Measurement and Calibration Registers 4.2.1 Voltage Reference ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) embed an analog voltage reference with a typical output voltage of 1.144V. The temperature drift of the voltage reference can be approximated by a linear fit. For H grade parts, the temperature drift is measured during manufacturing and stored in the calibration registers (ROM). Two measurements are made: one at a low temperature, TL, and another at a high temperature, TH. At both temperatures TL and TH, VREF voltage and ADC_TEMP_OUT (ADC I0 reading of the temperature sensor) parameters are saved. From the data obtained, the user can implement a software compensation of the voltage reference. 4.2.2 Die Temperature Sensor To measure the internal die temperature, ATSENSE-101/ATSENSE-201(H)/ATSENSE-301(H) devices embed a dedicated analog die temperature sensor that is multiplexed on the tamper channel (ADC I0). By measuring the die temperature periodically and by using the calibration bits, channel gain drifts over temperature due to the voltage reference can be corrected. To set the ADC to measure the temperature sensor, the user must set the TEMPMEAS bit in ADC I0 control register and ensure that the channel gain is set to x1 (0dB). Once the temperature measurement is selected, the ADC starts to output samples corresponding to the temperature sensor. The first four samples account for internal digital filters settling and must be ignored. Then, in order to have a repeatable temperature acquisition, the user must average the ADC output over a minimum of 64 samples. By following this procedure, the temperature acquisition set measurement exhibits a standard deviation of less than 0.25°C in repeatability. To calculate the real die temperature from the ADC acquisition, the following formula applies: TJ(°C) = ( (ADC_TEMP_OUT / 2 24) x 1.144 - 0.110) / 0.00049 where ADC_TEMP_OUT is the 24-bit output of ADC I0, averaged over 64 samples. Example: If ADC_TEMP_OUT = 1777345, the corresponding die temperature is TJ = 22.8°C. Because the temperature sensor is not offset-calibrated, the absolute temperature reading exhibits a large deviation (typically ±15°C). 4.2.3 Calibration Registers The registers used in the voltage reference compensation are listed in Table 4-1. The four parameters stored, VREF and ADC_TEMP_OUT at TL and TH, are:  REF_TL[11:0] and REF_TH[11:0]  TEMP_TL[11:0] and TEMP_TH[11:0] The following rule applies to recover the real values of VREF from the 12-bit coded values in the product registers:  VREF(TL) = 1.120V + REF_TL[11:0] * 25µV  VREF(TH) = 1.120V + REF_TH[11:0] * 25µV Note: REF_TL[11:0] and REF_TH[11:0] are unsigned 12-bit integers. The following rule applies to recover the real values of ADC_TEMP_OUT from the 12-bit coded values in the product registers:  ADC_TEMP_OUT[23:0](TL) = TEMP_TL[11:0]