8-bit AVR Microcontroller
ATtiny102 / ATtiny104
DATASHEET COMPLETE
Introduction
®
The Atmel ATtiny102/ATtiny104 is a low-power CMOS 8-bit microcontroller
based on the AVR® enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the ATtiny102/ATtiny104 achieves
throughputs close to 1 MIPS per MHz. This empowers system designer to
optimize the device for power consumption versus processing speed.
Feature
High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller Family
•
Advanced RISC Architecture
– 54 Powerful Instructions
– Mostly Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12MHz
•
Non-volatile Program and Data Memories
– 1024 Bytes of In-system Programmable Flash Program Memory
– 32 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85°C / 100 Years at 25°C
– Self-programming Flash on Full Operating Voltage Range (1.8 –
5.5V)
•
Peripheral Features
– One 16-bit Timer/Counter (TC) with Prescaler, Input Capture,
Two Output Capture and Two PWM Channels
– Programmable Watchdog Timer (WDT) with Separate On-chip
Oscillator
– Selectable Internal Voltage References: 1.1V, 2.2V and 4.3V
– 10-bit ADC with 8-channels/14-pin and 5-channel/8-pin Package
Options
– On-chip Analog Comparator (AC)
– Serial Communication Module: USART
Atmel-42505C-ATtiny102 / ATtiny104_Datasheet_Complete-07/2016
•
•
•
•
•
Special Microcontroller Features
– In-system Programmable
• External Programming (2.7 – 5.5V)
• Self Programming (1.8 – 5.5V)
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-pown Modes
– Enhanced Power-on Reset Circuit
– Programmable Supply Voltage Level Monitor with Interrupt and Reset
– Accurate Internal Calibrated Oscillator
– Fast and Normal Start-up Time Options Available
– Individual Serial Number to Represent a Unique ID.
I/O and Packages
– 12 Programmable I/O Lines for ATtiny104 and 6 Programmable I/O Lines for ATtiny102
– 8-pin UDFN (ATtiny102)
– 8-pin SOIC150 (ATtiny102)
– 14-pin SOIC150 (ATtiny104)
Operating Voltage
– 1.8 - 5.5V
Temperature Range
– -40 to +125°C
Speed Grades
– 0 – 4MHz at 1.8 – 5.5V
– 0 – 8MHz at 2.7 – 5.5V
– 0 – 12MHz at 4.5 – 5.5V
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Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description.................................................................................................................8
2. Configuration Summary............................................................................................. 9
3. Ordering Information ...............................................................................................10
4. Block Diagram..........................................................................................................11
5. Pin Configurations................................................................................................... 12
5.1.
Pin Descriptions..........................................................................................................................12
6. I/O Multiplexing........................................................................................................ 14
7. General Information................................................................................................. 15
7.1.
7.2.
7.3.
Resources.................................................................................................................................. 15
Data Retention............................................................................................................................15
About Code Examples................................................................................................................15
8. AVR CPU Core........................................................................................................ 16
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
Overview.....................................................................................................................................16
Features..................................................................................................................................... 16
Block Diagram............................................................................................................................ 16
ALU – Arithmetic Logic Unit........................................................................................................18
Status Register...........................................................................................................................18
General Purpose Register File................................................................................................... 19
The X-register, Y-register, and Z-register................................................................................... 19
Stack Pointer.............................................................................................................................. 20
8.9. Instruction Execution Timing...................................................................................................... 20
8.10. Reset and Interrupt Handling..................................................................................................... 21
8.11. Register Description................................................................................................................... 22
9. AVR Memories.........................................................................................................28
9.1.
9.2.
9.3.
9.4.
9.5.
Overview.....................................................................................................................................28
Features..................................................................................................................................... 28
In-System Reprogrammable Flash Program Memory................................................................ 28
SRAM Data Memory...................................................................................................................28
I/O Memory.................................................................................................................................30
10. Clock System...........................................................................................................31
10.1. Overview.....................................................................................................................................31
10.2. Clock Distribution........................................................................................................................31
10.3. Clock Subsystems......................................................................................................................31
10.4. Clock Sources............................................................................................................................ 32
10.5. System Clock Prescaler............................................................................................................. 33
10.6. Starting....................................................................................................................................... 34
10.7. Register Description................................................................................................................... 35
11. Power Management and Sleep Modes....................................................................40
11.1.
11.2.
11.3.
11.4.
11.5.
11.6.
Overview.....................................................................................................................................40
Features..................................................................................................................................... 40
Sleep Modes...............................................................................................................................40
Power Reduction Register..........................................................................................................41
Minimizing Power Consumption................................................................................................. 42
Register Description................................................................................................................... 43
12. SCRST - System Control and Reset....................................................................... 46
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
Overview.....................................................................................................................................46
Features..................................................................................................................................... 46
Resetting the AVR...................................................................................................................... 46
Reset Sources............................................................................................................................47
Watchdog Timer......................................................................................................................... 49
Register Description................................................................................................................... 51
13. Interrupts................................................................................................................. 56
13.1.
13.2.
13.3.
13.4.
Overview.....................................................................................................................................56
Interrupt Vectors ........................................................................................................................ 56
External Interrupts...................................................................................................................... 57
Register Description................................................................................................................... 58
14. I/O-Ports.................................................................................................................. 66
14.1.
14.2.
14.3.
14.4.
14.5.
Overview.....................................................................................................................................66
Features..................................................................................................................................... 66
I/O Pin Equivalent Schematic.....................................................................................................66
Ports as General Digital I/O........................................................................................................67
Register Description................................................................................................................... 80
15. USART - Universal Synchronous Asynchronous Receiver Transceiver..................90
15.1. Overview.....................................................................................................................................90
15.2. Features..................................................................................................................................... 90
15.3. Block Diagram............................................................................................................................ 90
15.4. Clock Generation........................................................................................................................91
15.5. Frame Formats...........................................................................................................................94
15.6. USART Initialization....................................................................................................................95
15.7. Data Transmission – The USART Transmitter........................................................................... 96
15.8. Data Reception – The USART Receiver.................................................................................... 98
15.9. Asynchronous Data Reception.................................................................................................101
15.10. Multi-Processor Communication Mode.................................................................................... 105
15.11. Examples of Baud Rate Setting............................................................................................... 106
15.12. Register Description.................................................................................................................109
16. USARTSPI - USART in SPI Mode.........................................................................121
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16.1. Overview...................................................................................................................................121
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
16.8.
Features................................................................................................................................... 121
Clock Generation......................................................................................................................121
SPI Data Modes and Timing.....................................................................................................122
Frame Formats.........................................................................................................................122
Data Transfer............................................................................................................................124
AVR USART MSPIM vs. AVR SPI............................................................................................125
Register Description................................................................................................................. 125
17. TC0 - 16-bit Timer/Counter0 with PWM.................................................................126
17.1. Overview...................................................................................................................................126
17.2. Features................................................................................................................................... 126
17.3. Block Diagram.......................................................................................................................... 126
17.4. Definitions.................................................................................................................................127
17.5. Registers.................................................................................................................................. 128
17.6. Accessing 16-bit Registers.......................................................................................................129
17.7. Timer/Counter Clock Sources.................................................................................................. 131
17.8. Counter Unit............................................................................................................................. 133
17.9. Input Capture Unit.................................................................................................................... 134
17.10. Output Compare Units............................................................................................................. 136
17.11. Compare Match Output Unit.....................................................................................................138
17.12. Modes of Operation..................................................................................................................139
17.13. Timer/Counter Timing Diagrams.............................................................................................. 147
17.14. Register Description.................................................................................................................148
18. AC - Analog Comparator....................................................................................... 166
18.1.
18.2.
18.3.
18.4.
Overview...................................................................................................................................166
Features................................................................................................................................... 166
Block Diagram.......................................................................................................................... 166
Register Description................................................................................................................. 167
19. ADC - Analog to Digital Converter.........................................................................172
19.1. Overview...................................................................................................................................172
19.2. Features................................................................................................................................... 172
19.3. Block Diagram.......................................................................................................................... 172
19.4. Operation..................................................................................................................................173
19.5. Starting a Conversion...............................................................................................................174
19.6. Prescaling and Conversion Timing...........................................................................................175
19.7. Changing Channel or Reference Selection.............................................................................. 178
19.8. ADC Input Channels.................................................................................................................178
19.9. ADC Voltage Reference........................................................................................................... 178
19.10. ADC Noise Canceler................................................................................................................ 179
19.11. Analog Input Circuitry............................................................................................................... 179
19.12. Analog Noise Canceling Techniques........................................................................................180
19.13. ADC Accuracy Definitions........................................................................................................ 180
19.14. ADC Conversion Result........................................................................................................... 182
19.15. Register Description.................................................................................................................182
20. MEMPROG- Memory Programming......................................................................193
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20.1. Overview...................................................................................................................................193
20.2.
20.3.
20.4.
20.5.
20.6.
20.7.
Features................................................................................................................................... 193
Non-Volatile Memories (NVM)..................................................................................................194
Accessing the NVM.................................................................................................................. 199
Self programming..................................................................................................................... 202
External Programming..............................................................................................................202
Register Description................................................................................................................. 203
21. TPI-Tiny Programming Interface............................................................................206
21.1.
21.2.
21.3.
21.4.
21.5.
21.6.
21.7.
Overview...................................................................................................................................206
Features................................................................................................................................... 206
Block Diagram.......................................................................................................................... 206
Physical Layer of Tiny Programming Interface.........................................................................207
Instruction Set...........................................................................................................................211
Accessing the Non-Volatile Memory Controller........................................................................ 213
Control and Status Space Register Descriptions..................................................................... 214
22. Electrical Characteristics ...................................................................................... 218
22.1.
22.2.
22.3.
22.4.
22.5.
22.6.
22.7.
22.8.
Absolute Maximum Ratings*.................................................................................................... 218
DC Characteristics....................................................................................................................218
Speed....................................................................................................................................... 220
Clock Characteristics................................................................................................................221
System and Reset Characteristics........................................................................................... 222
Analog Comparator Characteristics..........................................................................................223
ADC Characteristics ................................................................................................................ 224
Serial Programming Characteristics.........................................................................................225
23. Typical Characteristics...........................................................................................226
23.1. Active Supply Current...............................................................................................................226
23.2. Idle Supply Current...................................................................................................................229
23.3. Supply Current of I/O Modules................................................................................................. 230
23.4. Power-down Supply Current.....................................................................................................231
23.5. Pin Driver Strength................................................................................................................... 232
23.6. Pin Threshold and Hysteresis...................................................................................................236
23.7. Analog Comparator Offset........................................................................................................240
23.8. Pin Pull-up................................................................................................................................ 241
23.9. Internal Oscillator Speed.......................................................................................................... 244
23.10. VLM Thresholds....................................................................................................................... 246
23.11. Current Consumption of Peripheral Units.................................................................................248
23.12. Current Consumption in Reset and Reset Pulsewidth............................................................. 251
24. Register Summary.................................................................................................252
24.1. Note..........................................................................................................................................253
25. Instruction Set Summary....................................................................................... 254
26. Packaging Information...........................................................................................258
26.1. 8-pin UDFN...............................................................................................................................258
26.2. 8-pin SOIC150..........................................................................................................................259
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26.3. 14-pin SOIC150........................................................................................................................260
27. Errata.....................................................................................................................261
27.1. ATtiny102..................................................................................................................................261
27.2. ATtiny104..................................................................................................................................261
28. Datasheet Revision History................................................................................... 262
28.1. Rev C - 07/2016....................................................................................................................... 262
28.2. Rev B - 06/2016........................................................................................................................262
28.3. Rev A - 02/2016........................................................................................................................262
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1.
Description
The Atmel®AVR® core combines a rich instruction set with 16 general purpose working registers. All the
16 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more
code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The device provides the following features: 1024 Bytes of In-System Programmable Flash with ReadWhile-Write capabilities, 32 Bytes SRAM, 6/12 general purpose I/O lines for ATtiny102/ATtiny104, 16
general purpose working registers, a 16-bit Timer/Counters (TC) with compare modes, internal and
external interrupts, one serial programmable USART, a programmable Watchdog Timer with internal
Oscillator and three software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, TC, USART, ADC, Analog Comparator (AC), and interrupt system to continue
functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping
the CPU and all I/O modules except the ADC. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset.
The device is manufactured using Atmel’s high density Non-Volatile Memory (NVM) technology. The onchip, in-system programmable Flash allows program memory to be re-programmed in-system by a
conventional, NVM programmer.
The device is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kit.
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2.
Configuration Summary
ATtiny102
ATtiny104
Pin Count
8
14
Flash (Bytes)
1024
1024
SRAM (Bytes)
32
32
EEPROM (Bytes)
-
-
General Purpose I/O-pins (GPIOs)
6
12
USART
1
1
Analog-to-Digital Converter (ADC) / Channels
10-bit ADC with 5-channel 10-bit ADC with 8-channels
Analog Comparators (AC) Channels
1
1
AC Propagation Delay
75-750ns
75-750ns
16-bit Timer Counter (TC) Instances
1
1
PWM Channels
2
2
RC Oscillator
+/-2 %
+/-2 %
Internal Voltage Reference
1.1V/2.2V/4.3V
1.1V/2.2V/4.3V
Operating Voltage
1.8 - 5.5V
Max Operating Frequency (MHz)
12
Temperature Range
-40°C to +125°C
Packages
8-pin UDFN
14-pin SOIC150
8-pin SOIC150
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3.
Ordering Information
Speed [MHz]
Power Supply [V]
Ordering Code
Package
Operational Range
12
1.8 -5.5
ATtiny102-M7R
8 pad UDFN
Industrial (-40°C to +105°C)
ATtiny102F-M7R(1)
8 pad UDFN
ATtiny102-SSNR
8 pin SOIC150
ATtiny102F-SSNR(1)
8 pin SOIC150
ATtiny104-SSNR
14 pin SOIC150
ATtiny104F-SSNR(1)
14 pin SOIC150
ATtiny102-M8R
8 pad UDFN
ATtiny102F-M8R(1)
8 pad UDFN
ATtiny102-SSFR
8 pin SOIC150
ATtiny102F-SSFR(1)
8 pin SOIC150
ATtiny104-SSFR
14 pin SOIC150
ATtiny104F-SSFR(1)
14 pin SOIC150
Industrial (-40°C to +125°C)
Note:
1. ATtiny104F-xxx and ATtiny102F-xxx have the fast start-up time option.
Package Type
8 pad UDFN 8-pad, 2 x 3 x 0.6mm Body, Thermally Enhanced Plastic Ultra Thin Dual Flat No-Lead Package (UDFN)
8 pin
SOIC150
8-lead, 0.150” Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC)
14 pin
SOIC150
14-lead, 1.27mm Pitch, 8.65 x 3.90 x 1.60mm Body Size, Plastic Small Outline Package (SOIC)
Related Links
Starting from Reset on page 34
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4.
Block Diagram
Figure 4-1. Block Diagram
SRAM
FLASH
CPU
Clock generation
8MHz Calib Osc
External clock
128 kHz Internal Osc
Vcc
RESET
Power
Supervision
POR & RESET
GND
RxD0
TxD0
XCK0
Power
management
and clock
control
Watchdog
Timer
I/O
PORTS
D
A
T
A
B
U
S
Interrupt
PA[7:0]
PB[3:0]
PCINT[11:0]
INT0
ADC
ADC[7:0]
Vcc
Internal
Reference
AC
AIN0
AIN1
ACO
ACPMUX
USART 0
TC 0
OC0A/B
T0
ICP0
(16-bit)
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5.
Pin Configurations
Figure 5-1. Pin-Out of 8-Pin UDFN
Caution: The thermal pad on the rear of the package should not be connected.
Figure 5-2. Pin-Out of 8-Pin SOIC150
VCC
1
8
GND
(PCINT0/T0/CLKI/AIN0/ADC0/TPICLK) PA0
2
7
PB3 (ADC7/T0/RxD0/ACO/PCINT11)
(PCINT1/OC0B/AIN1/ADC1/TPIDATA ) PA1
3
6
PB2 (ADC6/ICP0/TxD0/PCINT10)
(PCINT2/RESET) PA2
4
5
PB1 (ADC5/CLKO/INT0/OC0A/PCINT9)
Figure 5-3. Pin-Out of 14-Pin SOIC150
VCC
1
14
GND
(PCINT0/T0/CLKI/AN0/ADC0/TPICLK) PA0
2
13
PB3 (ADC7/ACO/RxD0/T0*/PCINT11)
(PCINT1/OC0B/AIN1/ADC1/TPIDATA ) PA1
3
12
PB2 (ADC6/ICP0/TxD0/PCINT10)
(PCINT2/RESET) PA2
4
11
PB1 (ADC5/CLKO/INT0/OC0A/PCINT9)
(PCINT3/OC0A*) PA3
5
10
PB0 (ADC4/PCINT8)
(PCINT4/ICP0*) PA4
6
9
PA7 (PCINT7)
(PCINT5/OC0B*/ADC2) PA5
7
8
PA6 (ADC3/PCINT6)
5.1.
Pin Descriptions
5.1.1.
VCC
Digital supply voltage.
Power
Programming
Digital
Ground
Ext clock
Analog
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5.1.2.
GND
Ground.
5.1.3.
Port A (PA[7:0])
This is a 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The
output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs,
the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins
are tri-stated when a reset condition becomes active, even if the clock is not running.
5.1.4.
Port B (PB[3:0])
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The
output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs,
the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins
are tri-stated when a reset condition becomes active, even if the clock is not running.
5.1.5.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is
given in System and Reset Characteristics of Electrical Characteristics. Shorter pulses are not
guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
Related Links
System and Reset Characteristics on page 222
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6.
I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions. The following table describes the peripheral signals
multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
Special
INT(3)
ADC(3)
AC
Timer
Programming(8)
CLKI
PCINT0
ADC0
AIN0
T0
TPICLK
PCINT1
ADC1
AIN1
OC0B
TPIDATA
14-pin
8-pin
Pin name
1
1(1)
VCC
2
2
PA[0](2)
3
3
PA[1](5)
4
4
PA[2]
5
-
PA[3](9)
PCINT3
OC0A
6
-
PA[4](9)
PCINT4
ICP0
7
-
PA[5](5)(9)
PCINT5
ADC2
8
-
PA[6]
PCINT6
ADC3
9
-
PA[7]
PCINT7
10
-
PB[0]
PCINT8
ADC4
11
5
PB[1](6)
PCINT9/INT0
ADC5
XCK0
OC0A
12
6
PB[2](7)
PCINT10
ADC6
TxD0
ICP0
13
7
PB[3](4)(9)
PCINT11
ADC7
RxD0
T0
14
8
GND
RESET
CLKO
USART
PCINT2
RESET
OC0B
ACO
Note:
1. On the 8-pin UDFN package, the thermal pad should not be connected as well.
2. Priority of CLKI is higher than ADC0. When EXT_CLK is enabled, ADC channel will not work and
DIDR0 will not disable the digital input buffer.
3. When both PCINT and the corresponding ADC channel are enabled, the digital input buffer will not
be disabled.
4. When ACO is enabled, ADC, TC and USART RX inputs are not disabled.
5. When OC0B is enabled, ADC and AC will continue to receive inputs on that channel if enabled.
6. When CLKO is enable in PB[1], OCA will get lower priority.
7. When USART is enabled, the users must ensure that ADC channel corresponding to the TxD0 pin
is not used. Because DIDR0 register will only control the input buffer, not the output part.
8. During reset/external programming, all pins are treated as inputs and outputs are disabled.
9. Alternative location when enabling T/C Remap
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7.
General Information
7.1.
Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.atmel.com/avr.
7.2.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
7.3.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
Related Links
Reset and Interrupt Handling on page 21
Code Examples on page 51
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8.
AVR CPU Core
8.1.
Overview
The Atmel®AVR® core combines a rich instruction set with 16 general purpose working registers. All the
16 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more
code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
8.2.
Features
•
•
•
•
•
•
8.3.
Advanced RISC Architecture
54 Powerful Instructions
Mostly Single Clock Cycle Execution
16 x 8 General Purpose Working Registers
Fully Static Operation
Up to 12 MIPS Throughput at 12MHz
Block Diagram
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
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Figure 8-1. Block Diagram of the AVR Architecture
Program
counter
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R19
R17
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R18
R16
Flash program
memory
Instruction
register
Instruction
decode
Data memory
Stack
pointer
Status
register
ALU
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 16 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a
register. Single register operations can also be executed in the ALU. After an arithmetic operation, the
Status Register is updated to reflect information about the result of the operation.
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Program flow is provided by conditional and unconditional jump and call instructions, able to directly
address the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide
instructions also exist. The actual instruction set varies, as some devices only implement a part of the
instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.
The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only
limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the
Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write
accessible in the I/O space. The data SRAM can easily be accessed through the four different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt
Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector
table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,
and other I/O functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F.
See Instruction Set Summary section for a detailed description.
Related Links
Instruction Set Summary on page 254
8.4.
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 16 general purpose working
registers. Within a single clock cycle, arithmetic operations between general purpose registers or between
a register and an immediate are executed. The ALU operations are divided into three main categories –
arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful
multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction Set
Summary section for a detailed description.
Related Links
Instruction Set Summary on page 254
8.5.
Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set
Reference. This will in many cases remove the need for using the dedicated compare instructions,
resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when
returning from an interrupt. This must be handled by software.
Related Links
Instruction Set Summary on page 254
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8.6.
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the Register
File:
•
•
•
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
One 16-bit output operand and one 16-bit result input
Figure 8-2. AVR CPU General Purpose Working Registers
7
0
R16
R17
General
R18
Purpose
…
Working
R26
X-register Low Byte
Registers
R27
X-register High Byte
R28
Y-register Low Byte
R29
Y-register High Byte
R30
Z-register Low Byte
R31
Z-register High Byte
Note: A typical implementation of the AVR register file includes 32 general purpose registers but
ATtiny102/ATtiny104 implement only 16 registers. For reasons of compatibility the registers are numbered
R16...R31, not R0...R15.
Most of the instructions operating on the Register File have direct access to all registers, and most of
them are single cycle instructions.
8.7.
The X-register, Y-register, and Z-register
The registers R26...R31 have some added functions to their general purpose usage. These registers are
16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,
Y, and Z are defined as described in the figure.
Figure 8-3. The X-, Y-, and Z-registers
15
X-register
7
15
Y-register
XL
0
7
R26
YH
YL
0
7
R28
ZH
ZL
0
R31
0
0
R29
7
0
0
R27
7
15
Z-register
XH
7
0
0
R30
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In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
Related Links
Instruction Set Summary on page 254
8.8.
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return
addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to
lower memory locations. The Stack Pointer Register always points to the top of the Stack, and the Stack
Pointer must be set to point above 0x40.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are
located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be
defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack
Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point
above start of the SRAM. See the table for Stack Pointer details.
Table 8-1. Stack Pointer Instructions
Instruction Stack pointer
Description
PUSH
Decremented by 1 Data is pushed onto the stack
ICALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
RCALL
POP
Incremented by 1
Data is popped from the stack
RET
Incremented by 2
Return address is popped from the stack with return from subroutine or
return from interrupt
RETI
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR
architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
8.9.
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal
clock division is used. The Figure below shows the parallel instruction fetches and instruction executions
enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
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Figure 8-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following Figure shows the internal timing concept for the Register File. In a single clock cycle an
ALU operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 8-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
8.10.
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector
each have a separate program vector in the program memory space. All interrupts are assigned individual
enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status
Register in order to enable the interrupt.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt
Vectors. The complete list of vectors is shown in Interrupts. They have determined priority levels: The
lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the
External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The
user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then
interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt
instruction – RETI – is executed.
There are basically two types of interrupts:
•
The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program
Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine,
and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing
a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the
interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions
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occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set
and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of
priority.
•
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
The Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No
interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before
any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
Note: See Code Examples
Related Links
Interrupts on page 56
8.10.1.
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After
four clock cycles the program vector address for the actual interrupt handling routine is executed. During
this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump
to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs
when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles.
This increase comes in addition to the start-up time from the selected sleep mode. A return from an
interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter
(two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG
is set.
8.11.
Register Description
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8.11.1.
Configuration Change Protection Register
Name: CCP
Offset: 0x3C
Reset: 0x00
Property:
Bit
7
6
5
4
3
2
1
0
0
0
0
0
CCP[7:0]
Access
Reset
0
0
0
0
Bits 7:0 – CCP[7:0]: Configuration Change Protection
In order to change the contents of a protected I/O register, the CCP register must first be written with the
correct signature. After CCP is written, the protected I/O registers may be written to during the next four
CPU instruction cycles. All interrupts are ignored during these cycles. After these cycles interrupts are
automatically handled again by the CPU, and any pending interrupts will be executed according to their
priority.
When the protected I/O register signature is written, CCP[0] will read as one as long as the protected
feature is enabled, while CCP[7:1] will always read as zero.
When the NVM self-programming signature is written, CCP[1] will read as one for four CPU instruction
cycles , other bits will read as zero and CCP[1] will be cleared automatically after four cycles. The
software should write data to flash high byte within this four clock cycles to execute self-programming.
Table 8-2. Signatures Recognized by the Configuration Change Protection Register
Signature
Group
Description
0xD8
IOREG: CLKMSR, CLKPSR, WDTCSR
Protected I/O register
0xE7
SPM
NVM self-programming enable
Note: Bit 0 and 1 have R/W access. The other bits only have W access.
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8.11.2.
Stack Pointer Register High byte
Name: SPH
Offset: 0x3E
Reset: RAMEND
Property:
Bit
7
6
5
4
3
2
1
0
RW
RW
RW
(SP[15:8]) SPH
Access
RW
RW
RW
RW
RW
Reset
Bits 7:0 – (SP[15:8]) SPH: Stack Pointer Register
SPH and SPL are combined into SP. It means SPH[7:0] is SP[15:8].
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8.11.3.
Stack Pointer Register Low byte
Name: SPL
Offset: 0x3D
Reset: RAMEND
Property:
Bit
7
6
5
4
3
2
1
0
RW
RW
RW
RW
(SP[7:0]) SPL
Access
RW
RW
RW
RW
Reset
Bits 7:0 – (SP[7:0]) SPL: Stack Pointer Register
SPH and SPL are combined into SP. It means SPL[7:0] is SP[7:0].
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8.11.4.
Status Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be
used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an
I/O address offset within 0x00 - 0x3F.
Name: SREG
Offset: 0x5F
Reset: 0x00
Property: When addressing as I/O Register: address offset is 0x3F
Bit
Access
Reset
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable Register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI
instructions, as described in the instruction set reference.
Bit 6 – T: Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for
the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and
a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in
BCD arithmetic. See the Instruction Set Description for detailed information.
Bit 4 – S: Sign Flag, S = N ㊉ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow
Flag V. See the Instruction Set Description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction Set
Description for detailed information.
Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set
Description for detailed information.
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Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description
for detailed information.
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9.
AVR Memories
9.1.
Overview
This section describes the different memory types in the device. The AVR architecture has two main
memory spaces, the Data Memory and the Program Memory space. All memory spaces are linear and
regular.
9.2.
Features
•
•
•
•
•
•
9.3.
Non-volatile Program and Data Memories
1024 Bytes of In-system Programmable Flash Program Memory
32 Bytes Internal SRAM
Flash Write/Erase Cycles: 10,000
Data Retention: 20 Years at 85°C / 100 Years at 25°C
Self-programming Flash on Full Operating Voltage Range (1.8 – 5.5V)
In-System Reprogrammable Flash Program Memory
The ATtiny102/ATtiny104 contains 1024 Bytes On-chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x 16.
The device Program Counter (PC) is 9 bits wide, thus addressing the 512 program memory locations,
starting at 0x000. Memory Programming contains a detailed description on Flash data serial downloading.
Constant tables can be allocated within the entire address space of program memory by using load/store
instructions. Since program memory can not be accessed directly, it has been mapped to the data
memory. The mapped program memory begins at byte address 0x4000 in data memory. Although
programs are executed starting from address 0x000 in program memory it must be addressed starting
from 0x4000 when accessed via the data memory.
Timing diagrams of instruction fetch and execution are presented in Instruction Execution Timing section.
Related Links
Instruction Execution Timing on page 20
MEMPROG- Memory Programming on page 193
9.4.
SRAM Data Memory
Data memory locations include the I/O memory, the internal SRAM memory, the Non-Volatile Memory
(NVM) Lock bits, and the Flash memory. The following figure shows how the ATtiny102/ATtiny104 SRAM
Memory is organized.
The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address
the internal data SRAM.
The Non-Volatile Memory (NVM) Lock bits and all the Flash memory sections are mapped to the data
memory space. These locations appear as read-only for device firmware.
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The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and
indirect with post-increment. In the register file, registers R26 to R31 function as pointer registers for
indirect addressing.
The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS
and STS instructions reaches the 128 locations between 0x0040 and 0x00BF.
The indirect addressing reaches the entire data memory space. When using indirect addressing modes
with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or
incremented.
Figure 9-1. Data Memory Map (Byte Addressing)
I/O SPACE
0x0000 ... 0x003F
SRAM DATA MEMORY
0x0040 ... 0x005F
(reserved)
0x0060 ... 0x3EFF
NVM LOCK BITS
0x3F00 ... 0x3F01
(reserved)
0x3F02 ... 0x3F3F
CONFIGURATION BITS
0x3F40 ... 0x3F41
(reserved)
0x3F42 ... 0x3F7F
CALIBRATION BITS
0x3F80 ... 0x3F81
(reserved)
0x3F82 ... 0x3FBF
DEVICE ID BITS
0x3FC0 ... 0x3FC3
(reserved)
0x3FC4 ... 0x3FFF
FLASH PROGRAM MEMORY
(reserved)
9.4.1.
0x4000 ... 0x41FF/0x43FF
0x4400 ... 0xFFFF
Data Memory Access Times
The internal data SRAM access is performed in two clkCPU cycles as described in the following Figure.
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Figure 9-2. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address
Compute Address
Address valid
Write
Data
WR
Read
Data
RD
Memory Access Instruction
9.5.
Next Instruction
I/O Memory
The I/O space definition of the device is shown in the Register Summary.
All ATtiny102/ATtiny104 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD and ST instructions, transferring data between the 16 general purpose working
registers and the I/O space. I/O Registers within the address range 0x00-0x1F are directly bit-accessible
using the SBI and CBI instructions, except USART registers. In these registers, the value of single bits
can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set Summary section
for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O
memory addresses should never be written.
Some of the Status Flags are cleared by writing a '1' to them; this is described in the flag descriptions.
Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and
can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with
registers 0x00-0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
Related Links
Register Summary on page 252
Instruction Set Summary on page 254
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10.
Clock System
10.1.
Overview
This chapter summarizes the clock distribution and terminology in the ATtiny102/ATtiny104 device.
10.2.
Clock Distribution
All the clocks need not be active at a given time. In order to reduce power consumption, the clocks to
modules not being used can be halted by using different sleep modes, as described in the section on
Power Management and Sleep Modes. The clock systems are detailed below.
Figure 10-1. Clock Distribution
ANALOG-TO-DIGITAL
CONVERTER
clk ADC
GENERAL
I/O MODULES
CPU
CORE
clk I/O
NVM
RAM
clk NVM
clk CPU
CLOCK CONTROL UNIT
SOURCE CLOCK
RESET
LOGIC
WATCHDOG
CLOCK
CLOCK
PRESCALER
WATCHDOG
TIMER
CLOCK
SWITCH
EXTERNAL
CLOCK
WATCHDOG
OSCILLATOR
CALIBRATED
OSCILLATOR
Related Links
Power Management and Sleep Modes on page 40
10.3.
Clock Subsystems
10.3.1.
CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of
such modules are the General Purpose Register File, the System Registers and the SRAM data memory.
Halting the CPU clock inhibits the core from performing general operations and calculations.
10.3.2.
I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by
the External Interrupt module, but note that some external interrupts are detected by asynchronous logic,
allowing such interrupts to be detected even if the I/O clock is halted.
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10.3.3.
NVM Clock – clkNVM
The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usually active
simultaneously with the CPU clock.
10.3.4.
ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order
to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
10.4.
Clock Sources
The device has the following clock source options, selectable by Clock Main Select Bits in Clock Main
Settings Register (CLKMSR.CLKMS). All synchronous clock signals are derived from the main clock. The
three alternative sources for the main clock are as follows:
•
Calibrated Internal 8MHz Oscillator
•
External Clock
•
Internal 128kHz Oscillator.
Refer to description of Clock Main Select Bits in Clock Main Settings Register (CLKMSR.CLKMS) for how
to select and change the active clock source.
10.4.1.
Calibrated Internal 8MHz Oscillator
The calibrated internal oscillator provides an approximately 8MHz clock signal. Though voltage and
temperature dependent, this clock can be very accurately calibrated by the user.
During reset, hardware loads the calibration byte into the Oscillator Calibration Register (OSCCAL)
register and thereby automatically calibrates the oscillator. The accuracy of this calibration is shown as
Factory calibration in Accuracy of Calibrated Internal Oscillator of Electrical Characteristics chapter.
When this oscillator is used as the main clock, the watchdog oscillator will still be used for the watchdog
timer and reset time-out. For more information on the pre-programmed calibration value, see section
Calibration Section.
It is possible to reach higher accuracies than factory defaults, especially when the application allows
temperature and voltage ranges to be narrowed. The firmware can reprogram the calibration data in
OSCCAL either at start-up or during run-time. The continuous, run-time calibration method allows
firmware to monitor voltage and temperature and compensate for any detected variations.
When this oscillator is used as the chip clock, it will still be used for the Watchdog Timer and for the Reset
Time-out.
Related Links
Calibration Section on page 199
Accuracy of Calibrated Internal Oscillator on page 221
Internal Oscillator Speed on page 244
10.4.2.
External Clock
To drive the device from an external clock source, CLKI should be driven as shown in the Figure below.
To run the device on an external clock, the CLKMSR.CLKMS must be programmed to '0b10'.
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Table 10-1. External Clock Frequency
Frequency
CLKMSR.CLKMS
0 - 12MHz
0b10
Figure 10-2. External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
EXTCLK
GND
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to
ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the
next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during the
changes.
10.4.3.
Internal 128kHz Oscillator
The internal 128kHz oscillator is a low power oscillator providing a clock of 128kHz. The frequency
depends on supply voltage, temperature and batch variations. This clock may be select as the main clock
by setting the CLKMSR.CLKMS to 0b01.
10.4.4.
Switching Clock Source
The main clock source can be switched at run-time using the CLKMSR – Clock Main Settings Register.
When switching between any clock sources, the clock system ensures that no glitch occurs in the main
clock.
10.4.5.
Default Clock Source
The calibrated internal 8MHz oscillator is always selected as main clock when the device is powered up
or has been reset. The synchronous system clock is the main clock divided by 8, controlled by the
System Clock Prescaler. The Clock Prescaler Select Bits in Clock Prescale Register (CLKPSR.CLKPS)
can be written later to change the system clock frequency. See section “System Clock Prescaler”.
10.5.
System Clock Prescaler
The system clock is derived from the main clock via the System Clock Prescaler. The system clock can
be divided by setting the “CLKPSR – Clock Prescale Register”. The system clock prescaler can be used
to decrease power consumption at times when requirements for processing power is low or to bring the
system clock within limits of maximum frequency. The prescaler can be used with all main clock source
options, and it will affect the clock frequency of the CPU and all synchronous peripherals.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency
while still ensuring stable operation.
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10.5.1.
Switching Prescaler Setting
When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in
the system clock and that no intermediate frequency is higher than neither the clock frequency
corresponding the previous setting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be
faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler even if it were readable, and the exact time it takes to switch from one clock division to another cannot be
exactly predicted.
From the time the CLKPSR.CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.
10.6.
Starting
10.6.1.
Starting from Reset
The internal reset is immediately asserted when a reset source goes active. The internal reset is kept
asserted until the reset source is released and the start-up sequence is completed. The start-up
sequence includes three steps, as follows.
1. The first step after the reset source has been released consists of the device counting the reset
start-up time. The purpose of this reset start-up time is to ensure that supply voltage has reached
sufficient levels. The reset start-up time is counted using the internal 128kHz oscillator.
Note: The actual supply voltage is not monitored by the start-up logic. The device will count until
the reset start-up time has elapsed even if the device has reached sufficient supply voltage levels
earlier.
2. The second step is to count the oscillator start-up time, which ensures that the calibrated internal
oscillator has reached a stable state before it is used by the other parts of the system. The
calibrated internal oscillator needs to oscillate for a minimum number of cycles before it can be
considered stable.
3. The last step before releasing the internal reset is to load the calibration and the configuration
values from the Non-Volatile Memory to configure the device properly. The configuration time is
listed in the next table.
There are two start-up time options which will be supported :
•
Normal start-up time: 64ms
•
Fast start-up time: 8ms
Table 10-2. Start-up Times when Using the Internal Calibrated Oscillator with Normal start-up time
Reset
Oscillator
Configuration
Total start-up time
64ms
6cycles
21cycles
64ms + 6 oscillator cycles + 21 system clock cycles (1)
Table 10-3. Start-up Times when Using the Internal Calibrated Oscillator with shorter startup time
Reset
Oscillator
Configuration
Total start-up time
8ms
6cycles
21cycles
8 ms + 6 oscillator cycles + 21 system clock cycles (1)
Note:
1. After powering up the device or after a reset the system clock is automatically set to calibrated
internal 8MHz oscillator, divided by 8
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10.6.2.
Starting from Power-Down Mode
When waking up from Power-Down sleep mode, the supply voltage is assumed to be at a sufficient level
and only the oscillator start-up time is counted to ensure the stable operation of the oscillator. The
oscillator start-up time is counted on the selected main clock, and the start-up time depends on the clock
selected.
Table 10-4. Start-up Time from Power-Down Sleep Mode.
Oscillator start-up time
Total start-up time
6 cycles
6 oscillator cycles (1)
Note: 1. The start-up time is measured in main clock oscillator cycles.
10.6.3.
Starting from Idle / ADC Noise Reduction / Standby Mode
When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and
no oscillator start-up time is introduced.
10.7.
Register Description
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10.7.1.
Clock Main Settings Register
Name: CLKMSR
Offset: 0x37
Reset: 0x00
Property:
Bit
7
6
5
4
3
2
1
0
CLKMS[1:0]
Access
Reset
R/W
R/W
0
0
Bits 1:0 – CLKMS[1:0]: Clock Main Select Bits
These bits select the main clock source of the system. The bits can be written at run-time to switch the
source of the main clock. The clock system ensures glitch free switching of the main clock source.
Table 10-5. Selection of Main Clock
CLKM
Main Clock Source
00
Calibrated Internal 8MHz Oscillator
01
Internal 128kHz Oscillator (WDT Oscillator)
10
External clock
11
Reserved
To avoid unintentional switching of main clock source, a protected change sequence must be followed to
change the CLKMS bits, as follows:
1. Write the signature for change enable of protected I/O register to register CCP.
2. Within four instruction cycles, write the CLKMS bits with the desired value.
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10.7.2.
Oscillator Calibration Register
Name: OSCCAL
Offset: 0x39
Reset: xxxxxxxx
Property:
Bit
7
6
5
4
3
2
1
0
CAL[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process
variations from the oscillator frequency. A pre-programmed calibration value is automatically written to
this register during chip reset, giving the Factory calibrated frequency as specified in Accuracy of
Calibrated Internal Oscillator section of Electrical Characteristics chapter.
The application software can write this register to change the oscillator frequency. The oscillator can be
calibrated to frequencies as specified in Accuracy of Calibrated Internal Oscillator section of Electrical
Characteristics chapter. Calibration outside that range is not guaranteed.
The lowest oscillator frequency is reached by programming these bits to zero. Increasing the register
value increases the oscillator frequency.
Note that this oscillator is used to time Flash write accesses, and write times will be affected accordingly.
Do not calibrate to more than 8.8MHz if Flash is to be written. Otherwise, the Flash write may fail.
To ensure stable operation of the MCU the calibration value should be changed in small steps. A step
change in frequency of more than 2% from one cycle to the next can lead to unpredictable behavior. Also,
the difference between two consecutive register values should not exceed 0x20. If these limits are
exceeded the MCU must be kept in reset during changes to clock frequency.
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10.7.3.
Clock Prescaler Register
Name: CLKPSR
Offset: 0x36
Reset: 0x00000011
Property:
Bit
7
6
5
4
3
2
1
0
CLKPS[3:0]
Access
Reset
R/W
R/W
R/W
R/W
0
0
1
1
Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select
These bits define the division factor between the selected clock source and the internal system clock.
These bits can be written run-time to vary the clock frequency to suit the application requirements. As the
divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced
when a division factor is used. The division factors are given in the table below.
Table 10-6. Clock Prescaler Select
CLKPS[3:0]
Clock Division Factor
0000
1
0001
2
0010
4
0011
8 (default)
0100
16
0101
32
0110
64
0111
128
1000
256
1001
Reserved
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to
change the CLKPS bits:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
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At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock
source has a frequency higher than the maximum allowed the application software must make sure a
sufficient division factor is used. To make sure the write procedure is not interrupted, interrupts must be
disabled when changing prescaler settings.
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11.
Power Management and Sleep Modes
11.1.
Overview
The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal
choise for low power applications. In addition, sleep modes enable the application to shut down unused
modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to
tailor the power consumption to the application’s requirements.
11.2.
Features
•
•
11.3.
Minimizing Power Consumption
Sleep modes:
– Idle
– ADC Noise Reduction Mode
– Power-Down Mode
– Standby Mode
Sleep Modes
The following Table shows the different sleep modes and their wake up
Table 11-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Oscillators
Active Clock Domains
Wake-up Sources
Sleep Mode clkCPU clkNVM clkIO clkADC Main Clock
INT0 and Pin
Source Enabled Change
ADC Other I/O Watchdog
Interrupt
VLM Interrupt
Idle
Yes
Yes
Yes
Yes
Yes
ADC Noise
Reduction
Standby
Yes
Yes
Yes
Yes
Yes
Yes
Yes(1)
Yes
Yes
Yes(1)
Yes
Yes(1)
Yes
Power-down
Yes
Note:
1. For INT0, only level interrupt.
To enter any of the four sleep modes (Idle, ADC Noise Reduction, Power-down or Standby), the Sleep
Enable bit in the Sleep Mode Control Register (SMCR.SE) must be written to '1' and a SLEEP instruction
must be executed. Sleep Mode Select bits (SMCR.SM) select which sleep mode will be activated by the
SLEEP instruction.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then
halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes
execution from the instruction following SLEEP. The contents of the Register File and SRAM are
unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up
and executes from the Reset Vector.
Note: If a level triggered interrupt is used for wake-up the changed level must be held for some time to
wake up the MCU (and for the MCU to enter the interrupt service routine). See External Interrupts for
details.
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Related Links
SMCR on page 44
Interrupts on page 56
11.3.1.
Idle Mode
When the SMCR.SM is written to '0x000', the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the Analog Comparator, Timer/Counters, Watchdog, and the interrupt
system to continue operating. This sleep mode basically halts clkCPU and clkNVM, while allowing the other
clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the
timer overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register
(ACSR.ACD). This will reduce power consumption in Idle mode. If the ADC is enabled , a conversion
starts automatically when this mode is entered.
Related Links
ACSRA on page 168
11.3.2.
ADC Noise Reduction Mode
When the SMCR.SM is written to '0x001', the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts and the Watchdog to
continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkNVM, while allowing
the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC
is enabled, a conversion starts automatically when this mode is entered.
This mode is available in all devices equipped with an ADC.
11.3.3.
Power-Down Mode
When the SMCR.SM is written to '0x010', the SLEEP instruction makes the MCU enter Power-Down
mode. In this mode, the external Oscillator is stopped, while the external interrupts and the Watchdog
continue operating (if enabled).
Only an these events can wake up the MCU:
•
Watchdog System Reset
•
External level interrupt on INT0
•
Pin change interrupt
This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
11.3.4.
Standby Mode
When the SMCR.SM is written to '0x100', the SLEEP instruction makes the MCU enter Standby mode.
This mode is identical to Power-Down with the exception that the Oscillator is kept running. This reduces
wake-up time, because the oscillator is already running and doesn't need to be started up.
11.4.
Power Reduction Register
The Power Reduction Register (PRR) provides a method to stop the clock to individual peripherals to
reduce power consumption. When the clock for a peripheral is stopped then:
•
The current state of the peripheral is frozen.
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•
•
The associated registers can not be read or written.
Resources used by the peripheral will remain occupied.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes
up the peripheral and puts it in the same state as before shutdown.
Peripheral module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
Related Links
PRR on page 45
Supply Current of I/O Modules on page 230
11.5.
Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep mode
should be selected so that as few as possible of the device’s functions are operating. All functions not
needed should be disabled. In particular, the following modules may need special consideration when
trying to achieve the lowest possible power consumption.
11.5.1.
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. In the power-down
mode, the analog comparator is automatically disabled. See Analog Comparator for further details.
When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. However, if the
Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator
should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,
independent of sleep mode.
Related Links
AC - Analog Comparator on page 166
11.5.2.
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled
before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an
extended conversion.
Related Links
ADC - Analog to Digital Converter on page 172
11.5.3.
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Analog Comparator or the ADC. If
these modules are disabled as described in the sections above, the internal voltage reference will be
disabled and it will not be consuming power. When turned on again, the user must allow the reference to
start up before the output is used. If the reference is kept on in sleep mode, the output can be used
immediately.
11.5.4.
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog
Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
Related Links
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Watchdog Timer on page 49
11.5.5.
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most
important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock
(clkI/O) is stopped, the input buffers of the device will be disabled. This ensures that no power is
consumed by the input logic when not needed. In some cases, the input logic is needed for detecting
wake-up conditions, and it will then be enabled. Refer to the section Digital Input Enable and Sleep
Modes for details on which pins are enabled. If the input buffer is enabled and the input signal is left
floating or have an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close
to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be
disabled by writing to the Digital Input Disable Registers 0 (DIDR0).
Related Links
Digital Input Enable and Sleep Modes on page 70
DIDR0 on page 171
11.6.
Register Description
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11.6.1.
Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Name: SMCR
Offset: 0x3A
Reset: 0x00
Property:
Bit
7
6
5
4
3
2
1
SM[2:0]
Access
Reset
0
SE
R/W
R/W
R/W
R/W
0
0
0
0
Bits 3:1 – SM[2:0]: Sleep Mode Select
The SM[2:0] bits select between the five available sleep modes.
Table 11-2. Sleep Mode Select
SM[2:0]
Sleep Mode
000
Idle
001
ADC Noise Reduction
010
Power-down
011
Reserved
100
Standby
101
Reserved
110
Reserved
111
Reserved
Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose,
it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP
instruction and to clear it immediately after waking up.
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11.6.2.
Power Reduction Register
Name: PRR
Offset: 0x35
Reset: 0x00
Property:
Bit
Access
Reset
7
6
5
4
3
2
1
0
PRUSART0
PRADC
PRTIM0
R/W
R/W
R/W
0
0
0
Bit 2 – PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When waking
up the USART again, the USART should be re initialized to ensure proper operation.
Bit 1 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The
analog comparator cannot use the ADC input MUX when the ADC is shut down.
Bit 0 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is
enabled, operation will continue like before the shutdown.
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12.
SCRST - System Control and Reset
12.1.
Overview
The reset logic manages the reset of the microcontroller. It issues a microcontroller reset, sets the device
to its initial state and allows the reset source to be identified by software.
Features
•
•
Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution from the
Reset Vector. The instruction placed at the Reset Vector must be an Relative Jump instruction (RJMP) to
the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not
used, and regular program code can be placed at these locations. The circuit diagram in the next shows
the reset logic. Electrical parameters of the reset circuitry are defined in section System and Reset
Characteristics.
Figure 12-1. Reset Logic
DATA BUS
Power-on Reset
Circuit
WDRF
Reset Flag Register
(RSTFLR)
VLM
EXTRF
12.3.
Reset The Microcontroller to Initial State.
Multiple Reset Sources:
– Power-on Reset
– VCC Level Monitoring (VLM) Reset
– External Reset
– Watchdog System Reset
PORF
12.2.
Pull-up Resistor
SPIKE
FILTER
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This
does not require any clock source to be running.
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After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This
allows the power to reach a stable level before normal operation starts.
Related Links
Starting from Reset on page 34
System and Reset Characteristics on page 222
12.4.
Reset Sources
The device has four sources of reset:
•
•
•
•
12.4.1.
Power-on Reset. The MCU is reset when the supply voltage is less than the Power-on Reset
threshold (VPOT).
VLM (VCC Level Monitoring) Reset. The MCU is reset when voltage on the VCC pin is below the
selected trigger level.
External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the
minimum pulse length.
Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the
Watchdog System Reset mode is enabled.
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The POR is activated
whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on
Reset threshold voltage invokes the delay counter, which determines how long the device is kept in Reset
after VCC rise. The Reset signal is activated again, without any delay, when VCC decreases below the
detection level.
Figure 12-2. MCU Start-up, RESET Tied to VCC
VCC
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
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Figure 12-3. MCU Start-up, RESET Extended Externally
VCC
VPOT
RESET
TIME-OUT
VRST
tTOUT
INTERNAL
RESET
Related Links
System and Reset Characteristics on page 222
12.4.2.
VCC Level Monitoring
ATtiny102/ATtiny104 have a VCC Level Monitoring (VLM) circuit that compares the voltage level at the
VCC pin against fixed trigger levels. The trigger levels are set with VLM[2:0] bits, see VLMCSR – VCC
Level Monitoring Control and Status register.
The VLM circuit provides a status flag, VLMF, that indicates if voltage on the VCC pin is below the
selected trigger level. The flag can be read from VLMCSR, but it is also possible to have an interrupt
generated when the VLMF status flag is set. This interrupt is enabled by the VLMIE bit in the VLMCSR
register. The flag can be cleared by changing the trigger level or by writing it to zero. The flag is
automatically cleared when the voltage at VCC rises back above the selected trigger level.
The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the Power-On
Reset (POR) does not activate before supply voltage has dropped to a level where the MCU is not
necessarily functional any more. With VLM, it is possible to generate a reset earlier.
When active, the VLM circuit consumes some power, as illustrated in the figure of VCC Level Monitor
Current vs. VCC in Typical Characteristics. To save power the VLM circuit can be turned off completely, or
it can be switched on and off at regular intervals. However, detection takes some time and it is therefore
recommended to leave the circuitry on long enough for signals to settle. See VCC Level Monitor.
When VLM is active and voltage at VCC is above the selected trigger level operation will be as normal and
the VLM can be shut down for a short period of time. If voltage at VCC drops below the selected threshold
the VLM will either flag an interrupt or generate a reset, depending on the configuration.
When the VLM has been configured to generate a reset at low supply voltage it will keep the device in
reset as long as VCC is below the reset level. If supply voltage rises above the reset level the condition is
removed and the MCU will come out of reset, and initiate the power-up start-up sequence.
If supply voltage drops enough to trigger the POR then PORF is set after supply voltage has been
restored.
Related Links
VLMCSR on page 54
Electrical Characteristics on page 218
VCC Level Monitor on page 223
Typical Characteristics on page 226
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12.4.3.
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum
pulse width will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive
edge, the delay counter starts the MCU after the Time-out period (tTOUT ) has expired. The External Reset
can be disabled by the RSTDISBL fuse.
Figure 12-4. External Reset During Operation
CC
Related Links
System and Reset Characteristics on page 222
12.4.4.
Watchdog System Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling
edge of this pulse, the delay timer starts counting the Time-out period tTOUT.
Figure 12-5. Watchdog System Reset During Operation
CC
CK
12.5.
Watchdog Timer
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog
timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
Refer to Watchdog System Reset for details on how to configure the watchdog timer.
12.5.1.
Overview
The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128kHz, as the next figure. By
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted. The Watchdog
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Reset (WDR) instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is
disabled and when a device reset occurs. Ten different clock cycle periods can be selected to determine
the reset period. If the reset period expires without another Watchdog Reset, the device resets and
executes from the Reset Vector.
Figure 12-6. Watchdog Timer
WDP0
WDP1
WDP2
WDP3
OSC/512K
OSC/1024K
OSC/256K
OSC/128K
OSC/32K
OSC/64K
OSC/8K
OSC/2K
OSC/4K
WATCHDOG
RESET
OSC/16K
WATCHDOG
PRESCALER
128 kHz
OSCILLATOR
MUX
WDE
MCU RESET
The Watchdog Timer can also be configured to generate an interrupt instead of a reset. This can be very
helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two
different safety levels are selected by the fuse WDTON. See Procedure for Changing the Watchdog Timer
Configuration for details.
Table 12-1. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
12.5.2.
Safety Level WDT Initial
State
How to Disable the
WDT
How to Change Timeout
Unprogrammed 1
Disabled
Protected change
sequence
No limitations
Programmed
Enabled
Always enabled
Protected change
sequence
2
Procedure for Changing the Watchdog Timer Configuration
The sequence for changing configuration differs between the two safety levels, as follows:
12.5.2.1. Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one
without any restriction. A special sequence is needed when disabling an enabled Watchdog Timer. To
disable an enabled Watchdog Timer, the following procedure must be followed:
1. Write the signature for change enable of protected I/O registers to register CCP
2. Within four instruction cycles, in the same operation, write WDE and WDP bits
12.5.2.2. Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
protected change is needed when changing the Watchdog Time-out period. To change the Watchdog
Time-out, the following procedure must be followed:
Atmel ATtiny102 / ATtiny104 [DATASHEET]
Atmel-42505C-ATtiny102 / ATtiny104_Datasheet_Complete-07/2016
50
1.
2.
12.5.3.
Write the signature for change enable of protected I/O registers to register CCP
Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant
Code Examples
The following code example shows how to turn off the WDT. The example assumes that interrupts are
controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these
functions.
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in r16, RSTFLR
andi r16, ~(1
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